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KVM: x86: Preserve injected TF across emulation
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
e495606d 31#include <asm/desc.h>
6aa8b732 32
63d1142f 33#include <asm/virtext.h>
229456fc 34#include "trace.h"
63d1142f 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
41#define IOPM_ALLOC_ORDER 2
42#define MSRPM_ALLOC_ORDER 1
43
6aa8b732
AK		 44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
80b7706e
JR		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 49#define SVM_FEATURE_SVML (1 << 2)
66b7138f 50#define SVM_FEATURE_NRIP (1 << 3)
565d0998 51#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 52
410e4d57
JR		 53#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
56
24e09cbf
JR		 57#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58
6c8166a7
AK		 59static const u32 host_save_user_msrs[] = {
60#ifdef CONFIG_X86_64
61 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_FS_BASE,
63#endif
64 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65};
66
67#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
68
69struct kvm_vcpu;
70
e6aa9abd
JR		 71struct nested_state {
72 struct vmcb *hsave;
73 u64 hsave_msr;
74 u64 vmcb;
75
76 /* These are the merged vectors */
77 u32 *msrpm;
78
79 /* gpa pointers to the real vectors */
80 u64 vmcb_msrpm;
aad42c64 81
cd3ff653
JR		 82 /* A VMEXIT is required but not yet emulated */
83 bool exit_required;
84
aad42c64
JR		 85 /* cache for intercepts of the guest */
86 u16 intercept_cr_read;
87 u16 intercept_cr_write;
88 u16 intercept_dr_read;
89 u16 intercept_dr_write;
90 u32 intercept_exceptions;
91 u64 intercept;
92
e6aa9abd
JR		 93};
94
6c8166a7
AK		 95struct vcpu_svm {
96 struct kvm_vcpu vcpu;
97 struct vmcb *vmcb;
98 unsigned long vmcb_pa;
99 struct svm_cpu_data *svm_data;
100 uint64_t asid_generation;
101 uint64_t sysenter_esp;
102 uint64_t sysenter_eip;
103
104 u64 next_rip;
105
106 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
107 u64 host_gs_base;
6c8166a7
AK		 108
109 u32 *msrpm;
6c8166a7 110
e6aa9abd 111 struct nested_state nested;
6be7d306
JK		 112
113 bool nmi_singlestep;
66b7138f
JK		 114
115 unsigned int3_injected;
116 unsigned long int3_rip;
6c8166a7
AK		 117};
118
709ddebf
JR		 119/* enable NPT for AMD64 and X86 with PAE */
120#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
121static bool npt_enabled = true;
122#else
e3da3acd 123static bool npt_enabled = false;
709ddebf 124#endif
6c7dac72
JR		 125static int npt = 1;
126
127module_param(npt, int, S_IRUGO);
e3da3acd 128
4b6e4dca 129static int nested = 1;
236de055
AG		 130module_param(nested, int, S_IRUGO);
131
44874f84 132static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 133static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 134
410e4d57 135static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 136static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 137static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 138static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
139 bool has_error_code, u32 error_code);
140
a2fa3e9f
GH		 141static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
142{
fb3f0f51 143 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 144}
145
3d6368ef
AG		 146static inline bool is_nested(struct vcpu_svm *svm)
147{
e6aa9abd 148 return svm->nested.vmcb;
3d6368ef
AG		 149}
150
2af9194d
JR		 151static inline void enable_gif(struct vcpu_svm *svm)
152{
153 svm->vcpu.arch.hflags |= HF_GIF_MASK;
154}
155
156static inline void disable_gif(struct vcpu_svm *svm)
157{
158 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
159}
160
161static inline bool gif_set(struct vcpu_svm *svm)
162{
163 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
164}
165
4866d5e3 166static unsigned long iopm_base;
6aa8b732
AK		 167
168struct kvm_ldttss_desc {
169 u16 limit0;
170 u16 base0;
171 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
172 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
173 u32 base3;
174 u32 zero1;
175} __attribute__((packed));
176
177struct svm_cpu_data {
178 int cpu;
179
5008fdf5
AK		 180 u64 asid_generation;
181 u32 max_asid;
182 u32 next_asid;
6aa8b732
AK		 183 struct kvm_ldttss_desc *tss_desc;
184
185 struct page *save_area;
186};
187
188static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 189static uint32_t svm_features;
6aa8b732
AK		 190
191struct svm_init_data {
192 int cpu;
193 int r;
194};
195
196static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
197
9d8f549d 198#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 199#define MSRS_RANGE_SIZE 2048
200#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
201
202#define MAX_INST_SIZE 15
203
80b7706e
JR		 204static inline u32 svm_has(u32 feat)
205{
206 return svm_features & feat;
207}
208
6aa8b732
AK		 209static inline void clgi(void)
210{
4ecac3fd 211 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 212}
213
214static inline void stgi(void)
215{
4ecac3fd 216 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 217}
218
219static inline void invlpga(unsigned long addr, u32 asid)
220{
4ecac3fd 221 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 222}
223
6aa8b732
AK		 224static inline void force_new_asid(struct kvm_vcpu *vcpu)
225{
a2fa3e9f 226 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 227}
228
229static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
230{
231 force_new_asid(vcpu);
232}
233
234static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
235{
709ddebf 236 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 237 efer &= ~EFER_LME;
6aa8b732 238
9962d032 239 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 240 vcpu->arch.efer = efer;
6aa8b732
AK		 241}
242
6aa8b732
AK		 243static int is_external_interrupt(u32 info)
244{
245 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
246 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
247}
248
2809f5d2
GC		 249static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
250{
251 struct vcpu_svm *svm = to_svm(vcpu);
252 u32 ret = 0;
253
254 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 255 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 256 return ret & mask;
257}
258
259static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
260{
261 struct vcpu_svm *svm = to_svm(vcpu);
262
263 if (mask == 0)
264 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
265 else
266 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
267
268}
269
6aa8b732
AK		 270static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
271{
a2fa3e9f
GH		 272 struct vcpu_svm *svm = to_svm(vcpu);
273
274 if (!svm->next_rip) {
851ba692 275 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 276 EMULATE_DONE)
277 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 278 return;
279 }
5fdbf976
MT		 280 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
281 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
282 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 283
5fdbf976 284 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 285 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 286}
287
116a4752
JK		 288static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
289 bool has_error_code, u32 error_code)
290{
291 struct vcpu_svm *svm = to_svm(vcpu);
292
293 /* If we are within a nested VM we'd better #VMEXIT and let the
294 guest handle the exception */
295 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
296 return;
297
66b7138f
JK		 298 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
299 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
300
301 /*
302 * For guest debugging where we have to reinject #BP if some
303 * INT3 is guest-owned:
304 * Emulate nRIP by moving RIP forward. Will fail if injection
305 * raises a fault that is not intercepted. Still better than
306 * failing in all cases.
307 */
308 skip_emulated_instruction(&svm->vcpu);
309 rip = kvm_rip_read(&svm->vcpu);
310 svm->int3_rip = rip + svm->vmcb->save.cs.base;
311 svm->int3_injected = rip - old_rip;
312 }
313
116a4752
JK		 314 svm->vmcb->control.event_inj = nr
315 | SVM_EVTINJ_VALID
316 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
317 | SVM_EVTINJ_TYPE_EXEPT;
318 svm->vmcb->control.event_inj_err = error_code;
319}
320
6aa8b732
AK		 321static int has_svm(void)
322{
63d1142f 323 const char *msg;
6aa8b732 324
63d1142f 325 if (!cpu_has_svm(&msg)) {
ff81ff10 326 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 327 return 0;
328 }
329
6aa8b732
AK		 330 return 1;
331}
332
333static void svm_hardware_disable(void *garbage)
334{
2c8dceeb 335 cpu_svm_disable();
6aa8b732
AK		 336}
337
10474ae8 338static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 339{
340
0fe1e009 341 struct svm_cpu_data *sd;
6aa8b732 342 uint64_t efer;
89a27f4d 343 struct desc_ptr gdt_descr;
6aa8b732
AK		 344 struct desc_struct *gdt;
345 int me = raw_smp_processor_id();
346
10474ae8
AG		 347 rdmsrl(MSR_EFER, efer);
348 if (efer & EFER_SVME)
349 return -EBUSY;
350
6aa8b732 351 if (!has_svm()) {
e6732a5a
ZA		 352 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
353 me);
10474ae8 354 return -EINVAL;
6aa8b732 355 }
0fe1e009 356 sd = per_cpu(svm_data, me);
6aa8b732 357
0fe1e009 358 if (!sd) {
e6732a5a 359 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 360 me);
10474ae8 361 return -EINVAL;
6aa8b732
AK		 362 }
363
0fe1e009
TH		 364 sd->asid_generation = 1;
365 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
366 sd->next_asid = sd->max_asid + 1;
6aa8b732 367
b792c344 368 kvm_get_gdt(&gdt_descr);
89a27f4d 369 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 370 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 371
9962d032 372 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 373
d0316554 374 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 375
376 return 0;
6aa8b732
AK		 377}
378
0da1db75
JR		 379static void svm_cpu_uninit(int cpu)
380{
0fe1e009 381 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 382
0fe1e009 383 if (!sd)
0da1db75
JR		 384 return;
385
386 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 387 __free_page(sd->save_area);
388 kfree(sd);
0da1db75
JR		 389}
390
6aa8b732
AK		 391static int svm_cpu_init(int cpu)
392{
0fe1e009 393 struct svm_cpu_data *sd;
6aa8b732
AK		 394 int r;
395
0fe1e009
TH		 396 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
397 if (!sd)
6aa8b732 398 return -ENOMEM;
0fe1e009
TH		 399 sd->cpu = cpu;
400 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 401 r = -ENOMEM;
0fe1e009 402 if (!sd->save_area)
6aa8b732
AK		 403 goto err_1;
404
0fe1e009 405 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 406
407 return 0;
408
409err_1:
0fe1e009 410 kfree(sd);
6aa8b732
AK		 411 return r;
412
413}
414
bfc733a7
RR		 415static void set_msr_interception(u32 *msrpm, unsigned msr,
416 int read, int write)
6aa8b732
AK		 417{
418 int i;
419
420 for (i = 0; i < NUM_MSR_MAPS; i++) {
421 if (msr >= msrpm_ranges[i] &&
422 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
423 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
424 msrpm_ranges[i]) * 2;
425
426 u32 *base = msrpm + (msr_offset / 32);
427 u32 msr_shift = msr_offset % 32;
428 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
429 *base = (*base & ~(0x3 << msr_shift)) |
430 (mask << msr_shift);
bfc733a7 431 return;
6aa8b732
AK		 432 }
433 }
bfc733a7 434 BUG();
6aa8b732
AK		 435}
436
f65c229c
JR		 437static void svm_vcpu_init_msrpm(u32 *msrpm)
438{
439 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
440
441#ifdef CONFIG_X86_64
442 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
443 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
444 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
445 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
446 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
447 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
448#endif
449 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
450 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 451}
452
24e09cbf
JR		 453static void svm_enable_lbrv(struct vcpu_svm *svm)
454{
455 u32 *msrpm = svm->msrpm;
456
457 svm->vmcb->control.lbr_ctl = 1;
458 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
459 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
460 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
461 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
462}
463
464static void svm_disable_lbrv(struct vcpu_svm *svm)
465{
466 u32 *msrpm = svm->msrpm;
467
468 svm->vmcb->control.lbr_ctl = 0;
469 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
470 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
471 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
472 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
473}
474
6aa8b732
AK		 475static __init int svm_hardware_setup(void)
476{
477 int cpu;
478 struct page *iopm_pages;
f65c229c 479 void *iopm_va;
6aa8b732
AK		 480 int r;
481
6aa8b732
AK		 482 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
483
484 if (!iopm_pages)
485 return -ENOMEM;
c8681339
AL		 486
487 iopm_va = page_address(iopm_pages);
488 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 489 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
490
50a37eb4
JR		 491 if (boot_cpu_has(X86_FEATURE_NX))
492 kvm_enable_efer_bits(EFER_NX);
493
1b2fd70c
AG		 494 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
495 kvm_enable_efer_bits(EFER_FFXSR);
496
236de055
AG		 497 if (nested) {
498 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
499 kvm_enable_efer_bits(EFER_SVME);
500 }
501
3230bb47 502 for_each_possible_cpu(cpu) {
6aa8b732
AK		 503 r = svm_cpu_init(cpu);
504 if (r)
f65c229c 505 goto err;
6aa8b732 506 }
33bd6a0b
JR		 507
508 svm_features = cpuid_edx(SVM_CPUID_FUNC);
509
e3da3acd
JR		 510 if (!svm_has(SVM_FEATURE_NPT))
511 npt_enabled = false;
512
6c7dac72
JR		 513 if (npt_enabled && !npt) {
514 printk(KERN_INFO "kvm: Nested Paging disabled\n");
515 npt_enabled = false;
516 }
517
18552672 518 if (npt_enabled) {
e3da3acd 519 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 520 kvm_enable_tdp();
5f4cb662
JR		 521 } else
522 kvm_disable_tdp();
e3da3acd 523
6aa8b732
AK		 524 return 0;
525
f65c229c 526err:
6aa8b732
AK		 527 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
528 iopm_base = 0;
529 return r;
530}
531
532static __exit void svm_hardware_unsetup(void)
533{
0da1db75
JR		 534 int cpu;
535
3230bb47 536 for_each_possible_cpu(cpu)
0da1db75
JR		 537 svm_cpu_uninit(cpu);
538
6aa8b732 539 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 540 iopm_base = 0;
6aa8b732
AK		 541}
542
543static void init_seg(struct vmcb_seg *seg)
544{
545 seg->selector = 0;
546 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
547 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
548 seg->limit = 0xffff;
549 seg->base = 0;
550}
551
552static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
553{
554 seg->selector = 0;
555 seg->attrib = SVM_SELECTOR_P_MASK | type;
556 seg->limit = 0xffff;
557 seg->base = 0;
558}
559
e6101a96 560static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 561{
e6101a96
JR		 562 struct vmcb_control_area *control = &svm->vmcb->control;
563 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 564
bff78274
AK		 565 svm->vcpu.fpu_active = 1;
566
6aa8b732
AK		 567 control->intercept_cr_read = INTERCEPT_CR0_MASK |
568 INTERCEPT_CR3_MASK |
649d6864 569 INTERCEPT_CR4_MASK;
6aa8b732
AK		 570
571 control->intercept_cr_write = INTERCEPT_CR0_MASK |
572 INTERCEPT_CR3_MASK |
80a8119c
AK		 573 INTERCEPT_CR4_MASK |
574 INTERCEPT_CR8_MASK;
6aa8b732
AK		 575
576 control->intercept_dr_read = INTERCEPT_DR0_MASK |
577 INTERCEPT_DR1_MASK |
578 INTERCEPT_DR2_MASK |
727f5a23
JK		 579 INTERCEPT_DR3_MASK |
580 INTERCEPT_DR4_MASK |
581 INTERCEPT_DR5_MASK |
582 INTERCEPT_DR6_MASK |
583 INTERCEPT_DR7_MASK;
6aa8b732
AK		 584
585 control->intercept_dr_write = INTERCEPT_DR0_MASK |
586 INTERCEPT_DR1_MASK |
587 INTERCEPT_DR2_MASK |
588 INTERCEPT_DR3_MASK |
727f5a23 589 INTERCEPT_DR4_MASK |
6aa8b732 590 INTERCEPT_DR5_MASK |
727f5a23 591 INTERCEPT_DR6_MASK |
6aa8b732
AK		 592 INTERCEPT_DR7_MASK;
593
7aa81cc0 594 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 595 (1 << UD_VECTOR) |
596 (1 << MC_VECTOR);
6aa8b732
AK		 597
598
599 control->intercept = (1ULL << INTERCEPT_INTR) |
600 (1ULL << INTERCEPT_NMI) |
0152527b 601 (1ULL << INTERCEPT_SMI) |
d225157b 602 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 603 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 604 (1ULL << INTERCEPT_INVD) |
6aa8b732 605 (1ULL << INTERCEPT_HLT) |
a7052897 606 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 607 (1ULL << INTERCEPT_INVLPGA) |
608 (1ULL << INTERCEPT_IOIO_PROT) |
609 (1ULL << INTERCEPT_MSR_PROT) |
610 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 611 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 612 (1ULL << INTERCEPT_VMRUN) |
613 (1ULL << INTERCEPT_VMMCALL) |
614 (1ULL << INTERCEPT_VMLOAD) |
615 (1ULL << INTERCEPT_VMSAVE) |
616 (1ULL << INTERCEPT_STGI) |
617 (1ULL << INTERCEPT_CLGI) |
916ce236 618 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 619 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 620 (1ULL << INTERCEPT_MONITOR) |
621 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 622
623 control->iopm_base_pa = iopm_base;
f65c229c 624 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 625 control->tsc_offset = 0;
6aa8b732
AK		 626 control->int_ctl = V_INTR_MASKING_MASK;
627
628 init_seg(&save->es);
629 init_seg(&save->ss);
630 init_seg(&save->ds);
631 init_seg(&save->fs);
632 init_seg(&save->gs);
633
634 save->cs.selector = 0xf000;
635 /* Executable/Readable Code Segment */
636 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
637 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
638 save->cs.limit = 0xffff;
d92899a0
AK		 639 /*
640 * cs.base should really be 0xffff0000, but vmx can't handle that, so
641 * be consistent with it.
642 *
643 * Replace when we have real mode working for vmx.
644 */
645 save->cs.base = 0xf0000;
6aa8b732
AK		 646
647 save->gdtr.limit = 0xffff;
648 save->idtr.limit = 0xffff;
649
650 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
651 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
652
9962d032 653 save->efer = EFER_SVME;
d77c26fc 654 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 655 save->dr7 = 0x400;
656 save->rflags = 2;
657 save->rip = 0x0000fff0;
5fdbf976 658 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 659
18fa000a
EH		 660 /* This is the guest-visible cr0 value.
661 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 662 */
18fa000a
EH		 663 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
664 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
665
66aee91a 666 save->cr4 = X86_CR4_PAE;
6aa8b732 667 /* rdx = ?? */
709ddebf
JR		 668
669 if (npt_enabled) {
670 /* Setup VMCB for Nested Paging */
671 control->nested_ctl = 1;
a7052897
MT		 672 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
673 (1ULL << INTERCEPT_INVLPG));
709ddebf 674 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 675 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
676 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 677 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 678 save->cr3 = 0;
679 save->cr4 = 0;
680 }
a79d2f18 681 force_new_asid(&svm->vcpu);
1371d904 682
e6aa9abd 683 svm->nested.vmcb = 0;
2af9194d
JR		 684 svm->vcpu.arch.hflags = 0;
685
565d0998
ML		 686 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
687 control->pause_filter_count = 3000;
688 control->intercept |= (1ULL << INTERCEPT_PAUSE);
689 }
690
2af9194d 691 enable_gif(svm);
6aa8b732
AK		 692}
693
e00c8cf2 694static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 695{
696 struct vcpu_svm *svm = to_svm(vcpu);
697
e6101a96 698 init_vmcb(svm);
70433389 699
c5af89b6 700 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 701 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 702 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
703 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 704 }
5fdbf976
MT		 705 vcpu->arch.regs_avail = ~0;
706 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 707
708 return 0;
04d2cc77
AK		 709}
710
fb3f0f51 711static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 712{
a2fa3e9f 713 struct vcpu_svm *svm;
6aa8b732 714 struct page *page;
f65c229c 715 struct page *msrpm_pages;
b286d5d8 716 struct page *hsave_page;
3d6368ef 717 struct page *nested_msrpm_pages;
fb3f0f51 718 int err;
6aa8b732 719
c16f862d 720 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 721 if (!svm) {
722 err = -ENOMEM;
723 goto out;
724 }
725
726 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
727 if (err)
728 goto free_svm;
729
b7af4043 730 err = -ENOMEM;
6aa8b732 731 page = alloc_page(GFP_KERNEL);
b7af4043 732 if (!page)
fb3f0f51 733 goto uninit;
6aa8b732 734
f65c229c
JR		 735 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
736 if (!msrpm_pages)
b7af4043 737 goto free_page1;
3d6368ef
AG		 738
739 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
740 if (!nested_msrpm_pages)
b7af4043 741 goto free_page2;
f65c229c 742
b286d5d8
AG		 743 hsave_page = alloc_page(GFP_KERNEL);
744 if (!hsave_page)
b7af4043
TY		 745 goto free_page3;
746
e6aa9abd 747 svm->nested.hsave = page_address(hsave_page);
b286d5d8 748
b7af4043
TY		 749 svm->msrpm = page_address(msrpm_pages);
750 svm_vcpu_init_msrpm(svm->msrpm);
751
e6aa9abd 752 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 753
a2fa3e9f
GH		 754 svm->vmcb = page_address(page);
755 clear_page(svm->vmcb);
756 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
757 svm->asid_generation = 0;
e6101a96 758 init_vmcb(svm);
a2fa3e9f 759
fb3f0f51 760 fx_init(&svm->vcpu);
ad312c7c 761 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 762 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 763 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 764
fb3f0f51 765 return &svm->vcpu;
36241b8c 766
b7af4043
TY		 767free_page3:
768 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
769free_page2:
770 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
771free_page1:
772 __free_page(page);
fb3f0f51
RR		 773uninit:
774 kvm_vcpu_uninit(&svm->vcpu);
775free_svm:
a4770347 776 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 777out:
778 return ERR_PTR(err);
6aa8b732
AK		 779}
780
781static void svm_free_vcpu(struct kvm_vcpu *vcpu)
782{
a2fa3e9f
GH		 783 struct vcpu_svm *svm = to_svm(vcpu);
784
fb3f0f51 785 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 786 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 787 __free_page(virt_to_page(svm->nested.hsave));
788 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 789 kvm_vcpu_uninit(vcpu);
a4770347 790 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 791}
792
15ad7146 793static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 794{
a2fa3e9f 795 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 796 int i;
0cc5064d 797
0cc5064d 798 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 799 u64 delta;
0cc5064d 800
953899b6
JR		 801 if (check_tsc_unstable()) {
802 /*
803 * Make sure that the guest sees a monotonically
804 * increasing TSC.
805 */
806 delta = vcpu->arch.host_tsc - native_read_tsc();
807 svm->vmcb->control.tsc_offset += delta;
808 if (is_nested(svm))
809 svm->nested.hsave->control.tsc_offset += delta;
810 }
0cc5064d 811 vcpu->cpu = cpu;
2f599714 812 kvm_migrate_timers(vcpu);
4b656b12 813 svm->asid_generation = 0;
0cc5064d 814 }
94dfbdb3
AL		 815
816 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 817 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 818}
819
820static void svm_vcpu_put(struct kvm_vcpu *vcpu)
821{
a2fa3e9f 822 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 823 int i;
824
e1beb1d3 825 ++vcpu->stat.host_state_reload;
94dfbdb3 826 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 827 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 828
e935d48e 829 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 830}
831
6aa8b732
AK		 832static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
833{
a2fa3e9f 834 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 835}
836
837static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
838{
a2fa3e9f 839 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 840}
841
6de4f3ad
AK		 842static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
843{
844 switch (reg) {
845 case VCPU_EXREG_PDPTR:
846 BUG_ON(!npt_enabled);
847 load_pdptrs(vcpu, vcpu->arch.cr3);
848 break;
849 default:
850 BUG();
851 }
852}
853
f0b85051
AG		 854static void svm_set_vintr(struct vcpu_svm *svm)
855{
856 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
857}
858
859static void svm_clear_vintr(struct vcpu_svm *svm)
860{
861 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
862}
863
6aa8b732
AK		 864static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
865{
a2fa3e9f 866 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 867
868 switch (seg) {
869 case VCPU_SREG_CS: return &save->cs;
870 case VCPU_SREG_DS: return &save->ds;
871 case VCPU_SREG_ES: return &save->es;
872 case VCPU_SREG_FS: return &save->fs;
873 case VCPU_SREG_GS: return &save->gs;
874 case VCPU_SREG_SS: return &save->ss;
875 case VCPU_SREG_TR: return &save->tr;
876 case VCPU_SREG_LDTR: return &save->ldtr;
877 }
878 BUG();
8b6d44c7 879 return NULL;
6aa8b732
AK		 880}
881
882static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
883{
884 struct vmcb_seg *s = svm_seg(vcpu, seg);
885
886 return s->base;
887}
888
889static void svm_get_segment(struct kvm_vcpu *vcpu,
890 struct kvm_segment *var, int seg)
891{
892 struct vmcb_seg *s = svm_seg(vcpu, seg);
893
894 var->base = s->base;
895 var->limit = s->limit;
896 var->selector = s->selector;
897 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
898 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
899 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
900 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
901 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
902 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
903 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
904 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 905
19bca6ab
AP		 906 /* AMD's VMCB does not have an explicit unusable field, so emulate it
907 * for cross vendor migration purposes by "not present"
908 */
909 var->unusable = !var->present || (var->type == 0);
910
1fbdc7a5
AP		 911 switch (seg) {
912 case VCPU_SREG_CS:
913 /*
914 * SVM always stores 0 for the 'G' bit in the CS selector in
915 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
916 * Intel's VMENTRY has a check on the 'G' bit.
917 */
25022acc 918 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 919 break;
920 case VCPU_SREG_TR:
921 /*
922 * Work around a bug where the busy flag in the tr selector
923 * isn't exposed
924 */
c0d09828 925 var->type |= 0x2;
1fbdc7a5
AP		 926 break;
927 case VCPU_SREG_DS:
928 case VCPU_SREG_ES:
929 case VCPU_SREG_FS:
930 case VCPU_SREG_GS:
931 /*
932 * The accessed bit must always be set in the segment
933 * descriptor cache, although it can be cleared in the
934 * descriptor, the cached bit always remains at 1. Since
935 * Intel has a check on this, set it here to support
936 * cross-vendor migration.
937 */
938 if (!var->unusable)
939 var->type |= 0x1;
940 break;
b586eb02
AP		 941 case VCPU_SREG_SS:
942 /* On AMD CPUs sometimes the DB bit in the segment
943 * descriptor is left as 1, although the whole segment has
944 * been made unusable. Clear it here to pass an Intel VMX
945 * entry check when cross vendor migrating.
946 */
947 if (var->unusable)
948 var->db = 0;
949 break;
1fbdc7a5 950 }
6aa8b732
AK		 951}
952
2e4d2653
IE		 953static int svm_get_cpl(struct kvm_vcpu *vcpu)
954{
955 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
956
957 return save->cpl;
958}
959
89a27f4d 960static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 961{
a2fa3e9f
GH		 962 struct vcpu_svm *svm = to_svm(vcpu);
963
89a27f4d
GN		 964 dt->size = svm->vmcb->save.idtr.limit;
965 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 966}
967
89a27f4d 968static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 969{
a2fa3e9f
GH		 970 struct vcpu_svm *svm = to_svm(vcpu);
971
89a27f4d
GN		 972 svm->vmcb->save.idtr.limit = dt->size;
973 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 974}
975
89a27f4d 976static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 977{
a2fa3e9f
GH		 978 struct vcpu_svm *svm = to_svm(vcpu);
979
89a27f4d
GN		 980 dt->size = svm->vmcb->save.gdtr.limit;
981 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 982}
983
89a27f4d 984static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 985{
a2fa3e9f
GH		 986 struct vcpu_svm *svm = to_svm(vcpu);
987
89a27f4d
GN		 988 svm->vmcb->save.gdtr.limit = dt->size;
989 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 990}
991
e8467fda
AK		 992static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
993{
994}
995
25c4c276 996static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 997{
998}
999
d225157b
AK		 1000static void update_cr0_intercept(struct vcpu_svm *svm)
1001{
66a562f7 1002 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1003 ulong gcr0 = svm->vcpu.arch.cr0;
1004 u64 *hcr0 = &svm->vmcb->save.cr0;
1005
1006 if (!svm->vcpu.fpu_active)
1007 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1008 else
1009 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1010 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1011
1012
1013 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1014 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1015 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1016 if (is_nested(svm)) {
1017 struct vmcb *hsave = svm->nested.hsave;
1018
1019 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1020 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1021 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1022 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1023 }
d225157b
AK		 1024 } else {
1025 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1026 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1027 if (is_nested(svm)) {
1028 struct vmcb *hsave = svm->nested.hsave;
1029
1030 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1031 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1032 }
d225157b
AK		 1033 }
1034}
1035
6aa8b732
AK		 1036static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1037{
a2fa3e9f
GH		 1038 struct vcpu_svm *svm = to_svm(vcpu);
1039
05b3e0c2 1040#ifdef CONFIG_X86_64
f6801dff 1041 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1042 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1043 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1044 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1045 }
1046
d77c26fc 1047 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1048 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1049 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1050 }
1051 }
1052#endif
ad312c7c 1053 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1054
1055 if (!npt_enabled)
1056 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1057
1058 if (!vcpu->fpu_active)
334df50a 1059 cr0 |= X86_CR0_TS;
709ddebf
JR		 1060 /*
1061 * re-enable caching here because the QEMU bios
1062 * does not do it - this results in some delay at
1063 * reboot
1064 */
1065 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1066 svm->vmcb->save.cr0 = cr0;
d225157b 1067 update_cr0_intercept(svm);
6aa8b732
AK		 1068}
1069
1070static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1071{
6394b649 1072 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1073 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1074
1075 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1076 force_new_asid(vcpu);
6394b649 1077
ec077263
JR		 1078 vcpu->arch.cr4 = cr4;
1079 if (!npt_enabled)
1080 cr4 |= X86_CR4_PAE;
6394b649 1081 cr4 |= host_cr4_mce;
ec077263 1082 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1083}
1084
1085static void svm_set_segment(struct kvm_vcpu *vcpu,
1086 struct kvm_segment *var, int seg)
1087{
a2fa3e9f 1088 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1089 struct vmcb_seg *s = svm_seg(vcpu, seg);
1090
1091 s->base = var->base;
1092 s->limit = var->limit;
1093 s->selector = var->selector;
1094 if (var->unusable)
1095 s->attrib = 0;
1096 else {
1097 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1098 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1099 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1100 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1101 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1102 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1103 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1104 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1105 }
1106 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1107 svm->vmcb->save.cpl
1108 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1109 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1110
1111}
1112
44c11430 1113static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1114{
d0bfb940
JK		 1115 struct vcpu_svm *svm = to_svm(vcpu);
1116
d0bfb940
JK		 1117 svm->vmcb->control.intercept_exceptions &=
1118 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1119
6be7d306 1120 if (svm->nmi_singlestep)
44c11430
GN		 1121 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1122
d0bfb940
JK		 1123 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1124 if (vcpu->guest_debug &
1125 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1126 svm->vmcb->control.intercept_exceptions |=
1127 1 << DB_VECTOR;
1128 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1129 svm->vmcb->control.intercept_exceptions |=
1130 1 << BP_VECTOR;
1131 } else
1132 vcpu->guest_debug = 0;
44c11430
GN		 1133}
1134
355be0b9 1135static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1136{
44c11430
GN		 1137 struct vcpu_svm *svm = to_svm(vcpu);
1138
ae675ef0
JK		 1139 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1140 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1141 else
1142 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1143
355be0b9 1144 update_db_intercept(vcpu);
6aa8b732
AK		 1145}
1146
1147static void load_host_msrs(struct kvm_vcpu *vcpu)
1148{
94dfbdb3 1149#ifdef CONFIG_X86_64
a2fa3e9f 1150 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1151#endif
6aa8b732
AK		 1152}
1153
1154static void save_host_msrs(struct kvm_vcpu *vcpu)
1155{
94dfbdb3 1156#ifdef CONFIG_X86_64
a2fa3e9f 1157 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1158#endif
6aa8b732
AK		 1159}
1160
0fe1e009 1161static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1162{
0fe1e009
TH		 1163 if (sd->next_asid > sd->max_asid) {
1164 ++sd->asid_generation;
1165 sd->next_asid = 1;
a2fa3e9f 1166 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1167 }
1168
0fe1e009
TH		 1169 svm->asid_generation = sd->asid_generation;
1170 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1171}
1172
c76de350 1173static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
6aa8b732 1174{
42dbaa5a 1175 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a
JK		 1176
1177 switch (dr) {
1178 case 0 ... 3:
c76de350 1179 *dest = vcpu->arch.db[dr];
42dbaa5a 1180 break;
c76de350
JK		 1181 case 4:
1182 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1183 return EMULATE_FAIL; /* will re-inject UD */
1184 /* fall through */
42dbaa5a
JK		 1185 case 6:
1186 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1187 *dest = vcpu->arch.dr6;
42dbaa5a 1188 else
c76de350 1189 *dest = svm->vmcb->save.dr6;
42dbaa5a 1190 break;
c76de350
JK		 1191 case 5:
1192 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1193 return EMULATE_FAIL; /* will re-inject UD */
1194 /* fall through */
42dbaa5a
JK		 1195 case 7:
1196 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1197 *dest = vcpu->arch.dr7;
42dbaa5a 1198 else
c76de350 1199 *dest = svm->vmcb->save.dr7;
42dbaa5a 1200 break;
42dbaa5a
JK		 1201 }
1202
c76de350 1203 return EMULATE_DONE;
6aa8b732
AK		 1204}
1205
c76de350 1206static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
6aa8b732 1207{
a2fa3e9f
GH		 1208 struct vcpu_svm *svm = to_svm(vcpu);
1209
6aa8b732
AK		 1210 switch (dr) {
1211 case 0 ... 3:
42dbaa5a
JK		 1212 vcpu->arch.db[dr] = value;
1213 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1214 vcpu->arch.eff_db[dr] = value;
c76de350
JK		 1215 break;
1216 case 4:
1217 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1218 return EMULATE_FAIL; /* will re-inject UD */
1219 /* fall through */
42dbaa5a 1220 case 6:
42dbaa5a 1221 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
c76de350
JK		 1222 break;
1223 case 5:
1224 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1225 return EMULATE_FAIL; /* will re-inject UD */
1226 /* fall through */
42dbaa5a 1227 case 7:
42dbaa5a
JK		 1228 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1229 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1230 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1231 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1232 }
c76de350 1233 break;
6aa8b732 1234 }
c76de350
JK		 1235
1236 return EMULATE_DONE;
6aa8b732
AK		 1237}
1238
851ba692 1239static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1240{
6aa8b732
AK		 1241 u64 fault_address;
1242 u32 error_code;
6aa8b732 1243
a2fa3e9f
GH		 1244 fault_address = svm->vmcb->control.exit_info_2;
1245 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1246
229456fc 1247 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1248 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1249 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1250 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1251}
1252
851ba692 1253static int db_interception(struct vcpu_svm *svm)
d0bfb940 1254{
851ba692
AK		 1255 struct kvm_run *kvm_run = svm->vcpu.run;
1256
d0bfb940 1257 if (!(svm->vcpu.guest_debug &
44c11430 1258 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1259 !svm->nmi_singlestep) {
d0bfb940
JK		 1260 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1261 return 1;
1262 }
44c11430 1263
6be7d306
JK		 1264 if (svm->nmi_singlestep) {
1265 svm->nmi_singlestep = false;
44c11430
GN		 1266 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1267 svm->vmcb->save.rflags &=
1268 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1269 update_db_intercept(&svm->vcpu);
1270 }
1271
1272 if (svm->vcpu.guest_debug &
1273 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1274 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1275 kvm_run->debug.arch.pc =
1276 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1277 kvm_run->debug.arch.exception = DB_VECTOR;
1278 return 0;
1279 }
1280
1281 return 1;
d0bfb940
JK		 1282}
1283
851ba692 1284static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1285{
851ba692
AK		 1286 struct kvm_run *kvm_run = svm->vcpu.run;
1287
d0bfb940
JK		 1288 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1289 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1290 kvm_run->debug.arch.exception = BP_VECTOR;
1291 return 0;
1292}
1293
851ba692 1294static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1295{
1296 int er;
1297
851ba692 1298 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1299 if (er != EMULATE_DONE)
7ee5d940 1300 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1301 return 1;
1302}
1303
6b52d186 1304static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1305{
6b52d186 1306 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1307 u32 excp;
1308
1309 if (is_nested(svm)) {
1310 u32 h_excp, n_excp;
1311
1312 h_excp = svm->nested.hsave->control.intercept_exceptions;
1313 n_excp = svm->nested.intercept_exceptions;
1314 h_excp &= ~(1 << NM_VECTOR);
1315 excp = h_excp | n_excp;
1316 } else {
1317 excp = svm->vmcb->control.intercept_exceptions;
1318 excp &= ~(1 << NM_VECTOR);
1319 }
1320
1321 svm->vmcb->control.intercept_exceptions = excp;
1322
e756fc62 1323 svm->vcpu.fpu_active = 1;
d225157b 1324 update_cr0_intercept(svm);
6b52d186 1325}
a2fa3e9f 1326
6b52d186
AK		 1327static int nm_interception(struct vcpu_svm *svm)
1328{
1329 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1330 return 1;
7807fa6c
AL		 1331}
1332
851ba692 1333static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1334{
1335 /*
1336 * On an #MC intercept the MCE handler is not called automatically in
1337 * the host. So do it by hand here.
1338 */
1339 asm volatile (
1340 "int $0x12\n");
1341 /* not sure if we ever come back to this point */
1342
1343 return 1;
1344}
1345
851ba692 1346static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1347{
851ba692
AK		 1348 struct kvm_run *kvm_run = svm->vcpu.run;
1349
46fe4ddd
JR		 1350 /*
1351 * VMCB is undefined after a SHUTDOWN intercept
1352 * so reinitialize it.
1353 */
a2fa3e9f 1354 clear_page(svm->vmcb);
e6101a96 1355 init_vmcb(svm);
46fe4ddd
JR		 1356
1357 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1358 return 0;
1359}
1360
851ba692 1361static int io_interception(struct vcpu_svm *svm)
6aa8b732 1362{
d77c26fc 1363 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1364 int size, in, string;
039576c0 1365 unsigned port;
6aa8b732 1366
e756fc62 1367 ++svm->vcpu.stat.io_exits;
6aa8b732 1368
a2fa3e9f 1369 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1370
e70669ab
LV		 1371 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1372
1373 if (string) {
3427318f 1374 if (emulate_instruction(&svm->vcpu,
851ba692 1375 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1376 return 0;
1377 return 1;
1378 }
1379
039576c0
AK		 1380 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1381 port = io_info >> 16;
1382 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1383
e93f36bc 1384 skip_emulated_instruction(&svm->vcpu);
851ba692 1385 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1386}
1387
851ba692 1388static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1389{
1390 return 1;
1391}
1392
851ba692 1393static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1394{
1395 ++svm->vcpu.stat.irq_exits;
1396 return 1;
1397}
1398
851ba692 1399static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1400{
1401 return 1;
1402}
1403
851ba692 1404static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1405{
5fdbf976 1406 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1407 skip_emulated_instruction(&svm->vcpu);
1408 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1409}
1410
851ba692 1411static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1412{
5fdbf976 1413 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1414 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1415 kvm_emulate_hypercall(&svm->vcpu);
1416 return 1;
02e235bc
AK		 1417}
1418
c0725420
AG		 1419static int nested_svm_check_permissions(struct vcpu_svm *svm)
1420{
f6801dff 1421 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1422 || !is_paging(&svm->vcpu)) {
1423 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1424 return 1;
1425 }
1426
1427 if (svm->vmcb->save.cpl) {
1428 kvm_inject_gp(&svm->vcpu, 0);
1429 return 1;
1430 }
1431
1432 return 0;
1433}
1434
cf74a78b
AG		 1435static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1436 bool has_error_code, u32 error_code)
1437{
b8e88bc8
JR		 1438 int vmexit;
1439
0295ad7d
JR		 1440 if (!is_nested(svm))
1441 return 0;
cf74a78b 1442
0295ad7d
JR		 1443 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1444 svm->vmcb->control.exit_code_hi = 0;
1445 svm->vmcb->control.exit_info_1 = error_code;
1446 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1447
b8e88bc8
JR		 1448 vmexit = nested_svm_intercept(svm);
1449 if (vmexit == NESTED_EXIT_DONE)
1450 svm->nested.exit_required = true;
1451
1452 return vmexit;
cf74a78b
AG		 1453}
1454
8fe54654
JR		 1455/* This function returns true if it is save to enable the irq window */
1456static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1457{
26666957 1458 if (!is_nested(svm))
8fe54654 1459 return true;
cf74a78b 1460
26666957 1461 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1462 return true;
cf74a78b 1463
26666957 1464 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1465 return false;
cf74a78b 1466
26666957
JR		 1467 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1468
cd3ff653
JR		 1469 if (svm->nested.intercept & 1ULL) {
1470 /*
1471 * The #vmexit can't be emulated here directly because this
1472 * code path runs with irqs and preemtion disabled. A
1473 * #vmexit emulation might sleep. Only signal request for
1474 * the #vmexit here.
1475 */
1476 svm->nested.exit_required = true;
236649de 1477 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1478 return false;
cf74a78b
AG		 1479 }
1480
8fe54654 1481 return true;
cf74a78b
AG		 1482}
1483
7597f129 1484static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1485{
1486 struct page *page;
1487
6c3bd3d7
JR		 1488 might_sleep();
1489
34f80cfa 1490 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1491 if (is_error_page(page))
1492 goto error;
1493
7597f129
JR		 1494 *_page = page;
1495
1496 return kmap(page);
34f80cfa
JR		 1497
1498error:
1499 kvm_release_page_clean(page);
1500 kvm_inject_gp(&svm->vcpu, 0);
1501
1502 return NULL;
1503}
1504
7597f129 1505static void nested_svm_unmap(struct page *page)
34f80cfa 1506{
7597f129 1507 kunmap(page);
34f80cfa
JR		 1508 kvm_release_page_dirty(page);
1509}
1510
3d62d9aa 1511static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1512{
4c2161ae 1513 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1514 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1515 bool ret = false;
1516 u32 t0, t1;
4c7da8cb 1517 u8 val;
4c2161ae 1518
3d62d9aa
JR		 1519 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1520 return false;
1521
4c2161ae
JR		 1522 switch (msr) {
1523 case 0 ... 0x1fff:
1524 t0 = (msr * 2) % 8;
1525 t1 = msr / 8;
1526 break;
1527 case 0xc0000000 ... 0xc0001fff:
1528 t0 = (8192 + msr - 0xc0000000) * 2;
1529 t1 = (t0 / 8);
1530 t0 %= 8;
1531 break;
1532 case 0xc0010000 ... 0xc0011fff:
1533 t0 = (16384 + msr - 0xc0010000) * 2;
1534 t1 = (t0 / 8);
1535 t0 %= 8;
1536 break;
1537 default:
3d62d9aa
JR		 1538 ret = true;
1539 goto out;
4c2161ae 1540 }
4c2161ae 1541
4c7da8cb
JR		 1542 if (!kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + t1, &val, 1))
1543 ret = val & ((1 << param) << t0);
3d62d9aa
JR		 1544
1545out:
3d62d9aa 1546 return ret;
4c2161ae
JR		 1547}
1548
410e4d57 1549static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1550{
cf74a78b 1551 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1552
410e4d57
JR		 1553 switch (exit_code) {
1554 case SVM_EXIT_INTR:
1555 case SVM_EXIT_NMI:
1556 return NESTED_EXIT_HOST;
cf74a78b 1557 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1558 case SVM_EXIT_NPF:
1559 if (npt_enabled)
1560 return NESTED_EXIT_HOST;
1561 break;
1562 /* When we're shadowing, trap PFs */
1563 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1564 if (!npt_enabled)
1565 return NESTED_EXIT_HOST;
1566 break;
66a562f7
JR		 1567 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1568 nm_interception(svm);
1569 break;
410e4d57
JR		 1570 default:
1571 break;
cf74a78b
AG		 1572 }
1573
410e4d57
JR		 1574 return NESTED_EXIT_CONTINUE;
1575}
1576
1577/*
1578 * If this function returns true, this #vmexit was already handled
1579 */
b8e88bc8 1580static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1581{
1582 u32 exit_code = svm->vmcb->control.exit_code;
1583 int vmexit = NESTED_EXIT_HOST;
1584
cf74a78b 1585 switch (exit_code) {
9c4e40b9 1586 case SVM_EXIT_MSR:
3d62d9aa 1587 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1588 break;
cf74a78b
AG		 1589 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1590 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1591 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1592 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1593 break;
1594 }
1595 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1596 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1597 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1598 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1599 break;
1600 }
1601 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1602 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1603 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1604 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1605 break;
1606 }
1607 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1608 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1609 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1610 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1611 break;
1612 }
1613 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1614 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1615 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1616 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1617 break;
1618 }
1619 default: {
1620 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1621 if (svm->nested.intercept & exit_bits)
410e4d57 1622 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1623 }
1624 }
1625
b8e88bc8
JR		 1626 return vmexit;
1627}
1628
1629static int nested_svm_exit_handled(struct vcpu_svm *svm)
1630{
1631 int vmexit;
1632
1633 vmexit = nested_svm_intercept(svm);
1634
1635 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1636 nested_svm_vmexit(svm);
9c4e40b9
JR		 1637
1638 return vmexit;
cf74a78b
AG		 1639}
1640
0460a979
JR		 1641static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1642{
1643 struct vmcb_control_area *dst = &dst_vmcb->control;
1644 struct vmcb_control_area *from = &from_vmcb->control;
1645
1646 dst->intercept_cr_read = from->intercept_cr_read;
1647 dst->intercept_cr_write = from->intercept_cr_write;
1648 dst->intercept_dr_read = from->intercept_dr_read;
1649 dst->intercept_dr_write = from->intercept_dr_write;
1650 dst->intercept_exceptions = from->intercept_exceptions;
1651 dst->intercept = from->intercept;
1652 dst->iopm_base_pa = from->iopm_base_pa;
1653 dst->msrpm_base_pa = from->msrpm_base_pa;
1654 dst->tsc_offset = from->tsc_offset;
1655 dst->asid = from->asid;
1656 dst->tlb_ctl = from->tlb_ctl;
1657 dst->int_ctl = from->int_ctl;
1658 dst->int_vector = from->int_vector;
1659 dst->int_state = from->int_state;
1660 dst->exit_code = from->exit_code;
1661 dst->exit_code_hi = from->exit_code_hi;
1662 dst->exit_info_1 = from->exit_info_1;
1663 dst->exit_info_2 = from->exit_info_2;
1664 dst->exit_int_info = from->exit_int_info;
1665 dst->exit_int_info_err = from->exit_int_info_err;
1666 dst->nested_ctl = from->nested_ctl;
1667 dst->event_inj = from->event_inj;
1668 dst->event_inj_err = from->event_inj_err;
1669 dst->nested_cr3 = from->nested_cr3;
1670 dst->lbr_ctl = from->lbr_ctl;
1671}
1672
34f80cfa 1673static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1674{
34f80cfa 1675 struct vmcb *nested_vmcb;
e6aa9abd 1676 struct vmcb *hsave = svm->nested.hsave;
33740e40 1677 struct vmcb *vmcb = svm->vmcb;
7597f129 1678 struct page *page;
cf74a78b 1679
17897f36
JR		 1680 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1681 vmcb->control.exit_info_1,
1682 vmcb->control.exit_info_2,
1683 vmcb->control.exit_int_info,
1684 vmcb->control.exit_int_info_err);
1685
7597f129 1686 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1687 if (!nested_vmcb)
1688 return 1;
1689
06fc7772
JR		 1690 /* Exit nested SVM mode */
1691 svm->nested.vmcb = 0;
1692
cf74a78b 1693 /* Give the current vmcb to the guest */
33740e40
JR		 1694 disable_gif(svm);
1695
1696 nested_vmcb->save.es = vmcb->save.es;
1697 nested_vmcb->save.cs = vmcb->save.cs;
1698 nested_vmcb->save.ss = vmcb->save.ss;
1699 nested_vmcb->save.ds = vmcb->save.ds;
1700 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1701 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1702 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
33740e40
JR		 1703 if (npt_enabled)
1704 nested_vmcb->save.cr3 = vmcb->save.cr3;
cdbbdc12
JR		 1705 else
1706 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1707 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1708 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1709 nested_vmcb->save.rflags = vmcb->save.rflags;
1710 nested_vmcb->save.rip = vmcb->save.rip;
1711 nested_vmcb->save.rsp = vmcb->save.rsp;
1712 nested_vmcb->save.rax = vmcb->save.rax;
1713 nested_vmcb->save.dr7 = vmcb->save.dr7;
1714 nested_vmcb->save.dr6 = vmcb->save.dr6;
1715 nested_vmcb->save.cpl = vmcb->save.cpl;
1716
1717 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1718 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1719 nested_vmcb->control.int_state = vmcb->control.int_state;
1720 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1721 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1722 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1723 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1724 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1725 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1726
1727 /*
1728 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1729 * to make sure that we do not lose injected events. So check event_inj
1730 * here and copy it to exit_int_info if it is valid.
1731 * Exit_int_info and event_inj can't be both valid because the case
1732 * below only happens on a VMRUN instruction intercept which has
1733 * no valid exit_int_info set.
1734 */
1735 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1736 struct vmcb_control_area *nc = &nested_vmcb->control;
1737
1738 nc->exit_int_info = vmcb->control.event_inj;
1739 nc->exit_int_info_err = vmcb->control.event_inj_err;
1740 }
1741
33740e40
JR		 1742 nested_vmcb->control.tlb_ctl = 0;
1743 nested_vmcb->control.event_inj = 0;
1744 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1745
1746 /* We always set V_INTR_MASKING and remember the old value in hflags */
1747 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1748 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1749
cf74a78b 1750 /* Restore the original control entries */
0460a979 1751 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1752
219b65dc
AG		 1753 kvm_clear_exception_queue(&svm->vcpu);
1754 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1755
1756 /* Restore selected save entries */
1757 svm->vmcb->save.es = hsave->save.es;
1758 svm->vmcb->save.cs = hsave->save.cs;
1759 svm->vmcb->save.ss = hsave->save.ss;
1760 svm->vmcb->save.ds = hsave->save.ds;
1761 svm->vmcb->save.gdtr = hsave->save.gdtr;
1762 svm->vmcb->save.idtr = hsave->save.idtr;
1763 svm->vmcb->save.rflags = hsave->save.rflags;
1764 svm_set_efer(&svm->vcpu, hsave->save.efer);
1765 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1766 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1767 if (npt_enabled) {
1768 svm->vmcb->save.cr3 = hsave->save.cr3;
1769 svm->vcpu.arch.cr3 = hsave->save.cr3;
1770 } else {
1771 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1772 }
1773 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1774 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1775 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1776 svm->vmcb->save.dr7 = 0;
1777 svm->vmcb->save.cpl = 0;
1778 svm->vmcb->control.exit_int_info = 0;
1779
7597f129 1780 nested_svm_unmap(page);
cf74a78b
AG		 1781
1782 kvm_mmu_reset_context(&svm->vcpu);
1783 kvm_mmu_load(&svm->vcpu);
1784
1785 return 0;
1786}
3d6368ef 1787
9738b2c9 1788static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1789{
9738b2c9 1790 u32 *nested_msrpm;
7597f129 1791 struct page *page;
3d6368ef 1792 int i;
9738b2c9 1793
7597f129 1794 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
9738b2c9
JR		 1795 if (!nested_msrpm)
1796 return false;
1797
3d6368ef 1798 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1799 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1800
e6aa9abd 1801 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1802
7597f129 1803 nested_svm_unmap(page);
9738b2c9
JR		 1804
1805 return true;
3d6368ef
AG		 1806}
1807
9738b2c9 1808static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1809{
9738b2c9 1810 struct vmcb *nested_vmcb;
e6aa9abd 1811 struct vmcb *hsave = svm->nested.hsave;
defbba56 1812 struct vmcb *vmcb = svm->vmcb;
7597f129 1813 struct page *page;
06fc7772
JR		 1814 u64 vmcb_gpa;
1815
1816 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 1817
7597f129 1818 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 1819 if (!nested_vmcb)
1820 return false;
1821
0ac406de
JR		 1822 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1823 nested_vmcb->save.rip,
1824 nested_vmcb->control.int_ctl,
1825 nested_vmcb->control.event_inj,
1826 nested_vmcb->control.nested_ctl);
1827
3d6368ef 1828 /* Clear internal status */
219b65dc
AG		 1829 kvm_clear_exception_queue(&svm->vcpu);
1830 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1831
1832 /* Save the old vmcb, so we don't need to pick what we save, but
1833 can restore everything when a VMEXIT occurs */
defbba56
JR		 1834 hsave->save.es = vmcb->save.es;
1835 hsave->save.cs = vmcb->save.cs;
1836 hsave->save.ss = vmcb->save.ss;
1837 hsave->save.ds = vmcb->save.ds;
1838 hsave->save.gdtr = vmcb->save.gdtr;
1839 hsave->save.idtr = vmcb->save.idtr;
f6801dff 1840 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 1841 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1842 hsave->save.cr4 = svm->vcpu.arch.cr4;
1843 hsave->save.rflags = vmcb->save.rflags;
1844 hsave->save.rip = svm->next_rip;
1845 hsave->save.rsp = vmcb->save.rsp;
1846 hsave->save.rax = vmcb->save.rax;
1847 if (npt_enabled)
1848 hsave->save.cr3 = vmcb->save.cr3;
1849 else
1850 hsave->save.cr3 = svm->vcpu.arch.cr3;
1851
0460a979 1852 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1853
1854 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1855 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1856 else
1857 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1858
1859 /* Load the nested guest state */
1860 svm->vmcb->save.es = nested_vmcb->save.es;
1861 svm->vmcb->save.cs = nested_vmcb->save.cs;
1862 svm->vmcb->save.ss = nested_vmcb->save.ss;
1863 svm->vmcb->save.ds = nested_vmcb->save.ds;
1864 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1865 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1866 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1867 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1868 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1869 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1870 if (npt_enabled) {
1871 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1872 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1873 } else {
1874 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1875 kvm_mmu_reset_context(&svm->vcpu);
1876 }
defbba56 1877 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1878 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1879 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1880 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1881 /* In case we don't even reach vcpu_run, the fields are not updated */
1882 svm->vmcb->save.rax = nested_vmcb->save.rax;
1883 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1884 svm->vmcb->save.rip = nested_vmcb->save.rip;
1885 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1886 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1887 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1888
e6aa9abd 1889 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1890
aad42c64
JR		 1891 /* cache intercepts */
1892 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1893 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1894 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1895 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1896 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1897 svm->nested.intercept = nested_vmcb->control.intercept;
1898
3d6368ef 1899 force_new_asid(&svm->vcpu);
3d6368ef 1900 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 1901 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1902 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1903 else
1904 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1905
88ab24ad
JR		 1906 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
1907 /* We only want the cr8 intercept bits of the guest */
1908 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
1909 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1910 }
1911
1912 /* We don't want a nested guest to be more powerful than the guest,
1913 so all intercepts are ORed */
1914 svm->vmcb->control.intercept_cr_read |=
1915 nested_vmcb->control.intercept_cr_read;
1916 svm->vmcb->control.intercept_cr_write |=
1917 nested_vmcb->control.intercept_cr_write;
1918 svm->vmcb->control.intercept_dr_read |=
1919 nested_vmcb->control.intercept_dr_read;
1920 svm->vmcb->control.intercept_dr_write |=
1921 nested_vmcb->control.intercept_dr_write;
1922 svm->vmcb->control.intercept_exceptions |=
1923 nested_vmcb->control.intercept_exceptions;
1924
1925 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1926
1927 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 1928 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1929 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1930 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 1931 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1932 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1933
7597f129 1934 nested_svm_unmap(page);
9738b2c9 1935
06fc7772
JR		 1936 /* nested_vmcb is our indicator if nested SVM is activated */
1937 svm->nested.vmcb = vmcb_gpa;
1938
2af9194d 1939 enable_gif(svm);
3d6368ef 1940
9738b2c9 1941 return true;
3d6368ef
AG		 1942}
1943
9966bf68 1944static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1945{
1946 to_vmcb->save.fs = from_vmcb->save.fs;
1947 to_vmcb->save.gs = from_vmcb->save.gs;
1948 to_vmcb->save.tr = from_vmcb->save.tr;
1949 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1950 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1951 to_vmcb->save.star = from_vmcb->save.star;
1952 to_vmcb->save.lstar = from_vmcb->save.lstar;
1953 to_vmcb->save.cstar = from_vmcb->save.cstar;
1954 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1955 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1956 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1957 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1958}
1959
851ba692 1960static int vmload_interception(struct vcpu_svm *svm)
5542675b 1961{
9966bf68 1962 struct vmcb *nested_vmcb;
7597f129 1963 struct page *page;
9966bf68 1964
5542675b
AG		 1965 if (nested_svm_check_permissions(svm))
1966 return 1;
1967
1968 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1969 skip_emulated_instruction(&svm->vcpu);
1970
7597f129 1971 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 1972 if (!nested_vmcb)
1973 return 1;
1974
1975 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 1976 nested_svm_unmap(page);
5542675b
AG		 1977
1978 return 1;
1979}
1980
851ba692 1981static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1982{
9966bf68 1983 struct vmcb *nested_vmcb;
7597f129 1984 struct page *page;
9966bf68 1985
5542675b
AG		 1986 if (nested_svm_check_permissions(svm))
1987 return 1;
1988
1989 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1990 skip_emulated_instruction(&svm->vcpu);
1991
7597f129 1992 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 1993 if (!nested_vmcb)
1994 return 1;
1995
1996 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 1997 nested_svm_unmap(page);
5542675b
AG		 1998
1999 return 1;
2000}
2001
851ba692 2002static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2003{
3d6368ef
AG		 2004 if (nested_svm_check_permissions(svm))
2005 return 1;
2006
2007 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2008 skip_emulated_instruction(&svm->vcpu);
2009
9738b2c9 2010 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2011 return 1;
2012
9738b2c9 2013 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2014 goto failed;
2015
2016 return 1;
2017
2018failed:
2019
2020 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2021 svm->vmcb->control.exit_code_hi = 0;
2022 svm->vmcb->control.exit_info_1 = 0;
2023 svm->vmcb->control.exit_info_2 = 0;
2024
2025 nested_svm_vmexit(svm);
3d6368ef
AG		 2026
2027 return 1;
2028}
2029
851ba692 2030static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2031{
2032 if (nested_svm_check_permissions(svm))
2033 return 1;
2034
2035 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2036 skip_emulated_instruction(&svm->vcpu);
2037
2af9194d 2038 enable_gif(svm);
1371d904
AG		 2039
2040 return 1;
2041}
2042
851ba692 2043static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2044{
2045 if (nested_svm_check_permissions(svm))
2046 return 1;
2047
2048 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2049 skip_emulated_instruction(&svm->vcpu);
2050
2af9194d 2051 disable_gif(svm);
1371d904
AG		 2052
2053 /* After a CLGI no interrupts should come */
2054 svm_clear_vintr(svm);
2055 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2056
2057 return 1;
2058}
2059
851ba692 2060static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2061{
2062 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2063
ec1ff790
JR		 2064 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2065 vcpu->arch.regs[VCPU_REGS_RAX]);
2066
ff092385
AG		 2067 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2068 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2069
2070 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2071 skip_emulated_instruction(&svm->vcpu);
2072 return 1;
2073}
2074
532a46b9
JR		 2075static int skinit_interception(struct vcpu_svm *svm)
2076{
2077 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2078
2079 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2080 return 1;
2081}
2082
851ba692 2083static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2084{
7ee5d940 2085 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2086 return 1;
2087}
2088
851ba692 2089static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2090{
37817f29 2091 u16 tss_selector;
64a7ec06
GN		 2092 int reason;
2093 int int_type = svm->vmcb->control.exit_int_info &
2094 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2095 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2096 uint32_t type =
2097 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2098 uint32_t idt_v =
2099 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2100
2101 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2102
37817f29
IE		 2103 if (svm->vmcb->control.exit_info_2 &
2104 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2105 reason = TASK_SWITCH_IRET;
2106 else if (svm->vmcb->control.exit_info_2 &
2107 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2108 reason = TASK_SWITCH_JMP;
fe8e7f83 2109 else if (idt_v)
64a7ec06
GN		 2110 reason = TASK_SWITCH_GATE;
2111 else
2112 reason = TASK_SWITCH_CALL;
2113
fe8e7f83
GN		 2114 if (reason == TASK_SWITCH_GATE) {
2115 switch (type) {
2116 case SVM_EXITINTINFO_TYPE_NMI:
2117 svm->vcpu.arch.nmi_injected = false;
2118 break;
2119 case SVM_EXITINTINFO_TYPE_EXEPT:
2120 kvm_clear_exception_queue(&svm->vcpu);
2121 break;
2122 case SVM_EXITINTINFO_TYPE_INTR:
2123 kvm_clear_interrupt_queue(&svm->vcpu);
2124 break;
2125 default:
2126 break;
2127 }
2128 }
64a7ec06 2129
8317c298
GN		 2130 if (reason != TASK_SWITCH_GATE ||
2131 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2132 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2133 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2134 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2135
2136 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2137}
2138
851ba692 2139static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2140{
5fdbf976 2141 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2142 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2143 return 1;
6aa8b732
AK		 2144}
2145
851ba692 2146static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2147{
2148 ++svm->vcpu.stat.nmi_window_exits;
2149 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2150 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2151 return 1;
2152}
2153
851ba692 2154static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2155{
851ba692 2156 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2157 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2158 return 1;
2159}
2160
851ba692 2161static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2162{
851ba692 2163 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2164 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2165 return 1;
2166}
2167
851ba692 2168static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2169{
851ba692
AK		 2170 struct kvm_run *kvm_run = svm->vcpu.run;
2171
0a5fff19
GN		 2172 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2173 /* instruction emulation calls kvm_set_cr8() */
851ba692 2174 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2175 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2176 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2177 return 1;
95ba8273 2178 }
0a5fff19
GN		 2179 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2180 return 1;
1d075434
JR		 2181 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2182 return 0;
2183}
2184
6aa8b732
AK		 2185static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2186{
a2fa3e9f
GH		 2187 struct vcpu_svm *svm = to_svm(vcpu);
2188
6aa8b732 2189 switch (ecx) {
af24a4e4 2190 case MSR_IA32_TSC: {
20824f30 2191 u64 tsc_offset;
6aa8b732 2192
20824f30
JR		 2193 if (is_nested(svm))
2194 tsc_offset = svm->nested.hsave->control.tsc_offset;
2195 else
2196 tsc_offset = svm->vmcb->control.tsc_offset;
2197
2198 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2199 break;
2200 }
0e859cac 2201 case MSR_K6_STAR:
a2fa3e9f 2202 *data = svm->vmcb->save.star;
6aa8b732 2203 break;
0e859cac 2204#ifdef CONFIG_X86_64
6aa8b732 2205 case MSR_LSTAR:
a2fa3e9f 2206 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2207 break;
2208 case MSR_CSTAR:
a2fa3e9f 2209 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2210 break;
2211 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2212 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2213 break;
2214 case MSR_SYSCALL_MASK:
a2fa3e9f 2215 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2216 break;
2217#endif
2218 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2219 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2220 break;
2221 case MSR_IA32_SYSENTER_EIP:
017cb99e 2222 *data = svm->sysenter_eip;
6aa8b732
AK		 2223 break;
2224 case MSR_IA32_SYSENTER_ESP:
017cb99e 2225 *data = svm->sysenter_esp;
6aa8b732 2226 break;
a2938c80
JR		 2227 /* Nobody will change the following 5 values in the VMCB so
2228 we can safely return them on rdmsr. They will always be 0
2229 until LBRV is implemented. */
2230 case MSR_IA32_DEBUGCTLMSR:
2231 *data = svm->vmcb->save.dbgctl;
2232 break;
2233 case MSR_IA32_LASTBRANCHFROMIP:
2234 *data = svm->vmcb->save.br_from;
2235 break;
2236 case MSR_IA32_LASTBRANCHTOIP:
2237 *data = svm->vmcb->save.br_to;
2238 break;
2239 case MSR_IA32_LASTINTFROMIP:
2240 *data = svm->vmcb->save.last_excp_from;
2241 break;
2242 case MSR_IA32_LASTINTTOIP:
2243 *data = svm->vmcb->save.last_excp_to;
2244 break;
b286d5d8 2245 case MSR_VM_HSAVE_PA:
e6aa9abd 2246 *data = svm->nested.hsave_msr;
b286d5d8 2247 break;
eb6f302e
JR		 2248 case MSR_VM_CR:
2249 *data = 0;
2250 break;
c8a73f18
AG		 2251 case MSR_IA32_UCODE_REV:
2252 *data = 0x01000065;
2253 break;
6aa8b732 2254 default:
3bab1f5d 2255 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2256 }
2257 return 0;
2258}
2259
851ba692 2260static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2261{
ad312c7c 2262 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2263 u64 data;
2264
59200273
AK		 2265 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2266 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2267 kvm_inject_gp(&svm->vcpu, 0);
59200273 2268 } else {
229456fc 2269 trace_kvm_msr_read(ecx, data);
af9ca2d7 2270
5fdbf976 2271 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2272 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2273 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2274 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2275 }
2276 return 1;
2277}
2278
2279static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2280{
a2fa3e9f
GH		 2281 struct vcpu_svm *svm = to_svm(vcpu);
2282
6aa8b732 2283 switch (ecx) {
af24a4e4 2284 case MSR_IA32_TSC: {
20824f30
JR		 2285 u64 tsc_offset = data - native_read_tsc();
2286 u64 g_tsc_offset = 0;
2287
2288 if (is_nested(svm)) {
2289 g_tsc_offset = svm->vmcb->control.tsc_offset -
2290 svm->nested.hsave->control.tsc_offset;
2291 svm->nested.hsave->control.tsc_offset = tsc_offset;
2292 }
2293
2294 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2295
6aa8b732
AK		 2296 break;
2297 }
0e859cac 2298 case MSR_K6_STAR:
a2fa3e9f 2299 svm->vmcb->save.star = data;
6aa8b732 2300 break;
49b14f24 2301#ifdef CONFIG_X86_64
6aa8b732 2302 case MSR_LSTAR:
a2fa3e9f 2303 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2304 break;
2305 case MSR_CSTAR:
a2fa3e9f 2306 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2307 break;
2308 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2309 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2310 break;
2311 case MSR_SYSCALL_MASK:
a2fa3e9f 2312 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2313 break;
2314#endif
2315 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2316 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2317 break;
2318 case MSR_IA32_SYSENTER_EIP:
017cb99e 2319 svm->sysenter_eip = data;
a2fa3e9f 2320 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2321 break;
2322 case MSR_IA32_SYSENTER_ESP:
017cb99e 2323 svm->sysenter_esp = data;
a2fa3e9f 2324 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2325 break;
a2938c80 2326 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2327 if (!svm_has(SVM_FEATURE_LBRV)) {
2328 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2329 __func__, data);
24e09cbf
JR		 2330 break;
2331 }
2332 if (data & DEBUGCTL_RESERVED_BITS)
2333 return 1;
2334
2335 svm->vmcb->save.dbgctl = data;
2336 if (data & (1ULL<<0))
2337 svm_enable_lbrv(svm);
2338 else
2339 svm_disable_lbrv(svm);
a2938c80 2340 break;
b286d5d8 2341 case MSR_VM_HSAVE_PA:
e6aa9abd 2342 svm->nested.hsave_msr = data;
62b9abaa 2343 break;
3c5d0a44
AG		 2344 case MSR_VM_CR:
2345 case MSR_VM_IGNNE:
3c5d0a44
AG		 2346 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2347 break;
6aa8b732 2348 default:
3bab1f5d 2349 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2350 }
2351 return 0;
2352}
2353
851ba692 2354static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2355{
ad312c7c 2356 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2357 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2358 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2359
af9ca2d7 2360
5fdbf976 2361 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2362 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2363 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2364 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2365 } else {
2366 trace_kvm_msr_write(ecx, data);
e756fc62 2367 skip_emulated_instruction(&svm->vcpu);
59200273 2368 }
6aa8b732
AK		 2369 return 1;
2370}
2371
851ba692 2372static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2373{
e756fc62 2374 if (svm->vmcb->control.exit_info_1)
851ba692 2375 return wrmsr_interception(svm);
6aa8b732 2376 else
851ba692 2377 return rdmsr_interception(svm);
6aa8b732
AK		 2378}
2379
851ba692 2380static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2381{
851ba692
AK		 2382 struct kvm_run *kvm_run = svm->vcpu.run;
2383
f0b85051 2384 svm_clear_vintr(svm);
85f455f7 2385 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2386 /*
2387 * If the user space waits to inject interrupts, exit as soon as
2388 * possible
2389 */
8061823a
GN		 2390 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2391 kvm_run->request_interrupt_window &&
2392 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2393 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2394 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2395 return 0;
2396 }
2397
2398 return 1;
2399}
2400
565d0998
ML		 2401static int pause_interception(struct vcpu_svm *svm)
2402{
2403 kvm_vcpu_on_spin(&(svm->vcpu));
2404 return 1;
2405}
2406
851ba692 2407static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
6aa8b732
AK		 2408 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2409 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2410 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2411 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2412 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
6aa8b732
AK		 2413 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2414 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2415 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2416 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2417 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2418 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2419 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2420 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2421 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2422 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2423 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2424 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2425 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2426 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2427 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2428 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2429 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2430 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2431 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2432 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2433 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2434 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2435 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2436 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2437 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2438 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2439 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2440 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2441 [SVM_EXIT_SMI] = nop_on_interception,
2442 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2443 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2444 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2445 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2446 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2447 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2448 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2449 [SVM_EXIT_HLT] = halt_interception,
a7052897 2450 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2451 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2452 [SVM_EXIT_IOIO] = io_interception,
2453 [SVM_EXIT_MSR] = msr_interception,
2454 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2455 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2456 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2457 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2458 [SVM_EXIT_VMLOAD] = vmload_interception,
2459 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2460 [SVM_EXIT_STGI] = stgi_interception,
2461 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2462 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2463 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2464 [SVM_EXIT_MONITOR] = invalid_op_interception,
2465 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2466 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2467};
2468
851ba692 2469static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2470{
04d2cc77 2471 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2472 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2473 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2474
229456fc 2475 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2476
cd3ff653
JR		 2477 if (unlikely(svm->nested.exit_required)) {
2478 nested_svm_vmexit(svm);
2479 svm->nested.exit_required = false;
2480
2481 return 1;
2482 }
2483
cf74a78b 2484 if (is_nested(svm)) {
410e4d57
JR		 2485 int vmexit;
2486
d8cabddf
JR		 2487 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2488 svm->vmcb->control.exit_info_1,
2489 svm->vmcb->control.exit_info_2,
2490 svm->vmcb->control.exit_int_info,
2491 svm->vmcb->control.exit_int_info_err);
2492
410e4d57
JR		 2493 vmexit = nested_svm_exit_special(svm);
2494
2495 if (vmexit == NESTED_EXIT_CONTINUE)
2496 vmexit = nested_svm_exit_handled(svm);
2497
2498 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2499 return 1;
cf74a78b
AG		 2500 }
2501
a5c3832d
JR		 2502 svm_complete_interrupts(svm);
2503
888f9f3e 2504 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2505 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2506 if (npt_enabled)
709ddebf 2507 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2508
2509 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2510 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2511 kvm_run->fail_entry.hardware_entry_failure_reason
2512 = svm->vmcb->control.exit_code;
2513 return 0;
2514 }
2515
a2fa3e9f 2516 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2517 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2518 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2519 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2520 "exit_code 0x%x\n",
b8688d51 2521 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2522 exit_code);
2523
9d8f549d 2524 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2525 || !svm_exit_handlers[exit_code]) {
6aa8b732 2526 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2527 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2528 return 0;
2529 }
2530
851ba692 2531 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2532}
2533
2534static void reload_tss(struct kvm_vcpu *vcpu)
2535{
2536 int cpu = raw_smp_processor_id();
2537
0fe1e009
TH		 2538 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2539 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2540 load_TR_desc();
2541}
2542
e756fc62 2543static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2544{
2545 int cpu = raw_smp_processor_id();
2546
0fe1e009 2547 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2548
a2fa3e9f 2549 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2550 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2551 if (svm->asid_generation != sd->asid_generation)
2552 new_asid(svm, sd);
6aa8b732
AK		 2553}
2554
95ba8273
GN		 2555static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2556{
2557 struct vcpu_svm *svm = to_svm(vcpu);
2558
2559 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2560 vcpu->arch.hflags |= HF_NMI_MASK;
2561 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2562 ++vcpu->stat.nmi_injections;
2563}
6aa8b732 2564
85f455f7 2565static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2566{
2567 struct vmcb_control_area *control;
2568
229456fc 2569 trace_kvm_inj_virq(irq);
af9ca2d7 2570
fa89a817 2571 ++svm->vcpu.stat.irq_injections;
e756fc62 2572 control = &svm->vmcb->control;
85f455f7 2573 control->int_vector = irq;
6aa8b732
AK		 2574 control->int_ctl &= ~V_INTR_PRIO_MASK;
2575 control->int_ctl |= V_IRQ_MASK |
2576 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2577}
2578
66fd3f7f 2579static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2580{
2581 struct vcpu_svm *svm = to_svm(vcpu);
2582
2af9194d 2583 BUG_ON(!(gif_set(svm)));
cf74a78b 2584
219b65dc
AG		 2585 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2586 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2587}
2588
95ba8273 2589static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2590{
2591 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2592
88ab24ad
JR		 2593 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2594 return;
2595
95ba8273 2596 if (irr == -1)
aaacfc9a
JR		 2597 return;
2598
95ba8273
GN		 2599 if (tpr >= irr)
2600 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2601}
aaacfc9a 2602
95ba8273
GN		 2603static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2604{
2605 struct vcpu_svm *svm = to_svm(vcpu);
2606 struct vmcb *vmcb = svm->vmcb;
2607 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2608 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2609}
2610
3cfc3092
JK		 2611static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2612{
2613 struct vcpu_svm *svm = to_svm(vcpu);
2614
2615 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2616}
2617
2618static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2619{
2620 struct vcpu_svm *svm = to_svm(vcpu);
2621
2622 if (masked) {
2623 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2624 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2625 } else {
2626 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2627 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2628 }
2629}
2630
78646121
GN		 2631static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2632{
2633 struct vcpu_svm *svm = to_svm(vcpu);
2634 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2635 int ret;
2636
2637 if (!gif_set(svm) ||
2638 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2639 return 0;
2640
2641 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2642
2643 if (is_nested(svm))
2644 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2645
2646 return ret;
78646121
GN		 2647}
2648
9222be18 2649static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2650{
219b65dc 2651 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 2652
219b65dc
AG		 2653 /* In case GIF=0 we can't rely on the CPU to tell us when
2654 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2655 * The next time we get that intercept, this function will be
2656 * called again though and we'll get the vintr intercept. */
8fe54654 2657 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 2658 svm_set_vintr(svm);
2659 svm_inject_irq(svm, 0x0);
2660 }
85f455f7
ED		 2661}
2662
95ba8273 2663static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2664{
04d2cc77 2665 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2666
44c11430
GN		 2667 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2668 == HF_NMI_MASK)
2669 return; /* IRET will cause a vm exit */
2670
2671 /* Something prevents NMI from been injected. Single step over
2672 possible problem (IRET or exception injection or interrupt
2673 shadow) */
6be7d306 2674 svm->nmi_singlestep = true;
44c11430
GN		 2675 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2676 update_db_intercept(vcpu);
c1150d8c
DL		 2677}
2678
cbc94022
IE		 2679static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2680{
2681 return 0;
2682}
2683
d9e368d6
AK		 2684static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2685{
2686 force_new_asid(vcpu);
2687}
2688
04d2cc77
AK		 2689static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2690{
2691}
2692
d7bf8221
JR		 2693static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2694{
2695 struct vcpu_svm *svm = to_svm(vcpu);
2696
88ab24ad
JR		 2697 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2698 return;
2699
d7bf8221
JR		 2700 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2701 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2702 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2703 }
2704}
2705
649d6864
JR		 2706static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2707{
2708 struct vcpu_svm *svm = to_svm(vcpu);
2709 u64 cr8;
2710
88ab24ad
JR		 2711 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2712 return;
2713
649d6864
JR		 2714 cr8 = kvm_get_cr8(vcpu);
2715 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2716 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2717}
2718
9222be18
GN		 2719static void svm_complete_interrupts(struct vcpu_svm *svm)
2720{
2721 u8 vector;
2722 int type;
2723 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 2724 unsigned int3_injected = svm->int3_injected;
2725
2726 svm->int3_injected = 0;
9222be18 2727
44c11430
GN		 2728 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2729 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2730
9222be18
GN		 2731 svm->vcpu.arch.nmi_injected = false;
2732 kvm_clear_exception_queue(&svm->vcpu);
2733 kvm_clear_interrupt_queue(&svm->vcpu);
2734
2735 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2736 return;
2737
2738 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2739 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2740
2741 switch (type) {
2742 case SVM_EXITINTINFO_TYPE_NMI:
2743 svm->vcpu.arch.nmi_injected = true;
2744 break;
2745 case SVM_EXITINTINFO_TYPE_EXEPT:
219b65dc
AG		 2746 if (is_nested(svm))
2747 break;
66b7138f
JK		 2748 /*
2749 * In case of software exceptions, do not reinject the vector,
2750 * but re-execute the instruction instead. Rewind RIP first
2751 * if we emulated INT3 before.
2752 */
2753 if (kvm_exception_is_soft(vector)) {
2754 if (vector == BP_VECTOR && int3_injected &&
2755 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2756 kvm_rip_write(&svm->vcpu,
2757 kvm_rip_read(&svm->vcpu) -
2758 int3_injected);
9222be18 2759 break;
66b7138f 2760 }
9222be18
GN		 2761 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2762 u32 err = svm->vmcb->control.exit_int_info_err;
2763 kvm_queue_exception_e(&svm->vcpu, vector, err);
2764
2765 } else
2766 kvm_queue_exception(&svm->vcpu, vector);
2767 break;
2768 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2769 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2770 break;
2771 default:
2772 break;
2773 }
2774}
2775
80e31d4f
AK		 2776#ifdef CONFIG_X86_64
2777#define R "r"
2778#else
2779#define R "e"
2780#endif
2781
851ba692 2782static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2783{
a2fa3e9f 2784 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2785 u16 fs_selector;
2786 u16 gs_selector;
2787 u16 ldt_selector;
d9e368d6 2788
cd3ff653
JR		 2789 /*
2790 * A vmexit emulation is required before the vcpu can be executed
2791 * again.
2792 */
2793 if (unlikely(svm->nested.exit_required))
2794 return;
2795
5fdbf976
MT		 2796 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2797 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2798 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2799
e756fc62 2800 pre_svm_run(svm);
6aa8b732 2801
649d6864
JR		 2802 sync_lapic_to_cr8(vcpu);
2803
6aa8b732 2804 save_host_msrs(vcpu);
d6e88aec
AK		 2805 fs_selector = kvm_read_fs();
2806 gs_selector = kvm_read_gs();
2807 ldt_selector = kvm_read_ldt();
cda0ffdd 2808 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2809 /* required for live migration with NPT */
2810 if (npt_enabled)
2811 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2812
04d2cc77
AK		 2813 clgi();
2814
2815 local_irq_enable();
36241b8c 2816
6aa8b732 2817 asm volatile (
80e31d4f
AK		 2818 "push %%"R"bp; \n\t"
2819 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2820 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2821 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2822 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2823 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2824 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2825#ifdef CONFIG_X86_64
fb3f0f51
RR		 2826 "mov %c[r8](%[svm]), %%r8 \n\t"
2827 "mov %c[r9](%[svm]), %%r9 \n\t"
2828 "mov %c[r10](%[svm]), %%r10 \n\t"
2829 "mov %c[r11](%[svm]), %%r11 \n\t"
2830 "mov %c[r12](%[svm]), %%r12 \n\t"
2831 "mov %c[r13](%[svm]), %%r13 \n\t"
2832 "mov %c[r14](%[svm]), %%r14 \n\t"
2833 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2834#endif
2835
6aa8b732 2836 /* Enter guest mode */
80e31d4f
AK		 2837 "push %%"R"ax \n\t"
2838 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2839 __ex(SVM_VMLOAD) "\n\t"
2840 __ex(SVM_VMRUN) "\n\t"
2841 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2842 "pop %%"R"ax \n\t"
6aa8b732
AK		 2843
2844 /* Save guest registers, load host registers */
80e31d4f
AK		 2845 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2846 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2847 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2848 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2849 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2850 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2851#ifdef CONFIG_X86_64
fb3f0f51
RR		 2852 "mov %%r8, %c[r8](%[svm]) \n\t"
2853 "mov %%r9, %c[r9](%[svm]) \n\t"
2854 "mov %%r10, %c[r10](%[svm]) \n\t"
2855 "mov %%r11, %c[r11](%[svm]) \n\t"
2856 "mov %%r12, %c[r12](%[svm]) \n\t"
2857 "mov %%r13, %c[r13](%[svm]) \n\t"
2858 "mov %%r14, %c[r14](%[svm]) \n\t"
2859 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2860#endif
80e31d4f 2861 "pop %%"R"bp"
6aa8b732 2862 :
fb3f0f51 2863 : [svm]"a"(svm),
6aa8b732 2864 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2865 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2866 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2867 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2868 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2869 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2870 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2871#ifdef CONFIG_X86_64
ad312c7c
ZX		 2872 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2873 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2874 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2875 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2876 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2877 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2878 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2879 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2880#endif
54a08c04 2881 : "cc", "memory"
80e31d4f 2882 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2883#ifdef CONFIG_X86_64
54a08c04
LV		 2884 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2885#endif
2886 );
6aa8b732 2887
ad312c7c 2888 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2889 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2890 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2891 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2892
d6e88aec
AK		 2893 kvm_load_fs(fs_selector);
2894 kvm_load_gs(gs_selector);
2895 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2896 load_host_msrs(vcpu);
2897
2898 reload_tss(vcpu);
2899
56ba47dd
AK		 2900 local_irq_disable();
2901
2902 stgi();
2903
d7bf8221
JR		 2904 sync_cr8_to_lapic(vcpu);
2905
a2fa3e9f 2906 svm->next_rip = 0;
9222be18 2907
6de4f3ad
AK		 2908 if (npt_enabled) {
2909 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2910 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2911 }
6aa8b732
AK		 2912}
2913
80e31d4f
AK		 2914#undef R
2915
6aa8b732
AK		 2916static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2917{
a2fa3e9f
GH		 2918 struct vcpu_svm *svm = to_svm(vcpu);
2919
709ddebf
JR		 2920 if (npt_enabled) {
2921 svm->vmcb->control.nested_cr3 = root;
2922 force_new_asid(vcpu);
2923 return;
2924 }
2925
a2fa3e9f 2926 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 2927 force_new_asid(vcpu);
2928}
2929
6aa8b732
AK		 2930static int is_disabled(void)
2931{
6031a61c
JR		 2932 u64 vm_cr;
2933
2934 rdmsrl(MSR_VM_CR, vm_cr);
2935 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2936 return 1;
2937
6aa8b732
AK		 2938 return 0;
2939}
2940
102d8325
IM		 2941static void
2942svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2943{
2944 /*
2945 * Patch in the VMMCALL instruction:
2946 */
2947 hypercall[0] = 0x0f;
2948 hypercall[1] = 0x01;
2949 hypercall[2] = 0xd9;
102d8325
IM		 2950}
2951
002c7f7c
YS		 2952static void svm_check_processor_compat(void *rtn)
2953{
2954 *(int *)rtn = 0;
2955}
2956
774ead3a
AK		 2957static bool svm_cpu_has_accelerated_tpr(void)
2958{
2959 return false;
2960}
2961
67253af5
SY		 2962static int get_npt_level(void)
2963{
2964#ifdef CONFIG_X86_64
2965 return PT64_ROOT_LEVEL;
2966#else
2967 return PT32E_ROOT_LEVEL;
2968#endif
2969}
2970
4b12f0de 2971static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2972{
2973 return 0;
2974}
2975
0e851880
SY		 2976static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2977{
2978}
2979
229456fc
MT		 2980static const struct trace_print_flags svm_exit_reasons_str[] = {
2981 { SVM_EXIT_READ_CR0, "read_cr0" },
2982 { SVM_EXIT_READ_CR3, "read_cr3" },
2983 { SVM_EXIT_READ_CR4, "read_cr4" },
2984 { SVM_EXIT_READ_CR8, "read_cr8" },
2985 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2986 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2987 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2988 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2989 { SVM_EXIT_READ_DR0, "read_dr0" },
2990 { SVM_EXIT_READ_DR1, "read_dr1" },
2991 { SVM_EXIT_READ_DR2, "read_dr2" },
2992 { SVM_EXIT_READ_DR3, "read_dr3" },
2993 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2994 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2995 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2996 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2997 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2998 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2999 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3000 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3001 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3002 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3003 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3004 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3005 { SVM_EXIT_INTR, "interrupt" },
3006 { SVM_EXIT_NMI, "nmi" },
3007 { SVM_EXIT_SMI, "smi" },
3008 { SVM_EXIT_INIT, "init" },
3009 { SVM_EXIT_VINTR, "vintr" },
3010 { SVM_EXIT_CPUID, "cpuid" },
3011 { SVM_EXIT_INVD, "invd" },
3012 { SVM_EXIT_HLT, "hlt" },
3013 { SVM_EXIT_INVLPG, "invlpg" },
3014 { SVM_EXIT_INVLPGA, "invlpga" },
3015 { SVM_EXIT_IOIO, "io" },
3016 { SVM_EXIT_MSR, "msr" },
3017 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3018 { SVM_EXIT_SHUTDOWN, "shutdown" },
3019 { SVM_EXIT_VMRUN, "vmrun" },
3020 { SVM_EXIT_VMMCALL, "hypercall" },
3021 { SVM_EXIT_VMLOAD, "vmload" },
3022 { SVM_EXIT_VMSAVE, "vmsave" },
3023 { SVM_EXIT_STGI, "stgi" },
3024 { SVM_EXIT_CLGI, "clgi" },
3025 { SVM_EXIT_SKINIT, "skinit" },
3026 { SVM_EXIT_WBINVD, "wbinvd" },
3027 { SVM_EXIT_MONITOR, "monitor" },
3028 { SVM_EXIT_MWAIT, "mwait" },
3029 { SVM_EXIT_NPF, "npf" },
3030 { -1, NULL }
3031};
3032
17cc3935 3033static int svm_get_lpage_level(void)
344f414f 3034{
17cc3935 3035 return PT_PDPE_LEVEL;
344f414f
JR		 3036}
3037
4e47c7a6
SY		 3038static bool svm_rdtscp_supported(void)
3039{
3040 return false;
3041}
3042
02daab21
AK		 3043static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3044{
3045 struct vcpu_svm *svm = to_svm(vcpu);
3046
02daab21 3047 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3048 if (is_nested(svm))
3049 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3050 update_cr0_intercept(svm);
02daab21
AK		 3051}
3052
cbdd1bea 3053static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3054 .cpu_has_kvm_support = has_svm,
3055 .disabled_by_bios = is_disabled,
3056 .hardware_setup = svm_hardware_setup,
3057 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3058 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3059 .hardware_enable = svm_hardware_enable,
3060 .hardware_disable = svm_hardware_disable,
774ead3a 3061 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3062
3063 .vcpu_create = svm_create_vcpu,
3064 .vcpu_free = svm_free_vcpu,
04d2cc77 3065 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3066
04d2cc77 3067 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3068 .vcpu_load = svm_vcpu_load,
3069 .vcpu_put = svm_vcpu_put,
3070
3071 .set_guest_debug = svm_guest_debug,
3072 .get_msr = svm_get_msr,
3073 .set_msr = svm_set_msr,
3074 .get_segment_base = svm_get_segment_base,
3075 .get_segment = svm_get_segment,
3076 .set_segment = svm_set_segment,
2e4d2653 3077 .get_cpl = svm_get_cpl,
1747fb71 3078 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3079 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3080 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3081 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3082 .set_cr3 = svm_set_cr3,
3083 .set_cr4 = svm_set_cr4,
3084 .set_efer = svm_set_efer,
3085 .get_idt = svm_get_idt,
3086 .set_idt = svm_set_idt,
3087 .get_gdt = svm_get_gdt,
3088 .set_gdt = svm_set_gdt,
3089 .get_dr = svm_get_dr,
3090 .set_dr = svm_set_dr,
6de4f3ad 3091 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3092 .get_rflags = svm_get_rflags,
3093 .set_rflags = svm_set_rflags,
6b52d186 3094 .fpu_activate = svm_fpu_activate,
02daab21 3095 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3096
6aa8b732 3097 .tlb_flush = svm_flush_tlb,
6aa8b732 3098
6aa8b732 3099 .run = svm_vcpu_run,
04d2cc77 3100 .handle_exit = handle_exit,
6aa8b732 3101 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3102 .set_interrupt_shadow = svm_set_interrupt_shadow,
3103 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3104 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3105 .set_irq = svm_set_irq,
95ba8273 3106 .set_nmi = svm_inject_nmi,
298101da 3107 .queue_exception = svm_queue_exception,
78646121 3108 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3109 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3110 .get_nmi_mask = svm_get_nmi_mask,
3111 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3112 .enable_nmi_window = enable_nmi_window,
3113 .enable_irq_window = enable_irq_window,
3114 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3115
3116 .set_tss_addr = svm_set_tss_addr,
67253af5 3117 .get_tdp_level = get_npt_level,
4b12f0de 3118 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3119
3120 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3121 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3122
3123 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3124
3125 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3126};
3127
3128static int __init svm_init(void)
3129{
cb498ea2 3130 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3131 THIS_MODULE);
6aa8b732
AK		 3132}
3133
3134static void __exit svm_exit(void)
3135{
cb498ea2 3136 kvm_exit();
6aa8b732
AK		 3137}
3138
3139module_init(svm_init)
3140module_exit(svm_exit)
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