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KVM: SVM: Introduce direct access msr list
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
e495606d 31#include <asm/desc.h>
6aa8b732 32
63d1142f 33#include <asm/virtext.h>
229456fc 34#include "trace.h"
63d1142f 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
41#define IOPM_ALLOC_ORDER 2
42#define MSRPM_ALLOC_ORDER 1
43
6aa8b732
AK		 44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
80b7706e
JR		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 49#define SVM_FEATURE_SVML (1 << 2)
66b7138f 50#define SVM_FEATURE_NRIP (1 << 3)
565d0998 51#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 52
410e4d57
JR		 53#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
56
24e09cbf
JR		 57#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58
6c8166a7
AK		 59static const u32 host_save_user_msrs[] = {
60#ifdef CONFIG_X86_64
61 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_FS_BASE,
63#endif
64 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65};
66
67#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
68
69struct kvm_vcpu;
70
e6aa9abd
JR		 71struct nested_state {
72 struct vmcb *hsave;
73 u64 hsave_msr;
4a810181 74 u64 vm_cr_msr;
e6aa9abd
JR		 75 u64 vmcb;
76
77 /* These are the merged vectors */
78 u32 *msrpm;
79
80 /* gpa pointers to the real vectors */
81 u64 vmcb_msrpm;
aad42c64 82
cd3ff653
JR		 83 /* A VMEXIT is required but not yet emulated */
84 bool exit_required;
85
aad42c64
JR		 86 /* cache for intercepts of the guest */
87 u16 intercept_cr_read;
88 u16 intercept_cr_write;
89 u16 intercept_dr_read;
90 u16 intercept_dr_write;
91 u32 intercept_exceptions;
92 u64 intercept;
93
e6aa9abd
JR		 94};
95
6c8166a7
AK		 96struct vcpu_svm {
97 struct kvm_vcpu vcpu;
98 struct vmcb *vmcb;
99 unsigned long vmcb_pa;
100 struct svm_cpu_data *svm_data;
101 uint64_t asid_generation;
102 uint64_t sysenter_esp;
103 uint64_t sysenter_eip;
104
105 u64 next_rip;
106
107 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
108 u64 host_gs_base;
6c8166a7
AK		 109
110 u32 *msrpm;
6c8166a7 111
e6aa9abd 112 struct nested_state nested;
6be7d306
JK		 113
114 bool nmi_singlestep;
66b7138f
JK		 115
116 unsigned int3_injected;
117 unsigned long int3_rip;
6c8166a7
AK		 118};
119
455716fa
JR		 120#define MSR_INVALID 0xffffffffU
121
ac72a9b7
JR		 122static struct svm_direct_access_msrs {
123 u32 index; /* Index of the MSR */
124 bool always; /* True if intercept is always on */
125} direct_access_msrs[] = {
126 { .index = MSR_K6_STAR, .always = true },
127 { .index = MSR_IA32_SYSENTER_CS, .always = true },
128#ifdef CONFIG_X86_64
129 { .index = MSR_GS_BASE, .always = true },
130 { .index = MSR_FS_BASE, .always = true },
131 { .index = MSR_KERNEL_GS_BASE, .always = true },
132 { .index = MSR_LSTAR, .always = true },
133 { .index = MSR_CSTAR, .always = true },
134 { .index = MSR_SYSCALL_MASK, .always = true },
135#endif
136 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
137 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
138 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
139 { .index = MSR_IA32_LASTINTTOIP, .always = false },
140 { .index = MSR_INVALID, .always = false },
141};
142
709ddebf
JR		 143/* enable NPT for AMD64 and X86 with PAE */
144#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
145static bool npt_enabled = true;
146#else
e0231715 147static bool npt_enabled;
709ddebf 148#endif
6c7dac72
JR		 149static int npt = 1;
150
151module_param(npt, int, S_IRUGO);
e3da3acd 152
4b6e4dca 153static int nested = 1;
236de055
AG		 154module_param(nested, int, S_IRUGO);
155
44874f84 156static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 157static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 158
410e4d57 159static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 160static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 161static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 162static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
163 bool has_error_code, u32 error_code);
164
a2fa3e9f
GH		 165static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
166{
fb3f0f51 167 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 168}
169
3d6368ef
AG		 170static inline bool is_nested(struct vcpu_svm *svm)
171{
e6aa9abd 172 return svm->nested.vmcb;
3d6368ef
AG		 173}
174
2af9194d
JR		 175static inline void enable_gif(struct vcpu_svm *svm)
176{
177 svm->vcpu.arch.hflags |= HF_GIF_MASK;
178}
179
180static inline void disable_gif(struct vcpu_svm *svm)
181{
182 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
183}
184
185static inline bool gif_set(struct vcpu_svm *svm)
186{
187 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
188}
189
4866d5e3 190static unsigned long iopm_base;
6aa8b732
AK		 191
192struct kvm_ldttss_desc {
193 u16 limit0;
194 u16 base0;
e0231715
JR		 195 unsigned base1:8, type:5, dpl:2, p:1;
196 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 197 u32 base3;
198 u32 zero1;
199} __attribute__((packed));
200
201struct svm_cpu_data {
202 int cpu;
203
5008fdf5
AK		 204 u64 asid_generation;
205 u32 max_asid;
206 u32 next_asid;
6aa8b732
AK		 207 struct kvm_ldttss_desc *tss_desc;
208
209 struct page *save_area;
210};
211
212static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 213static uint32_t svm_features;
6aa8b732
AK		 214
215struct svm_init_data {
216 int cpu;
217 int r;
218};
219
220static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
221
9d8f549d 222#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 223#define MSRS_RANGE_SIZE 2048
224#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
225
455716fa
JR		 226static u32 svm_msrpm_offset(u32 msr)
227{
228 u32 offset;
229 int i;
230
231 for (i = 0; i < NUM_MSR_MAPS; i++) {
232 if (msr < msrpm_ranges[i] ||
233 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
234 continue;
235
236 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
237 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
238
239 /* Now we have the u8 offset - but need the u32 offset */
240 return offset / 4;
241 }
242
243 /* MSR not in any range */
244 return MSR_INVALID;
245}
246
6aa8b732
AK		 247#define MAX_INST_SIZE 15
248
80b7706e
JR		 249static inline u32 svm_has(u32 feat)
250{
251 return svm_features & feat;
252}
253
6aa8b732
AK		 254static inline void clgi(void)
255{
4ecac3fd 256 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 257}
258
259static inline void stgi(void)
260{
4ecac3fd 261 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 262}
263
264static inline void invlpga(unsigned long addr, u32 asid)
265{
e0231715 266 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 267}
268
6aa8b732
AK		 269static inline void force_new_asid(struct kvm_vcpu *vcpu)
270{
a2fa3e9f 271 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 272}
273
274static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
275{
276 force_new_asid(vcpu);
277}
278
279static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
280{
709ddebf 281 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 282 efer &= ~EFER_LME;
6aa8b732 283
9962d032 284 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 285 vcpu->arch.efer = efer;
6aa8b732
AK		 286}
287
6aa8b732
AK		 288static int is_external_interrupt(u32 info)
289{
290 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
291 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
292}
293
2809f5d2
GC		 294static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
295{
296 struct vcpu_svm *svm = to_svm(vcpu);
297 u32 ret = 0;
298
299 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 300 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 301 return ret & mask;
302}
303
304static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
305{
306 struct vcpu_svm *svm = to_svm(vcpu);
307
308 if (mask == 0)
309 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
310 else
311 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
312
313}
314
6aa8b732
AK		 315static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
316{
a2fa3e9f
GH		 317 struct vcpu_svm *svm = to_svm(vcpu);
318
319 if (!svm->next_rip) {
851ba692 320 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 321 EMULATE_DONE)
322 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 323 return;
324 }
5fdbf976
MT		 325 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
326 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
327 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 328
5fdbf976 329 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 330 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 331}
332
116a4752
JK		 333static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
334 bool has_error_code, u32 error_code)
335{
336 struct vcpu_svm *svm = to_svm(vcpu);
337
e0231715
JR		 338 /*
339 * If we are within a nested VM we'd better #VMEXIT and let the guest
340 * handle the exception
341 */
116a4752
JK		 342 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
343 return;
344
66b7138f
JK		 345 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
346 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
347
348 /*
349 * For guest debugging where we have to reinject #BP if some
350 * INT3 is guest-owned:
351 * Emulate nRIP by moving RIP forward. Will fail if injection
352 * raises a fault that is not intercepted. Still better than
353 * failing in all cases.
354 */
355 skip_emulated_instruction(&svm->vcpu);
356 rip = kvm_rip_read(&svm->vcpu);
357 svm->int3_rip = rip + svm->vmcb->save.cs.base;
358 svm->int3_injected = rip - old_rip;
359 }
360
116a4752
JK		 361 svm->vmcb->control.event_inj = nr
362 | SVM_EVTINJ_VALID
363 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
364 | SVM_EVTINJ_TYPE_EXEPT;
365 svm->vmcb->control.event_inj_err = error_code;
366}
367
6aa8b732
AK		 368static int has_svm(void)
369{
63d1142f 370 const char *msg;
6aa8b732 371
63d1142f 372 if (!cpu_has_svm(&msg)) {
ff81ff10 373 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 374 return 0;
375 }
376
6aa8b732
AK		 377 return 1;
378}
379
380static void svm_hardware_disable(void *garbage)
381{
2c8dceeb 382 cpu_svm_disable();
6aa8b732
AK		 383}
384
10474ae8 385static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 386{
387
0fe1e009 388 struct svm_cpu_data *sd;
6aa8b732 389 uint64_t efer;
89a27f4d 390 struct desc_ptr gdt_descr;
6aa8b732
AK		 391 struct desc_struct *gdt;
392 int me = raw_smp_processor_id();
393
10474ae8
AG		 394 rdmsrl(MSR_EFER, efer);
395 if (efer & EFER_SVME)
396 return -EBUSY;
397
6aa8b732 398 if (!has_svm()) {
e6732a5a
ZA		 399 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
400 me);
10474ae8 401 return -EINVAL;
6aa8b732 402 }
0fe1e009 403 sd = per_cpu(svm_data, me);
6aa8b732 404
0fe1e009 405 if (!sd) {
e6732a5a 406 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 407 me);
10474ae8 408 return -EINVAL;
6aa8b732
AK		 409 }
410
0fe1e009
TH		 411 sd->asid_generation = 1;
412 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
413 sd->next_asid = sd->max_asid + 1;
6aa8b732 414
d6ab1ed4 415 native_store_gdt(&gdt_descr);
89a27f4d 416 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 417 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 418
9962d032 419 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 420
d0316554 421 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 422
423 return 0;
6aa8b732
AK		 424}
425
0da1db75
JR		 426static void svm_cpu_uninit(int cpu)
427{
0fe1e009 428 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 429
0fe1e009 430 if (!sd)
0da1db75
JR		 431 return;
432
433 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 434 __free_page(sd->save_area);
435 kfree(sd);
0da1db75
JR		 436}
437
6aa8b732
AK		 438static int svm_cpu_init(int cpu)
439{
0fe1e009 440 struct svm_cpu_data *sd;
6aa8b732
AK		 441 int r;
442
0fe1e009
TH		 443 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
444 if (!sd)
6aa8b732 445 return -ENOMEM;
0fe1e009
TH		 446 sd->cpu = cpu;
447 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 448 r = -ENOMEM;
0fe1e009 449 if (!sd->save_area)
6aa8b732
AK		 450 goto err_1;
451
0fe1e009 452 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 453
454 return 0;
455
456err_1:
0fe1e009 457 kfree(sd);
6aa8b732
AK		 458 return r;
459
460}
461
ac72a9b7
JR		 462static bool valid_msr_intercept(u32 index)
463{
464 int i;
465
466 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
467 if (direct_access_msrs[i].index == index)
468 return true;
469
470 return false;
471}
472
bfc733a7
RR		 473static void set_msr_interception(u32 *msrpm, unsigned msr,
474 int read, int write)
6aa8b732 475{
455716fa
JR		 476 u8 bit_read, bit_write;
477 unsigned long tmp;
478 u32 offset;
6aa8b732 479
ac72a9b7
JR		 480 /*
481 * If this warning triggers extend the direct_access_msrs list at the
482 * beginning of the file
483 */
484 WARN_ON(!valid_msr_intercept(msr));
485
455716fa
JR		 486 offset = svm_msrpm_offset(msr);
487 bit_read = 2 * (msr & 0x0f);
488 bit_write = 2 * (msr & 0x0f) + 1;
489 tmp = msrpm[offset];
490
491 BUG_ON(offset == MSR_INVALID);
492
493 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
494 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
495
496 msrpm[offset] = tmp;
6aa8b732
AK		 497}
498
f65c229c
JR		 499static void svm_vcpu_init_msrpm(u32 *msrpm)
500{
ac72a9b7
JR		 501 int i;
502
f65c229c
JR		 503 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
504
ac72a9b7
JR		 505 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
506 if (!direct_access_msrs[i].always)
507 continue;
508
509 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
510 }
f65c229c
JR		 511}
512
24e09cbf
JR		 513static void svm_enable_lbrv(struct vcpu_svm *svm)
514{
515 u32 *msrpm = svm->msrpm;
516
517 svm->vmcb->control.lbr_ctl = 1;
518 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
519 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
520 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
521 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
522}
523
524static void svm_disable_lbrv(struct vcpu_svm *svm)
525{
526 u32 *msrpm = svm->msrpm;
527
528 svm->vmcb->control.lbr_ctl = 0;
529 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
530 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
531 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
532 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
533}
534
6aa8b732
AK		 535static __init int svm_hardware_setup(void)
536{
537 int cpu;
538 struct page *iopm_pages;
f65c229c 539 void *iopm_va;
6aa8b732
AK		 540 int r;
541
6aa8b732
AK		 542 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
543
544 if (!iopm_pages)
545 return -ENOMEM;
c8681339
AL		 546
547 iopm_va = page_address(iopm_pages);
548 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 549 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
550
50a37eb4
JR		 551 if (boot_cpu_has(X86_FEATURE_NX))
552 kvm_enable_efer_bits(EFER_NX);
553
1b2fd70c
AG		 554 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
555 kvm_enable_efer_bits(EFER_FFXSR);
556
236de055
AG		 557 if (nested) {
558 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
559 kvm_enable_efer_bits(EFER_SVME);
560 }
561
3230bb47 562 for_each_possible_cpu(cpu) {
6aa8b732
AK		 563 r = svm_cpu_init(cpu);
564 if (r)
f65c229c 565 goto err;
6aa8b732 566 }
33bd6a0b
JR		 567
568 svm_features = cpuid_edx(SVM_CPUID_FUNC);
569
e3da3acd
JR		 570 if (!svm_has(SVM_FEATURE_NPT))
571 npt_enabled = false;
572
6c7dac72
JR		 573 if (npt_enabled && !npt) {
574 printk(KERN_INFO "kvm: Nested Paging disabled\n");
575 npt_enabled = false;
576 }
577
18552672 578 if (npt_enabled) {
e3da3acd 579 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 580 kvm_enable_tdp();
5f4cb662
JR		 581 } else
582 kvm_disable_tdp();
e3da3acd 583
6aa8b732
AK		 584 return 0;
585
f65c229c 586err:
6aa8b732
AK		 587 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
588 iopm_base = 0;
589 return r;
590}
591
592static __exit void svm_hardware_unsetup(void)
593{
0da1db75
JR		 594 int cpu;
595
3230bb47 596 for_each_possible_cpu(cpu)
0da1db75
JR		 597 svm_cpu_uninit(cpu);
598
6aa8b732 599 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 600 iopm_base = 0;
6aa8b732
AK		 601}
602
603static void init_seg(struct vmcb_seg *seg)
604{
605 seg->selector = 0;
606 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 607 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 608 seg->limit = 0xffff;
609 seg->base = 0;
610}
611
612static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
613{
614 seg->selector = 0;
615 seg->attrib = SVM_SELECTOR_P_MASK | type;
616 seg->limit = 0xffff;
617 seg->base = 0;
618}
619
e6101a96 620static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 621{
e6101a96
JR		 622 struct vmcb_control_area *control = &svm->vmcb->control;
623 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 624
bff78274
AK		 625 svm->vcpu.fpu_active = 1;
626
e0231715 627 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 628 INTERCEPT_CR3_MASK |
649d6864 629 INTERCEPT_CR4_MASK;
6aa8b732 630
e0231715 631 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 632 INTERCEPT_CR3_MASK |
80a8119c
AK		 633 INTERCEPT_CR4_MASK |
634 INTERCEPT_CR8_MASK;
6aa8b732 635
e0231715 636 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 637 INTERCEPT_DR1_MASK |
638 INTERCEPT_DR2_MASK |
727f5a23
JK		 639 INTERCEPT_DR3_MASK |
640 INTERCEPT_DR4_MASK |
641 INTERCEPT_DR5_MASK |
642 INTERCEPT_DR6_MASK |
643 INTERCEPT_DR7_MASK;
6aa8b732 644
e0231715 645 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 646 INTERCEPT_DR1_MASK |
647 INTERCEPT_DR2_MASK |
648 INTERCEPT_DR3_MASK |
727f5a23 649 INTERCEPT_DR4_MASK |
6aa8b732 650 INTERCEPT_DR5_MASK |
727f5a23 651 INTERCEPT_DR6_MASK |
6aa8b732
AK		 652 INTERCEPT_DR7_MASK;
653
7aa81cc0 654 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 655 (1 << UD_VECTOR) |
656 (1 << MC_VECTOR);
6aa8b732
AK		 657
658
e0231715 659 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 660 (1ULL << INTERCEPT_NMI) |
0152527b 661 (1ULL << INTERCEPT_SMI) |
d225157b 662 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 663 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 664 (1ULL << INTERCEPT_INVD) |
6aa8b732 665 (1ULL << INTERCEPT_HLT) |
a7052897 666 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 667 (1ULL << INTERCEPT_INVLPGA) |
668 (1ULL << INTERCEPT_IOIO_PROT) |
669 (1ULL << INTERCEPT_MSR_PROT) |
670 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 671 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 672 (1ULL << INTERCEPT_VMRUN) |
673 (1ULL << INTERCEPT_VMMCALL) |
674 (1ULL << INTERCEPT_VMLOAD) |
675 (1ULL << INTERCEPT_VMSAVE) |
676 (1ULL << INTERCEPT_STGI) |
677 (1ULL << INTERCEPT_CLGI) |
916ce236 678 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 679 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 680 (1ULL << INTERCEPT_MONITOR) |
681 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 682
683 control->iopm_base_pa = iopm_base;
f65c229c 684 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 685 control->tsc_offset = 0;
6aa8b732
AK		 686 control->int_ctl = V_INTR_MASKING_MASK;
687
688 init_seg(&save->es);
689 init_seg(&save->ss);
690 init_seg(&save->ds);
691 init_seg(&save->fs);
692 init_seg(&save->gs);
693
694 save->cs.selector = 0xf000;
695 /* Executable/Readable Code Segment */
696 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
697 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
698 save->cs.limit = 0xffff;
d92899a0
AK		 699 /*
700 * cs.base should really be 0xffff0000, but vmx can't handle that, so
701 * be consistent with it.
702 *
703 * Replace when we have real mode working for vmx.
704 */
705 save->cs.base = 0xf0000;
6aa8b732
AK		 706
707 save->gdtr.limit = 0xffff;
708 save->idtr.limit = 0xffff;
709
710 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
711 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
712
9962d032 713 save->efer = EFER_SVME;
d77c26fc 714 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 715 save->dr7 = 0x400;
716 save->rflags = 2;
717 save->rip = 0x0000fff0;
5fdbf976 718 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 719
e0231715
JR		 720 /*
721 * This is the guest-visible cr0 value.
18fa000a 722 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 723 */
18fa000a
EH		 724 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
725 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
726
66aee91a 727 save->cr4 = X86_CR4_PAE;
6aa8b732 728 /* rdx = ?? */
709ddebf
JR		 729
730 if (npt_enabled) {
731 /* Setup VMCB for Nested Paging */
732 control->nested_ctl = 1;
a7052897
MT		 733 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
734 (1ULL << INTERCEPT_INVLPG));
709ddebf 735 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 736 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
737 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 738 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 739 save->cr3 = 0;
740 save->cr4 = 0;
741 }
a79d2f18 742 force_new_asid(&svm->vcpu);
1371d904 743
e6aa9abd 744 svm->nested.vmcb = 0;
2af9194d
JR		 745 svm->vcpu.arch.hflags = 0;
746
565d0998
ML		 747 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
748 control->pause_filter_count = 3000;
749 control->intercept |= (1ULL << INTERCEPT_PAUSE);
750 }
751
2af9194d 752 enable_gif(svm);
6aa8b732
AK		 753}
754
e00c8cf2 755static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 756{
757 struct vcpu_svm *svm = to_svm(vcpu);
758
e6101a96 759 init_vmcb(svm);
70433389 760
c5af89b6 761 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 762 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 763 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
764 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 765 }
5fdbf976
MT		 766 vcpu->arch.regs_avail = ~0;
767 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 768
769 return 0;
04d2cc77
AK		 770}
771
fb3f0f51 772static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 773{
a2fa3e9f 774 struct vcpu_svm *svm;
6aa8b732 775 struct page *page;
f65c229c 776 struct page *msrpm_pages;
b286d5d8 777 struct page *hsave_page;
3d6368ef 778 struct page *nested_msrpm_pages;
fb3f0f51 779 int err;
6aa8b732 780
c16f862d 781 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 782 if (!svm) {
783 err = -ENOMEM;
784 goto out;
785 }
786
787 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
788 if (err)
789 goto free_svm;
790
b7af4043 791 err = -ENOMEM;
6aa8b732 792 page = alloc_page(GFP_KERNEL);
b7af4043 793 if (!page)
fb3f0f51 794 goto uninit;
6aa8b732 795
f65c229c
JR		 796 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
797 if (!msrpm_pages)
b7af4043 798 goto free_page1;
3d6368ef
AG		 799
800 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
801 if (!nested_msrpm_pages)
b7af4043 802 goto free_page2;
f65c229c 803
b286d5d8
AG		 804 hsave_page = alloc_page(GFP_KERNEL);
805 if (!hsave_page)
b7af4043
TY		 806 goto free_page3;
807
e6aa9abd 808 svm->nested.hsave = page_address(hsave_page);
b286d5d8 809
b7af4043
TY		 810 svm->msrpm = page_address(msrpm_pages);
811 svm_vcpu_init_msrpm(svm->msrpm);
812
e6aa9abd 813 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 814
a2fa3e9f
GH		 815 svm->vmcb = page_address(page);
816 clear_page(svm->vmcb);
817 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
818 svm->asid_generation = 0;
e6101a96 819 init_vmcb(svm);
a2fa3e9f 820
fb3f0f51 821 fx_init(&svm->vcpu);
ad312c7c 822 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 823 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 824 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 825
fb3f0f51 826 return &svm->vcpu;
36241b8c 827
b7af4043
TY		 828free_page3:
829 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
830free_page2:
831 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
832free_page1:
833 __free_page(page);
fb3f0f51
RR		 834uninit:
835 kvm_vcpu_uninit(&svm->vcpu);
836free_svm:
a4770347 837 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 838out:
839 return ERR_PTR(err);
6aa8b732
AK		 840}
841
842static void svm_free_vcpu(struct kvm_vcpu *vcpu)
843{
a2fa3e9f
GH		 844 struct vcpu_svm *svm = to_svm(vcpu);
845
fb3f0f51 846 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 847 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 848 __free_page(virt_to_page(svm->nested.hsave));
849 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 850 kvm_vcpu_uninit(vcpu);
a4770347 851 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 852}
853
15ad7146 854static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 855{
a2fa3e9f 856 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 857 int i;
0cc5064d 858
0cc5064d 859 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 860 u64 delta;
0cc5064d 861
953899b6
JR		 862 if (check_tsc_unstable()) {
863 /*
864 * Make sure that the guest sees a monotonically
865 * increasing TSC.
866 */
867 delta = vcpu->arch.host_tsc - native_read_tsc();
868 svm->vmcb->control.tsc_offset += delta;
869 if (is_nested(svm))
870 svm->nested.hsave->control.tsc_offset += delta;
871 }
0cc5064d 872 vcpu->cpu = cpu;
2f599714 873 kvm_migrate_timers(vcpu);
4b656b12 874 svm->asid_generation = 0;
0cc5064d 875 }
94dfbdb3
AL		 876
877 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 878 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 879}
880
881static void svm_vcpu_put(struct kvm_vcpu *vcpu)
882{
a2fa3e9f 883 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 884 int i;
885
e1beb1d3 886 ++vcpu->stat.host_state_reload;
94dfbdb3 887 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 888 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 889
e935d48e 890 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 891}
892
6aa8b732
AK		 893static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
894{
a2fa3e9f 895 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 896}
897
898static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
899{
a2fa3e9f 900 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 901}
902
6de4f3ad
AK		 903static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
904{
905 switch (reg) {
906 case VCPU_EXREG_PDPTR:
907 BUG_ON(!npt_enabled);
908 load_pdptrs(vcpu, vcpu->arch.cr3);
909 break;
910 default:
911 BUG();
912 }
913}
914
f0b85051
AG		 915static void svm_set_vintr(struct vcpu_svm *svm)
916{
917 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
918}
919
920static void svm_clear_vintr(struct vcpu_svm *svm)
921{
922 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
923}
924
6aa8b732
AK		 925static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
926{
a2fa3e9f 927 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 928
929 switch (seg) {
930 case VCPU_SREG_CS: return &save->cs;
931 case VCPU_SREG_DS: return &save->ds;
932 case VCPU_SREG_ES: return &save->es;
933 case VCPU_SREG_FS: return &save->fs;
934 case VCPU_SREG_GS: return &save->gs;
935 case VCPU_SREG_SS: return &save->ss;
936 case VCPU_SREG_TR: return &save->tr;
937 case VCPU_SREG_LDTR: return &save->ldtr;
938 }
939 BUG();
8b6d44c7 940 return NULL;
6aa8b732
AK		 941}
942
943static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
944{
945 struct vmcb_seg *s = svm_seg(vcpu, seg);
946
947 return s->base;
948}
949
950static void svm_get_segment(struct kvm_vcpu *vcpu,
951 struct kvm_segment *var, int seg)
952{
953 struct vmcb_seg *s = svm_seg(vcpu, seg);
954
955 var->base = s->base;
956 var->limit = s->limit;
957 var->selector = s->selector;
958 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
959 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
960 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
961 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
962 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
963 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
964 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
965 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 966
e0231715
JR		 967 /*
968 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 969 * for cross vendor migration purposes by "not present"
970 */
971 var->unusable = !var->present || (var->type == 0);
972
1fbdc7a5
AP		 973 switch (seg) {
974 case VCPU_SREG_CS:
975 /*
976 * SVM always stores 0 for the 'G' bit in the CS selector in
977 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
978 * Intel's VMENTRY has a check on the 'G' bit.
979 */
25022acc 980 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 981 break;
982 case VCPU_SREG_TR:
983 /*
984 * Work around a bug where the busy flag in the tr selector
985 * isn't exposed
986 */
c0d09828 987 var->type |= 0x2;
1fbdc7a5
AP		 988 break;
989 case VCPU_SREG_DS:
990 case VCPU_SREG_ES:
991 case VCPU_SREG_FS:
992 case VCPU_SREG_GS:
993 /*
994 * The accessed bit must always be set in the segment
995 * descriptor cache, although it can be cleared in the
996 * descriptor, the cached bit always remains at 1. Since
997 * Intel has a check on this, set it here to support
998 * cross-vendor migration.
999 */
1000 if (!var->unusable)
1001 var->type |= 0x1;
1002 break;
b586eb02 1003 case VCPU_SREG_SS:
e0231715
JR		 1004 /*
1005 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1006 * descriptor is left as 1, although the whole segment has
1007 * been made unusable. Clear it here to pass an Intel VMX
1008 * entry check when cross vendor migrating.
1009 */
1010 if (var->unusable)
1011 var->db = 0;
1012 break;
1fbdc7a5 1013 }
6aa8b732
AK		 1014}
1015
2e4d2653
IE		 1016static int svm_get_cpl(struct kvm_vcpu *vcpu)
1017{
1018 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1019
1020 return save->cpl;
1021}
1022
89a27f4d 1023static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1024{
a2fa3e9f
GH		 1025 struct vcpu_svm *svm = to_svm(vcpu);
1026
89a27f4d
GN		 1027 dt->size = svm->vmcb->save.idtr.limit;
1028 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1029}
1030
89a27f4d 1031static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1032{
a2fa3e9f
GH		 1033 struct vcpu_svm *svm = to_svm(vcpu);
1034
89a27f4d
GN		 1035 svm->vmcb->save.idtr.limit = dt->size;
1036 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1037}
1038
89a27f4d 1039static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1040{
a2fa3e9f
GH		 1041 struct vcpu_svm *svm = to_svm(vcpu);
1042
89a27f4d
GN		 1043 dt->size = svm->vmcb->save.gdtr.limit;
1044 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1045}
1046
89a27f4d 1047static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1048{
a2fa3e9f
GH		 1049 struct vcpu_svm *svm = to_svm(vcpu);
1050
89a27f4d
GN		 1051 svm->vmcb->save.gdtr.limit = dt->size;
1052 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1053}
1054
e8467fda
AK		 1055static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1056{
1057}
1058
25c4c276 1059static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1060{
1061}
1062
d225157b
AK		 1063static void update_cr0_intercept(struct vcpu_svm *svm)
1064{
66a562f7 1065 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1066 ulong gcr0 = svm->vcpu.arch.cr0;
1067 u64 *hcr0 = &svm->vmcb->save.cr0;
1068
1069 if (!svm->vcpu.fpu_active)
1070 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1071 else
1072 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1073 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1074
1075
1076 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1077 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1078 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1079 if (is_nested(svm)) {
1080 struct vmcb *hsave = svm->nested.hsave;
1081
1082 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1083 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1084 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1085 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1086 }
d225157b
AK		 1087 } else {
1088 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1089 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1090 if (is_nested(svm)) {
1091 struct vmcb *hsave = svm->nested.hsave;
1092
1093 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1094 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1095 }
d225157b
AK		 1096 }
1097}
1098
6aa8b732
AK		 1099static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1100{
a2fa3e9f
GH		 1101 struct vcpu_svm *svm = to_svm(vcpu);
1102
7f5d8b56
JR		 1103 if (is_nested(svm)) {
1104 /*
1105 * We are here because we run in nested mode, the host kvm
1106 * intercepts cr0 writes but the l1 hypervisor does not.
1107 * But the L1 hypervisor may intercept selective cr0 writes.
1108 * This needs to be checked here.
1109 */
1110 unsigned long old, new;
1111
1112 /* Remove bits that would trigger a real cr0 write intercept */
1113 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1114 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1115
1116 if (old == new) {
1117 /* cr0 write with ts and mp unchanged */
1118 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1119 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1120 return;
1121 }
1122 }
1123
05b3e0c2 1124#ifdef CONFIG_X86_64
f6801dff 1125 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1126 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1127 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1128 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1129 }
1130
d77c26fc 1131 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1132 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1133 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1134 }
1135 }
1136#endif
ad312c7c 1137 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1138
1139 if (!npt_enabled)
1140 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1141
1142 if (!vcpu->fpu_active)
334df50a 1143 cr0 |= X86_CR0_TS;
709ddebf
JR		 1144 /*
1145 * re-enable caching here because the QEMU bios
1146 * does not do it - this results in some delay at
1147 * reboot
1148 */
1149 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1150 svm->vmcb->save.cr0 = cr0;
d225157b 1151 update_cr0_intercept(svm);
6aa8b732
AK		 1152}
1153
1154static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1155{
6394b649 1156 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1157 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1158
1159 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1160 force_new_asid(vcpu);
6394b649 1161
ec077263
JR		 1162 vcpu->arch.cr4 = cr4;
1163 if (!npt_enabled)
1164 cr4 |= X86_CR4_PAE;
6394b649 1165 cr4 |= host_cr4_mce;
ec077263 1166 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1167}
1168
1169static void svm_set_segment(struct kvm_vcpu *vcpu,
1170 struct kvm_segment *var, int seg)
1171{
a2fa3e9f 1172 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1173 struct vmcb_seg *s = svm_seg(vcpu, seg);
1174
1175 s->base = var->base;
1176 s->limit = var->limit;
1177 s->selector = var->selector;
1178 if (var->unusable)
1179 s->attrib = 0;
1180 else {
1181 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1182 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1183 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1184 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1185 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1186 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1187 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1188 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1189 }
1190 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1191 svm->vmcb->save.cpl
1192 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1193 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1194
1195}
1196
44c11430 1197static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1198{
d0bfb940
JK		 1199 struct vcpu_svm *svm = to_svm(vcpu);
1200
d0bfb940
JK		 1201 svm->vmcb->control.intercept_exceptions &=
1202 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1203
6be7d306 1204 if (svm->nmi_singlestep)
44c11430
GN		 1205 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1206
d0bfb940
JK		 1207 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1208 if (vcpu->guest_debug &
1209 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1210 svm->vmcb->control.intercept_exceptions |=
1211 1 << DB_VECTOR;
1212 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1213 svm->vmcb->control.intercept_exceptions |=
1214 1 << BP_VECTOR;
1215 } else
1216 vcpu->guest_debug = 0;
44c11430
GN		 1217}
1218
355be0b9 1219static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1220{
44c11430
GN		 1221 struct vcpu_svm *svm = to_svm(vcpu);
1222
ae675ef0
JK		 1223 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1224 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1225 else
1226 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1227
355be0b9 1228 update_db_intercept(vcpu);
6aa8b732
AK		 1229}
1230
1231static void load_host_msrs(struct kvm_vcpu *vcpu)
1232{
94dfbdb3 1233#ifdef CONFIG_X86_64
a2fa3e9f 1234 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1235#endif
6aa8b732
AK		 1236}
1237
1238static void save_host_msrs(struct kvm_vcpu *vcpu)
1239{
94dfbdb3 1240#ifdef CONFIG_X86_64
a2fa3e9f 1241 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1242#endif
6aa8b732
AK		 1243}
1244
0fe1e009 1245static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1246{
0fe1e009
TH		 1247 if (sd->next_asid > sd->max_asid) {
1248 ++sd->asid_generation;
1249 sd->next_asid = 1;
a2fa3e9f 1250 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1251 }
1252
0fe1e009
TH		 1253 svm->asid_generation = sd->asid_generation;
1254 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1255}
1256
c76de350 1257static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
6aa8b732 1258{
42dbaa5a 1259 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a
JK		 1260
1261 switch (dr) {
1262 case 0 ... 3:
c76de350 1263 *dest = vcpu->arch.db[dr];
42dbaa5a 1264 break;
c76de350
JK		 1265 case 4:
1266 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1267 return EMULATE_FAIL; /* will re-inject UD */
1268 /* fall through */
42dbaa5a
JK		 1269 case 6:
1270 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1271 *dest = vcpu->arch.dr6;
42dbaa5a 1272 else
c76de350 1273 *dest = svm->vmcb->save.dr6;
42dbaa5a 1274 break;
c76de350
JK		 1275 case 5:
1276 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1277 return EMULATE_FAIL; /* will re-inject UD */
1278 /* fall through */
42dbaa5a
JK		 1279 case 7:
1280 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1281 *dest = vcpu->arch.dr7;
42dbaa5a 1282 else
c76de350 1283 *dest = svm->vmcb->save.dr7;
42dbaa5a 1284 break;
42dbaa5a
JK		 1285 }
1286
c76de350 1287 return EMULATE_DONE;
6aa8b732
AK		 1288}
1289
c76de350 1290static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
6aa8b732 1291{
a2fa3e9f
GH		 1292 struct vcpu_svm *svm = to_svm(vcpu);
1293
6aa8b732
AK		 1294 switch (dr) {
1295 case 0 ... 3:
42dbaa5a
JK		 1296 vcpu->arch.db[dr] = value;
1297 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1298 vcpu->arch.eff_db[dr] = value;
c76de350
JK		 1299 break;
1300 case 4:
1301 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1302 return EMULATE_FAIL; /* will re-inject UD */
1303 /* fall through */
42dbaa5a 1304 case 6:
42dbaa5a 1305 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
c76de350
JK		 1306 break;
1307 case 5:
1308 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1309 return EMULATE_FAIL; /* will re-inject UD */
1310 /* fall through */
42dbaa5a 1311 case 7:
42dbaa5a
JK		 1312 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1313 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1314 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1315 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1316 }
c76de350 1317 break;
6aa8b732 1318 }
c76de350
JK		 1319
1320 return EMULATE_DONE;
6aa8b732
AK		 1321}
1322
851ba692 1323static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1324{
6aa8b732
AK		 1325 u64 fault_address;
1326 u32 error_code;
6aa8b732 1327
a2fa3e9f
GH		 1328 fault_address = svm->vmcb->control.exit_info_2;
1329 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1330
229456fc 1331 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1332 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1333 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1334 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1335}
1336
851ba692 1337static int db_interception(struct vcpu_svm *svm)
d0bfb940 1338{
851ba692
AK		 1339 struct kvm_run *kvm_run = svm->vcpu.run;
1340
d0bfb940 1341 if (!(svm->vcpu.guest_debug &
44c11430 1342 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1343 !svm->nmi_singlestep) {
d0bfb940
JK		 1344 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1345 return 1;
1346 }
44c11430 1347
6be7d306
JK		 1348 if (svm->nmi_singlestep) {
1349 svm->nmi_singlestep = false;
44c11430
GN		 1350 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1351 svm->vmcb->save.rflags &=
1352 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1353 update_db_intercept(&svm->vcpu);
1354 }
1355
1356 if (svm->vcpu.guest_debug &
e0231715 1357 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1358 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1359 kvm_run->debug.arch.pc =
1360 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1361 kvm_run->debug.arch.exception = DB_VECTOR;
1362 return 0;
1363 }
1364
1365 return 1;
d0bfb940
JK		 1366}
1367
851ba692 1368static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1369{
851ba692
AK		 1370 struct kvm_run *kvm_run = svm->vcpu.run;
1371
d0bfb940
JK		 1372 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1373 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1374 kvm_run->debug.arch.exception = BP_VECTOR;
1375 return 0;
1376}
1377
851ba692 1378static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1379{
1380 int er;
1381
851ba692 1382 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1383 if (er != EMULATE_DONE)
7ee5d940 1384 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1385 return 1;
1386}
1387
6b52d186 1388static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1389{
6b52d186 1390 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1391 u32 excp;
1392
1393 if (is_nested(svm)) {
1394 u32 h_excp, n_excp;
1395
1396 h_excp = svm->nested.hsave->control.intercept_exceptions;
1397 n_excp = svm->nested.intercept_exceptions;
1398 h_excp &= ~(1 << NM_VECTOR);
1399 excp = h_excp | n_excp;
1400 } else {
1401 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1402 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1403 }
1404
1405 svm->vmcb->control.intercept_exceptions = excp;
1406
e756fc62 1407 svm->vcpu.fpu_active = 1;
d225157b 1408 update_cr0_intercept(svm);
6b52d186 1409}
a2fa3e9f 1410
6b52d186
AK		 1411static int nm_interception(struct vcpu_svm *svm)
1412{
1413 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1414 return 1;
7807fa6c
AL		 1415}
1416
851ba692 1417static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1418{
1419 /*
1420 * On an #MC intercept the MCE handler is not called automatically in
1421 * the host. So do it by hand here.
1422 */
1423 asm volatile (
1424 "int $0x12\n");
1425 /* not sure if we ever come back to this point */
1426
1427 return 1;
1428}
1429
851ba692 1430static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1431{
851ba692
AK		 1432 struct kvm_run *kvm_run = svm->vcpu.run;
1433
46fe4ddd
JR		 1434 /*
1435 * VMCB is undefined after a SHUTDOWN intercept
1436 * so reinitialize it.
1437 */
a2fa3e9f 1438 clear_page(svm->vmcb);
e6101a96 1439 init_vmcb(svm);
46fe4ddd
JR		 1440
1441 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1442 return 0;
1443}
1444
851ba692 1445static int io_interception(struct vcpu_svm *svm)
6aa8b732 1446{
d77c26fc 1447 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1448 int size, in, string;
039576c0 1449 unsigned port;
6aa8b732 1450
e756fc62 1451 ++svm->vcpu.stat.io_exits;
6aa8b732 1452
a2fa3e9f 1453 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1454
e70669ab
LV		 1455 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1456
1457 if (string) {
3427318f 1458 if (emulate_instruction(&svm->vcpu,
851ba692 1459 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1460 return 0;
1461 return 1;
1462 }
1463
039576c0
AK		 1464 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1465 port = io_info >> 16;
1466 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1467
e93f36bc 1468 skip_emulated_instruction(&svm->vcpu);
851ba692 1469 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1470}
1471
851ba692 1472static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1473{
1474 return 1;
1475}
1476
851ba692 1477static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1478{
1479 ++svm->vcpu.stat.irq_exits;
1480 return 1;
1481}
1482
851ba692 1483static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1484{
1485 return 1;
1486}
1487
851ba692 1488static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1489{
5fdbf976 1490 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1491 skip_emulated_instruction(&svm->vcpu);
1492 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1493}
1494
851ba692 1495static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1496{
5fdbf976 1497 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1498 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1499 kvm_emulate_hypercall(&svm->vcpu);
1500 return 1;
02e235bc
AK		 1501}
1502
c0725420
AG		 1503static int nested_svm_check_permissions(struct vcpu_svm *svm)
1504{
f6801dff 1505 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1506 || !is_paging(&svm->vcpu)) {
1507 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1508 return 1;
1509 }
1510
1511 if (svm->vmcb->save.cpl) {
1512 kvm_inject_gp(&svm->vcpu, 0);
1513 return 1;
1514 }
1515
1516 return 0;
1517}
1518
cf74a78b
AG		 1519static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1520 bool has_error_code, u32 error_code)
1521{
b8e88bc8
JR		 1522 int vmexit;
1523
0295ad7d
JR		 1524 if (!is_nested(svm))
1525 return 0;
cf74a78b 1526
0295ad7d
JR		 1527 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1528 svm->vmcb->control.exit_code_hi = 0;
1529 svm->vmcb->control.exit_info_1 = error_code;
1530 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1531
b8e88bc8
JR		 1532 vmexit = nested_svm_intercept(svm);
1533 if (vmexit == NESTED_EXIT_DONE)
1534 svm->nested.exit_required = true;
1535
1536 return vmexit;
cf74a78b
AG		 1537}
1538
8fe54654
JR		 1539/* This function returns true if it is save to enable the irq window */
1540static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1541{
26666957 1542 if (!is_nested(svm))
8fe54654 1543 return true;
cf74a78b 1544
26666957 1545 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1546 return true;
cf74a78b 1547
26666957 1548 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1549 return false;
cf74a78b 1550
197717d5
JR		 1551 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1552 svm->vmcb->control.exit_info_1 = 0;
1553 svm->vmcb->control.exit_info_2 = 0;
26666957 1554
cd3ff653
JR		 1555 if (svm->nested.intercept & 1ULL) {
1556 /*
1557 * The #vmexit can't be emulated here directly because this
1558 * code path runs with irqs and preemtion disabled. A
1559 * #vmexit emulation might sleep. Only signal request for
1560 * the #vmexit here.
1561 */
1562 svm->nested.exit_required = true;
236649de 1563 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1564 return false;
cf74a78b
AG		 1565 }
1566
8fe54654 1567 return true;
cf74a78b
AG		 1568}
1569
887f500c
JR		 1570/* This function returns true if it is save to enable the nmi window */
1571static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1572{
1573 if (!is_nested(svm))
1574 return true;
1575
1576 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1577 return true;
1578
1579 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1580 svm->nested.exit_required = true;
1581
1582 return false;
1583}
1584
7597f129 1585static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1586{
1587 struct page *page;
1588
6c3bd3d7
JR		 1589 might_sleep();
1590
34f80cfa 1591 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1592 if (is_error_page(page))
1593 goto error;
1594
7597f129
JR		 1595 *_page = page;
1596
1597 return kmap(page);
34f80cfa
JR		 1598
1599error:
1600 kvm_release_page_clean(page);
1601 kvm_inject_gp(&svm->vcpu, 0);
1602
1603 return NULL;
1604}
1605
7597f129 1606static void nested_svm_unmap(struct page *page)
34f80cfa 1607{
7597f129 1608 kunmap(page);
34f80cfa
JR		 1609 kvm_release_page_dirty(page);
1610}
1611
d2477826 1612static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1613{
4c2161ae 1614 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa 1615 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3d62d9aa 1616 u32 t0, t1;
d2477826 1617 int ret;
4c7da8cb 1618 u8 val;
4c2161ae 1619
3d62d9aa 1620 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1621 return NESTED_EXIT_HOST;
3d62d9aa 1622
4c2161ae
JR		 1623 switch (msr) {
1624 case 0 ... 0x1fff:
1625 t0 = (msr * 2) % 8;
1626 t1 = msr / 8;
1627 break;
1628 case 0xc0000000 ... 0xc0001fff:
1629 t0 = (8192 + msr - 0xc0000000) * 2;
1630 t1 = (t0 / 8);
1631 t0 %= 8;
1632 break;
1633 case 0xc0010000 ... 0xc0011fff:
1634 t0 = (16384 + msr - 0xc0010000) * 2;
1635 t1 = (t0 / 8);
1636 t0 %= 8;
1637 break;
1638 default:
d2477826 1639 ret = NESTED_EXIT_DONE;
3d62d9aa 1640 goto out;
4c2161ae 1641 }
4c2161ae 1642
4c7da8cb 1643 if (!kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + t1, &val, 1))
d2477826 1644 ret = val & ((1 << param) << t0) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3d62d9aa
JR		 1645
1646out:
3d62d9aa 1647 return ret;
4c2161ae
JR		 1648}
1649
410e4d57 1650static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1651{
cf74a78b 1652 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1653
410e4d57
JR		 1654 switch (exit_code) {
1655 case SVM_EXIT_INTR:
1656 case SVM_EXIT_NMI:
1657 return NESTED_EXIT_HOST;
410e4d57 1658 case SVM_EXIT_NPF:
e0231715 1659 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1660 if (npt_enabled)
1661 return NESTED_EXIT_HOST;
1662 break;
410e4d57 1663 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1664 /* When we're shadowing, trap PFs */
410e4d57
JR		 1665 if (!npt_enabled)
1666 return NESTED_EXIT_HOST;
1667 break;
66a562f7
JR		 1668 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1669 nm_interception(svm);
1670 break;
410e4d57
JR		 1671 default:
1672 break;
cf74a78b
AG		 1673 }
1674
410e4d57
JR		 1675 return NESTED_EXIT_CONTINUE;
1676}
1677
1678/*
1679 * If this function returns true, this #vmexit was already handled
1680 */
b8e88bc8 1681static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1682{
1683 u32 exit_code = svm->vmcb->control.exit_code;
1684 int vmexit = NESTED_EXIT_HOST;
1685
cf74a78b 1686 switch (exit_code) {
9c4e40b9 1687 case SVM_EXIT_MSR:
3d62d9aa 1688 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1689 break;
cf74a78b
AG		 1690 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1691 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1692 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1693 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1694 break;
1695 }
1696 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1697 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1698 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1699 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1700 break;
1701 }
1702 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1703 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1704 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1705 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1706 break;
1707 }
1708 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1709 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1710 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1711 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1712 break;
1713 }
1714 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1715 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1716 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1717 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1718 break;
1719 }
1720 default: {
1721 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1722 if (svm->nested.intercept & exit_bits)
410e4d57 1723 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1724 }
1725 }
1726
b8e88bc8
JR		 1727 return vmexit;
1728}
1729
1730static int nested_svm_exit_handled(struct vcpu_svm *svm)
1731{
1732 int vmexit;
1733
1734 vmexit = nested_svm_intercept(svm);
1735
1736 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1737 nested_svm_vmexit(svm);
9c4e40b9
JR		 1738
1739 return vmexit;
cf74a78b
AG		 1740}
1741
0460a979
JR		 1742static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1743{
1744 struct vmcb_control_area *dst = &dst_vmcb->control;
1745 struct vmcb_control_area *from = &from_vmcb->control;
1746
1747 dst->intercept_cr_read = from->intercept_cr_read;
1748 dst->intercept_cr_write = from->intercept_cr_write;
1749 dst->intercept_dr_read = from->intercept_dr_read;
1750 dst->intercept_dr_write = from->intercept_dr_write;
1751 dst->intercept_exceptions = from->intercept_exceptions;
1752 dst->intercept = from->intercept;
1753 dst->iopm_base_pa = from->iopm_base_pa;
1754 dst->msrpm_base_pa = from->msrpm_base_pa;
1755 dst->tsc_offset = from->tsc_offset;
1756 dst->asid = from->asid;
1757 dst->tlb_ctl = from->tlb_ctl;
1758 dst->int_ctl = from->int_ctl;
1759 dst->int_vector = from->int_vector;
1760 dst->int_state = from->int_state;
1761 dst->exit_code = from->exit_code;
1762 dst->exit_code_hi = from->exit_code_hi;
1763 dst->exit_info_1 = from->exit_info_1;
1764 dst->exit_info_2 = from->exit_info_2;
1765 dst->exit_int_info = from->exit_int_info;
1766 dst->exit_int_info_err = from->exit_int_info_err;
1767 dst->nested_ctl = from->nested_ctl;
1768 dst->event_inj = from->event_inj;
1769 dst->event_inj_err = from->event_inj_err;
1770 dst->nested_cr3 = from->nested_cr3;
1771 dst->lbr_ctl = from->lbr_ctl;
1772}
1773
34f80cfa 1774static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1775{
34f80cfa 1776 struct vmcb *nested_vmcb;
e6aa9abd 1777 struct vmcb *hsave = svm->nested.hsave;
33740e40 1778 struct vmcb *vmcb = svm->vmcb;
7597f129 1779 struct page *page;
cf74a78b 1780
17897f36
JR		 1781 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1782 vmcb->control.exit_info_1,
1783 vmcb->control.exit_info_2,
1784 vmcb->control.exit_int_info,
1785 vmcb->control.exit_int_info_err);
1786
7597f129 1787 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1788 if (!nested_vmcb)
1789 return 1;
1790
06fc7772
JR		 1791 /* Exit nested SVM mode */
1792 svm->nested.vmcb = 0;
1793
cf74a78b 1794 /* Give the current vmcb to the guest */
33740e40
JR		 1795 disable_gif(svm);
1796
1797 nested_vmcb->save.es = vmcb->save.es;
1798 nested_vmcb->save.cs = vmcb->save.cs;
1799 nested_vmcb->save.ss = vmcb->save.ss;
1800 nested_vmcb->save.ds = vmcb->save.ds;
1801 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1802 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1803 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
33740e40
JR		 1804 if (npt_enabled)
1805 nested_vmcb->save.cr3 = vmcb->save.cr3;
cdbbdc12
JR		 1806 else
1807 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1808 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1809 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1810 nested_vmcb->save.rflags = vmcb->save.rflags;
1811 nested_vmcb->save.rip = vmcb->save.rip;
1812 nested_vmcb->save.rsp = vmcb->save.rsp;
1813 nested_vmcb->save.rax = vmcb->save.rax;
1814 nested_vmcb->save.dr7 = vmcb->save.dr7;
1815 nested_vmcb->save.dr6 = vmcb->save.dr6;
1816 nested_vmcb->save.cpl = vmcb->save.cpl;
1817
1818 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1819 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1820 nested_vmcb->control.int_state = vmcb->control.int_state;
1821 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1822 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1823 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1824 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1825 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1826 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1827
1828 /*
1829 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1830 * to make sure that we do not lose injected events. So check event_inj
1831 * here and copy it to exit_int_info if it is valid.
1832 * Exit_int_info and event_inj can't be both valid because the case
1833 * below only happens on a VMRUN instruction intercept which has
1834 * no valid exit_int_info set.
1835 */
1836 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1837 struct vmcb_control_area *nc = &nested_vmcb->control;
1838
1839 nc->exit_int_info = vmcb->control.event_inj;
1840 nc->exit_int_info_err = vmcb->control.event_inj_err;
1841 }
1842
33740e40
JR		 1843 nested_vmcb->control.tlb_ctl = 0;
1844 nested_vmcb->control.event_inj = 0;
1845 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1846
1847 /* We always set V_INTR_MASKING and remember the old value in hflags */
1848 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1849 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1850
cf74a78b 1851 /* Restore the original control entries */
0460a979 1852 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1853
219b65dc
AG		 1854 kvm_clear_exception_queue(&svm->vcpu);
1855 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1856
1857 /* Restore selected save entries */
1858 svm->vmcb->save.es = hsave->save.es;
1859 svm->vmcb->save.cs = hsave->save.cs;
1860 svm->vmcb->save.ss = hsave->save.ss;
1861 svm->vmcb->save.ds = hsave->save.ds;
1862 svm->vmcb->save.gdtr = hsave->save.gdtr;
1863 svm->vmcb->save.idtr = hsave->save.idtr;
1864 svm->vmcb->save.rflags = hsave->save.rflags;
1865 svm_set_efer(&svm->vcpu, hsave->save.efer);
1866 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1867 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1868 if (npt_enabled) {
1869 svm->vmcb->save.cr3 = hsave->save.cr3;
1870 svm->vcpu.arch.cr3 = hsave->save.cr3;
1871 } else {
1872 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1873 }
1874 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1875 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1876 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1877 svm->vmcb->save.dr7 = 0;
1878 svm->vmcb->save.cpl = 0;
1879 svm->vmcb->control.exit_int_info = 0;
1880
7597f129 1881 nested_svm_unmap(page);
cf74a78b
AG		 1882
1883 kvm_mmu_reset_context(&svm->vcpu);
1884 kvm_mmu_load(&svm->vcpu);
1885
1886 return 0;
1887}
3d6368ef 1888
9738b2c9 1889static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1890{
9738b2c9 1891 u32 *nested_msrpm;
7597f129 1892 struct page *page;
3d6368ef 1893 int i;
9738b2c9 1894
7597f129 1895 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
9738b2c9
JR		 1896 if (!nested_msrpm)
1897 return false;
1898
e0231715 1899 for (i = 0; i < PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1900 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1901
e6aa9abd 1902 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1903
7597f129 1904 nested_svm_unmap(page);
9738b2c9
JR		 1905
1906 return true;
3d6368ef
AG		 1907}
1908
9738b2c9 1909static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1910{
9738b2c9 1911 struct vmcb *nested_vmcb;
e6aa9abd 1912 struct vmcb *hsave = svm->nested.hsave;
defbba56 1913 struct vmcb *vmcb = svm->vmcb;
7597f129 1914 struct page *page;
06fc7772
JR		 1915 u64 vmcb_gpa;
1916
1917 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 1918
7597f129 1919 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 1920 if (!nested_vmcb)
1921 return false;
1922
ecf1405d 1923 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
0ac406de
JR		 1924 nested_vmcb->save.rip,
1925 nested_vmcb->control.int_ctl,
1926 nested_vmcb->control.event_inj,
1927 nested_vmcb->control.nested_ctl);
1928
2e554e8d
JR		 1929 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
1930 nested_vmcb->control.intercept_cr_write,
1931 nested_vmcb->control.intercept_exceptions,
1932 nested_vmcb->control.intercept);
1933
3d6368ef 1934 /* Clear internal status */
219b65dc
AG		 1935 kvm_clear_exception_queue(&svm->vcpu);
1936 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 1937
e0231715
JR		 1938 /*
1939 * Save the old vmcb, so we don't need to pick what we save, but can
1940 * restore everything when a VMEXIT occurs
1941 */
defbba56
JR		 1942 hsave->save.es = vmcb->save.es;
1943 hsave->save.cs = vmcb->save.cs;
1944 hsave->save.ss = vmcb->save.ss;
1945 hsave->save.ds = vmcb->save.ds;
1946 hsave->save.gdtr = vmcb->save.gdtr;
1947 hsave->save.idtr = vmcb->save.idtr;
f6801dff 1948 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 1949 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1950 hsave->save.cr4 = svm->vcpu.arch.cr4;
1951 hsave->save.rflags = vmcb->save.rflags;
1952 hsave->save.rip = svm->next_rip;
1953 hsave->save.rsp = vmcb->save.rsp;
1954 hsave->save.rax = vmcb->save.rax;
1955 if (npt_enabled)
1956 hsave->save.cr3 = vmcb->save.cr3;
1957 else
1958 hsave->save.cr3 = svm->vcpu.arch.cr3;
1959
0460a979 1960 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1961
1962 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1963 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1964 else
1965 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1966
1967 /* Load the nested guest state */
1968 svm->vmcb->save.es = nested_vmcb->save.es;
1969 svm->vmcb->save.cs = nested_vmcb->save.cs;
1970 svm->vmcb->save.ss = nested_vmcb->save.ss;
1971 svm->vmcb->save.ds = nested_vmcb->save.ds;
1972 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1973 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1974 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1975 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1976 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1977 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1978 if (npt_enabled) {
1979 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1980 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 1981 } else
3d6368ef 1982 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 1983
1984 /* Guest paging mode is active - reset mmu */
1985 kvm_mmu_reset_context(&svm->vcpu);
1986
defbba56 1987 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1988 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1989 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1990 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 1991
3d6368ef
AG		 1992 /* In case we don't even reach vcpu_run, the fields are not updated */
1993 svm->vmcb->save.rax = nested_vmcb->save.rax;
1994 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1995 svm->vmcb->save.rip = nested_vmcb->save.rip;
1996 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1997 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1998 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1999
e6aa9abd 2000 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 2001
aad42c64
JR		 2002 /* cache intercepts */
2003 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2004 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2005 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2006 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2007 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2008 svm->nested.intercept = nested_vmcb->control.intercept;
2009
3d6368ef 2010 force_new_asid(&svm->vcpu);
3d6368ef 2011 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2012 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2013 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2014 else
2015 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2016
88ab24ad
JR		 2017 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2018 /* We only want the cr8 intercept bits of the guest */
2019 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2020 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2021 }
2022
e0231715
JR		 2023 /*
2024 * We don't want a nested guest to be more powerful than the guest, so
2025 * all intercepts are ORed
2026 */
88ab24ad
JR		 2027 svm->vmcb->control.intercept_cr_read |=
2028 nested_vmcb->control.intercept_cr_read;
2029 svm->vmcb->control.intercept_cr_write |=
2030 nested_vmcb->control.intercept_cr_write;
2031 svm->vmcb->control.intercept_dr_read |=
2032 nested_vmcb->control.intercept_dr_read;
2033 svm->vmcb->control.intercept_dr_write |=
2034 nested_vmcb->control.intercept_dr_write;
2035 svm->vmcb->control.intercept_exceptions |=
2036 nested_vmcb->control.intercept_exceptions;
2037
2038 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2039
2040 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2041 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2042 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2043 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2044 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2045 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2046
7597f129 2047 nested_svm_unmap(page);
9738b2c9 2048
06fc7772
JR		 2049 /* nested_vmcb is our indicator if nested SVM is activated */
2050 svm->nested.vmcb = vmcb_gpa;
2051
2af9194d 2052 enable_gif(svm);
3d6368ef 2053
9738b2c9 2054 return true;
3d6368ef
AG		 2055}
2056
9966bf68 2057static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2058{
2059 to_vmcb->save.fs = from_vmcb->save.fs;
2060 to_vmcb->save.gs = from_vmcb->save.gs;
2061 to_vmcb->save.tr = from_vmcb->save.tr;
2062 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2063 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2064 to_vmcb->save.star = from_vmcb->save.star;
2065 to_vmcb->save.lstar = from_vmcb->save.lstar;
2066 to_vmcb->save.cstar = from_vmcb->save.cstar;
2067 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2068 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2069 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2070 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2071}
2072
851ba692 2073static int vmload_interception(struct vcpu_svm *svm)
5542675b 2074{
9966bf68 2075 struct vmcb *nested_vmcb;
7597f129 2076 struct page *page;
9966bf68 2077
5542675b
AG		 2078 if (nested_svm_check_permissions(svm))
2079 return 1;
2080
2081 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2082 skip_emulated_instruction(&svm->vcpu);
2083
7597f129 2084 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2085 if (!nested_vmcb)
2086 return 1;
2087
2088 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2089 nested_svm_unmap(page);
5542675b
AG		 2090
2091 return 1;
2092}
2093
851ba692 2094static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2095{
9966bf68 2096 struct vmcb *nested_vmcb;
7597f129 2097 struct page *page;
9966bf68 2098
5542675b
AG		 2099 if (nested_svm_check_permissions(svm))
2100 return 1;
2101
2102 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2103 skip_emulated_instruction(&svm->vcpu);
2104
7597f129 2105 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2106 if (!nested_vmcb)
2107 return 1;
2108
2109 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2110 nested_svm_unmap(page);
5542675b
AG		 2111
2112 return 1;
2113}
2114
851ba692 2115static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2116{
3d6368ef
AG		 2117 if (nested_svm_check_permissions(svm))
2118 return 1;
2119
2120 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2121 skip_emulated_instruction(&svm->vcpu);
2122
9738b2c9 2123 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2124 return 1;
2125
9738b2c9 2126 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2127 goto failed;
2128
2129 return 1;
2130
2131failed:
2132
2133 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2134 svm->vmcb->control.exit_code_hi = 0;
2135 svm->vmcb->control.exit_info_1 = 0;
2136 svm->vmcb->control.exit_info_2 = 0;
2137
2138 nested_svm_vmexit(svm);
3d6368ef
AG		 2139
2140 return 1;
2141}
2142
851ba692 2143static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2144{
2145 if (nested_svm_check_permissions(svm))
2146 return 1;
2147
2148 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2149 skip_emulated_instruction(&svm->vcpu);
2150
2af9194d 2151 enable_gif(svm);
1371d904
AG		 2152
2153 return 1;
2154}
2155
851ba692 2156static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2157{
2158 if (nested_svm_check_permissions(svm))
2159 return 1;
2160
2161 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2162 skip_emulated_instruction(&svm->vcpu);
2163
2af9194d 2164 disable_gif(svm);
1371d904
AG		 2165
2166 /* After a CLGI no interrupts should come */
2167 svm_clear_vintr(svm);
2168 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2169
2170 return 1;
2171}
2172
851ba692 2173static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2174{
2175 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2176
ec1ff790
JR		 2177 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2178 vcpu->arch.regs[VCPU_REGS_RAX]);
2179
ff092385
AG		 2180 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2181 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2182
2183 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2184 skip_emulated_instruction(&svm->vcpu);
2185 return 1;
2186}
2187
532a46b9
JR		 2188static int skinit_interception(struct vcpu_svm *svm)
2189{
2190 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2191
2192 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2193 return 1;
2194}
2195
851ba692 2196static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2197{
7ee5d940 2198 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2199 return 1;
2200}
2201
851ba692 2202static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2203{
37817f29 2204 u16 tss_selector;
64a7ec06
GN		 2205 int reason;
2206 int int_type = svm->vmcb->control.exit_int_info &
2207 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2208 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2209 uint32_t type =
2210 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2211 uint32_t idt_v =
2212 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2213
2214 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2215
37817f29
IE		 2216 if (svm->vmcb->control.exit_info_2 &
2217 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2218 reason = TASK_SWITCH_IRET;
2219 else if (svm->vmcb->control.exit_info_2 &
2220 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2221 reason = TASK_SWITCH_JMP;
fe8e7f83 2222 else if (idt_v)
64a7ec06
GN		 2223 reason = TASK_SWITCH_GATE;
2224 else
2225 reason = TASK_SWITCH_CALL;
2226
fe8e7f83
GN		 2227 if (reason == TASK_SWITCH_GATE) {
2228 switch (type) {
2229 case SVM_EXITINTINFO_TYPE_NMI:
2230 svm->vcpu.arch.nmi_injected = false;
2231 break;
2232 case SVM_EXITINTINFO_TYPE_EXEPT:
2233 kvm_clear_exception_queue(&svm->vcpu);
2234 break;
2235 case SVM_EXITINTINFO_TYPE_INTR:
2236 kvm_clear_interrupt_queue(&svm->vcpu);
2237 break;
2238 default:
2239 break;
2240 }
2241 }
64a7ec06 2242
8317c298
GN		 2243 if (reason != TASK_SWITCH_GATE ||
2244 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2245 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2246 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2247 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2248
2249 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2250}
2251
851ba692 2252static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2253{
5fdbf976 2254 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2255 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2256 return 1;
6aa8b732
AK		 2257}
2258
851ba692 2259static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2260{
2261 ++svm->vcpu.stat.nmi_window_exits;
2262 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2263 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2264 return 1;
2265}
2266
851ba692 2267static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2268{
851ba692 2269 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2270 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2271 return 1;
2272}
2273
851ba692 2274static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2275{
851ba692 2276 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2277 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2278 return 1;
2279}
2280
851ba692 2281static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2282{
851ba692
AK		 2283 struct kvm_run *kvm_run = svm->vcpu.run;
2284
0a5fff19
GN		 2285 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2286 /* instruction emulation calls kvm_set_cr8() */
851ba692 2287 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2288 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2289 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2290 return 1;
95ba8273 2291 }
0a5fff19
GN		 2292 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2293 return 1;
1d075434
JR		 2294 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2295 return 0;
2296}
2297
6aa8b732
AK		 2298static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2299{
a2fa3e9f
GH		 2300 struct vcpu_svm *svm = to_svm(vcpu);
2301
6aa8b732 2302 switch (ecx) {
af24a4e4 2303 case MSR_IA32_TSC: {
20824f30 2304 u64 tsc_offset;
6aa8b732 2305
20824f30
JR		 2306 if (is_nested(svm))
2307 tsc_offset = svm->nested.hsave->control.tsc_offset;
2308 else
2309 tsc_offset = svm->vmcb->control.tsc_offset;
2310
2311 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2312 break;
2313 }
0e859cac 2314 case MSR_K6_STAR:
a2fa3e9f 2315 *data = svm->vmcb->save.star;
6aa8b732 2316 break;
0e859cac 2317#ifdef CONFIG_X86_64
6aa8b732 2318 case MSR_LSTAR:
a2fa3e9f 2319 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2320 break;
2321 case MSR_CSTAR:
a2fa3e9f 2322 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2323 break;
2324 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2325 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2326 break;
2327 case MSR_SYSCALL_MASK:
a2fa3e9f 2328 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2329 break;
2330#endif
2331 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2332 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2333 break;
2334 case MSR_IA32_SYSENTER_EIP:
017cb99e 2335 *data = svm->sysenter_eip;
6aa8b732
AK		 2336 break;
2337 case MSR_IA32_SYSENTER_ESP:
017cb99e 2338 *data = svm->sysenter_esp;
6aa8b732 2339 break;
e0231715
JR		 2340 /*
2341 * Nobody will change the following 5 values in the VMCB so we can
2342 * safely return them on rdmsr. They will always be 0 until LBRV is
2343 * implemented.
2344 */
a2938c80
JR		 2345 case MSR_IA32_DEBUGCTLMSR:
2346 *data = svm->vmcb->save.dbgctl;
2347 break;
2348 case MSR_IA32_LASTBRANCHFROMIP:
2349 *data = svm->vmcb->save.br_from;
2350 break;
2351 case MSR_IA32_LASTBRANCHTOIP:
2352 *data = svm->vmcb->save.br_to;
2353 break;
2354 case MSR_IA32_LASTINTFROMIP:
2355 *data = svm->vmcb->save.last_excp_from;
2356 break;
2357 case MSR_IA32_LASTINTTOIP:
2358 *data = svm->vmcb->save.last_excp_to;
2359 break;
b286d5d8 2360 case MSR_VM_HSAVE_PA:
e6aa9abd 2361 *data = svm->nested.hsave_msr;
b286d5d8 2362 break;
eb6f302e 2363 case MSR_VM_CR:
4a810181 2364 *data = svm->nested.vm_cr_msr;
eb6f302e 2365 break;
c8a73f18
AG		 2366 case MSR_IA32_UCODE_REV:
2367 *data = 0x01000065;
2368 break;
6aa8b732 2369 default:
3bab1f5d 2370 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2371 }
2372 return 0;
2373}
2374
851ba692 2375static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2376{
ad312c7c 2377 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2378 u64 data;
2379
59200273
AK		 2380 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2381 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2382 kvm_inject_gp(&svm->vcpu, 0);
59200273 2383 } else {
229456fc 2384 trace_kvm_msr_read(ecx, data);
af9ca2d7 2385
5fdbf976 2386 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2387 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2388 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2389 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2390 }
2391 return 1;
2392}
2393
4a810181
JR		 2394static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2395{
2396 struct vcpu_svm *svm = to_svm(vcpu);
2397 int svm_dis, chg_mask;
2398
2399 if (data & ~SVM_VM_CR_VALID_MASK)
2400 return 1;
2401
2402 chg_mask = SVM_VM_CR_VALID_MASK;
2403
2404 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2405 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2406
2407 svm->nested.vm_cr_msr &= ~chg_mask;
2408 svm->nested.vm_cr_msr |= (data & chg_mask);
2409
2410 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2411
2412 /* check for svm_disable while efer.svme is set */
2413 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2414 return 1;
2415
2416 return 0;
2417}
2418
6aa8b732
AK		 2419static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2420{
a2fa3e9f
GH		 2421 struct vcpu_svm *svm = to_svm(vcpu);
2422
6aa8b732 2423 switch (ecx) {
af24a4e4 2424 case MSR_IA32_TSC: {
20824f30
JR		 2425 u64 tsc_offset = data - native_read_tsc();
2426 u64 g_tsc_offset = 0;
2427
2428 if (is_nested(svm)) {
2429 g_tsc_offset = svm->vmcb->control.tsc_offset -
2430 svm->nested.hsave->control.tsc_offset;
2431 svm->nested.hsave->control.tsc_offset = tsc_offset;
2432 }
2433
2434 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2435
6aa8b732
AK		 2436 break;
2437 }
0e859cac 2438 case MSR_K6_STAR:
a2fa3e9f 2439 svm->vmcb->save.star = data;
6aa8b732 2440 break;
49b14f24 2441#ifdef CONFIG_X86_64
6aa8b732 2442 case MSR_LSTAR:
a2fa3e9f 2443 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2444 break;
2445 case MSR_CSTAR:
a2fa3e9f 2446 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2447 break;
2448 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2449 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2450 break;
2451 case MSR_SYSCALL_MASK:
a2fa3e9f 2452 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2453 break;
2454#endif
2455 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2456 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2457 break;
2458 case MSR_IA32_SYSENTER_EIP:
017cb99e 2459 svm->sysenter_eip = data;
a2fa3e9f 2460 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2461 break;
2462 case MSR_IA32_SYSENTER_ESP:
017cb99e 2463 svm->sysenter_esp = data;
a2fa3e9f 2464 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2465 break;
a2938c80 2466 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2467 if (!svm_has(SVM_FEATURE_LBRV)) {
2468 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2469 __func__, data);
24e09cbf
JR		 2470 break;
2471 }
2472 if (data & DEBUGCTL_RESERVED_BITS)
2473 return 1;
2474
2475 svm->vmcb->save.dbgctl = data;
2476 if (data & (1ULL<<0))
2477 svm_enable_lbrv(svm);
2478 else
2479 svm_disable_lbrv(svm);
a2938c80 2480 break;
b286d5d8 2481 case MSR_VM_HSAVE_PA:
e6aa9abd 2482 svm->nested.hsave_msr = data;
62b9abaa 2483 break;
3c5d0a44 2484 case MSR_VM_CR:
4a810181 2485 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2486 case MSR_VM_IGNNE:
3c5d0a44
AG		 2487 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2488 break;
6aa8b732 2489 default:
3bab1f5d 2490 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2491 }
2492 return 0;
2493}
2494
851ba692 2495static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2496{
ad312c7c 2497 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2498 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2499 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2500
af9ca2d7 2501
5fdbf976 2502 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2503 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2504 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2505 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2506 } else {
2507 trace_kvm_msr_write(ecx, data);
e756fc62 2508 skip_emulated_instruction(&svm->vcpu);
59200273 2509 }
6aa8b732
AK		 2510 return 1;
2511}
2512
851ba692 2513static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2514{
e756fc62 2515 if (svm->vmcb->control.exit_info_1)
851ba692 2516 return wrmsr_interception(svm);
6aa8b732 2517 else
851ba692 2518 return rdmsr_interception(svm);
6aa8b732
AK		 2519}
2520
851ba692 2521static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2522{
851ba692
AK		 2523 struct kvm_run *kvm_run = svm->vcpu.run;
2524
f0b85051 2525 svm_clear_vintr(svm);
85f455f7 2526 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2527 /*
2528 * If the user space waits to inject interrupts, exit as soon as
2529 * possible
2530 */
8061823a
GN		 2531 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2532 kvm_run->request_interrupt_window &&
2533 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2534 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2535 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2536 return 0;
2537 }
2538
2539 return 1;
2540}
2541
565d0998
ML		 2542static int pause_interception(struct vcpu_svm *svm)
2543{
2544 kvm_vcpu_on_spin(&(svm->vcpu));
2545 return 1;
2546}
2547
851ba692 2548static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2549 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2550 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2551 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2552 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2553 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2554 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2555 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2556 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2557 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2558 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2559 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2560 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2561 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2562 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2563 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2564 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2565 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2566 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2567 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2568 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2569 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2570 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2571 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2572 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2573 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2574 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2575 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2576 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2577 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2578 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2579 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2580 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2581 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2582 [SVM_EXIT_SMI] = nop_on_interception,
2583 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2584 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2585 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2586 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2587 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2588 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2589 [SVM_EXIT_HLT] = halt_interception,
a7052897 2590 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2591 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2592 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2593 [SVM_EXIT_MSR] = msr_interception,
2594 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2595 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2596 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2597 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2598 [SVM_EXIT_VMLOAD] = vmload_interception,
2599 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2600 [SVM_EXIT_STGI] = stgi_interception,
2601 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2602 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2603 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2604 [SVM_EXIT_MONITOR] = invalid_op_interception,
2605 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2606 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2607};
2608
851ba692 2609static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2610{
04d2cc77 2611 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2612 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2613 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2614
229456fc 2615 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2616
cd3ff653
JR		 2617 if (unlikely(svm->nested.exit_required)) {
2618 nested_svm_vmexit(svm);
2619 svm->nested.exit_required = false;
2620
2621 return 1;
2622 }
2623
cf74a78b 2624 if (is_nested(svm)) {
410e4d57
JR		 2625 int vmexit;
2626
d8cabddf
JR		 2627 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2628 svm->vmcb->control.exit_info_1,
2629 svm->vmcb->control.exit_info_2,
2630 svm->vmcb->control.exit_int_info,
2631 svm->vmcb->control.exit_int_info_err);
2632
410e4d57
JR		 2633 vmexit = nested_svm_exit_special(svm);
2634
2635 if (vmexit == NESTED_EXIT_CONTINUE)
2636 vmexit = nested_svm_exit_handled(svm);
2637
2638 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2639 return 1;
cf74a78b
AG		 2640 }
2641
a5c3832d
JR		 2642 svm_complete_interrupts(svm);
2643
888f9f3e 2644 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2645 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2646 if (npt_enabled)
709ddebf 2647 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2648
2649 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2650 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2651 kvm_run->fail_entry.hardware_entry_failure_reason
2652 = svm->vmcb->control.exit_code;
2653 return 0;
2654 }
2655
a2fa3e9f 2656 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2657 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2658 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2659 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2660 "exit_code 0x%x\n",
b8688d51 2661 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2662 exit_code);
2663
9d8f549d 2664 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2665 || !svm_exit_handlers[exit_code]) {
6aa8b732 2666 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2667 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2668 return 0;
2669 }
2670
851ba692 2671 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2672}
2673
2674static void reload_tss(struct kvm_vcpu *vcpu)
2675{
2676 int cpu = raw_smp_processor_id();
2677
0fe1e009
TH		 2678 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2679 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2680 load_TR_desc();
2681}
2682
e756fc62 2683static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2684{
2685 int cpu = raw_smp_processor_id();
2686
0fe1e009 2687 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2688
a2fa3e9f 2689 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2690 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2691 if (svm->asid_generation != sd->asid_generation)
2692 new_asid(svm, sd);
6aa8b732
AK		 2693}
2694
95ba8273
GN		 2695static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2696{
2697 struct vcpu_svm *svm = to_svm(vcpu);
2698
2699 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2700 vcpu->arch.hflags |= HF_NMI_MASK;
2701 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2702 ++vcpu->stat.nmi_injections;
2703}
6aa8b732 2704
85f455f7 2705static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2706{
2707 struct vmcb_control_area *control;
2708
229456fc 2709 trace_kvm_inj_virq(irq);
af9ca2d7 2710
fa89a817 2711 ++svm->vcpu.stat.irq_injections;
e756fc62 2712 control = &svm->vmcb->control;
85f455f7 2713 control->int_vector = irq;
6aa8b732
AK		 2714 control->int_ctl &= ~V_INTR_PRIO_MASK;
2715 control->int_ctl |= V_IRQ_MASK |
2716 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2717}
2718
66fd3f7f 2719static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2720{
2721 struct vcpu_svm *svm = to_svm(vcpu);
2722
2af9194d 2723 BUG_ON(!(gif_set(svm)));
cf74a78b 2724
219b65dc
AG		 2725 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2726 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2727}
2728
95ba8273 2729static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2730{
2731 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2732
88ab24ad
JR		 2733 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2734 return;
2735
95ba8273 2736 if (irr == -1)
aaacfc9a
JR		 2737 return;
2738
95ba8273
GN		 2739 if (tpr >= irr)
2740 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2741}
aaacfc9a 2742
95ba8273
GN		 2743static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2744{
2745 struct vcpu_svm *svm = to_svm(vcpu);
2746 struct vmcb *vmcb = svm->vmcb;
2747 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2748 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2749}
2750
3cfc3092
JK		 2751static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2752{
2753 struct vcpu_svm *svm = to_svm(vcpu);
2754
2755 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2756}
2757
2758static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2759{
2760 struct vcpu_svm *svm = to_svm(vcpu);
2761
2762 if (masked) {
2763 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2764 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2765 } else {
2766 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2767 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2768 }
2769}
2770
78646121
GN		 2771static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2772{
2773 struct vcpu_svm *svm = to_svm(vcpu);
2774 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2775 int ret;
2776
2777 if (!gif_set(svm) ||
2778 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2779 return 0;
2780
2781 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2782
2783 if (is_nested(svm))
2784 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2785
2786 return ret;
78646121
GN		 2787}
2788
9222be18 2789static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2790{
219b65dc 2791 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 2792
e0231715
JR		 2793 /*
2794 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2795 * 1, because that's a separate STGI/VMRUN intercept. The next time we
2796 * get that intercept, this function will be called again though and
2797 * we'll get the vintr intercept.
2798 */
8fe54654 2799 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 2800 svm_set_vintr(svm);
2801 svm_inject_irq(svm, 0x0);
2802 }
85f455f7
ED		 2803}
2804
95ba8273 2805static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2806{
04d2cc77 2807 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2808
44c11430
GN		 2809 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2810 == HF_NMI_MASK)
2811 return; /* IRET will cause a vm exit */
2812
e0231715
JR		 2813 /*
2814 * Something prevents NMI from been injected. Single step over possible
2815 * problem (IRET or exception injection or interrupt shadow)
2816 */
887f500c
JR		 2817 if (gif_set(svm) && nested_svm_nmi(svm)) {
2818 svm->nmi_singlestep = true;
2819 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2820 update_db_intercept(vcpu);
2821 }
c1150d8c
DL		 2822}
2823
cbc94022
IE		 2824static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2825{
2826 return 0;
2827}
2828
d9e368d6
AK		 2829static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2830{
2831 force_new_asid(vcpu);
2832}
2833
04d2cc77
AK		 2834static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2835{
2836}
2837
d7bf8221
JR		 2838static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2839{
2840 struct vcpu_svm *svm = to_svm(vcpu);
2841
88ab24ad
JR		 2842 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2843 return;
2844
d7bf8221
JR		 2845 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2846 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2847 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2848 }
2849}
2850
649d6864
JR		 2851static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2852{
2853 struct vcpu_svm *svm = to_svm(vcpu);
2854 u64 cr8;
2855
88ab24ad
JR		 2856 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2857 return;
2858
649d6864
JR		 2859 cr8 = kvm_get_cr8(vcpu);
2860 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2861 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2862}
2863
9222be18
GN		 2864static void svm_complete_interrupts(struct vcpu_svm *svm)
2865{
2866 u8 vector;
2867 int type;
2868 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 2869 unsigned int3_injected = svm->int3_injected;
2870
2871 svm->int3_injected = 0;
9222be18 2872
44c11430
GN		 2873 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2874 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2875
9222be18
GN		 2876 svm->vcpu.arch.nmi_injected = false;
2877 kvm_clear_exception_queue(&svm->vcpu);
2878 kvm_clear_interrupt_queue(&svm->vcpu);
2879
2880 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2881 return;
2882
2883 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2884 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2885
2886 switch (type) {
2887 case SVM_EXITINTINFO_TYPE_NMI:
2888 svm->vcpu.arch.nmi_injected = true;
2889 break;
2890 case SVM_EXITINTINFO_TYPE_EXEPT:
219b65dc
AG		 2891 if (is_nested(svm))
2892 break;
66b7138f
JK		 2893 /*
2894 * In case of software exceptions, do not reinject the vector,
2895 * but re-execute the instruction instead. Rewind RIP first
2896 * if we emulated INT3 before.
2897 */
2898 if (kvm_exception_is_soft(vector)) {
2899 if (vector == BP_VECTOR && int3_injected &&
2900 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2901 kvm_rip_write(&svm->vcpu,
2902 kvm_rip_read(&svm->vcpu) -
2903 int3_injected);
9222be18 2904 break;
66b7138f 2905 }
9222be18
GN		 2906 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2907 u32 err = svm->vmcb->control.exit_int_info_err;
2908 kvm_queue_exception_e(&svm->vcpu, vector, err);
2909
2910 } else
2911 kvm_queue_exception(&svm->vcpu, vector);
2912 break;
2913 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2914 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2915 break;
2916 default:
2917 break;
2918 }
2919}
2920
80e31d4f
AK		 2921#ifdef CONFIG_X86_64
2922#define R "r"
2923#else
2924#define R "e"
2925#endif
2926
851ba692 2927static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2928{
a2fa3e9f 2929 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2930 u16 fs_selector;
2931 u16 gs_selector;
2932 u16 ldt_selector;
d9e368d6 2933
cd3ff653
JR		 2934 /*
2935 * A vmexit emulation is required before the vcpu can be executed
2936 * again.
2937 */
2938 if (unlikely(svm->nested.exit_required))
2939 return;
2940
5fdbf976
MT		 2941 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2942 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2943 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2944
e756fc62 2945 pre_svm_run(svm);
6aa8b732 2946
649d6864
JR		 2947 sync_lapic_to_cr8(vcpu);
2948
6aa8b732 2949 save_host_msrs(vcpu);
d6e88aec
AK		 2950 fs_selector = kvm_read_fs();
2951 gs_selector = kvm_read_gs();
2952 ldt_selector = kvm_read_ldt();
cda0ffdd 2953 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2954 /* required for live migration with NPT */
2955 if (npt_enabled)
2956 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2957
04d2cc77
AK		 2958 clgi();
2959
2960 local_irq_enable();
36241b8c 2961
6aa8b732 2962 asm volatile (
80e31d4f
AK		 2963 "push %%"R"bp; \n\t"
2964 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2965 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2966 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2967 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2968 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2969 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2970#ifdef CONFIG_X86_64
fb3f0f51
RR		 2971 "mov %c[r8](%[svm]), %%r8 \n\t"
2972 "mov %c[r9](%[svm]), %%r9 \n\t"
2973 "mov %c[r10](%[svm]), %%r10 \n\t"
2974 "mov %c[r11](%[svm]), %%r11 \n\t"
2975 "mov %c[r12](%[svm]), %%r12 \n\t"
2976 "mov %c[r13](%[svm]), %%r13 \n\t"
2977 "mov %c[r14](%[svm]), %%r14 \n\t"
2978 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2979#endif
2980
6aa8b732 2981 /* Enter guest mode */
80e31d4f
AK		 2982 "push %%"R"ax \n\t"
2983 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2984 __ex(SVM_VMLOAD) "\n\t"
2985 __ex(SVM_VMRUN) "\n\t"
2986 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2987 "pop %%"R"ax \n\t"
6aa8b732
AK		 2988
2989 /* Save guest registers, load host registers */
80e31d4f
AK		 2990 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2991 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2992 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2993 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2994 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2995 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2996#ifdef CONFIG_X86_64
fb3f0f51
RR		 2997 "mov %%r8, %c[r8](%[svm]) \n\t"
2998 "mov %%r9, %c[r9](%[svm]) \n\t"
2999 "mov %%r10, %c[r10](%[svm]) \n\t"
3000 "mov %%r11, %c[r11](%[svm]) \n\t"
3001 "mov %%r12, %c[r12](%[svm]) \n\t"
3002 "mov %%r13, %c[r13](%[svm]) \n\t"
3003 "mov %%r14, %c[r14](%[svm]) \n\t"
3004 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3005#endif
80e31d4f 3006 "pop %%"R"bp"
6aa8b732 3007 :
fb3f0f51 3008 : [svm]"a"(svm),
6aa8b732 3009 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3010 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3011 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3012 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3013 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3014 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3015 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3016#ifdef CONFIG_X86_64
ad312c7c
ZX		 3017 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3018 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3019 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3020 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3021 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3022 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3023 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3024 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3025#endif
54a08c04 3026 : "cc", "memory"
80e31d4f 3027 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3028#ifdef CONFIG_X86_64
54a08c04
LV		 3029 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3030#endif
3031 );
6aa8b732 3032
ad312c7c 3033 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3034 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3035 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3036 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3037
d6e88aec
AK		 3038 kvm_load_fs(fs_selector);
3039 kvm_load_gs(gs_selector);
3040 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3041 load_host_msrs(vcpu);
3042
3043 reload_tss(vcpu);
3044
56ba47dd
AK		 3045 local_irq_disable();
3046
3047 stgi();
3048
d7bf8221
JR		 3049 sync_cr8_to_lapic(vcpu);
3050
a2fa3e9f 3051 svm->next_rip = 0;
9222be18 3052
6de4f3ad
AK		 3053 if (npt_enabled) {
3054 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3055 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3056 }
6aa8b732
AK		 3057}
3058
80e31d4f
AK		 3059#undef R
3060
6aa8b732
AK		 3061static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3062{
a2fa3e9f
GH		 3063 struct vcpu_svm *svm = to_svm(vcpu);
3064
709ddebf
JR		 3065 if (npt_enabled) {
3066 svm->vmcb->control.nested_cr3 = root;
3067 force_new_asid(vcpu);
3068 return;
3069 }
3070
a2fa3e9f 3071 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3072 force_new_asid(vcpu);
3073}
3074
6aa8b732
AK		 3075static int is_disabled(void)
3076{
6031a61c
JR		 3077 u64 vm_cr;
3078
3079 rdmsrl(MSR_VM_CR, vm_cr);
3080 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3081 return 1;
3082
6aa8b732
AK		 3083 return 0;
3084}
3085
102d8325
IM		 3086static void
3087svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3088{
3089 /*
3090 * Patch in the VMMCALL instruction:
3091 */
3092 hypercall[0] = 0x0f;
3093 hypercall[1] = 0x01;
3094 hypercall[2] = 0xd9;
102d8325
IM		 3095}
3096
002c7f7c
YS		 3097static void svm_check_processor_compat(void *rtn)
3098{
3099 *(int *)rtn = 0;
3100}
3101
774ead3a
AK		 3102static bool svm_cpu_has_accelerated_tpr(void)
3103{
3104 return false;
3105}
3106
67253af5
SY		 3107static int get_npt_level(void)
3108{
3109#ifdef CONFIG_X86_64
3110 return PT64_ROOT_LEVEL;
3111#else
3112 return PT32E_ROOT_LEVEL;
3113#endif
3114}
3115
4b12f0de 3116static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3117{
3118 return 0;
3119}
3120
0e851880
SY		 3121static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3122{
3123}
3124
229456fc 3125static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3126 { SVM_EXIT_READ_CR0, "read_cr0" },
3127 { SVM_EXIT_READ_CR3, "read_cr3" },
3128 { SVM_EXIT_READ_CR4, "read_cr4" },
3129 { SVM_EXIT_READ_CR8, "read_cr8" },
3130 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3131 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3132 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3133 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3134 { SVM_EXIT_READ_DR0, "read_dr0" },
3135 { SVM_EXIT_READ_DR1, "read_dr1" },
3136 { SVM_EXIT_READ_DR2, "read_dr2" },
3137 { SVM_EXIT_READ_DR3, "read_dr3" },
3138 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3139 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3140 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3141 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3142 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3143 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3144 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3145 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3146 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3147 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3148 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3149 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3150 { SVM_EXIT_INTR, "interrupt" },
3151 { SVM_EXIT_NMI, "nmi" },
3152 { SVM_EXIT_SMI, "smi" },
3153 { SVM_EXIT_INIT, "init" },
3154 { SVM_EXIT_VINTR, "vintr" },
3155 { SVM_EXIT_CPUID, "cpuid" },
3156 { SVM_EXIT_INVD, "invd" },
3157 { SVM_EXIT_HLT, "hlt" },
3158 { SVM_EXIT_INVLPG, "invlpg" },
3159 { SVM_EXIT_INVLPGA, "invlpga" },
3160 { SVM_EXIT_IOIO, "io" },
3161 { SVM_EXIT_MSR, "msr" },
3162 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3163 { SVM_EXIT_SHUTDOWN, "shutdown" },
3164 { SVM_EXIT_VMRUN, "vmrun" },
3165 { SVM_EXIT_VMMCALL, "hypercall" },
3166 { SVM_EXIT_VMLOAD, "vmload" },
3167 { SVM_EXIT_VMSAVE, "vmsave" },
3168 { SVM_EXIT_STGI, "stgi" },
3169 { SVM_EXIT_CLGI, "clgi" },
3170 { SVM_EXIT_SKINIT, "skinit" },
3171 { SVM_EXIT_WBINVD, "wbinvd" },
3172 { SVM_EXIT_MONITOR, "monitor" },
3173 { SVM_EXIT_MWAIT, "mwait" },
3174 { SVM_EXIT_NPF, "npf" },
3175 { -1, NULL }
3176};
3177
17cc3935 3178static int svm_get_lpage_level(void)
344f414f 3179{
17cc3935 3180 return PT_PDPE_LEVEL;
344f414f
JR		 3181}
3182
4e47c7a6
SY		 3183static bool svm_rdtscp_supported(void)
3184{
3185 return false;
3186}
3187
02daab21
AK		 3188static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3189{
3190 struct vcpu_svm *svm = to_svm(vcpu);
3191
02daab21 3192 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3193 if (is_nested(svm))
3194 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3195 update_cr0_intercept(svm);
02daab21
AK		 3196}
3197
cbdd1bea 3198static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3199 .cpu_has_kvm_support = has_svm,
3200 .disabled_by_bios = is_disabled,
3201 .hardware_setup = svm_hardware_setup,
3202 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3203 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3204 .hardware_enable = svm_hardware_enable,
3205 .hardware_disable = svm_hardware_disable,
774ead3a 3206 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3207
3208 .vcpu_create = svm_create_vcpu,
3209 .vcpu_free = svm_free_vcpu,
04d2cc77 3210 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3211
04d2cc77 3212 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3213 .vcpu_load = svm_vcpu_load,
3214 .vcpu_put = svm_vcpu_put,
3215
3216 .set_guest_debug = svm_guest_debug,
3217 .get_msr = svm_get_msr,
3218 .set_msr = svm_set_msr,
3219 .get_segment_base = svm_get_segment_base,
3220 .get_segment = svm_get_segment,
3221 .set_segment = svm_set_segment,
2e4d2653 3222 .get_cpl = svm_get_cpl,
1747fb71 3223 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3224 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3225 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3226 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3227 .set_cr3 = svm_set_cr3,
3228 .set_cr4 = svm_set_cr4,
3229 .set_efer = svm_set_efer,
3230 .get_idt = svm_get_idt,
3231 .set_idt = svm_set_idt,
3232 .get_gdt = svm_get_gdt,
3233 .set_gdt = svm_set_gdt,
3234 .get_dr = svm_get_dr,
3235 .set_dr = svm_set_dr,
6de4f3ad 3236 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3237 .get_rflags = svm_get_rflags,
3238 .set_rflags = svm_set_rflags,
6b52d186 3239 .fpu_activate = svm_fpu_activate,
02daab21 3240 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3241
6aa8b732 3242 .tlb_flush = svm_flush_tlb,
6aa8b732 3243
6aa8b732 3244 .run = svm_vcpu_run,
04d2cc77 3245 .handle_exit = handle_exit,
6aa8b732 3246 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3247 .set_interrupt_shadow = svm_set_interrupt_shadow,
3248 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3249 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3250 .set_irq = svm_set_irq,
95ba8273 3251 .set_nmi = svm_inject_nmi,
298101da 3252 .queue_exception = svm_queue_exception,
78646121 3253 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3254 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3255 .get_nmi_mask = svm_get_nmi_mask,
3256 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3257 .enable_nmi_window = enable_nmi_window,
3258 .enable_irq_window = enable_irq_window,
3259 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3260
3261 .set_tss_addr = svm_set_tss_addr,
67253af5 3262 .get_tdp_level = get_npt_level,
4b12f0de 3263 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3264
3265 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3266 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3267
3268 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3269
3270 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3271};
3272
3273static int __init svm_init(void)
3274{
cb498ea2 3275 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3276 THIS_MODULE);
6aa8b732
AK		 3277}
3278
3279static void __exit svm_exit(void)
3280{
cb498ea2 3281 kvm_exit();
6aa8b732
AK		 3282}
3283
3284module_init(svm_init)
3285module_exit(svm_exit)
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