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KVM: VMX: Report unexpected simultaneous exceptions as internal errors
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
13673a90 34#include <asm/vmx.h>
6210e37b 35#include <asm/virtext.h>
a0861c02 36#include <asm/mce.h>
6aa8b732 37
229456fc
MT		 38#include "trace.h"
39
4ecac3fd
AK		 40#define __ex(x) __kvm_handle_fault_on_reboot(x)
41
6aa8b732
AK		 42MODULE_AUTHOR("Qumranet");
43MODULE_LICENSE("GPL");
44
4462d21a 45static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 46module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 47
4462d21a 48static int __read_mostly enable_vpid = 1;
736caefe 49module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 50
4462d21a 51static int __read_mostly flexpriority_enabled = 1;
736caefe 52module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 53
4462d21a 54static int __read_mostly enable_ept = 1;
736caefe 55module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 56
3a624e29
NK		 57static int __read_mostly enable_unrestricted_guest = 1;
58module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
4462d21a 61static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 62module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 63
4b8d54f9
ZE		 64/*
65 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
66 * ple_gap: upper bound on the amount of time between two successive
67 * executions of PAUSE in a loop. Also indicate if ple enabled.
68 * According to test, this time is usually small than 41 cycles.
69 * ple_window: upper bound on the amount of time a guest is allowed to execute
70 * in a PAUSE loop. Tests indicate that most spinlocks are held for
71 * less than 2^12 cycles
72 * Time is measured based on a counter that runs at the same rate as the TSC,
73 * refer SDM volume 3b section 21.6.13 & 22.1.3.
74 */
75#define KVM_VMX_DEFAULT_PLE_GAP 41
76#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
77static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
78module_param(ple_gap, int, S_IRUGO);
79
80static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
81module_param(ple_window, int, S_IRUGO);
82
a2fa3e9f
GH		 83struct vmcs {
84 u32 revision_id;
85 u32 abort;
86 char data[0];
87};
88
26bb0981
AK		 89struct shared_msr_entry {
90 unsigned index;
91 u64 data;
92};
93
a2fa3e9f 94struct vcpu_vmx {
fb3f0f51 95 struct kvm_vcpu vcpu;
543e4243 96 struct list_head local_vcpus_link;
313dbd49 97 unsigned long host_rsp;
a2fa3e9f 98 int launched;
29bd8a78 99 u8 fail;
1155f76a 100 u32 idt_vectoring_info;
26bb0981 101 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 102 int nmsrs;
103 int save_nmsrs;
a2fa3e9f 104#ifdef CONFIG_X86_64
44ea2b17
AK		 105 u64 msr_host_kernel_gs_base;
106 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 107#endif
108 struct vmcs *vmcs;
109 struct {
110 int loaded;
111 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 112 int gs_ldt_reload_needed;
113 int fs_reload_needed;
d77c26fc 114 } host_state;
9c8cba37 115 struct {
7ffd92c5
AK		 116 int vm86_active;
117 u8 save_iopl;
118 struct kvm_save_segment {
119 u16 selector;
120 unsigned long base;
121 u32 limit;
122 u32 ar;
123 } tr, es, ds, fs, gs;
9c8cba37
AK		 124 struct {
125 bool pending;
126 u8 vector;
127 unsigned rip;
128 } irq;
129 } rmode;
2384d2b3 130 int vpid;
04fa4d32 131 bool emulation_required;
3b86cd99
JK		 132
133 /* Support for vnmi-less CPUs */
134 int soft_vnmi_blocked;
135 ktime_t entry_time;
136 s64 vnmi_blocked_time;
a0861c02 137 u32 exit_reason;
a2fa3e9f
GH		 138};
139
140static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
141{
fb3f0f51 142 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 143}
144
b7ebfb05 145static int init_rmode(struct kvm *kvm);
4e1096d2 146static u64 construct_eptp(unsigned long root_hpa);
75880a01 147
6aa8b732
AK		 148static DEFINE_PER_CPU(struct vmcs *, vmxarea);
149static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 150static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 151
3e7c73e9
AK		 152static unsigned long *vmx_io_bitmap_a;
153static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 154static unsigned long *vmx_msr_bitmap_legacy;
155static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 156
2384d2b3
SY		 157static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
158static DEFINE_SPINLOCK(vmx_vpid_lock);
159
1c3d14fe 160static struct vmcs_config {
6aa8b732
AK		 161 int size;
162 int order;
163 u32 revision_id;
1c3d14fe
YS		 164 u32 pin_based_exec_ctrl;
165 u32 cpu_based_exec_ctrl;
f78e0e2e 166 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 167 u32 vmexit_ctrl;
168 u32 vmentry_ctrl;
169} vmcs_config;
6aa8b732 170
efff9e53 171static struct vmx_capability {
d56f546d
SY		 172 u32 ept;
173 u32 vpid;
174} vmx_capability;
175
6aa8b732
AK		 176#define VMX_SEGMENT_FIELD(seg) \
177 [VCPU_SREG_##seg] = { \
178 .selector = GUEST_##seg##_SELECTOR, \
179 .base = GUEST_##seg##_BASE, \
180 .limit = GUEST_##seg##_LIMIT, \
181 .ar_bytes = GUEST_##seg##_AR_BYTES, \
182 }
183
184static struct kvm_vmx_segment_field {
185 unsigned selector;
186 unsigned base;
187 unsigned limit;
188 unsigned ar_bytes;
189} kvm_vmx_segment_fields[] = {
190 VMX_SEGMENT_FIELD(CS),
191 VMX_SEGMENT_FIELD(DS),
192 VMX_SEGMENT_FIELD(ES),
193 VMX_SEGMENT_FIELD(FS),
194 VMX_SEGMENT_FIELD(GS),
195 VMX_SEGMENT_FIELD(SS),
196 VMX_SEGMENT_FIELD(TR),
197 VMX_SEGMENT_FIELD(LDTR),
198};
199
26bb0981
AK		 200static u64 host_efer;
201
6de4f3ad
AK		 202static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
203
4d56c8a7
AK		 204/*
205 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
206 * away by decrementing the array size.
207 */
6aa8b732 208static const u32 vmx_msr_index[] = {
05b3e0c2 209#ifdef CONFIG_X86_64
44ea2b17 210 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732
AK		 211#endif
212 MSR_EFER, MSR_K6_STAR,
213};
9d8f549d 214#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 215
6aa8b732
AK		 216static inline int is_page_fault(u32 intr_info)
217{
218 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
219 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 220 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 221}
222
2ab455cc
AL		 223static inline int is_no_device(u32 intr_info)
224{
225 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
226 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 227 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 228}
229
7aa81cc0
AL		 230static inline int is_invalid_opcode(u32 intr_info)
231{
232 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
233 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 234 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 235}
236
6aa8b732
AK		 237static inline int is_external_interrupt(u32 intr_info)
238{
239 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
240 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
241}
242
a0861c02
AK		 243static inline int is_machine_check(u32 intr_info)
244{
245 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
246 INTR_INFO_VALID_MASK)) ==
247 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
248}
249
25c5f225
SY		 250static inline int cpu_has_vmx_msr_bitmap(void)
251{
04547156 252 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 253}
254
6e5d865c
YS		 255static inline int cpu_has_vmx_tpr_shadow(void)
256{
04547156 257 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 258}
259
260static inline int vm_need_tpr_shadow(struct kvm *kvm)
261{
04547156 262 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 263}
264
f78e0e2e
SY		 265static inline int cpu_has_secondary_exec_ctrls(void)
266{
04547156
SY		 267 return vmcs_config.cpu_based_exec_ctrl &
268 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 269}
270
774ead3a 271static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 272{
04547156
SY		 273 return vmcs_config.cpu_based_2nd_exec_ctrl &
274 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
275}
276
277static inline bool cpu_has_vmx_flexpriority(void)
278{
279 return cpu_has_vmx_tpr_shadow() &&
280 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 281}
282
e799794e
MT		 283static inline bool cpu_has_vmx_ept_execute_only(void)
284{
285 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
286}
287
288static inline bool cpu_has_vmx_eptp_uncacheable(void)
289{
290 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
291}
292
293static inline bool cpu_has_vmx_eptp_writeback(void)
294{
295 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
296}
297
298static inline bool cpu_has_vmx_ept_2m_page(void)
299{
300 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
301}
302
d56f546d
SY		 303static inline int cpu_has_vmx_invept_individual_addr(void)
304{
04547156 305 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 306}
307
308static inline int cpu_has_vmx_invept_context(void)
309{
04547156 310 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 311}
312
313static inline int cpu_has_vmx_invept_global(void)
314{
04547156 315 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 316}
317
318static inline int cpu_has_vmx_ept(void)
319{
04547156
SY		 320 return vmcs_config.cpu_based_2nd_exec_ctrl &
321 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 322}
323
3a624e29
NK		 324static inline int cpu_has_vmx_unrestricted_guest(void)
325{
326 return vmcs_config.cpu_based_2nd_exec_ctrl &
327 SECONDARY_EXEC_UNRESTRICTED_GUEST;
328}
329
4b8d54f9
ZE		 330static inline int cpu_has_vmx_ple(void)
331{
332 return vmcs_config.cpu_based_2nd_exec_ctrl &
333 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
334}
335
f78e0e2e
SY		 336static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
337{
04547156
SY		 338 return flexpriority_enabled &&
339 (cpu_has_vmx_virtualize_apic_accesses()) &&
340 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 341}
342
2384d2b3
SY		 343static inline int cpu_has_vmx_vpid(void)
344{
04547156
SY		 345 return vmcs_config.cpu_based_2nd_exec_ctrl &
346 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 347}
348
f08864b4
SY		 349static inline int cpu_has_virtual_nmis(void)
350{
351 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
352}
353
04547156
SY		 354static inline bool report_flexpriority(void)
355{
356 return flexpriority_enabled;
357}
358
8b9cf98c 359static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 360{
361 int i;
362
a2fa3e9f 363 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 364 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 365 return i;
366 return -1;
367}
368
2384d2b3
SY		 369static inline void __invvpid(int ext, u16 vpid, gva_t gva)
370{
371 struct {
372 u64 vpid : 16;
373 u64 rsvd : 48;
374 u64 gva;
375 } operand = { vpid, 0, gva };
376
4ecac3fd 377 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 378 /* CF==1 or ZF==1 --> rc = -1 */
379 "; ja 1f ; ud2 ; 1:"
380 : : "a"(&operand), "c"(ext) : "cc", "memory");
381}
382
1439442c
SY		 383static inline void __invept(int ext, u64 eptp, gpa_t gpa)
384{
385 struct {
386 u64 eptp, gpa;
387 } operand = {eptp, gpa};
388
4ecac3fd 389 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 390 /* CF==1 or ZF==1 --> rc = -1 */
391 "; ja 1f ; ud2 ; 1:\n"
392 : : "a" (&operand), "c" (ext) : "cc", "memory");
393}
394
26bb0981 395static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 396{
397 int i;
398
8b9cf98c 399 i = __find_msr_index(vmx, msr);
a75beee6 400 if (i >= 0)
a2fa3e9f 401 return &vmx->guest_msrs[i];
8b6d44c7 402 return NULL;
7725f0ba
AK		 403}
404
6aa8b732
AK		 405static void vmcs_clear(struct vmcs *vmcs)
406{
407 u64 phys_addr = __pa(vmcs);
408 u8 error;
409
4ecac3fd 410 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 411 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
412 : "cc", "memory");
413 if (error)
414 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
415 vmcs, phys_addr);
416}
417
418static void __vcpu_clear(void *arg)
419{
8b9cf98c 420 struct vcpu_vmx *vmx = arg;
d3b2c338 421 int cpu = raw_smp_processor_id();
6aa8b732 422
8b9cf98c 423 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 424 vmcs_clear(vmx->vmcs);
425 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 426 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 427 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 428 list_del(&vmx->local_vcpus_link);
429 vmx->vcpu.cpu = -1;
430 vmx->launched = 0;
6aa8b732
AK		 431}
432
8b9cf98c 433static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 434{
eae5ecb5
AK		 435 if (vmx->vcpu.cpu == -1)
436 return;
8691e5a8 437 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 438}
439
2384d2b3
SY		 440static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
441{
442 if (vmx->vpid == 0)
443 return;
444
445 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
446}
447
1439442c
SY		 448static inline void ept_sync_global(void)
449{
450 if (cpu_has_vmx_invept_global())
451 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
452}
453
454static inline void ept_sync_context(u64 eptp)
455{
089d034e 456 if (enable_ept) {
1439442c
SY		 457 if (cpu_has_vmx_invept_context())
458 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
459 else
460 ept_sync_global();
461 }
462}
463
464static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
465{
089d034e 466 if (enable_ept) {
1439442c
SY		 467 if (cpu_has_vmx_invept_individual_addr())
468 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
469 eptp, gpa);
470 else
471 ept_sync_context(eptp);
472 }
473}
474
6aa8b732
AK		 475static unsigned long vmcs_readl(unsigned long field)
476{
477 unsigned long value;
478
4ecac3fd 479 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 480 : "=a"(value) : "d"(field) : "cc");
481 return value;
482}
483
484static u16 vmcs_read16(unsigned long field)
485{
486 return vmcs_readl(field);
487}
488
489static u32 vmcs_read32(unsigned long field)
490{
491 return vmcs_readl(field);
492}
493
494static u64 vmcs_read64(unsigned long field)
495{
05b3e0c2 496#ifdef CONFIG_X86_64
6aa8b732
AK		 497 return vmcs_readl(field);
498#else
499 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
500#endif
501}
502
e52de1b8
AK		 503static noinline void vmwrite_error(unsigned long field, unsigned long value)
504{
505 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
506 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
507 dump_stack();
508}
509
6aa8b732
AK		 510static void vmcs_writel(unsigned long field, unsigned long value)
511{
512 u8 error;
513
4ecac3fd 514 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 515 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 516 if (unlikely(error))
517 vmwrite_error(field, value);
6aa8b732
AK		 518}
519
520static void vmcs_write16(unsigned long field, u16 value)
521{
522 vmcs_writel(field, value);
523}
524
525static void vmcs_write32(unsigned long field, u32 value)
526{
527 vmcs_writel(field, value);
528}
529
530static void vmcs_write64(unsigned long field, u64 value)
531{
6aa8b732 532 vmcs_writel(field, value);
7682f2d0 533#ifndef CONFIG_X86_64
6aa8b732
AK		 534 asm volatile ("");
535 vmcs_writel(field+1, value >> 32);
536#endif
537}
538
2ab455cc
AL		 539static void vmcs_clear_bits(unsigned long field, u32 mask)
540{
541 vmcs_writel(field, vmcs_readl(field) & ~mask);
542}
543
544static void vmcs_set_bits(unsigned long field, u32 mask)
545{
546 vmcs_writel(field, vmcs_readl(field) | mask);
547}
548
abd3f2d6
AK		 549static void update_exception_bitmap(struct kvm_vcpu *vcpu)
550{
551 u32 eb;
552
a0861c02 553 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
abd3f2d6
AK		 554 if (!vcpu->fpu_active)
555 eb |= 1u << NM_VECTOR;
e8a48342
AK		 556 /*
557 * Unconditionally intercept #DB so we can maintain dr6 without
558 * reading it every exit.
559 */
560 eb |= 1u << DB_VECTOR;
d0bfb940 561 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940
JK		 562 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
563 eb |= 1u << BP_VECTOR;
564 }
7ffd92c5 565 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 566 eb = ~0;
089d034e 567 if (enable_ept)
1439442c 568 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 569 vmcs_write32(EXCEPTION_BITMAP, eb);
570}
571
33ed6329
AK		 572static void reload_tss(void)
573{
33ed6329
AK		 574 /*
575 * VT restores TR but not its size. Useless.
576 */
577 struct descriptor_table gdt;
a5f61300 578 struct desc_struct *descs;
33ed6329 579
d6e88aec 580 kvm_get_gdt(&gdt);
33ed6329
AK		 581 descs = (void *)gdt.base;
582 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
583 load_TR_desc();
33ed6329
AK		 584}
585
92c0d900 586static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 587{
3a34a881 588 u64 guest_efer;
51c6cf66
AK		 589 u64 ignore_bits;
590
26bb0981 591 guest_efer = vmx->vcpu.arch.shadow_efer;
3a34a881 592
51c6cf66
AK		 593 /*
594 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
595 * outside long mode
596 */
597 ignore_bits = EFER_NX | EFER_SCE;
598#ifdef CONFIG_X86_64
599 ignore_bits |= EFER_LMA | EFER_LME;
600 /* SCE is meaningful only in long mode on Intel */
601 if (guest_efer & EFER_LMA)
602 ignore_bits &= ~(u64)EFER_SCE;
603#endif
604 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
26bb0981 605 return false;
2cc51560 606
51c6cf66
AK		 607 guest_efer &= ~ignore_bits;
608 guest_efer |= host_efer & ignore_bits;
26bb0981
AK		 609 vmx->guest_msrs[efer_offset].data = guest_efer;
610 return true;
51c6cf66
AK		 611}
612
04d2cc77 613static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 614{
04d2cc77 615 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 616 int i;
04d2cc77 617
a2fa3e9f 618 if (vmx->host_state.loaded)
33ed6329
AK		 619 return;
620
a2fa3e9f 621 vmx->host_state.loaded = 1;
33ed6329
AK		 622 /*
623 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
624 * allow segment selectors with cpl > 0 or ti == 1.
625 */
d6e88aec 626 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 627 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 628 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 629 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 630 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 631 vmx->host_state.fs_reload_needed = 0;
632 } else {
33ed6329 633 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 634 vmx->host_state.fs_reload_needed = 1;
33ed6329 635 }
d6e88aec 636 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 637 if (!(vmx->host_state.gs_sel & 7))
638 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 639 else {
640 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 641 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 642 }
643
644#ifdef CONFIG_X86_64
645 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
646 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
647#else
a2fa3e9f
GH		 648 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
649 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 650#endif
707c0874
AK		 651
652#ifdef CONFIG_X86_64
44ea2b17
AK		 653 if (is_long_mode(&vmx->vcpu)) {
654 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
655 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
656 }
707c0874 657#endif
26bb0981
AK		 658 for (i = 0; i < vmx->save_nmsrs; ++i)
659 kvm_set_shared_msr(vmx->guest_msrs[i].index,
660 vmx->guest_msrs[i].data);
33ed6329
AK		 661}
662
a9b21b62 663static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 664{
15ad7146 665 unsigned long flags;
33ed6329 666
a2fa3e9f 667 if (!vmx->host_state.loaded)
33ed6329
AK		 668 return;
669
e1beb1d3 670 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 671 vmx->host_state.loaded = 0;
152d3f2f 672 if (vmx->host_state.fs_reload_needed)
d6e88aec 673 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 674 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 675 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 676 /*
677 * If we have to reload gs, we must take care to
678 * preserve our gs base.
679 */
15ad7146 680 local_irq_save(flags);
d6e88aec 681 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 682#ifdef CONFIG_X86_64
683 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
684#endif
15ad7146 685 local_irq_restore(flags);
33ed6329 686 }
152d3f2f 687 reload_tss();
44ea2b17
AK		 688#ifdef CONFIG_X86_64
689 if (is_long_mode(&vmx->vcpu)) {
690 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
691 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
692 }
693#endif
33ed6329
AK		 694}
695
a9b21b62
AK		 696static void vmx_load_host_state(struct vcpu_vmx *vmx)
697{
698 preempt_disable();
699 __vmx_load_host_state(vmx);
700 preempt_enable();
701}
702
6aa8b732
AK		 703/*
704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
705 * vcpu mutex is already taken.
706 */
15ad7146 707static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 708{
a2fa3e9f
GH		 709 struct vcpu_vmx *vmx = to_vmx(vcpu);
710 u64 phys_addr = __pa(vmx->vmcs);
019960ae 711 u64 tsc_this, delta, new_offset;
6aa8b732 712
a3d7f85f 713 if (vcpu->cpu != cpu) {
8b9cf98c 714 vcpu_clear(vmx);
2f599714 715 kvm_migrate_timers(vcpu);
eb5109e3 716 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 717 local_irq_disable();
718 list_add(&vmx->local_vcpus_link,
719 &per_cpu(vcpus_on_cpu, cpu));
720 local_irq_enable();
a3d7f85f 721 }
6aa8b732 722
a2fa3e9f 723 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 724 u8 error;
725
a2fa3e9f 726 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 727 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 728 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
729 : "cc");
730 if (error)
731 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 732 vmx->vmcs, phys_addr);
6aa8b732
AK		 733 }
734
735 if (vcpu->cpu != cpu) {
736 struct descriptor_table dt;
737 unsigned long sysenter_esp;
738
739 vcpu->cpu = cpu;
740 /*
741 * Linux uses per-cpu TSS and GDT, so set these when switching
742 * processors.
743 */
d6e88aec
AK		 744 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
745 kvm_get_gdt(&dt);
6aa8b732
AK		 746 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
747
748 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
749 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 750
751 /*
752 * Make sure the time stamp counter is monotonous.
753 */
754 rdtscll(tsc_this);
019960ae
AK		 755 if (tsc_this < vcpu->arch.host_tsc) {
756 delta = vcpu->arch.host_tsc - tsc_this;
757 new_offset = vmcs_read64(TSC_OFFSET) + delta;
758 vmcs_write64(TSC_OFFSET, new_offset);
759 }
6aa8b732 760 }
6aa8b732
AK		 761}
762
763static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
764{
a9b21b62 765 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 766}
767
5fd86fcf
AK		 768static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
769{
770 if (vcpu->fpu_active)
771 return;
772 vcpu->fpu_active = 1;
707d92fa 773 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 774 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 775 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 776 update_exception_bitmap(vcpu);
777}
778
779static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
780{
781 if (!vcpu->fpu_active)
782 return;
783 vcpu->fpu_active = 0;
707d92fa 784 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 785 update_exception_bitmap(vcpu);
786}
787
6aa8b732
AK		 788static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
789{
345dcaa8
AK		 790 unsigned long rflags;
791
792 rflags = vmcs_readl(GUEST_RFLAGS);
793 if (to_vmx(vcpu)->rmode.vm86_active)
794 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
795 return rflags;
6aa8b732
AK		 796}
797
798static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
799{
7ffd92c5 800 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 801 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 802 vmcs_writel(GUEST_RFLAGS, rflags);
803}
804
2809f5d2
GC		 805static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
806{
807 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
808 int ret = 0;
809
810 if (interruptibility & GUEST_INTR_STATE_STI)
811 ret |= X86_SHADOW_INT_STI;
812 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
813 ret |= X86_SHADOW_INT_MOV_SS;
814
815 return ret & mask;
816}
817
818static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
819{
820 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
821 u32 interruptibility = interruptibility_old;
822
823 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
824
825 if (mask & X86_SHADOW_INT_MOV_SS)
826 interruptibility |= GUEST_INTR_STATE_MOV_SS;
827 if (mask & X86_SHADOW_INT_STI)
828 interruptibility |= GUEST_INTR_STATE_STI;
829
830 if ((interruptibility != interruptibility_old))
831 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
832}
833
6aa8b732
AK		 834static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
835{
836 unsigned long rip;
6aa8b732 837
5fdbf976 838 rip = kvm_rip_read(vcpu);
6aa8b732 839 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 840 kvm_rip_write(vcpu, rip);
6aa8b732 841
2809f5d2
GC		 842 /* skipping an emulated instruction also counts */
843 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 844}
845
298101da
AK		 846static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
847 bool has_error_code, u32 error_code)
848{
77ab6db0 849 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 850 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 851
8ab2d2e2 852 if (has_error_code) {
77ab6db0 853 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 854 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
855 }
77ab6db0 856
7ffd92c5 857 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 858 vmx->rmode.irq.pending = true;
859 vmx->rmode.irq.vector = nr;
860 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 861 if (kvm_exception_is_soft(nr))
862 vmx->rmode.irq.rip +=
863 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 864 intr_info |= INTR_TYPE_SOFT_INTR;
865 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 866 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
867 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
868 return;
869 }
870
66fd3f7f
GN		 871 if (kvm_exception_is_soft(nr)) {
872 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
873 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 874 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
875 } else
876 intr_info |= INTR_TYPE_HARD_EXCEPTION;
877
878 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 879}
880
a75beee6
ED		 881/*
882 * Swap MSR entry in host/guest MSR entry array.
883 */
8b9cf98c 884static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 885{
26bb0981 886 struct shared_msr_entry tmp;
a2fa3e9f
GH		 887
888 tmp = vmx->guest_msrs[to];
889 vmx->guest_msrs[to] = vmx->guest_msrs[from];
890 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 891}
892
e38aea3e
AK		 893/*
894 * Set up the vmcs to automatically save and restore system
895 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
896 * mode, as fiddling with msrs is very expensive.
897 */
8b9cf98c 898static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 899{
26bb0981 900 int save_nmsrs, index;
5897297b 901 unsigned long *msr_bitmap;
e38aea3e 902
33f9c505 903 vmx_load_host_state(vmx);
a75beee6
ED		 904 save_nmsrs = 0;
905#ifdef CONFIG_X86_64
8b9cf98c 906 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 907 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 908 if (index >= 0)
8b9cf98c
RR		 909 move_msr_up(vmx, index, save_nmsrs++);
910 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 911 if (index >= 0)
8b9cf98c
RR		 912 move_msr_up(vmx, index, save_nmsrs++);
913 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 914 if (index >= 0)
8b9cf98c 915 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 916 /*
917 * MSR_K6_STAR is only needed on long mode guests, and only
918 * if efer.sce is enabled.
919 */
8b9cf98c 920 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 921 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 922 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 923 }
924#endif
92c0d900
AK		 925 index = __find_msr_index(vmx, MSR_EFER);
926 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 927 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 928
26bb0981 929 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 930
931 if (cpu_has_vmx_msr_bitmap()) {
932 if (is_long_mode(&vmx->vcpu))
933 msr_bitmap = vmx_msr_bitmap_longmode;
934 else
935 msr_bitmap = vmx_msr_bitmap_legacy;
936
937 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
938 }
e38aea3e
AK		 939}
940
6aa8b732
AK		 941/*
942 * reads and returns guest's timestamp counter "register"
943 * guest_tsc = host_tsc + tsc_offset -- 21.3
944 */
945static u64 guest_read_tsc(void)
946{
947 u64 host_tsc, tsc_offset;
948
949 rdtscll(host_tsc);
950 tsc_offset = vmcs_read64(TSC_OFFSET);
951 return host_tsc + tsc_offset;
952}
953
954/*
955 * writes 'guest_tsc' into guest's timestamp counter "register"
956 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
957 */
53f658b3 958static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 959{
6aa8b732
AK		 960 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
961}
962
6aa8b732
AK		 963/*
964 * Reads an msr value (of 'msr_index') into 'pdata'.
965 * Returns 0 on success, non-0 otherwise.
966 * Assumes vcpu_load() was already called.
967 */
968static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
969{
970 u64 data;
26bb0981 971 struct shared_msr_entry *msr;
6aa8b732
AK		 972
973 if (!pdata) {
974 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
975 return -EINVAL;
976 }
977
978 switch (msr_index) {
05b3e0c2 979#ifdef CONFIG_X86_64
6aa8b732
AK		 980 case MSR_FS_BASE:
981 data = vmcs_readl(GUEST_FS_BASE);
982 break;
983 case MSR_GS_BASE:
984 data = vmcs_readl(GUEST_GS_BASE);
985 break;
44ea2b17
AK		 986 case MSR_KERNEL_GS_BASE:
987 vmx_load_host_state(to_vmx(vcpu));
988 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
989 break;
26bb0981 990#endif
6aa8b732 991 case MSR_EFER:
3bab1f5d 992 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 993 case MSR_IA32_TSC:
6aa8b732
AK		 994 data = guest_read_tsc();
995 break;
996 case MSR_IA32_SYSENTER_CS:
997 data = vmcs_read32(GUEST_SYSENTER_CS);
998 break;
999 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1000 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1001 break;
1002 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1003 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1004 break;
6aa8b732 1005 default:
26bb0981 1006 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1007 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1008 if (msr) {
542423b0 1009 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1010 data = msr->data;
1011 break;
6aa8b732 1012 }
3bab1f5d 1013 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1014 }
1015
1016 *pdata = data;
1017 return 0;
1018}
1019
1020/*
1021 * Writes msr value into into the appropriate "register".
1022 * Returns 0 on success, non-0 otherwise.
1023 * Assumes vcpu_load() was already called.
1024 */
1025static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1026{
a2fa3e9f 1027 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1028 struct shared_msr_entry *msr;
53f658b3 1029 u64 host_tsc;
2cc51560
ED		 1030 int ret = 0;
1031
6aa8b732 1032 switch (msr_index) {
3bab1f5d 1033 case MSR_EFER:
a9b21b62 1034 vmx_load_host_state(vmx);
2cc51560 1035 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1036 break;
16175a79 1037#ifdef CONFIG_X86_64
6aa8b732
AK		 1038 case MSR_FS_BASE:
1039 vmcs_writel(GUEST_FS_BASE, data);
1040 break;
1041 case MSR_GS_BASE:
1042 vmcs_writel(GUEST_GS_BASE, data);
1043 break;
44ea2b17
AK		 1044 case MSR_KERNEL_GS_BASE:
1045 vmx_load_host_state(vmx);
1046 vmx->msr_guest_kernel_gs_base = data;
1047 break;
6aa8b732
AK		 1048#endif
1049 case MSR_IA32_SYSENTER_CS:
1050 vmcs_write32(GUEST_SYSENTER_CS, data);
1051 break;
1052 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1053 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1054 break;
1055 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1056 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1057 break;
af24a4e4 1058 case MSR_IA32_TSC:
53f658b3
MT		 1059 rdtscll(host_tsc);
1060 guest_write_tsc(data, host_tsc);
6aa8b732 1061 break;
468d472f
SY		 1062 case MSR_IA32_CR_PAT:
1063 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1064 vmcs_write64(GUEST_IA32_PAT, data);
1065 vcpu->arch.pat = data;
1066 break;
1067 }
1068 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 1069 default:
8b9cf98c 1070 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1071 if (msr) {
542423b0 1072 vmx_load_host_state(vmx);
3bab1f5d
AK		 1073 msr->data = data;
1074 break;
6aa8b732 1075 }
2cc51560 1076 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1077 }
1078
2cc51560 1079 return ret;
6aa8b732
AK		 1080}
1081
5fdbf976 1082static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1083{
5fdbf976
MT		 1084 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1085 switch (reg) {
1086 case VCPU_REGS_RSP:
1087 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1088 break;
1089 case VCPU_REGS_RIP:
1090 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1091 break;
6de4f3ad
AK		 1092 case VCPU_EXREG_PDPTR:
1093 if (enable_ept)
1094 ept_save_pdptrs(vcpu);
1095 break;
5fdbf976
MT		 1096 default:
1097 break;
1098 }
6aa8b732
AK		 1099}
1100
355be0b9 1101static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1102{
ae675ef0
JK		 1103 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1104 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1105 else
1106 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1107
abd3f2d6 1108 update_exception_bitmap(vcpu);
6aa8b732
AK		 1109}
1110
1111static __init int cpu_has_kvm_support(void)
1112{
6210e37b 1113 return cpu_has_vmx();
6aa8b732
AK		 1114}
1115
1116static __init int vmx_disabled_by_bios(void)
1117{
1118 u64 msr;
1119
1120 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1121 return (msr & (FEATURE_CONTROL_LOCKED |
1122 FEATURE_CONTROL_VMXON_ENABLED))
1123 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1124 /* locked but not enabled */
6aa8b732
AK		 1125}
1126
10474ae8 1127static int hardware_enable(void *garbage)
6aa8b732
AK		 1128{
1129 int cpu = raw_smp_processor_id();
1130 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1131 u64 old;
1132
10474ae8
AG		 1133 if (read_cr4() & X86_CR4_VMXE)
1134 return -EBUSY;
1135
543e4243 1136 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1137 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1138 if ((old & (FEATURE_CONTROL_LOCKED |
1139 FEATURE_CONTROL_VMXON_ENABLED))
1140 != (FEATURE_CONTROL_LOCKED |
1141 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1142 /* enable and lock */
62b3ffb8 1143 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1144 FEATURE_CONTROL_LOCKED |
1145 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1146 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1147 asm volatile (ASM_VMX_VMXON_RAX
1148 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1149 : "memory", "cc");
10474ae8
AG		 1150
1151 ept_sync_global();
1152
1153 return 0;
6aa8b732
AK		 1154}
1155
543e4243
AK		 1156static void vmclear_local_vcpus(void)
1157{
1158 int cpu = raw_smp_processor_id();
1159 struct vcpu_vmx *vmx, *n;
1160
1161 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1162 local_vcpus_link)
1163 __vcpu_clear(vmx);
1164}
1165
710ff4a8
EH		 1166
1167/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1168 * tricks.
1169 */
1170static void kvm_cpu_vmxoff(void)
6aa8b732 1171{
4ecac3fd 1172 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1173 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1174}
1175
710ff4a8
EH		 1176static void hardware_disable(void *garbage)
1177{
1178 vmclear_local_vcpus();
1179 kvm_cpu_vmxoff();
1180}
1181
1c3d14fe 1182static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1183 u32 msr, u32 *result)
1c3d14fe
YS		 1184{
1185 u32 vmx_msr_low, vmx_msr_high;
1186 u32 ctl = ctl_min | ctl_opt;
1187
1188 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1189
1190 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1191 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1192
1193 /* Ensure minimum (required) set of control bits are supported. */
1194 if (ctl_min & ~ctl)
002c7f7c 1195 return -EIO;
1c3d14fe
YS		 1196
1197 *result = ctl;
1198 return 0;
1199}
1200
002c7f7c 1201static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1202{
1203 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1204 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1205 u32 _pin_based_exec_control = 0;
1206 u32 _cpu_based_exec_control = 0;
f78e0e2e 1207 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1208 u32 _vmexit_control = 0;
1209 u32 _vmentry_control = 0;
1210
1211 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1212 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1213 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1214 &_pin_based_exec_control) < 0)
002c7f7c 1215 return -EIO;
1c3d14fe
YS		 1216
1217 min = CPU_BASED_HLT_EXITING |
1218#ifdef CONFIG_X86_64
1219 CPU_BASED_CR8_LOAD_EXITING |
1220 CPU_BASED_CR8_STORE_EXITING |
1221#endif
d56f546d
SY		 1222 CPU_BASED_CR3_LOAD_EXITING |
1223 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1224 CPU_BASED_USE_IO_BITMAPS |
1225 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1226 CPU_BASED_USE_TSC_OFFSETING |
1227 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1228 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1229 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1230 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1231 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1232 &_cpu_based_exec_control) < 0)
002c7f7c 1233 return -EIO;
6e5d865c
YS		 1234#ifdef CONFIG_X86_64
1235 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1236 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1237 ~CPU_BASED_CR8_STORE_EXITING;
1238#endif
f78e0e2e 1239 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1240 min2 = 0;
1241 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1242 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1243 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1244 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9
ZE		 1245 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1246 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d56f546d
SY		 1247 if (adjust_vmx_controls(min2, opt2,
1248 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1249 &_cpu_based_2nd_exec_control) < 0)
1250 return -EIO;
1251 }
1252#ifndef CONFIG_X86_64
1253 if (!(_cpu_based_2nd_exec_control &
1254 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1255 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1256#endif
d56f546d 1257 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1258 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1259 enabled */
5fff7d27
GN		 1260 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1261 CPU_BASED_CR3_STORE_EXITING |
1262 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1263 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1264 vmx_capability.ept, vmx_capability.vpid);
1265 }
1c3d14fe
YS		 1266
1267 min = 0;
1268#ifdef CONFIG_X86_64
1269 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1270#endif
468d472f 1271 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1272 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1273 &_vmexit_control) < 0)
002c7f7c 1274 return -EIO;
1c3d14fe 1275
468d472f
SY		 1276 min = 0;
1277 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1278 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1279 &_vmentry_control) < 0)
002c7f7c 1280 return -EIO;
6aa8b732 1281
c68876fd 1282 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1283
1284 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1285 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1286 return -EIO;
1c3d14fe
YS		 1287
1288#ifdef CONFIG_X86_64
1289 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1290 if (vmx_msr_high & (1u<<16))
002c7f7c 1291 return -EIO;
1c3d14fe
YS		 1292#endif
1293
1294 /* Require Write-Back (WB) memory type for VMCS accesses. */
1295 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1296 return -EIO;
1c3d14fe 1297
002c7f7c
YS		 1298 vmcs_conf->size = vmx_msr_high & 0x1fff;
1299 vmcs_conf->order = get_order(vmcs_config.size);
1300 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1301
002c7f7c
YS		 1302 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1303 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1304 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1305 vmcs_conf->vmexit_ctrl = _vmexit_control;
1306 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1307
1308 return 0;
c68876fd 1309}
6aa8b732
AK		 1310
1311static struct vmcs *alloc_vmcs_cpu(int cpu)
1312{
1313 int node = cpu_to_node(cpu);
1314 struct page *pages;
1315 struct vmcs *vmcs;
1316
6484eb3e 1317 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1318 if (!pages)
1319 return NULL;
1320 vmcs = page_address(pages);
1c3d14fe
YS		 1321 memset(vmcs, 0, vmcs_config.size);
1322 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1323 return vmcs;
1324}
1325
1326static struct vmcs *alloc_vmcs(void)
1327{
d3b2c338 1328 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1329}
1330
1331static void free_vmcs(struct vmcs *vmcs)
1332{
1c3d14fe 1333 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1334}
1335
39959588 1336static void free_kvm_area(void)
6aa8b732
AK		 1337{
1338 int cpu;
1339
3230bb47 1340 for_each_possible_cpu(cpu) {
6aa8b732 1341 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1342 per_cpu(vmxarea, cpu) = NULL;
1343 }
6aa8b732
AK		 1344}
1345
6aa8b732
AK		 1346static __init int alloc_kvm_area(void)
1347{
1348 int cpu;
1349
3230bb47 1350 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1351 struct vmcs *vmcs;
1352
1353 vmcs = alloc_vmcs_cpu(cpu);
1354 if (!vmcs) {
1355 free_kvm_area();
1356 return -ENOMEM;
1357 }
1358
1359 per_cpu(vmxarea, cpu) = vmcs;
1360 }
1361 return 0;
1362}
1363
1364static __init int hardware_setup(void)
1365{
002c7f7c
YS		 1366 if (setup_vmcs_config(&vmcs_config) < 0)
1367 return -EIO;
50a37eb4
JR		 1368
1369 if (boot_cpu_has(X86_FEATURE_NX))
1370 kvm_enable_efer_bits(EFER_NX);
1371
93ba03c2
SY		 1372 if (!cpu_has_vmx_vpid())
1373 enable_vpid = 0;
1374
3a624e29 1375 if (!cpu_has_vmx_ept()) {
93ba03c2 1376 enable_ept = 0;
3a624e29
NK		 1377 enable_unrestricted_guest = 0;
1378 }
1379
1380 if (!cpu_has_vmx_unrestricted_guest())
1381 enable_unrestricted_guest = 0;
93ba03c2
SY		 1382
1383 if (!cpu_has_vmx_flexpriority())
1384 flexpriority_enabled = 0;
1385
95ba8273
GN		 1386 if (!cpu_has_vmx_tpr_shadow())
1387 kvm_x86_ops->update_cr8_intercept = NULL;
1388
54dee993
MT		 1389 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1390 kvm_disable_largepages();
1391
4b8d54f9
ZE		 1392 if (!cpu_has_vmx_ple())
1393 ple_gap = 0;
1394
6aa8b732
AK		 1395 return alloc_kvm_area();
1396}
1397
1398static __exit void hardware_unsetup(void)
1399{
1400 free_kvm_area();
1401}
1402
6aa8b732
AK		 1403static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1404{
1405 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1406
6af11b9e 1407 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1408 vmcs_write16(sf->selector, save->selector);
1409 vmcs_writel(sf->base, save->base);
1410 vmcs_write32(sf->limit, save->limit);
1411 vmcs_write32(sf->ar_bytes, save->ar);
1412 } else {
1413 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1414 << AR_DPL_SHIFT;
1415 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1416 }
1417}
1418
1419static void enter_pmode(struct kvm_vcpu *vcpu)
1420{
1421 unsigned long flags;
a89a8fb9 1422 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1423
a89a8fb9 1424 vmx->emulation_required = 1;
7ffd92c5 1425 vmx->rmode.vm86_active = 0;
6aa8b732 1426
7ffd92c5
AK		 1427 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1428 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1429 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1430
1431 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1432 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1433 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1434 vmcs_writel(GUEST_RFLAGS, flags);
1435
66aee91a
RR		 1436 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1437 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1438
1439 update_exception_bitmap(vcpu);
1440
a89a8fb9
MG		 1441 if (emulate_invalid_guest_state)
1442 return;
1443
7ffd92c5
AK		 1444 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1445 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1446 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1447 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1448
1449 vmcs_write16(GUEST_SS_SELECTOR, 0);
1450 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1451
1452 vmcs_write16(GUEST_CS_SELECTOR,
1453 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1454 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1455}
1456
d77c26fc 1457static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1458{
bfc6d222 1459 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1460 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1461 kvm->memslots[0].npages - 3;
1462 return base_gfn << PAGE_SHIFT;
1463 }
bfc6d222 1464 return kvm->arch.tss_addr;
6aa8b732
AK		 1465}
1466
1467static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1468{
1469 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1470
1471 save->selector = vmcs_read16(sf->selector);
1472 save->base = vmcs_readl(sf->base);
1473 save->limit = vmcs_read32(sf->limit);
1474 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1475 vmcs_write16(sf->selector, save->base >> 4);
1476 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1477 vmcs_write32(sf->limit, 0xffff);
1478 vmcs_write32(sf->ar_bytes, 0xf3);
1479}
1480
1481static void enter_rmode(struct kvm_vcpu *vcpu)
1482{
1483 unsigned long flags;
a89a8fb9 1484 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1485
3a624e29
NK		 1486 if (enable_unrestricted_guest)
1487 return;
1488
a89a8fb9 1489 vmx->emulation_required = 1;
7ffd92c5 1490 vmx->rmode.vm86_active = 1;
6aa8b732 1491
7ffd92c5 1492 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1493 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1494
7ffd92c5 1495 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1496 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1497
7ffd92c5 1498 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1499 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1500
1501 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1502 vmx->rmode.save_iopl
ad312c7c 1503 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1504
053de044 1505 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1506
1507 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1508 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1509 update_exception_bitmap(vcpu);
1510
a89a8fb9
MG		 1511 if (emulate_invalid_guest_state)
1512 goto continue_rmode;
1513
6aa8b732
AK		 1514 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1515 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1516 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1517
1518 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1519 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1520 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1521 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1522 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1523
7ffd92c5
AK		 1524 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1525 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1526 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1527 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1528
a89a8fb9 1529continue_rmode:
8668a3c4 1530 kvm_mmu_reset_context(vcpu);
b7ebfb05 1531 init_rmode(vcpu->kvm);
6aa8b732
AK		 1532}
1533
401d10de
AS		 1534static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1535{
1536 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1537 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1538
1539 if (!msr)
1540 return;
401d10de 1541
44ea2b17
AK		 1542 /*
1543 * Force kernel_gs_base reloading before EFER changes, as control
1544 * of this msr depends on is_long_mode().
1545 */
1546 vmx_load_host_state(to_vmx(vcpu));
401d10de
AS		 1547 vcpu->arch.shadow_efer = efer;
1548 if (!msr)
1549 return;
1550 if (efer & EFER_LMA) {
1551 vmcs_write32(VM_ENTRY_CONTROLS,
1552 vmcs_read32(VM_ENTRY_CONTROLS) |
1553 VM_ENTRY_IA32E_MODE);
1554 msr->data = efer;
1555 } else {
1556 vmcs_write32(VM_ENTRY_CONTROLS,
1557 vmcs_read32(VM_ENTRY_CONTROLS) &
1558 ~VM_ENTRY_IA32E_MODE);
1559
1560 msr->data = efer & ~EFER_LME;
1561 }
1562 setup_msrs(vmx);
1563}
1564
05b3e0c2 1565#ifdef CONFIG_X86_64
6aa8b732
AK		 1566
1567static void enter_lmode(struct kvm_vcpu *vcpu)
1568{
1569 u32 guest_tr_ar;
1570
1571 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1572 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1573 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1574 __func__);
6aa8b732
AK		 1575 vmcs_write32(GUEST_TR_AR_BYTES,
1576 (guest_tr_ar & ~AR_TYPE_MASK)
1577 | AR_TYPE_BUSY_64_TSS);
1578 }
ad312c7c 1579 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1580 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1581}
1582
1583static void exit_lmode(struct kvm_vcpu *vcpu)
1584{
ad312c7c 1585 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1586
1587 vmcs_write32(VM_ENTRY_CONTROLS,
1588 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1589 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1590}
1591
1592#endif
1593
2384d2b3
SY		 1594static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1595{
1596 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1597 if (enable_ept)
4e1096d2 1598 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1599}
1600
25c4c276 1601static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1602{
ad312c7c
ZX		 1603 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1604 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1605}
1606
1439442c
SY		 1607static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1608{
6de4f3ad
AK		 1609 if (!test_bit(VCPU_EXREG_PDPTR,
1610 (unsigned long *)&vcpu->arch.regs_dirty))
1611 return;
1612
1439442c 1613 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1614 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1615 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1616 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1617 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1618 }
1619}
1620
8f5d549f
AK		 1621static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1622{
1623 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1624 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1625 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1626 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1627 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1628 }
6de4f3ad
AK		 1629
1630 __set_bit(VCPU_EXREG_PDPTR,
1631 (unsigned long *)&vcpu->arch.regs_avail);
1632 __set_bit(VCPU_EXREG_PDPTR,
1633 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1634}
1635
1439442c
SY		 1636static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1637
1638static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1639 unsigned long cr0,
1640 struct kvm_vcpu *vcpu)
1641{
1642 if (!(cr0 & X86_CR0_PG)) {
1643 /* From paging/starting to nonpaging */
1644 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1645 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1646 (CPU_BASED_CR3_LOAD_EXITING |
1647 CPU_BASED_CR3_STORE_EXITING));
1648 vcpu->arch.cr0 = cr0;
1649 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c
SY		 1650 } else if (!is_paging(vcpu)) {
1651 /* From nonpaging to paging */
1652 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1653 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1654 ~(CPU_BASED_CR3_LOAD_EXITING |
1655 CPU_BASED_CR3_STORE_EXITING));
1656 vcpu->arch.cr0 = cr0;
1657 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c 1658 }
95eb84a7
SY		 1659
1660 if (!(cr0 & X86_CR0_WP))
1661 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1662}
1663
1664static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1665 struct kvm_vcpu *vcpu)
1666{
1667 if (!is_paging(vcpu)) {
1668 *hw_cr4 &= ~X86_CR4_PAE;
1669 *hw_cr4 |= X86_CR4_PSE;
1670 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1671 *hw_cr4 &= ~X86_CR4_PAE;
1672}
1673
6aa8b732
AK		 1674static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1675{
7ffd92c5 1676 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1677 unsigned long hw_cr0;
1678
1679 if (enable_unrestricted_guest)
1680 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1681 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1682 else
1683 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1684
5fd86fcf
AK		 1685 vmx_fpu_deactivate(vcpu);
1686
7ffd92c5 1687 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1688 enter_pmode(vcpu);
1689
7ffd92c5 1690 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1691 enter_rmode(vcpu);
1692
05b3e0c2 1693#ifdef CONFIG_X86_64
ad312c7c 1694 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1695 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1696 enter_lmode(vcpu);
707d92fa 1697 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1698 exit_lmode(vcpu);
1699 }
1700#endif
1701
089d034e 1702 if (enable_ept)
1439442c
SY		 1703 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1704
6aa8b732 1705 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1706 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1707 vcpu->arch.cr0 = cr0;
5fd86fcf 1708
707d92fa 1709 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1710 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1711}
1712
1439442c
SY		 1713static u64 construct_eptp(unsigned long root_hpa)
1714{
1715 u64 eptp;
1716
1717 /* TODO write the value reading from MSR */
1718 eptp = VMX_EPT_DEFAULT_MT |
1719 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1720 eptp |= (root_hpa & PAGE_MASK);
1721
1722 return eptp;
1723}
1724
6aa8b732
AK		 1725static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1726{
1439442c
SY		 1727 unsigned long guest_cr3;
1728 u64 eptp;
1729
1730 guest_cr3 = cr3;
089d034e 1731 if (enable_ept) {
1439442c
SY		 1732 eptp = construct_eptp(cr3);
1733 vmcs_write64(EPT_POINTER, eptp);
1439442c 1734 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1735 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1736 ept_load_pdptrs(vcpu);
1439442c
SY		 1737 }
1738
2384d2b3 1739 vmx_flush_tlb(vcpu);
1439442c 1740 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1741 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1742 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1743}
1744
1745static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1746{
7ffd92c5 1747 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1748 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1749
ad312c7c 1750 vcpu->arch.cr4 = cr4;
089d034e 1751 if (enable_ept)
1439442c
SY		 1752 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1753
1754 vmcs_writel(CR4_READ_SHADOW, cr4);
1755 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1756}
1757
6aa8b732
AK		 1758static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1759{
1760 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1761
1762 return vmcs_readl(sf->base);
1763}
1764
1765static void vmx_get_segment(struct kvm_vcpu *vcpu,
1766 struct kvm_segment *var, int seg)
1767{
1768 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1769 u32 ar;
1770
1771 var->base = vmcs_readl(sf->base);
1772 var->limit = vmcs_read32(sf->limit);
1773 var->selector = vmcs_read16(sf->selector);
1774 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1775 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1776 ar = 0;
1777 var->type = ar & 15;
1778 var->s = (ar >> 4) & 1;
1779 var->dpl = (ar >> 5) & 3;
1780 var->present = (ar >> 7) & 1;
1781 var->avl = (ar >> 12) & 1;
1782 var->l = (ar >> 13) & 1;
1783 var->db = (ar >> 14) & 1;
1784 var->g = (ar >> 15) & 1;
1785 var->unusable = (ar >> 16) & 1;
1786}
1787
2e4d2653
IE		 1788static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1789{
2e4d2653
IE		 1790 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1791 return 0;
1792
1793 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1794 return 3;
1795
eab4b8aa 1796 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1797}
1798
653e3108 1799static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1800{
6aa8b732
AK		 1801 u32 ar;
1802
653e3108 1803 if (var->unusable)
6aa8b732
AK		 1804 ar = 1 << 16;
1805 else {
1806 ar = var->type & 15;
1807 ar |= (var->s & 1) << 4;
1808 ar |= (var->dpl & 3) << 5;
1809 ar |= (var->present & 1) << 7;
1810 ar |= (var->avl & 1) << 12;
1811 ar |= (var->l & 1) << 13;
1812 ar |= (var->db & 1) << 14;
1813 ar |= (var->g & 1) << 15;
1814 }
f7fbf1fd
UL		 1815 if (ar == 0) /* a 0 value means unusable */
1816 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1817
1818 return ar;
1819}
1820
1821static void vmx_set_segment(struct kvm_vcpu *vcpu,
1822 struct kvm_segment *var, int seg)
1823{
7ffd92c5 1824 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1825 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1826 u32 ar;
1827
7ffd92c5
AK		 1828 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1829 vmx->rmode.tr.selector = var->selector;
1830 vmx->rmode.tr.base = var->base;
1831 vmx->rmode.tr.limit = var->limit;
1832 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1833 return;
1834 }
1835 vmcs_writel(sf->base, var->base);
1836 vmcs_write32(sf->limit, var->limit);
1837 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1838 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1839 /*
1840 * Hack real-mode segments into vm86 compatibility.
1841 */
1842 if (var->base == 0xffff0000 && var->selector == 0xf000)
1843 vmcs_writel(sf->base, 0xf0000);
1844 ar = 0xf3;
1845 } else
1846 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1847
1848 /*
1849 * Fix the "Accessed" bit in AR field of segment registers for older
1850 * qemu binaries.
1851 * IA32 arch specifies that at the time of processor reset the
1852 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1853 * is setting it to 0 in the usedland code. This causes invalid guest
1854 * state vmexit when "unrestricted guest" mode is turned on.
1855 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1856 * tree. Newer qemu binaries with that qemu fix would not need this
1857 * kvm hack.
1858 */
1859 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1860 ar |= 0x1; /* Accessed */
1861
6aa8b732
AK		 1862 vmcs_write32(sf->ar_bytes, ar);
1863}
1864
6aa8b732
AK		 1865static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1866{
1867 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1868
1869 *db = (ar >> 14) & 1;
1870 *l = (ar >> 13) & 1;
1871}
1872
1873static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1874{
1875 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1876 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1877}
1878
1879static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1880{
1881 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1882 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1883}
1884
1885static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1886{
1887 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1888 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1889}
1890
1891static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1892{
1893 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1894 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1895}
1896
648dfaa7
MG		 1897static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1898{
1899 struct kvm_segment var;
1900 u32 ar;
1901
1902 vmx_get_segment(vcpu, &var, seg);
1903 ar = vmx_segment_access_rights(&var);
1904
1905 if (var.base != (var.selector << 4))
1906 return false;
1907 if (var.limit != 0xffff)
1908 return false;
1909 if (ar != 0xf3)
1910 return false;
1911
1912 return true;
1913}
1914
1915static bool code_segment_valid(struct kvm_vcpu *vcpu)
1916{
1917 struct kvm_segment cs;
1918 unsigned int cs_rpl;
1919
1920 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1921 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1922
1872a3f4
AK		 1923 if (cs.unusable)
1924 return false;
648dfaa7
MG		 1925 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1926 return false;
1927 if (!cs.s)
1928 return false;
1872a3f4 1929 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1930 if (cs.dpl > cs_rpl)
1931 return false;
1872a3f4 1932 } else {
648dfaa7
MG		 1933 if (cs.dpl != cs_rpl)
1934 return false;
1935 }
1936 if (!cs.present)
1937 return false;
1938
1939 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1940 return true;
1941}
1942
1943static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1944{
1945 struct kvm_segment ss;
1946 unsigned int ss_rpl;
1947
1948 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1949 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1950
1872a3f4
AK		 1951 if (ss.unusable)
1952 return true;
1953 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1954 return false;
1955 if (!ss.s)
1956 return false;
1957 if (ss.dpl != ss_rpl) /* DPL != RPL */
1958 return false;
1959 if (!ss.present)
1960 return false;
1961
1962 return true;
1963}
1964
1965static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1966{
1967 struct kvm_segment var;
1968 unsigned int rpl;
1969
1970 vmx_get_segment(vcpu, &var, seg);
1971 rpl = var.selector & SELECTOR_RPL_MASK;
1972
1872a3f4
AK		 1973 if (var.unusable)
1974 return true;
648dfaa7
MG		 1975 if (!var.s)
1976 return false;
1977 if (!var.present)
1978 return false;
1979 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1980 if (var.dpl < rpl) /* DPL < RPL */
1981 return false;
1982 }
1983
1984 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1985 * rights flags
1986 */
1987 return true;
1988}
1989
1990static bool tr_valid(struct kvm_vcpu *vcpu)
1991{
1992 struct kvm_segment tr;
1993
1994 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1995
1872a3f4
AK		 1996 if (tr.unusable)
1997 return false;
648dfaa7
MG		 1998 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1999 return false;
1872a3f4 2000 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2001 return false;
2002 if (!tr.present)
2003 return false;
2004
2005 return true;
2006}
2007
2008static bool ldtr_valid(struct kvm_vcpu *vcpu)
2009{
2010 struct kvm_segment ldtr;
2011
2012 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2013
1872a3f4
AK		 2014 if (ldtr.unusable)
2015 return true;
648dfaa7
MG		 2016 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2017 return false;
2018 if (ldtr.type != 2)
2019 return false;
2020 if (!ldtr.present)
2021 return false;
2022
2023 return true;
2024}
2025
2026static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2027{
2028 struct kvm_segment cs, ss;
2029
2030 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2031 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2032
2033 return ((cs.selector & SELECTOR_RPL_MASK) ==
2034 (ss.selector & SELECTOR_RPL_MASK));
2035}
2036
2037/*
2038 * Check if guest state is valid. Returns true if valid, false if
2039 * not.
2040 * We assume that registers are always usable
2041 */
2042static bool guest_state_valid(struct kvm_vcpu *vcpu)
2043{
2044 /* real mode guest state checks */
2045 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2046 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2047 return false;
2048 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2049 return false;
2050 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2051 return false;
2052 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2053 return false;
2054 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2055 return false;
2056 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2057 return false;
2058 } else {
2059 /* protected mode guest state checks */
2060 if (!cs_ss_rpl_check(vcpu))
2061 return false;
2062 if (!code_segment_valid(vcpu))
2063 return false;
2064 if (!stack_segment_valid(vcpu))
2065 return false;
2066 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2067 return false;
2068 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2069 return false;
2070 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2071 return false;
2072 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2073 return false;
2074 if (!tr_valid(vcpu))
2075 return false;
2076 if (!ldtr_valid(vcpu))
2077 return false;
2078 }
2079 /* TODO:
2080 * - Add checks on RIP
2081 * - Add checks on RFLAGS
2082 */
2083
2084 return true;
2085}
2086
d77c26fc 2087static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2088{
6aa8b732 2089 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2090 u16 data = 0;
10589a46 2091 int ret = 0;
195aefde 2092 int r;
6aa8b732 2093
195aefde
IE		 2094 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2095 if (r < 0)
10589a46 2096 goto out;
195aefde 2097 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2098 r = kvm_write_guest_page(kvm, fn++, &data,
2099 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2100 if (r < 0)
10589a46 2101 goto out;
195aefde
IE		 2102 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2103 if (r < 0)
10589a46 2104 goto out;
195aefde
IE		 2105 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2106 if (r < 0)
10589a46 2107 goto out;
195aefde 2108 data = ~0;
10589a46
MT		 2109 r = kvm_write_guest_page(kvm, fn, &data,
2110 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2111 sizeof(u8));
195aefde 2112 if (r < 0)
10589a46
MT		 2113 goto out;
2114
2115 ret = 1;
2116out:
10589a46 2117 return ret;
6aa8b732
AK		 2118}
2119
b7ebfb05
SY		 2120static int init_rmode_identity_map(struct kvm *kvm)
2121{
2122 int i, r, ret;
2123 pfn_t identity_map_pfn;
2124 u32 tmp;
2125
089d034e 2126 if (!enable_ept)
b7ebfb05
SY		 2127 return 1;
2128 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2129 printk(KERN_ERR "EPT: identity-mapping pagetable "
2130 "haven't been allocated!\n");
2131 return 0;
2132 }
2133 if (likely(kvm->arch.ept_identity_pagetable_done))
2134 return 1;
2135 ret = 0;
b927a3ce 2136 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2137 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2138 if (r < 0)
2139 goto out;
2140 /* Set up identity-mapping pagetable for EPT in real mode */
2141 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2142 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2143 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2144 r = kvm_write_guest_page(kvm, identity_map_pfn,
2145 &tmp, i * sizeof(tmp), sizeof(tmp));
2146 if (r < 0)
2147 goto out;
2148 }
2149 kvm->arch.ept_identity_pagetable_done = true;
2150 ret = 1;
2151out:
2152 return ret;
2153}
2154
6aa8b732
AK		 2155static void seg_setup(int seg)
2156{
2157 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2158 unsigned int ar;
6aa8b732
AK		 2159
2160 vmcs_write16(sf->selector, 0);
2161 vmcs_writel(sf->base, 0);
2162 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2163 if (enable_unrestricted_guest) {
2164 ar = 0x93;
2165 if (seg == VCPU_SREG_CS)
2166 ar |= 0x08; /* code segment */
2167 } else
2168 ar = 0xf3;
2169
2170 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2171}
2172
f78e0e2e
SY		 2173static int alloc_apic_access_page(struct kvm *kvm)
2174{
2175 struct kvm_userspace_memory_region kvm_userspace_mem;
2176 int r = 0;
2177
72dc67a6 2178 down_write(&kvm->slots_lock);
bfc6d222 2179 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2180 goto out;
2181 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2182 kvm_userspace_mem.flags = 0;
2183 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2184 kvm_userspace_mem.memory_size = PAGE_SIZE;
2185 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2186 if (r)
2187 goto out;
72dc67a6 2188
bfc6d222 2189 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2190out:
72dc67a6 2191 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2192 return r;
2193}
2194
b7ebfb05
SY		 2195static int alloc_identity_pagetable(struct kvm *kvm)
2196{
2197 struct kvm_userspace_memory_region kvm_userspace_mem;
2198 int r = 0;
2199
2200 down_write(&kvm->slots_lock);
2201 if (kvm->arch.ept_identity_pagetable)
2202 goto out;
2203 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2204 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2205 kvm_userspace_mem.guest_phys_addr =
2206 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2207 kvm_userspace_mem.memory_size = PAGE_SIZE;
2208 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2209 if (r)
2210 goto out;
2211
b7ebfb05 2212 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2213 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05
SY		 2214out:
2215 up_write(&kvm->slots_lock);
2216 return r;
2217}
2218
2384d2b3
SY		 2219static void allocate_vpid(struct vcpu_vmx *vmx)
2220{
2221 int vpid;
2222
2223 vmx->vpid = 0;
919818ab 2224 if (!enable_vpid)
2384d2b3
SY		 2225 return;
2226 spin_lock(&vmx_vpid_lock);
2227 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2228 if (vpid < VMX_NR_VPIDS) {
2229 vmx->vpid = vpid;
2230 __set_bit(vpid, vmx_vpid_bitmap);
2231 }
2232 spin_unlock(&vmx_vpid_lock);
2233}
2234
5897297b 2235static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2236{
3e7c73e9 2237 int f = sizeof(unsigned long);
25c5f225
SY		 2238
2239 if (!cpu_has_vmx_msr_bitmap())
2240 return;
2241
2242 /*
2243 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2244 * have the write-low and read-high bitmap offsets the wrong way round.
2245 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2246 */
25c5f225 2247 if (msr <= 0x1fff) {
3e7c73e9
AK		 2248 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2249 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2250 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2251 msr &= 0x1fff;
3e7c73e9
AK		 2252 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2253 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2254 }
25c5f225
SY		 2255}
2256
5897297b
AK		 2257static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2258{
2259 if (!longmode_only)
2260 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2261 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2262}
2263
6aa8b732
AK		 2264/*
2265 * Sets up the vmcs for emulated real mode.
2266 */
8b9cf98c 2267static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2268{
468d472f 2269 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2270 u32 junk;
53f658b3 2271 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2272 unsigned long a;
2273 struct descriptor_table dt;
2274 int i;
cd2276a7 2275 unsigned long kvm_vmx_return;
6e5d865c 2276 u32 exec_control;
6aa8b732 2277
6aa8b732 2278 /* I/O */
3e7c73e9
AK		 2279 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2280 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2281
25c5f225 2282 if (cpu_has_vmx_msr_bitmap())
5897297b 2283 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2284
6aa8b732
AK		 2285 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2286
6aa8b732 2287 /* Control */
1c3d14fe
YS		 2288 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2289 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2290
2291 exec_control = vmcs_config.cpu_based_exec_ctrl;
2292 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2293 exec_control &= ~CPU_BASED_TPR_SHADOW;
2294#ifdef CONFIG_X86_64
2295 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2296 CPU_BASED_CR8_LOAD_EXITING;
2297#endif
2298 }
089d034e 2299 if (!enable_ept)
d56f546d 2300 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2301 CPU_BASED_CR3_LOAD_EXITING |
2302 CPU_BASED_INVLPG_EXITING;
6e5d865c 2303 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2304
83ff3b9d
SY		 2305 if (cpu_has_secondary_exec_ctrls()) {
2306 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2307 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2308 exec_control &=
2309 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2310 if (vmx->vpid == 0)
2311 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
089d034e 2312 if (!enable_ept)
d56f546d 2313 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3a624e29
NK		 2314 if (!enable_unrestricted_guest)
2315 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2316 if (!ple_gap)
2317 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2318 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2319 }
f78e0e2e 2320
4b8d54f9
ZE		 2321 if (ple_gap) {
2322 vmcs_write32(PLE_GAP, ple_gap);
2323 vmcs_write32(PLE_WINDOW, ple_window);
2324 }
2325
c7addb90
AK		 2326 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2327 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2328 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2329
2330 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2331 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2332 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2333
2334 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2335 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2336 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2337 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2338 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2339 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2340#ifdef CONFIG_X86_64
6aa8b732
AK		 2341 rdmsrl(MSR_FS_BASE, a);
2342 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2343 rdmsrl(MSR_GS_BASE, a);
2344 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2345#else
2346 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2347 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2348#endif
2349
2350 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2351
d6e88aec 2352 kvm_get_idt(&dt);
6aa8b732
AK		 2353 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2354
d77c26fc 2355 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2356 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2357 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2358 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2359 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2360
2361 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2362 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2363 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2364 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2365 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2366 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2367
468d472f
SY		 2368 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2369 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2370 host_pat = msr_low | ((u64) msr_high << 32);
2371 vmcs_write64(HOST_IA32_PAT, host_pat);
2372 }
2373 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2374 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2375 host_pat = msr_low | ((u64) msr_high << 32);
2376 /* Write the default value follow host pat */
2377 vmcs_write64(GUEST_IA32_PAT, host_pat);
2378 /* Keep arch.pat sync with GUEST_IA32_PAT */
2379 vmx->vcpu.arch.pat = host_pat;
2380 }
2381
6aa8b732
AK		 2382 for (i = 0; i < NR_VMX_MSR; ++i) {
2383 u32 index = vmx_msr_index[i];
2384 u32 data_low, data_high;
2385 u64 data;
a2fa3e9f 2386 int j = vmx->nmsrs;
6aa8b732
AK		 2387
2388 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2389 continue;
432bd6cb
AK		 2390 if (wrmsr_safe(index, data_low, data_high) < 0)
2391 continue;
6aa8b732 2392 data = data_low | ((u64)data_high << 32);
26bb0981
AK		 2393 vmx->guest_msrs[j].index = i;
2394 vmx->guest_msrs[j].data = 0;
a2fa3e9f 2395 ++vmx->nmsrs;
6aa8b732 2396 }
6aa8b732 2397
1c3d14fe 2398 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2399
2400 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2401 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2402
e00c8cf2
AK		 2403 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2404 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2405
53f658b3
MT		 2406 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2407 rdtscll(tsc_this);
2408 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2409 tsc_base = tsc_this;
2410
2411 guest_write_tsc(0, tsc_base);
f78e0e2e 2412
e00c8cf2
AK		 2413 return 0;
2414}
2415
b7ebfb05
SY		 2416static int init_rmode(struct kvm *kvm)
2417{
2418 if (!init_rmode_tss(kvm))
2419 return 0;
2420 if (!init_rmode_identity_map(kvm))
2421 return 0;
2422 return 1;
2423}
2424
e00c8cf2
AK		 2425static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2426{
2427 struct vcpu_vmx *vmx = to_vmx(vcpu);
2428 u64 msr;
2429 int ret;
2430
5fdbf976 2431 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2432 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2433 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2434 ret = -ENOMEM;
2435 goto out;
2436 }
2437
7ffd92c5 2438 vmx->rmode.vm86_active = 0;
e00c8cf2 2439
3b86cd99
JK		 2440 vmx->soft_vnmi_blocked = 0;
2441
ad312c7c 2442 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2443 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2444 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2445 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2446 msr |= MSR_IA32_APICBASE_BSP;
2447 kvm_set_apic_base(&vmx->vcpu, msr);
2448
2449 fx_init(&vmx->vcpu);
2450
5706be0d 2451 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2452 /*
2453 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2454 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2455 */
c5af89b6 2456 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2457 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2458 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2459 } else {
ad312c7c
ZX		 2460 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2461 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2462 }
e00c8cf2
AK		 2463
2464 seg_setup(VCPU_SREG_DS);
2465 seg_setup(VCPU_SREG_ES);
2466 seg_setup(VCPU_SREG_FS);
2467 seg_setup(VCPU_SREG_GS);
2468 seg_setup(VCPU_SREG_SS);
2469
2470 vmcs_write16(GUEST_TR_SELECTOR, 0);
2471 vmcs_writel(GUEST_TR_BASE, 0);
2472 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2473 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2474
2475 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2476 vmcs_writel(GUEST_LDTR_BASE, 0);
2477 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2478 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2479
2480 vmcs_write32(GUEST_SYSENTER_CS, 0);
2481 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2482 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2483
2484 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2485 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2486 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2487 else
5fdbf976
MT		 2488 kvm_rip_write(vcpu, 0);
2489 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2490
e00c8cf2
AK		 2491 vmcs_writel(GUEST_DR7, 0x400);
2492
2493 vmcs_writel(GUEST_GDTR_BASE, 0);
2494 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2495
2496 vmcs_writel(GUEST_IDTR_BASE, 0);
2497 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2498
2499 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2500 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2501 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2502
e00c8cf2
AK		 2503 /* Special registers */
2504 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2505
2506 setup_msrs(vmx);
2507
6aa8b732
AK		 2508 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2509
f78e0e2e
SY		 2510 if (cpu_has_vmx_tpr_shadow()) {
2511 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2512 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2513 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2514 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2515 vmcs_write32(TPR_THRESHOLD, 0);
2516 }
2517
2518 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2519 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2520 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2521
2384d2b3
SY		 2522 if (vmx->vpid != 0)
2523 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2524
fa40052c 2525 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
ad312c7c 2526 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2527 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2528 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2529 vmx_fpu_activate(&vmx->vcpu);
2530 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2531
2384d2b3
SY		 2532 vpid_sync_vcpu_all(vmx);
2533
3200f405 2534 ret = 0;
6aa8b732 2535
a89a8fb9
MG		 2536 /* HACK: Don't enable emulation on guest boot/reset */
2537 vmx->emulation_required = 0;
2538
6aa8b732 2539out:
3200f405 2540 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2541 return ret;
2542}
2543
3b86cd99
JK		 2544static void enable_irq_window(struct kvm_vcpu *vcpu)
2545{
2546 u32 cpu_based_vm_exec_control;
2547
2548 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2549 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2550 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2551}
2552
2553static void enable_nmi_window(struct kvm_vcpu *vcpu)
2554{
2555 u32 cpu_based_vm_exec_control;
2556
2557 if (!cpu_has_virtual_nmis()) {
2558 enable_irq_window(vcpu);
2559 return;
2560 }
2561
2562 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2563 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2564 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2565}
2566
66fd3f7f 2567static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2568{
9c8cba37 2569 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2570 uint32_t intr;
2571 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2572
229456fc 2573 trace_kvm_inj_virq(irq);
2714d1d3 2574
fa89a817 2575 ++vcpu->stat.irq_injections;
7ffd92c5 2576 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2577 vmx->rmode.irq.pending = true;
2578 vmx->rmode.irq.vector = irq;
5fdbf976 2579 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2580 if (vcpu->arch.interrupt.soft)
2581 vmx->rmode.irq.rip +=
2582 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2583 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2584 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2585 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2586 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2587 return;
2588 }
66fd3f7f
GN		 2589 intr = irq | INTR_INFO_VALID_MASK;
2590 if (vcpu->arch.interrupt.soft) {
2591 intr |= INTR_TYPE_SOFT_INTR;
2592 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2593 vmx->vcpu.arch.event_exit_inst_len);
2594 } else
2595 intr |= INTR_TYPE_EXT_INTR;
2596 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2597}
2598
f08864b4
SY		 2599static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2600{
66a5a347
JK		 2601 struct vcpu_vmx *vmx = to_vmx(vcpu);
2602
3b86cd99
JK		 2603 if (!cpu_has_virtual_nmis()) {
2604 /*
2605 * Tracking the NMI-blocked state in software is built upon
2606 * finding the next open IRQ window. This, in turn, depends on
2607 * well-behaving guests: They have to keep IRQs disabled at
2608 * least as long as the NMI handler runs. Otherwise we may
2609 * cause NMI nesting, maybe breaking the guest. But as this is
2610 * highly unlikely, we can live with the residual risk.
2611 */
2612 vmx->soft_vnmi_blocked = 1;
2613 vmx->vnmi_blocked_time = 0;
2614 }
2615
487b391d 2616 ++vcpu->stat.nmi_injections;
7ffd92c5 2617 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2618 vmx->rmode.irq.pending = true;
2619 vmx->rmode.irq.vector = NMI_VECTOR;
2620 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2621 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2622 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2623 INTR_INFO_VALID_MASK);
2624 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2625 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2626 return;
2627 }
f08864b4
SY		 2628 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2629 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2630}
2631
c4282df9 2632static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2633{
3b86cd99 2634 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2635 return 0;
33f089ca 2636
c4282df9
GN		 2637 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2638 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2639 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2640}
2641
78646121
GN		 2642static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2643{
c4282df9
GN		 2644 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2645 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2646 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2647}
2648
cbc94022
IE		 2649static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2650{
2651 int ret;
2652 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2653 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2654 .guest_phys_addr = addr,
2655 .memory_size = PAGE_SIZE * 3,
2656 .flags = 0,
2657 };
2658
2659 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2660 if (ret)
2661 return ret;
bfc6d222 2662 kvm->arch.tss_addr = addr;
cbc94022
IE		 2663 return 0;
2664}
2665
6aa8b732
AK		 2666static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2667 int vec, u32 err_code)
2668{
b3f37707
NK		 2669 /*
2670 * Instruction with address size override prefix opcode 0x67
2671 * Cause the #SS fault with 0 error code in VM86 mode.
2672 */
2673 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2674 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2675 return 1;
77ab6db0
JK		 2676 /*
2677 * Forward all other exceptions that are valid in real mode.
2678 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2679 * the required debugging infrastructure rework.
2680 */
2681 switch (vec) {
77ab6db0 2682 case DB_VECTOR:
d0bfb940
JK		 2683 if (vcpu->guest_debug &
2684 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2685 return 0;
2686 kvm_queue_exception(vcpu, vec);
2687 return 1;
77ab6db0 2688 case BP_VECTOR:
d0bfb940
JK		 2689 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2690 return 0;
2691 /* fall through */
2692 case DE_VECTOR:
77ab6db0
JK		 2693 case OF_VECTOR:
2694 case BR_VECTOR:
2695 case UD_VECTOR:
2696 case DF_VECTOR:
2697 case SS_VECTOR:
2698 case GP_VECTOR:
2699 case MF_VECTOR:
2700 kvm_queue_exception(vcpu, vec);
2701 return 1;
2702 }
6aa8b732
AK		 2703 return 0;
2704}
2705
a0861c02
AK		 2706/*
2707 * Trigger machine check on the host. We assume all the MSRs are already set up
2708 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2709 * We pass a fake environment to the machine check handler because we want
2710 * the guest to be always treated like user space, no matter what context
2711 * it used internally.
2712 */
2713static void kvm_machine_check(void)
2714{
2715#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2716 struct pt_regs regs = {
2717 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2718 .flags = X86_EFLAGS_IF,
2719 };
2720
2721 do_machine_check(&regs, 0);
2722#endif
2723}
2724
851ba692 2725static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2726{
2727 /* already handled by vcpu_run */
2728 return 1;
2729}
2730
851ba692 2731static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2732{
1155f76a 2733 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2734 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2735 u32 intr_info, ex_no, error_code;
42dbaa5a 2736 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2737 u32 vect_info;
2738 enum emulation_result er;
2739
1155f76a 2740 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2741 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2742
a0861c02 2743 if (is_machine_check(intr_info))
851ba692 2744 return handle_machine_check(vcpu);
a0861c02 2745
6aa8b732 2746 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2747 !is_page_fault(intr_info)) {
2748 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2749 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2750 vcpu->run->internal.ndata = 2;
2751 vcpu->run->internal.data[0] = vect_info;
2752 vcpu->run->internal.data[1] = intr_info;
2753 return 0;
2754 }
6aa8b732 2755
e4a41889 2756 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2757 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2758
2759 if (is_no_device(intr_info)) {
5fd86fcf 2760 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2761 return 1;
2762 }
2763
7aa81cc0 2764 if (is_invalid_opcode(intr_info)) {
851ba692 2765 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2766 if (er != EMULATE_DONE)
7ee5d940 2767 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2768 return 1;
2769 }
2770
6aa8b732 2771 error_code = 0;
5fdbf976 2772 rip = kvm_rip_read(vcpu);
2e11384c 2773 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2774 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2775 if (is_page_fault(intr_info)) {
1439442c 2776 /* EPT won't cause page fault directly */
089d034e 2777 if (enable_ept)
1439442c 2778 BUG();
6aa8b732 2779 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2780 trace_kvm_page_fault(cr2, error_code);
2781
3298b75c 2782 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2783 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2784 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2785 }
2786
7ffd92c5 2787 if (vmx->rmode.vm86_active &&
6aa8b732 2788 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2789 error_code)) {
ad312c7c
ZX		 2790 if (vcpu->arch.halt_request) {
2791 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2792 return kvm_emulate_halt(vcpu);
2793 }
6aa8b732 2794 return 1;
72d6e5a0 2795 }
6aa8b732 2796
d0bfb940 2797 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2798 switch (ex_no) {
2799 case DB_VECTOR:
2800 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2801 if (!(vcpu->guest_debug &
2802 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2803 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2804 kvm_queue_exception(vcpu, DB_VECTOR);
2805 return 1;
2806 }
2807 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2808 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2809 /* fall through */
2810 case BP_VECTOR:
6aa8b732 2811 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2812 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2813 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2814 break;
2815 default:
d0bfb940
JK		 2816 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2817 kvm_run->ex.exception = ex_no;
2818 kvm_run->ex.error_code = error_code;
42dbaa5a 2819 break;
6aa8b732 2820 }
6aa8b732
AK		 2821 return 0;
2822}
2823
851ba692 2824static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 2825{
1165f5fe 2826 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2827 return 1;
2828}
2829
851ba692 2830static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 2831{
851ba692 2832 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 2833 return 0;
2834}
6aa8b732 2835
851ba692 2836static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 2837{
bfdaab09 2838 unsigned long exit_qualification;
34c33d16 2839 int size, in, string;
039576c0 2840 unsigned port;
6aa8b732 2841
1165f5fe 2842 ++vcpu->stat.io_exits;
bfdaab09 2843 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2844 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2845
2846 if (string) {
851ba692 2847 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2848 return 0;
2849 return 1;
2850 }
2851
2852 size = (exit_qualification & 7) + 1;
2853 in = (exit_qualification & 8) != 0;
039576c0 2854 port = exit_qualification >> 16;
e70669ab 2855
e93f36bc 2856 skip_emulated_instruction(vcpu);
851ba692 2857 return kvm_emulate_pio(vcpu, in, size, port);
6aa8b732
AK		 2858}
2859
102d8325
IM		 2860static void
2861vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2862{
2863 /*
2864 * Patch in the VMCALL instruction:
2865 */
2866 hypercall[0] = 0x0f;
2867 hypercall[1] = 0x01;
2868 hypercall[2] = 0xc1;
102d8325
IM		 2869}
2870
851ba692 2871static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 2872{
229456fc 2873 unsigned long exit_qualification, val;
6aa8b732
AK		 2874 int cr;
2875 int reg;
2876
bfdaab09 2877 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2878 cr = exit_qualification & 15;
2879 reg = (exit_qualification >> 8) & 15;
2880 switch ((exit_qualification >> 4) & 3) {
2881 case 0: /* mov to cr */
229456fc
MT		 2882 val = kvm_register_read(vcpu, reg);
2883 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2884 switch (cr) {
2885 case 0:
229456fc 2886 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2887 skip_emulated_instruction(vcpu);
2888 return 1;
2889 case 3:
229456fc 2890 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 2891 skip_emulated_instruction(vcpu);
2892 return 1;
2893 case 4:
229456fc 2894 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 2895 skip_emulated_instruction(vcpu);
2896 return 1;
0a5fff19
GN		 2897 case 8: {
2898 u8 cr8_prev = kvm_get_cr8(vcpu);
2899 u8 cr8 = kvm_register_read(vcpu, reg);
2900 kvm_set_cr8(vcpu, cr8);
2901 skip_emulated_instruction(vcpu);
2902 if (irqchip_in_kernel(vcpu->kvm))
2903 return 1;
2904 if (cr8_prev <= cr8)
2905 return 1;
851ba692 2906 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 2907 return 0;
2908 }
6aa8b732
AK		 2909 };
2910 break;
25c4c276 2911 case 2: /* clts */
5fd86fcf 2912 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2913 vcpu->arch.cr0 &= ~X86_CR0_TS;
2914 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2915 vmx_fpu_activate(vcpu);
25c4c276
AL		 2916 skip_emulated_instruction(vcpu);
2917 return 1;
6aa8b732
AK		 2918 case 1: /*mov from cr*/
2919 switch (cr) {
2920 case 3:
5fdbf976 2921 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 2922 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 2923 skip_emulated_instruction(vcpu);
2924 return 1;
2925 case 8:
229456fc
MT		 2926 val = kvm_get_cr8(vcpu);
2927 kvm_register_write(vcpu, reg, val);
2928 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 2929 skip_emulated_instruction(vcpu);
2930 return 1;
2931 }
2932 break;
2933 case 3: /* lmsw */
2d3ad1f4 2934 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2935
2936 skip_emulated_instruction(vcpu);
2937 return 1;
2938 default:
2939 break;
2940 }
851ba692 2941 vcpu->run->exit_reason = 0;
f0242478 2942 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2943 (int)(exit_qualification >> 4) & 3, cr);
2944 return 0;
2945}
2946
851ba692 2947static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 2948{
bfdaab09 2949 unsigned long exit_qualification;
6aa8b732
AK		 2950 unsigned long val;
2951 int dr, reg;
2952
0a79b009
AK		 2953 if (!kvm_require_cpl(vcpu, 0))
2954 return 1;
42dbaa5a
JK		 2955 dr = vmcs_readl(GUEST_DR7);
2956 if (dr & DR7_GD) {
2957 /*
2958 * As the vm-exit takes precedence over the debug trap, we
2959 * need to emulate the latter, either for the host or the
2960 * guest debugging itself.
2961 */
2962 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 2963 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
2964 vcpu->run->debug.arch.dr7 = dr;
2965 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 2966 vmcs_readl(GUEST_CS_BASE) +
2967 vmcs_readl(GUEST_RIP);
851ba692
AK		 2968 vcpu->run->debug.arch.exception = DB_VECTOR;
2969 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 2970 return 0;
2971 } else {
2972 vcpu->arch.dr7 &= ~DR7_GD;
2973 vcpu->arch.dr6 |= DR6_BD;
2974 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2975 kvm_queue_exception(vcpu, DB_VECTOR);
2976 return 1;
2977 }
2978 }
2979
bfdaab09 2980 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 2981 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2982 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2983 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 2984 switch (dr) {
42dbaa5a
JK		 2985 case 0 ... 3:
2986 val = vcpu->arch.db[dr];
2987 break;
6aa8b732 2988 case 6:
42dbaa5a 2989 val = vcpu->arch.dr6;
6aa8b732
AK		 2990 break;
2991 case 7:
42dbaa5a 2992 val = vcpu->arch.dr7;
6aa8b732
AK		 2993 break;
2994 default:
2995 val = 0;
2996 }
5fdbf976 2997 kvm_register_write(vcpu, reg, val);
6aa8b732 2998 } else {
42dbaa5a
JK		 2999 val = vcpu->arch.regs[reg];
3000 switch (dr) {
3001 case 0 ... 3:
3002 vcpu->arch.db[dr] = val;
3003 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3004 vcpu->arch.eff_db[dr] = val;
3005 break;
3006 case 4 ... 5:
3007 if (vcpu->arch.cr4 & X86_CR4_DE)
3008 kvm_queue_exception(vcpu, UD_VECTOR);
3009 break;
3010 case 6:
3011 if (val & 0xffffffff00000000ULL) {
3012 kvm_queue_exception(vcpu, GP_VECTOR);
3013 break;
3014 }
3015 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3016 break;
3017 case 7:
3018 if (val & 0xffffffff00000000ULL) {
3019 kvm_queue_exception(vcpu, GP_VECTOR);
3020 break;
3021 }
3022 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3023 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3024 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3025 vcpu->arch.switch_db_regs =
3026 (val & DR7_BP_EN_MASK);
3027 }
3028 break;
3029 }
6aa8b732 3030 }
6aa8b732
AK		 3031 skip_emulated_instruction(vcpu);
3032 return 1;
3033}
3034
851ba692 3035static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3036{
06465c5a
AK		 3037 kvm_emulate_cpuid(vcpu);
3038 return 1;
6aa8b732
AK		 3039}
3040
851ba692 3041static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3042{
ad312c7c 3043 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3044 u64 data;
3045
3046 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 3047 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3048 return 1;
3049 }
3050
229456fc 3051 trace_kvm_msr_read(ecx, data);
2714d1d3 3052
6aa8b732 3053 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3054 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3055 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3056 skip_emulated_instruction(vcpu);
3057 return 1;
3058}
3059
851ba692 3060static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3061{
ad312c7c
ZX		 3062 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3063 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3064 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 3065
229456fc 3066 trace_kvm_msr_write(ecx, data);
2714d1d3 3067
6aa8b732 3068 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 3069 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3070 return 1;
3071 }
3072
3073 skip_emulated_instruction(vcpu);
3074 return 1;
3075}
3076
851ba692 3077static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3078{
3079 return 1;
3080}
3081
851ba692 3082static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3083{
85f455f7
ED		 3084 u32 cpu_based_vm_exec_control;
3085
3086 /* clear pending irq */
3087 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3088 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3089 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3090
a26bf12a 3091 ++vcpu->stat.irq_window_exits;
2714d1d3 3092
c1150d8c
DL		 3093 /*
3094 * If the user space waits to inject interrupts, exit as soon as
3095 * possible
3096 */
8061823a 3097 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3098 vcpu->run->request_interrupt_window &&
8061823a 3099 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3100 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3101 return 0;
3102 }
6aa8b732
AK		 3103 return 1;
3104}
3105
851ba692 3106static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3107{
3108 skip_emulated_instruction(vcpu);
d3bef15f 3109 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3110}
3111
851ba692 3112static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3113{
510043da 3114 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3115 kvm_emulate_hypercall(vcpu);
3116 return 1;
c21415e8
IM		 3117}
3118
851ba692 3119static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3120{
3121 kvm_queue_exception(vcpu, UD_VECTOR);
3122 return 1;
3123}
3124
851ba692 3125static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3126{
f9c617f6 3127 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3128
3129 kvm_mmu_invlpg(vcpu, exit_qualification);
3130 skip_emulated_instruction(vcpu);
3131 return 1;
3132}
3133
851ba692 3134static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3135{
3136 skip_emulated_instruction(vcpu);
3137 /* TODO: Add support for VT-d/pass-through device */
3138 return 1;
3139}
3140
851ba692 3141static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3142{
f9c617f6 3143 unsigned long exit_qualification;
f78e0e2e
SY		 3144 enum emulation_result er;
3145 unsigned long offset;
3146
f9c617f6 3147 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3148 offset = exit_qualification & 0xffful;
3149
851ba692 3150 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3151
3152 if (er != EMULATE_DONE) {
3153 printk(KERN_ERR
3154 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3155 offset);
7f582ab6 3156 return -ENOEXEC;
f78e0e2e
SY		 3157 }
3158 return 1;
3159}
3160
851ba692 3161static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3162{
60637aac 3163 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3164 unsigned long exit_qualification;
3165 u16 tss_selector;
64a7ec06
GN		 3166 int reason, type, idt_v;
3167
3168 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3169 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3170
3171 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3172
3173 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3174 if (reason == TASK_SWITCH_GATE && idt_v) {
3175 switch (type) {
3176 case INTR_TYPE_NMI_INTR:
3177 vcpu->arch.nmi_injected = false;
3178 if (cpu_has_virtual_nmis())
3179 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3180 GUEST_INTR_STATE_NMI);
3181 break;
3182 case INTR_TYPE_EXT_INTR:
66fd3f7f 3183 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3184 kvm_clear_interrupt_queue(vcpu);
3185 break;
3186 case INTR_TYPE_HARD_EXCEPTION:
3187 case INTR_TYPE_SOFT_EXCEPTION:
3188 kvm_clear_exception_queue(vcpu);
3189 break;
3190 default:
3191 break;
3192 }
60637aac 3193 }
37817f29
IE		 3194 tss_selector = exit_qualification;
3195
64a7ec06
GN		 3196 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3197 type != INTR_TYPE_EXT_INTR &&
3198 type != INTR_TYPE_NMI_INTR))
3199 skip_emulated_instruction(vcpu);
3200
42dbaa5a
JK		 3201 if (!kvm_task_switch(vcpu, tss_selector, reason))
3202 return 0;
3203
3204 /* clear all local breakpoint enable flags */
3205 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3206
3207 /*
3208 * TODO: What about debug traps on tss switch?
3209 * Are we supposed to inject them and update dr6?
3210 */
3211
3212 return 1;
37817f29
IE		 3213}
3214
851ba692 3215static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3216{
f9c617f6 3217 unsigned long exit_qualification;
1439442c 3218 gpa_t gpa;
1439442c 3219 int gla_validity;
1439442c 3220
f9c617f6 3221 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3222
3223 if (exit_qualification & (1 << 6)) {
3224 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3225 return -EINVAL;
1439442c
SY		 3226 }
3227
3228 gla_validity = (exit_qualification >> 7) & 0x3;
3229 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3230 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3231 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3232 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3233 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3234 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3235 (long unsigned int)exit_qualification);
851ba692
AK		 3236 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3237 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3238 return 0;
1439442c
SY		 3239 }
3240
3241 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3242 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3243 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3244}
3245
68f89400
MT		 3246static u64 ept_rsvd_mask(u64 spte, int level)
3247{
3248 int i;
3249 u64 mask = 0;
3250
3251 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3252 mask |= (1ULL << i);
3253
3254 if (level > 2)
3255 /* bits 7:3 reserved */
3256 mask |= 0xf8;
3257 else if (level == 2) {
3258 if (spte & (1ULL << 7))
3259 /* 2MB ref, bits 20:12 reserved */
3260 mask |= 0x1ff000;
3261 else
3262 /* bits 6:3 reserved */
3263 mask |= 0x78;
3264 }
3265
3266 return mask;
3267}
3268
3269static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3270 int level)
3271{
3272 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3273
3274 /* 010b (write-only) */
3275 WARN_ON((spte & 0x7) == 0x2);
3276
3277 /* 110b (write/execute) */
3278 WARN_ON((spte & 0x7) == 0x6);
3279
3280 /* 100b (execute-only) and value not supported by logical processor */
3281 if (!cpu_has_vmx_ept_execute_only())
3282 WARN_ON((spte & 0x7) == 0x4);
3283
3284 /* not 000b */
3285 if ((spte & 0x7)) {
3286 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3287
3288 if (rsvd_bits != 0) {
3289 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3290 __func__, rsvd_bits);
3291 WARN_ON(1);
3292 }
3293
3294 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3295 u64 ept_mem_type = (spte & 0x38) >> 3;
3296
3297 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3298 ept_mem_type == 7) {
3299 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3300 __func__, ept_mem_type);
3301 WARN_ON(1);
3302 }
3303 }
3304 }
3305}
3306
851ba692 3307static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3308{
3309 u64 sptes[4];
3310 int nr_sptes, i;
3311 gpa_t gpa;
3312
3313 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3314
3315 printk(KERN_ERR "EPT: Misconfiguration.\n");
3316 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3317
3318 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3319
3320 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3321 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3322
851ba692
AK		 3323 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3324 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3325
3326 return 0;
3327}
3328
851ba692 3329static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3330{
3331 u32 cpu_based_vm_exec_control;
3332
3333 /* clear pending NMI */
3334 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3335 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3336 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3337 ++vcpu->stat.nmi_window_exits;
3338
3339 return 1;
3340}
3341
80ced186 3342static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3343{
8b3079a5
AK		 3344 struct vcpu_vmx *vmx = to_vmx(vcpu);
3345 enum emulation_result err = EMULATE_DONE;
80ced186 3346 int ret = 1;
ea953ef0
MG		 3347
3348 while (!guest_state_valid(vcpu)) {
851ba692 3349 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3350
80ced186
MG		 3351 if (err == EMULATE_DO_MMIO) {
3352 ret = 0;
3353 goto out;
3354 }
1d5a4d9b
GT		 3355
3356 if (err != EMULATE_DONE) {
3357 kvm_report_emulation_failure(vcpu, "emulation failure");
80ced186
MG		 3358 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3359 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 3360 vcpu->run->internal.ndata = 0;
80ced186
MG		 3361 ret = 0;
3362 goto out;
ea953ef0
MG		 3363 }
3364
3365 if (signal_pending(current))
80ced186 3366 goto out;
ea953ef0
MG		 3367 if (need_resched())
3368 schedule();
3369 }
3370
80ced186
MG		 3371 vmx->emulation_required = 0;
3372out:
3373 return ret;
ea953ef0
MG		 3374}
3375
4b8d54f9
ZE		 3376/*
3377 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3378 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3379 */
9fb41ba8 3380static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3381{
3382 skip_emulated_instruction(vcpu);
3383 kvm_vcpu_on_spin(vcpu);
3384
3385 return 1;
3386}
3387
6aa8b732
AK		 3388/*
3389 * The exit handlers return 1 if the exit was handled fully and guest execution
3390 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3391 * to be done to userspace and return 0.
3392 */
851ba692 3393static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3394 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3395 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3396 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3397 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3398 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3399 [EXIT_REASON_CR_ACCESS] = handle_cr,
3400 [EXIT_REASON_DR_ACCESS] = handle_dr,
3401 [EXIT_REASON_CPUID] = handle_cpuid,
3402 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3403 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3404 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3405 [EXIT_REASON_HLT] = handle_halt,
a7052897 3406 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3407 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3408 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3409 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3410 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3411 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3412 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3413 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3414 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3415 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3416 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3417 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3418 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3419 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3420 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3421 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3422 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3423 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3424 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
6aa8b732
AK		 3425};
3426
3427static const int kvm_vmx_max_exit_handlers =
50a3485c 3428 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3429
3430/*
3431 * The guest has exited. See if we can fix it or if we need userspace
3432 * assistance.
3433 */
851ba692 3434static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3435{
29bd8a78 3436 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3437 u32 exit_reason = vmx->exit_reason;
1155f76a 3438 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3439
229456fc 3440 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3441
80ced186
MG		 3442 /* If guest state is invalid, start emulating */
3443 if (vmx->emulation_required && emulate_invalid_guest_state)
3444 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3445
1439442c
SY		 3446 /* Access CR3 don't cause VMExit in paging mode, so we need
3447 * to sync with guest real CR3. */
6de4f3ad 3448 if (enable_ept && is_paging(vcpu))
1439442c 3449 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3450
29bd8a78 3451 if (unlikely(vmx->fail)) {
851ba692
AK		 3452 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3453 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3454 = vmcs_read32(VM_INSTRUCTION_ERROR);
3455 return 0;
3456 }
6aa8b732 3457
d77c26fc 3458 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3459 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3460 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3461 exit_reason != EXIT_REASON_TASK_SWITCH))
3462 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3463 "(0x%x) and exit reason is 0x%x\n",
3464 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3465
3466 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3467 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3468 vmx->soft_vnmi_blocked = 0;
3b86cd99 3469 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3470 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3471 /*
3472 * This CPU don't support us in finding the end of an
3473 * NMI-blocked window if the guest runs with IRQs
3474 * disabled. So we pull the trigger after 1 s of
3475 * futile waiting, but inform the user about this.
3476 */
3477 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3478 "state on VCPU %d after 1 s timeout\n",
3479 __func__, vcpu->vcpu_id);
3480 vmx->soft_vnmi_blocked = 0;
3b86cd99 3481 }
3b86cd99
JK		 3482 }
3483
6aa8b732
AK		 3484 if (exit_reason < kvm_vmx_max_exit_handlers
3485 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3486 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3487 else {
851ba692
AK		 3488 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3489 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3490 }
3491 return 0;
3492}
3493
95ba8273 3494static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3495{
95ba8273 3496 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3497 vmcs_write32(TPR_THRESHOLD, 0);
3498 return;
3499 }
3500
95ba8273 3501 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3502}
3503
cf393f75
AK		 3504static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3505{
3506 u32 exit_intr_info;
7b4a25cb 3507 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3508 bool unblock_nmi;
3509 u8 vector;
668f612f
AK		 3510 int type;
3511 bool idtv_info_valid;
cf393f75
AK		 3512
3513 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3514
a0861c02
AK		 3515 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3516
3517 /* Handle machine checks before interrupts are enabled */
3518 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3519 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3520 && is_machine_check(exit_intr_info)))
3521 kvm_machine_check();
3522
20f65983
GN		 3523 /* We need to handle NMIs before interrupts are enabled */
3524 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3525 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3526 asm("int $2");
20f65983
GN		 3527
3528 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3529
cf393f75
AK		 3530 if (cpu_has_virtual_nmis()) {
3531 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3532 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3533 /*
7b4a25cb 3534 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3535 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3536 * a guest IRET fault.
7b4a25cb
GN		 3537 * SDM 3: 23.2.2 (September 2008)
3538 * Bit 12 is undefined in any of the following cases:
3539 * If the VM exit sets the valid bit in the IDT-vectoring
3540 * information field.
3541 * If the VM exit is due to a double fault.
cf393f75 3542 */
7b4a25cb
GN		 3543 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3544 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3545 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3546 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3547 } else if (unlikely(vmx->soft_vnmi_blocked))
3548 vmx->vnmi_blocked_time +=
3549 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3550
37b96e98
GN		 3551 vmx->vcpu.arch.nmi_injected = false;
3552 kvm_clear_exception_queue(&vmx->vcpu);
3553 kvm_clear_interrupt_queue(&vmx->vcpu);
3554
3555 if (!idtv_info_valid)
3556 return;
3557
668f612f
AK		 3558 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3559 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3560
64a7ec06 3561 switch (type) {
37b96e98
GN		 3562 case INTR_TYPE_NMI_INTR:
3563 vmx->vcpu.arch.nmi_injected = true;
668f612f 3564 /*
7b4a25cb 3565 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3566 * Clear bit "block by NMI" before VM entry if a NMI
3567 * delivery faulted.
668f612f 3568 */
37b96e98
GN		 3569 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3570 GUEST_INTR_STATE_NMI);
3571 break;
37b96e98 3572 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3573 vmx->vcpu.arch.event_exit_inst_len =
3574 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3575 /* fall through */
3576 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3577 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3578 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3579 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3580 } else
3581 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3582 break;
66fd3f7f
GN		 3583 case INTR_TYPE_SOFT_INTR:
3584 vmx->vcpu.arch.event_exit_inst_len =
3585 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3586 /* fall through */
37b96e98 3587 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3588 kvm_queue_interrupt(&vmx->vcpu, vector,
3589 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3590 break;
3591 default:
3592 break;
f7d9238f 3593 }
cf393f75
AK		 3594}
3595
9c8cba37
AK		 3596/*
3597 * Failure to inject an interrupt should give us the information
3598 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3599 * when fetching the interrupt redirection bitmap in the real-mode
3600 * tss, this doesn't happen. So we do it ourselves.
3601 */
3602static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3603{
3604 vmx->rmode.irq.pending = 0;
5fdbf976 3605 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3606 return;
5fdbf976 3607 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3608 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3609 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3610 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3611 return;
3612 }
3613 vmx->idt_vectoring_info =
3614 VECTORING_INFO_VALID_MASK
3615 | INTR_TYPE_EXT_INTR
3616 | vmx->rmode.irq.vector;
3617}
3618
c801949d
AK		 3619#ifdef CONFIG_X86_64
3620#define R "r"
3621#define Q "q"
3622#else
3623#define R "e"
3624#define Q "l"
3625#endif
3626
851ba692 3627static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3628{
a2fa3e9f 3629 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3630
3b86cd99
JK		 3631 /* Record the guest's net vcpu time for enforced NMI injections. */
3632 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3633 vmx->entry_time = ktime_get();
3634
80ced186
MG		 3635 /* Don't enter VMX if guest state is invalid, let the exit handler
3636 start emulation until we arrive back to a valid state */
3637 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3638 return;
a89a8fb9 3639
5fdbf976
MT		 3640 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3641 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3642 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3643 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3644
787ff736
GN		 3645 /* When single-stepping over STI and MOV SS, we must clear the
3646 * corresponding interruptibility bits in the guest state. Otherwise
3647 * vmentry fails as it then expects bit 14 (BS) in pending debug
3648 * exceptions being set, but that's not correct for the guest debugging
3649 * case. */
3650 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3651 vmx_set_interrupt_shadow(vcpu, 0);
3652
e6adf283
AK		 3653 /*
3654 * Loading guest fpu may have cleared host cr0.ts
3655 */
3656 vmcs_writel(HOST_CR0, read_cr0());
3657
e8a48342
AK		 3658 if (vcpu->arch.switch_db_regs)
3659 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3660
d77c26fc 3661 asm(
6aa8b732 3662 /* Store host registers */
c801949d
AK		 3663 "push %%"R"dx; push %%"R"bp;"
3664 "push %%"R"cx \n\t"
313dbd49
AK		 3665 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3666 "je 1f \n\t"
3667 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3668 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3669 "1: \n\t"
d3edefc0
AK		 3670 /* Reload cr2 if changed */
3671 "mov %c[cr2](%0), %%"R"ax \n\t"
3672 "mov %%cr2, %%"R"dx \n\t"
3673 "cmp %%"R"ax, %%"R"dx \n\t"
3674 "je 2f \n\t"
3675 "mov %%"R"ax, %%cr2 \n\t"
3676 "2: \n\t"
6aa8b732 3677 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3678 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3679 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3680 "mov %c[rax](%0), %%"R"ax \n\t"
3681 "mov %c[rbx](%0), %%"R"bx \n\t"
3682 "mov %c[rdx](%0), %%"R"dx \n\t"
3683 "mov %c[rsi](%0), %%"R"si \n\t"
3684 "mov %c[rdi](%0), %%"R"di \n\t"
3685 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3686#ifdef CONFIG_X86_64
e08aa78a
AK		 3687 "mov %c[r8](%0), %%r8 \n\t"
3688 "mov %c[r9](%0), %%r9 \n\t"
3689 "mov %c[r10](%0), %%r10 \n\t"
3690 "mov %c[r11](%0), %%r11 \n\t"
3691 "mov %c[r12](%0), %%r12 \n\t"
3692 "mov %c[r13](%0), %%r13 \n\t"
3693 "mov %c[r14](%0), %%r14 \n\t"
3694 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3695#endif
c801949d
AK		 3696 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3697
6aa8b732 3698 /* Enter guest mode */
cd2276a7 3699 "jne .Llaunched \n\t"
4ecac3fd 3700 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3701 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3702 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3703 ".Lkvm_vmx_return: "
6aa8b732 3704 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3705 "xchg %0, (%%"R"sp) \n\t"
3706 "mov %%"R"ax, %c[rax](%0) \n\t"
3707 "mov %%"R"bx, %c[rbx](%0) \n\t"
3708 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3709 "mov %%"R"dx, %c[rdx](%0) \n\t"
3710 "mov %%"R"si, %c[rsi](%0) \n\t"
3711 "mov %%"R"di, %c[rdi](%0) \n\t"
3712 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3713#ifdef CONFIG_X86_64
e08aa78a
AK		 3714 "mov %%r8, %c[r8](%0) \n\t"
3715 "mov %%r9, %c[r9](%0) \n\t"
3716 "mov %%r10, %c[r10](%0) \n\t"
3717 "mov %%r11, %c[r11](%0) \n\t"
3718 "mov %%r12, %c[r12](%0) \n\t"
3719 "mov %%r13, %c[r13](%0) \n\t"
3720 "mov %%r14, %c[r14](%0) \n\t"
3721 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3722#endif
c801949d
AK		 3723 "mov %%cr2, %%"R"ax \n\t"
3724 "mov %%"R"ax, %c[cr2](%0) \n\t"
3725
3726 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3727 "setbe %c[fail](%0) \n\t"
3728 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3729 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3730 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3731 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3732 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3733 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3734 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3735 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3736 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3737 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3738 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3739#ifdef CONFIG_X86_64
ad312c7c
ZX		 3740 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3741 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3742 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3743 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3744 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3745 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3746 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3747 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3748#endif
ad312c7c 3749 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3750 : "cc", "memory"
c801949d 3751 , R"bx", R"di", R"si"
c2036300 3752#ifdef CONFIG_X86_64
c2036300
LV		 3753 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3754#endif
3755 );
6aa8b732 3756
6de4f3ad
AK		 3757 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3758 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3759 vcpu->arch.regs_dirty = 0;
3760
e8a48342
AK		 3761 if (vcpu->arch.switch_db_regs)
3762 get_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3763
1155f76a 3764 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3765 if (vmx->rmode.irq.pending)
3766 fixup_rmode_irq(vmx);
1155f76a 3767
d77c26fc 3768 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3769 vmx->launched = 1;
1b6269db 3770
cf393f75 3771 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3772}
3773
c801949d
AK		 3774#undef R
3775#undef Q
3776
6aa8b732
AK		 3777static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3778{
a2fa3e9f
GH		 3779 struct vcpu_vmx *vmx = to_vmx(vcpu);
3780
3781 if (vmx->vmcs) {
543e4243 3782 vcpu_clear(vmx);
a2fa3e9f
GH		 3783 free_vmcs(vmx->vmcs);
3784 vmx->vmcs = NULL;
6aa8b732
AK		 3785 }
3786}
3787
3788static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3789{
fb3f0f51
RR		 3790 struct vcpu_vmx *vmx = to_vmx(vcpu);
3791
2384d2b3
SY		 3792 spin_lock(&vmx_vpid_lock);
3793 if (vmx->vpid != 0)
3794 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3795 spin_unlock(&vmx_vpid_lock);
6aa8b732 3796 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3797 kfree(vmx->guest_msrs);
3798 kvm_vcpu_uninit(vcpu);
a4770347 3799 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3800}
3801
fb3f0f51 3802static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3803{
fb3f0f51 3804 int err;
c16f862d 3805 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3806 int cpu;
6aa8b732 3807
a2fa3e9f 3808 if (!vmx)
fb3f0f51
RR		 3809 return ERR_PTR(-ENOMEM);
3810
2384d2b3
SY		 3811 allocate_vpid(vmx);
3812
fb3f0f51
RR		 3813 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3814 if (err)
3815 goto free_vcpu;
965b58a5 3816
a2fa3e9f 3817 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3818 if (!vmx->guest_msrs) {
3819 err = -ENOMEM;
3820 goto uninit_vcpu;
3821 }
965b58a5 3822
a2fa3e9f
GH		 3823 vmx->vmcs = alloc_vmcs();
3824 if (!vmx->vmcs)
fb3f0f51 3825 goto free_msrs;
a2fa3e9f
GH		 3826
3827 vmcs_clear(vmx->vmcs);
3828
15ad7146
AK		 3829 cpu = get_cpu();
3830 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3831 err = vmx_vcpu_setup(vmx);
fb3f0f51 3832 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3833 put_cpu();
fb3f0f51
RR		 3834 if (err)
3835 goto free_vmcs;
5e4a0b3c
MT		 3836 if (vm_need_virtualize_apic_accesses(kvm))
3837 if (alloc_apic_access_page(kvm) != 0)
3838 goto free_vmcs;
fb3f0f51 3839
b927a3ce
SY		 3840 if (enable_ept) {
3841 if (!kvm->arch.ept_identity_map_addr)
3842 kvm->arch.ept_identity_map_addr =
3843 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3844 if (alloc_identity_pagetable(kvm) != 0)
3845 goto free_vmcs;
b927a3ce 3846 }
b7ebfb05 3847
fb3f0f51
RR		 3848 return &vmx->vcpu;
3849
3850free_vmcs:
3851 free_vmcs(vmx->vmcs);
3852free_msrs:
fb3f0f51
RR		 3853 kfree(vmx->guest_msrs);
3854uninit_vcpu:
3855 kvm_vcpu_uninit(&vmx->vcpu);
3856free_vcpu:
a4770347 3857 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3858 return ERR_PTR(err);
6aa8b732
AK		 3859}
3860
002c7f7c
YS		 3861static void __init vmx_check_processor_compat(void *rtn)
3862{
3863 struct vmcs_config vmcs_conf;
3864
3865 *(int *)rtn = 0;
3866 if (setup_vmcs_config(&vmcs_conf) < 0)
3867 *(int *)rtn = -EIO;
3868 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3869 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3870 smp_processor_id());
3871 *(int *)rtn = -EIO;
3872 }
3873}
3874
67253af5
SY		 3875static int get_ept_level(void)
3876{
3877 return VMX_EPT_DEFAULT_GAW + 1;
3878}
3879
4b12f0de 3880static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3881{
4b12f0de
SY		 3882 u64 ret;
3883
522c68c4
SY		 3884 /* For VT-d and EPT combination
3885 * 1. MMIO: always map as UC
3886 * 2. EPT with VT-d:
3887 * a. VT-d without snooping control feature: can't guarantee the
3888 * result, try to trust guest.
3889 * b. VT-d with snooping control feature: snooping control feature of
3890 * VT-d engine can guarantee the cache correctness. Just set it
3891 * to WB to keep consistent with host. So the same as item 3.
3892 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3893 * consistent with host MTRR
3894 */
4b12f0de
SY		 3895 if (is_mmio)
3896 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 3897 else if (vcpu->kvm->arch.iommu_domain &&
3898 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3899 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3900 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 3901 else
522c68c4
SY		 3902 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3903 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 3904
3905 return ret;
64d4d521
SY		 3906}
3907
229456fc
MT		 3908static const struct trace_print_flags vmx_exit_reasons_str[] = {
3909 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3910 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3911 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3912 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3913 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3914 { EXIT_REASON_CR_ACCESS, "cr_access" },
3915 { EXIT_REASON_DR_ACCESS, "dr_access" },
3916 { EXIT_REASON_CPUID, "cpuid" },
3917 { EXIT_REASON_MSR_READ, "rdmsr" },
3918 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3919 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3920 { EXIT_REASON_HLT, "halt" },
3921 { EXIT_REASON_INVLPG, "invlpg" },
3922 { EXIT_REASON_VMCALL, "hypercall" },
3923 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3924 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3925 { EXIT_REASON_WBINVD, "wbinvd" },
3926 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3927 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3928 { -1, NULL }
3929};
3930
344f414f
JR		 3931static bool vmx_gb_page_enable(void)
3932{
3933 return false;
3934}
3935
cbdd1bea 3936static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3937 .cpu_has_kvm_support = cpu_has_kvm_support,
3938 .disabled_by_bios = vmx_disabled_by_bios,
3939 .hardware_setup = hardware_setup,
3940 .hardware_unsetup = hardware_unsetup,
002c7f7c 3941 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3942 .hardware_enable = hardware_enable,
3943 .hardware_disable = hardware_disable,
04547156 3944 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 3945
3946 .vcpu_create = vmx_create_vcpu,
3947 .vcpu_free = vmx_free_vcpu,
04d2cc77 3948 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3949
04d2cc77 3950 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3951 .vcpu_load = vmx_vcpu_load,
3952 .vcpu_put = vmx_vcpu_put,
3953
3954 .set_guest_debug = set_guest_debug,
3955 .get_msr = vmx_get_msr,
3956 .set_msr = vmx_set_msr,
3957 .get_segment_base = vmx_get_segment_base,
3958 .get_segment = vmx_get_segment,
3959 .set_segment = vmx_set_segment,
2e4d2653 3960 .get_cpl = vmx_get_cpl,
6aa8b732 3961 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3962 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3963 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3964 .set_cr3 = vmx_set_cr3,
3965 .set_cr4 = vmx_set_cr4,
6aa8b732 3966 .set_efer = vmx_set_efer,
6aa8b732
AK		 3967 .get_idt = vmx_get_idt,
3968 .set_idt = vmx_set_idt,
3969 .get_gdt = vmx_get_gdt,
3970 .set_gdt = vmx_set_gdt,
5fdbf976 3971 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3972 .get_rflags = vmx_get_rflags,
3973 .set_rflags = vmx_set_rflags,
3974
3975 .tlb_flush = vmx_flush_tlb,
6aa8b732 3976
6aa8b732 3977 .run = vmx_vcpu_run,
6062d012 3978 .handle_exit = vmx_handle_exit,
6aa8b732 3979 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3980 .set_interrupt_shadow = vmx_set_interrupt_shadow,
3981 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 3982 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 3983 .set_irq = vmx_inject_irq,
95ba8273 3984 .set_nmi = vmx_inject_nmi,
298101da 3985 .queue_exception = vmx_queue_exception,
78646121 3986 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273
GN		 3987 .nmi_allowed = vmx_nmi_allowed,
3988 .enable_nmi_window = enable_nmi_window,
3989 .enable_irq_window = enable_irq_window,
3990 .update_cr8_intercept = update_cr8_intercept,
95ba8273 3991
cbc94022 3992 .set_tss_addr = vmx_set_tss_addr,
67253af5 3993 .get_tdp_level = get_ept_level,
4b12f0de 3994 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 3995
3996 .exit_reasons_str = vmx_exit_reasons_str,
344f414f 3997 .gb_page_enable = vmx_gb_page_enable,
6aa8b732
AK		 3998};
3999
4000static int __init vmx_init(void)
4001{
26bb0981
AK		 4002 int r, i;
4003
4004 rdmsrl_safe(MSR_EFER, &host_efer);
4005
4006 for (i = 0; i < NR_VMX_MSR; ++i)
4007 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4008
3e7c73e9 4009 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4010 if (!vmx_io_bitmap_a)
4011 return -ENOMEM;
4012
3e7c73e9 4013 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4014 if (!vmx_io_bitmap_b) {
4015 r = -ENOMEM;
4016 goto out;
4017 }
4018
5897297b
AK		 4019 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4020 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4021 r = -ENOMEM;
4022 goto out1;
4023 }
4024
5897297b
AK		 4025 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4026 if (!vmx_msr_bitmap_longmode) {
4027 r = -ENOMEM;
4028 goto out2;
4029 }
4030
fdef3ad1
HQ		 4031 /*
4032 * Allow direct access to the PC debug port (it is often used for I/O
4033 * delays, but the vmexits simply slow things down).
4034 */
3e7c73e9
AK		 4035 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4036 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4037
3e7c73e9 4038 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4039
5897297b
AK		 4040 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4041 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4042
2384d2b3
SY		 4043 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4044
cb498ea2 4045 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4046 if (r)
5897297b 4047 goto out3;
25c5f225 4048
5897297b
AK		 4049 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4050 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4051 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4052 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4053 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4054 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4055
089d034e 4056 if (enable_ept) {
1439442c 4057 bypass_guest_pf = 0;
5fdbcb9d 4058 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4059 VMX_EPT_WRITABLE_MASK);
534e38b4 4060 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4061 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4062 kvm_enable_tdp();
4063 } else
4064 kvm_disable_tdp();
1439442c 4065
c7addb90
AK		 4066 if (bypass_guest_pf)
4067 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4068
fdef3ad1
HQ		 4069 return 0;
4070
5897297b
AK		 4071out3:
4072 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4073out2:
5897297b 4074 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4075out1:
3e7c73e9 4076 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4077out:
3e7c73e9 4078 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4079 return r;
6aa8b732
AK		 4080}
4081
4082static void __exit vmx_exit(void)
4083{
5897297b
AK		 4084 free_page((unsigned long)vmx_msr_bitmap_legacy);
4085 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4086 free_page((unsigned long)vmx_io_bitmap_b);
4087 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4088
cb498ea2 4089 kvm_exit();
6aa8b732
AK		 4090}
4091
4092module_init(vmx_init)
4093module_exit(vmx_exit)
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