]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/x86/kvm/vmx.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: fix LAPIC timer period overflow
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
13673a90 34#include <asm/vmx.h>
6210e37b 35#include <asm/virtext.h>
a0861c02 36#include <asm/mce.h>
6aa8b732 37
229456fc
MT		 38#include "trace.h"
39
4ecac3fd
AK		 40#define __ex(x) __kvm_handle_fault_on_reboot(x)
41
6aa8b732
AK		 42MODULE_AUTHOR("Qumranet");
43MODULE_LICENSE("GPL");
44
4462d21a 45static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 46module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 47
4462d21a 48static int __read_mostly enable_vpid = 1;
736caefe 49module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 50
4462d21a 51static int __read_mostly flexpriority_enabled = 1;
736caefe 52module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 53
4462d21a 54static int __read_mostly enable_ept = 1;
736caefe 55module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 56
3a624e29
NK		 57static int __read_mostly enable_unrestricted_guest = 1;
58module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
4462d21a 61static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 62module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 63
a2fa3e9f
GH		 64struct vmcs {
65 u32 revision_id;
66 u32 abort;
67 char data[0];
68};
69
70struct vcpu_vmx {
fb3f0f51 71 struct kvm_vcpu vcpu;
543e4243 72 struct list_head local_vcpus_link;
313dbd49 73 unsigned long host_rsp;
a2fa3e9f 74 int launched;
29bd8a78 75 u8 fail;
1155f76a 76 u32 idt_vectoring_info;
a2fa3e9f
GH		 77 struct kvm_msr_entry *guest_msrs;
78 struct kvm_msr_entry *host_msrs;
79 int nmsrs;
80 int save_nmsrs;
81 int msr_offset_efer;
82#ifdef CONFIG_X86_64
83 int msr_offset_kernel_gs_base;
84#endif
85 struct vmcs *vmcs;
86 struct {
87 int loaded;
88 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 89 int gs_ldt_reload_needed;
90 int fs_reload_needed;
51c6cf66 91 int guest_efer_loaded;
d77c26fc 92 } host_state;
9c8cba37 93 struct {
7ffd92c5
AK		 94 int vm86_active;
95 u8 save_iopl;
96 struct kvm_save_segment {
97 u16 selector;
98 unsigned long base;
99 u32 limit;
100 u32 ar;
101 } tr, es, ds, fs, gs;
9c8cba37
AK		 102 struct {
103 bool pending;
104 u8 vector;
105 unsigned rip;
106 } irq;
107 } rmode;
2384d2b3 108 int vpid;
04fa4d32 109 bool emulation_required;
8b3079a5 110 enum emulation_result invalid_state_emulation_result;
3b86cd99
JK		 111
112 /* Support for vnmi-less CPUs */
113 int soft_vnmi_blocked;
114 ktime_t entry_time;
115 s64 vnmi_blocked_time;
a0861c02 116 u32 exit_reason;
a2fa3e9f
GH		 117};
118
119static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
120{
fb3f0f51 121 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 122}
123
b7ebfb05 124static int init_rmode(struct kvm *kvm);
4e1096d2 125static u64 construct_eptp(unsigned long root_hpa);
75880a01 126
6aa8b732
AK		 127static DEFINE_PER_CPU(struct vmcs *, vmxarea);
128static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 129static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 130
3e7c73e9
AK		 131static unsigned long *vmx_io_bitmap_a;
132static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 133static unsigned long *vmx_msr_bitmap_legacy;
134static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 135
2384d2b3
SY		 136static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
137static DEFINE_SPINLOCK(vmx_vpid_lock);
138
1c3d14fe 139static struct vmcs_config {
6aa8b732
AK		 140 int size;
141 int order;
142 u32 revision_id;
1c3d14fe
YS		 143 u32 pin_based_exec_ctrl;
144 u32 cpu_based_exec_ctrl;
f78e0e2e 145 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 146 u32 vmexit_ctrl;
147 u32 vmentry_ctrl;
148} vmcs_config;
6aa8b732 149
efff9e53 150static struct vmx_capability {
d56f546d
SY		 151 u32 ept;
152 u32 vpid;
153} vmx_capability;
154
6aa8b732
AK		 155#define VMX_SEGMENT_FIELD(seg) \
156 [VCPU_SREG_##seg] = { \
157 .selector = GUEST_##seg##_SELECTOR, \
158 .base = GUEST_##seg##_BASE, \
159 .limit = GUEST_##seg##_LIMIT, \
160 .ar_bytes = GUEST_##seg##_AR_BYTES, \
161 }
162
163static struct kvm_vmx_segment_field {
164 unsigned selector;
165 unsigned base;
166 unsigned limit;
167 unsigned ar_bytes;
168} kvm_vmx_segment_fields[] = {
169 VMX_SEGMENT_FIELD(CS),
170 VMX_SEGMENT_FIELD(DS),
171 VMX_SEGMENT_FIELD(ES),
172 VMX_SEGMENT_FIELD(FS),
173 VMX_SEGMENT_FIELD(GS),
174 VMX_SEGMENT_FIELD(SS),
175 VMX_SEGMENT_FIELD(TR),
176 VMX_SEGMENT_FIELD(LDTR),
177};
178
6de4f3ad
AK		 179static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
180
4d56c8a7
AK		 181/*
182 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
183 * away by decrementing the array size.
184 */
6aa8b732 185static const u32 vmx_msr_index[] = {
05b3e0c2 186#ifdef CONFIG_X86_64
6aa8b732
AK		 187 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
188#endif
189 MSR_EFER, MSR_K6_STAR,
190};
9d8f549d 191#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 192
a2fa3e9f
GH		 193static void load_msrs(struct kvm_msr_entry *e, int n)
194{
195 int i;
196
197 for (i = 0; i < n; ++i)
198 wrmsrl(e[i].index, e[i].data);
199}
200
201static void save_msrs(struct kvm_msr_entry *e, int n)
202{
203 int i;
204
205 for (i = 0; i < n; ++i)
206 rdmsrl(e[i].index, e[i].data);
207}
208
6aa8b732
AK		 209static inline int is_page_fault(u32 intr_info)
210{
211 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
212 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 213 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 214}
215
2ab455cc
AL		 216static inline int is_no_device(u32 intr_info)
217{
218 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
219 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 220 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 221}
222
7aa81cc0
AL		 223static inline int is_invalid_opcode(u32 intr_info)
224{
225 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
226 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 227 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 228}
229
6aa8b732
AK		 230static inline int is_external_interrupt(u32 intr_info)
231{
232 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
233 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
234}
235
a0861c02
AK		 236static inline int is_machine_check(u32 intr_info)
237{
238 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
239 INTR_INFO_VALID_MASK)) ==
240 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
241}
242
25c5f225
SY		 243static inline int cpu_has_vmx_msr_bitmap(void)
244{
04547156 245 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 246}
247
6e5d865c
YS		 248static inline int cpu_has_vmx_tpr_shadow(void)
249{
04547156 250 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 251}
252
253static inline int vm_need_tpr_shadow(struct kvm *kvm)
254{
04547156 255 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 256}
257
f78e0e2e
SY		 258static inline int cpu_has_secondary_exec_ctrls(void)
259{
04547156
SY		 260 return vmcs_config.cpu_based_exec_ctrl &
261 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 262}
263
774ead3a 264static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 265{
04547156
SY		 266 return vmcs_config.cpu_based_2nd_exec_ctrl &
267 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
268}
269
270static inline bool cpu_has_vmx_flexpriority(void)
271{
272 return cpu_has_vmx_tpr_shadow() &&
273 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 274}
275
e799794e
MT		 276static inline bool cpu_has_vmx_ept_execute_only(void)
277{
278 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
279}
280
281static inline bool cpu_has_vmx_eptp_uncacheable(void)
282{
283 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
284}
285
286static inline bool cpu_has_vmx_eptp_writeback(void)
287{
288 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
289}
290
291static inline bool cpu_has_vmx_ept_2m_page(void)
292{
293 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
294}
295
d56f546d
SY		 296static inline int cpu_has_vmx_invept_individual_addr(void)
297{
04547156 298 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 299}
300
301static inline int cpu_has_vmx_invept_context(void)
302{
04547156 303 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 304}
305
306static inline int cpu_has_vmx_invept_global(void)
307{
04547156 308 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 309}
310
311static inline int cpu_has_vmx_ept(void)
312{
04547156
SY		 313 return vmcs_config.cpu_based_2nd_exec_ctrl &
314 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 315}
316
3a624e29
NK		 317static inline int cpu_has_vmx_unrestricted_guest(void)
318{
319 return vmcs_config.cpu_based_2nd_exec_ctrl &
320 SECONDARY_EXEC_UNRESTRICTED_GUEST;
321}
322
f78e0e2e
SY		 323static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
324{
04547156
SY		 325 return flexpriority_enabled &&
326 (cpu_has_vmx_virtualize_apic_accesses()) &&
327 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 328}
329
2384d2b3
SY		 330static inline int cpu_has_vmx_vpid(void)
331{
04547156
SY		 332 return vmcs_config.cpu_based_2nd_exec_ctrl &
333 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 334}
335
f08864b4
SY		 336static inline int cpu_has_virtual_nmis(void)
337{
338 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
339}
340
04547156
SY		 341static inline bool report_flexpriority(void)
342{
343 return flexpriority_enabled;
344}
345
8b9cf98c 346static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 347{
348 int i;
349
a2fa3e9f
GH		 350 for (i = 0; i < vmx->nmsrs; ++i)
351 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 352 return i;
353 return -1;
354}
355
2384d2b3
SY		 356static inline void __invvpid(int ext, u16 vpid, gva_t gva)
357{
358 struct {
359 u64 vpid : 16;
360 u64 rsvd : 48;
361 u64 gva;
362 } operand = { vpid, 0, gva };
363
4ecac3fd 364 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 365 /* CF==1 or ZF==1 --> rc = -1 */
366 "; ja 1f ; ud2 ; 1:"
367 : : "a"(&operand), "c"(ext) : "cc", "memory");
368}
369
1439442c
SY		 370static inline void __invept(int ext, u64 eptp, gpa_t gpa)
371{
372 struct {
373 u64 eptp, gpa;
374 } operand = {eptp, gpa};
375
4ecac3fd 376 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 377 /* CF==1 or ZF==1 --> rc = -1 */
378 "; ja 1f ; ud2 ; 1:\n"
379 : : "a" (&operand), "c" (ext) : "cc", "memory");
380}
381
8b9cf98c 382static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 383{
384 int i;
385
8b9cf98c 386 i = __find_msr_index(vmx, msr);
a75beee6 387 if (i >= 0)
a2fa3e9f 388 return &vmx->guest_msrs[i];
8b6d44c7 389 return NULL;
7725f0ba
AK		 390}
391
6aa8b732
AK		 392static void vmcs_clear(struct vmcs *vmcs)
393{
394 u64 phys_addr = __pa(vmcs);
395 u8 error;
396
4ecac3fd 397 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 398 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
399 : "cc", "memory");
400 if (error)
401 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
402 vmcs, phys_addr);
403}
404
405static void __vcpu_clear(void *arg)
406{
8b9cf98c 407 struct vcpu_vmx *vmx = arg;
d3b2c338 408 int cpu = raw_smp_processor_id();
6aa8b732 409
8b9cf98c 410 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 411 vmcs_clear(vmx->vmcs);
412 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 413 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 414 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 415 list_del(&vmx->local_vcpus_link);
416 vmx->vcpu.cpu = -1;
417 vmx->launched = 0;
6aa8b732
AK		 418}
419
8b9cf98c 420static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 421{
eae5ecb5
AK		 422 if (vmx->vcpu.cpu == -1)
423 return;
8691e5a8 424 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 425}
426
2384d2b3
SY		 427static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
428{
429 if (vmx->vpid == 0)
430 return;
431
432 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
433}
434
1439442c
SY		 435static inline void ept_sync_global(void)
436{
437 if (cpu_has_vmx_invept_global())
438 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
439}
440
441static inline void ept_sync_context(u64 eptp)
442{
089d034e 443 if (enable_ept) {
1439442c
SY		 444 if (cpu_has_vmx_invept_context())
445 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
446 else
447 ept_sync_global();
448 }
449}
450
451static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
452{
089d034e 453 if (enable_ept) {
1439442c
SY		 454 if (cpu_has_vmx_invept_individual_addr())
455 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
456 eptp, gpa);
457 else
458 ept_sync_context(eptp);
459 }
460}
461
6aa8b732
AK		 462static unsigned long vmcs_readl(unsigned long field)
463{
464 unsigned long value;
465
4ecac3fd 466 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 467 : "=a"(value) : "d"(field) : "cc");
468 return value;
469}
470
471static u16 vmcs_read16(unsigned long field)
472{
473 return vmcs_readl(field);
474}
475
476static u32 vmcs_read32(unsigned long field)
477{
478 return vmcs_readl(field);
479}
480
481static u64 vmcs_read64(unsigned long field)
482{
05b3e0c2 483#ifdef CONFIG_X86_64
6aa8b732
AK		 484 return vmcs_readl(field);
485#else
486 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
487#endif
488}
489
e52de1b8
AK		 490static noinline void vmwrite_error(unsigned long field, unsigned long value)
491{
492 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
493 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
494 dump_stack();
495}
496
6aa8b732
AK		 497static void vmcs_writel(unsigned long field, unsigned long value)
498{
499 u8 error;
500
4ecac3fd 501 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 502 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 503 if (unlikely(error))
504 vmwrite_error(field, value);
6aa8b732
AK		 505}
506
507static void vmcs_write16(unsigned long field, u16 value)
508{
509 vmcs_writel(field, value);
510}
511
512static void vmcs_write32(unsigned long field, u32 value)
513{
514 vmcs_writel(field, value);
515}
516
517static void vmcs_write64(unsigned long field, u64 value)
518{
6aa8b732 519 vmcs_writel(field, value);
7682f2d0 520#ifndef CONFIG_X86_64
6aa8b732
AK		 521 asm volatile ("");
522 vmcs_writel(field+1, value >> 32);
523#endif
524}
525
2ab455cc
AL		 526static void vmcs_clear_bits(unsigned long field, u32 mask)
527{
528 vmcs_writel(field, vmcs_readl(field) & ~mask);
529}
530
531static void vmcs_set_bits(unsigned long field, u32 mask)
532{
533 vmcs_writel(field, vmcs_readl(field) | mask);
534}
535
abd3f2d6
AK		 536static void update_exception_bitmap(struct kvm_vcpu *vcpu)
537{
538 u32 eb;
539
a0861c02 540 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
abd3f2d6
AK		 541 if (!vcpu->fpu_active)
542 eb |= 1u << NM_VECTOR;
e8a48342
AK		 543 /*
544 * Unconditionally intercept #DB so we can maintain dr6 without
545 * reading it every exit.
546 */
547 eb |= 1u << DB_VECTOR;
d0bfb940 548 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940
JK		 549 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
550 eb |= 1u << BP_VECTOR;
551 }
7ffd92c5 552 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 553 eb = ~0;
089d034e 554 if (enable_ept)
1439442c 555 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 556 vmcs_write32(EXCEPTION_BITMAP, eb);
557}
558
33ed6329
AK		 559static void reload_tss(void)
560{
33ed6329
AK		 561 /*
562 * VT restores TR but not its size. Useless.
563 */
564 struct descriptor_table gdt;
a5f61300 565 struct desc_struct *descs;
33ed6329 566
d6e88aec 567 kvm_get_gdt(&gdt);
33ed6329
AK		 568 descs = (void *)gdt.base;
569 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
570 load_TR_desc();
33ed6329
AK		 571}
572
8b9cf98c 573static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 574{
a2fa3e9f 575 int efer_offset = vmx->msr_offset_efer;
3a34a881
RK		 576 u64 host_efer;
577 u64 guest_efer;
51c6cf66
AK		 578 u64 ignore_bits;
579
580 if (efer_offset < 0)
581 return;
3a34a881
RK		 582 host_efer = vmx->host_msrs[efer_offset].data;
583 guest_efer = vmx->guest_msrs[efer_offset].data;
584
51c6cf66
AK		 585 /*
586 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
587 * outside long mode
588 */
589 ignore_bits = EFER_NX | EFER_SCE;
590#ifdef CONFIG_X86_64
591 ignore_bits |= EFER_LMA | EFER_LME;
592 /* SCE is meaningful only in long mode on Intel */
593 if (guest_efer & EFER_LMA)
594 ignore_bits &= ~(u64)EFER_SCE;
595#endif
596 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
597 return;
2cc51560 598
51c6cf66
AK		 599 vmx->host_state.guest_efer_loaded = 1;
600 guest_efer &= ~ignore_bits;
601 guest_efer |= host_efer & ignore_bits;
602 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 603 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 604}
605
51c6cf66
AK		 606static void reload_host_efer(struct vcpu_vmx *vmx)
607{
608 if (vmx->host_state.guest_efer_loaded) {
609 vmx->host_state.guest_efer_loaded = 0;
610 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
611 }
612}
613
04d2cc77 614static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 615{
04d2cc77
AK		 616 struct vcpu_vmx *vmx = to_vmx(vcpu);
617
a2fa3e9f 618 if (vmx->host_state.loaded)
33ed6329
AK		 619 return;
620
a2fa3e9f 621 vmx->host_state.loaded = 1;
33ed6329
AK		 622 /*
623 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
624 * allow segment selectors with cpl > 0 or ti == 1.
625 */
d6e88aec 626 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 627 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 628 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 629 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 630 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 631 vmx->host_state.fs_reload_needed = 0;
632 } else {
33ed6329 633 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 634 vmx->host_state.fs_reload_needed = 1;
33ed6329 635 }
d6e88aec 636 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 637 if (!(vmx->host_state.gs_sel & 7))
638 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 639 else {
640 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 641 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 642 }
643
644#ifdef CONFIG_X86_64
645 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
646 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
647#else
a2fa3e9f
GH		 648 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
649 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 650#endif
707c0874
AK		 651
652#ifdef CONFIG_X86_64
d77c26fc 653 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 654 save_msrs(vmx->host_msrs +
655 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 656
707c0874 657#endif
a2fa3e9f 658 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 659 load_transition_efer(vmx);
33ed6329
AK		 660}
661
a9b21b62 662static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 663{
15ad7146 664 unsigned long flags;
33ed6329 665
a2fa3e9f 666 if (!vmx->host_state.loaded)
33ed6329
AK		 667 return;
668
e1beb1d3 669 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 670 vmx->host_state.loaded = 0;
152d3f2f 671 if (vmx->host_state.fs_reload_needed)
d6e88aec 672 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 673 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 674 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 675 /*
676 * If we have to reload gs, we must take care to
677 * preserve our gs base.
678 */
15ad7146 679 local_irq_save(flags);
d6e88aec 680 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 681#ifdef CONFIG_X86_64
682 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
683#endif
15ad7146 684 local_irq_restore(flags);
33ed6329 685 }
152d3f2f 686 reload_tss();
a2fa3e9f
GH		 687 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
688 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 689 reload_host_efer(vmx);
33ed6329
AK		 690}
691
a9b21b62
AK		 692static void vmx_load_host_state(struct vcpu_vmx *vmx)
693{
694 preempt_disable();
695 __vmx_load_host_state(vmx);
696 preempt_enable();
697}
698
6aa8b732
AK		 699/*
700 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
701 * vcpu mutex is already taken.
702 */
15ad7146 703static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 704{
a2fa3e9f
GH		 705 struct vcpu_vmx *vmx = to_vmx(vcpu);
706 u64 phys_addr = __pa(vmx->vmcs);
019960ae 707 u64 tsc_this, delta, new_offset;
6aa8b732 708
a3d7f85f 709 if (vcpu->cpu != cpu) {
8b9cf98c 710 vcpu_clear(vmx);
2f599714 711 kvm_migrate_timers(vcpu);
2384d2b3 712 vpid_sync_vcpu_all(vmx);
543e4243
AK		 713 local_irq_disable();
714 list_add(&vmx->local_vcpus_link,
715 &per_cpu(vcpus_on_cpu, cpu));
716 local_irq_enable();
a3d7f85f 717 }
6aa8b732 718
a2fa3e9f 719 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 720 u8 error;
721
a2fa3e9f 722 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 723 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 724 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
725 : "cc");
726 if (error)
727 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 728 vmx->vmcs, phys_addr);
6aa8b732
AK		 729 }
730
731 if (vcpu->cpu != cpu) {
732 struct descriptor_table dt;
733 unsigned long sysenter_esp;
734
735 vcpu->cpu = cpu;
736 /*
737 * Linux uses per-cpu TSS and GDT, so set these when switching
738 * processors.
739 */
d6e88aec
AK		 740 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
741 kvm_get_gdt(&dt);
6aa8b732
AK		 742 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
743
744 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
745 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 746
747 /*
748 * Make sure the time stamp counter is monotonous.
749 */
750 rdtscll(tsc_this);
019960ae
AK		 751 if (tsc_this < vcpu->arch.host_tsc) {
752 delta = vcpu->arch.host_tsc - tsc_this;
753 new_offset = vmcs_read64(TSC_OFFSET) + delta;
754 vmcs_write64(TSC_OFFSET, new_offset);
755 }
6aa8b732 756 }
6aa8b732
AK		 757}
758
759static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
760{
a9b21b62 761 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 762}
763
5fd86fcf
AK		 764static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
765{
766 if (vcpu->fpu_active)
767 return;
768 vcpu->fpu_active = 1;
707d92fa 769 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 770 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 771 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 772 update_exception_bitmap(vcpu);
773}
774
775static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
776{
777 if (!vcpu->fpu_active)
778 return;
779 vcpu->fpu_active = 0;
707d92fa 780 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 781 update_exception_bitmap(vcpu);
782}
783
6aa8b732
AK		 784static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
785{
345dcaa8
AK		 786 unsigned long rflags;
787
788 rflags = vmcs_readl(GUEST_RFLAGS);
789 if (to_vmx(vcpu)->rmode.vm86_active)
790 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
791 return rflags;
6aa8b732
AK		 792}
793
794static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
795{
7ffd92c5 796 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 797 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 798 vmcs_writel(GUEST_RFLAGS, rflags);
799}
800
2809f5d2
GC		 801static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
802{
803 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
804 int ret = 0;
805
806 if (interruptibility & GUEST_INTR_STATE_STI)
807 ret |= X86_SHADOW_INT_STI;
808 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
809 ret |= X86_SHADOW_INT_MOV_SS;
810
811 return ret & mask;
812}
813
814static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
815{
816 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
817 u32 interruptibility = interruptibility_old;
818
819 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
820
821 if (mask & X86_SHADOW_INT_MOV_SS)
822 interruptibility |= GUEST_INTR_STATE_MOV_SS;
823 if (mask & X86_SHADOW_INT_STI)
824 interruptibility |= GUEST_INTR_STATE_STI;
825
826 if ((interruptibility != interruptibility_old))
827 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
828}
829
6aa8b732
AK		 830static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
831{
832 unsigned long rip;
6aa8b732 833
5fdbf976 834 rip = kvm_rip_read(vcpu);
6aa8b732 835 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 836 kvm_rip_write(vcpu, rip);
6aa8b732 837
2809f5d2
GC		 838 /* skipping an emulated instruction also counts */
839 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 840}
841
298101da
AK		 842static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
843 bool has_error_code, u32 error_code)
844{
77ab6db0 845 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 846 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 847
8ab2d2e2 848 if (has_error_code) {
77ab6db0 849 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 850 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
851 }
77ab6db0 852
7ffd92c5 853 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 854 vmx->rmode.irq.pending = true;
855 vmx->rmode.irq.vector = nr;
856 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 857 if (kvm_exception_is_soft(nr))
858 vmx->rmode.irq.rip +=
859 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 860 intr_info |= INTR_TYPE_SOFT_INTR;
861 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 862 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
863 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
864 return;
865 }
866
66fd3f7f
GN		 867 if (kvm_exception_is_soft(nr)) {
868 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
869 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 870 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
871 } else
872 intr_info |= INTR_TYPE_HARD_EXCEPTION;
873
874 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 875}
876
a75beee6
ED		 877/*
878 * Swap MSR entry in host/guest MSR entry array.
879 */
54e11fa1 880#ifdef CONFIG_X86_64
8b9cf98c 881static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 882{
a2fa3e9f
GH		 883 struct kvm_msr_entry tmp;
884
885 tmp = vmx->guest_msrs[to];
886 vmx->guest_msrs[to] = vmx->guest_msrs[from];
887 vmx->guest_msrs[from] = tmp;
888 tmp = vmx->host_msrs[to];
889 vmx->host_msrs[to] = vmx->host_msrs[from];
890 vmx->host_msrs[from] = tmp;
a75beee6 891}
54e11fa1 892#endif
a75beee6 893
e38aea3e
AK		 894/*
895 * Set up the vmcs to automatically save and restore system
896 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
897 * mode, as fiddling with msrs is very expensive.
898 */
8b9cf98c 899static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 900{
2cc51560 901 int save_nmsrs;
5897297b 902 unsigned long *msr_bitmap;
e38aea3e 903
33f9c505 904 vmx_load_host_state(vmx);
a75beee6
ED		 905 save_nmsrs = 0;
906#ifdef CONFIG_X86_64
8b9cf98c 907 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 908 int index;
909
8b9cf98c 910 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 911 if (index >= 0)
8b9cf98c
RR		 912 move_msr_up(vmx, index, save_nmsrs++);
913 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 914 if (index >= 0)
8b9cf98c
RR		 915 move_msr_up(vmx, index, save_nmsrs++);
916 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 917 if (index >= 0)
8b9cf98c
RR		 918 move_msr_up(vmx, index, save_nmsrs++);
919 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 920 if (index >= 0)
8b9cf98c 921 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 922 /*
923 * MSR_K6_STAR is only needed on long mode guests, and only
924 * if efer.sce is enabled.
925 */
8b9cf98c 926 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 927 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 928 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 929 }
930#endif
a2fa3e9f 931 vmx->save_nmsrs = save_nmsrs;
e38aea3e 932
4d56c8a7 933#ifdef CONFIG_X86_64
a2fa3e9f 934 vmx->msr_offset_kernel_gs_base =
8b9cf98c 935 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 936#endif
8b9cf98c 937 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
5897297b
AK		 938
939 if (cpu_has_vmx_msr_bitmap()) {
940 if (is_long_mode(&vmx->vcpu))
941 msr_bitmap = vmx_msr_bitmap_longmode;
942 else
943 msr_bitmap = vmx_msr_bitmap_legacy;
944
945 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
946 }
e38aea3e
AK		 947}
948
6aa8b732
AK		 949/*
950 * reads and returns guest's timestamp counter "register"
951 * guest_tsc = host_tsc + tsc_offset -- 21.3
952 */
953static u64 guest_read_tsc(void)
954{
955 u64 host_tsc, tsc_offset;
956
957 rdtscll(host_tsc);
958 tsc_offset = vmcs_read64(TSC_OFFSET);
959 return host_tsc + tsc_offset;
960}
961
962/*
963 * writes 'guest_tsc' into guest's timestamp counter "register"
964 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
965 */
53f658b3 966static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 967{
6aa8b732
AK		 968 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
969}
970
6aa8b732
AK		 971/*
972 * Reads an msr value (of 'msr_index') into 'pdata'.
973 * Returns 0 on success, non-0 otherwise.
974 * Assumes vcpu_load() was already called.
975 */
976static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
977{
978 u64 data;
a2fa3e9f 979 struct kvm_msr_entry *msr;
6aa8b732
AK		 980
981 if (!pdata) {
982 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
983 return -EINVAL;
984 }
985
986 switch (msr_index) {
05b3e0c2 987#ifdef CONFIG_X86_64
6aa8b732
AK		 988 case MSR_FS_BASE:
989 data = vmcs_readl(GUEST_FS_BASE);
990 break;
991 case MSR_GS_BASE:
992 data = vmcs_readl(GUEST_GS_BASE);
993 break;
994 case MSR_EFER:
3bab1f5d 995 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732 996#endif
af24a4e4 997 case MSR_IA32_TSC:
6aa8b732
AK		 998 data = guest_read_tsc();
999 break;
1000 case MSR_IA32_SYSENTER_CS:
1001 data = vmcs_read32(GUEST_SYSENTER_CS);
1002 break;
1003 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1004 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1005 break;
1006 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1007 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1008 break;
6aa8b732 1009 default:
8b9cf98c 1010 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1011 if (msr) {
542423b0 1012 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1013 data = msr->data;
1014 break;
6aa8b732 1015 }
3bab1f5d 1016 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1017 }
1018
1019 *pdata = data;
1020 return 0;
1021}
1022
1023/*
1024 * Writes msr value into into the appropriate "register".
1025 * Returns 0 on success, non-0 otherwise.
1026 * Assumes vcpu_load() was already called.
1027 */
1028static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1029{
a2fa3e9f
GH		 1030 struct vcpu_vmx *vmx = to_vmx(vcpu);
1031 struct kvm_msr_entry *msr;
53f658b3 1032 u64 host_tsc;
2cc51560
ED		 1033 int ret = 0;
1034
6aa8b732 1035 switch (msr_index) {
3bab1f5d 1036 case MSR_EFER:
a9b21b62 1037 vmx_load_host_state(vmx);
2cc51560 1038 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1039 break;
16175a79 1040#ifdef CONFIG_X86_64
6aa8b732
AK		 1041 case MSR_FS_BASE:
1042 vmcs_writel(GUEST_FS_BASE, data);
1043 break;
1044 case MSR_GS_BASE:
1045 vmcs_writel(GUEST_GS_BASE, data);
1046 break;
1047#endif
1048 case MSR_IA32_SYSENTER_CS:
1049 vmcs_write32(GUEST_SYSENTER_CS, data);
1050 break;
1051 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1052 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1053 break;
1054 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1055 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1056 break;
af24a4e4 1057 case MSR_IA32_TSC:
53f658b3
MT		 1058 rdtscll(host_tsc);
1059 guest_write_tsc(data, host_tsc);
6aa8b732 1060 break;
468d472f
SY		 1061 case MSR_IA32_CR_PAT:
1062 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1063 vmcs_write64(GUEST_IA32_PAT, data);
1064 vcpu->arch.pat = data;
1065 break;
1066 }
1067 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 1068 default:
8b9cf98c 1069 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1070 if (msr) {
542423b0 1071 vmx_load_host_state(vmx);
3bab1f5d
AK		 1072 msr->data = data;
1073 break;
6aa8b732 1074 }
2cc51560 1075 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1076 }
1077
2cc51560 1078 return ret;
6aa8b732
AK		 1079}
1080
5fdbf976 1081static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1082{
5fdbf976
MT		 1083 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1084 switch (reg) {
1085 case VCPU_REGS_RSP:
1086 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1087 break;
1088 case VCPU_REGS_RIP:
1089 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1090 break;
6de4f3ad
AK		 1091 case VCPU_EXREG_PDPTR:
1092 if (enable_ept)
1093 ept_save_pdptrs(vcpu);
1094 break;
5fdbf976
MT		 1095 default:
1096 break;
1097 }
6aa8b732
AK		 1098}
1099
d0bfb940 1100static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1101{
d0bfb940
JK		 1102 int old_debug = vcpu->guest_debug;
1103 unsigned long flags;
6aa8b732 1104
d0bfb940
JK		 1105 vcpu->guest_debug = dbg->control;
1106 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1107 vcpu->guest_debug = 0;
6aa8b732 1108
ae675ef0
JK		 1109 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1110 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1111 else
1112 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1113
d0bfb940
JK		 1114 flags = vmcs_readl(GUEST_RFLAGS);
1115 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1116 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1117 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
6aa8b732 1118 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
d0bfb940 1119 vmcs_writel(GUEST_RFLAGS, flags);
6aa8b732 1120
abd3f2d6 1121 update_exception_bitmap(vcpu);
6aa8b732
AK		 1122
1123 return 0;
1124}
1125
1126static __init int cpu_has_kvm_support(void)
1127{
6210e37b 1128 return cpu_has_vmx();
6aa8b732
AK		 1129}
1130
1131static __init int vmx_disabled_by_bios(void)
1132{
1133 u64 msr;
1134
1135 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1136 return (msr & (FEATURE_CONTROL_LOCKED |
1137 FEATURE_CONTROL_VMXON_ENABLED))
1138 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1139 /* locked but not enabled */
6aa8b732
AK		 1140}
1141
774c47f1 1142static void hardware_enable(void *garbage)
6aa8b732
AK		 1143{
1144 int cpu = raw_smp_processor_id();
1145 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1146 u64 old;
1147
543e4243 1148 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1149 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1150 if ((old & (FEATURE_CONTROL_LOCKED |
1151 FEATURE_CONTROL_VMXON_ENABLED))
1152 != (FEATURE_CONTROL_LOCKED |
1153 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1154 /* enable and lock */
62b3ffb8 1155 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1156 FEATURE_CONTROL_LOCKED |
1157 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1158 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1159 asm volatile (ASM_VMX_VMXON_RAX
1160 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1161 : "memory", "cc");
1162}
1163
543e4243
AK		 1164static void vmclear_local_vcpus(void)
1165{
1166 int cpu = raw_smp_processor_id();
1167 struct vcpu_vmx *vmx, *n;
1168
1169 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1170 local_vcpus_link)
1171 __vcpu_clear(vmx);
1172}
1173
710ff4a8
EH		 1174
1175/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1176 * tricks.
1177 */
1178static void kvm_cpu_vmxoff(void)
6aa8b732 1179{
4ecac3fd 1180 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1181 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1182}
1183
710ff4a8
EH		 1184static void hardware_disable(void *garbage)
1185{
1186 vmclear_local_vcpus();
1187 kvm_cpu_vmxoff();
1188}
1189
1c3d14fe 1190static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1191 u32 msr, u32 *result)
1c3d14fe
YS		 1192{
1193 u32 vmx_msr_low, vmx_msr_high;
1194 u32 ctl = ctl_min | ctl_opt;
1195
1196 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1197
1198 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1199 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1200
1201 /* Ensure minimum (required) set of control bits are supported. */
1202 if (ctl_min & ~ctl)
002c7f7c 1203 return -EIO;
1c3d14fe
YS		 1204
1205 *result = ctl;
1206 return 0;
1207}
1208
002c7f7c 1209static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1210{
1211 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1212 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1213 u32 _pin_based_exec_control = 0;
1214 u32 _cpu_based_exec_control = 0;
f78e0e2e 1215 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1216 u32 _vmexit_control = 0;
1217 u32 _vmentry_control = 0;
1218
1219 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1220 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1221 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1222 &_pin_based_exec_control) < 0)
002c7f7c 1223 return -EIO;
1c3d14fe
YS		 1224
1225 min = CPU_BASED_HLT_EXITING |
1226#ifdef CONFIG_X86_64
1227 CPU_BASED_CR8_LOAD_EXITING |
1228 CPU_BASED_CR8_STORE_EXITING |
1229#endif
d56f546d
SY		 1230 CPU_BASED_CR3_LOAD_EXITING |
1231 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1232 CPU_BASED_USE_IO_BITMAPS |
1233 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1234 CPU_BASED_USE_TSC_OFFSETING |
1235 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1236 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1237 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1238 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1239 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1240 &_cpu_based_exec_control) < 0)
002c7f7c 1241 return -EIO;
6e5d865c
YS		 1242#ifdef CONFIG_X86_64
1243 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1244 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1245 ~CPU_BASED_CR8_STORE_EXITING;
1246#endif
f78e0e2e 1247 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1248 min2 = 0;
1249 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1250 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1251 SECONDARY_EXEC_ENABLE_VPID |
3a624e29
NK		 1252 SECONDARY_EXEC_ENABLE_EPT |
1253 SECONDARY_EXEC_UNRESTRICTED_GUEST;
d56f546d
SY		 1254 if (adjust_vmx_controls(min2, opt2,
1255 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1256 &_cpu_based_2nd_exec_control) < 0)
1257 return -EIO;
1258 }
1259#ifndef CONFIG_X86_64
1260 if (!(_cpu_based_2nd_exec_control &
1261 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1262 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1263#endif
d56f546d 1264 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1265 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1266 enabled */
5fff7d27
GN		 1267 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1268 CPU_BASED_CR3_STORE_EXITING |
1269 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1270 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1271 vmx_capability.ept, vmx_capability.vpid);
1272 }
1c3d14fe
YS		 1273
1274 min = 0;
1275#ifdef CONFIG_X86_64
1276 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1277#endif
468d472f 1278 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1279 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1280 &_vmexit_control) < 0)
002c7f7c 1281 return -EIO;
1c3d14fe 1282
468d472f
SY		 1283 min = 0;
1284 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1285 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1286 &_vmentry_control) < 0)
002c7f7c 1287 return -EIO;
6aa8b732 1288
c68876fd 1289 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1290
1291 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1292 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1293 return -EIO;
1c3d14fe
YS		 1294
1295#ifdef CONFIG_X86_64
1296 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1297 if (vmx_msr_high & (1u<<16))
002c7f7c 1298 return -EIO;
1c3d14fe
YS		 1299#endif
1300
1301 /* Require Write-Back (WB) memory type for VMCS accesses. */
1302 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1303 return -EIO;
1c3d14fe 1304
002c7f7c
YS		 1305 vmcs_conf->size = vmx_msr_high & 0x1fff;
1306 vmcs_conf->order = get_order(vmcs_config.size);
1307 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1308
002c7f7c
YS		 1309 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1310 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1311 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1312 vmcs_conf->vmexit_ctrl = _vmexit_control;
1313 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1314
1315 return 0;
c68876fd 1316}
6aa8b732
AK		 1317
1318static struct vmcs *alloc_vmcs_cpu(int cpu)
1319{
1320 int node = cpu_to_node(cpu);
1321 struct page *pages;
1322 struct vmcs *vmcs;
1323
6484eb3e 1324 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1325 if (!pages)
1326 return NULL;
1327 vmcs = page_address(pages);
1c3d14fe
YS		 1328 memset(vmcs, 0, vmcs_config.size);
1329 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1330 return vmcs;
1331}
1332
1333static struct vmcs *alloc_vmcs(void)
1334{
d3b2c338 1335 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1336}
1337
1338static void free_vmcs(struct vmcs *vmcs)
1339{
1c3d14fe 1340 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1341}
1342
39959588 1343static void free_kvm_area(void)
6aa8b732
AK		 1344{
1345 int cpu;
1346
1347 for_each_online_cpu(cpu)
1348 free_vmcs(per_cpu(vmxarea, cpu));
1349}
1350
6aa8b732
AK		 1351static __init int alloc_kvm_area(void)
1352{
1353 int cpu;
1354
1355 for_each_online_cpu(cpu) {
1356 struct vmcs *vmcs;
1357
1358 vmcs = alloc_vmcs_cpu(cpu);
1359 if (!vmcs) {
1360 free_kvm_area();
1361 return -ENOMEM;
1362 }
1363
1364 per_cpu(vmxarea, cpu) = vmcs;
1365 }
1366 return 0;
1367}
1368
1369static __init int hardware_setup(void)
1370{
002c7f7c
YS		 1371 if (setup_vmcs_config(&vmcs_config) < 0)
1372 return -EIO;
50a37eb4
JR		 1373
1374 if (boot_cpu_has(X86_FEATURE_NX))
1375 kvm_enable_efer_bits(EFER_NX);
1376
93ba03c2
SY		 1377 if (!cpu_has_vmx_vpid())
1378 enable_vpid = 0;
1379
3a624e29 1380 if (!cpu_has_vmx_ept()) {
93ba03c2 1381 enable_ept = 0;
3a624e29
NK		 1382 enable_unrestricted_guest = 0;
1383 }
1384
1385 if (!cpu_has_vmx_unrestricted_guest())
1386 enable_unrestricted_guest = 0;
93ba03c2
SY		 1387
1388 if (!cpu_has_vmx_flexpriority())
1389 flexpriority_enabled = 0;
1390
95ba8273
GN		 1391 if (!cpu_has_vmx_tpr_shadow())
1392 kvm_x86_ops->update_cr8_intercept = NULL;
1393
54dee993
MT		 1394 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1395 kvm_disable_largepages();
1396
6aa8b732
AK		 1397 return alloc_kvm_area();
1398}
1399
1400static __exit void hardware_unsetup(void)
1401{
1402 free_kvm_area();
1403}
1404
6aa8b732
AK		 1405static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1406{
1407 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1408
6af11b9e 1409 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1410 vmcs_write16(sf->selector, save->selector);
1411 vmcs_writel(sf->base, save->base);
1412 vmcs_write32(sf->limit, save->limit);
1413 vmcs_write32(sf->ar_bytes, save->ar);
1414 } else {
1415 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1416 << AR_DPL_SHIFT;
1417 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1418 }
1419}
1420
1421static void enter_pmode(struct kvm_vcpu *vcpu)
1422{
1423 unsigned long flags;
a89a8fb9 1424 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1425
a89a8fb9 1426 vmx->emulation_required = 1;
7ffd92c5 1427 vmx->rmode.vm86_active = 0;
6aa8b732 1428
7ffd92c5
AK		 1429 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1430 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1431 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1432
1433 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1434 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1435 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1436 vmcs_writel(GUEST_RFLAGS, flags);
1437
66aee91a
RR		 1438 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1439 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1440
1441 update_exception_bitmap(vcpu);
1442
a89a8fb9
MG		 1443 if (emulate_invalid_guest_state)
1444 return;
1445
7ffd92c5
AK		 1446 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1447 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1448 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1449 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1450
1451 vmcs_write16(GUEST_SS_SELECTOR, 0);
1452 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1453
1454 vmcs_write16(GUEST_CS_SELECTOR,
1455 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1456 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1457}
1458
d77c26fc 1459static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1460{
bfc6d222 1461 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1462 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1463 kvm->memslots[0].npages - 3;
1464 return base_gfn << PAGE_SHIFT;
1465 }
bfc6d222 1466 return kvm->arch.tss_addr;
6aa8b732
AK		 1467}
1468
1469static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1470{
1471 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1472
1473 save->selector = vmcs_read16(sf->selector);
1474 save->base = vmcs_readl(sf->base);
1475 save->limit = vmcs_read32(sf->limit);
1476 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1477 vmcs_write16(sf->selector, save->base >> 4);
1478 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1479 vmcs_write32(sf->limit, 0xffff);
1480 vmcs_write32(sf->ar_bytes, 0xf3);
1481}
1482
1483static void enter_rmode(struct kvm_vcpu *vcpu)
1484{
1485 unsigned long flags;
a89a8fb9 1486 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1487
3a624e29
NK		 1488 if (enable_unrestricted_guest)
1489 return;
1490
a89a8fb9 1491 vmx->emulation_required = 1;
7ffd92c5 1492 vmx->rmode.vm86_active = 1;
6aa8b732 1493
7ffd92c5 1494 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1495 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1496
7ffd92c5 1497 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1498 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1499
7ffd92c5 1500 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1501 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1502
1503 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1504 vmx->rmode.save_iopl
ad312c7c 1505 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1506
053de044 1507 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1508
1509 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1510 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1511 update_exception_bitmap(vcpu);
1512
a89a8fb9
MG		 1513 if (emulate_invalid_guest_state)
1514 goto continue_rmode;
1515
6aa8b732
AK		 1516 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1517 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1518 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1519
1520 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1521 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1522 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1523 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1524 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1525
7ffd92c5
AK		 1526 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1527 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1528 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1529 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1530
a89a8fb9 1531continue_rmode:
8668a3c4 1532 kvm_mmu_reset_context(vcpu);
b7ebfb05 1533 init_rmode(vcpu->kvm);
6aa8b732
AK		 1534}
1535
401d10de
AS		 1536static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1537{
1538 struct vcpu_vmx *vmx = to_vmx(vcpu);
1539 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1540
1541 vcpu->arch.shadow_efer = efer;
1542 if (!msr)
1543 return;
1544 if (efer & EFER_LMA) {
1545 vmcs_write32(VM_ENTRY_CONTROLS,
1546 vmcs_read32(VM_ENTRY_CONTROLS) |
1547 VM_ENTRY_IA32E_MODE);
1548 msr->data = efer;
1549 } else {
1550 vmcs_write32(VM_ENTRY_CONTROLS,
1551 vmcs_read32(VM_ENTRY_CONTROLS) &
1552 ~VM_ENTRY_IA32E_MODE);
1553
1554 msr->data = efer & ~EFER_LME;
1555 }
1556 setup_msrs(vmx);
1557}
1558
05b3e0c2 1559#ifdef CONFIG_X86_64
6aa8b732
AK		 1560
1561static void enter_lmode(struct kvm_vcpu *vcpu)
1562{
1563 u32 guest_tr_ar;
1564
1565 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1566 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1567 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1568 __func__);
6aa8b732
AK		 1569 vmcs_write32(GUEST_TR_AR_BYTES,
1570 (guest_tr_ar & ~AR_TYPE_MASK)
1571 | AR_TYPE_BUSY_64_TSS);
1572 }
ad312c7c 1573 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1574 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1575}
1576
1577static void exit_lmode(struct kvm_vcpu *vcpu)
1578{
ad312c7c 1579 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1580
1581 vmcs_write32(VM_ENTRY_CONTROLS,
1582 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1583 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1584}
1585
1586#endif
1587
2384d2b3
SY		 1588static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1589{
1590 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1591 if (enable_ept)
4e1096d2 1592 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1593}
1594
25c4c276 1595static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1596{
ad312c7c
ZX		 1597 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1598 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1599}
1600
1439442c
SY		 1601static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1602{
6de4f3ad
AK		 1603 if (!test_bit(VCPU_EXREG_PDPTR,
1604 (unsigned long *)&vcpu->arch.regs_dirty))
1605 return;
1606
1439442c 1607 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1608 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1609 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1610 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1611 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1612 }
1613}
1614
8f5d549f
AK		 1615static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1616{
1617 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1618 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1619 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1620 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1621 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1622 }
6de4f3ad
AK		 1623
1624 __set_bit(VCPU_EXREG_PDPTR,
1625 (unsigned long *)&vcpu->arch.regs_avail);
1626 __set_bit(VCPU_EXREG_PDPTR,
1627 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1628}
1629
1439442c
SY		 1630static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1631
1632static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1633 unsigned long cr0,
1634 struct kvm_vcpu *vcpu)
1635{
1636 if (!(cr0 & X86_CR0_PG)) {
1637 /* From paging/starting to nonpaging */
1638 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1639 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1640 (CPU_BASED_CR3_LOAD_EXITING |
1641 CPU_BASED_CR3_STORE_EXITING));
1642 vcpu->arch.cr0 = cr0;
1643 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c
SY		 1644 } else if (!is_paging(vcpu)) {
1645 /* From nonpaging to paging */
1646 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1647 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1648 ~(CPU_BASED_CR3_LOAD_EXITING |
1649 CPU_BASED_CR3_STORE_EXITING));
1650 vcpu->arch.cr0 = cr0;
1651 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c 1652 }
95eb84a7
SY		 1653
1654 if (!(cr0 & X86_CR0_WP))
1655 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1656}
1657
1658static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1659 struct kvm_vcpu *vcpu)
1660{
1661 if (!is_paging(vcpu)) {
1662 *hw_cr4 &= ~X86_CR4_PAE;
1663 *hw_cr4 |= X86_CR4_PSE;
1664 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1665 *hw_cr4 &= ~X86_CR4_PAE;
1666}
1667
6aa8b732
AK		 1668static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1669{
7ffd92c5 1670 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1671 unsigned long hw_cr0;
1672
1673 if (enable_unrestricted_guest)
1674 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1675 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1676 else
1677 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1678
5fd86fcf
AK		 1679 vmx_fpu_deactivate(vcpu);
1680
7ffd92c5 1681 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1682 enter_pmode(vcpu);
1683
7ffd92c5 1684 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1685 enter_rmode(vcpu);
1686
05b3e0c2 1687#ifdef CONFIG_X86_64
ad312c7c 1688 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1689 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1690 enter_lmode(vcpu);
707d92fa 1691 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1692 exit_lmode(vcpu);
1693 }
1694#endif
1695
089d034e 1696 if (enable_ept)
1439442c
SY		 1697 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1698
6aa8b732 1699 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1700 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1701 vcpu->arch.cr0 = cr0;
5fd86fcf 1702
707d92fa 1703 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1704 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1705}
1706
1439442c
SY		 1707static u64 construct_eptp(unsigned long root_hpa)
1708{
1709 u64 eptp;
1710
1711 /* TODO write the value reading from MSR */
1712 eptp = VMX_EPT_DEFAULT_MT |
1713 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1714 eptp |= (root_hpa & PAGE_MASK);
1715
1716 return eptp;
1717}
1718
6aa8b732
AK		 1719static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1720{
1439442c
SY		 1721 unsigned long guest_cr3;
1722 u64 eptp;
1723
1724 guest_cr3 = cr3;
089d034e 1725 if (enable_ept) {
1439442c
SY		 1726 eptp = construct_eptp(cr3);
1727 vmcs_write64(EPT_POINTER, eptp);
1439442c 1728 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1729 vcpu->kvm->arch.ept_identity_map_addr;
1439442c
SY		 1730 }
1731
2384d2b3 1732 vmx_flush_tlb(vcpu);
1439442c 1733 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1734 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1735 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1736}
1737
1738static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1739{
7ffd92c5 1740 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1741 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1742
ad312c7c 1743 vcpu->arch.cr4 = cr4;
089d034e 1744 if (enable_ept)
1439442c
SY		 1745 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1746
1747 vmcs_writel(CR4_READ_SHADOW, cr4);
1748 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1749}
1750
6aa8b732
AK		 1751static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1752{
1753 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1754
1755 return vmcs_readl(sf->base);
1756}
1757
1758static void vmx_get_segment(struct kvm_vcpu *vcpu,
1759 struct kvm_segment *var, int seg)
1760{
1761 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1762 u32 ar;
1763
1764 var->base = vmcs_readl(sf->base);
1765 var->limit = vmcs_read32(sf->limit);
1766 var->selector = vmcs_read16(sf->selector);
1767 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1768 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1769 ar = 0;
1770 var->type = ar & 15;
1771 var->s = (ar >> 4) & 1;
1772 var->dpl = (ar >> 5) & 3;
1773 var->present = (ar >> 7) & 1;
1774 var->avl = (ar >> 12) & 1;
1775 var->l = (ar >> 13) & 1;
1776 var->db = (ar >> 14) & 1;
1777 var->g = (ar >> 15) & 1;
1778 var->unusable = (ar >> 16) & 1;
1779}
1780
2e4d2653
IE		 1781static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1782{
2e4d2653
IE		 1783 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1784 return 0;
1785
1786 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1787 return 3;
1788
eab4b8aa 1789 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1790}
1791
653e3108 1792static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1793{
6aa8b732
AK		 1794 u32 ar;
1795
653e3108 1796 if (var->unusable)
6aa8b732
AK		 1797 ar = 1 << 16;
1798 else {
1799 ar = var->type & 15;
1800 ar |= (var->s & 1) << 4;
1801 ar |= (var->dpl & 3) << 5;
1802 ar |= (var->present & 1) << 7;
1803 ar |= (var->avl & 1) << 12;
1804 ar |= (var->l & 1) << 13;
1805 ar |= (var->db & 1) << 14;
1806 ar |= (var->g & 1) << 15;
1807 }
f7fbf1fd
UL		 1808 if (ar == 0) /* a 0 value means unusable */
1809 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1810
1811 return ar;
1812}
1813
1814static void vmx_set_segment(struct kvm_vcpu *vcpu,
1815 struct kvm_segment *var, int seg)
1816{
7ffd92c5 1817 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1818 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1819 u32 ar;
1820
7ffd92c5
AK		 1821 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1822 vmx->rmode.tr.selector = var->selector;
1823 vmx->rmode.tr.base = var->base;
1824 vmx->rmode.tr.limit = var->limit;
1825 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1826 return;
1827 }
1828 vmcs_writel(sf->base, var->base);
1829 vmcs_write32(sf->limit, var->limit);
1830 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1831 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1832 /*
1833 * Hack real-mode segments into vm86 compatibility.
1834 */
1835 if (var->base == 0xffff0000 && var->selector == 0xf000)
1836 vmcs_writel(sf->base, 0xf0000);
1837 ar = 0xf3;
1838 } else
1839 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1840
1841 /*
1842 * Fix the "Accessed" bit in AR field of segment registers for older
1843 * qemu binaries.
1844 * IA32 arch specifies that at the time of processor reset the
1845 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1846 * is setting it to 0 in the usedland code. This causes invalid guest
1847 * state vmexit when "unrestricted guest" mode is turned on.
1848 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1849 * tree. Newer qemu binaries with that qemu fix would not need this
1850 * kvm hack.
1851 */
1852 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1853 ar |= 0x1; /* Accessed */
1854
6aa8b732
AK		 1855 vmcs_write32(sf->ar_bytes, ar);
1856}
1857
6aa8b732
AK		 1858static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1859{
1860 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1861
1862 *db = (ar >> 14) & 1;
1863 *l = (ar >> 13) & 1;
1864}
1865
1866static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1867{
1868 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1869 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1870}
1871
1872static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1873{
1874 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1875 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1876}
1877
1878static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1879{
1880 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1881 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1882}
1883
1884static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1885{
1886 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1887 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1888}
1889
648dfaa7
MG		 1890static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1891{
1892 struct kvm_segment var;
1893 u32 ar;
1894
1895 vmx_get_segment(vcpu, &var, seg);
1896 ar = vmx_segment_access_rights(&var);
1897
1898 if (var.base != (var.selector << 4))
1899 return false;
1900 if (var.limit != 0xffff)
1901 return false;
1902 if (ar != 0xf3)
1903 return false;
1904
1905 return true;
1906}
1907
1908static bool code_segment_valid(struct kvm_vcpu *vcpu)
1909{
1910 struct kvm_segment cs;
1911 unsigned int cs_rpl;
1912
1913 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1914 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1915
1872a3f4
AK		 1916 if (cs.unusable)
1917 return false;
648dfaa7
MG		 1918 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1919 return false;
1920 if (!cs.s)
1921 return false;
1872a3f4 1922 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1923 if (cs.dpl > cs_rpl)
1924 return false;
1872a3f4 1925 } else {
648dfaa7
MG		 1926 if (cs.dpl != cs_rpl)
1927 return false;
1928 }
1929 if (!cs.present)
1930 return false;
1931
1932 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1933 return true;
1934}
1935
1936static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1937{
1938 struct kvm_segment ss;
1939 unsigned int ss_rpl;
1940
1941 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1942 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1943
1872a3f4
AK		 1944 if (ss.unusable)
1945 return true;
1946 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1947 return false;
1948 if (!ss.s)
1949 return false;
1950 if (ss.dpl != ss_rpl) /* DPL != RPL */
1951 return false;
1952 if (!ss.present)
1953 return false;
1954
1955 return true;
1956}
1957
1958static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1959{
1960 struct kvm_segment var;
1961 unsigned int rpl;
1962
1963 vmx_get_segment(vcpu, &var, seg);
1964 rpl = var.selector & SELECTOR_RPL_MASK;
1965
1872a3f4
AK		 1966 if (var.unusable)
1967 return true;
648dfaa7
MG		 1968 if (!var.s)
1969 return false;
1970 if (!var.present)
1971 return false;
1972 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1973 if (var.dpl < rpl) /* DPL < RPL */
1974 return false;
1975 }
1976
1977 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1978 * rights flags
1979 */
1980 return true;
1981}
1982
1983static bool tr_valid(struct kvm_vcpu *vcpu)
1984{
1985 struct kvm_segment tr;
1986
1987 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1988
1872a3f4
AK		 1989 if (tr.unusable)
1990 return false;
648dfaa7
MG		 1991 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1992 return false;
1872a3f4 1993 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 1994 return false;
1995 if (!tr.present)
1996 return false;
1997
1998 return true;
1999}
2000
2001static bool ldtr_valid(struct kvm_vcpu *vcpu)
2002{
2003 struct kvm_segment ldtr;
2004
2005 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2006
1872a3f4
AK		 2007 if (ldtr.unusable)
2008 return true;
648dfaa7
MG		 2009 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2010 return false;
2011 if (ldtr.type != 2)
2012 return false;
2013 if (!ldtr.present)
2014 return false;
2015
2016 return true;
2017}
2018
2019static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2020{
2021 struct kvm_segment cs, ss;
2022
2023 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2024 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2025
2026 return ((cs.selector & SELECTOR_RPL_MASK) ==
2027 (ss.selector & SELECTOR_RPL_MASK));
2028}
2029
2030/*
2031 * Check if guest state is valid. Returns true if valid, false if
2032 * not.
2033 * We assume that registers are always usable
2034 */
2035static bool guest_state_valid(struct kvm_vcpu *vcpu)
2036{
2037 /* real mode guest state checks */
2038 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2039 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2040 return false;
2041 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2042 return false;
2043 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2044 return false;
2045 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2046 return false;
2047 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2048 return false;
2049 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2050 return false;
2051 } else {
2052 /* protected mode guest state checks */
2053 if (!cs_ss_rpl_check(vcpu))
2054 return false;
2055 if (!code_segment_valid(vcpu))
2056 return false;
2057 if (!stack_segment_valid(vcpu))
2058 return false;
2059 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2060 return false;
2061 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2062 return false;
2063 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2064 return false;
2065 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2066 return false;
2067 if (!tr_valid(vcpu))
2068 return false;
2069 if (!ldtr_valid(vcpu))
2070 return false;
2071 }
2072 /* TODO:
2073 * - Add checks on RIP
2074 * - Add checks on RFLAGS
2075 */
2076
2077 return true;
2078}
2079
d77c26fc 2080static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2081{
6aa8b732 2082 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2083 u16 data = 0;
10589a46 2084 int ret = 0;
195aefde 2085 int r;
6aa8b732 2086
195aefde
IE		 2087 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2088 if (r < 0)
10589a46 2089 goto out;
195aefde 2090 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2091 r = kvm_write_guest_page(kvm, fn++, &data,
2092 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2093 if (r < 0)
10589a46 2094 goto out;
195aefde
IE		 2095 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2096 if (r < 0)
10589a46 2097 goto out;
195aefde
IE		 2098 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2099 if (r < 0)
10589a46 2100 goto out;
195aefde 2101 data = ~0;
10589a46
MT		 2102 r = kvm_write_guest_page(kvm, fn, &data,
2103 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2104 sizeof(u8));
195aefde 2105 if (r < 0)
10589a46
MT		 2106 goto out;
2107
2108 ret = 1;
2109out:
10589a46 2110 return ret;
6aa8b732
AK		 2111}
2112
b7ebfb05
SY		 2113static int init_rmode_identity_map(struct kvm *kvm)
2114{
2115 int i, r, ret;
2116 pfn_t identity_map_pfn;
2117 u32 tmp;
2118
089d034e 2119 if (!enable_ept)
b7ebfb05
SY		 2120 return 1;
2121 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2122 printk(KERN_ERR "EPT: identity-mapping pagetable "
2123 "haven't been allocated!\n");
2124 return 0;
2125 }
2126 if (likely(kvm->arch.ept_identity_pagetable_done))
2127 return 1;
2128 ret = 0;
b927a3ce 2129 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2130 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2131 if (r < 0)
2132 goto out;
2133 /* Set up identity-mapping pagetable for EPT in real mode */
2134 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2135 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2136 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2137 r = kvm_write_guest_page(kvm, identity_map_pfn,
2138 &tmp, i * sizeof(tmp), sizeof(tmp));
2139 if (r < 0)
2140 goto out;
2141 }
2142 kvm->arch.ept_identity_pagetable_done = true;
2143 ret = 1;
2144out:
2145 return ret;
2146}
2147
6aa8b732
AK		 2148static void seg_setup(int seg)
2149{
2150 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2151 unsigned int ar;
6aa8b732
AK		 2152
2153 vmcs_write16(sf->selector, 0);
2154 vmcs_writel(sf->base, 0);
2155 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2156 if (enable_unrestricted_guest) {
2157 ar = 0x93;
2158 if (seg == VCPU_SREG_CS)
2159 ar |= 0x08; /* code segment */
2160 } else
2161 ar = 0xf3;
2162
2163 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2164}
2165
f78e0e2e
SY		 2166static int alloc_apic_access_page(struct kvm *kvm)
2167{
2168 struct kvm_userspace_memory_region kvm_userspace_mem;
2169 int r = 0;
2170
72dc67a6 2171 down_write(&kvm->slots_lock);
bfc6d222 2172 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2173 goto out;
2174 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2175 kvm_userspace_mem.flags = 0;
2176 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2177 kvm_userspace_mem.memory_size = PAGE_SIZE;
2178 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2179 if (r)
2180 goto out;
72dc67a6 2181
bfc6d222 2182 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2183out:
72dc67a6 2184 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2185 return r;
2186}
2187
b7ebfb05
SY		 2188static int alloc_identity_pagetable(struct kvm *kvm)
2189{
2190 struct kvm_userspace_memory_region kvm_userspace_mem;
2191 int r = 0;
2192
2193 down_write(&kvm->slots_lock);
2194 if (kvm->arch.ept_identity_pagetable)
2195 goto out;
2196 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2197 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2198 kvm_userspace_mem.guest_phys_addr =
2199 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2200 kvm_userspace_mem.memory_size = PAGE_SIZE;
2201 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2202 if (r)
2203 goto out;
2204
b7ebfb05 2205 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2206 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05
SY		 2207out:
2208 up_write(&kvm->slots_lock);
2209 return r;
2210}
2211
2384d2b3
SY		 2212static void allocate_vpid(struct vcpu_vmx *vmx)
2213{
2214 int vpid;
2215
2216 vmx->vpid = 0;
919818ab 2217 if (!enable_vpid)
2384d2b3
SY		 2218 return;
2219 spin_lock(&vmx_vpid_lock);
2220 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2221 if (vpid < VMX_NR_VPIDS) {
2222 vmx->vpid = vpid;
2223 __set_bit(vpid, vmx_vpid_bitmap);
2224 }
2225 spin_unlock(&vmx_vpid_lock);
2226}
2227
5897297b 2228static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2229{
3e7c73e9 2230 int f = sizeof(unsigned long);
25c5f225
SY		 2231
2232 if (!cpu_has_vmx_msr_bitmap())
2233 return;
2234
2235 /*
2236 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2237 * have the write-low and read-high bitmap offsets the wrong way round.
2238 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2239 */
25c5f225 2240 if (msr <= 0x1fff) {
3e7c73e9
AK		 2241 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2242 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2243 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2244 msr &= 0x1fff;
3e7c73e9
AK		 2245 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2246 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2247 }
25c5f225
SY		 2248}
2249
5897297b
AK		 2250static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2251{
2252 if (!longmode_only)
2253 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2254 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2255}
2256
6aa8b732
AK		 2257/*
2258 * Sets up the vmcs for emulated real mode.
2259 */
8b9cf98c 2260static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2261{
468d472f 2262 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2263 u32 junk;
53f658b3 2264 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2265 unsigned long a;
2266 struct descriptor_table dt;
2267 int i;
cd2276a7 2268 unsigned long kvm_vmx_return;
6e5d865c 2269 u32 exec_control;
6aa8b732 2270
6aa8b732 2271 /* I/O */
3e7c73e9
AK		 2272 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2273 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2274
25c5f225 2275 if (cpu_has_vmx_msr_bitmap())
5897297b 2276 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2277
6aa8b732
AK		 2278 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2279
6aa8b732 2280 /* Control */
1c3d14fe
YS		 2281 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2282 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2283
2284 exec_control = vmcs_config.cpu_based_exec_ctrl;
2285 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2286 exec_control &= ~CPU_BASED_TPR_SHADOW;
2287#ifdef CONFIG_X86_64
2288 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2289 CPU_BASED_CR8_LOAD_EXITING;
2290#endif
2291 }
089d034e 2292 if (!enable_ept)
d56f546d 2293 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2294 CPU_BASED_CR3_LOAD_EXITING |
2295 CPU_BASED_INVLPG_EXITING;
6e5d865c 2296 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2297
83ff3b9d
SY		 2298 if (cpu_has_secondary_exec_ctrls()) {
2299 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2300 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2301 exec_control &=
2302 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2303 if (vmx->vpid == 0)
2304 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
089d034e 2305 if (!enable_ept)
d56f546d 2306 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3a624e29
NK		 2307 if (!enable_unrestricted_guest)
2308 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
83ff3b9d
SY		 2309 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2310 }
f78e0e2e 2311
c7addb90
AK		 2312 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2313 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2314 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2315
2316 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2317 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2318 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2319
2320 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2321 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2322 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2323 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2324 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2325 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2326#ifdef CONFIG_X86_64
6aa8b732
AK		 2327 rdmsrl(MSR_FS_BASE, a);
2328 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2329 rdmsrl(MSR_GS_BASE, a);
2330 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2331#else
2332 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2333 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2334#endif
2335
2336 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2337
d6e88aec 2338 kvm_get_idt(&dt);
6aa8b732
AK		 2339 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2340
d77c26fc 2341 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2342 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2343 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2344 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2345 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2346
2347 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2348 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2349 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2350 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2351 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2352 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2353
468d472f
SY		 2354 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2355 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2356 host_pat = msr_low | ((u64) msr_high << 32);
2357 vmcs_write64(HOST_IA32_PAT, host_pat);
2358 }
2359 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2360 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2361 host_pat = msr_low | ((u64) msr_high << 32);
2362 /* Write the default value follow host pat */
2363 vmcs_write64(GUEST_IA32_PAT, host_pat);
2364 /* Keep arch.pat sync with GUEST_IA32_PAT */
2365 vmx->vcpu.arch.pat = host_pat;
2366 }
2367
6aa8b732
AK		 2368 for (i = 0; i < NR_VMX_MSR; ++i) {
2369 u32 index = vmx_msr_index[i];
2370 u32 data_low, data_high;
2371 u64 data;
a2fa3e9f 2372 int j = vmx->nmsrs;
6aa8b732
AK		 2373
2374 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2375 continue;
432bd6cb
AK		 2376 if (wrmsr_safe(index, data_low, data_high) < 0)
2377 continue;
6aa8b732 2378 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 2379 vmx->host_msrs[j].index = index;
2380 vmx->host_msrs[j].reserved = 0;
2381 vmx->host_msrs[j].data = data;
2382 vmx->guest_msrs[j] = vmx->host_msrs[j];
2383 ++vmx->nmsrs;
6aa8b732 2384 }
6aa8b732 2385
1c3d14fe 2386 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2387
2388 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2389 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2390
e00c8cf2
AK		 2391 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2392 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2393
53f658b3
MT		 2394 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2395 rdtscll(tsc_this);
2396 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2397 tsc_base = tsc_this;
2398
2399 guest_write_tsc(0, tsc_base);
f78e0e2e 2400
e00c8cf2
AK		 2401 return 0;
2402}
2403
b7ebfb05
SY		 2404static int init_rmode(struct kvm *kvm)
2405{
2406 if (!init_rmode_tss(kvm))
2407 return 0;
2408 if (!init_rmode_identity_map(kvm))
2409 return 0;
2410 return 1;
2411}
2412
e00c8cf2
AK		 2413static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2414{
2415 struct vcpu_vmx *vmx = to_vmx(vcpu);
2416 u64 msr;
2417 int ret;
2418
5fdbf976 2419 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2420 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2421 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2422 ret = -ENOMEM;
2423 goto out;
2424 }
2425
7ffd92c5 2426 vmx->rmode.vm86_active = 0;
e00c8cf2 2427
3b86cd99
JK		 2428 vmx->soft_vnmi_blocked = 0;
2429
ad312c7c 2430 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2431 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2432 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2433 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2434 msr |= MSR_IA32_APICBASE_BSP;
2435 kvm_set_apic_base(&vmx->vcpu, msr);
2436
2437 fx_init(&vmx->vcpu);
2438
5706be0d 2439 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2440 /*
2441 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2442 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2443 */
c5af89b6 2444 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2445 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2446 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2447 } else {
ad312c7c
ZX		 2448 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2449 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2450 }
e00c8cf2
AK		 2451
2452 seg_setup(VCPU_SREG_DS);
2453 seg_setup(VCPU_SREG_ES);
2454 seg_setup(VCPU_SREG_FS);
2455 seg_setup(VCPU_SREG_GS);
2456 seg_setup(VCPU_SREG_SS);
2457
2458 vmcs_write16(GUEST_TR_SELECTOR, 0);
2459 vmcs_writel(GUEST_TR_BASE, 0);
2460 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2461 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2462
2463 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2464 vmcs_writel(GUEST_LDTR_BASE, 0);
2465 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2466 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2467
2468 vmcs_write32(GUEST_SYSENTER_CS, 0);
2469 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2470 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2471
2472 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2473 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2474 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2475 else
5fdbf976
MT		 2476 kvm_rip_write(vcpu, 0);
2477 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2478
e00c8cf2
AK		 2479 vmcs_writel(GUEST_DR7, 0x400);
2480
2481 vmcs_writel(GUEST_GDTR_BASE, 0);
2482 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2483
2484 vmcs_writel(GUEST_IDTR_BASE, 0);
2485 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2486
2487 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2488 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2489 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2490
e00c8cf2
AK		 2491 /* Special registers */
2492 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2493
2494 setup_msrs(vmx);
2495
6aa8b732
AK		 2496 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2497
f78e0e2e
SY		 2498 if (cpu_has_vmx_tpr_shadow()) {
2499 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2500 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2501 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2502 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2503 vmcs_write32(TPR_THRESHOLD, 0);
2504 }
2505
2506 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2507 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2508 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2509
2384d2b3
SY		 2510 if (vmx->vpid != 0)
2511 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2512
ad312c7c
ZX		 2513 vmx->vcpu.arch.cr0 = 0x60000010;
2514 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2515 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2516 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2517 vmx_fpu_activate(&vmx->vcpu);
2518 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2519
2384d2b3
SY		 2520 vpid_sync_vcpu_all(vmx);
2521
3200f405 2522 ret = 0;
6aa8b732 2523
a89a8fb9
MG		 2524 /* HACK: Don't enable emulation on guest boot/reset */
2525 vmx->emulation_required = 0;
2526
6aa8b732 2527out:
3200f405 2528 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2529 return ret;
2530}
2531
3b86cd99
JK		 2532static void enable_irq_window(struct kvm_vcpu *vcpu)
2533{
2534 u32 cpu_based_vm_exec_control;
2535
2536 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2537 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2538 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2539}
2540
2541static void enable_nmi_window(struct kvm_vcpu *vcpu)
2542{
2543 u32 cpu_based_vm_exec_control;
2544
2545 if (!cpu_has_virtual_nmis()) {
2546 enable_irq_window(vcpu);
2547 return;
2548 }
2549
2550 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2551 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2552 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2553}
2554
66fd3f7f 2555static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2556{
9c8cba37 2557 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2558 uint32_t intr;
2559 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2560
229456fc 2561 trace_kvm_inj_virq(irq);
2714d1d3 2562
fa89a817 2563 ++vcpu->stat.irq_injections;
7ffd92c5 2564 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2565 vmx->rmode.irq.pending = true;
2566 vmx->rmode.irq.vector = irq;
5fdbf976 2567 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2568 if (vcpu->arch.interrupt.soft)
2569 vmx->rmode.irq.rip +=
2570 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2571 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2572 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2573 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2574 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2575 return;
2576 }
66fd3f7f
GN		 2577 intr = irq | INTR_INFO_VALID_MASK;
2578 if (vcpu->arch.interrupt.soft) {
2579 intr |= INTR_TYPE_SOFT_INTR;
2580 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2581 vmx->vcpu.arch.event_exit_inst_len);
2582 } else
2583 intr |= INTR_TYPE_EXT_INTR;
2584 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2585}
2586
f08864b4
SY		 2587static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2588{
66a5a347
JK		 2589 struct vcpu_vmx *vmx = to_vmx(vcpu);
2590
3b86cd99
JK		 2591 if (!cpu_has_virtual_nmis()) {
2592 /*
2593 * Tracking the NMI-blocked state in software is built upon
2594 * finding the next open IRQ window. This, in turn, depends on
2595 * well-behaving guests: They have to keep IRQs disabled at
2596 * least as long as the NMI handler runs. Otherwise we may
2597 * cause NMI nesting, maybe breaking the guest. But as this is
2598 * highly unlikely, we can live with the residual risk.
2599 */
2600 vmx->soft_vnmi_blocked = 1;
2601 vmx->vnmi_blocked_time = 0;
2602 }
2603
487b391d 2604 ++vcpu->stat.nmi_injections;
7ffd92c5 2605 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2606 vmx->rmode.irq.pending = true;
2607 vmx->rmode.irq.vector = NMI_VECTOR;
2608 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2609 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2610 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2611 INTR_INFO_VALID_MASK);
2612 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2613 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2614 return;
2615 }
f08864b4
SY		 2616 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2617 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2618}
2619
c4282df9 2620static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2621{
3b86cd99 2622 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2623 return 0;
33f089ca 2624
c4282df9
GN		 2625 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2626 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2627 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2628}
2629
78646121
GN		 2630static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2631{
c4282df9
GN		 2632 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2633 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2634 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2635}
2636
cbc94022
IE		 2637static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2638{
2639 int ret;
2640 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2641 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2642 .guest_phys_addr = addr,
2643 .memory_size = PAGE_SIZE * 3,
2644 .flags = 0,
2645 };
2646
2647 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2648 if (ret)
2649 return ret;
bfc6d222 2650 kvm->arch.tss_addr = addr;
cbc94022
IE		 2651 return 0;
2652}
2653
6aa8b732
AK		 2654static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2655 int vec, u32 err_code)
2656{
b3f37707
NK		 2657 /*
2658 * Instruction with address size override prefix opcode 0x67
2659 * Cause the #SS fault with 0 error code in VM86 mode.
2660 */
2661 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2662 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2663 return 1;
77ab6db0
JK		 2664 /*
2665 * Forward all other exceptions that are valid in real mode.
2666 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2667 * the required debugging infrastructure rework.
2668 */
2669 switch (vec) {
77ab6db0 2670 case DB_VECTOR:
d0bfb940
JK		 2671 if (vcpu->guest_debug &
2672 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2673 return 0;
2674 kvm_queue_exception(vcpu, vec);
2675 return 1;
77ab6db0 2676 case BP_VECTOR:
d0bfb940
JK		 2677 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2678 return 0;
2679 /* fall through */
2680 case DE_VECTOR:
77ab6db0
JK		 2681 case OF_VECTOR:
2682 case BR_VECTOR:
2683 case UD_VECTOR:
2684 case DF_VECTOR:
2685 case SS_VECTOR:
2686 case GP_VECTOR:
2687 case MF_VECTOR:
2688 kvm_queue_exception(vcpu, vec);
2689 return 1;
2690 }
6aa8b732
AK		 2691 return 0;
2692}
2693
a0861c02
AK		 2694/*
2695 * Trigger machine check on the host. We assume all the MSRs are already set up
2696 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2697 * We pass a fake environment to the machine check handler because we want
2698 * the guest to be always treated like user space, no matter what context
2699 * it used internally.
2700 */
2701static void kvm_machine_check(void)
2702{
2703#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2704 struct pt_regs regs = {
2705 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2706 .flags = X86_EFLAGS_IF,
2707 };
2708
2709 do_machine_check(&regs, 0);
2710#endif
2711}
2712
2713static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2714{
2715 /* already handled by vcpu_run */
2716 return 1;
2717}
2718
6aa8b732
AK		 2719static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2720{
1155f76a 2721 struct vcpu_vmx *vmx = to_vmx(vcpu);
d0bfb940 2722 u32 intr_info, ex_no, error_code;
42dbaa5a 2723 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2724 u32 vect_info;
2725 enum emulation_result er;
2726
1155f76a 2727 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2728 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2729
a0861c02
AK		 2730 if (is_machine_check(intr_info))
2731 return handle_machine_check(vcpu, kvm_run);
2732
6aa8b732 2733 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2734 !is_page_fault(intr_info))
6aa8b732 2735 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2736 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2737
e4a41889 2738 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2739 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2740
2741 if (is_no_device(intr_info)) {
5fd86fcf 2742 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2743 return 1;
2744 }
2745
7aa81cc0 2746 if (is_invalid_opcode(intr_info)) {
571008da 2747 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2748 if (er != EMULATE_DONE)
7ee5d940 2749 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2750 return 1;
2751 }
2752
6aa8b732 2753 error_code = 0;
5fdbf976 2754 rip = kvm_rip_read(vcpu);
2e11384c 2755 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2756 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2757 if (is_page_fault(intr_info)) {
1439442c 2758 /* EPT won't cause page fault directly */
089d034e 2759 if (enable_ept)
1439442c 2760 BUG();
6aa8b732 2761 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2762 trace_kvm_page_fault(cr2, error_code);
2763
3298b75c 2764 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2765 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2766 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2767 }
2768
7ffd92c5 2769 if (vmx->rmode.vm86_active &&
6aa8b732 2770 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2771 error_code)) {
ad312c7c
ZX		 2772 if (vcpu->arch.halt_request) {
2773 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2774 return kvm_emulate_halt(vcpu);
2775 }
6aa8b732 2776 return 1;
72d6e5a0 2777 }
6aa8b732 2778
d0bfb940 2779 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2780 switch (ex_no) {
2781 case DB_VECTOR:
2782 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2783 if (!(vcpu->guest_debug &
2784 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2785 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2786 kvm_queue_exception(vcpu, DB_VECTOR);
2787 return 1;
2788 }
2789 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2790 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2791 /* fall through */
2792 case BP_VECTOR:
6aa8b732 2793 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2794 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2795 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2796 break;
2797 default:
d0bfb940
JK		 2798 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2799 kvm_run->ex.exception = ex_no;
2800 kvm_run->ex.error_code = error_code;
42dbaa5a 2801 break;
6aa8b732 2802 }
6aa8b732
AK		 2803 return 0;
2804}
2805
2806static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2807 struct kvm_run *kvm_run)
2808{
1165f5fe 2809 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2810 return 1;
2811}
2812
988ad74f
AK		 2813static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2814{
2815 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2816 return 0;
2817}
6aa8b732 2818
6aa8b732
AK		 2819static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2820{
bfdaab09 2821 unsigned long exit_qualification;
34c33d16 2822 int size, in, string;
039576c0 2823 unsigned port;
6aa8b732 2824
1165f5fe 2825 ++vcpu->stat.io_exits;
bfdaab09 2826 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2827 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2828
2829 if (string) {
3427318f
LV		 2830 if (emulate_instruction(vcpu,
2831 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2832 return 0;
2833 return 1;
2834 }
2835
2836 size = (exit_qualification & 7) + 1;
2837 in = (exit_qualification & 8) != 0;
039576c0 2838 port = exit_qualification >> 16;
e70669ab 2839
e93f36bc 2840 skip_emulated_instruction(vcpu);
3090dd73 2841 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2842}
2843
102d8325
IM		 2844static void
2845vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2846{
2847 /*
2848 * Patch in the VMCALL instruction:
2849 */
2850 hypercall[0] = 0x0f;
2851 hypercall[1] = 0x01;
2852 hypercall[2] = 0xc1;
102d8325
IM		 2853}
2854
6aa8b732
AK		 2855static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2856{
229456fc 2857 unsigned long exit_qualification, val;
6aa8b732
AK		 2858 int cr;
2859 int reg;
2860
bfdaab09 2861 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2862 cr = exit_qualification & 15;
2863 reg = (exit_qualification >> 8) & 15;
2864 switch ((exit_qualification >> 4) & 3) {
2865 case 0: /* mov to cr */
229456fc
MT		 2866 val = kvm_register_read(vcpu, reg);
2867 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2868 switch (cr) {
2869 case 0:
229456fc 2870 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2871 skip_emulated_instruction(vcpu);
2872 return 1;
2873 case 3:
229456fc 2874 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 2875 skip_emulated_instruction(vcpu);
2876 return 1;
2877 case 4:
229456fc 2878 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 2879 skip_emulated_instruction(vcpu);
2880 return 1;
0a5fff19
GN		 2881 case 8: {
2882 u8 cr8_prev = kvm_get_cr8(vcpu);
2883 u8 cr8 = kvm_register_read(vcpu, reg);
2884 kvm_set_cr8(vcpu, cr8);
2885 skip_emulated_instruction(vcpu);
2886 if (irqchip_in_kernel(vcpu->kvm))
2887 return 1;
2888 if (cr8_prev <= cr8)
2889 return 1;
2890 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2891 return 0;
2892 }
6aa8b732
AK		 2893 };
2894 break;
25c4c276 2895 case 2: /* clts */
5fd86fcf 2896 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2897 vcpu->arch.cr0 &= ~X86_CR0_TS;
2898 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2899 vmx_fpu_activate(vcpu);
25c4c276
AL		 2900 skip_emulated_instruction(vcpu);
2901 return 1;
6aa8b732
AK		 2902 case 1: /*mov from cr*/
2903 switch (cr) {
2904 case 3:
5fdbf976 2905 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 2906 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 2907 skip_emulated_instruction(vcpu);
2908 return 1;
2909 case 8:
229456fc
MT		 2910 val = kvm_get_cr8(vcpu);
2911 kvm_register_write(vcpu, reg, val);
2912 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 2913 skip_emulated_instruction(vcpu);
2914 return 1;
2915 }
2916 break;
2917 case 3: /* lmsw */
2d3ad1f4 2918 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2919
2920 skip_emulated_instruction(vcpu);
2921 return 1;
2922 default:
2923 break;
2924 }
2925 kvm_run->exit_reason = 0;
f0242478 2926 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2927 (int)(exit_qualification >> 4) & 3, cr);
2928 return 0;
2929}
2930
2931static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2932{
bfdaab09 2933 unsigned long exit_qualification;
6aa8b732
AK		 2934 unsigned long val;
2935 int dr, reg;
2936
0a79b009
AK		 2937 if (!kvm_require_cpl(vcpu, 0))
2938 return 1;
42dbaa5a
JK		 2939 dr = vmcs_readl(GUEST_DR7);
2940 if (dr & DR7_GD) {
2941 /*
2942 * As the vm-exit takes precedence over the debug trap, we
2943 * need to emulate the latter, either for the host or the
2944 * guest debugging itself.
2945 */
2946 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2947 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2948 kvm_run->debug.arch.dr7 = dr;
2949 kvm_run->debug.arch.pc =
2950 vmcs_readl(GUEST_CS_BASE) +
2951 vmcs_readl(GUEST_RIP);
2952 kvm_run->debug.arch.exception = DB_VECTOR;
2953 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2954 return 0;
2955 } else {
2956 vcpu->arch.dr7 &= ~DR7_GD;
2957 vcpu->arch.dr6 |= DR6_BD;
2958 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2959 kvm_queue_exception(vcpu, DB_VECTOR);
2960 return 1;
2961 }
2962 }
2963
bfdaab09 2964 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 2965 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2966 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2967 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 2968 switch (dr) {
42dbaa5a
JK		 2969 case 0 ... 3:
2970 val = vcpu->arch.db[dr];
2971 break;
6aa8b732 2972 case 6:
42dbaa5a 2973 val = vcpu->arch.dr6;
6aa8b732
AK		 2974 break;
2975 case 7:
42dbaa5a 2976 val = vcpu->arch.dr7;
6aa8b732
AK		 2977 break;
2978 default:
2979 val = 0;
2980 }
5fdbf976 2981 kvm_register_write(vcpu, reg, val);
6aa8b732 2982 } else {
42dbaa5a
JK		 2983 val = vcpu->arch.regs[reg];
2984 switch (dr) {
2985 case 0 ... 3:
2986 vcpu->arch.db[dr] = val;
2987 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2988 vcpu->arch.eff_db[dr] = val;
2989 break;
2990 case 4 ... 5:
2991 if (vcpu->arch.cr4 & X86_CR4_DE)
2992 kvm_queue_exception(vcpu, UD_VECTOR);
2993 break;
2994 case 6:
2995 if (val & 0xffffffff00000000ULL) {
2996 kvm_queue_exception(vcpu, GP_VECTOR);
2997 break;
2998 }
2999 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3000 break;
3001 case 7:
3002 if (val & 0xffffffff00000000ULL) {
3003 kvm_queue_exception(vcpu, GP_VECTOR);
3004 break;
3005 }
3006 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3007 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3008 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3009 vcpu->arch.switch_db_regs =
3010 (val & DR7_BP_EN_MASK);
3011 }
3012 break;
3013 }
6aa8b732 3014 }
6aa8b732
AK		 3015 skip_emulated_instruction(vcpu);
3016 return 1;
3017}
3018
3019static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3020{
06465c5a
AK		 3021 kvm_emulate_cpuid(vcpu);
3022 return 1;
6aa8b732
AK		 3023}
3024
3025static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3026{
ad312c7c 3027 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3028 u64 data;
3029
3030 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 3031 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3032 return 1;
3033 }
3034
229456fc 3035 trace_kvm_msr_read(ecx, data);
2714d1d3 3036
6aa8b732 3037 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3038 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3039 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3040 skip_emulated_instruction(vcpu);
3041 return 1;
3042}
3043
3044static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3045{
ad312c7c
ZX		 3046 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3047 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3048 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 3049
229456fc 3050 trace_kvm_msr_write(ecx, data);
2714d1d3 3051
6aa8b732 3052 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 3053 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3054 return 1;
3055 }
3056
3057 skip_emulated_instruction(vcpu);
3058 return 1;
3059}
3060
6e5d865c
YS		 3061static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
3062 struct kvm_run *kvm_run)
3063{
3064 return 1;
3065}
3066
6aa8b732
AK		 3067static int handle_interrupt_window(struct kvm_vcpu *vcpu,
3068 struct kvm_run *kvm_run)
3069{
85f455f7
ED		 3070 u32 cpu_based_vm_exec_control;
3071
3072 /* clear pending irq */
3073 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3074 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3075 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3076
a26bf12a 3077 ++vcpu->stat.irq_window_exits;
2714d1d3 3078
c1150d8c
DL		 3079 /*
3080 * If the user space waits to inject interrupts, exit as soon as
3081 * possible
3082 */
8061823a
GN		 3083 if (!irqchip_in_kernel(vcpu->kvm) &&
3084 kvm_run->request_interrupt_window &&
3085 !kvm_cpu_has_interrupt(vcpu)) {
c1150d8c 3086 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3087 return 0;
3088 }
6aa8b732
AK		 3089 return 1;
3090}
3091
3092static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3093{
3094 skip_emulated_instruction(vcpu);
d3bef15f 3095 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3096}
3097
c21415e8
IM		 3098static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3099{
510043da 3100 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3101 kvm_emulate_hypercall(vcpu);
3102 return 1;
c21415e8
IM		 3103}
3104
e3c7cb6a
AK		 3105static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3106{
3107 kvm_queue_exception(vcpu, UD_VECTOR);
3108 return 1;
3109}
3110
a7052897
MT		 3111static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3112{
f9c617f6 3113 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3114
3115 kvm_mmu_invlpg(vcpu, exit_qualification);
3116 skip_emulated_instruction(vcpu);
3117 return 1;
3118}
3119
e5edaa01
ED		 3120static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3121{
3122 skip_emulated_instruction(vcpu);
3123 /* TODO: Add support for VT-d/pass-through device */
3124 return 1;
3125}
3126
f78e0e2e
SY		 3127static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3128{
f9c617f6 3129 unsigned long exit_qualification;
f78e0e2e
SY		 3130 enum emulation_result er;
3131 unsigned long offset;
3132
f9c617f6 3133 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3134 offset = exit_qualification & 0xffful;
3135
3136 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3137
3138 if (er != EMULATE_DONE) {
3139 printk(KERN_ERR
3140 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3141 offset);
7f582ab6 3142 return -ENOEXEC;
f78e0e2e
SY		 3143 }
3144 return 1;
3145}
3146
37817f29
IE		 3147static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3148{
60637aac 3149 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3150 unsigned long exit_qualification;
3151 u16 tss_selector;
64a7ec06
GN		 3152 int reason, type, idt_v;
3153
3154 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3155 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3156
3157 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3158
3159 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3160 if (reason == TASK_SWITCH_GATE && idt_v) {
3161 switch (type) {
3162 case INTR_TYPE_NMI_INTR:
3163 vcpu->arch.nmi_injected = false;
3164 if (cpu_has_virtual_nmis())
3165 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3166 GUEST_INTR_STATE_NMI);
3167 break;
3168 case INTR_TYPE_EXT_INTR:
66fd3f7f 3169 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3170 kvm_clear_interrupt_queue(vcpu);
3171 break;
3172 case INTR_TYPE_HARD_EXCEPTION:
3173 case INTR_TYPE_SOFT_EXCEPTION:
3174 kvm_clear_exception_queue(vcpu);
3175 break;
3176 default:
3177 break;
3178 }
60637aac 3179 }
37817f29
IE		 3180 tss_selector = exit_qualification;
3181
64a7ec06
GN		 3182 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3183 type != INTR_TYPE_EXT_INTR &&
3184 type != INTR_TYPE_NMI_INTR))
3185 skip_emulated_instruction(vcpu);
3186
42dbaa5a
JK		 3187 if (!kvm_task_switch(vcpu, tss_selector, reason))
3188 return 0;
3189
3190 /* clear all local breakpoint enable flags */
3191 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3192
3193 /*
3194 * TODO: What about debug traps on tss switch?
3195 * Are we supposed to inject them and update dr6?
3196 */
3197
3198 return 1;
37817f29
IE		 3199}
3200
1439442c
SY		 3201static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3202{
f9c617f6 3203 unsigned long exit_qualification;
1439442c 3204 gpa_t gpa;
1439442c 3205 int gla_validity;
1439442c 3206
f9c617f6 3207 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3208
3209 if (exit_qualification & (1 << 6)) {
3210 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3211 return -EINVAL;
1439442c
SY		 3212 }
3213
3214 gla_validity = (exit_qualification >> 7) & 0x3;
3215 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3216 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3217 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3218 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3219 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3220 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3221 (long unsigned int)exit_qualification);
3222 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
596ae895
AK		 3223 kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3224 return 0;
1439442c
SY		 3225 }
3226
3227 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3228 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3229 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3230}
3231
68f89400
MT		 3232static u64 ept_rsvd_mask(u64 spte, int level)
3233{
3234 int i;
3235 u64 mask = 0;
3236
3237 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3238 mask |= (1ULL << i);
3239
3240 if (level > 2)
3241 /* bits 7:3 reserved */
3242 mask |= 0xf8;
3243 else if (level == 2) {
3244 if (spte & (1ULL << 7))
3245 /* 2MB ref, bits 20:12 reserved */
3246 mask |= 0x1ff000;
3247 else
3248 /* bits 6:3 reserved */
3249 mask |= 0x78;
3250 }
3251
3252 return mask;
3253}
3254
3255static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3256 int level)
3257{
3258 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3259
3260 /* 010b (write-only) */
3261 WARN_ON((spte & 0x7) == 0x2);
3262
3263 /* 110b (write/execute) */
3264 WARN_ON((spte & 0x7) == 0x6);
3265
3266 /* 100b (execute-only) and value not supported by logical processor */
3267 if (!cpu_has_vmx_ept_execute_only())
3268 WARN_ON((spte & 0x7) == 0x4);
3269
3270 /* not 000b */
3271 if ((spte & 0x7)) {
3272 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3273
3274 if (rsvd_bits != 0) {
3275 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3276 __func__, rsvd_bits);
3277 WARN_ON(1);
3278 }
3279
3280 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3281 u64 ept_mem_type = (spte & 0x38) >> 3;
3282
3283 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3284 ept_mem_type == 7) {
3285 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3286 __func__, ept_mem_type);
3287 WARN_ON(1);
3288 }
3289 }
3290 }
3291}
3292
3293static int handle_ept_misconfig(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3294{
3295 u64 sptes[4];
3296 int nr_sptes, i;
3297 gpa_t gpa;
3298
3299 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3300
3301 printk(KERN_ERR "EPT: Misconfiguration.\n");
3302 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3303
3304 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3305
3306 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3307 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3308
3309 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3310 kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3311
3312 return 0;
3313}
3314
f08864b4
SY		 3315static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3316{
3317 u32 cpu_based_vm_exec_control;
3318
3319 /* clear pending NMI */
3320 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3321 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3322 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3323 ++vcpu->stat.nmi_window_exits;
3324
3325 return 1;
3326}
3327
ea953ef0
MG		 3328static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3329 struct kvm_run *kvm_run)
3330{
8b3079a5
AK		 3331 struct vcpu_vmx *vmx = to_vmx(vcpu);
3332 enum emulation_result err = EMULATE_DONE;
ea953ef0 3333
ea953ef0 3334 local_irq_enable();
34f0c1ad 3335 preempt_enable();
ea953ef0
MG		 3336
3337 while (!guest_state_valid(vcpu)) {
3338 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3339
1d5a4d9b
GT		 3340 if (err == EMULATE_DO_MMIO)
3341 break;
3342
3343 if (err != EMULATE_DONE) {
3344 kvm_report_emulation_failure(vcpu, "emulation failure");
263799a3 3345 break;
ea953ef0
MG		 3346 }
3347
3348 if (signal_pending(current))
3349 break;
3350 if (need_resched())
3351 schedule();
3352 }
3353
ea953ef0 3354 preempt_disable();
34f0c1ad 3355 local_irq_disable();
8b3079a5
AK		 3356
3357 vmx->invalid_state_emulation_result = err;
ea953ef0
MG		 3358}
3359
6aa8b732
AK		 3360/*
3361 * The exit handlers return 1 if the exit was handled fully and guest execution
3362 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3363 * to be done to userspace and return 0.
3364 */
3365static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3366 struct kvm_run *kvm_run) = {
3367 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3368 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3369 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3370 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3371 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3372 [EXIT_REASON_CR_ACCESS] = handle_cr,
3373 [EXIT_REASON_DR_ACCESS] = handle_dr,
3374 [EXIT_REASON_CPUID] = handle_cpuid,
3375 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3376 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3377 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3378 [EXIT_REASON_HLT] = handle_halt,
a7052897 3379 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3380 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3381 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3382 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3383 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3384 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3385 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3386 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3387 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3388 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3389 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3390 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3391 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3392 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3393 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3394 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3395 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3396 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
6aa8b732
AK		 3397};
3398
3399static const int kvm_vmx_max_exit_handlers =
50a3485c 3400 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3401
3402/*
3403 * The guest has exited. See if we can fix it or if we need userspace
3404 * assistance.
3405 */
6062d012 3406static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 3407{
29bd8a78 3408 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3409 u32 exit_reason = vmx->exit_reason;
1155f76a 3410 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3411
229456fc 3412 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3413
1d5a4d9b
GT		 3414 /* If we need to emulate an MMIO from handle_invalid_guest_state
3415 * we just return 0 */
10f32d84
AK		 3416 if (vmx->emulation_required && emulate_invalid_guest_state) {
3417 if (guest_state_valid(vcpu))
3418 vmx->emulation_required = 0;
8b3079a5 3419 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
10f32d84 3420 }
1d5a4d9b 3421
1439442c
SY		 3422 /* Access CR3 don't cause VMExit in paging mode, so we need
3423 * to sync with guest real CR3. */
6de4f3ad 3424 if (enable_ept && is_paging(vcpu))
1439442c 3425 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3426
29bd8a78
AK		 3427 if (unlikely(vmx->fail)) {
3428 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3429 kvm_run->fail_entry.hardware_entry_failure_reason
3430 = vmcs_read32(VM_INSTRUCTION_ERROR);
3431 return 0;
3432 }
6aa8b732 3433
d77c26fc 3434 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3435 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3436 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3437 exit_reason != EXIT_REASON_TASK_SWITCH))
3438 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3439 "(0x%x) and exit reason is 0x%x\n",
3440 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3441
3442 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3443 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3444 vmx->soft_vnmi_blocked = 0;
3b86cd99 3445 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3446 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3447 /*
3448 * This CPU don't support us in finding the end of an
3449 * NMI-blocked window if the guest runs with IRQs
3450 * disabled. So we pull the trigger after 1 s of
3451 * futile waiting, but inform the user about this.
3452 */
3453 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3454 "state on VCPU %d after 1 s timeout\n",
3455 __func__, vcpu->vcpu_id);
3456 vmx->soft_vnmi_blocked = 0;
3b86cd99 3457 }
3b86cd99
JK		 3458 }
3459
6aa8b732
AK		 3460 if (exit_reason < kvm_vmx_max_exit_handlers
3461 && kvm_vmx_exit_handlers[exit_reason])
3462 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3463 else {
3464 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3465 kvm_run->hw.hardware_exit_reason = exit_reason;
3466 }
3467 return 0;
3468}
3469
95ba8273 3470static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3471{
95ba8273 3472 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3473 vmcs_write32(TPR_THRESHOLD, 0);
3474 return;
3475 }
3476
95ba8273 3477 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3478}
3479
cf393f75
AK		 3480static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3481{
3482 u32 exit_intr_info;
7b4a25cb 3483 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3484 bool unblock_nmi;
3485 u8 vector;
668f612f
AK		 3486 int type;
3487 bool idtv_info_valid;
cf393f75
AK		 3488
3489 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3490
a0861c02
AK		 3491 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3492
3493 /* Handle machine checks before interrupts are enabled */
3494 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3495 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3496 && is_machine_check(exit_intr_info)))
3497 kvm_machine_check();
3498
20f65983
GN		 3499 /* We need to handle NMIs before interrupts are enabled */
3500 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3501 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3502 asm("int $2");
20f65983
GN		 3503
3504 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3505
cf393f75
AK		 3506 if (cpu_has_virtual_nmis()) {
3507 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3508 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3509 /*
7b4a25cb 3510 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3511 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3512 * a guest IRET fault.
7b4a25cb
GN		 3513 * SDM 3: 23.2.2 (September 2008)
3514 * Bit 12 is undefined in any of the following cases:
3515 * If the VM exit sets the valid bit in the IDT-vectoring
3516 * information field.
3517 * If the VM exit is due to a double fault.
cf393f75 3518 */
7b4a25cb
GN		 3519 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3520 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3521 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3522 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3523 } else if (unlikely(vmx->soft_vnmi_blocked))
3524 vmx->vnmi_blocked_time +=
3525 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3526
37b96e98
GN		 3527 vmx->vcpu.arch.nmi_injected = false;
3528 kvm_clear_exception_queue(&vmx->vcpu);
3529 kvm_clear_interrupt_queue(&vmx->vcpu);
3530
3531 if (!idtv_info_valid)
3532 return;
3533
668f612f
AK		 3534 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3535 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3536
64a7ec06 3537 switch (type) {
37b96e98
GN		 3538 case INTR_TYPE_NMI_INTR:
3539 vmx->vcpu.arch.nmi_injected = true;
668f612f 3540 /*
7b4a25cb 3541 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3542 * Clear bit "block by NMI" before VM entry if a NMI
3543 * delivery faulted.
668f612f 3544 */
37b96e98
GN		 3545 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3546 GUEST_INTR_STATE_NMI);
3547 break;
37b96e98 3548 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3549 vmx->vcpu.arch.event_exit_inst_len =
3550 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3551 /* fall through */
3552 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3553 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3554 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3555 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3556 } else
3557 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3558 break;
66fd3f7f
GN		 3559 case INTR_TYPE_SOFT_INTR:
3560 vmx->vcpu.arch.event_exit_inst_len =
3561 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3562 /* fall through */
37b96e98 3563 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3564 kvm_queue_interrupt(&vmx->vcpu, vector,
3565 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3566 break;
3567 default:
3568 break;
f7d9238f 3569 }
cf393f75
AK		 3570}
3571
9c8cba37
AK		 3572/*
3573 * Failure to inject an interrupt should give us the information
3574 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3575 * when fetching the interrupt redirection bitmap in the real-mode
3576 * tss, this doesn't happen. So we do it ourselves.
3577 */
3578static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3579{
3580 vmx->rmode.irq.pending = 0;
5fdbf976 3581 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3582 return;
5fdbf976 3583 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3584 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3585 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3586 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3587 return;
3588 }
3589 vmx->idt_vectoring_info =
3590 VECTORING_INFO_VALID_MASK
3591 | INTR_TYPE_EXT_INTR
3592 | vmx->rmode.irq.vector;
3593}
3594
c801949d
AK		 3595#ifdef CONFIG_X86_64
3596#define R "r"
3597#define Q "q"
3598#else
3599#define R "e"
3600#define Q "l"
3601#endif
3602
04d2cc77 3603static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 3604{
a2fa3e9f 3605 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3606
8f5d549f
AK		 3607 if (enable_ept && is_paging(vcpu)) {
3608 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3609 ept_load_pdptrs(vcpu);
3610 }
3b86cd99
JK		 3611 /* Record the guest's net vcpu time for enforced NMI injections. */
3612 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3613 vmx->entry_time = ktime_get();
3614
a89a8fb9
MG		 3615 /* Handle invalid guest state instead of entering VMX */
3616 if (vmx->emulation_required && emulate_invalid_guest_state) {
3617 handle_invalid_guest_state(vcpu, kvm_run);
3618 return;
3619 }
3620
5fdbf976
MT		 3621 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3622 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3623 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3624 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3625
787ff736
GN		 3626 /* When single-stepping over STI and MOV SS, we must clear the
3627 * corresponding interruptibility bits in the guest state. Otherwise
3628 * vmentry fails as it then expects bit 14 (BS) in pending debug
3629 * exceptions being set, but that's not correct for the guest debugging
3630 * case. */
3631 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3632 vmx_set_interrupt_shadow(vcpu, 0);
3633
e6adf283
AK		 3634 /*
3635 * Loading guest fpu may have cleared host cr0.ts
3636 */
3637 vmcs_writel(HOST_CR0, read_cr0());
3638
e8a48342
AK		 3639 if (vcpu->arch.switch_db_regs)
3640 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3641
d77c26fc 3642 asm(
6aa8b732 3643 /* Store host registers */
c801949d
AK		 3644 "push %%"R"dx; push %%"R"bp;"
3645 "push %%"R"cx \n\t"
313dbd49
AK		 3646 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3647 "je 1f \n\t"
3648 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3649 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3650 "1: \n\t"
d3edefc0
AK		 3651 /* Reload cr2 if changed */
3652 "mov %c[cr2](%0), %%"R"ax \n\t"
3653 "mov %%cr2, %%"R"dx \n\t"
3654 "cmp %%"R"ax, %%"R"dx \n\t"
3655 "je 2f \n\t"
3656 "mov %%"R"ax, %%cr2 \n\t"
3657 "2: \n\t"
6aa8b732 3658 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3659 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3660 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3661 "mov %c[rax](%0), %%"R"ax \n\t"
3662 "mov %c[rbx](%0), %%"R"bx \n\t"
3663 "mov %c[rdx](%0), %%"R"dx \n\t"
3664 "mov %c[rsi](%0), %%"R"si \n\t"
3665 "mov %c[rdi](%0), %%"R"di \n\t"
3666 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3667#ifdef CONFIG_X86_64
e08aa78a
AK		 3668 "mov %c[r8](%0), %%r8 \n\t"
3669 "mov %c[r9](%0), %%r9 \n\t"
3670 "mov %c[r10](%0), %%r10 \n\t"
3671 "mov %c[r11](%0), %%r11 \n\t"
3672 "mov %c[r12](%0), %%r12 \n\t"
3673 "mov %c[r13](%0), %%r13 \n\t"
3674 "mov %c[r14](%0), %%r14 \n\t"
3675 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3676#endif
c801949d
AK		 3677 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3678
6aa8b732 3679 /* Enter guest mode */
cd2276a7 3680 "jne .Llaunched \n\t"
4ecac3fd 3681 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3682 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3683 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3684 ".Lkvm_vmx_return: "
6aa8b732 3685 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3686 "xchg %0, (%%"R"sp) \n\t"
3687 "mov %%"R"ax, %c[rax](%0) \n\t"
3688 "mov %%"R"bx, %c[rbx](%0) \n\t"
3689 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3690 "mov %%"R"dx, %c[rdx](%0) \n\t"
3691 "mov %%"R"si, %c[rsi](%0) \n\t"
3692 "mov %%"R"di, %c[rdi](%0) \n\t"
3693 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3694#ifdef CONFIG_X86_64
e08aa78a
AK		 3695 "mov %%r8, %c[r8](%0) \n\t"
3696 "mov %%r9, %c[r9](%0) \n\t"
3697 "mov %%r10, %c[r10](%0) \n\t"
3698 "mov %%r11, %c[r11](%0) \n\t"
3699 "mov %%r12, %c[r12](%0) \n\t"
3700 "mov %%r13, %c[r13](%0) \n\t"
3701 "mov %%r14, %c[r14](%0) \n\t"
3702 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3703#endif
c801949d
AK		 3704 "mov %%cr2, %%"R"ax \n\t"
3705 "mov %%"R"ax, %c[cr2](%0) \n\t"
3706
3707 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3708 "setbe %c[fail](%0) \n\t"
3709 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3710 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3711 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3712 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3713 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3714 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3715 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3716 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3717 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3718 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3719 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3720#ifdef CONFIG_X86_64
ad312c7c
ZX		 3721 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3722 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3723 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3724 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3725 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3726 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3727 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3728 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3729#endif
ad312c7c 3730 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3731 : "cc", "memory"
c801949d 3732 , R"bx", R"di", R"si"
c2036300 3733#ifdef CONFIG_X86_64
c2036300
LV		 3734 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3735#endif
3736 );
6aa8b732 3737
6de4f3ad
AK		 3738 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3739 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3740 vcpu->arch.regs_dirty = 0;
3741
e8a48342
AK		 3742 if (vcpu->arch.switch_db_regs)
3743 get_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3744
1155f76a 3745 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3746 if (vmx->rmode.irq.pending)
3747 fixup_rmode_irq(vmx);
1155f76a 3748
d77c26fc 3749 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3750 vmx->launched = 1;
1b6269db 3751
cf393f75 3752 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3753}
3754
c801949d
AK		 3755#undef R
3756#undef Q
3757
6aa8b732
AK		 3758static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3759{
a2fa3e9f
GH		 3760 struct vcpu_vmx *vmx = to_vmx(vcpu);
3761
3762 if (vmx->vmcs) {
543e4243 3763 vcpu_clear(vmx);
a2fa3e9f
GH		 3764 free_vmcs(vmx->vmcs);
3765 vmx->vmcs = NULL;
6aa8b732
AK		 3766 }
3767}
3768
3769static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3770{
fb3f0f51
RR		 3771 struct vcpu_vmx *vmx = to_vmx(vcpu);
3772
2384d2b3
SY		 3773 spin_lock(&vmx_vpid_lock);
3774 if (vmx->vpid != 0)
3775 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3776 spin_unlock(&vmx_vpid_lock);
6aa8b732 3777 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3778 kfree(vmx->host_msrs);
3779 kfree(vmx->guest_msrs);
3780 kvm_vcpu_uninit(vcpu);
a4770347 3781 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3782}
3783
fb3f0f51 3784static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3785{
fb3f0f51 3786 int err;
c16f862d 3787 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3788 int cpu;
6aa8b732 3789
a2fa3e9f 3790 if (!vmx)
fb3f0f51
RR		 3791 return ERR_PTR(-ENOMEM);
3792
2384d2b3
SY		 3793 allocate_vpid(vmx);
3794
fb3f0f51
RR		 3795 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3796 if (err)
3797 goto free_vcpu;
965b58a5 3798
a2fa3e9f 3799 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3800 if (!vmx->guest_msrs) {
3801 err = -ENOMEM;
3802 goto uninit_vcpu;
3803 }
965b58a5 3804
a2fa3e9f
GH		 3805 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3806 if (!vmx->host_msrs)
fb3f0f51 3807 goto free_guest_msrs;
965b58a5 3808
a2fa3e9f
GH		 3809 vmx->vmcs = alloc_vmcs();
3810 if (!vmx->vmcs)
fb3f0f51 3811 goto free_msrs;
a2fa3e9f
GH		 3812
3813 vmcs_clear(vmx->vmcs);
3814
15ad7146
AK		 3815 cpu = get_cpu();
3816 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3817 err = vmx_vcpu_setup(vmx);
fb3f0f51 3818 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3819 put_cpu();
fb3f0f51
RR		 3820 if (err)
3821 goto free_vmcs;
5e4a0b3c
MT		 3822 if (vm_need_virtualize_apic_accesses(kvm))
3823 if (alloc_apic_access_page(kvm) != 0)
3824 goto free_vmcs;
fb3f0f51 3825
b927a3ce
SY		 3826 if (enable_ept) {
3827 if (!kvm->arch.ept_identity_map_addr)
3828 kvm->arch.ept_identity_map_addr =
3829 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3830 if (alloc_identity_pagetable(kvm) != 0)
3831 goto free_vmcs;
b927a3ce 3832 }
b7ebfb05 3833
fb3f0f51
RR		 3834 return &vmx->vcpu;
3835
3836free_vmcs:
3837 free_vmcs(vmx->vmcs);
3838free_msrs:
3839 kfree(vmx->host_msrs);
3840free_guest_msrs:
3841 kfree(vmx->guest_msrs);
3842uninit_vcpu:
3843 kvm_vcpu_uninit(&vmx->vcpu);
3844free_vcpu:
a4770347 3845 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3846 return ERR_PTR(err);
6aa8b732
AK		 3847}
3848
002c7f7c
YS		 3849static void __init vmx_check_processor_compat(void *rtn)
3850{
3851 struct vmcs_config vmcs_conf;
3852
3853 *(int *)rtn = 0;
3854 if (setup_vmcs_config(&vmcs_conf) < 0)
3855 *(int *)rtn = -EIO;
3856 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3857 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3858 smp_processor_id());
3859 *(int *)rtn = -EIO;
3860 }
3861}
3862
67253af5
SY		 3863static int get_ept_level(void)
3864{
3865 return VMX_EPT_DEFAULT_GAW + 1;
3866}
3867
4b12f0de 3868static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3869{
4b12f0de
SY		 3870 u64 ret;
3871
522c68c4
SY		 3872 /* For VT-d and EPT combination
3873 * 1. MMIO: always map as UC
3874 * 2. EPT with VT-d:
3875 * a. VT-d without snooping control feature: can't guarantee the
3876 * result, try to trust guest.
3877 * b. VT-d with snooping control feature: snooping control feature of
3878 * VT-d engine can guarantee the cache correctness. Just set it
3879 * to WB to keep consistent with host. So the same as item 3.
3880 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3881 * consistent with host MTRR
3882 */
4b12f0de
SY		 3883 if (is_mmio)
3884 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 3885 else if (vcpu->kvm->arch.iommu_domain &&
3886 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3887 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3888 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 3889 else
522c68c4
SY		 3890 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3891 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 3892
3893 return ret;
64d4d521
SY		 3894}
3895
229456fc
MT		 3896static const struct trace_print_flags vmx_exit_reasons_str[] = {
3897 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3898 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3899 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3900 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3901 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3902 { EXIT_REASON_CR_ACCESS, "cr_access" },
3903 { EXIT_REASON_DR_ACCESS, "dr_access" },
3904 { EXIT_REASON_CPUID, "cpuid" },
3905 { EXIT_REASON_MSR_READ, "rdmsr" },
3906 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3907 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3908 { EXIT_REASON_HLT, "halt" },
3909 { EXIT_REASON_INVLPG, "invlpg" },
3910 { EXIT_REASON_VMCALL, "hypercall" },
3911 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3912 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3913 { EXIT_REASON_WBINVD, "wbinvd" },
3914 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3915 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3916 { -1, NULL }
3917};
3918
344f414f
JR		 3919static bool vmx_gb_page_enable(void)
3920{
3921 return false;
3922}
3923
cbdd1bea 3924static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3925 .cpu_has_kvm_support = cpu_has_kvm_support,
3926 .disabled_by_bios = vmx_disabled_by_bios,
3927 .hardware_setup = hardware_setup,
3928 .hardware_unsetup = hardware_unsetup,
002c7f7c 3929 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3930 .hardware_enable = hardware_enable,
3931 .hardware_disable = hardware_disable,
04547156 3932 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 3933
3934 .vcpu_create = vmx_create_vcpu,
3935 .vcpu_free = vmx_free_vcpu,
04d2cc77 3936 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3937
04d2cc77 3938 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3939 .vcpu_load = vmx_vcpu_load,
3940 .vcpu_put = vmx_vcpu_put,
3941
3942 .set_guest_debug = set_guest_debug,
3943 .get_msr = vmx_get_msr,
3944 .set_msr = vmx_set_msr,
3945 .get_segment_base = vmx_get_segment_base,
3946 .get_segment = vmx_get_segment,
3947 .set_segment = vmx_set_segment,
2e4d2653 3948 .get_cpl = vmx_get_cpl,
6aa8b732 3949 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3950 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3951 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3952 .set_cr3 = vmx_set_cr3,
3953 .set_cr4 = vmx_set_cr4,
6aa8b732 3954 .set_efer = vmx_set_efer,
6aa8b732
AK		 3955 .get_idt = vmx_get_idt,
3956 .set_idt = vmx_set_idt,
3957 .get_gdt = vmx_get_gdt,
3958 .set_gdt = vmx_set_gdt,
5fdbf976 3959 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3960 .get_rflags = vmx_get_rflags,
3961 .set_rflags = vmx_set_rflags,
3962
3963 .tlb_flush = vmx_flush_tlb,
6aa8b732 3964
6aa8b732 3965 .run = vmx_vcpu_run,
6062d012 3966 .handle_exit = vmx_handle_exit,
6aa8b732 3967 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3968 .set_interrupt_shadow = vmx_set_interrupt_shadow,
3969 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 3970 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 3971 .set_irq = vmx_inject_irq,
95ba8273 3972 .set_nmi = vmx_inject_nmi,
298101da 3973 .queue_exception = vmx_queue_exception,
78646121 3974 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273
GN		 3975 .nmi_allowed = vmx_nmi_allowed,
3976 .enable_nmi_window = enable_nmi_window,
3977 .enable_irq_window = enable_irq_window,
3978 .update_cr8_intercept = update_cr8_intercept,
95ba8273 3979
cbc94022 3980 .set_tss_addr = vmx_set_tss_addr,
67253af5 3981 .get_tdp_level = get_ept_level,
4b12f0de 3982 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 3983
3984 .exit_reasons_str = vmx_exit_reasons_str,
344f414f 3985 .gb_page_enable = vmx_gb_page_enable,
6aa8b732
AK		 3986};
3987
3988static int __init vmx_init(void)
3989{
fdef3ad1
HQ		 3990 int r;
3991
3e7c73e9 3992 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3993 if (!vmx_io_bitmap_a)
3994 return -ENOMEM;
3995
3e7c73e9 3996 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3997 if (!vmx_io_bitmap_b) {
3998 r = -ENOMEM;
3999 goto out;
4000 }
4001
5897297b
AK		 4002 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4003 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4004 r = -ENOMEM;
4005 goto out1;
4006 }
4007
5897297b
AK		 4008 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4009 if (!vmx_msr_bitmap_longmode) {
4010 r = -ENOMEM;
4011 goto out2;
4012 }
4013
fdef3ad1
HQ		 4014 /*
4015 * Allow direct access to the PC debug port (it is often used for I/O
4016 * delays, but the vmexits simply slow things down).
4017 */
3e7c73e9
AK		 4018 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4019 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4020
3e7c73e9 4021 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4022
5897297b
AK		 4023 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4024 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4025
2384d2b3
SY		 4026 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4027
cb498ea2 4028 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4029 if (r)
5897297b 4030 goto out3;
25c5f225 4031
5897297b
AK		 4032 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4033 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4034 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4035 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4036 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4037 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4038
089d034e 4039 if (enable_ept) {
1439442c 4040 bypass_guest_pf = 0;
5fdbcb9d 4041 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4042 VMX_EPT_WRITABLE_MASK);
534e38b4 4043 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4044 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4045 kvm_enable_tdp();
4046 } else
4047 kvm_disable_tdp();
1439442c 4048
c7addb90
AK		 4049 if (bypass_guest_pf)
4050 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4051
1439442c
SY		 4052 ept_sync_global();
4053
fdef3ad1
HQ		 4054 return 0;
4055
5897297b
AK		 4056out3:
4057 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4058out2:
5897297b 4059 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4060out1:
3e7c73e9 4061 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4062out:
3e7c73e9 4063 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4064 return r;
6aa8b732
AK		 4065}
4066
4067static void __exit vmx_exit(void)
4068{
5897297b
AK		 4069 free_page((unsigned long)vmx_msr_bitmap_legacy);
4070 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4071 free_page((unsigned long)vmx_io_bitmap_b);
4072 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4073
cb498ea2 4074 kvm_exit();
6aa8b732
AK		 4075}
4076
4077module_init(vmx_init)
4078module_exit(vmx_exit)
Ubuntu Artful kernel mirror