Update ShellPkg DSC file to build an extra version of
the Shell with all commands integrated. This verifies
that the shell can build in this max configuration.
Cc: Jaben Carsey <jaben.carsey@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Tested-by: Sami Mujawar <sami.mujawar@arm.com>
Update SLIT_ELEMENT() macro to use MultU64x64() to
perform multiplication on 64-bit operands. This is
required to avoid use of an intrinsic on IA32 VS20xx
builds.
Cc: Jaben Carsey <jaben.carsey@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Tested-by: Sami Mujawar <sami.mujawar@arm.com>
UefiCpuPkg/PiSmmCpuDxeSmm: Add check for pointer Pml5Entry
The pointer Pml5Entry, returned from call to function
AllocatePageTableMemory, may be null.
So add check for it.
Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
Zhang, Shenglei [Fri, 2 Aug 2019 06:55:27 +0000 (14:55 +0800)]
MdeModulePkg: Remove RecoveryLib.h and PeiRecoveryLibNull
RecoveryLib.h and PeiRecoveryLibNull have been deprecated from 2009,
so remove them.
https://bugzilla.tianocore.org/show_bug.cgi?id=1299
Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Zhang, Shenglei [Fri, 2 Aug 2019 06:55:26 +0000 (14:55 +0800)]
MdeModulePkg: Remove S3Lib.h and PeiS3LibNull
S3Lib.h and PeiS3LibNull have been deprecated since 2009, so remove them.
https://bugzilla.tianocore.org/show_bug.cgi?id=1299
Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Marcin Wojtas [Wed, 31 Jul 2019 06:25:19 +0000 (14:25 +0800)]
MdeModulePkg/UsbBusDxe: Return error when the device is not present
Until now, during the USB device enumeration when its PortState
USB_PORT_STAT_CONNECTION bit was not set, the stack was not informed
that the device is not present. Fix that by returning appropriate
error code.
Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Update the data structure signatures in the PiSmmCore
to be unique. Some of the signatures are the same as those
used by the DxeCore. For example, the memory pool head and
tail structures use the same signature in the PiSmmCore
and DxeCore. This means the use of the wrong FreePool API
will not be noticed at the time FreePool is called and a
failure can occur much later. By making the signatures
unique, misuse of an API is caught at that time the API is
called.
Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
MpInitLibInitialize in MpLib.c will be invoked on both PEI and DXE
CPU code, MicrocodeDetect would be performed twice and copy
Microcode from flash to memory twice as well, which consider as
duplicate work to lead longer boot time.
This patch just use microcode memory copied in PEI phase if exist.
Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
When running with Python 3.x and relying on GenCfgOpt.py to
automatically assign UPD offsets, the script crashed
because some float type variable not compatible with
the operations.
Converted those float variable to int to fix these issues.
Added arch output to build report so it's easy to tell
which arch is being generated. Useful when multiple versions
of a single module is being emitted for multiple archs.
Move Performance Monitoring Counter Group (PMCG) node ID mapping count
validation from the core IORT acpiview parser logic to a dedicated
function. Now, the pointer to the validation function is passed to the
IortNodePmcgParser[] ACPI_PARSER array.
This check does not affect the flow of IORT parsing and is limited to
a single table field in scope, therefore, it is better to keep it away
from the code responsible for traversing the table.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Split the Interrupt Controller Structure length validation in the
acpiview UEFI shell tool into two logical parts:
1. Ensuring MADT table parser forward progress.
2. Preventing MADT table buffer overruns.
Also, make the condition for infinite loop detection applicable to
all types of Interrupt Controller Structures (for all interrupt models
which can be represented in MADT). Check if the controller length
specified is shorter than the byte size of the first two fields
('Type' and 'Length') present in every valid Interrupt Controller
Structure.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Remove a call to ParseAcpi() responsible for getting the XSDT table
length. This call is not needed because the ACPI table buffer length is
provided as an input argument to the ParseAcpiXsdt() function.
Modify remaining code to use the AcpiTableLength argument of the
ParseAcpiXsdt() function instead of a global static variable.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Chen, Marc W [Mon, 29 Jul 2019 08:41:19 +0000 (16:41 +0800)]
MdePkg: Add PI 1.5 SmramMemoryReserve HOB file
This is a special GUID extension Hob to describe SMRAM memory regions
Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2020 Signed-off-by: Marc W Chen <marc.w.chen@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
MdePkg/PciExpress21.h: Fix the PCI industry standard register defines
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
The following two PCI Capability Structure registers are updated as per
the PCI Base Specification Revision 4:-
(1) The PCI Device capability register 2(PCI_REG_PCIE_DEVICE_CAPABILITY2)
needs to be upgraded for the PCI features like -
LN system CLS (LnSystemCLS),
10b Tag completer/requester register fields
(TenBitTagCompleterSupported, TenBitTagRequesterSupported),
Emergency power reduction support and initialization requirement
(EmergencyPowerReductionSupported,
EmergencyPowerReductionInitializationRequired),
and FRS support (FrsSupported ).
(2) The PCI Device Control register 2(PCI_REG_PCIE_DEVICE_CONTROL2) needs
to be upgraded for the -
Emergency power reduction request enabling
(EmergencyPowerReductionRequest), and also the 10b Extended Tag
enabling (TenBitTagRequesterEnable).
The following two are defined as per the PCI Express Base Specification
Revision 2.1:-
(1) Defined macro definitions for all the ranges of Maximum Payload Sizes
and Maximum Read Request Sizes register fields
(2) Defined macro definitions for all the ranges of Completion Timeout
value.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
Refer to CSS_2_1 5.7.2.1 "Non-Boolean comparisons must use a
compare operator (==, !=, >, < >=, <=).", use compare operator
for the non-boolean comparisons.
Cc: Jian Wang <jian.j.wang@intel.com> Cc: Ting Ye <ting.ye@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
ArmPkg: DebugPeCoffExtraActionLib: debugger commands are not errors
In commit 1fce963d89f3e we reduced the level of information printed
by PeCoffLoaderRelocateImageExtraAction() but we did not update the
similar PeCoffLoaderUnloadImageExtraAction() function.
PeCoffLoaderUnloadImageExtraAction() prints helpful debugger commands
for source level debugging. These messages should not be printed on the
EFI_D_ERROR level; they don't report errors. Change the debug level
(bitmask, actually) to DEBUG_LOAD | DEBUG_INFO, because the messages are
printed in relation to image loading, and they are informative.
Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reported-by: Andrew Jones <drjones@redhat.com> Suggested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
OvmfPkg/build.sh: use newer '-drive if=pflash' syntax when running qemu
Specify the firmware to use via the newer '-drive if=pflash' syntax
which allows specifying the raw format parameter. This
avoids warnings with newer version of QEMU.
Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
For semaphore type register, it required all processors to do the
task at the same time.
Current logic begins BSP's task after all APs have finished their tasks.
This will caused set semaphore task hang if semaphore has package
level type.
This patch use new EDKII_PEI_MP_SERVICES2_PPI to start all processors at
the same time to fix the potential hang issue.
Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
It includes all APIs existed in EFI_PEI_MP_SERVICES_PPI
and add new API EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS.
Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Add definition for new EDKII_PEI_MP_SERVICES2_PPI.
It includes all APIs existed in EFI_PEI_MP_SERVICES_PPI
and add new API EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS.
Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Add new MpInitLibStartupAllCPUs API uses to start all processors
at the same time.
Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
Add new MpInitLibStartupAllCPUs API uses to start all processors
at the same time.
Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Add new MpInitLibStartupAllCPUs API uses to start all processors
at the same time.
Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Commit 30f6148546c7 causes a build failure, when building for IA32:
> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c: In function
> 'PerformRemainingTasks':
> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c:1440:9: error:
> 'mCpuSmmStaticPageTable' undeclared (first use in this function)
> if (mCpuSmmStaticPageTable) {
"mCpuSmmStaticPageTable" is an X64-only variable. It is defined in
"X64/PageTbl.c", which is not linked into the IA32 binary. We must not
reference the variable in such code that is linked into both IA32 and X64
builds, such as "PiSmmCpuDxeSmm.c".
We have encountered the same challenge at least once in the past:
- https://bugzilla.tianocore.org/show_bug.cgi?id=1593
- commit 37f9fea5b88d ("UefiCpuPkg\CpuSmm: Save & restore CR2 on-demand
paging in SMM", 2019-04-04)
The right approach is to declare a new function in "PiSmmCpuDxeSmm.h", and
to provide two definitions for the function, one in "Ia32/PageTbl.c", and
another in "X64/PageTbl.c". The IA32 implementation should return a
constant value. The X64 implementation should return
"mCpuSmmStaticPageTable". (In the example named above, the functions were
SaveCr2() and RestoreCr2().)
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
[lersek@redhat.com: push revert immediately, due to build breakage that
would have been easy to catch before submitting the patch]
updated page fault handler to treat SMM access-out as allowed
address when static paging is not used.
But that commit is not complete because the page table is still
updated in SetUefiMemMapAttributes() for non-SMRAM memory. When SMM
code accesses non-SMRAM memory, page fault is still generated.
This patch skips to update page table for non-SMRAM memory and
page table itself.
Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
Current FSP SEC_IDT_TABLE structure is not natural aligned:
typedef struct _SEC_IDT_TABLE {
EFI_PEI_SERVICES *PeiService;
UINT64 IdtTable[];
} SEC_IDT_TABLE;
Compiler will insert DWORD padding between 2 elements and
GetPeiServicesTablePointer() in early phase then always
returns padding data from stack, which was not reset to 0
in SecMain.
Solution is to align FSP SEC_IDT_TABLE structure to UefiCpuPkg
to have UINT64 as PeiService field and reset it to 0.
Test: Verified on internal platform and booting successfully
with FSP API mode.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
OvmfPkg/build.sh: enable multitheaded build by default
Enable multithreaded builds by default when building OvmfPkg
using build.sh.
This can drastically reduce build times. For example, on a
modern ThreadRipper system the time required to build decreases
from 3 minutes to 1 minute.
EmbeddedPkg: list module-internal header files in INF [Sources]
The BaseTools build feature introduced for TianoCore#1804 / in commit 1fa6699e6cd4 ("BaseTools: Add a checking for Sources section in INF file",
2019-06-10) logs some (non-fatal) warnings about unlisted internal header
files. List those files explicitly.
Note: header files are added in lexicographical order only if the
underlying INF file already keeps the [Sources] and [LibraryClasses]
sections in lexicographical order. Otherwise, header files are added in
rough "logical" order.
CryptoPkg/BaseCryptLib: list module-internal header files in INF [Sources]
The BaseTools build feature introduced for TianoCore#1804 / in commit 1fa6699e6cd4 ("BaseTools: Add a checking for Sources section in INF file",
2019-06-10) logs some (non-fatal) warnings about unlisted internal header
files. List those files explicitly.
Note: header files are added in lexicographical order only if the
underlying INF file already keeps the [Sources] and [LibraryClasses]
sections in lexicographical order. Otherwise, header files are added in
rough "logical" order.
Cc: Jian Wang <jian.j.wang@intel.com> Cc: Ting Ye <ting.ye@intel.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
ArmPlatformPkg: list module-internal header files in INF [Sources]
The BaseTools build feature introduced for TianoCore#1804 / in commit 1fa6699e6cd4 ("BaseTools: Add a checking for Sources section in INF file",
2019-06-10) logs some (non-fatal) warnings about unlisted internal header
files. List those files explicitly.
Note: header files are added in lexicographical order only if the
underlying INF file already keeps the [Sources] and [LibraryClasses]
sections in lexicographical order. Otherwise, header files are added in
rough "logical" order.
ArmPkg: list module-internal header files in INF [Sources]
The BaseTools build feature introduced for TianoCore#1804 / in commit 1fa6699e6cd4 ("BaseTools: Add a checking for Sources section in INF file",
2019-06-10) logs some (non-fatal) warnings about unlisted internal header
files. List those files explicitly.
Note: header files are added in lexicographical order only if the
underlying INF file already keeps the [Sources] and [LibraryClasses]
sections in lexicographical order. Otherwise, header files are added in
rough "logical" order.
Create "Conf/.cache" folder as early as possible
so that the later code do need to check
if it exits and then create it.
Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
Remove redundant forward function declarations by repositioning
blocks of code. This way the code structure is consistent across
ACPI table parsers and the code becomes more concise.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Remove redundant forward function declarations by repositioning
blocks of code. This way the code structure is consistent across
ACPI table parsers and the code becomes more concise.
Replace multple use of literal values for GT Block Timer Frame
count/number validation with a macro definition.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Remove redundant forward function declarations by repositioning
blocks of code. This way the code structure is consistent across
ACPI table parsers and the code becomes more concise.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Remove redundant forward function declarations by repositioning
blocks of code. This way the code structure is consistent across
ACPI table parsers and the code becomes more concise.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Remove redundant forward function declarations by repositioning
blocks of code. This way the code structure is consistent across
ACPI table parsers and the code becomes more concise.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Remove redundant forward function declarations by repositioning
blocks of code. This way the code structure is consistent across
ACPI table parsers and the code becomes more concise.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Remove redundant forward function declarations by repositioning
blocks of code. This way the code structure is consistent across
ACPI table parsers and the code becomes more concise.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
If the file begin with single line Feed ('\n'), then
"AsciiChar == '\n' && ((CHAR8*)Buffer)[LoopVar-1] != '\r'"
would cause a underflow. Add this condition
"(AsciiChar == '\n' && LoopVar == 0)" before it to make sure
(LoopVar - 1) would never encounter a underflow.
Same change in Unicode section.
Cc: Jaben Carsey <jaben.carsey@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Andrew Fish <afish@apple.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Andrew Fish <afish@apple.com>
EDK2 Support for SM3 digest algorithm is needed to enable TPM with SM3 PCR
banks. This digest algorithm is part of the China Crypto algorithm suite.
This integration has dependency on the openssl_1_1_1b integration into
edk2.
This patch links SM3 support into Tcg2Pei and Tcg2Dxe.
EDK2 Support for SM3 digest algorithm is needed to enable TPM with SM3 PCR
banks. This digest algorithm is part of the China Crypto algorithm suite.
This integration has dependency on the openssl_1_1_1b integration into
edk2.
This patch sets SM3 bit in TPM2.0 hash mask by default.
Cc: Chao Zhang <chao.b.zhang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian Wang <jian.j.wang@intel.com> Signed-off-by: Imran Desai <imran.desai@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Message-Id: <20190718225326.40839-4-imran.desai@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
EDK2 Support for SM3 digest algorithm is needed to enable TPM with SM3 PCR
banks. This digest algorithm is part of the China Crypto algorithm suite.
This integration has dependency on the openssl_1_1_1b integration into
edk2.
This patch adds SM3 as an available digest algorithm to crypto router.
Cc: Chao Zhang <chao.b.zhang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian Wang <jian.j.wang@intel.com> Signed-off-by: Imran Desai <imran.desai@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Message-Id: <20190718225326.40839-3-imran.desai@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
EDK2 Support for SM3 digest algorithm is needed to enable TPM with SM3 PCR
banks. This digest algorithm is part of the China Crypto algorithm suite.
This integration has dependency on the openssl_1_1_1b integration into
edk2.
This patch add SM3 algorithm in the hashinstance library.
Delta in v7:
1. Dropped 95a040cff from v6 to address https://edk2.groups.io/g/devel/topic/ 32454898?p=,,,20,0,0,0::Created,,sm3,20,2,0,32454898,ct=1&ct=1
2. Relocated SM3 GUID definition from MdePkg to SecurityPkg in 9728b54f4
Cc: Chao Zhang <chao.b.zhang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian Wang <jian.j.wang@intel.com> Signed-off-by: Imran Desai <imran.desai@intel.com>
Message-Id: <20190718225326.40839-2-imran.desai@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Maintainers.txt: Fine-grained review ownership for MdeModulePkg
This commit add the reviewers information for modules within MdeModulePkg.
For now the modules list includes:
ACPI
ACPI S3
BDS
Console and Graphics
Core services (PEI, DXE and Runtime)
Device and Peripheral
Firmware Update
HII and UI
Management Mode (MM, SMM)
Reset
SMBIOS
UEFI Variable
Please note that, for MdeModulePkg components not included in the above
list, the reviewers will fall back to the package maintainers.
Cc: Andrew Fish <afish@apple.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Signed-off-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Maintainers.txt: split out section "OvmfPkg: CSM modules"
We ask contributors to copy David on patches that affect "CSM modules"
under OvmfPkg. With the "GetMaintainer.py" script being introduced later,
express this expectation in "Maintainers.txt" in machine-readable format.
Cc: Andrew Fish <afish@apple.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Acked-by: David Woodhouse <dwmw2@infradead.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Maintainers.txt: split out section "OvmfPkg: TCG- and TPM2-related modules"
We ask contributors to copy Marc-André and Stefan on patches that affect
"TPM2 modules" under OvmfPkg. With the "GetMaintainer.py" script being
introduced later, express this expectation in "Maintainers.txt" in
machine-readable format.
Cc: Andrew Fish <afish@apple.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Marc-André Lureau <marcandre.lureau@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Maintainers.txt: split out section "OvmfPkg: Xen-related modules"
We ask contributors to copy Anthony and Julien on patches that affect "Xen
modules" under OvmfPkg. With the "GetMaintainer.py" script being
introduced later, express this expectation in "Maintainers.txt" in
machine-readable format.
Cc: Andrew Fish <afish@apple.com> Cc: Anthony Perard <anthony.perard@citrix.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Julien Grall <julien.grall@arm.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Julien Grall <julien.grall@arm.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Maintainers.txt: split out section "ArmVirtPkg: modules used on Xen"
We ask contributors to copy Julien on patches that affect "Xen modules"
under ArmVirtPkg. With the "GetMaintainer.py" script being introduced
later, express this expectation in "Maintainers.txt" in machine-readable
format.
Cc: Andrew Fish <afish@apple.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Julien Grall <julien.grall@arm.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Julien Grall <julien.grall@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Leif Lindholm [Fri, 14 Jun 2019 19:27:39 +0000 (20:27 +0100)]
Maintainers.txt: update for filesystem area descriptions
Add comment describing new F: and X: tags for associating maintainership
sections with specific filesystem paths, including wildcards.
Add global section associating *all* code with devel@edk2.groups.io,
with a default '*' F: tag directing all modifications that do not hit a
rule to the stewards.
Also tag all files in top directory as maintained by the stewards.
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Tested-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Function in this library may be used by APs. Assert will be trig if AP
uses dynamic pcd.
This patch enhance the current code, remove the unnecessary usage of
dynamic PCD. This change try to avoid report this issue again later.
Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
AP calls CollectProcessorData() to collect processor info.
CollectProcessorData function finally calls PcdGetSize function to
get DynamicPCD PcdCpuFeaturesSetting value. PcdGetSize will use
PeiServices table which caused below assert info:
Processor Info: Package: 1, MaxCore : 4, MaxThread: 1
Package: 0, Valid Core : 4
ASSERT [CpuFeaturesPei] c:\projects\jsl\jsl_v1193\Edk2\MdePkg\Library
\PeiServicesTablePointerLibIdt\PeiServicesTablePointer.c(48):
PeiServices != ((void *) 0)
This change uses saved global pcd size instead of calls PcdGetSize to
fix this issue.
Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
The new VS2012 build failure is caused by 7a0df26.
xxx\registercpufeatureslib\dxeregistercpufeatureslib.c(258) :
warning C4701: potentially uninitialized local variable 'MpEvent' used
It is a false positive alarm.
MpEvent is assigned at line 238 and will be used at line 258, both
lines are controlled by "if (CpuFeaturesData->NumberOfCpus > 1)".
This patch initializes MpEvent to suppress incorrect compiler/analyzer
warnings.
Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
> Block (local) Scope
>
> [...]
>
> Data declarations may follow the opening brace of a compound statement,
> regardless of nesting depth, and before any code generating statements
> have been entered. Other than at the outermost block of a function body,
> this type of declaration is strongly discouraged.
Hoist such variable declarations in Base64Decode() to the outermost
function scope.
Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Fixes: 35e242b698cdc6205e99a6d6a188bf27fecf9fb4
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1980 Reported-by: Zhichao Gao <zhichao.gao@intel.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Tested-by: Philippe Mathieu-Daude <philmd@redhat.com>
Rewrite Base64Decode() from scratch, due to reasons listed in the second
reference below.
Implement Base64Decode() according to the specification added in the
previous patch. The decoder scans the input buffer once, it has no inner
loop(s), and it spills each output byte as soon as the output byte is
complete.
The intent is to only strengthen the checks (sanity and input) relative to
the previous implementation, hence the MAX_ADDRESS checks are reinstated.
Cc: Liming Gao <liming.gao@intel.com> Cc: Marvin Häuser <mhaeuser@outlook.de> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Zhichao Gao <zhichao.gao@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1891
Ref: http://mid.mail-archive.com/c495bd0b-ea4d-7206-8a4f-a7149760d19a@redhat.com Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Tested-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
[lersek@redhat.com: add last para to commit msg per talks w/ Marvin & Phil]
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1961
Enhance Ppin code to enable and unlock for TRUE State,
and disable and lock for FALSE State.
Note: enable and lock could not be set both.
According to SDM, once Enable_PPIN is set, attempt to write
1 to LockOut will cause #GP, and writing 1 to LockOut is
permitted only if Enable_PPIN is clear.
Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
EFI MM MP Protocol is defined in the PI 1.5 specification.
The MM MP protocol provides a set of functions to allow execution of
procedures on processors that have entered MM. This protocol has the
following properties:
1. The caller can invoke execution of a procedure on a processor, other
than the caller, that has also entered MM. Supports blocking and
non-blocking modes of operation.
2. The caller can invoke a procedure on multiple processors. Supports
blocking and non-blocking modes of operation.
Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Bob Feng [Thu, 11 Jul 2019 00:57:58 +0000 (08:57 +0800)]
BaseTools: Fixed the issue when ToolDefinitionFile is not generated
ToolDefinitionFile is generated by PlatformAutoGen.ToolDefinition()
Code assume ToolDefinition is always called before using
ToolDefinitionFile, but in some cases, it's not true.
Fixes: 4eee0cc7c Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
The patch changes SMM environment to use 5 level paging when CPU
supports it.
Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
(cherry picked from commit 7365eb2c8cf1d7112330d09918c0c67e8d0b827a)
This patch updates IA32_CR4 structure to include LA57 field.
Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
(cherry picked from commit 7c5010c7f88b790f4524c4a5311819e3af5e2752)
Ray Ni [Fri, 12 Jul 2019 07:11:02 +0000 (15:11 +0800)]
Revert "MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging"
This reverts commit 7c5010c7f88b790f4524c4a5311819e3af5e2752.
Commit 7c5010c7f8 MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging
technically breaks the EDKII development process documented in
https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process
and Maintainers.txt in EDKII repo root directory.
The voilation is commit 7c5010c7f8 doesn't have a Reviewed-by or
Acked-by from MdePkg maintainers.
Ray Ni [Fri, 12 Jul 2019 06:59:32 +0000 (14:59 +0800)]
Revert "UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports"
This reverts commit 7365eb2c8cf1d7112330d09918c0c67e8d0b827a.
Commit 7c5010c7f8 MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging
technically breaks the EDKII development process documented in
https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process
and Maintainers.txt in EDKII repo root directory.
The voilation is commit 7c5010c7f8 doesn't have a Reviewed-by or
Acked-by from MdePkg maintainers.
In order to revert 7c5010c7f8, 7365eb2c8 needs to revert first otherwise
simply reverting 7c5010c7f8 will cause build break.
Ray Ni [Wed, 10 Jul 2019 08:04:40 +0000 (16:04 +0800)]
Maintainers.txt: Remove maintainer info for IntelFsp[Wrapper]Pkg
We removed IntelFspPkg and IntelFspWrapperPkg for
<https://bugzilla.tianocore.org/show_bug.cgi?id=1819>; now remove
the dangling maintainer/reviewer assignments too.
Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Andrew Fish <afish@apple.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
projects / mirror_edk2.git / log