]> git.proxmox.com Git - mirror_qemu.git/blame - target-i386/cpu.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-i386/cpu: Introduce FeatureWord typedefs
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
c6dc6f63 26
1de7afc9
PB		 27#include "qemu/option.h"
28#include "qemu/config-file.h"
7b1b5d19 29#include "qapi/qmp/qerror.h"
c6dc6f63 30
7b1b5d19 31#include "qapi/visitor.h"
9c17d615 32#include "sysemu/arch_init.h"
71ad61d3 33
28f52cc0
VR		 34#include "hyperv.h"
35
65dee380 36#include "hw/hw.h"
b834b508 37#if defined(CONFIG_KVM)
ef8621b1 38#include <linux/kvm_para.h>
b834b508 39#endif
65dee380 40
9c17d615 41#include "sysemu/sysemu.h"
bdeec802
IM		 42#ifndef CONFIG_USER_ONLY
43#include "hw/xen.h"
44#include "hw/sysbus.h"
449994eb 45#include "hw/apic_internal.h"
bdeec802
IM		 46#endif
47
c6dc6f63
AP		 48/* feature flags taken from "Intel Processor Identification and the CPUID
49 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
50 * between feature naming conventions, aliases may be added.
51 */
52static const char *feature_name[] = {
53 "fpu", "vme", "de", "pse",
54 "tsc", "msr", "pae", "mce",
55 "cx8", "apic", NULL, "sep",
56 "mtrr", "pge", "mca", "cmov",
57 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
58 NULL, "ds" /* Intel dts */, "acpi", "mmx",
59 "fxsr", "sse", "sse2", "ss",
60 "ht" /* Intel htt */, "tm", "ia64", "pbe",
61};
62static const char *ext_feature_name[] = {
f370be3c 63 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 64 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 65 "tm2", "ssse3", "cid", NULL,
e117f772 66 "fma", "cx16", "xtpr", "pdcm",
434acb81 67 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 68 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 69 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 70 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 71};
3b671a40
EH		 72/* Feature names that are already defined on feature_name[] but are set on
73 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
74 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
75 * if and only if CPU vendor is AMD.
76 */
c6dc6f63 77static const char *ext2_feature_name[] = {
3b671a40
EH		 78 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
79 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
80 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
81 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
82 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
83 "nx|xd", NULL, "mmxext", NULL /* mmx */,
84 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 85 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 86};
87static const char *ext3_feature_name[] = {
88 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
89 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 90 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 91 "skinit", "wdt", NULL, "lwp",
92 "fma4", "tce", NULL, "nodeid_msr",
93 NULL, "tbm", "topoext", "perfctr_core",
94 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 95 NULL, NULL, NULL, NULL,
96};
97
98static const char *kvm_feature_name[] = {
c3d39807
DS		 99 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
100 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 107};
108
296acb64
JR		 109static const char *svm_feature_name[] = {
110 "npt", "lbrv", "svm_lock", "nrip_save",
111 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
112 NULL, NULL, "pause_filter", NULL,
113 "pfthreshold", NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
118};
119
a9321a4d 120static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 121 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
122 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 123 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 124 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
125};
126
5ef57876
EH		 127typedef struct FeatureWordInfo {
128 const char **feat_names;
129} FeatureWordInfo;
130
131static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
132 [FEAT_1_EDX] = { .feat_names = feature_name },
133 [FEAT_1_ECX] = { .feat_names = ext_feature_name },
134 [FEAT_8000_0001_EDX] = { .feat_names = ext2_feature_name },
135 [FEAT_8000_0001_ECX] = { .feat_names = ext3_feature_name },
136 [FEAT_KVM] = { .feat_names = kvm_feature_name },
137 [FEAT_SVM] = { .feat_names = svm_feature_name },
138 [FEAT_7_0_EBX] = { .feat_names = cpuid_7_0_ebx_feature_name },
139};
140
8b4beddc
EH		 141const char *get_register_name_32(unsigned int reg)
142{
143 static const char *reg_names[CPU_NB_REGS32] = {
144 [R_EAX] = "EAX",
145 [R_ECX] = "ECX",
146 [R_EDX] = "EDX",
147 [R_EBX] = "EBX",
148 [R_ESP] = "ESP",
149 [R_EBP] = "EBP",
150 [R_ESI] = "ESI",
151 [R_EDI] = "EDI",
152 };
153
154 if (reg > CPU_NB_REGS32) {
155 return NULL;
156 }
157 return reg_names[reg];
158}
159
c6dc6f63
AP		 160/* collects per-function cpuid data
161 */
162typedef struct model_features_t {
163 uint32_t *guest_feat;
164 uint32_t *host_feat;
c6dc6f63
AP		 165 const char **flag_names;
166 uint32_t cpuid;
8b4beddc
EH		 167 int reg;
168} model_features_t;
c6dc6f63
AP		 169
170int check_cpuid = 0;
171int enforce_cpuid = 0;
172
dc59944b
MT		 173#if defined(CONFIG_KVM)
174static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
175 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 176 (1 << KVM_FEATURE_CLOCKSOURCE2) |
177 (1 << KVM_FEATURE_ASYNC_PF) |
178 (1 << KVM_FEATURE_STEAL_TIME) |
179 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
180static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
181#else
182static uint32_t kvm_default_features = 0;
183static const uint32_t kvm_pv_eoi_features = 0;
184#endif
185
186void enable_kvm_pv_eoi(void)
187{
188 kvm_default_features |= kvm_pv_eoi_features;
189}
190
bb44e0d1
JK		 191void host_cpuid(uint32_t function, uint32_t count,
192 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 193{
194#if defined(CONFIG_KVM)
a1fd24af
AL		 195 uint32_t vec[4];
196
197#ifdef __x86_64__
198 asm volatile("cpuid"
199 : "=a"(vec[0]), "=b"(vec[1]),
200 "=c"(vec[2]), "=d"(vec[3])
201 : "0"(function), "c"(count) : "cc");
202#else
203 asm volatile("pusha \n\t"
204 "cpuid \n\t"
205 "mov %%eax, 0(%2) \n\t"
206 "mov %%ebx, 4(%2) \n\t"
207 "mov %%ecx, 8(%2) \n\t"
208 "mov %%edx, 12(%2) \n\t"
209 "popa"
210 : : "a"(function), "c"(count), "S"(vec)
211 : "memory", "cc");
212#endif
213
bdde476a 214 if (eax)
a1fd24af 215 *eax = vec[0];
bdde476a 216 if (ebx)
a1fd24af 217 *ebx = vec[1];
bdde476a 218 if (ecx)
a1fd24af 219 *ecx = vec[2];
bdde476a 220 if (edx)
a1fd24af 221 *edx = vec[3];
bdde476a
AP		 222#endif
223}
c6dc6f63
AP		 224
225#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
226
227/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
228 * a substring. ex if !NULL points to the first char after a substring,
229 * otherwise the string is assumed to sized by a terminating nul.
230 * Return lexical ordering of *s1:*s2.
231 */
232static int sstrcmp(const char *s1, const char *e1, const char *s2,
233 const char *e2)
234{
235 for (;;) {
236 if (!*s1 || !*s2 || *s1 != *s2)
237 return (*s1 - *s2);
238 ++s1, ++s2;
239 if (s1 == e1 && s2 == e2)
240 return (0);
241 else if (s1 == e1)
242 return (*s2);
243 else if (s2 == e2)
244 return (*s1);
245 }
246}
247
248/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
249 * '|' delimited (possibly empty) strings in which case search for a match
250 * within the alternatives proceeds left to right. Return 0 for success,
251 * non-zero otherwise.
252 */
253static int altcmp(const char *s, const char *e, const char *altstr)
254{
255 const char *p, *q;
256
257 for (q = p = altstr; ; ) {
258 while (*p && *p != '|')
259 ++p;
260 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
261 return (0);
262 if (!*p)
263 return (1);
264 else
265 q = ++p;
266 }
267}
268
269/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 270 * *pval and return true, otherwise return false
c6dc6f63 271 */
e41e0fc6
JK		 272static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
273 const char **featureset)
c6dc6f63
AP		 274{
275 uint32_t mask;
276 const char **ppc;
e41e0fc6 277 bool found = false;
c6dc6f63 278
e41e0fc6 279 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 280 if (*ppc && !altcmp(s, e, *ppc)) {
281 *pval |= mask;
e41e0fc6 282 found = true;
c6dc6f63 283 }
e41e0fc6
JK		 284 }
285 return found;
c6dc6f63
AP		 286}
287
5ef57876
EH		 288static void add_flagname_to_bitmaps(const char *flagname,
289 FeatureWordArray words)
c6dc6f63 290{
5ef57876
EH		 291 FeatureWord w;
292 for (w = 0; w < FEATURE_WORDS; w++) {
293 FeatureWordInfo *wi = &feature_word_info[w];
294 if (wi->feat_names &&
295 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
296 break;
297 }
298 }
299 if (w == FEATURE_WORDS) {
300 fprintf(stderr, "CPU feature %s not found\n", flagname);
301 }
c6dc6f63
AP		 302}
303
304typedef struct x86_def_t {
305 struct x86_def_t *next;
306 const char *name;
307 uint32_t level;
308 uint32_t vendor1, vendor2, vendor3;
309 int family;
310 int model;
311 int stepping;
b862d1fe 312 int tsc_khz;
296acb64
JR		 313 uint32_t features, ext_features, ext2_features, ext3_features;
314 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 315 uint32_t xlevel;
316 char model_id[48];
317 int vendor_override;
b3baa152
BW		 318 /* Store the results of Centaur's CPUID instructions */
319 uint32_t ext4_features;
320 uint32_t xlevel2;
13526728
EH		 321 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
322 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 323} x86_def_t;
324
325#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
326#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
327 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
328#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
329 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
330 CPUID_PSE36 | CPUID_FXSR)
331#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
332#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
333 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
334 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
335 CPUID_PAE | CPUID_SEP | CPUID_APIC)
336
551a2dec
AP		 337#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
338 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
339 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
340 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
341 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 342 /* partly implemented:
343 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
344 CPUID_PSE36 (needed for Solaris) */
345 /* missing:
346 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 347#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
a0a70681 348 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 349 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 350 /* missing:
351 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 352 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
60032ac0 353#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 354 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
355 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 356 /* missing:
357 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 358#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
359 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 360#define TCG_SVM_FEATURES 0
a9321a4d 361#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
551a2dec 362
c6dc6f63
AP		 363/* maintains list of cpu model definitions
364 */
365static x86_def_t *x86_defs = {NULL};
366
367/* built-in cpu model definitions (deprecated)
368 */
369static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 370 {
371 .name = "qemu64",
372 .level = 4,
373 .vendor1 = CPUID_VENDOR_AMD_1,
374 .vendor2 = CPUID_VENDOR_AMD_2,
375 .vendor3 = CPUID_VENDOR_AMD_3,
376 .family = 6,
377 .model = 2,
378 .stepping = 3,
379 .features = PPRO_FEATURES |
c6dc6f63 380 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 381 CPUID_PSE36,
382 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
60032ac0 383 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 384 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
385 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
386 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
387 .xlevel = 0x8000000A,
c6dc6f63
AP		 388 },
389 {
390 .name = "phenom",
391 .level = 5,
392 .vendor1 = CPUID_VENDOR_AMD_1,
393 .vendor2 = CPUID_VENDOR_AMD_2,
394 .vendor3 = CPUID_VENDOR_AMD_3,
395 .family = 16,
396 .model = 2,
397 .stepping = 3,
c6dc6f63
AP		 398 .features = PPRO_FEATURES |
399 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 400 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 401 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
402 CPUID_EXT_POPCNT,
60032ac0 403 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 404 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
405 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 406 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 407 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
408 CPUID_EXT3_CR8LEG,
409 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
410 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
411 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
412 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 413 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 414 .xlevel = 0x8000001A,
415 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
416 },
417 {
418 .name = "core2duo",
419 .level = 10,
ebe8b9c6
IM		 420 .vendor1 = CPUID_VENDOR_INTEL_1,
421 .vendor2 = CPUID_VENDOR_INTEL_2,
422 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 423 .family = 6,
424 .model = 15,
425 .stepping = 11,
c6dc6f63
AP		 426 .features = PPRO_FEATURES |
427 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 428 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
429 CPUID_HT | CPUID_TM | CPUID_PBE,
430 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
431 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
432 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 433 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
434 .ext3_features = CPUID_EXT3_LAHF_LM,
435 .xlevel = 0x80000008,
436 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
437 },
438 {
439 .name = "kvm64",
440 .level = 5,
441 .vendor1 = CPUID_VENDOR_INTEL_1,
442 .vendor2 = CPUID_VENDOR_INTEL_2,
443 .vendor3 = CPUID_VENDOR_INTEL_3,
444 .family = 15,
445 .model = 6,
446 .stepping = 1,
447 /* Missing: CPUID_VME, CPUID_HT */
448 .features = PPRO_FEATURES |
449 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
450 CPUID_PSE36,
451 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
452 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
453 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
60032ac0 454 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 455 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
456 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
457 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
458 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
459 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
460 .ext3_features = 0,
461 .xlevel = 0x80000008,
462 .model_id = "Common KVM processor"
463 },
c6dc6f63
AP		 464 {
465 .name = "qemu32",
466 .level = 4,
ebe8b9c6
IM		 467 .vendor1 = CPUID_VENDOR_INTEL_1,
468 .vendor2 = CPUID_VENDOR_INTEL_2,
469 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 470 .family = 6,
471 .model = 3,
472 .stepping = 3,
473 .features = PPRO_FEATURES,
474 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 475 .xlevel = 0x80000004,
c6dc6f63 476 },
eafaf1e5
AP		 477 {
478 .name = "kvm32",
479 .level = 5,
ebe8b9c6
IM		 480 .vendor1 = CPUID_VENDOR_INTEL_1,
481 .vendor2 = CPUID_VENDOR_INTEL_2,
482 .vendor3 = CPUID_VENDOR_INTEL_3,
eafaf1e5
AP		 483 .family = 15,
484 .model = 6,
485 .stepping = 1,
486 .features = PPRO_FEATURES |
487 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
488 .ext_features = CPUID_EXT_SSE3,
60032ac0 489 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
eafaf1e5
AP		 490 .ext3_features = 0,
491 .xlevel = 0x80000008,
492 .model_id = "Common 32-bit KVM processor"
493 },
c6dc6f63
AP		 494 {
495 .name = "coreduo",
496 .level = 10,
ebe8b9c6
IM		 497 .vendor1 = CPUID_VENDOR_INTEL_1,
498 .vendor2 = CPUID_VENDOR_INTEL_2,
499 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 500 .family = 6,
501 .model = 14,
502 .stepping = 8,
c6dc6f63 503 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 504 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
505 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
506 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
507 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 508 .ext2_features = CPUID_EXT2_NX,
509 .xlevel = 0x80000008,
510 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
511 },
512 {
513 .name = "486",
58012d66 514 .level = 1,
ebe8b9c6
IM		 515 .vendor1 = CPUID_VENDOR_INTEL_1,
516 .vendor2 = CPUID_VENDOR_INTEL_2,
517 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 518 .family = 4,
519 .model = 0,
520 .stepping = 0,
521 .features = I486_FEATURES,
522 .xlevel = 0,
523 },
524 {
525 .name = "pentium",
526 .level = 1,
ebe8b9c6
IM		 527 .vendor1 = CPUID_VENDOR_INTEL_1,
528 .vendor2 = CPUID_VENDOR_INTEL_2,
529 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 530 .family = 5,
531 .model = 4,
532 .stepping = 3,
533 .features = PENTIUM_FEATURES,
534 .xlevel = 0,
535 },
536 {
537 .name = "pentium2",
538 .level = 2,
ebe8b9c6
IM		 539 .vendor1 = CPUID_VENDOR_INTEL_1,
540 .vendor2 = CPUID_VENDOR_INTEL_2,
541 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 542 .family = 6,
543 .model = 5,
544 .stepping = 2,
545 .features = PENTIUM2_FEATURES,
546 .xlevel = 0,
547 },
548 {
549 .name = "pentium3",
550 .level = 2,
ebe8b9c6
IM		 551 .vendor1 = CPUID_VENDOR_INTEL_1,
552 .vendor2 = CPUID_VENDOR_INTEL_2,
553 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 554 .family = 6,
555 .model = 7,
556 .stepping = 3,
557 .features = PENTIUM3_FEATURES,
558 .xlevel = 0,
559 },
560 {
561 .name = "athlon",
562 .level = 2,
563 .vendor1 = CPUID_VENDOR_AMD_1,
564 .vendor2 = CPUID_VENDOR_AMD_2,
565 .vendor3 = CPUID_VENDOR_AMD_3,
566 .family = 6,
567 .model = 2,
568 .stepping = 3,
60032ac0
EH		 569 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
570 CPUID_MCA,
571 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
572 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 573 .xlevel = 0x80000008,
c6dc6f63
AP		 574 },
575 {
576 .name = "n270",
577 /* original is on level 10 */
578 .level = 5,
ebe8b9c6
IM		 579 .vendor1 = CPUID_VENDOR_INTEL_1,
580 .vendor2 = CPUID_VENDOR_INTEL_2,
581 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 582 .family = 6,
583 .model = 28,
584 .stepping = 2,
585 .features = PPRO_FEATURES |
8560efed
AJ		 586 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
587 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 588 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 589 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
590 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
60032ac0
EH		 591 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
592 CPUID_EXT2_NX,
8560efed 593 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 594 .xlevel = 0x8000000A,
595 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
596 },
3eca4642
EH		 597 {
598 .name = "Conroe",
599 .level = 2,
600 .vendor1 = CPUID_VENDOR_INTEL_1,
601 .vendor2 = CPUID_VENDOR_INTEL_2,
602 .vendor3 = CPUID_VENDOR_INTEL_3,
603 .family = 6,
604 .model = 2,
605 .stepping = 3,
606 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
607 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
608 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
609 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
610 CPUID_DE | CPUID_FP87,
611 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
612 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
613 .ext3_features = CPUID_EXT3_LAHF_LM,
614 .xlevel = 0x8000000A,
615 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
616 },
617 {
618 .name = "Penryn",
619 .level = 2,
620 .vendor1 = CPUID_VENDOR_INTEL_1,
621 .vendor2 = CPUID_VENDOR_INTEL_2,
622 .vendor3 = CPUID_VENDOR_INTEL_3,
623 .family = 6,
624 .model = 2,
625 .stepping = 3,
626 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
627 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
628 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
629 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
630 CPUID_DE | CPUID_FP87,
631 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
632 CPUID_EXT_SSE3,
633 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
634 .ext3_features = CPUID_EXT3_LAHF_LM,
635 .xlevel = 0x8000000A,
636 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
637 },
638 {
639 .name = "Nehalem",
640 .level = 2,
641 .vendor1 = CPUID_VENDOR_INTEL_1,
642 .vendor2 = CPUID_VENDOR_INTEL_2,
643 .vendor3 = CPUID_VENDOR_INTEL_3,
644 .family = 6,
645 .model = 2,
646 .stepping = 3,
647 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
648 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
649 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
650 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
651 CPUID_DE | CPUID_FP87,
652 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
653 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
654 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
655 .ext3_features = CPUID_EXT3_LAHF_LM,
656 .xlevel = 0x8000000A,
657 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
658 },
659 {
660 .name = "Westmere",
661 .level = 11,
662 .vendor1 = CPUID_VENDOR_INTEL_1,
663 .vendor2 = CPUID_VENDOR_INTEL_2,
664 .vendor3 = CPUID_VENDOR_INTEL_3,
665 .family = 6,
666 .model = 44,
667 .stepping = 1,
668 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
669 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
670 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
671 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
672 CPUID_DE | CPUID_FP87,
673 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
674 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
675 CPUID_EXT_SSE3,
676 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
677 .ext3_features = CPUID_EXT3_LAHF_LM,
678 .xlevel = 0x8000000A,
679 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
680 },
681 {
682 .name = "SandyBridge",
683 .level = 0xd,
684 .vendor1 = CPUID_VENDOR_INTEL_1,
685 .vendor2 = CPUID_VENDOR_INTEL_2,
686 .vendor3 = CPUID_VENDOR_INTEL_3,
687 .family = 6,
688 .model = 42,
689 .stepping = 1,
690 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
691 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
692 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
693 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
694 CPUID_DE | CPUID_FP87,
695 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
696 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
697 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
698 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
699 CPUID_EXT_SSE3,
700 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
701 CPUID_EXT2_SYSCALL,
702 .ext3_features = CPUID_EXT3_LAHF_LM,
703 .xlevel = 0x8000000A,
704 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
705 },
37507094
EH		 706 {
707 .name = "Haswell",
708 .level = 0xd,
709 .vendor1 = CPUID_VENDOR_INTEL_1,
710 .vendor2 = CPUID_VENDOR_INTEL_2,
711 .vendor3 = CPUID_VENDOR_INTEL_3,
712 .family = 6,
713 .model = 60,
714 .stepping = 1,
715 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
716 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 717 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 718 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
719 CPUID_DE | CPUID_FP87,
720 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
721 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
722 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
723 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
724 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
725 CPUID_EXT_PCID,
80ae4160
EH		 726 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
727 CPUID_EXT2_SYSCALL,
37507094
EH		 728 .ext3_features = CPUID_EXT3_LAHF_LM,
729 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
730 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
731 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
732 CPUID_7_0_EBX_RTM,
733 .xlevel = 0x8000000A,
734 .model_id = "Intel Core Processor (Haswell)",
735 },
3eca4642
EH		 736 {
737 .name = "Opteron_G1",
738 .level = 5,
739 .vendor1 = CPUID_VENDOR_AMD_1,
740 .vendor2 = CPUID_VENDOR_AMD_2,
741 .vendor3 = CPUID_VENDOR_AMD_3,
742 .family = 15,
743 .model = 6,
744 .stepping = 1,
745 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
746 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
747 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
748 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
749 CPUID_DE | CPUID_FP87,
750 .ext_features = CPUID_EXT_SSE3,
751 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
752 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
753 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
754 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
755 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
756 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
757 .xlevel = 0x80000008,
758 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
759 },
760 {
761 .name = "Opteron_G2",
762 .level = 5,
763 .vendor1 = CPUID_VENDOR_AMD_1,
764 .vendor2 = CPUID_VENDOR_AMD_2,
765 .vendor3 = CPUID_VENDOR_AMD_3,
766 .family = 15,
767 .model = 6,
768 .stepping = 1,
769 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
770 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
771 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
772 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
773 CPUID_DE | CPUID_FP87,
774 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
775 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
776 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
777 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
778 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
779 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
780 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
781 CPUID_EXT2_DE | CPUID_EXT2_FPU,
782 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
783 .xlevel = 0x80000008,
784 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
785 },
786 {
787 .name = "Opteron_G3",
788 .level = 5,
789 .vendor1 = CPUID_VENDOR_AMD_1,
790 .vendor2 = CPUID_VENDOR_AMD_2,
791 .vendor3 = CPUID_VENDOR_AMD_3,
792 .family = 15,
793 .model = 6,
794 .stepping = 1,
795 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
796 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
797 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
798 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
799 CPUID_DE | CPUID_FP87,
800 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
801 CPUID_EXT_SSE3,
802 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
803 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
804 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
805 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
806 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
807 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
808 CPUID_EXT2_DE | CPUID_EXT2_FPU,
809 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
810 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
811 .xlevel = 0x80000008,
812 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
813 },
814 {
815 .name = "Opteron_G4",
816 .level = 0xd,
817 .vendor1 = CPUID_VENDOR_AMD_1,
818 .vendor2 = CPUID_VENDOR_AMD_2,
819 .vendor3 = CPUID_VENDOR_AMD_3,
820 .family = 21,
821 .model = 1,
822 .stepping = 2,
823 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
824 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
825 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
826 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
827 CPUID_DE | CPUID_FP87,
828 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
829 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
830 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
831 CPUID_EXT_SSE3,
832 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
833 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
834 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
835 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
836 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
837 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
838 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
839 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
840 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
841 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
842 CPUID_EXT3_LAHF_LM,
843 .xlevel = 0x8000001A,
844 .model_id = "AMD Opteron 62xx class CPU",
845 },
021941b9
AP		 846 {
847 .name = "Opteron_G5",
848 .level = 0xd,
849 .vendor1 = CPUID_VENDOR_AMD_1,
850 .vendor2 = CPUID_VENDOR_AMD_2,
851 .vendor3 = CPUID_VENDOR_AMD_3,
852 .family = 21,
853 .model = 2,
854 .stepping = 0,
855 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
856 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
857 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
858 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
859 CPUID_DE | CPUID_FP87,
860 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
861 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
862 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
863 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
864 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
865 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
866 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
867 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
868 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
869 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
870 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
871 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
872 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
873 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
874 CPUID_EXT3_LAHF_LM,
875 .xlevel = 0x8000001A,
876 .model_id = "AMD Opteron 63xx class CPU",
877 },
c6dc6f63
AP		 878};
879
e4ab0d6b 880#ifdef CONFIG_KVM
c6dc6f63
AP		 881static int cpu_x86_fill_model_id(char *str)
882{
883 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
884 int i;
885
886 for (i = 0; i < 3; i++) {
887 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
888 memcpy(str + i * 16 + 0, &eax, 4);
889 memcpy(str + i * 16 + 4, &ebx, 4);
890 memcpy(str + i * 16 + 8, &ecx, 4);
891 memcpy(str + i * 16 + 12, &edx, 4);
892 }
893 return 0;
894}
e4ab0d6b 895#endif
c6dc6f63 896
6e746f30
EH		 897/* Fill a x86_def_t struct with information about the host CPU, and
898 * the CPU features supported by the host hardware + host kernel
899 *
900 * This function may be called only if KVM is enabled.
901 */
902static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 903{
e4ab0d6b 904#ifdef CONFIG_KVM
12869995 905 KVMState *s = kvm_state;
c6dc6f63
AP		 906 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
907
6e746f30
EH		 908 assert(kvm_enabled());
909
c6dc6f63
AP		 910 x86_cpu_def->name = "host";
911 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
c6dc6f63
AP		 912 x86_cpu_def->vendor1 = ebx;
913 x86_cpu_def->vendor2 = edx;
914 x86_cpu_def->vendor3 = ecx;
915
916 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
917 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
918 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
919 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 920
12869995
EH		 921 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
922 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
923 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 924
6e746f30 925 if (x86_cpu_def->level >= 7) {
12869995
EH		 926 x86_cpu_def->cpuid_7_0_ebx_features =
927 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728
EH		 928 } else {
929 x86_cpu_def->cpuid_7_0_ebx_features = 0;
930 }
931
12869995
EH		 932 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
933 x86_cpu_def->ext2_features =
934 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
935 x86_cpu_def->ext3_features =
936 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 937
c6dc6f63
AP		 938 cpu_x86_fill_model_id(x86_cpu_def->model_id);
939 x86_cpu_def->vendor_override = 0;
940
b3baa152
BW		 941 /* Call Centaur's CPUID instruction. */
942 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
943 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
944 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
945 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
12869995 946 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
b3baa152
BW		 947 if (eax >= 0xC0000001) {
948 /* Support VIA max extended level */
949 x86_cpu_def->xlevel2 = eax;
950 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
12869995
EH		 951 x86_cpu_def->ext4_features =
952 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
b3baa152
BW		 953 }
954 }
296acb64 955
fcb93c03
EH		 956 /* Other KVM-specific feature fields: */
957 x86_cpu_def->svm_features =
958 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
bd004bef
EH		 959 x86_cpu_def->kvm_features =
960 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 961
e4ab0d6b 962#endif /* CONFIG_KVM */
c6dc6f63
AP		 963}
964
965static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
966{
967 int i;
968
969 for (i = 0; i < 32; ++i)
970 if (1 << i & mask) {
8b4beddc
EH		 971 const char *reg = get_register_name_32(f->reg);
972 assert(reg);
973 fprintf(stderr, "warning: host doesn't support requested feature: "
974 "CPUID.%02XH:%s%s%s [bit %d]\n",
975 f->cpuid, reg,
976 f->flag_names[i] ? "." : "",
977 f->flag_names[i] ? f->flag_names[i] : "", i);
c6dc6f63
AP		 978 break;
979 }
980 return 0;
981}
982
983/* best effort attempt to inform user requested cpu flags aren't making
e8beac00 984 * their way to the guest.
6e746f30
EH		 985 *
986 * This function may be called only if KVM is enabled.
c6dc6f63 987 */
6e746f30 988static int kvm_check_features_against_host(x86_def_t *guest_def)
c6dc6f63
AP		 989{
990 x86_def_t host_def;
991 uint32_t mask;
992 int rv, i;
993 struct model_features_t ft[] = {
994 {&guest_def->features, &host_def.features,
e8beac00 995 feature_name, 0x00000001, R_EDX},
c6dc6f63 996 {&guest_def->ext_features, &host_def.ext_features,
e8beac00 997 ext_feature_name, 0x00000001, R_ECX},
c6dc6f63 998 {&guest_def->ext2_features, &host_def.ext2_features,
e8beac00 999 ext2_feature_name, 0x80000001, R_EDX},
c6dc6f63 1000 {&guest_def->ext3_features, &host_def.ext3_features,
e8beac00 1001 ext3_feature_name, 0x80000001, R_ECX}
8b4beddc 1002 };
c6dc6f63 1003
6e746f30
EH		 1004 assert(kvm_enabled());
1005
1006 kvm_cpu_fill_host(&host_def);
66fe09ee 1007 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63 1008 for (mask = 1; mask; mask <<= 1)
e8beac00 1009 if (*ft[i].guest_feat & mask &&
c6dc6f63
AP		 1010 !(*ft[i].host_feat & mask)) {
1011 unavailable_host_feature(&ft[i], mask);
1012 rv = 1;
1013 }
1014 return rv;
1015}
1016
95b8519d
AF		 1017static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1018 const char *name, Error **errp)
1019{
1020 X86CPU *cpu = X86_CPU(obj);
1021 CPUX86State *env = &cpu->env;
1022 int64_t value;
1023
1024 value = (env->cpuid_version >> 8) & 0xf;
1025 if (value == 0xf) {
1026 value += (env->cpuid_version >> 20) & 0xff;
1027 }
1028 visit_type_int(v, &value, name, errp);
1029}
1030
71ad61d3
AF		 1031static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1032 const char *name, Error **errp)
ed5e1ec3 1033{
71ad61d3
AF		 1034 X86CPU *cpu = X86_CPU(obj);
1035 CPUX86State *env = &cpu->env;
1036 const int64_t min = 0;
1037 const int64_t max = 0xff + 0xf;
1038 int64_t value;
1039
1040 visit_type_int(v, &value, name, errp);
1041 if (error_is_set(errp)) {
1042 return;
1043 }
1044 if (value < min || value > max) {
1045 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1046 name ? name : "null", value, min, max);
1047 return;
1048 }
1049
ed5e1ec3 1050 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1051 if (value > 0x0f) {
1052 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1053 } else {
71ad61d3 1054 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1055 }
1056}
1057
67e30c83
AF		 1058static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1059 const char *name, Error **errp)
1060{
1061 X86CPU *cpu = X86_CPU(obj);
1062 CPUX86State *env = &cpu->env;
1063 int64_t value;
1064
1065 value = (env->cpuid_version >> 4) & 0xf;
1066 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1067 visit_type_int(v, &value, name, errp);
1068}
1069
c5291a4f
AF		 1070static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1071 const char *name, Error **errp)
b0704cbd 1072{
c5291a4f
AF		 1073 X86CPU *cpu = X86_CPU(obj);
1074 CPUX86State *env = &cpu->env;
1075 const int64_t min = 0;
1076 const int64_t max = 0xff;
1077 int64_t value;
1078
1079 visit_type_int(v, &value, name, errp);
1080 if (error_is_set(errp)) {
1081 return;
1082 }
1083 if (value < min || value > max) {
1084 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1085 name ? name : "null", value, min, max);
1086 return;
1087 }
1088
b0704cbd 1089 env->cpuid_version &= ~0xf00f0;
c5291a4f 1090 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1091}
1092
35112e41
AF		 1093static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1094 void *opaque, const char *name,
1095 Error **errp)
1096{
1097 X86CPU *cpu = X86_CPU(obj);
1098 CPUX86State *env = &cpu->env;
1099 int64_t value;
1100
1101 value = env->cpuid_version & 0xf;
1102 visit_type_int(v, &value, name, errp);
1103}
1104
036e2222
AF		 1105static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1106 void *opaque, const char *name,
1107 Error **errp)
38c3dc46 1108{
036e2222
AF		 1109 X86CPU *cpu = X86_CPU(obj);
1110 CPUX86State *env = &cpu->env;
1111 const int64_t min = 0;
1112 const int64_t max = 0xf;
1113 int64_t value;
1114
1115 visit_type_int(v, &value, name, errp);
1116 if (error_is_set(errp)) {
1117 return;
1118 }
1119 if (value < min || value > max) {
1120 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1121 name ? name : "null", value, min, max);
1122 return;
1123 }
1124
38c3dc46 1125 env->cpuid_version &= ~0xf;
036e2222 1126 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1127}
1128
8e1898bf
AF		 1129static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1130 const char *name, Error **errp)
1131{
1132 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1133
fa029887 1134 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1135}
1136
1137static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1138 const char *name, Error **errp)
1139{
1140 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1141
fa029887 1142 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1143}
1144
16b93aa8
AF		 1145static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1146 const char *name, Error **errp)
1147{
1148 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1149
fa029887 1150 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1151}
1152
1153static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1154 const char *name, Error **errp)
1155{
1156 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1157
fa029887 1158 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1159}
1160
d480e1af
AF		 1161static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1162{
1163 X86CPU *cpu = X86_CPU(obj);
1164 CPUX86State *env = &cpu->env;
1165 char *value;
1166 int i;
1167
9df694ee 1168 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
d480e1af
AF		 1169 for (i = 0; i < 4; i++) {
1170 value[i ] = env->cpuid_vendor1 >> (8 * i);
1171 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1172 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1173 }
9df694ee 1174 value[CPUID_VENDOR_SZ] = '\0';
d480e1af
AF		 1175 return value;
1176}
1177
1178static void x86_cpuid_set_vendor(Object *obj, const char *value,
1179 Error **errp)
1180{
1181 X86CPU *cpu = X86_CPU(obj);
1182 CPUX86State *env = &cpu->env;
1183 int i;
1184
9df694ee 1185 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1186 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1187 "vendor", value);
1188 return;
1189 }
1190
1191 env->cpuid_vendor1 = 0;
1192 env->cpuid_vendor2 = 0;
1193 env->cpuid_vendor3 = 0;
1194 for (i = 0; i < 4; i++) {
1195 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1196 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1197 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1198 }
1199 env->cpuid_vendor_override = 1;
1200}
1201
63e886eb
AF		 1202static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1203{
1204 X86CPU *cpu = X86_CPU(obj);
1205 CPUX86State *env = &cpu->env;
1206 char *value;
1207 int i;
1208
1209 value = g_malloc(48 + 1);
1210 for (i = 0; i < 48; i++) {
1211 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1212 }
1213 value[48] = '\0';
1214 return value;
1215}
1216
938d4c25
AF		 1217static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1218 Error **errp)
dcce6675 1219{
938d4c25
AF		 1220 X86CPU *cpu = X86_CPU(obj);
1221 CPUX86State *env = &cpu->env;
dcce6675
AF		 1222 int c, len, i;
1223
1224 if (model_id == NULL) {
1225 model_id = "";
1226 }
1227 len = strlen(model_id);
d0a6acf4 1228 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1229 for (i = 0; i < 48; i++) {
1230 if (i >= len) {
1231 c = '\0';
1232 } else {
1233 c = (uint8_t)model_id[i];
1234 }
1235 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1236 }
1237}
1238
89e48965
AF		 1239static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1240 const char *name, Error **errp)
1241{
1242 X86CPU *cpu = X86_CPU(obj);
1243 int64_t value;
1244
1245 value = cpu->env.tsc_khz * 1000;
1246 visit_type_int(v, &value, name, errp);
1247}
1248
1249static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1250 const char *name, Error **errp)
1251{
1252 X86CPU *cpu = X86_CPU(obj);
1253 const int64_t min = 0;
2e84849a 1254 const int64_t max = INT64_MAX;
89e48965
AF		 1255 int64_t value;
1256
1257 visit_type_int(v, &value, name, errp);
1258 if (error_is_set(errp)) {
1259 return;
1260 }
1261 if (value < min || value > max) {
1262 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1263 name ? name : "null", value, min, max);
1264 return;
1265 }
1266
1267 cpu->env.tsc_khz = value / 1000;
1268}
1269
8f961357 1270static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
c6dc6f63 1271{
c6dc6f63
AP		 1272 x86_def_t *def;
1273
9f3fb565
EH		 1274 for (def = x86_defs; def; def = def->next) {
1275 if (name && !strcmp(name, def->name)) {
c6dc6f63 1276 break;
9f3fb565
EH		 1277 }
1278 }
04c5b17a 1279 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
6e746f30 1280 kvm_cpu_fill_host(x86_cpu_def);
c6dc6f63 1281 } else if (!def) {
8f961357 1282 return -1;
c6dc6f63
AP		 1283 } else {
1284 memcpy(x86_cpu_def, def, sizeof(*def));
1285 }
1286
8f961357
EH		 1287 return 0;
1288}
1289
1290/* Parse "+feature,-feature,feature=foo" CPU feature string
1291 */
1292static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1293{
1294 unsigned int i;
1295 char *featurestr; /* Single 'key=value" string being parsed */
1296 /* Features to be added */
5ef57876
EH		 1297 FeatureWordArray plus_features = {
1298 [FEAT_KVM] = kvm_default_features,
1299 };
8f961357 1300 /* Features to be removed */
5ef57876 1301 FeatureWordArray minus_features = { 0 };
8f961357
EH		 1302 uint32_t numvalue;
1303
5ef57876 1304 add_flagname_to_bitmaps("hypervisor", plus_features);
c6dc6f63 1305
8f961357 1306 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1307
1308 while (featurestr) {
1309 char *val;
1310 if (featurestr[0] == '+') {
5ef57876 1311 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1312 } else if (featurestr[0] == '-') {
5ef57876 1313 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1314 } else if ((val = strchr(featurestr, '='))) {
1315 *val = 0; val++;
1316 if (!strcmp(featurestr, "family")) {
1317 char *err;
1318 numvalue = strtoul(val, &err, 0);
a88a677f 1319 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 1320 fprintf(stderr, "bad numerical value %s\n", val);
1321 goto error;
1322 }
1323 x86_cpu_def->family = numvalue;
1324 } else if (!strcmp(featurestr, "model")) {
1325 char *err;
1326 numvalue = strtoul(val, &err, 0);
1327 if (!*val || *err || numvalue > 0xff) {
1328 fprintf(stderr, "bad numerical value %s\n", val);
1329 goto error;
1330 }
1331 x86_cpu_def->model = numvalue;
1332 } else if (!strcmp(featurestr, "stepping")) {
1333 char *err;
1334 numvalue = strtoul(val, &err, 0);
1335 if (!*val || *err || numvalue > 0xf) {
1336 fprintf(stderr, "bad numerical value %s\n", val);
1337 goto error;
1338 }
1339 x86_cpu_def->stepping = numvalue ;
1340 } else if (!strcmp(featurestr, "level")) {
1341 char *err;
1342 numvalue = strtoul(val, &err, 0);
1343 if (!*val || *err) {
1344 fprintf(stderr, "bad numerical value %s\n", val);
1345 goto error;
1346 }
1347 x86_cpu_def->level = numvalue;
1348 } else if (!strcmp(featurestr, "xlevel")) {
1349 char *err;
1350 numvalue = strtoul(val, &err, 0);
1351 if (!*val || *err) {
1352 fprintf(stderr, "bad numerical value %s\n", val);
1353 goto error;
1354 }
1355 if (numvalue < 0x80000000) {
2f7a21c4 1356 numvalue += 0x80000000;
c6dc6f63
AP		 1357 }
1358 x86_cpu_def->xlevel = numvalue;
1359 } else if (!strcmp(featurestr, "vendor")) {
1360 if (strlen(val) != 12) {
1361 fprintf(stderr, "vendor string must be 12 chars long\n");
1362 goto error;
1363 }
1364 x86_cpu_def->vendor1 = 0;
1365 x86_cpu_def->vendor2 = 0;
1366 x86_cpu_def->vendor3 = 0;
1367 for(i = 0; i < 4; i++) {
1368 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1369 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1370 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1371 }
1372 x86_cpu_def->vendor_override = 1;
1373 } else if (!strcmp(featurestr, "model_id")) {
1374 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1375 val);
b862d1fe
JR		 1376 } else if (!strcmp(featurestr, "tsc_freq")) {
1377 int64_t tsc_freq;
1378 char *err;
1379
1380 tsc_freq = strtosz_suffix_unit(val, &err,
1381 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1382 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 1383 fprintf(stderr, "bad numerical value %s\n", val);
1384 goto error;
1385 }
1386 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 1387 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1388 char *err;
1389 numvalue = strtoul(val, &err, 0);
1390 if (!*val || *err) {
1391 fprintf(stderr, "bad numerical value %s\n", val);
1392 goto error;
1393 }
1394 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1395 } else {
1396 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1397 goto error;
1398 }
1399 } else if (!strcmp(featurestr, "check")) {
1400 check_cpuid = 1;
1401 } else if (!strcmp(featurestr, "enforce")) {
1402 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1403 } else if (!strcmp(featurestr, "hv_relaxed")) {
1404 hyperv_enable_relaxed_timing(true);
1405 } else if (!strcmp(featurestr, "hv_vapic")) {
1406 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1407 } else {
1408 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1409 goto error;
1410 }
1411 featurestr = strtok(NULL, ",");
1412 }
5ef57876
EH		 1413 x86_cpu_def->features |= plus_features[FEAT_1_EDX];
1414 x86_cpu_def->ext_features |= plus_features[FEAT_1_ECX];
1415 x86_cpu_def->ext2_features |= plus_features[FEAT_8000_0001_EDX];
1416 x86_cpu_def->ext3_features |= plus_features[FEAT_8000_0001_ECX];
1417 x86_cpu_def->kvm_features |= plus_features[FEAT_KVM];
1418 x86_cpu_def->svm_features |= plus_features[FEAT_SVM];
1419 x86_cpu_def->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1420 x86_cpu_def->features &= ~minus_features[FEAT_1_EDX];
1421 x86_cpu_def->ext_features &= ~minus_features[FEAT_1_ECX];
1422 x86_cpu_def->ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1423 x86_cpu_def->ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1424 x86_cpu_def->kvm_features &= ~minus_features[FEAT_KVM];
1425 x86_cpu_def->svm_features &= ~minus_features[FEAT_SVM];
1426 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
6e746f30
EH		 1427 if (check_cpuid && kvm_enabled()) {
1428 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
c6dc6f63
AP		 1429 goto error;
1430 }
c6dc6f63
AP		 1431 return 0;
1432
1433error:
c6dc6f63
AP		 1434 return -1;
1435}
1436
1437/* generate a composite string into buf of all cpuid names in featureset
1438 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1439 * if flags, suppress names undefined in featureset.
1440 */
1441static void listflags(char *buf, int bufsize, uint32_t fbits,
1442 const char **featureset, uint32_t flags)
1443{
1444 const char **p = &featureset[31];
1445 char *q, *b, bit;
1446 int nc;
1447
1448 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1449 *buf = '\0';
1450 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1451 if (fbits & 1 << bit && (*p || !flags)) {
1452 if (*p)
1453 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1454 else
1455 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1456 if (bufsize <= nc) {
1457 if (b) {
1458 memcpy(b, "...", sizeof("..."));
1459 }
1460 return;
1461 }
1462 q += nc;
1463 bufsize -= nc;
1464 }
1465}
1466
e916cbf8
PM		 1467/* generate CPU information. */
1468void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1469{
c6dc6f63
AP		 1470 x86_def_t *def;
1471 char buf[256];
1472
c6dc6f63 1473 for (def = x86_defs; def; def = def->next) {
c04321b3 1474 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1475 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1476 }
ed2c54d4
AP		 1477 if (kvm_enabled()) {
1478 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1479 }
6cdf8854
PM		 1480 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1481 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
4a19e505 1482 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1483 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
4a19e505 1484 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1485 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
4a19e505 1486 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1487 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
4a19e505 1488 (*cpu_fprintf)(f, " %s\n", buf);
c6dc6f63
AP		 1489}
1490
76b64a7a 1491CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1492{
1493 CpuDefinitionInfoList *cpu_list = NULL;
1494 x86_def_t *def;
1495
1496 for (def = x86_defs; def; def = def->next) {
1497 CpuDefinitionInfoList *entry;
1498 CpuDefinitionInfo *info;
1499
1500 info = g_malloc0(sizeof(*info));
1501 info->name = g_strdup(def->name);
1502
1503 entry = g_malloc0(sizeof(*entry));
1504 entry->value = info;
1505 entry->next = cpu_list;
1506 cpu_list = entry;
1507 }
1508
1509 return cpu_list;
1510}
1511
bc74b7db
EH		 1512#ifdef CONFIG_KVM
1513static void filter_features_for_kvm(X86CPU *cpu)
1514{
1515 CPUX86State *env = &cpu->env;
1516 KVMState *s = kvm_state;
1517
b8091f24
EH		 1518 env->cpuid_features &=
1519 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1520 env->cpuid_ext_features &=
1521 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1522 env->cpuid_ext2_features &=
1523 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1524 env->cpuid_ext3_features &=
1525 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1526 env->cpuid_svm_features &=
1527 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
ffa8c11f
EH		 1528 env->cpuid_7_0_ebx_features &=
1529 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
bc74b7db 1530 env->cpuid_kvm_features &=
b8091f24
EH		 1531 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1532 env->cpuid_ext4_features &=
1533 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
bc74b7db
EH		 1534
1535}
1536#endif
1537
61dcd775 1538int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1539{
61dcd775 1540 CPUX86State *env = &cpu->env;
c6dc6f63 1541 x86_def_t def1, *def = &def1;
71ad61d3 1542 Error *error = NULL;
8f961357
EH		 1543 char *name, *features;
1544 gchar **model_pieces;
c6dc6f63 1545
db0ad1ba
JR		 1546 memset(def, 0, sizeof(*def));
1547
8f961357
EH		 1548 model_pieces = g_strsplit(cpu_model, ",", 2);
1549 if (!model_pieces[0]) {
1550 goto error;
1551 }
1552 name = model_pieces[0];
1553 features = model_pieces[1];
1554
1555 if (cpu_x86_find_by_name(def, name) < 0) {
1556 goto error;
1557 }
1558
1559 if (cpu_x86_parse_featurestr(def, features) < 0) {
1560 goto error;
1561 }
ebe8b9c6
IM		 1562 assert(def->vendor1);
1563 env->cpuid_vendor1 = def->vendor1;
1564 env->cpuid_vendor2 = def->vendor2;
1565 env->cpuid_vendor3 = def->vendor3;
c6dc6f63 1566 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1567 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1568 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1569 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1570 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1571 env->cpuid_features = def->features;
c6dc6f63
AP		 1572 env->cpuid_ext_features = def->ext_features;
1573 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1574 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1575 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1576 env->cpuid_kvm_features = def->kvm_features;
296acb64 1577 env->cpuid_svm_features = def->svm_features;
b3baa152 1578 env->cpuid_ext4_features = def->ext4_features;
a9321a4d 1579 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
b3baa152 1580 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1581 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1582 "tsc-frequency", &error);
3b671a40 1583
938d4c25 1584 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
18eb473f
IM		 1585 if (error) {
1586 fprintf(stderr, "%s\n", error_get_pretty(error));
71ad61d3 1587 error_free(error);
8f961357 1588 goto error;
71ad61d3 1589 }
8f961357
EH		 1590
1591 g_strfreev(model_pieces);
c6dc6f63 1592 return 0;
8f961357
EH		 1593error:
1594 g_strfreev(model_pieces);
1595 return -1;
c6dc6f63
AP		 1596}
1597
1598#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1599
0e26b7b8
BS		 1600void cpu_clear_apic_feature(CPUX86State *env)
1601{
1602 env->cpuid_features &= ~CPUID_APIC;
1603}
1604
c6dc6f63
AP		 1605#endif /* !CONFIG_USER_ONLY */
1606
c04321b3 1607/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1608 */
1609void x86_cpudef_setup(void)
1610{
93bfef4c
CV		 1611 int i, j;
1612 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1613
1614 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291
EH		 1615 x86_def_t *def = &builtin_x86_defs[i];
1616 def->next = x86_defs;
93bfef4c
CV		 1617
1618 /* Look for specific "cpudef" models that */
09faecf2 1619 /* have the QEMU version in .model_id */
93bfef4c 1620 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1621 if (strcmp(model_with_versions[j], def->name) == 0) {
1622 pstrcpy(def->model_id, sizeof(def->model_id),
1623 "QEMU Virtual CPU version ");
1624 pstrcat(def->model_id, sizeof(def->model_id),
1625 qemu_get_version());
93bfef4c
CV		 1626 break;
1627 }
1628 }
1629
bc3e1291 1630 x86_defs = def;
c6dc6f63 1631 }
c6dc6f63
AP		 1632}
1633
c6dc6f63
AP		 1634static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1635 uint32_t *ecx, uint32_t *edx)
1636{
1637 *ebx = env->cpuid_vendor1;
1638 *edx = env->cpuid_vendor2;
1639 *ecx = env->cpuid_vendor3;
1640
1641 /* sysenter isn't supported on compatibility mode on AMD, syscall
1642 * isn't supported in compatibility mode on Intel.
1643 * Normally we advertise the actual cpu vendor, but you can override
1644 * this if you want to use KVM's sysenter/syscall emulation
1645 * in compatibility mode and when doing cross vendor migration
1646 */
89354998 1647 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1648 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1649 }
1650}
1651
1652void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1653 uint32_t *eax, uint32_t *ebx,
1654 uint32_t *ecx, uint32_t *edx)
1655{
a60f24b5
AF		 1656 X86CPU *cpu = x86_env_get_cpu(env);
1657 CPUState *cs = CPU(cpu);
1658
c6dc6f63
AP		 1659 /* test if maximum index reached */
1660 if (index & 0x80000000) {
b3baa152
BW		 1661 if (index > env->cpuid_xlevel) {
1662 if (env->cpuid_xlevel2 > 0) {
1663 /* Handle the Centaur's CPUID instruction. */
1664 if (index > env->cpuid_xlevel2) {
1665 index = env->cpuid_xlevel2;
1666 } else if (index < 0xC0000000) {
1667 index = env->cpuid_xlevel;
1668 }
1669 } else {
57f26ae7
EH		 1670 /* Intel documentation states that invalid EAX input will
1671 * return the same information as EAX=cpuid_level
1672 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1673 */
1674 index = env->cpuid_level;
b3baa152
BW		 1675 }
1676 }
c6dc6f63
AP		 1677 } else {
1678 if (index > env->cpuid_level)
1679 index = env->cpuid_level;
1680 }
1681
1682 switch(index) {
1683 case 0:
1684 *eax = env->cpuid_level;
1685 get_cpuid_vendor(env, ebx, ecx, edx);
1686 break;
1687 case 1:
1688 *eax = env->cpuid_version;
1689 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1690 *ecx = env->cpuid_ext_features;
1691 *edx = env->cpuid_features;
ce3960eb
AF		 1692 if (cs->nr_cores * cs->nr_threads > 1) {
1693 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 1694 *edx |= 1 << 28; /* HTT bit */
1695 }
1696 break;
1697 case 2:
1698 /* cache info: needed for Pentium Pro compatibility */
1699 *eax = 1;
1700 *ebx = 0;
1701 *ecx = 0;
1702 *edx = 0x2c307d;
1703 break;
1704 case 4:
1705 /* cache info: needed for Core compatibility */
ce3960eb
AF		 1706 if (cs->nr_cores > 1) {
1707 *eax = (cs->nr_cores - 1) << 26;
c6dc6f63 1708 } else {
2f7a21c4 1709 *eax = 0;
c6dc6f63
AP		 1710 }
1711 switch (count) {
1712 case 0: /* L1 dcache info */
1713 *eax |= 0x0000121;
1714 *ebx = 0x1c0003f;
1715 *ecx = 0x000003f;
1716 *edx = 0x0000001;
1717 break;
1718 case 1: /* L1 icache info */
1719 *eax |= 0x0000122;
1720 *ebx = 0x1c0003f;
1721 *ecx = 0x000003f;
1722 *edx = 0x0000001;
1723 break;
1724 case 2: /* L2 cache info */
1725 *eax |= 0x0000143;
ce3960eb
AF		 1726 if (cs->nr_threads > 1) {
1727 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63
AP		 1728 }
1729 *ebx = 0x3c0003f;
1730 *ecx = 0x0000fff;
1731 *edx = 0x0000001;
1732 break;
1733 default: /* end of info */
1734 *eax = 0;
1735 *ebx = 0;
1736 *ecx = 0;
1737 *edx = 0;
1738 break;
1739 }
1740 break;
1741 case 5:
1742 /* mwait info: needed for Core compatibility */
1743 *eax = 0; /* Smallest monitor-line size in bytes */
1744 *ebx = 0; /* Largest monitor-line size in bytes */
1745 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1746 *edx = 0;
1747 break;
1748 case 6:
1749 /* Thermal and Power Leaf */
1750 *eax = 0;
1751 *ebx = 0;
1752 *ecx = 0;
1753 *edx = 0;
1754 break;
f7911686 1755 case 7:
13526728
EH		 1756 /* Structured Extended Feature Flags Enumeration Leaf */
1757 if (count == 0) {
1758 *eax = 0; /* Maximum ECX value for sub-leaves */
a9321a4d 1759 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
13526728
EH		 1760 *ecx = 0; /* Reserved */
1761 *edx = 0; /* Reserved */
f7911686
YW		 1762 } else {
1763 *eax = 0;
1764 *ebx = 0;
1765 *ecx = 0;
1766 *edx = 0;
1767 }
1768 break;
c6dc6f63
AP		 1769 case 9:
1770 /* Direct Cache Access Information Leaf */
1771 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1772 *ebx = 0;
1773 *ecx = 0;
1774 *edx = 0;
1775 break;
1776 case 0xA:
1777 /* Architectural Performance Monitoring Leaf */
a0fa8208 1778 if (kvm_enabled()) {
a60f24b5 1779 KVMState *s = cs->kvm_state;
a0fa8208
GN		 1780
1781 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1782 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1783 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1784 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1785 } else {
1786 *eax = 0;
1787 *ebx = 0;
1788 *ecx = 0;
1789 *edx = 0;
1790 }
c6dc6f63 1791 break;
51e49430
SY		 1792 case 0xD:
1793 /* Processor Extended State */
1794 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1795 *eax = 0;
1796 *ebx = 0;
1797 *ecx = 0;
1798 *edx = 0;
1799 break;
1800 }
1801 if (kvm_enabled()) {
a60f24b5 1802 KVMState *s = cs->kvm_state;
ba9bc59e
JK		 1803
1804 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1805 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1806 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1807 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1808 } else {
1809 *eax = 0;
1810 *ebx = 0;
1811 *ecx = 0;
1812 *edx = 0;
1813 }
1814 break;
c6dc6f63
AP		 1815 case 0x80000000:
1816 *eax = env->cpuid_xlevel;
1817 *ebx = env->cpuid_vendor1;
1818 *edx = env->cpuid_vendor2;
1819 *ecx = env->cpuid_vendor3;
1820 break;
1821 case 0x80000001:
1822 *eax = env->cpuid_version;
1823 *ebx = 0;
1824 *ecx = env->cpuid_ext3_features;
1825 *edx = env->cpuid_ext2_features;
1826
1827 /* The Linux kernel checks for the CMPLegacy bit and
1828 * discards multiple thread information if it is set.
1829 * So dont set it here for Intel to make Linux guests happy.
1830 */
ce3960eb 1831 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 1832 uint32_t tebx, tecx, tedx;
1833 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1834 if (tebx != CPUID_VENDOR_INTEL_1 ||
1835 tedx != CPUID_VENDOR_INTEL_2 ||
1836 tecx != CPUID_VENDOR_INTEL_3) {
1837 *ecx |= 1 << 1; /* CmpLegacy bit */
1838 }
1839 }
c6dc6f63
AP		 1840 break;
1841 case 0x80000002:
1842 case 0x80000003:
1843 case 0x80000004:
1844 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1845 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1846 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1847 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1848 break;
1849 case 0x80000005:
1850 /* cache info (L1 cache) */
1851 *eax = 0x01ff01ff;
1852 *ebx = 0x01ff01ff;
1853 *ecx = 0x40020140;
1854 *edx = 0x40020140;
1855 break;
1856 case 0x80000006:
1857 /* cache info (L2 cache) */
1858 *eax = 0;
1859 *ebx = 0x42004200;
1860 *ecx = 0x02008140;
1861 *edx = 0;
1862 break;
1863 case 0x80000008:
1864 /* virtual & phys address size in low 2 bytes. */
1865/* XXX: This value must match the one used in the MMU code. */
1866 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1867 /* 64 bit processor */
1868/* XXX: The physical address space is limited to 42 bits in exec.c. */
1869 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1870 } else {
1871 if (env->cpuid_features & CPUID_PSE36)
1872 *eax = 0x00000024; /* 36 bits physical */
1873 else
1874 *eax = 0x00000020; /* 32 bits physical */
1875 }
1876 *ebx = 0;
1877 *ecx = 0;
1878 *edx = 0;
ce3960eb
AF		 1879 if (cs->nr_cores * cs->nr_threads > 1) {
1880 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 1881 }
1882 break;
1883 case 0x8000000A:
9f3fb565
EH		 1884 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1885 *eax = 0x00000001; /* SVM Revision */
1886 *ebx = 0x00000010; /* nr of ASIDs */
1887 *ecx = 0;
1888 *edx = env->cpuid_svm_features; /* optional features */
1889 } else {
1890 *eax = 0;
1891 *ebx = 0;
1892 *ecx = 0;
1893 *edx = 0;
1894 }
c6dc6f63 1895 break;
b3baa152
BW		 1896 case 0xC0000000:
1897 *eax = env->cpuid_xlevel2;
1898 *ebx = 0;
1899 *ecx = 0;
1900 *edx = 0;
1901 break;
1902 case 0xC0000001:
1903 /* Support for VIA CPU's CPUID instruction */
1904 *eax = env->cpuid_version;
1905 *ebx = 0;
1906 *ecx = 0;
1907 *edx = env->cpuid_ext4_features;
1908 break;
1909 case 0xC0000002:
1910 case 0xC0000003:
1911 case 0xC0000004:
1912 /* Reserved for the future, and now filled with zero */
1913 *eax = 0;
1914 *ebx = 0;
1915 *ecx = 0;
1916 *edx = 0;
1917 break;
c6dc6f63
AP		 1918 default:
1919 /* reserved values: zero */
1920 *eax = 0;
1921 *ebx = 0;
1922 *ecx = 0;
1923 *edx = 0;
1924 break;
1925 }
1926}
5fd2087a
AF		 1927
1928/* CPUClass::reset() */
1929static void x86_cpu_reset(CPUState *s)
1930{
1931 X86CPU *cpu = X86_CPU(s);
1932 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1933 CPUX86State *env = &cpu->env;
c1958aea
AF		 1934 int i;
1935
1936 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 1937 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
6fd2a026 1938 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
c1958aea 1939 }
5fd2087a
AF		 1940
1941 xcc->parent_reset(s);
1942
c1958aea
AF		 1943
1944 memset(env, 0, offsetof(CPUX86State, breakpoints));
1945
1946 tlb_flush(env, 1);
1947
1948 env->old_exception = -1;
1949
1950 /* init to reset state */
1951
1952#ifdef CONFIG_SOFTMMU
1953 env->hflags |= HF_SOFTMMU_MASK;
1954#endif
1955 env->hflags2 |= HF2_GIF_MASK;
1956
1957 cpu_x86_update_cr0(env, 0x60000010);
1958 env->a20_mask = ~0x0;
1959 env->smbase = 0x30000;
1960
1961 env->idt.limit = 0xffff;
1962 env->gdt.limit = 0xffff;
1963 env->ldt.limit = 0xffff;
1964 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1965 env->tr.limit = 0xffff;
1966 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1967
1968 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1969 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1970 DESC_R_MASK | DESC_A_MASK);
1971 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1972 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1973 DESC_A_MASK);
1974 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1975 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1976 DESC_A_MASK);
1977 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1978 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1979 DESC_A_MASK);
1980 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1981 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1982 DESC_A_MASK);
1983 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1984 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1985 DESC_A_MASK);
1986
1987 env->eip = 0xfff0;
1988 env->regs[R_EDX] = env->cpuid_version;
1989
1990 env->eflags = 0x2;
1991
1992 /* FPU init */
1993 for (i = 0; i < 8; i++) {
1994 env->fptags[i] = 1;
1995 }
1996 env->fpuc = 0x37f;
1997
1998 env->mxcsr = 0x1f80;
1999
2000 env->pat = 0x0007040600070406ULL;
2001 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2002
2003 memset(env->dr, 0, sizeof(env->dr));
2004 env->dr[6] = DR6_FIXED_1;
2005 env->dr[7] = DR7_FIXED_1;
2006 cpu_breakpoint_remove_all(env, BP_CPU);
2007 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 2008
2009#if !defined(CONFIG_USER_ONLY)
2010 /* We hard-wire the BSP to the first CPU. */
55e5c285 2011 if (s->cpu_index == 0) {
dd673288
IM		 2012 apic_designate_bsp(env->apic_state);
2013 }
2014
2015 env->halted = !cpu_is_bsp(cpu);
2016#endif
5fd2087a
AF		 2017}
2018
dd673288
IM		 2019#ifndef CONFIG_USER_ONLY
2020bool cpu_is_bsp(X86CPU *cpu)
2021{
2022 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2023}
65dee380
IM		 2024
2025/* TODO: remove me, when reset over QOM tree is implemented */
2026static void x86_cpu_machine_reset_cb(void *opaque)
2027{
2028 X86CPU *cpu = opaque;
2029 cpu_reset(CPU(cpu));
2030}
dd673288
IM		 2031#endif
2032
de024815
AF		 2033static void mce_init(X86CPU *cpu)
2034{
2035 CPUX86State *cenv = &cpu->env;
2036 unsigned int bank;
2037
2038 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2039 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2040 (CPUID_MCE | CPUID_MCA)) {
2041 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2042 cenv->mcg_ctl = ~(uint64_t)0;
2043 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2044 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2045 }
2046 }
2047}
2048
bdeec802
IM		 2049#define MSI_ADDR_BASE 0xfee00000
2050
2051#ifndef CONFIG_USER_ONLY
2052static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2053{
2054 static int apic_mapped;
2055 CPUX86State *env = &cpu->env;
449994eb 2056 APICCommonState *apic;
bdeec802
IM		 2057 const char *apic_type = "apic";
2058
2059 if (kvm_irqchip_in_kernel()) {
2060 apic_type = "kvm-apic";
2061 } else if (xen_enabled()) {
2062 apic_type = "xen-apic";
2063 }
2064
2065 env->apic_state = qdev_try_create(NULL, apic_type);
2066 if (env->apic_state == NULL) {
2067 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2068 return;
2069 }
2070
2071 object_property_add_child(OBJECT(cpu), "apic",
2072 OBJECT(env->apic_state), NULL);
2073 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2074 /* TODO: convert to link<> */
449994eb 2075 apic = APIC_COMMON(env->apic_state);
60671e58 2076 apic->cpu = cpu;
bdeec802
IM		 2077
2078 if (qdev_init(env->apic_state)) {
2079 error_setg(errp, "APIC device '%s' could not be initialized",
2080 object_get_typename(OBJECT(env->apic_state)));
2081 return;
2082 }
2083
2084 /* XXX: mapping more APICs at the same memory location */
2085 if (apic_mapped == 0) {
2086 /* NOTE: the APIC is directly connected to the CPU - it is not
2087 on the global memory bus. */
2088 /* XXX: what if the base changes? */
2089 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2090 apic_mapped = 1;
2091 }
2092}
2093#endif
2094
7a059953
AF		 2095void x86_cpu_realize(Object *obj, Error **errp)
2096{
2097 X86CPU *cpu = X86_CPU(obj);
b34d12d1
IM		 2098 CPUX86State *env = &cpu->env;
2099
2100 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2101 env->cpuid_level = 7;
2102 }
7a059953 2103
9b15cd9e
IM		 2104 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2105 * CPUID[1].EDX.
2106 */
2107 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2108 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2109 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2110 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2111 env->cpuid_ext2_features |= (env->cpuid_features
2112 & CPUID_EXT2_AMD_ALIASES);
2113 }
2114
4586f157
IM		 2115 if (!kvm_enabled()) {
2116 env->cpuid_features &= TCG_FEATURES;
2117 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2118 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2119#ifdef TARGET_X86_64
2120 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2121#endif
2122 );
2123 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2124 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2125 } else {
2126#ifdef CONFIG_KVM
2127 filter_features_for_kvm(cpu);
2128#endif
2129 }
2130
65dee380
IM		 2131#ifndef CONFIG_USER_ONLY
2132 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802
IM		 2133
2134 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2135 x86_cpu_apic_init(cpu, errp);
2136 if (error_is_set(errp)) {
2137 return;
2138 }
2139 }
65dee380
IM		 2140#endif
2141
7a059953
AF		 2142 mce_init(cpu);
2143 qemu_init_vcpu(&cpu->env);
65dee380 2144 cpu_reset(CPU(cpu));
7a059953
AF		 2145}
2146
de024815
AF		 2147static void x86_cpu_initfn(Object *obj)
2148{
55e5c285 2149 CPUState *cs = CPU(obj);
de024815
AF		 2150 X86CPU *cpu = X86_CPU(obj);
2151 CPUX86State *env = &cpu->env;
d65e9815 2152 static int inited;
de024815
AF		 2153
2154 cpu_exec_init(env);
71ad61d3
AF		 2155
2156 object_property_add(obj, "family", "int",
95b8519d 2157 x86_cpuid_version_get_family,
71ad61d3 2158 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2159 object_property_add(obj, "model", "int",
67e30c83 2160 x86_cpuid_version_get_model,
c5291a4f 2161 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2162 object_property_add(obj, "stepping", "int",
35112e41 2163 x86_cpuid_version_get_stepping,
036e2222 2164 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2165 object_property_add(obj, "level", "int",
2166 x86_cpuid_get_level,
2167 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2168 object_property_add(obj, "xlevel", "int",
2169 x86_cpuid_get_xlevel,
2170 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2171 object_property_add_str(obj, "vendor",
2172 x86_cpuid_get_vendor,
2173 x86_cpuid_set_vendor, NULL);
938d4c25 2174 object_property_add_str(obj, "model-id",
63e886eb 2175 x86_cpuid_get_model_id,
938d4c25 2176 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2177 object_property_add(obj, "tsc-frequency", "int",
2178 x86_cpuid_get_tsc_freq,
2179 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 2180
55e5c285 2181 env->cpuid_apic_id = cs->cpu_index;
d65e9815
IM		 2182
2183 /* init various static tables used in TCG mode */
2184 if (tcg_enabled() && !inited) {
2185 inited = 1;
2186 optimize_flags_init();
2187#ifndef CONFIG_USER_ONLY
2188 cpu_set_debug_excp_handler(breakpoint_handler);
2189#endif
2190 }
de024815
AF		 2191}
2192
5fd2087a
AF		 2193static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2194{
2195 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2196 CPUClass *cc = CPU_CLASS(oc);
2197
2198 xcc->parent_reset = cc->reset;
2199 cc->reset = x86_cpu_reset;
2200}
2201
2202static const TypeInfo x86_cpu_type_info = {
2203 .name = TYPE_X86_CPU,
2204 .parent = TYPE_CPU,
2205 .instance_size = sizeof(X86CPU),
de024815 2206 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2207 .abstract = false,
2208 .class_size = sizeof(X86CPUClass),
2209 .class_init = x86_cpu_common_class_init,
2210};
2211
2212static void x86_cpu_register_types(void)
2213{
2214 type_register_static(&x86_cpu_type_info);
2215}
2216
2217type_init(x86_cpu_register_types)
QEMU mirror