]>
Commit | Line | Data |
---|---|---|
48555339 FT |
1 | /** @file\r |
2 | This driver is used to manage SD/MMC PCI host controllers which are compliance\r | |
48190274 HW |
3 | with SD Host Controller Simplified Specification version 3.00 plus the 64-bit\r |
4 | System Addressing support in SD Host Controller Simplified Specification version\r | |
5 | 4.20.\r | |
48555339 FT |
6 | \r |
7 | It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.\r | |
8 | \r | |
690d60c0 | 9 | Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.\r |
4e2ac806 | 10 | Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>\r |
9d510e61 | 11 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
48555339 FT |
12 | \r |
13 | **/\r | |
14 | \r | |
15 | #include "SdMmcPciHcDxe.h"\r | |
16 | \r | |
17 | /**\r | |
18 | Dump the content of SD/MMC host controller's Capability Register.\r | |
19 | \r | |
20 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
21 | @param[in] Capability The buffer to store the capability data.\r | |
22 | \r | |
23 | **/\r | |
24 | VOID\r | |
25 | DumpCapabilityReg (\r | |
26 | IN UINT8 Slot,\r | |
27 | IN SD_MMC_HC_SLOT_CAP *Capability\r | |
28 | )\r | |
29 | {\r | |
30 | //\r | |
31 | // Dump Capability Data\r | |
32 | //\r | |
e27ccaba FT |
33 | DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));\r |
34 | DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));\r | |
35 | DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));\r | |
36 | DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));\r | |
37 | DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));\r | |
38 | DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));\r | |
39 | DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));\r | |
40 | DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));\r | |
41 | DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));\r | |
42 | DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));\r | |
43 | DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));\r | |
44 | DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));\r | |
b5547b9c AS |
45 | DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));\r |
46 | DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));\r | |
e27ccaba FT |
47 | DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));\r |
48 | DEBUG ((DEBUG_INFO, " SlotType "));\r | |
48555339 | 49 | if (Capability->SlotType == 0x00) {\r |
e27ccaba | 50 | DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));\r |
48555339 | 51 | } else if (Capability->SlotType == 0x01) {\r |
e27ccaba | 52 | DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));\r |
48555339 | 53 | } else if (Capability->SlotType == 0x02) {\r |
e27ccaba | 54 | DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));\r |
48555339 | 55 | } else {\r |
e27ccaba | 56 | DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));\r |
48555339 | 57 | }\r |
e27ccaba FT |
58 | DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));\r |
59 | DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));\r | |
60 | DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));\r | |
61 | DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));\r | |
62 | DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));\r | |
63 | DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));\r | |
64 | DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));\r | |
48555339 | 65 | if (Capability->TimerCount == 0) {\r |
e27ccaba | 66 | DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));\r |
48555339 | 67 | } else {\r |
e27ccaba | 68 | DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));\r |
48555339 | 69 | }\r |
e27ccaba FT |
70 | DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));\r |
71 | DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));\r | |
72 | DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));\r | |
73 | DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));\r | |
48555339 FT |
74 | return;\r |
75 | }\r | |
76 | \r | |
77 | /**\r | |
78 | Read SlotInfo register from SD/MMC host controller pci config space.\r | |
79 | \r | |
80 | @param[in] PciIo The PCI IO protocol instance.\r | |
81 | @param[out] FirstBar The buffer to store the first BAR value.\r | |
82 | @param[out] SlotNum The buffer to store the supported slot number.\r | |
83 | \r | |
84 | @retval EFI_SUCCESS The operation succeeds.\r | |
85 | @retval Others The operation fails.\r | |
86 | \r | |
87 | **/\r | |
88 | EFI_STATUS\r | |
89 | EFIAPI\r | |
90 | SdMmcHcGetSlotInfo (\r | |
91 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
92 | OUT UINT8 *FirstBar,\r | |
93 | OUT UINT8 *SlotNum\r | |
94 | )\r | |
95 | {\r | |
96 | EFI_STATUS Status;\r | |
97 | SD_MMC_HC_SLOT_INFO SlotInfo;\r | |
98 | \r | |
99 | Status = PciIo->Pci.Read (\r | |
100 | PciIo,\r | |
101 | EfiPciIoWidthUint8,\r | |
102 | SD_MMC_HC_SLOT_OFFSET,\r | |
103 | sizeof (SlotInfo),\r | |
104 | &SlotInfo\r | |
105 | );\r | |
106 | if (EFI_ERROR (Status)) {\r | |
107 | return Status;\r | |
108 | }\r | |
109 | \r | |
110 | *FirstBar = SlotInfo.FirstBar;\r | |
111 | *SlotNum = SlotInfo.SlotNum + 1;\r | |
112 | ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);\r | |
113 | return EFI_SUCCESS;\r | |
114 | }\r | |
115 | \r | |
116 | /**\r | |
117 | Read/Write specified SD/MMC host controller mmio register.\r | |
118 | \r | |
119 | @param[in] PciIo The PCI IO protocol instance.\r | |
120 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
121 | header to use as the base address for the memory\r | |
122 | operation to perform.\r | |
123 | @param[in] Offset The offset within the selected BAR to start the\r | |
124 | memory operation.\r | |
125 | @param[in] Read A boolean to indicate it's read or write operation.\r | |
126 | @param[in] Count The width of the mmio register in bytes.\r | |
127 | Must be 1, 2 , 4 or 8 bytes.\r | |
128 | @param[in, out] Data For read operations, the destination buffer to store\r | |
129 | the results. For write operations, the source buffer\r | |
130 | to write data from. The caller is responsible for\r | |
131 | having ownership of the data buffer and ensuring its\r | |
132 | size not less than Count bytes.\r | |
133 | \r | |
134 | @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r | |
135 | @retval EFI_SUCCESS The read/write operation succeeds.\r | |
136 | @retval Others The read/write operation fails.\r | |
137 | \r | |
138 | **/\r | |
139 | EFI_STATUS\r | |
140 | EFIAPI\r | |
141 | SdMmcHcRwMmio (\r | |
142 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
143 | IN UINT8 BarIndex,\r | |
144 | IN UINT32 Offset,\r | |
145 | IN BOOLEAN Read,\r | |
146 | IN UINT8 Count,\r | |
147 | IN OUT VOID *Data\r | |
148 | )\r | |
149 | {\r | |
150 | EFI_STATUS Status;\r | |
f168816c | 151 | EFI_PCI_IO_PROTOCOL_WIDTH Width;\r |
48555339 FT |
152 | \r |
153 | if ((PciIo == NULL) || (Data == NULL)) {\r | |
154 | return EFI_INVALID_PARAMETER;\r | |
155 | }\r | |
156 | \r | |
f168816c EH |
157 | switch (Count) {\r |
158 | case 1:\r | |
159 | Width = EfiPciIoWidthUint8;\r | |
160 | break;\r | |
161 | case 2:\r | |
162 | Width = EfiPciIoWidthUint16;\r | |
163 | Count = 1;\r | |
164 | break;\r | |
165 | case 4:\r | |
166 | Width = EfiPciIoWidthUint32;\r | |
167 | Count = 1;\r | |
168 | break;\r | |
169 | case 8:\r | |
170 | Width = EfiPciIoWidthUint32;\r | |
171 | Count = 2;\r | |
172 | break;\r | |
173 | default:\r | |
174 | return EFI_INVALID_PARAMETER;\r | |
48555339 FT |
175 | }\r |
176 | \r | |
177 | if (Read) {\r | |
178 | Status = PciIo->Mem.Read (\r | |
179 | PciIo,\r | |
f168816c | 180 | Width,\r |
48555339 FT |
181 | BarIndex,\r |
182 | (UINT64) Offset,\r | |
183 | Count,\r | |
184 | Data\r | |
185 | );\r | |
186 | } else {\r | |
187 | Status = PciIo->Mem.Write (\r | |
188 | PciIo,\r | |
f168816c | 189 | Width,\r |
48555339 FT |
190 | BarIndex,\r |
191 | (UINT64) Offset,\r | |
192 | Count,\r | |
193 | Data\r | |
194 | );\r | |
195 | }\r | |
196 | \r | |
197 | return Status;\r | |
198 | }\r | |
199 | \r | |
200 | /**\r | |
201 | Do OR operation with the value of the specified SD/MMC host controller mmio register.\r | |
202 | \r | |
203 | @param[in] PciIo The PCI IO protocol instance.\r | |
204 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
205 | header to use as the base address for the memory\r | |
206 | operation to perform.\r | |
207 | @param[in] Offset The offset within the selected BAR to start the\r | |
208 | memory operation.\r | |
209 | @param[in] Count The width of the mmio register in bytes.\r | |
210 | Must be 1, 2 , 4 or 8 bytes.\r | |
211 | @param[in] OrData The pointer to the data used to do OR operation.\r | |
212 | The caller is responsible for having ownership of\r | |
213 | the data buffer and ensuring its size not less than\r | |
214 | Count bytes.\r | |
215 | \r | |
216 | @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r | |
217 | @retval EFI_SUCCESS The OR operation succeeds.\r | |
218 | @retval Others The OR operation fails.\r | |
219 | \r | |
220 | **/\r | |
221 | EFI_STATUS\r | |
222 | EFIAPI\r | |
223 | SdMmcHcOrMmio (\r | |
224 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
225 | IN UINT8 BarIndex,\r | |
226 | IN UINT32 Offset,\r | |
227 | IN UINT8 Count,\r | |
228 | IN VOID *OrData\r | |
229 | )\r | |
230 | {\r | |
231 | EFI_STATUS Status;\r | |
232 | UINT64 Data;\r | |
233 | UINT64 Or;\r | |
234 | \r | |
235 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r | |
236 | if (EFI_ERROR (Status)) {\r | |
237 | return Status;\r | |
238 | }\r | |
239 | \r | |
240 | if (Count == 1) {\r | |
241 | Or = *(UINT8*) OrData;\r | |
242 | } else if (Count == 2) {\r | |
243 | Or = *(UINT16*) OrData;\r | |
244 | } else if (Count == 4) {\r | |
245 | Or = *(UINT32*) OrData;\r | |
246 | } else if (Count == 8) {\r | |
247 | Or = *(UINT64*) OrData;\r | |
248 | } else {\r | |
249 | return EFI_INVALID_PARAMETER;\r | |
250 | }\r | |
251 | \r | |
252 | Data |= Or;\r | |
253 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r | |
254 | \r | |
255 | return Status;\r | |
256 | }\r | |
257 | \r | |
258 | /**\r | |
259 | Do AND operation with the value of the specified SD/MMC host controller mmio register.\r | |
260 | \r | |
261 | @param[in] PciIo The PCI IO protocol instance.\r | |
262 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
263 | header to use as the base address for the memory\r | |
264 | operation to perform.\r | |
265 | @param[in] Offset The offset within the selected BAR to start the\r | |
266 | memory operation.\r | |
267 | @param[in] Count The width of the mmio register in bytes.\r | |
268 | Must be 1, 2 , 4 or 8 bytes.\r | |
269 | @param[in] AndData The pointer to the data used to do AND operation.\r | |
270 | The caller is responsible for having ownership of\r | |
271 | the data buffer and ensuring its size not less than\r | |
272 | Count bytes.\r | |
273 | \r | |
274 | @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r | |
275 | @retval EFI_SUCCESS The AND operation succeeds.\r | |
276 | @retval Others The AND operation fails.\r | |
277 | \r | |
278 | **/\r | |
279 | EFI_STATUS\r | |
280 | EFIAPI\r | |
281 | SdMmcHcAndMmio (\r | |
282 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
283 | IN UINT8 BarIndex,\r | |
284 | IN UINT32 Offset,\r | |
285 | IN UINT8 Count,\r | |
286 | IN VOID *AndData\r | |
287 | )\r | |
288 | {\r | |
289 | EFI_STATUS Status;\r | |
290 | UINT64 Data;\r | |
291 | UINT64 And;\r | |
292 | \r | |
293 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);\r | |
294 | if (EFI_ERROR (Status)) {\r | |
295 | return Status;\r | |
296 | }\r | |
297 | \r | |
298 | if (Count == 1) {\r | |
299 | And = *(UINT8*) AndData;\r | |
300 | } else if (Count == 2) {\r | |
301 | And = *(UINT16*) AndData;\r | |
302 | } else if (Count == 4) {\r | |
303 | And = *(UINT32*) AndData;\r | |
304 | } else if (Count == 8) {\r | |
305 | And = *(UINT64*) AndData;\r | |
306 | } else {\r | |
307 | return EFI_INVALID_PARAMETER;\r | |
308 | }\r | |
309 | \r | |
310 | Data &= And;\r | |
311 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);\r | |
312 | \r | |
313 | return Status;\r | |
314 | }\r | |
315 | \r | |
316 | /**\r | |
317 | Wait for the value of the specified MMIO register set to the test value.\r | |
318 | \r | |
319 | @param[in] PciIo The PCI IO protocol instance.\r | |
320 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
321 | header to use as the base address for the memory\r | |
322 | operation to perform.\r | |
323 | @param[in] Offset The offset within the selected BAR to start the\r | |
324 | memory operation.\r | |
325 | @param[in] Count The width of the mmio register in bytes.\r | |
326 | Must be 1, 2, 4 or 8 bytes.\r | |
327 | @param[in] MaskValue The mask value of memory.\r | |
328 | @param[in] TestValue The test value of memory.\r | |
329 | \r | |
330 | @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.\r | |
331 | @retval EFI_SUCCESS The MMIO register has expected value.\r | |
332 | @retval Others The MMIO operation fails.\r | |
333 | \r | |
334 | **/\r | |
335 | EFI_STATUS\r | |
336 | EFIAPI\r | |
337 | SdMmcHcCheckMmioSet (\r | |
338 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
339 | IN UINT8 BarIndex,\r | |
340 | IN UINT32 Offset,\r | |
341 | IN UINT8 Count,\r | |
342 | IN UINT64 MaskValue,\r | |
343 | IN UINT64 TestValue\r | |
344 | )\r | |
345 | {\r | |
346 | EFI_STATUS Status;\r | |
347 | UINT64 Value;\r | |
348 | \r | |
349 | //\r | |
350 | // Access PCI MMIO space to see if the value is the tested one.\r | |
351 | //\r | |
352 | Value = 0;\r | |
353 | Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);\r | |
354 | if (EFI_ERROR (Status)) {\r | |
355 | return Status;\r | |
356 | }\r | |
357 | \r | |
358 | Value &= MaskValue;\r | |
359 | \r | |
360 | if (Value == TestValue) {\r | |
361 | return EFI_SUCCESS;\r | |
362 | }\r | |
363 | \r | |
364 | return EFI_NOT_READY;\r | |
365 | }\r | |
366 | \r | |
367 | /**\r | |
368 | Wait for the value of the specified MMIO register set to the test value.\r | |
369 | \r | |
370 | @param[in] PciIo The PCI IO protocol instance.\r | |
371 | @param[in] BarIndex The BAR index of the standard PCI Configuration\r | |
372 | header to use as the base address for the memory\r | |
373 | operation to perform.\r | |
374 | @param[in] Offset The offset within the selected BAR to start the\r | |
375 | memory operation.\r | |
376 | @param[in] Count The width of the mmio register in bytes.\r | |
377 | Must be 1, 2, 4 or 8 bytes.\r | |
378 | @param[in] MaskValue The mask value of memory.\r | |
379 | @param[in] TestValue The test value of memory.\r | |
380 | @param[in] Timeout The time out value for wait memory set, uses 1\r | |
381 | microsecond as a unit.\r | |
382 | \r | |
383 | @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout\r | |
384 | range.\r | |
385 | @retval EFI_SUCCESS The MMIO register has expected value.\r | |
386 | @retval Others The MMIO operation fails.\r | |
387 | \r | |
388 | **/\r | |
389 | EFI_STATUS\r | |
390 | EFIAPI\r | |
391 | SdMmcHcWaitMmioSet (\r | |
392 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
393 | IN UINT8 BarIndex,\r | |
394 | IN UINT32 Offset,\r | |
395 | IN UINT8 Count,\r | |
396 | IN UINT64 MaskValue,\r | |
397 | IN UINT64 TestValue,\r | |
398 | IN UINT64 Timeout\r | |
399 | )\r | |
400 | {\r | |
401 | EFI_STATUS Status;\r | |
402 | BOOLEAN InfiniteWait;\r | |
403 | \r | |
404 | if (Timeout == 0) {\r | |
405 | InfiniteWait = TRUE;\r | |
406 | } else {\r | |
407 | InfiniteWait = FALSE;\r | |
408 | }\r | |
409 | \r | |
410 | while (InfiniteWait || (Timeout > 0)) {\r | |
411 | Status = SdMmcHcCheckMmioSet (\r | |
412 | PciIo,\r | |
413 | BarIndex,\r | |
414 | Offset,\r | |
415 | Count,\r | |
416 | MaskValue,\r | |
417 | TestValue\r | |
418 | );\r | |
419 | if (Status != EFI_NOT_READY) {\r | |
420 | return Status;\r | |
421 | }\r | |
422 | \r | |
423 | //\r | |
424 | // Stall for 1 microsecond.\r | |
425 | //\r | |
426 | gBS->Stall (1);\r | |
427 | \r | |
428 | Timeout--;\r | |
429 | }\r | |
430 | \r | |
431 | return EFI_TIMEOUT;\r | |
432 | }\r | |
433 | \r | |
b5547b9c AS |
434 | /**\r |
435 | Get the controller version information from the specified slot.\r | |
436 | \r | |
437 | @param[in] PciIo The PCI IO protocol instance.\r | |
438 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
439 | @param[out] Version The buffer to store the version information.\r | |
440 | \r | |
441 | @retval EFI_SUCCESS The operation executes successfully.\r | |
442 | @retval Others The operation fails.\r | |
443 | \r | |
444 | **/\r | |
445 | EFI_STATUS\r | |
446 | SdMmcHcGetControllerVersion (\r | |
447 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
448 | IN UINT8 Slot,\r | |
449 | OUT UINT16 *Version\r | |
450 | )\r | |
451 | {\r | |
452 | EFI_STATUS Status;\r | |
453 | \r | |
454 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);\r | |
455 | if (EFI_ERROR (Status)) {\r | |
456 | return Status;\r | |
457 | }\r | |
458 | \r | |
459 | *Version &= 0xFF;\r | |
460 | \r | |
461 | return EFI_SUCCESS;\r | |
462 | }\r | |
463 | \r | |
48555339 FT |
464 | /**\r |
465 | Software reset the specified SD/MMC host controller and enable all interrupts.\r | |
466 | \r | |
b23fc39c | 467 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r |
48555339 FT |
468 | @param[in] Slot The slot number of the SD card to send the command to.\r |
469 | \r | |
470 | @retval EFI_SUCCESS The software reset executes successfully.\r | |
471 | @retval Others The software reset fails.\r | |
472 | \r | |
473 | **/\r | |
474 | EFI_STATUS\r | |
475 | SdMmcHcReset (\r | |
b23fc39c | 476 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
48555339 FT |
477 | IN UINT8 Slot\r |
478 | )\r | |
479 | {\r | |
480 | EFI_STATUS Status;\r | |
481 | UINT8 SwReset;\r | |
b23fc39c | 482 | EFI_PCI_IO_PROTOCOL *PciIo;\r |
48555339 | 483 | \r |
b23fc39c AB |
484 | //\r |
485 | // Notify the SD/MMC override protocol that we are about to reset\r | |
486 | // the SD/MMC host controller.\r | |
487 | //\r | |
488 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
489 | Status = mOverride->NotifyPhase (\r | |
490 | Private->ControllerHandle,\r | |
491 | Slot,\r | |
49c99534 MW |
492 | EdkiiSdMmcResetPre,\r |
493 | NULL);\r | |
b23fc39c AB |
494 | if (EFI_ERROR (Status)) {\r |
495 | DEBUG ((DEBUG_WARN,\r | |
496 | "%a: SD/MMC pre reset notifier callback failed - %r\n",\r | |
497 | __FUNCTION__, Status));\r | |
498 | return Status;\r | |
499 | }\r | |
500 | }\r | |
501 | \r | |
502 | PciIo = Private->PciIo;\r | |
064d301f TM |
503 | SwReset = BIT0;\r |
504 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);\r | |
48555339 FT |
505 | \r |
506 | if (EFI_ERROR (Status)) {\r | |
064d301f | 507 | DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));\r |
48555339 FT |
508 | return Status;\r |
509 | }\r | |
510 | \r | |
511 | Status = SdMmcHcWaitMmioSet (\r | |
512 | PciIo,\r | |
513 | Slot,\r | |
514 | SD_MMC_HC_SW_RST,\r | |
515 | sizeof (SwReset),\r | |
064d301f | 516 | BIT0,\r |
48555339 FT |
517 | 0x00,\r |
518 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
519 | );\r | |
520 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 521 | DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));\r |
48555339 FT |
522 | return Status;\r |
523 | }\r | |
b23fc39c | 524 | \r |
48555339 FT |
525 | //\r |
526 | // Enable all interrupt after reset all.\r | |
527 | //\r | |
528 | Status = SdMmcHcEnableInterrupt (PciIo, Slot);\r | |
b23fc39c AB |
529 | if (EFI_ERROR (Status)) {\r |
530 | DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",\r | |
531 | Status));\r | |
532 | return Status;\r | |
533 | }\r | |
534 | \r | |
535 | //\r | |
536 | // Notify the SD/MMC override protocol that we have just reset\r | |
537 | // the SD/MMC host controller.\r | |
538 | //\r | |
539 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
540 | Status = mOverride->NotifyPhase (\r | |
541 | Private->ControllerHandle,\r | |
542 | Slot,\r | |
49c99534 MW |
543 | EdkiiSdMmcResetPost,\r |
544 | NULL);\r | |
b23fc39c AB |
545 | if (EFI_ERROR (Status)) {\r |
546 | DEBUG ((DEBUG_WARN,\r | |
547 | "%a: SD/MMC post reset notifier callback failed - %r\n",\r | |
548 | __FUNCTION__, Status));\r | |
549 | }\r | |
550 | }\r | |
48555339 FT |
551 | \r |
552 | return Status;\r | |
553 | }\r | |
554 | \r | |
555 | /**\r | |
556 | Set all interrupt status bits in Normal and Error Interrupt Status Enable\r | |
557 | register.\r | |
558 | \r | |
559 | @param[in] PciIo The PCI IO protocol instance.\r | |
560 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
561 | \r | |
562 | @retval EFI_SUCCESS The operation executes successfully.\r | |
563 | @retval Others The operation fails.\r | |
564 | \r | |
565 | **/\r | |
566 | EFI_STATUS\r | |
567 | SdMmcHcEnableInterrupt (\r | |
568 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
569 | IN UINT8 Slot\r | |
570 | )\r | |
571 | {\r | |
572 | EFI_STATUS Status;\r | |
573 | UINT16 IntStatus;\r | |
574 | \r | |
575 | //\r | |
576 | // Enable all bits in Error Interrupt Status Enable Register\r | |
577 | //\r | |
578 | IntStatus = 0xFFFF;\r | |
579 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r | |
580 | if (EFI_ERROR (Status)) {\r | |
581 | return Status;\r | |
582 | }\r | |
583 | //\r | |
584 | // Enable all bits in Normal Interrupt Status Enable Register\r | |
585 | //\r | |
586 | IntStatus = 0xFFFF;\r | |
587 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r | |
588 | \r | |
589 | return Status;\r | |
590 | }\r | |
591 | \r | |
592 | /**\r | |
593 | Get the capability data from the specified slot.\r | |
594 | \r | |
595 | @param[in] PciIo The PCI IO protocol instance.\r | |
596 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
597 | @param[out] Capability The buffer to store the capability data.\r | |
598 | \r | |
599 | @retval EFI_SUCCESS The operation executes successfully.\r | |
600 | @retval Others The operation fails.\r | |
601 | \r | |
602 | **/\r | |
603 | EFI_STATUS\r | |
604 | SdMmcHcGetCapability (\r | |
605 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
606 | IN UINT8 Slot,\r | |
607 | OUT SD_MMC_HC_SLOT_CAP *Capability\r | |
608 | )\r | |
609 | {\r | |
610 | EFI_STATUS Status;\r | |
611 | UINT64 Cap;\r | |
612 | \r | |
613 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);\r | |
614 | if (EFI_ERROR (Status)) {\r | |
615 | return Status;\r | |
616 | }\r | |
617 | \r | |
618 | CopyMem (Capability, &Cap, sizeof (Cap));\r | |
619 | \r | |
620 | return EFI_SUCCESS;\r | |
621 | }\r | |
622 | \r | |
623 | /**\r | |
624 | Get the maximum current capability data from the specified slot.\r | |
625 | \r | |
626 | @param[in] PciIo The PCI IO protocol instance.\r | |
627 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
628 | @param[out] MaxCurrent The buffer to store the maximum current capability data.\r | |
629 | \r | |
630 | @retval EFI_SUCCESS The operation executes successfully.\r | |
631 | @retval Others The operation fails.\r | |
632 | \r | |
633 | **/\r | |
634 | EFI_STATUS\r | |
635 | SdMmcHcGetMaxCurrent (\r | |
636 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
637 | IN UINT8 Slot,\r | |
638 | OUT UINT64 *MaxCurrent\r | |
639 | )\r | |
640 | {\r | |
641 | EFI_STATUS Status;\r | |
642 | \r | |
643 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);\r | |
644 | \r | |
645 | return Status;\r | |
646 | }\r | |
647 | \r | |
648 | /**\r | |
649 | Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r | |
650 | slot.\r | |
651 | \r | |
652 | Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r | |
653 | \r | |
654 | @param[in] PciIo The PCI IO protocol instance.\r | |
655 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
656 | @param[out] MediaPresent The pointer to the media present boolean value.\r | |
657 | \r | |
658 | @retval EFI_SUCCESS There is no media change happened.\r | |
659 | @retval EFI_MEDIA_CHANGED There is media change happened.\r | |
660 | @retval Others The detection fails.\r | |
661 | \r | |
662 | **/\r | |
663 | EFI_STATUS\r | |
664 | SdMmcHcCardDetect (\r | |
665 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
666 | IN UINT8 Slot,\r | |
667 | OUT BOOLEAN *MediaPresent\r | |
668 | )\r | |
669 | {\r | |
670 | EFI_STATUS Status;\r | |
671 | UINT16 Data;\r | |
672 | UINT32 PresentState;\r | |
673 | \r | |
2e9107b8 FT |
674 | //\r |
675 | // Check Present State Register to see if there is a card presented.\r | |
676 | //\r | |
677 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r | |
678 | if (EFI_ERROR (Status)) {\r | |
679 | return Status;\r | |
680 | }\r | |
681 | \r | |
682 | if ((PresentState & BIT16) != 0) {\r | |
683 | *MediaPresent = TRUE;\r | |
684 | } else {\r | |
685 | *MediaPresent = FALSE;\r | |
686 | }\r | |
687 | \r | |
48555339 FT |
688 | //\r |
689 | // Check Normal Interrupt Status Register\r | |
690 | //\r | |
691 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);\r | |
692 | if (EFI_ERROR (Status)) {\r | |
693 | return Status;\r | |
694 | }\r | |
695 | \r | |
696 | if ((Data & (BIT6 | BIT7)) != 0) {\r | |
697 | //\r | |
698 | // Clear BIT6 and BIT7 by writing 1 to these two bits if set.\r | |
699 | //\r | |
700 | Data &= BIT6 | BIT7;\r | |
701 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);\r | |
702 | if (EFI_ERROR (Status)) {\r | |
703 | return Status;\r | |
704 | }\r | |
705 | \r | |
48555339 FT |
706 | return EFI_MEDIA_CHANGED;\r |
707 | }\r | |
708 | \r | |
709 | return EFI_SUCCESS;\r | |
710 | }\r | |
711 | \r | |
712 | /**\r | |
713 | Stop SD/MMC card clock.\r | |
714 | \r | |
715 | Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r | |
716 | \r | |
717 | @param[in] PciIo The PCI IO protocol instance.\r | |
718 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
719 | \r | |
720 | @retval EFI_SUCCESS Succeed to stop SD/MMC clock.\r | |
721 | @retval Others Fail to stop SD/MMC clock.\r | |
722 | \r | |
723 | **/\r | |
724 | EFI_STATUS\r | |
725 | SdMmcHcStopClock (\r | |
726 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
727 | IN UINT8 Slot\r | |
728 | )\r | |
729 | {\r | |
730 | EFI_STATUS Status;\r | |
731 | UINT32 PresentState;\r | |
732 | UINT16 ClockCtrl;\r | |
733 | \r | |
734 | //\r | |
735 | // Ensure no SD transactions are occurring on the SD Bus by\r | |
736 | // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)\r | |
737 | // in the Present State register to be 0.\r | |
738 | //\r | |
739 | Status = SdMmcHcWaitMmioSet (\r | |
740 | PciIo,\r | |
741 | Slot,\r | |
742 | SD_MMC_HC_PRESENT_STATE,\r | |
743 | sizeof (PresentState),\r | |
744 | BIT0 | BIT1,\r | |
745 | 0,\r | |
746 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
747 | );\r | |
748 | if (EFI_ERROR (Status)) {\r | |
749 | return Status;\r | |
750 | }\r | |
751 | \r | |
752 | //\r | |
753 | // Set SD Clock Enable in the Clock Control register to 0\r | |
754 | //\r | |
755 | ClockCtrl = (UINT16)~BIT2;\r | |
756 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r | |
757 | \r | |
758 | return Status;\r | |
759 | }\r | |
760 | \r | |
f68cb23c AM |
761 | /**\r |
762 | Start the SD clock.\r | |
763 | \r | |
764 | @param[in] PciIo The PCI IO protocol instance.\r | |
765 | @param[in] Slot The slot number.\r | |
766 | \r | |
767 | @retval EFI_SUCCESS Succeeded to start the SD clock.\r | |
27f44ea1 | 768 | @retval Others Failed to start the SD clock.\r |
f68cb23c AM |
769 | **/\r |
770 | EFI_STATUS\r | |
771 | SdMmcHcStartSdClock (\r | |
772 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
773 | IN UINT8 Slot\r | |
774 | )\r | |
775 | {\r | |
776 | UINT16 ClockCtrl;\r | |
777 | \r | |
778 | //\r | |
779 | // Set SD Clock Enable in the Clock Control register to 1\r | |
780 | //\r | |
781 | ClockCtrl = BIT2;\r | |
782 | return SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r | |
783 | }\r | |
784 | \r | |
48555339 FT |
785 | /**\r |
786 | SD/MMC card clock supply.\r | |
787 | \r | |
788 | Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r | |
789 | \r | |
49accded AM |
790 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r |
791 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
792 | @param[in] BusTiming BusTiming at which the frequency change is done.\r | |
793 | @param[in] FirstTimeSetup Flag to indicate whether the clock is being setup for the first time.\r | |
794 | @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r | |
48555339 FT |
795 | \r |
796 | @retval EFI_SUCCESS The clock is supplied successfully.\r | |
797 | @retval Others The clock isn't supplied successfully.\r | |
798 | \r | |
799 | **/\r | |
800 | EFI_STATUS\r | |
801 | SdMmcHcClockSupply (\r | |
49accded AM |
802 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
803 | IN UINT8 Slot,\r | |
804 | IN SD_MMC_BUS_MODE BusTiming,\r | |
805 | IN BOOLEAN FirstTimeSetup,\r | |
806 | IN UINT64 ClockFreq\r | |
48555339 FT |
807 | )\r |
808 | {\r | |
809 | EFI_STATUS Status;\r | |
48555339 FT |
810 | UINT32 SettingFreq;\r |
811 | UINT32 Divisor;\r | |
812 | UINT32 Remainder;\r | |
48555339 | 813 | UINT16 ClockCtrl;\r |
49accded AM |
814 | UINT32 BaseClkFreq;\r |
815 | UINT16 ControllerVer;\r | |
816 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
48555339 | 817 | \r |
49accded AM |
818 | PciIo = Private->PciIo;\r |
819 | BaseClkFreq = Private->BaseClkFreq[Slot];\r | |
820 | ControllerVer = Private->ControllerVersion[Slot];\r | |
48555339 | 821 | \r |
49accded | 822 | if (BaseClkFreq == 0 || ClockFreq == 0) {\r |
48555339 FT |
823 | return EFI_INVALID_PARAMETER;\r |
824 | }\r | |
cb9cb9e2 FT |
825 | \r |
826 | if (ClockFreq > (BaseClkFreq * 1000)) {\r | |
827 | ClockFreq = BaseClkFreq * 1000;\r | |
828 | }\r | |
829 | \r | |
48555339 FT |
830 | //\r |
831 | // Calculate the divisor of base frequency.\r | |
832 | //\r | |
833 | Divisor = 0;\r | |
834 | SettingFreq = BaseClkFreq * 1000;\r | |
835 | while (ClockFreq < SettingFreq) {\r | |
836 | Divisor++;\r | |
837 | \r | |
838 | SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);\r | |
839 | Remainder = (BaseClkFreq * 1000) % (2 * Divisor);\r | |
840 | if ((ClockFreq == SettingFreq) && (Remainder == 0)) {\r | |
841 | break;\r | |
842 | }\r | |
843 | if ((ClockFreq == SettingFreq) && (Remainder != 0)) {\r | |
844 | SettingFreq ++;\r | |
845 | }\r | |
846 | }\r | |
847 | \r | |
e27ccaba | 848 | DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));\r |
48555339 | 849 | \r |
48555339 FT |
850 | //\r |
851 | // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r | |
852 | //\r | |
b5547b9c AS |
853 | if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&\r |
854 | (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {\r | |
48555339 FT |
855 | ASSERT (Divisor <= 0x3FF);\r |
856 | ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r | |
b5547b9c AS |
857 | } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||\r |
858 | (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {\r | |
48555339 FT |
859 | //\r |
860 | // Only the most significant bit can be used as divisor.\r | |
861 | //\r | |
862 | if (((Divisor - 1) & Divisor) != 0) {\r | |
863 | Divisor = 1 << (HighBitSet32 (Divisor) + 1);\r | |
864 | }\r | |
865 | ASSERT (Divisor <= 0x80);\r | |
866 | ClockCtrl = (Divisor & 0xFF) << 8;\r | |
867 | } else {\r | |
e27ccaba | 868 | DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));\r |
48555339 FT |
869 | return EFI_UNSUPPORTED;\r |
870 | }\r | |
871 | \r | |
872 | //\r | |
873 | // Stop bus clock at first\r | |
874 | //\r | |
875 | Status = SdMmcHcStopClock (PciIo, Slot);\r | |
876 | if (EFI_ERROR (Status)) {\r | |
877 | return Status;\r | |
878 | }\r | |
879 | \r | |
880 | //\r | |
881 | // Supply clock frequency with specified divisor\r | |
882 | //\r | |
883 | ClockCtrl |= BIT0;\r | |
884 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);\r | |
885 | if (EFI_ERROR (Status)) {\r | |
e27ccaba | 886 | DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));\r |
48555339 FT |
887 | return Status;\r |
888 | }\r | |
889 | \r | |
890 | //\r | |
891 | // Wait Internal Clock Stable in the Clock Control register to be 1\r | |
892 | //\r | |
893 | Status = SdMmcHcWaitMmioSet (\r | |
894 | PciIo,\r | |
895 | Slot,\r | |
896 | SD_MMC_HC_CLOCK_CTRL,\r | |
897 | sizeof (ClockCtrl),\r | |
898 | BIT1,\r | |
899 | BIT1,\r | |
900 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
901 | );\r | |
902 | if (EFI_ERROR (Status)) {\r | |
903 | return Status;\r | |
904 | }\r | |
905 | \r | |
f68cb23c AM |
906 | Status = SdMmcHcStartSdClock (PciIo, Slot);\r |
907 | if (EFI_ERROR (Status)) {\r | |
908 | return Status;\r | |
909 | }\r | |
48555339 | 910 | \r |
49accded AM |
911 | //\r |
912 | // We don't notify the platform on first time setup to avoid changing\r | |
913 | // legacy behavior. During first time setup we also don't know what type\r | |
914 | // of the card slot it is and which enum value of BusTiming applies.\r | |
915 | //\r | |
916 | if (!FirstTimeSetup && mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
917 | Status = mOverride->NotifyPhase (\r | |
918 | Private->ControllerHandle,\r | |
919 | Slot,\r | |
920 | EdkiiSdMmcSwitchClockFreqPost,\r | |
921 | &BusTiming\r | |
922 | );\r | |
923 | if (EFI_ERROR (Status)) {\r | |
924 | DEBUG ((\r | |
925 | DEBUG_ERROR,\r | |
926 | "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",\r | |
927 | __FUNCTION__,\r | |
928 | Status\r | |
929 | ));\r | |
930 | return Status;\r | |
931 | }\r | |
932 | }\r | |
933 | \r | |
48555339 FT |
934 | return Status;\r |
935 | }\r | |
936 | \r | |
937 | /**\r | |
938 | SD/MMC bus power control.\r | |
939 | \r | |
940 | Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r | |
941 | \r | |
942 | @param[in] PciIo The PCI IO protocol instance.\r | |
943 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
944 | @param[in] PowerCtrl The value setting to the power control register.\r | |
945 | \r | |
946 | @retval TRUE There is a SD/MMC card attached.\r | |
947 | @retval FALSE There is no a SD/MMC card attached.\r | |
948 | \r | |
949 | **/\r | |
950 | EFI_STATUS\r | |
951 | SdMmcHcPowerControl (\r | |
952 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
953 | IN UINT8 Slot,\r | |
954 | IN UINT8 PowerCtrl\r | |
955 | )\r | |
956 | {\r | |
957 | EFI_STATUS Status;\r | |
958 | \r | |
959 | //\r | |
960 | // Clr SD Bus Power\r | |
961 | //\r | |
962 | PowerCtrl &= (UINT8)~BIT0;\r | |
963 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r | |
964 | if (EFI_ERROR (Status)) {\r | |
965 | return Status;\r | |
966 | }\r | |
967 | \r | |
968 | //\r | |
969 | // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r | |
970 | //\r | |
971 | PowerCtrl |= BIT0;\r | |
972 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r | |
973 | \r | |
974 | return Status;\r | |
975 | }\r | |
976 | \r | |
977 | /**\r | |
978 | Set the SD/MMC bus width.\r | |
979 | \r | |
980 | Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r | |
981 | \r | |
982 | @param[in] PciIo The PCI IO protocol instance.\r | |
983 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
984 | @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r | |
985 | \r | |
986 | @retval EFI_SUCCESS The bus width is set successfully.\r | |
987 | @retval Others The bus width isn't set successfully.\r | |
988 | \r | |
989 | **/\r | |
990 | EFI_STATUS\r | |
991 | SdMmcHcSetBusWidth (\r | |
992 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
993 | IN UINT8 Slot,\r | |
994 | IN UINT16 BusWidth\r | |
995 | )\r | |
996 | {\r | |
997 | EFI_STATUS Status;\r | |
998 | UINT8 HostCtrl1;\r | |
999 | \r | |
1000 | if (BusWidth == 1) {\r | |
1001 | HostCtrl1 = (UINT8)~(BIT5 | BIT1);\r | |
1002 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
1003 | } else if (BusWidth == 4) {\r | |
1004 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r | |
1005 | if (EFI_ERROR (Status)) {\r | |
1006 | return Status;\r | |
1007 | }\r | |
1008 | HostCtrl1 |= BIT1;\r | |
1009 | HostCtrl1 &= (UINT8)~BIT5;\r | |
1010 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r | |
1011 | } else if (BusWidth == 8) {\r | |
1012 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r | |
1013 | if (EFI_ERROR (Status)) {\r | |
1014 | return Status;\r | |
1015 | }\r | |
1016 | HostCtrl1 &= (UINT8)~BIT1;\r | |
1017 | HostCtrl1 |= BIT5;\r | |
1018 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r | |
1019 | } else {\r | |
1020 | ASSERT (FALSE);\r | |
1021 | return EFI_INVALID_PARAMETER;\r | |
1022 | }\r | |
1023 | \r | |
1024 | return Status;\r | |
1025 | }\r | |
1026 | \r | |
b5547b9c AS |
1027 | /**\r |
1028 | Configure V4 controller enhancements at initialization.\r | |
1029 | \r | |
1030 | @param[in] PciIo The PCI IO protocol instance.\r | |
1031 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1032 | @param[in] Capability The capability of the slot.\r | |
1033 | @param[in] ControllerVer The version of host controller.\r | |
1034 | \r | |
1035 | @retval EFI_SUCCESS The clock is supplied successfully.\r | |
1036 | \r | |
1037 | **/\r | |
1038 | EFI_STATUS\r | |
1039 | SdMmcHcInitV4Enhancements (\r | |
1040 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1041 | IN UINT8 Slot,\r | |
1042 | IN SD_MMC_HC_SLOT_CAP Capability,\r | |
1043 | IN UINT16 ControllerVer\r | |
1044 | )\r | |
1045 | {\r | |
1046 | EFI_STATUS Status;\r | |
1047 | UINT16 HostCtrl2;\r | |
1048 | \r | |
1049 | //\r | |
1050 | // Check if controller version V4 or higher\r | |
1051 | //\r | |
1052 | if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {\r | |
1053 | HostCtrl2 = SD_MMC_HC_V4_EN;\r | |
1054 | //\r | |
690d60c0 | 1055 | // Check if controller version V4.0\r |
b5547b9c | 1056 | //\r |
690d60c0 AS |
1057 | if (ControllerVer == SD_MMC_HC_CTRL_VER_400) {\r |
1058 | //\r | |
1059 | // Check if 64bit support is available\r | |
1060 | //\r | |
1061 | if (Capability.SysBus64V3 != 0) {\r | |
1062 | HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;\r | |
1063 | DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));\r | |
1064 | }\r | |
b5547b9c AS |
1065 | }\r |
1066 | //\r | |
1067 | // Check if controller version V4.10 or higher\r | |
1068 | //\r | |
690d60c0 AS |
1069 | else if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {\r |
1070 | //\r | |
1071 | // Check if 64bit support is available\r | |
1072 | //\r | |
1073 | if (Capability.SysBus64V4 != 0) {\r | |
1074 | HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;\r | |
1075 | DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));\r | |
1076 | }\r | |
b5547b9c AS |
1077 | HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;\r |
1078 | DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));\r | |
1079 | }\r | |
1080 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1081 | if (EFI_ERROR (Status)) {\r | |
1082 | return Status;\r | |
1083 | }\r | |
1084 | }\r | |
1085 | \r | |
1086 | return EFI_SUCCESS;\r | |
1087 | }\r | |
1088 | \r | |
48555339 FT |
1089 | /**\r |
1090 | Supply SD/MMC card with maximum voltage at initialization.\r | |
1091 | \r | |
1092 | Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r | |
1093 | \r | |
1094 | @param[in] PciIo The PCI IO protocol instance.\r | |
1095 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1096 | @param[in] Capability The capability of the slot.\r | |
1097 | \r | |
1098 | @retval EFI_SUCCESS The voltage is supplied successfully.\r | |
1099 | @retval Others The voltage isn't supplied successfully.\r | |
1100 | \r | |
1101 | **/\r | |
1102 | EFI_STATUS\r | |
1103 | SdMmcHcInitPowerVoltage (\r | |
1104 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1105 | IN UINT8 Slot,\r | |
1106 | IN SD_MMC_HC_SLOT_CAP Capability\r | |
1107 | )\r | |
1108 | {\r | |
1109 | EFI_STATUS Status;\r | |
1110 | UINT8 MaxVoltage;\r | |
1111 | UINT8 HostCtrl2;\r | |
1112 | \r | |
1113 | //\r | |
1114 | // Calculate supported maximum voltage according to SD Bus Voltage Select\r | |
1115 | //\r | |
1116 | if (Capability.Voltage33 != 0) {\r | |
1117 | //\r | |
1118 | // Support 3.3V\r | |
1119 | //\r | |
1120 | MaxVoltage = 0x0E;\r | |
1121 | } else if (Capability.Voltage30 != 0) {\r | |
1122 | //\r | |
1123 | // Support 3.0V\r | |
1124 | //\r | |
1125 | MaxVoltage = 0x0C;\r | |
1126 | } else if (Capability.Voltage18 != 0) {\r | |
1127 | //\r | |
1128 | // Support 1.8V\r | |
1129 | //\r | |
1130 | MaxVoltage = 0x0A;\r | |
1131 | HostCtrl2 = BIT3;\r | |
1132 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1133 | gBS->Stall (5000);\r | |
1134 | if (EFI_ERROR (Status)) {\r | |
1135 | return Status;\r | |
1136 | }\r | |
1137 | } else {\r | |
1138 | ASSERT (FALSE);\r | |
1139 | return EFI_DEVICE_ERROR;\r | |
1140 | }\r | |
1141 | \r | |
1142 | //\r | |
1143 | // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r | |
1144 | //\r | |
1145 | Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);\r | |
1146 | \r | |
1147 | return Status;\r | |
1148 | }\r | |
1149 | \r | |
1150 | /**\r | |
1151 | Initialize the Timeout Control register with most conservative value at initialization.\r | |
1152 | \r | |
1153 | Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r | |
1154 | \r | |
1155 | @param[in] PciIo The PCI IO protocol instance.\r | |
1156 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1157 | \r | |
1158 | @retval EFI_SUCCESS The timeout control register is configured successfully.\r | |
1159 | @retval Others The timeout control register isn't configured successfully.\r | |
1160 | \r | |
1161 | **/\r | |
1162 | EFI_STATUS\r | |
1163 | SdMmcHcInitTimeoutCtrl (\r | |
1164 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1165 | IN UINT8 Slot\r | |
1166 | )\r | |
1167 | {\r | |
1168 | EFI_STATUS Status;\r | |
1169 | UINT8 Timeout;\r | |
1170 | \r | |
1171 | Timeout = 0x0E;\r | |
1172 | Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);\r | |
1173 | \r | |
1174 | return Status;\r | |
1175 | }\r | |
1176 | \r | |
1177 | /**\r | |
1178 | Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value\r | |
1179 | at initialization.\r | |
1180 | \r | |
b23fc39c | 1181 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r |
48555339 | 1182 | @param[in] Slot The slot number of the SD card to send the command to.\r |
48555339 FT |
1183 | \r |
1184 | @retval EFI_SUCCESS The host controller is initialized successfully.\r | |
1185 | @retval Others The host controller isn't initialized successfully.\r | |
1186 | \r | |
1187 | **/\r | |
1188 | EFI_STATUS\r | |
1189 | SdMmcHcInitHost (\r | |
b23fc39c AB |
1190 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r |
1191 | IN UINT8 Slot\r | |
48555339 FT |
1192 | )\r |
1193 | {\r | |
b23fc39c AB |
1194 | EFI_STATUS Status;\r |
1195 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1196 | SD_MMC_HC_SLOT_CAP Capability;\r | |
1197 | \r | |
1198 | //\r | |
1199 | // Notify the SD/MMC override protocol that we are about to initialize\r | |
1200 | // the SD/MMC host controller.\r | |
1201 | //\r | |
1202 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
1203 | Status = mOverride->NotifyPhase (\r | |
1204 | Private->ControllerHandle,\r | |
1205 | Slot,\r | |
49c99534 MW |
1206 | EdkiiSdMmcInitHostPre,\r |
1207 | NULL);\r | |
b23fc39c AB |
1208 | if (EFI_ERROR (Status)) {\r |
1209 | DEBUG ((DEBUG_WARN,\r | |
1210 | "%a: SD/MMC pre init notifier callback failed - %r\n",\r | |
1211 | __FUNCTION__, Status));\r | |
1212 | return Status;\r | |
1213 | }\r | |
1214 | }\r | |
1215 | \r | |
1216 | PciIo = Private->PciIo;\r | |
1217 | Capability = Private->Capability[Slot];\r | |
48555339 | 1218 | \r |
b5547b9c AS |
1219 | Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);\r |
1220 | if (EFI_ERROR (Status)) {\r | |
1221 | return Status;\r | |
1222 | }\r | |
1223 | \r | |
49accded AM |
1224 | //\r |
1225 | // Perform first time clock setup with 400 KHz frequency.\r | |
1226 | // We send the 0 as the BusTiming value because at this time\r | |
1227 | // we still do not know the slot type and which enum value will apply.\r | |
1228 | // Since it is a first time setup SdMmcHcClockSupply won't notify\r | |
1229 | // the platofrm driver anyway so it doesn't matter.\r | |
1230 | //\r | |
1231 | Status = SdMmcHcClockSupply (Private, Slot, 0, TRUE, 400);\r | |
48555339 FT |
1232 | if (EFI_ERROR (Status)) {\r |
1233 | return Status;\r | |
1234 | }\r | |
1235 | \r | |
1236 | Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);\r | |
1237 | if (EFI_ERROR (Status)) {\r | |
1238 | return Status;\r | |
1239 | }\r | |
1240 | \r | |
1241 | Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);\r | |
b23fc39c AB |
1242 | if (EFI_ERROR (Status)) {\r |
1243 | return Status;\r | |
1244 | }\r | |
1245 | \r | |
1246 | //\r | |
1247 | // Notify the SD/MMC override protocol that we are have just initialized\r | |
1248 | // the SD/MMC host controller.\r | |
1249 | //\r | |
1250 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
1251 | Status = mOverride->NotifyPhase (\r | |
1252 | Private->ControllerHandle,\r | |
1253 | Slot,\r | |
49c99534 MW |
1254 | EdkiiSdMmcInitHostPost,\r |
1255 | NULL);\r | |
b23fc39c AB |
1256 | if (EFI_ERROR (Status)) {\r |
1257 | DEBUG ((DEBUG_WARN,\r | |
1258 | "%a: SD/MMC post init notifier callback failed - %r\n",\r | |
1259 | __FUNCTION__, Status));\r | |
1260 | }\r | |
1261 | }\r | |
48555339 FT |
1262 | return Status;\r |
1263 | }\r | |
1264 | \r | |
a4708009 TM |
1265 | /**\r |
1266 | Set SD Host Controler control 2 registry according to selected speed.\r | |
1267 | \r | |
1268 | @param[in] ControllerHandle The handle of the controller.\r | |
1269 | @param[in] PciIo The PCI IO protocol instance.\r | |
1270 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1271 | @param[in] Timing The timing to select.\r | |
1272 | \r | |
1273 | @retval EFI_SUCCESS The timing is set successfully.\r | |
1274 | @retval Others The timing isn't set successfully.\r | |
1275 | **/\r | |
1276 | EFI_STATUS\r | |
1277 | SdMmcHcUhsSignaling (\r | |
1278 | IN EFI_HANDLE ControllerHandle,\r | |
1279 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1280 | IN UINT8 Slot,\r | |
1281 | IN SD_MMC_BUS_MODE Timing\r | |
1282 | )\r | |
1283 | {\r | |
1284 | EFI_STATUS Status;\r | |
1285 | UINT8 HostCtrl2;\r | |
1286 | \r | |
1287 | HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;\r | |
1288 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1289 | if (EFI_ERROR (Status)) {\r | |
1290 | return Status;\r | |
1291 | }\r | |
1292 | \r | |
1293 | switch (Timing) {\r | |
1294 | case SdMmcUhsSdr12:\r | |
1295 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;\r | |
1296 | break;\r | |
1297 | case SdMmcUhsSdr25:\r | |
1298 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;\r | |
1299 | break;\r | |
1300 | case SdMmcUhsSdr50:\r | |
1301 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;\r | |
1302 | break;\r | |
1303 | case SdMmcUhsSdr104:\r | |
1304 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;\r | |
1305 | break;\r | |
1306 | case SdMmcUhsDdr50:\r | |
1307 | HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;\r | |
1308 | break;\r | |
1309 | case SdMmcMmcLegacy:\r | |
1310 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;\r | |
1311 | break;\r | |
1312 | case SdMmcMmcHsSdr:\r | |
1313 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;\r | |
1314 | break;\r | |
1315 | case SdMmcMmcHsDdr:\r | |
1316 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;\r | |
1317 | break;\r | |
1318 | case SdMmcMmcHs200:\r | |
1319 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;\r | |
1320 | break;\r | |
1321 | case SdMmcMmcHs400:\r | |
1322 | HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;\r | |
1323 | break;\r | |
1324 | default:\r | |
1325 | HostCtrl2 = 0;\r | |
1326 | break;\r | |
1327 | }\r | |
1328 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1329 | if (EFI_ERROR (Status)) {\r | |
1330 | return Status;\r | |
1331 | }\r | |
1332 | \r | |
1333 | if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r | |
1334 | Status = mOverride->NotifyPhase (\r | |
1335 | ControllerHandle,\r | |
1336 | Slot,\r | |
1337 | EdkiiSdMmcUhsSignaling,\r | |
1338 | &Timing\r | |
1339 | );\r | |
1340 | if (EFI_ERROR (Status)) {\r | |
1341 | DEBUG ((\r | |
1342 | DEBUG_ERROR,\r | |
1343 | "%a: SD/MMC uhs signaling notifier callback failed - %r\n",\r | |
1344 | __FUNCTION__,\r | |
1345 | Status\r | |
1346 | ));\r | |
1347 | return Status;\r | |
1348 | }\r | |
1349 | }\r | |
1350 | \r | |
1351 | return EFI_SUCCESS;\r | |
1352 | }\r | |
1353 | \r | |
adec1f5d AM |
1354 | /**\r |
1355 | Set driver strength in host controller.\r | |
1356 | \r | |
1357 | @param[in] PciIo The PCI IO protocol instance.\r | |
1358 | @param[in] SlotIndex The slot index of the card.\r | |
1359 | @param[in] DriverStrength DriverStrength to set in the controller.\r | |
1360 | \r | |
1361 | @retval EFI_SUCCESS Driver strength programmed successfully.\r | |
1362 | @retval Others Failed to set driver strength.\r | |
1363 | **/\r | |
1364 | EFI_STATUS\r | |
1365 | SdMmcSetDriverStrength (\r | |
1366 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1367 | IN UINT8 SlotIndex,\r | |
1368 | IN SD_DRIVER_STRENGTH_TYPE DriverStrength\r | |
1369 | )\r | |
1370 | {\r | |
1371 | EFI_STATUS Status;\r | |
1372 | UINT16 HostCtrl2;\r | |
1373 | \r | |
1374 | if (DriverStrength == SdDriverStrengthIgnore) {\r | |
1375 | return EFI_SUCCESS;\r | |
1376 | }\r | |
1377 | \r | |
1378 | HostCtrl2 = (UINT16)~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;\r | |
1379 | Status = SdMmcHcAndMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1380 | if (EFI_ERROR (Status)) {\r | |
1381 | return Status;\r | |
1382 | }\r | |
1383 | \r | |
1384 | HostCtrl2 = (DriverStrength << 4) & SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;\r | |
1385 | return SdMmcHcOrMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r | |
1386 | }\r | |
1387 | \r | |
48555339 FT |
1388 | /**\r |
1389 | Turn on/off LED.\r | |
1390 | \r | |
1391 | @param[in] PciIo The PCI IO protocol instance.\r | |
1392 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1393 | @param[in] On The boolean to turn on/off LED.\r | |
1394 | \r | |
1395 | @retval EFI_SUCCESS The LED is turned on/off successfully.\r | |
1396 | @retval Others The LED isn't turned on/off successfully.\r | |
1397 | \r | |
1398 | **/\r | |
1399 | EFI_STATUS\r | |
1400 | SdMmcHcLedOnOff (\r | |
1401 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
1402 | IN UINT8 Slot,\r | |
1403 | IN BOOLEAN On\r | |
1404 | )\r | |
1405 | {\r | |
1406 | EFI_STATUS Status;\r | |
1407 | UINT8 HostCtrl1;\r | |
1408 | \r | |
1409 | if (On) {\r | |
1410 | HostCtrl1 = BIT0;\r | |
1411 | Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
1412 | } else {\r | |
1413 | HostCtrl1 = (UINT8)~BIT0;\r | |
1414 | Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
1415 | }\r | |
1416 | \r | |
1417 | return Status;\r | |
1418 | }\r | |
1419 | \r | |
1420 | /**\r | |
1421 | Build ADMA descriptor table for transfer.\r | |
1422 | \r | |
b5547b9c | 1423 | Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.\r |
48555339 FT |
1424 | \r |
1425 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
b5547b9c | 1426 | @param[in] ControllerVer The version of host controller.\r |
48555339 FT |
1427 | \r |
1428 | @retval EFI_SUCCESS The ADMA descriptor table is created successfully.\r | |
1429 | @retval Others The ADMA descriptor table isn't created successfully.\r | |
1430 | \r | |
1431 | **/\r | |
1432 | EFI_STATUS\r | |
1433 | BuildAdmaDescTable (\r | |
b5547b9c AS |
1434 | IN SD_MMC_HC_TRB *Trb,\r |
1435 | IN UINT16 ControllerVer\r | |
48555339 FT |
1436 | )\r |
1437 | {\r | |
1438 | EFI_PHYSICAL_ADDRESS Data;\r | |
1439 | UINT64 DataLen;\r | |
1440 | UINT64 Entries;\r | |
1441 | UINT32 Index;\r | |
1442 | UINT64 Remaining;\r | |
b5547b9c | 1443 | UINT64 Address;\r |
48555339 FT |
1444 | UINTN TableSize;\r |
1445 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1446 | EFI_STATUS Status;\r | |
1447 | UINTN Bytes;\r | |
b5547b9c AS |
1448 | UINT32 AdmaMaxDataPerLine;\r |
1449 | UINT32 DescSize;\r | |
1450 | VOID *AdmaDesc;\r | |
1451 | \r | |
b5547b9c AS |
1452 | AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;\r |
1453 | DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);\r | |
1454 | AdmaDesc = NULL;\r | |
48555339 FT |
1455 | \r |
1456 | Data = Trb->DataPhy;\r | |
1457 | DataLen = Trb->DataLen;\r | |
1458 | PciIo = Trb->Private->PciIo;\r | |
b5547b9c | 1459 | \r |
b5547b9c AS |
1460 | //\r |
1461 | // Check for valid ranges in 32bit ADMA Descriptor Table\r | |
1462 | //\r | |
690d60c0 | 1463 | if ((Trb->Mode == SdMmcAdma32bMode) &&\r |
b5547b9c | 1464 | ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {\r |
48555339 FT |
1465 | return EFI_INVALID_PARAMETER;\r |
1466 | }\r | |
1467 | //\r | |
b5547b9c | 1468 | // Check address field alignment\r |
48555339 | 1469 | //\r |
690d60c0 | 1470 | if (Trb->Mode != SdMmcAdma32bMode) {\r |
b5547b9c AS |
1471 | //\r |
1472 | // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)\r | |
1473 | //\r | |
1474 | if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {\r | |
1475 | DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));\r | |
1476 | }\r | |
1477 | } else {\r | |
1478 | //\r | |
1479 | // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r | |
1480 | //\r | |
1481 | if ((Data & (BIT0 | BIT1)) != 0) {\r | |
1482 | DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));\r | |
1483 | }\r | |
1484 | }\r | |
690d60c0 AS |
1485 | \r |
1486 | //\r | |
1487 | // Configure 64b ADMA.\r | |
b5547b9c | 1488 | //\r |
690d60c0 AS |
1489 | if (Trb->Mode == SdMmcAdma64bV3Mode) {\r |
1490 | DescSize = sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE);\r | |
1491 | }else if (Trb->Mode == SdMmcAdma64bV4Mode) {\r | |
1492 | DescSize = sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE);\r | |
1493 | }\r | |
b5547b9c | 1494 | //\r |
690d60c0 AS |
1495 | // Configure 26b data length.\r |
1496 | //\r | |
1497 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
b5547b9c | 1498 | AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;\r |
48555339 FT |
1499 | }\r |
1500 | \r | |
b5547b9c AS |
1501 | Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);\r |
1502 | TableSize = (UINTN)MultU64x32 (Entries, DescSize);\r | |
48555339 FT |
1503 | Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);\r |
1504 | Status = PciIo->AllocateBuffer (\r | |
1505 | PciIo,\r | |
1506 | AllocateAnyPages,\r | |
1507 | EfiBootServicesData,\r | |
1508 | EFI_SIZE_TO_PAGES (TableSize),\r | |
b5547b9c | 1509 | (VOID **)&AdmaDesc,\r |
48555339 FT |
1510 | 0\r |
1511 | );\r | |
1512 | if (EFI_ERROR (Status)) {\r | |
1513 | return EFI_OUT_OF_RESOURCES;\r | |
1514 | }\r | |
b5547b9c | 1515 | ZeroMem (AdmaDesc, TableSize);\r |
48555339 FT |
1516 | Bytes = TableSize;\r |
1517 | Status = PciIo->Map (\r | |
1518 | PciIo,\r | |
1519 | EfiPciIoOperationBusMasterCommonBuffer,\r | |
b5547b9c | 1520 | AdmaDesc,\r |
48555339 FT |
1521 | &Bytes,\r |
1522 | &Trb->AdmaDescPhy,\r | |
1523 | &Trb->AdmaMap\r | |
1524 | );\r | |
1525 | \r | |
1526 | if (EFI_ERROR (Status) || (Bytes != TableSize)) {\r | |
1527 | //\r | |
1528 | // Map error or unable to map the whole RFis buffer into a contiguous region.\r | |
1529 | //\r | |
1530 | PciIo->FreeBuffer (\r | |
1531 | PciIo,\r | |
1532 | EFI_SIZE_TO_PAGES (TableSize),\r | |
b5547b9c | 1533 | AdmaDesc\r |
48555339 FT |
1534 | );\r |
1535 | return EFI_OUT_OF_RESOURCES;\r | |
1536 | }\r | |
1537 | \r | |
690d60c0 | 1538 | if ((Trb->Mode == SdMmcAdma32bMode) &&\r |
b5547b9c | 1539 | (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {\r |
48555339 FT |
1540 | //\r |
1541 | // The ADMA doesn't support 64bit addressing.\r | |
1542 | //\r | |
1543 | PciIo->Unmap (\r | |
1544 | PciIo,\r | |
1545 | Trb->AdmaMap\r | |
1546 | );\r | |
1547 | PciIo->FreeBuffer (\r | |
1548 | PciIo,\r | |
1549 | EFI_SIZE_TO_PAGES (TableSize),\r | |
b5547b9c | 1550 | AdmaDesc\r |
48555339 FT |
1551 | );\r |
1552 | return EFI_DEVICE_ERROR;\r | |
1553 | }\r | |
1554 | \r | |
1555 | Remaining = DataLen;\r | |
b5547b9c | 1556 | Address = Data;\r |
690d60c0 | 1557 | if (Trb->Mode == SdMmcAdma32bMode) {\r |
b5547b9c | 1558 | Trb->Adma32Desc = AdmaDesc;\r |
690d60c0 AS |
1559 | } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r |
1560 | Trb->Adma64V3Desc = AdmaDesc;\r | |
b5547b9c | 1561 | } else {\r |
690d60c0 | 1562 | Trb->Adma64V4Desc = AdmaDesc;\r |
b5547b9c | 1563 | }\r |
690d60c0 | 1564 | \r |
48555339 | 1565 | for (Index = 0; Index < Entries; Index++) {\r |
690d60c0 | 1566 | if (Trb->Mode == SdMmcAdma32bMode) {\r |
b5547b9c AS |
1567 | if (Remaining <= AdmaMaxDataPerLine) {\r |
1568 | Trb->Adma32Desc[Index].Valid = 1;\r | |
1569 | Trb->Adma32Desc[Index].Act = 2;\r | |
690d60c0 | 1570 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r |
46f4c967 | 1571 | Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r |
b5547b9c AS |
1572 | }\r |
1573 | Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r | |
1574 | Trb->Adma32Desc[Index].Address = (UINT32)Address;\r | |
1575 | break;\r | |
1576 | } else {\r | |
1577 | Trb->Adma32Desc[Index].Valid = 1;\r | |
1578 | Trb->Adma32Desc[Index].Act = 2;\r | |
690d60c0 | 1579 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r |
b5547b9c AS |
1580 | Trb->Adma32Desc[Index].UpperLength = 0;\r |
1581 | }\r | |
1582 | Trb->Adma32Desc[Index].LowerLength = 0;\r | |
1583 | Trb->Adma32Desc[Index].Address = (UINT32)Address;\r | |
1584 | }\r | |
690d60c0 AS |
1585 | } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r |
1586 | if (Remaining <= AdmaMaxDataPerLine) {\r | |
1587 | Trb->Adma64V3Desc[Index].Valid = 1;\r | |
1588 | Trb->Adma64V3Desc[Index].Act = 2;\r | |
1589 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
1590 | Trb->Adma64V3Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r | |
1591 | }\r | |
1592 | Trb->Adma64V3Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r | |
1593 | Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;\r | |
1594 | Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r | |
1595 | break;\r | |
1596 | } else {\r | |
1597 | Trb->Adma64V3Desc[Index].Valid = 1;\r | |
1598 | Trb->Adma64V3Desc[Index].Act = 2;\r | |
1599 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
1600 | Trb->Adma64V3Desc[Index].UpperLength = 0;\r | |
1601 | }\r | |
1602 | Trb->Adma64V3Desc[Index].LowerLength = 0;\r | |
1603 | Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;\r | |
1604 | Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r | |
1605 | }\r | |
48555339 | 1606 | } else {\r |
b5547b9c | 1607 | if (Remaining <= AdmaMaxDataPerLine) {\r |
690d60c0 AS |
1608 | Trb->Adma64V4Desc[Index].Valid = 1;\r |
1609 | Trb->Adma64V4Desc[Index].Act = 2;\r | |
1610 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
1611 | Trb->Adma64V4Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);\r | |
b5547b9c | 1612 | }\r |
690d60c0 AS |
1613 | Trb->Adma64V4Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r |
1614 | Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;\r | |
1615 | Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r | |
b5547b9c AS |
1616 | break;\r |
1617 | } else {\r | |
690d60c0 AS |
1618 | Trb->Adma64V4Desc[Index].Valid = 1;\r |
1619 | Trb->Adma64V4Desc[Index].Act = 2;\r | |
1620 | if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {\r | |
1621 | Trb->Adma64V4Desc[Index].UpperLength = 0;\r | |
b5547b9c | 1622 | }\r |
690d60c0 AS |
1623 | Trb->Adma64V4Desc[Index].LowerLength = 0;\r |
1624 | Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;\r | |
1625 | Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);\r | |
b5547b9c | 1626 | }\r |
48555339 FT |
1627 | }\r |
1628 | \r | |
b5547b9c AS |
1629 | Remaining -= AdmaMaxDataPerLine;\r |
1630 | Address += AdmaMaxDataPerLine;\r | |
48555339 FT |
1631 | }\r |
1632 | \r | |
1633 | //\r | |
1634 | // Set the last descriptor line as end of descriptor table\r | |
1635 | //\r | |
690d60c0 AS |
1636 | if (Trb->Mode == SdMmcAdma32bMode) {\r |
1637 | Trb->Adma32Desc[Index].End = 1;\r | |
1638 | } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r | |
1639 | Trb->Adma64V3Desc[Index].End = 1;\r | |
1640 | } else {\r | |
1641 | Trb->Adma64V4Desc[Index].End = 1;\r | |
1642 | }\r | |
48555339 FT |
1643 | return EFI_SUCCESS;\r |
1644 | }\r | |
1645 | \r | |
1646 | /**\r | |
1647 | Create a new TRB for the SD/MMC cmd request.\r | |
1648 | \r | |
1649 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1650 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
1651 | @param[in] Packet A pointer to the SD command data structure.\r | |
1652 | @param[in] Event If Event is NULL, blocking I/O is performed. If Event is\r | |
1653 | not NULL, then nonblocking I/O is performed, and Event\r | |
1654 | will be signaled when the Packet completes.\r | |
1655 | \r | |
1656 | @return Created Trb or NULL.\r | |
1657 | \r | |
1658 | **/\r | |
1659 | SD_MMC_HC_TRB *\r | |
1660 | SdMmcCreateTrb (\r | |
1661 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1662 | IN UINT8 Slot,\r | |
1663 | IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,\r | |
1664 | IN EFI_EVENT Event\r | |
1665 | )\r | |
1666 | {\r | |
1667 | SD_MMC_HC_TRB *Trb;\r | |
1668 | EFI_STATUS Status;\r | |
1669 | EFI_TPL OldTpl;\r | |
1670 | EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r | |
1671 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1672 | UINTN MapLength;\r | |
1673 | \r | |
1674 | Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));\r | |
1675 | if (Trb == NULL) {\r | |
1676 | return NULL;\r | |
1677 | }\r | |
1678 | \r | |
1679 | Trb->Signature = SD_MMC_HC_TRB_SIG;\r | |
1680 | Trb->Slot = Slot;\r | |
1681 | Trb->BlockSize = 0x200;\r | |
1682 | Trb->Packet = Packet;\r | |
1683 | Trb->Event = Event;\r | |
1684 | Trb->Started = FALSE;\r | |
1685 | Trb->Timeout = Packet->Timeout;\r | |
c67617f3 | 1686 | Trb->Retries = SD_MMC_TRB_RETRIES;\r |
48555339 FT |
1687 | Trb->Private = Private;\r |
1688 | \r | |
1689 | if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {\r | |
1690 | Trb->Data = Packet->InDataBuffer;\r | |
1691 | Trb->DataLen = Packet->InTransferLength;\r | |
1692 | Trb->Read = TRUE;\r | |
1693 | } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {\r | |
1694 | Trb->Data = Packet->OutDataBuffer;\r | |
1695 | Trb->DataLen = Packet->OutTransferLength;\r | |
1696 | Trb->Read = FALSE;\r | |
1697 | } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {\r | |
1698 | Trb->Data = NULL;\r | |
1699 | Trb->DataLen = 0;\r | |
1700 | } else {\r | |
1701 | goto Error;\r | |
1702 | }\r | |
1703 | \r | |
54228046 | 1704 | if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {\r |
e7e89b08 FT |
1705 | Trb->BlockSize = (UINT16)Trb->DataLen;\r |
1706 | }\r | |
1707 | \r | |
1708 | if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r | |
1709 | (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r | |
1710 | ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r | |
1711 | (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {\r | |
1712 | Trb->Mode = SdMmcPioMode;\r | |
48555339 | 1713 | } else {\r |
e7e89b08 FT |
1714 | if (Trb->Read) {\r |
1715 | Flag = EfiPciIoOperationBusMasterWrite;\r | |
1716 | } else {\r | |
1717 | Flag = EfiPciIoOperationBusMasterRead;\r | |
48555339 | 1718 | }\r |
48555339 | 1719 | \r |
e7e89b08 FT |
1720 | PciIo = Private->PciIo;\r |
1721 | if (Trb->DataLen != 0) {\r | |
1722 | MapLength = Trb->DataLen;\r | |
1723 | Status = PciIo->Map (\r | |
1724 | PciIo,\r | |
1725 | Flag,\r | |
1726 | Trb->Data,\r | |
1727 | &MapLength,\r | |
1728 | &Trb->DataPhy,\r | |
1729 | &Trb->DataMap\r | |
1730 | );\r | |
1731 | if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {\r | |
1732 | Status = EFI_BAD_BUFFER_SIZE;\r | |
1733 | goto Error;\r | |
1734 | }\r | |
48555339 | 1735 | }\r |
48555339 | 1736 | \r |
e7e89b08 FT |
1737 | if (Trb->DataLen == 0) {\r |
1738 | Trb->Mode = SdMmcNoData;\r | |
1739 | } else if (Private->Capability[Slot].Adma2 != 0) {\r | |
690d60c0 AS |
1740 | Trb->Mode = SdMmcAdma32bMode;\r |
1741 | Trb->AdmaLengthMode = SdMmcAdmaLen16b;\r | |
1742 | if ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300) &&\r | |
1743 | (Private->Capability[Slot].SysBus64V3 == 1)) {\r | |
1744 | Trb->Mode = SdMmcAdma64bV3Mode;\r | |
1745 | } else if (((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400) &&\r | |
1746 | (Private->Capability[Slot].SysBus64V3 == 1)) ||\r | |
1747 | ((Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) &&\r | |
1748 | (Private->Capability[Slot].SysBus64V4 == 1))) {\r | |
1749 | Trb->Mode = SdMmcAdma64bV4Mode;\r | |
1750 | }\r | |
1751 | if (Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) {\r | |
1752 | Trb->AdmaLengthMode = SdMmcAdmaLen26b;\r | |
1753 | }\r | |
b5547b9c | 1754 | Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);\r |
e7e89b08 FT |
1755 | if (EFI_ERROR (Status)) {\r |
1756 | PciIo->Unmap (PciIo, Trb->DataMap);\r | |
1757 | goto Error;\r | |
1758 | }\r | |
1759 | } else if (Private->Capability[Slot].Sdma != 0) {\r | |
1760 | Trb->Mode = SdMmcSdmaMode;\r | |
1761 | } else {\r | |
1762 | Trb->Mode = SdMmcPioMode;\r | |
48555339 | 1763 | }\r |
48555339 FT |
1764 | }\r |
1765 | \r | |
1766 | if (Event != NULL) {\r | |
3b1d8241 | 1767 | OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r |
48555339 FT |
1768 | InsertTailList (&Private->Queue, &Trb->TrbList);\r |
1769 | gBS->RestoreTPL (OldTpl);\r | |
1770 | }\r | |
1771 | \r | |
1772 | return Trb;\r | |
1773 | \r | |
1774 | Error:\r | |
1775 | SdMmcFreeTrb (Trb);\r | |
1776 | return NULL;\r | |
1777 | }\r | |
1778 | \r | |
1779 | /**\r | |
1780 | Free the resource used by the TRB.\r | |
1781 | \r | |
1782 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1783 | \r | |
1784 | **/\r | |
1785 | VOID\r | |
1786 | SdMmcFreeTrb (\r | |
1787 | IN SD_MMC_HC_TRB *Trb\r | |
1788 | )\r | |
1789 | {\r | |
1790 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1791 | \r | |
1792 | PciIo = Trb->Private->PciIo;\r | |
1793 | \r | |
1794 | if (Trb->AdmaMap != NULL) {\r | |
1795 | PciIo->Unmap (\r | |
1796 | PciIo,\r | |
1797 | Trb->AdmaMap\r | |
1798 | );\r | |
1799 | }\r | |
b5547b9c AS |
1800 | if (Trb->Adma32Desc != NULL) {\r |
1801 | PciIo->FreeBuffer (\r | |
1802 | PciIo,\r | |
1803 | Trb->AdmaPages,\r | |
1804 | Trb->Adma32Desc\r | |
1805 | );\r | |
1806 | }\r | |
690d60c0 | 1807 | if (Trb->Adma64V3Desc != NULL) {\r |
48555339 FT |
1808 | PciIo->FreeBuffer (\r |
1809 | PciIo,\r | |
1810 | Trb->AdmaPages,\r | |
690d60c0 AS |
1811 | Trb->Adma64V3Desc\r |
1812 | );\r | |
1813 | }\r | |
1814 | if (Trb->Adma64V4Desc != NULL) {\r | |
1815 | PciIo->FreeBuffer (\r | |
1816 | PciIo,\r | |
1817 | Trb->AdmaPages,\r | |
1818 | Trb->Adma64V4Desc\r | |
48555339 FT |
1819 | );\r |
1820 | }\r | |
1821 | if (Trb->DataMap != NULL) {\r | |
1822 | PciIo->Unmap (\r | |
1823 | PciIo,\r | |
1824 | Trb->DataMap\r | |
1825 | );\r | |
1826 | }\r | |
1827 | FreePool (Trb);\r | |
1828 | return;\r | |
1829 | }\r | |
1830 | \r | |
1831 | /**\r | |
1832 | Check if the env is ready for execute specified TRB.\r | |
1833 | \r | |
1834 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1835 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1836 | \r | |
1837 | @retval EFI_SUCCESS The env is ready for TRB execution.\r | |
1838 | @retval EFI_NOT_READY The env is not ready for TRB execution.\r | |
1839 | @retval Others Some erros happen.\r | |
1840 | \r | |
1841 | **/\r | |
1842 | EFI_STATUS\r | |
1843 | SdMmcCheckTrbEnv (\r | |
1844 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1845 | IN SD_MMC_HC_TRB *Trb\r | |
1846 | )\r | |
1847 | {\r | |
1848 | EFI_STATUS Status;\r | |
1849 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
1850 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1851 | UINT32 PresentState;\r | |
1852 | \r | |
1853 | Packet = Trb->Packet;\r | |
1854 | \r | |
1855 | if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||\r | |
1856 | (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||\r | |
1857 | (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {\r | |
1858 | //\r | |
1859 | // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in\r | |
1860 | // the Present State register to be 0\r | |
1861 | //\r | |
1862 | PresentState = BIT0 | BIT1;\r | |
48555339 FT |
1863 | } else {\r |
1864 | //\r | |
1865 | // Wait Command Inhibit (CMD) in the Present State register\r | |
1866 | // to be 0\r | |
1867 | //\r | |
1868 | PresentState = BIT0;\r | |
1869 | }\r | |
1870 | \r | |
1871 | PciIo = Private->PciIo;\r | |
1872 | Status = SdMmcHcCheckMmioSet (\r | |
1873 | PciIo,\r | |
1874 | Trb->Slot,\r | |
1875 | SD_MMC_HC_PRESENT_STATE,\r | |
1876 | sizeof (PresentState),\r | |
1877 | PresentState,\r | |
1878 | 0\r | |
1879 | );\r | |
1880 | \r | |
1881 | return Status;\r | |
1882 | }\r | |
1883 | \r | |
1884 | /**\r | |
1885 | Wait for the env to be ready for execute specified TRB.\r | |
1886 | \r | |
1887 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1888 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1889 | \r | |
1890 | @retval EFI_SUCCESS The env is ready for TRB execution.\r | |
1891 | @retval EFI_TIMEOUT The env is not ready for TRB execution in time.\r | |
1892 | @retval Others Some erros happen.\r | |
1893 | \r | |
1894 | **/\r | |
1895 | EFI_STATUS\r | |
1896 | SdMmcWaitTrbEnv (\r | |
1897 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1898 | IN SD_MMC_HC_TRB *Trb\r | |
1899 | )\r | |
1900 | {\r | |
1901 | EFI_STATUS Status;\r | |
1902 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
1903 | UINT64 Timeout;\r | |
1904 | BOOLEAN InfiniteWait;\r | |
1905 | \r | |
1906 | //\r | |
1907 | // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r | |
1908 | //\r | |
1909 | Packet = Trb->Packet;\r | |
1910 | Timeout = Packet->Timeout;\r | |
1911 | if (Timeout == 0) {\r | |
1912 | InfiniteWait = TRUE;\r | |
1913 | } else {\r | |
1914 | InfiniteWait = FALSE;\r | |
1915 | }\r | |
1916 | \r | |
1917 | while (InfiniteWait || (Timeout > 0)) {\r | |
1918 | //\r | |
1919 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
1920 | //\r | |
1921 | Status = SdMmcCheckTrbEnv (Private, Trb);\r | |
1922 | if (Status != EFI_NOT_READY) {\r | |
1923 | return Status;\r | |
1924 | }\r | |
1925 | //\r | |
1926 | // Stall for 1 microsecond.\r | |
1927 | //\r | |
1928 | gBS->Stall (1);\r | |
1929 | \r | |
1930 | Timeout--;\r | |
1931 | }\r | |
1932 | \r | |
1933 | return EFI_TIMEOUT;\r | |
1934 | }\r | |
1935 | \r | |
1936 | /**\r | |
1937 | Execute the specified TRB.\r | |
1938 | \r | |
1939 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
1940 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
1941 | \r | |
1942 | @retval EFI_SUCCESS The TRB is sent to host controller successfully.\r | |
1943 | @retval Others Some erros happen when sending this request to the host controller.\r | |
1944 | \r | |
1945 | **/\r | |
1946 | EFI_STATUS\r | |
1947 | SdMmcExecTrb (\r | |
1948 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
1949 | IN SD_MMC_HC_TRB *Trb\r | |
1950 | )\r | |
1951 | {\r | |
1952 | EFI_STATUS Status;\r | |
1953 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
1954 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1955 | UINT16 Cmd;\r | |
1956 | UINT16 IntStatus;\r | |
1957 | UINT32 Argument;\r | |
b5547b9c | 1958 | UINT32 BlkCount;\r |
48555339 FT |
1959 | UINT16 BlkSize;\r |
1960 | UINT16 TransMode;\r | |
1961 | UINT8 HostCtrl1;\r | |
b5547b9c | 1962 | UINT64 SdmaAddr;\r |
48555339 | 1963 | UINT64 AdmaAddr;\r |
b5547b9c AS |
1964 | BOOLEAN AddressingMode64;\r |
1965 | \r | |
1966 | AddressingMode64 = FALSE;\r | |
48555339 FT |
1967 | \r |
1968 | Packet = Trb->Packet;\r | |
1969 | PciIo = Trb->Private->PciIo;\r | |
1970 | //\r | |
1971 | // Clear all bits in Error Interrupt Status Register\r | |
1972 | //\r | |
1973 | IntStatus = 0xFFFF;\r | |
1974 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
1975 | if (EFI_ERROR (Status)) {\r | |
1976 | return Status;\r | |
1977 | }\r | |
1978 | //\r | |
1979 | // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.\r | |
1980 | //\r | |
1981 | IntStatus = 0xFF3F;\r | |
1982 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
1983 | if (EFI_ERROR (Status)) {\r | |
1984 | return Status;\r | |
1985 | }\r | |
690d60c0 AS |
1986 | \r |
1987 | if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r | |
1988 | Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),\r | |
1989 | SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_64_ADDR_EN);\r | |
1990 | if (!EFI_ERROR (Status)) {\r | |
1991 | AddressingMode64 = TRUE;\r | |
1992 | }\r | |
1993 | }\r | |
1994 | \r | |
48555339 FT |
1995 | //\r |
1996 | // Set Host Control 1 register DMA Select field\r | |
1997 | //\r | |
690d60c0 AS |
1998 | if ((Trb->Mode == SdMmcAdma32bMode) ||\r |
1999 | (Trb->Mode == SdMmcAdma64bV4Mode)) {\r | |
48555339 FT |
2000 | HostCtrl1 = BIT4;\r |
2001 | Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
2002 | if (EFI_ERROR (Status)) {\r | |
2003 | return Status;\r | |
2004 | }\r | |
690d60c0 AS |
2005 | } else if (Trb->Mode == SdMmcAdma64bV3Mode) {\r |
2006 | HostCtrl1 = BIT4|BIT3;\r | |
2007 | Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r | |
2008 | if (EFI_ERROR (Status)) {\r | |
2009 | return Status;\r | |
2010 | }\r | |
48555339 FT |
2011 | }\r |
2012 | \r | |
2013 | SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);\r | |
2014 | \r | |
2015 | if (Trb->Mode == SdMmcSdmaMode) {\r | |
b5547b9c AS |
2016 | if ((!AddressingMode64) &&\r |
2017 | ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {\r | |
48555339 FT |
2018 | return EFI_INVALID_PARAMETER;\r |
2019 | }\r | |
2020 | \r | |
b5547b9c AS |
2021 | SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;\r |
2022 | \r | |
2023 | if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r | |
2024 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);\r | |
2025 | } else {\r | |
2026 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);\r | |
2027 | }\r | |
2028 | \r | |
48555339 FT |
2029 | if (EFI_ERROR (Status)) {\r |
2030 | return Status;\r | |
2031 | }\r | |
690d60c0 AS |
2032 | } else if ((Trb->Mode == SdMmcAdma32bMode) ||\r |
2033 | (Trb->Mode == SdMmcAdma64bV3Mode) ||\r | |
2034 | (Trb->Mode == SdMmcAdma64bV4Mode)) {\r | |
48555339 FT |
2035 | AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;\r |
2036 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);\r | |
2037 | if (EFI_ERROR (Status)) {\r | |
2038 | return Status;\r | |
2039 | }\r | |
2040 | }\r | |
2041 | \r | |
2042 | BlkSize = Trb->BlockSize;\r | |
2043 | if (Trb->Mode == SdMmcSdmaMode) {\r | |
2044 | //\r | |
2045 | // Set SDMA boundary to be 512K bytes.\r | |
2046 | //\r | |
2047 | BlkSize |= 0x7000;\r | |
2048 | }\r | |
2049 | \r | |
2050 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);\r | |
2051 | if (EFI_ERROR (Status)) {\r | |
2052 | return Status;\r | |
2053 | }\r | |
2054 | \r | |
e7e89b08 FT |
2055 | BlkCount = 0;\r |
2056 | if (Trb->Mode != SdMmcNoData) {\r | |
2057 | //\r | |
2058 | // Calcuate Block Count.\r | |
2059 | //\r | |
b5547b9c AS |
2060 | BlkCount = (Trb->DataLen / Trb->BlockSize);\r |
2061 | }\r | |
2062 | if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {\r | |
2063 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);\r | |
2064 | } else {\r | |
2065 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);\r | |
e7e89b08 | 2066 | }\r |
48555339 FT |
2067 | if (EFI_ERROR (Status)) {\r |
2068 | return Status;\r | |
2069 | }\r | |
2070 | \r | |
2071 | Argument = Packet->SdMmcCmdBlk->CommandArgument;\r | |
2072 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);\r | |
2073 | if (EFI_ERROR (Status)) {\r | |
2074 | return Status;\r | |
2075 | }\r | |
2076 | \r | |
2077 | TransMode = 0;\r | |
2078 | if (Trb->Mode != SdMmcNoData) {\r | |
2079 | if (Trb->Mode != SdMmcPioMode) {\r | |
2080 | TransMode |= BIT0;\r | |
2081 | }\r | |
2082 | if (Trb->Read) {\r | |
2083 | TransMode |= BIT4;\r | |
2084 | }\r | |
e7e89b08 | 2085 | if (BlkCount > 1) {\r |
48555339 FT |
2086 | TransMode |= BIT5 | BIT1;\r |
2087 | }\r | |
2088 | //\r | |
2089 | // Only SD memory card needs to use AUTO CMD12 feature.\r | |
2090 | //\r | |
2091 | if (Private->Slot[Trb->Slot].CardType == SdCardType) {\r | |
2092 | if (BlkCount > 1) {\r | |
2093 | TransMode |= BIT2;\r | |
2094 | }\r | |
2095 | }\r | |
2096 | }\r | |
2097 | \r | |
2098 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);\r | |
2099 | if (EFI_ERROR (Status)) {\r | |
2100 | return Status;\r | |
2101 | }\r | |
2102 | \r | |
2103 | Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);\r | |
2104 | if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {\r | |
2105 | Cmd |= BIT5;\r | |
2106 | }\r | |
2107 | //\r | |
2108 | // Convert ResponseType to value\r | |
2109 | //\r | |
2110 | if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r | |
2111 | switch (Packet->SdMmcCmdBlk->ResponseType) {\r | |
2112 | case SdMmcResponseTypeR1:\r | |
2113 | case SdMmcResponseTypeR5:\r | |
2114 | case SdMmcResponseTypeR6:\r | |
2115 | case SdMmcResponseTypeR7:\r | |
2116 | Cmd |= (BIT1 | BIT3 | BIT4);\r | |
2117 | break;\r | |
2118 | case SdMmcResponseTypeR2:\r | |
2119 | Cmd |= (BIT0 | BIT3);\r | |
2120 | break;\r | |
2121 | case SdMmcResponseTypeR3:\r | |
2122 | case SdMmcResponseTypeR4:\r | |
2123 | Cmd |= BIT1;\r | |
2124 | break;\r | |
2125 | case SdMmcResponseTypeR1b:\r | |
2126 | case SdMmcResponseTypeR5b:\r | |
2127 | Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);\r | |
2128 | break;\r | |
2129 | default:\r | |
2130 | ASSERT (FALSE);\r | |
2131 | break;\r | |
2132 | }\r | |
2133 | }\r | |
2134 | //\r | |
2135 | // Execute cmd\r | |
2136 | //\r | |
2137 | Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);\r | |
2138 | return Status;\r | |
2139 | }\r | |
2140 | \r | |
a22f4c34 AM |
2141 | /**\r |
2142 | Performs SW reset based on passed error status mask.\r | |
2143 | \r | |
2144 | @param[in] Private Pointer to driver private data.\r | |
2145 | @param[in] Slot Index of the slot to reset.\r | |
2146 | @param[in] ErrIntStatus Error interrupt status mask.\r | |
2147 | \r | |
2148 | @retval EFI_SUCCESS Software reset performed successfully.\r | |
2149 | @retval Other Software reset failed.\r | |
2150 | **/\r | |
2151 | EFI_STATUS\r | |
2152 | SdMmcSoftwareReset (\r | |
2153 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2154 | IN UINT8 Slot,\r | |
2155 | IN UINT16 ErrIntStatus\r | |
2156 | )\r | |
2157 | {\r | |
2158 | UINT8 SwReset;\r | |
2159 | EFI_STATUS Status;\r | |
2160 | \r | |
2161 | SwReset = 0;\r | |
2162 | if ((ErrIntStatus & 0x0F) != 0) {\r | |
2163 | SwReset |= BIT1;\r | |
2164 | }\r | |
2165 | if ((ErrIntStatus & 0x70) != 0) {\r | |
2166 | SwReset |= BIT2;\r | |
2167 | }\r | |
2168 | \r | |
2169 | Status = SdMmcHcRwMmio (\r | |
2170 | Private->PciIo,\r | |
2171 | Slot,\r | |
2172 | SD_MMC_HC_SW_RST,\r | |
2173 | FALSE,\r | |
2174 | sizeof (SwReset),\r | |
2175 | &SwReset\r | |
2176 | );\r | |
2177 | if (EFI_ERROR (Status)) {\r | |
2178 | return Status;\r | |
2179 | }\r | |
2180 | \r | |
2181 | Status = SdMmcHcWaitMmioSet (\r | |
2182 | Private->PciIo,\r | |
2183 | Slot,\r | |
2184 | SD_MMC_HC_SW_RST,\r | |
2185 | sizeof (SwReset),\r | |
2186 | 0xFF,\r | |
2187 | 0,\r | |
2188 | SD_MMC_HC_GENERIC_TIMEOUT\r | |
2189 | );\r | |
2190 | if (EFI_ERROR (Status)) {\r | |
2191 | return Status;\r | |
2192 | }\r | |
2193 | \r | |
2194 | return EFI_SUCCESS;\r | |
2195 | }\r | |
2196 | \r | |
2197 | /**\r | |
2198 | Checks the error status in error status register\r | |
2199 | and issues appropriate software reset as described in\r | |
2200 | SD specification section 3.10.\r | |
2201 | \r | |
2202 | @param[in] Private Pointer to driver private data.\r | |
1e947f9b | 2203 | @param[in] Slot Index of the slot for device.\r |
a22f4c34 AM |
2204 | @param[in] IntStatus Normal interrupt status mask.\r |
2205 | \r | |
2206 | @retval EFI_CRC_ERROR CRC error happened during CMD execution.\r | |
2207 | @retval EFI_SUCCESS No error reported.\r | |
2208 | @retval Others Some other error happened.\r | |
2209 | \r | |
2210 | **/\r | |
2211 | EFI_STATUS\r | |
2212 | SdMmcCheckAndRecoverErrors (\r | |
2213 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2214 | IN UINT8 Slot,\r | |
2215 | IN UINT16 IntStatus\r | |
2216 | )\r | |
2217 | {\r | |
2218 | UINT16 ErrIntStatus;\r | |
2219 | EFI_STATUS Status;\r | |
2220 | EFI_STATUS ErrorStatus;\r | |
2221 | \r | |
2222 | if ((IntStatus & BIT15) == 0) {\r | |
2223 | return EFI_SUCCESS;\r | |
2224 | }\r | |
2225 | \r | |
2226 | Status = SdMmcHcRwMmio (\r | |
2227 | Private->PciIo,\r | |
2228 | Slot,\r | |
2229 | SD_MMC_HC_ERR_INT_STS,\r | |
2230 | TRUE,\r | |
2231 | sizeof (ErrIntStatus),\r | |
2232 | &ErrIntStatus\r | |
2233 | );\r | |
2234 | if (EFI_ERROR (Status)) {\r | |
2235 | return Status;\r | |
2236 | }\r | |
2237 | \r | |
2238 | //\r | |
2239 | // If the data timeout error is reported\r | |
2240 | // but data transfer is signaled as completed we\r | |
2241 | // have to ignore data timeout. We also assume that no\r | |
2242 | // other error is present on the link since data transfer\r | |
2243 | // completed successfully. Error interrupt status\r | |
2244 | // register is going to be reset when the next command\r | |
2245 | // is started.\r | |
2246 | //\r | |
2247 | if (((ErrIntStatus & BIT4) != 0) && ((IntStatus & BIT1) != 0)) {\r | |
2248 | return EFI_SUCCESS;\r | |
2249 | }\r | |
2250 | \r | |
2251 | //\r | |
2252 | // We treat both CMD and DAT CRC errors and\r | |
2253 | // end bits errors as EFI_CRC_ERROR. This will\r | |
2254 | // let higher layer know that the error possibly\r | |
2255 | // happened due to random bus condition and the\r | |
2256 | // command can be retried.\r | |
2257 | //\r | |
2258 | if ((ErrIntStatus & (BIT1 | BIT2 | BIT5 | BIT6)) != 0) {\r | |
2259 | ErrorStatus = EFI_CRC_ERROR;\r | |
2260 | } else {\r | |
2261 | ErrorStatus = EFI_DEVICE_ERROR;\r | |
2262 | }\r | |
2263 | \r | |
2264 | Status = SdMmcSoftwareReset (Private, Slot, ErrIntStatus);\r | |
2265 | if (EFI_ERROR (Status)) {\r | |
2266 | return Status;\r | |
2267 | }\r | |
2268 | \r | |
2269 | return ErrorStatus;\r | |
2270 | }\r | |
2271 | \r | |
48555339 FT |
2272 | /**\r |
2273 | Check the TRB execution result.\r | |
2274 | \r | |
2275 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2276 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2277 | \r | |
2278 | @retval EFI_SUCCESS The TRB is executed successfully.\r | |
2279 | @retval EFI_NOT_READY The TRB is not completed for execution.\r | |
2280 | @retval Others Some erros happen when executing this request.\r | |
2281 | \r | |
2282 | **/\r | |
2283 | EFI_STATUS\r | |
2284 | SdMmcCheckTrbResult (\r | |
2285 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2286 | IN SD_MMC_HC_TRB *Trb\r | |
2287 | )\r | |
2288 | {\r | |
2289 | EFI_STATUS Status;\r | |
2290 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
2291 | UINT16 IntStatus;\r | |
2292 | UINT32 Response[4];\r | |
b5547b9c | 2293 | UINT64 SdmaAddr;\r |
48555339 | 2294 | UINT8 Index;\r |
e7e89b08 | 2295 | UINT32 PioLength;\r |
48555339 | 2296 | \r |
48555339 FT |
2297 | Packet = Trb->Packet;\r |
2298 | //\r | |
2299 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
2300 | //\r | |
2301 | Status = SdMmcHcRwMmio (\r | |
2302 | Private->PciIo,\r | |
2303 | Trb->Slot,\r | |
2304 | SD_MMC_HC_NOR_INT_STS,\r | |
2305 | TRUE,\r | |
2306 | sizeof (IntStatus),\r | |
2307 | &IntStatus\r | |
2308 | );\r | |
2309 | if (EFI_ERROR (Status)) {\r | |
2310 | goto Done;\r | |
2311 | }\r | |
a22f4c34 | 2312 | \r |
48555339 | 2313 | //\r |
a22f4c34 AM |
2314 | // Check if there are any errors reported by host controller\r |
2315 | // and if neccessary recover the controller before next command is executed.\r | |
48555339 | 2316 | //\r |
a22f4c34 AM |
2317 | Status = SdMmcCheckAndRecoverErrors (Private, Trb->Slot, IntStatus);\r |
2318 | if (EFI_ERROR (Status)) {\r | |
48555339 FT |
2319 | goto Done;\r |
2320 | }\r | |
a22f4c34 | 2321 | \r |
48555339 | 2322 | //\r |
a22f4c34 | 2323 | // Check Transfer Complete bit is set or not.\r |
48555339 | 2324 | //\r |
a22f4c34 | 2325 | if ((IntStatus & BIT1) == BIT1) {\r |
48555339 FT |
2326 | goto Done;\r |
2327 | }\r | |
a22f4c34 | 2328 | \r |
48555339 FT |
2329 | //\r |
2330 | // Check if DMA interrupt is signalled for the SDMA transfer.\r | |
2331 | //\r | |
2332 | if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {\r | |
2333 | //\r | |
2334 | // Clear DMA interrupt bit.\r | |
2335 | //\r | |
2336 | IntStatus = BIT3;\r | |
2337 | Status = SdMmcHcRwMmio (\r | |
2338 | Private->PciIo,\r | |
2339 | Trb->Slot,\r | |
2340 | SD_MMC_HC_NOR_INT_STS,\r | |
2341 | FALSE,\r | |
2342 | sizeof (IntStatus),\r | |
2343 | &IntStatus\r | |
2344 | );\r | |
2345 | if (EFI_ERROR (Status)) {\r | |
2346 | goto Done;\r | |
2347 | }\r | |
2348 | //\r | |
2349 | // Update SDMA Address register.\r | |
2350 | //\r | |
b5547b9c AS |
2351 | SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);\r |
2352 | \r | |
2353 | if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r | |
2354 | Status = SdMmcHcRwMmio (\r | |
2355 | Private->PciIo,\r | |
2356 | Trb->Slot,\r | |
2357 | SD_MMC_HC_ADMA_SYS_ADDR,\r | |
2358 | FALSE,\r | |
2359 | sizeof (UINT64),\r | |
2360 | &SdmaAddr\r | |
2361 | );\r | |
2362 | } else {\r | |
2363 | Status = SdMmcHcRwMmio (\r | |
48555339 FT |
2364 | Private->PciIo,\r |
2365 | Trb->Slot,\r | |
2366 | SD_MMC_HC_SDMA_ADDR,\r | |
2367 | FALSE,\r | |
2368 | sizeof (UINT32),\r | |
2369 | &SdmaAddr\r | |
2370 | );\r | |
b5547b9c AS |
2371 | }\r |
2372 | \r | |
48555339 FT |
2373 | if (EFI_ERROR (Status)) {\r |
2374 | goto Done;\r | |
2375 | }\r | |
b5547b9c | 2376 | Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;\r |
48555339 FT |
2377 | }\r |
2378 | \r | |
2379 | if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&\r | |
2380 | (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&\r | |
2381 | (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {\r | |
2382 | if ((IntStatus & BIT0) == BIT0) {\r | |
2383 | Status = EFI_SUCCESS;\r | |
2384 | goto Done;\r | |
2385 | }\r | |
2386 | }\r | |
2387 | \r | |
2388 | if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&\r | |
2389 | (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||\r | |
2390 | ((Private->Slot[Trb->Slot].CardType == SdCardType) &&\r | |
2391 | (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {\r | |
2392 | //\r | |
e7e89b08 FT |
2393 | // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,\r |
2394 | // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.\r | |
2395 | // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.\r | |
48555339 | 2396 | //\r |
e7e89b08 FT |
2397 | if ((IntStatus & BIT5) == BIT5) {\r |
2398 | //\r | |
2399 | // Clear Buffer Read Ready interrupt at first.\r | |
2400 | //\r | |
2401 | IntStatus = BIT5;\r | |
2402 | SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r | |
2403 | //\r | |
2404 | // Read data out from Buffer Port register\r | |
2405 | //\r | |
2406 | for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {\r | |
2407 | SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);\r | |
2408 | }\r | |
2409 | Status = EFI_SUCCESS;\r | |
2410 | goto Done;\r | |
2411 | }\r | |
48555339 FT |
2412 | }\r |
2413 | \r | |
2414 | Status = EFI_NOT_READY;\r | |
2415 | Done:\r | |
2416 | //\r | |
2417 | // Get response data when the cmd is executed successfully.\r | |
2418 | //\r | |
2419 | if (!EFI_ERROR (Status)) {\r | |
2420 | if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {\r | |
2421 | for (Index = 0; Index < 4; Index++) {\r | |
2422 | Status = SdMmcHcRwMmio (\r | |
2423 | Private->PciIo,\r | |
2424 | Trb->Slot,\r | |
2425 | SD_MMC_HC_RESPONSE + Index * 4,\r | |
2426 | TRUE,\r | |
2427 | sizeof (UINT32),\r | |
2428 | &Response[Index]\r | |
2429 | );\r | |
2430 | if (EFI_ERROR (Status)) {\r | |
2431 | SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r | |
2432 | return Status;\r | |
2433 | }\r | |
2434 | }\r | |
2435 | CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));\r | |
2436 | }\r | |
2437 | }\r | |
2438 | \r | |
2439 | if (Status != EFI_NOT_READY) {\r | |
2440 | SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);\r | |
2441 | }\r | |
2442 | \r | |
2443 | return Status;\r | |
2444 | }\r | |
2445 | \r | |
2446 | /**\r | |
2447 | Wait for the TRB execution result.\r | |
2448 | \r | |
2449 | @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r | |
2450 | @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r | |
2451 | \r | |
2452 | @retval EFI_SUCCESS The TRB is executed successfully.\r | |
2453 | @retval Others Some erros happen when executing this request.\r | |
2454 | \r | |
2455 | **/\r | |
2456 | EFI_STATUS\r | |
2457 | SdMmcWaitTrbResult (\r | |
2458 | IN SD_MMC_HC_PRIVATE_DATA *Private,\r | |
2459 | IN SD_MMC_HC_TRB *Trb\r | |
2460 | )\r | |
2461 | {\r | |
2462 | EFI_STATUS Status;\r | |
2463 | EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r | |
2464 | UINT64 Timeout;\r | |
2465 | BOOLEAN InfiniteWait;\r | |
2466 | \r | |
2467 | Packet = Trb->Packet;\r | |
2468 | //\r | |
2469 | // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r | |
2470 | //\r | |
2471 | Timeout = Packet->Timeout;\r | |
2472 | if (Timeout == 0) {\r | |
2473 | InfiniteWait = TRUE;\r | |
2474 | } else {\r | |
2475 | InfiniteWait = FALSE;\r | |
2476 | }\r | |
2477 | \r | |
2478 | while (InfiniteWait || (Timeout > 0)) {\r | |
2479 | //\r | |
2480 | // Check Trb execution result by reading Normal Interrupt Status register.\r | |
2481 | //\r | |
2482 | Status = SdMmcCheckTrbResult (Private, Trb);\r | |
2483 | if (Status != EFI_NOT_READY) {\r | |
2484 | return Status;\r | |
2485 | }\r | |
2486 | //\r | |
2487 | // Stall for 1 microsecond.\r | |
2488 | //\r | |
2489 | gBS->Stall (1);\r | |
2490 | \r | |
2491 | Timeout--;\r | |
2492 | }\r | |
2493 | \r | |
2494 | return EFI_TIMEOUT;\r | |
2495 | }\r | |
2496 | \r |