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KVM: SVM: Dump vmcb contents on failed vmrun
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
67ec6607 31#include <asm/tlbflush.h>
e495606d 32#include <asm/desc.h>
6aa8b732 33
63d1142f 34#include <asm/virtext.h>
229456fc 35#include "trace.h"
63d1142f 36
4ecac3fd
AK		 37#define __ex(x) __kvm_handle_fault_on_reboot(x)
38
6aa8b732
AK		 39MODULE_AUTHOR("Qumranet");
40MODULE_LICENSE("GPL");
41
42#define IOPM_ALLOC_ORDER 2
43#define MSRPM_ALLOC_ORDER 1
44
6aa8b732
AK		 45#define SEG_TYPE_LDT 2
46#define SEG_TYPE_BUSY_TSS16 3
47
6bc31bdc
AP		 48#define SVM_FEATURE_NPT (1 << 0)
49#define SVM_FEATURE_LBRV (1 << 1)
50#define SVM_FEATURE_SVML (1 << 2)
51#define SVM_FEATURE_NRIP (1 << 3)
52#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 53
410e4d57
JR		 54#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
55#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
56#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
57
24e09cbf
JR		 58#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
59
67ec6607
JR		 60static bool erratum_383_found __read_mostly;
61
6c8166a7
AK		 62static const u32 host_save_user_msrs[] = {
63#ifdef CONFIG_X86_64
64 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
65 MSR_FS_BASE,
66#endif
67 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
68};
69
70#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
71
72struct kvm_vcpu;
73
e6aa9abd
JR		 74struct nested_state {
75 struct vmcb *hsave;
76 u64 hsave_msr;
4a810181 77 u64 vm_cr_msr;
e6aa9abd
JR		 78 u64 vmcb;
79
80 /* These are the merged vectors */
81 u32 *msrpm;
82
83 /* gpa pointers to the real vectors */
84 u64 vmcb_msrpm;
ce2ac085 85 u64 vmcb_iopm;
aad42c64 86
cd3ff653
JR		 87 /* A VMEXIT is required but not yet emulated */
88 bool exit_required;
89
aad42c64
JR		 90 /* cache for intercepts of the guest */
91 u16 intercept_cr_read;
92 u16 intercept_cr_write;
93 u16 intercept_dr_read;
94 u16 intercept_dr_write;
95 u32 intercept_exceptions;
96 u64 intercept;
97
e6aa9abd
JR		 98};
99
323c3d80
JR		 100#define MSRPM_OFFSETS 16
101static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
102
6c8166a7
AK		 103struct vcpu_svm {
104 struct kvm_vcpu vcpu;
105 struct vmcb *vmcb;
106 unsigned long vmcb_pa;
107 struct svm_cpu_data *svm_data;
108 uint64_t asid_generation;
109 uint64_t sysenter_esp;
110 uint64_t sysenter_eip;
111
112 u64 next_rip;
113
114 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
115 u64 host_gs_base;
6c8166a7
AK		 116
117 u32 *msrpm;
6c8166a7 118
e6aa9abd 119 struct nested_state nested;
6be7d306
JK		 120
121 bool nmi_singlestep;
66b7138f
JK		 122
123 unsigned int3_injected;
124 unsigned long int3_rip;
6c8166a7
AK		 125};
126
455716fa
JR		 127#define MSR_INVALID 0xffffffffU
128
ac72a9b7
JR		 129static struct svm_direct_access_msrs {
130 u32 index; /* Index of the MSR */
131 bool always; /* True if intercept is always on */
132} direct_access_msrs[] = {
133 { .index = MSR_K6_STAR, .always = true },
134 { .index = MSR_IA32_SYSENTER_CS, .always = true },
135#ifdef CONFIG_X86_64
136 { .index = MSR_GS_BASE, .always = true },
137 { .index = MSR_FS_BASE, .always = true },
138 { .index = MSR_KERNEL_GS_BASE, .always = true },
139 { .index = MSR_LSTAR, .always = true },
140 { .index = MSR_CSTAR, .always = true },
141 { .index = MSR_SYSCALL_MASK, .always = true },
142#endif
143 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
144 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
145 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
146 { .index = MSR_IA32_LASTINTTOIP, .always = false },
147 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 148};
149
709ddebf
JR		 150/* enable NPT for AMD64 and X86 with PAE */
151#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
152static bool npt_enabled = true;
153#else
e0231715 154static bool npt_enabled;
709ddebf 155#endif
6c7dac72
JR		 156static int npt = 1;
157
158module_param(npt, int, S_IRUGO);
e3da3acd 159
4b6e4dca 160static int nested = 1;
236de055
AG		 161module_param(nested, int, S_IRUGO);
162
44874f84 163static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 164static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 165
410e4d57 166static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 167static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 168static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 169static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
170 bool has_error_code, u32 error_code);
171
a2fa3e9f
GH		 172static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
173{
fb3f0f51 174 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 175}
176
3d6368ef
AG		 177static inline bool is_nested(struct vcpu_svm *svm)
178{
e6aa9abd 179 return svm->nested.vmcb;
3d6368ef
AG		 180}
181
2af9194d
JR		 182static inline void enable_gif(struct vcpu_svm *svm)
183{
184 svm->vcpu.arch.hflags |= HF_GIF_MASK;
185}
186
187static inline void disable_gif(struct vcpu_svm *svm)
188{
189 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
190}
191
192static inline bool gif_set(struct vcpu_svm *svm)
193{
194 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
195}
196
4866d5e3 197static unsigned long iopm_base;
6aa8b732
AK		 198
199struct kvm_ldttss_desc {
200 u16 limit0;
201 u16 base0;
e0231715
JR		 202 unsigned base1:8, type:5, dpl:2, p:1;
203 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 204 u32 base3;
205 u32 zero1;
206} __attribute__((packed));
207
208struct svm_cpu_data {
209 int cpu;
210
5008fdf5
AK		 211 u64 asid_generation;
212 u32 max_asid;
213 u32 next_asid;
6aa8b732
AK		 214 struct kvm_ldttss_desc *tss_desc;
215
216 struct page *save_area;
217};
218
219static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 220static uint32_t svm_features;
6aa8b732
AK		 221
222struct svm_init_data {
223 int cpu;
224 int r;
225};
226
227static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
228
9d8f549d 229#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 230#define MSRS_RANGE_SIZE 2048
231#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
232
455716fa
JR		 233static u32 svm_msrpm_offset(u32 msr)
234{
235 u32 offset;
236 int i;
237
238 for (i = 0; i < NUM_MSR_MAPS; i++) {
239 if (msr < msrpm_ranges[i] ||
240 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
241 continue;
242
243 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
244 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
245
246 /* Now we have the u8 offset - but need the u32 offset */
247 return offset / 4;
248 }
249
250 /* MSR not in any range */
251 return MSR_INVALID;
252}
253
6aa8b732
AK		 254#define MAX_INST_SIZE 15
255
80b7706e
JR		 256static inline u32 svm_has(u32 feat)
257{
258 return svm_features & feat;
259}
260
6aa8b732
AK		 261static inline void clgi(void)
262{
4ecac3fd 263 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 264}
265
266static inline void stgi(void)
267{
4ecac3fd 268 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 269}
270
271static inline void invlpga(unsigned long addr, u32 asid)
272{
e0231715 273 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 274}
275
6aa8b732
AK		 276static inline void force_new_asid(struct kvm_vcpu *vcpu)
277{
a2fa3e9f 278 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 279}
280
281static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
282{
283 force_new_asid(vcpu);
284}
285
286static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
287{
709ddebf 288 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 289 efer &= ~EFER_LME;
6aa8b732 290
9962d032 291 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 292 vcpu->arch.efer = efer;
6aa8b732
AK		 293}
294
6aa8b732
AK		 295static int is_external_interrupt(u32 info)
296{
297 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
298 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
299}
300
2809f5d2
GC		 301static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
302{
303 struct vcpu_svm *svm = to_svm(vcpu);
304 u32 ret = 0;
305
306 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 307 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 308 return ret & mask;
309}
310
311static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
312{
313 struct vcpu_svm *svm = to_svm(vcpu);
314
315 if (mask == 0)
316 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
317 else
318 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
319
320}
321
6aa8b732
AK		 322static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
323{
a2fa3e9f
GH		 324 struct vcpu_svm *svm = to_svm(vcpu);
325
6bc31bdc
AP		 326 if (svm->vmcb->control.next_rip != 0)
327 svm->next_rip = svm->vmcb->control.next_rip;
328
a2fa3e9f 329 if (!svm->next_rip) {
851ba692 330 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 331 EMULATE_DONE)
332 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 333 return;
334 }
5fdbf976
MT		 335 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
336 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
337 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 338
5fdbf976 339 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 340 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 341}
342
116a4752 343static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 344 bool has_error_code, u32 error_code,
345 bool reinject)
116a4752
JK		 346{
347 struct vcpu_svm *svm = to_svm(vcpu);
348
e0231715
JR		 349 /*
350 * If we are within a nested VM we'd better #VMEXIT and let the guest
351 * handle the exception
352 */
ce7ddec4
JR		 353 if (!reinject &&
354 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 355 return;
356
66b7138f
JK		 357 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
358 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
359
360 /*
361 * For guest debugging where we have to reinject #BP if some
362 * INT3 is guest-owned:
363 * Emulate nRIP by moving RIP forward. Will fail if injection
364 * raises a fault that is not intercepted. Still better than
365 * failing in all cases.
366 */
367 skip_emulated_instruction(&svm->vcpu);
368 rip = kvm_rip_read(&svm->vcpu);
369 svm->int3_rip = rip + svm->vmcb->save.cs.base;
370 svm->int3_injected = rip - old_rip;
371 }
372
116a4752
JK		 373 svm->vmcb->control.event_inj = nr
374 | SVM_EVTINJ_VALID
375 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
376 | SVM_EVTINJ_TYPE_EXEPT;
377 svm->vmcb->control.event_inj_err = error_code;
378}
379
67ec6607
JR		 380static void svm_init_erratum_383(void)
381{
382 u32 low, high;
383 int err;
384 u64 val;
385
386 /* Only Fam10h is affected */
387 if (boot_cpu_data.x86 != 0x10)
388 return;
389
390 /* Use _safe variants to not break nested virtualization */
391 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
392 if (err)
393 return;
394
395 val |= (1ULL << 47);
396
397 low = lower_32_bits(val);
398 high = upper_32_bits(val);
399
400 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
401
402 erratum_383_found = true;
403}
404
6aa8b732
AK		 405static int has_svm(void)
406{
63d1142f 407 const char *msg;
6aa8b732 408
63d1142f 409 if (!cpu_has_svm(&msg)) {
ff81ff10 410 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 411 return 0;
412 }
413
6aa8b732
AK		 414 return 1;
415}
416
417static void svm_hardware_disable(void *garbage)
418{
2c8dceeb 419 cpu_svm_disable();
6aa8b732
AK		 420}
421
10474ae8 422static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 423{
424
0fe1e009 425 struct svm_cpu_data *sd;
6aa8b732 426 uint64_t efer;
89a27f4d 427 struct desc_ptr gdt_descr;
6aa8b732
AK		 428 struct desc_struct *gdt;
429 int me = raw_smp_processor_id();
430
10474ae8
AG		 431 rdmsrl(MSR_EFER, efer);
432 if (efer & EFER_SVME)
433 return -EBUSY;
434
6aa8b732 435 if (!has_svm()) {
e6732a5a
ZA		 436 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
437 me);
10474ae8 438 return -EINVAL;
6aa8b732 439 }
0fe1e009 440 sd = per_cpu(svm_data, me);
6aa8b732 441
0fe1e009 442 if (!sd) {
e6732a5a 443 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 444 me);
10474ae8 445 return -EINVAL;
6aa8b732
AK		 446 }
447
0fe1e009
TH		 448 sd->asid_generation = 1;
449 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
450 sd->next_asid = sd->max_asid + 1;
6aa8b732 451
d6ab1ed4 452 native_store_gdt(&gdt_descr);
89a27f4d 453 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 454 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 455
9962d032 456 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 457
d0316554 458 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 459
67ec6607
JR		 460 svm_init_erratum_383();
461
10474ae8 462 return 0;
6aa8b732
AK		 463}
464
0da1db75
JR		 465static void svm_cpu_uninit(int cpu)
466{
0fe1e009 467 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 468
0fe1e009 469 if (!sd)
0da1db75
JR		 470 return;
471
472 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 473 __free_page(sd->save_area);
474 kfree(sd);
0da1db75
JR		 475}
476
6aa8b732
AK		 477static int svm_cpu_init(int cpu)
478{
0fe1e009 479 struct svm_cpu_data *sd;
6aa8b732
AK		 480 int r;
481
0fe1e009
TH		 482 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
483 if (!sd)
6aa8b732 484 return -ENOMEM;
0fe1e009
TH		 485 sd->cpu = cpu;
486 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 487 r = -ENOMEM;
0fe1e009 488 if (!sd->save_area)
6aa8b732
AK		 489 goto err_1;
490
0fe1e009 491 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 492
493 return 0;
494
495err_1:
0fe1e009 496 kfree(sd);
6aa8b732
AK		 497 return r;
498
499}
500
ac72a9b7
JR		 501static bool valid_msr_intercept(u32 index)
502{
503 int i;
504
505 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
506 if (direct_access_msrs[i].index == index)
507 return true;
508
509 return false;
510}
511
bfc733a7
RR		 512static void set_msr_interception(u32 *msrpm, unsigned msr,
513 int read, int write)
6aa8b732 514{
455716fa
JR		 515 u8 bit_read, bit_write;
516 unsigned long tmp;
517 u32 offset;
6aa8b732 518
ac72a9b7
JR		 519 /*
520 * If this warning triggers extend the direct_access_msrs list at the
521 * beginning of the file
522 */
523 WARN_ON(!valid_msr_intercept(msr));
524
455716fa
JR		 525 offset = svm_msrpm_offset(msr);
526 bit_read = 2 * (msr & 0x0f);
527 bit_write = 2 * (msr & 0x0f) + 1;
528 tmp = msrpm[offset];
529
530 BUG_ON(offset == MSR_INVALID);
531
532 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
533 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
534
535 msrpm[offset] = tmp;
6aa8b732
AK		 536}
537
f65c229c 538static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 539{
540 int i;
541
f65c229c
JR		 542 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
543
ac72a9b7
JR		 544 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
545 if (!direct_access_msrs[i].always)
546 continue;
547
548 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
549 }
f65c229c
JR		 550}
551
323c3d80
JR		 552static void add_msr_offset(u32 offset)
553{
554 int i;
555
556 for (i = 0; i < MSRPM_OFFSETS; ++i) {
557
558 /* Offset already in list? */
559 if (msrpm_offsets[i] == offset)
bfc733a7 560 return;
323c3d80
JR		 561
562 /* Slot used by another offset? */
563 if (msrpm_offsets[i] != MSR_INVALID)
564 continue;
565
566 /* Add offset to list */
567 msrpm_offsets[i] = offset;
568
569 return;
6aa8b732 570 }
323c3d80
JR		 571
572 /*
573 * If this BUG triggers the msrpm_offsets table has an overflow. Just
574 * increase MSRPM_OFFSETS in this case.
575 */
bfc733a7 576 BUG();
6aa8b732
AK		 577}
578
323c3d80 579static void init_msrpm_offsets(void)
f65c229c 580{
323c3d80 581 int i;
f65c229c 582
323c3d80
JR		 583 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
584
585 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
586 u32 offset;
587
588 offset = svm_msrpm_offset(direct_access_msrs[i].index);
589 BUG_ON(offset == MSR_INVALID);
590
591 add_msr_offset(offset);
592 }
f65c229c
JR		 593}
594
24e09cbf
JR		 595static void svm_enable_lbrv(struct vcpu_svm *svm)
596{
597 u32 *msrpm = svm->msrpm;
598
599 svm->vmcb->control.lbr_ctl = 1;
600 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
601 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
602 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
603 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
604}
605
606static void svm_disable_lbrv(struct vcpu_svm *svm)
607{
608 u32 *msrpm = svm->msrpm;
609
610 svm->vmcb->control.lbr_ctl = 0;
611 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
612 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
613 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
614 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
615}
616
6aa8b732
AK		 617static __init int svm_hardware_setup(void)
618{
619 int cpu;
620 struct page *iopm_pages;
f65c229c 621 void *iopm_va;
6aa8b732
AK		 622 int r;
623
6aa8b732
AK		 624 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
625
626 if (!iopm_pages)
627 return -ENOMEM;
c8681339
AL		 628
629 iopm_va = page_address(iopm_pages);
630 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 631 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
632
323c3d80
JR		 633 init_msrpm_offsets();
634
50a37eb4
JR		 635 if (boot_cpu_has(X86_FEATURE_NX))
636 kvm_enable_efer_bits(EFER_NX);
637
1b2fd70c
AG		 638 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
639 kvm_enable_efer_bits(EFER_FFXSR);
640
236de055
AG		 641 if (nested) {
642 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
643 kvm_enable_efer_bits(EFER_SVME);
644 }
645
3230bb47 646 for_each_possible_cpu(cpu) {
6aa8b732
AK		 647 r = svm_cpu_init(cpu);
648 if (r)
f65c229c 649 goto err;
6aa8b732 650 }
33bd6a0b
JR		 651
652 svm_features = cpuid_edx(SVM_CPUID_FUNC);
653
e3da3acd
JR		 654 if (!svm_has(SVM_FEATURE_NPT))
655 npt_enabled = false;
656
6c7dac72
JR		 657 if (npt_enabled && !npt) {
658 printk(KERN_INFO "kvm: Nested Paging disabled\n");
659 npt_enabled = false;
660 }
661
18552672 662 if (npt_enabled) {
e3da3acd 663 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 664 kvm_enable_tdp();
5f4cb662
JR		 665 } else
666 kvm_disable_tdp();
e3da3acd 667
6aa8b732
AK		 668 return 0;
669
f65c229c 670err:
6aa8b732
AK		 671 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
672 iopm_base = 0;
673 return r;
674}
675
676static __exit void svm_hardware_unsetup(void)
677{
0da1db75
JR		 678 int cpu;
679
3230bb47 680 for_each_possible_cpu(cpu)
0da1db75
JR		 681 svm_cpu_uninit(cpu);
682
6aa8b732 683 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 684 iopm_base = 0;
6aa8b732
AK		 685}
686
687static void init_seg(struct vmcb_seg *seg)
688{
689 seg->selector = 0;
690 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 691 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 692 seg->limit = 0xffff;
693 seg->base = 0;
694}
695
696static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
697{
698 seg->selector = 0;
699 seg->attrib = SVM_SELECTOR_P_MASK | type;
700 seg->limit = 0xffff;
701 seg->base = 0;
702}
703
e6101a96 704static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 705{
e6101a96
JR		 706 struct vmcb_control_area *control = &svm->vmcb->control;
707 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 708
bff78274
AK		 709 svm->vcpu.fpu_active = 1;
710
e0231715 711 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 712 INTERCEPT_CR3_MASK |
649d6864 713 INTERCEPT_CR4_MASK;
6aa8b732 714
e0231715 715 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 716 INTERCEPT_CR3_MASK |
80a8119c
AK		 717 INTERCEPT_CR4_MASK |
718 INTERCEPT_CR8_MASK;
6aa8b732 719
e0231715 720 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 721 INTERCEPT_DR1_MASK |
722 INTERCEPT_DR2_MASK |
727f5a23
JK		 723 INTERCEPT_DR3_MASK |
724 INTERCEPT_DR4_MASK |
725 INTERCEPT_DR5_MASK |
726 INTERCEPT_DR6_MASK |
727 INTERCEPT_DR7_MASK;
6aa8b732 728
e0231715 729 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 730 INTERCEPT_DR1_MASK |
731 INTERCEPT_DR2_MASK |
732 INTERCEPT_DR3_MASK |
727f5a23 733 INTERCEPT_DR4_MASK |
6aa8b732 734 INTERCEPT_DR5_MASK |
727f5a23 735 INTERCEPT_DR6_MASK |
6aa8b732
AK		 736 INTERCEPT_DR7_MASK;
737
7aa81cc0 738 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 739 (1 << UD_VECTOR) |
740 (1 << MC_VECTOR);
6aa8b732
AK		 741
742
e0231715 743 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 744 (1ULL << INTERCEPT_NMI) |
0152527b 745 (1ULL << INTERCEPT_SMI) |
d225157b 746 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 747 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 748 (1ULL << INTERCEPT_INVD) |
6aa8b732 749 (1ULL << INTERCEPT_HLT) |
a7052897 750 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 751 (1ULL << INTERCEPT_INVLPGA) |
752 (1ULL << INTERCEPT_IOIO_PROT) |
753 (1ULL << INTERCEPT_MSR_PROT) |
754 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 755 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 756 (1ULL << INTERCEPT_VMRUN) |
757 (1ULL << INTERCEPT_VMMCALL) |
758 (1ULL << INTERCEPT_VMLOAD) |
759 (1ULL << INTERCEPT_VMSAVE) |
760 (1ULL << INTERCEPT_STGI) |
761 (1ULL << INTERCEPT_CLGI) |
916ce236 762 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 763 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 764 (1ULL << INTERCEPT_MONITOR) |
765 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 766
767 control->iopm_base_pa = iopm_base;
f65c229c 768 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 769 control->tsc_offset = 0;
6aa8b732
AK		 770 control->int_ctl = V_INTR_MASKING_MASK;
771
772 init_seg(&save->es);
773 init_seg(&save->ss);
774 init_seg(&save->ds);
775 init_seg(&save->fs);
776 init_seg(&save->gs);
777
778 save->cs.selector = 0xf000;
779 /* Executable/Readable Code Segment */
780 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
781 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
782 save->cs.limit = 0xffff;
d92899a0
AK		 783 /*
784 * cs.base should really be 0xffff0000, but vmx can't handle that, so
785 * be consistent with it.
786 *
787 * Replace when we have real mode working for vmx.
788 */
789 save->cs.base = 0xf0000;
6aa8b732
AK		 790
791 save->gdtr.limit = 0xffff;
792 save->idtr.limit = 0xffff;
793
794 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
795 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
796
9962d032 797 save->efer = EFER_SVME;
d77c26fc 798 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 799 save->dr7 = 0x400;
800 save->rflags = 2;
801 save->rip = 0x0000fff0;
5fdbf976 802 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 803
e0231715
JR		 804 /*
805 * This is the guest-visible cr0 value.
18fa000a 806 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 807 */
18fa000a
EH		 808 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
809 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
810
66aee91a 811 save->cr4 = X86_CR4_PAE;
6aa8b732 812 /* rdx = ?? */
709ddebf
JR		 813
814 if (npt_enabled) {
815 /* Setup VMCB for Nested Paging */
816 control->nested_ctl = 1;
a7052897
MT		 817 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
818 (1ULL << INTERCEPT_INVLPG));
709ddebf 819 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 820 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
821 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 822 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 823 save->cr3 = 0;
824 save->cr4 = 0;
825 }
a79d2f18 826 force_new_asid(&svm->vcpu);
1371d904 827
e6aa9abd 828 svm->nested.vmcb = 0;
2af9194d
JR		 829 svm->vcpu.arch.hflags = 0;
830
565d0998
ML		 831 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
832 control->pause_filter_count = 3000;
833 control->intercept |= (1ULL << INTERCEPT_PAUSE);
834 }
835
2af9194d 836 enable_gif(svm);
6aa8b732
AK		 837}
838
e00c8cf2 839static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 840{
841 struct vcpu_svm *svm = to_svm(vcpu);
842
e6101a96 843 init_vmcb(svm);
70433389 844
c5af89b6 845 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 846 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 847 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
848 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 849 }
5fdbf976
MT		 850 vcpu->arch.regs_avail = ~0;
851 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 852
853 return 0;
04d2cc77
AK		 854}
855
fb3f0f51 856static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 857{
a2fa3e9f 858 struct vcpu_svm *svm;
6aa8b732 859 struct page *page;
f65c229c 860 struct page *msrpm_pages;
b286d5d8 861 struct page *hsave_page;
3d6368ef 862 struct page *nested_msrpm_pages;
fb3f0f51 863 int err;
6aa8b732 864
c16f862d 865 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 866 if (!svm) {
867 err = -ENOMEM;
868 goto out;
869 }
870
871 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
872 if (err)
873 goto free_svm;
874
b7af4043 875 err = -ENOMEM;
6aa8b732 876 page = alloc_page(GFP_KERNEL);
b7af4043 877 if (!page)
fb3f0f51 878 goto uninit;
6aa8b732 879
f65c229c
JR		 880 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
881 if (!msrpm_pages)
b7af4043 882 goto free_page1;
3d6368ef
AG		 883
884 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
885 if (!nested_msrpm_pages)
b7af4043 886 goto free_page2;
f65c229c 887
b286d5d8
AG		 888 hsave_page = alloc_page(GFP_KERNEL);
889 if (!hsave_page)
b7af4043
TY		 890 goto free_page3;
891
e6aa9abd 892 svm->nested.hsave = page_address(hsave_page);
b286d5d8 893
b7af4043
TY		 894 svm->msrpm = page_address(msrpm_pages);
895 svm_vcpu_init_msrpm(svm->msrpm);
896
e6aa9abd 897 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 898 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 899
a2fa3e9f
GH		 900 svm->vmcb = page_address(page);
901 clear_page(svm->vmcb);
902 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
903 svm->asid_generation = 0;
e6101a96 904 init_vmcb(svm);
a2fa3e9f 905
fb3f0f51 906 fx_init(&svm->vcpu);
ad312c7c 907 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 908 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 909 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 910
fb3f0f51 911 return &svm->vcpu;
36241b8c 912
b7af4043
TY		 913free_page3:
914 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
915free_page2:
916 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
917free_page1:
918 __free_page(page);
fb3f0f51
RR		 919uninit:
920 kvm_vcpu_uninit(&svm->vcpu);
921free_svm:
a4770347 922 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 923out:
924 return ERR_PTR(err);
6aa8b732
AK		 925}
926
927static void svm_free_vcpu(struct kvm_vcpu *vcpu)
928{
a2fa3e9f
GH		 929 struct vcpu_svm *svm = to_svm(vcpu);
930
fb3f0f51 931 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 932 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 933 __free_page(virt_to_page(svm->nested.hsave));
934 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 935 kvm_vcpu_uninit(vcpu);
a4770347 936 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 937}
938
15ad7146 939static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 940{
a2fa3e9f 941 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 942 int i;
0cc5064d 943
0cc5064d 944 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 945 u64 delta;
0cc5064d 946
953899b6
JR		 947 if (check_tsc_unstable()) {
948 /*
949 * Make sure that the guest sees a monotonically
950 * increasing TSC.
951 */
952 delta = vcpu->arch.host_tsc - native_read_tsc();
953 svm->vmcb->control.tsc_offset += delta;
954 if (is_nested(svm))
955 svm->nested.hsave->control.tsc_offset += delta;
956 }
0cc5064d 957 vcpu->cpu = cpu;
2f599714 958 kvm_migrate_timers(vcpu);
4b656b12 959 svm->asid_generation = 0;
0cc5064d 960 }
94dfbdb3
AL		 961
962 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 963 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 964}
965
966static void svm_vcpu_put(struct kvm_vcpu *vcpu)
967{
a2fa3e9f 968 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 969 int i;
970
e1beb1d3 971 ++vcpu->stat.host_state_reload;
94dfbdb3 972 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 973 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 974
e935d48e 975 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 976}
977
6aa8b732
AK		 978static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
979{
a2fa3e9f 980 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 981}
982
983static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
984{
a2fa3e9f 985 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 986}
987
6de4f3ad
AK		 988static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
989{
990 switch (reg) {
991 case VCPU_EXREG_PDPTR:
992 BUG_ON(!npt_enabled);
993 load_pdptrs(vcpu, vcpu->arch.cr3);
994 break;
995 default:
996 BUG();
997 }
998}
999
f0b85051
AG		 1000static void svm_set_vintr(struct vcpu_svm *svm)
1001{
1002 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1003}
1004
1005static void svm_clear_vintr(struct vcpu_svm *svm)
1006{
1007 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1008}
1009
6aa8b732
AK		 1010static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1011{
a2fa3e9f 1012 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1013
1014 switch (seg) {
1015 case VCPU_SREG_CS: return &save->cs;
1016 case VCPU_SREG_DS: return &save->ds;
1017 case VCPU_SREG_ES: return &save->es;
1018 case VCPU_SREG_FS: return &save->fs;
1019 case VCPU_SREG_GS: return &save->gs;
1020 case VCPU_SREG_SS: return &save->ss;
1021 case VCPU_SREG_TR: return &save->tr;
1022 case VCPU_SREG_LDTR: return &save->ldtr;
1023 }
1024 BUG();
8b6d44c7 1025 return NULL;
6aa8b732
AK		 1026}
1027
1028static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1029{
1030 struct vmcb_seg *s = svm_seg(vcpu, seg);
1031
1032 return s->base;
1033}
1034
1035static void svm_get_segment(struct kvm_vcpu *vcpu,
1036 struct kvm_segment *var, int seg)
1037{
1038 struct vmcb_seg *s = svm_seg(vcpu, seg);
1039
1040 var->base = s->base;
1041 var->limit = s->limit;
1042 var->selector = s->selector;
1043 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1044 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1045 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1046 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1047 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1048 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1049 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1050 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1051
e0231715
JR		 1052 /*
1053 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1054 * for cross vendor migration purposes by "not present"
1055 */
1056 var->unusable = !var->present || (var->type == 0);
1057
1fbdc7a5
AP		 1058 switch (seg) {
1059 case VCPU_SREG_CS:
1060 /*
1061 * SVM always stores 0 for the 'G' bit in the CS selector in
1062 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1063 * Intel's VMENTRY has a check on the 'G' bit.
1064 */
25022acc 1065 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1066 break;
1067 case VCPU_SREG_TR:
1068 /*
1069 * Work around a bug where the busy flag in the tr selector
1070 * isn't exposed
1071 */
c0d09828 1072 var->type |= 0x2;
1fbdc7a5
AP		 1073 break;
1074 case VCPU_SREG_DS:
1075 case VCPU_SREG_ES:
1076 case VCPU_SREG_FS:
1077 case VCPU_SREG_GS:
1078 /*
1079 * The accessed bit must always be set in the segment
1080 * descriptor cache, although it can be cleared in the
1081 * descriptor, the cached bit always remains at 1. Since
1082 * Intel has a check on this, set it here to support
1083 * cross-vendor migration.
1084 */
1085 if (!var->unusable)
1086 var->type |= 0x1;
1087 break;
b586eb02 1088 case VCPU_SREG_SS:
e0231715
JR		 1089 /*
1090 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1091 * descriptor is left as 1, although the whole segment has
1092 * been made unusable. Clear it here to pass an Intel VMX
1093 * entry check when cross vendor migrating.
1094 */
1095 if (var->unusable)
1096 var->db = 0;
1097 break;
1fbdc7a5 1098 }
6aa8b732
AK		 1099}
1100
2e4d2653
IE		 1101static int svm_get_cpl(struct kvm_vcpu *vcpu)
1102{
1103 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1104
1105 return save->cpl;
1106}
1107
89a27f4d 1108static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1109{
a2fa3e9f
GH		 1110 struct vcpu_svm *svm = to_svm(vcpu);
1111
89a27f4d
GN		 1112 dt->size = svm->vmcb->save.idtr.limit;
1113 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1114}
1115
89a27f4d 1116static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1117{
a2fa3e9f
GH		 1118 struct vcpu_svm *svm = to_svm(vcpu);
1119
89a27f4d
GN		 1120 svm->vmcb->save.idtr.limit = dt->size;
1121 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1122}
1123
89a27f4d 1124static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1125{
a2fa3e9f
GH		 1126 struct vcpu_svm *svm = to_svm(vcpu);
1127
89a27f4d
GN		 1128 dt->size = svm->vmcb->save.gdtr.limit;
1129 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1130}
1131
89a27f4d 1132static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1133{
a2fa3e9f
GH		 1134 struct vcpu_svm *svm = to_svm(vcpu);
1135
89a27f4d
GN		 1136 svm->vmcb->save.gdtr.limit = dt->size;
1137 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1138}
1139
e8467fda
AK		 1140static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1141{
1142}
1143
25c4c276 1144static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1145{
1146}
1147
d225157b
AK		 1148static void update_cr0_intercept(struct vcpu_svm *svm)
1149{
66a562f7 1150 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1151 ulong gcr0 = svm->vcpu.arch.cr0;
1152 u64 *hcr0 = &svm->vmcb->save.cr0;
1153
1154 if (!svm->vcpu.fpu_active)
1155 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1156 else
1157 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1158 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1159
1160
1161 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1162 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1163 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1164 if (is_nested(svm)) {
1165 struct vmcb *hsave = svm->nested.hsave;
1166
1167 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1168 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1169 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1170 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1171 }
d225157b
AK		 1172 } else {
1173 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1174 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1175 if (is_nested(svm)) {
1176 struct vmcb *hsave = svm->nested.hsave;
1177
1178 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1179 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1180 }
d225157b
AK		 1181 }
1182}
1183
6aa8b732
AK		 1184static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1185{
a2fa3e9f
GH		 1186 struct vcpu_svm *svm = to_svm(vcpu);
1187
7f5d8b56
JR		 1188 if (is_nested(svm)) {
1189 /*
1190 * We are here because we run in nested mode, the host kvm
1191 * intercepts cr0 writes but the l1 hypervisor does not.
1192 * But the L1 hypervisor may intercept selective cr0 writes.
1193 * This needs to be checked here.
1194 */
1195 unsigned long old, new;
1196
1197 /* Remove bits that would trigger a real cr0 write intercept */
1198 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1199 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1200
1201 if (old == new) {
1202 /* cr0 write with ts and mp unchanged */
1203 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1204 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1205 return;
1206 }
1207 }
1208
05b3e0c2 1209#ifdef CONFIG_X86_64
f6801dff 1210 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1211 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1212 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1213 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1214 }
1215
d77c26fc 1216 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1217 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1218 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1219 }
1220 }
1221#endif
ad312c7c 1222 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1223
1224 if (!npt_enabled)
1225 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1226
1227 if (!vcpu->fpu_active)
334df50a 1228 cr0 |= X86_CR0_TS;
709ddebf
JR		 1229 /*
1230 * re-enable caching here because the QEMU bios
1231 * does not do it - this results in some delay at
1232 * reboot
1233 */
1234 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1235 svm->vmcb->save.cr0 = cr0;
d225157b 1236 update_cr0_intercept(svm);
6aa8b732
AK		 1237}
1238
1239static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1240{
6394b649 1241 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1242 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1243
1244 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1245 force_new_asid(vcpu);
6394b649 1246
ec077263
JR		 1247 vcpu->arch.cr4 = cr4;
1248 if (!npt_enabled)
1249 cr4 |= X86_CR4_PAE;
6394b649 1250 cr4 |= host_cr4_mce;
ec077263 1251 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1252}
1253
1254static void svm_set_segment(struct kvm_vcpu *vcpu,
1255 struct kvm_segment *var, int seg)
1256{
a2fa3e9f 1257 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1258 struct vmcb_seg *s = svm_seg(vcpu, seg);
1259
1260 s->base = var->base;
1261 s->limit = var->limit;
1262 s->selector = var->selector;
1263 if (var->unusable)
1264 s->attrib = 0;
1265 else {
1266 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1267 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1268 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1269 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1270 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1271 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1272 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1273 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1274 }
1275 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1276 svm->vmcb->save.cpl
1277 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1278 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1279
1280}
1281
44c11430 1282static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1283{
d0bfb940
JK		 1284 struct vcpu_svm *svm = to_svm(vcpu);
1285
d0bfb940
JK		 1286 svm->vmcb->control.intercept_exceptions &=
1287 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1288
6be7d306 1289 if (svm->nmi_singlestep)
44c11430
GN		 1290 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1291
d0bfb940
JK		 1292 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1293 if (vcpu->guest_debug &
1294 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1295 svm->vmcb->control.intercept_exceptions |=
1296 1 << DB_VECTOR;
1297 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1298 svm->vmcb->control.intercept_exceptions |=
1299 1 << BP_VECTOR;
1300 } else
1301 vcpu->guest_debug = 0;
44c11430
GN		 1302}
1303
355be0b9 1304static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1305{
44c11430
GN		 1306 struct vcpu_svm *svm = to_svm(vcpu);
1307
ae675ef0
JK		 1308 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1309 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1310 else
1311 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1312
355be0b9 1313 update_db_intercept(vcpu);
6aa8b732
AK		 1314}
1315
1316static void load_host_msrs(struct kvm_vcpu *vcpu)
1317{
94dfbdb3 1318#ifdef CONFIG_X86_64
a2fa3e9f 1319 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1320#endif
6aa8b732
AK		 1321}
1322
1323static void save_host_msrs(struct kvm_vcpu *vcpu)
1324{
94dfbdb3 1325#ifdef CONFIG_X86_64
a2fa3e9f 1326 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1327#endif
6aa8b732
AK		 1328}
1329
0fe1e009 1330static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1331{
0fe1e009
TH		 1332 if (sd->next_asid > sd->max_asid) {
1333 ++sd->asid_generation;
1334 sd->next_asid = 1;
a2fa3e9f 1335 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1336 }
1337
0fe1e009
TH		 1338 svm->asid_generation = sd->asid_generation;
1339 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1340}
1341
020df079 1342static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1343{
42dbaa5a 1344 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1345
020df079 1346 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1347}
1348
851ba692 1349static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1350{
6aa8b732
AK		 1351 u64 fault_address;
1352 u32 error_code;
6aa8b732 1353
a2fa3e9f
GH		 1354 fault_address = svm->vmcb->control.exit_info_2;
1355 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1356
229456fc 1357 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1358 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1359 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1360 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1361}
1362
851ba692 1363static int db_interception(struct vcpu_svm *svm)
d0bfb940 1364{
851ba692
AK		 1365 struct kvm_run *kvm_run = svm->vcpu.run;
1366
d0bfb940 1367 if (!(svm->vcpu.guest_debug &
44c11430 1368 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1369 !svm->nmi_singlestep) {
d0bfb940
JK		 1370 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1371 return 1;
1372 }
44c11430 1373
6be7d306
JK		 1374 if (svm->nmi_singlestep) {
1375 svm->nmi_singlestep = false;
44c11430
GN		 1376 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1377 svm->vmcb->save.rflags &=
1378 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1379 update_db_intercept(&svm->vcpu);
1380 }
1381
1382 if (svm->vcpu.guest_debug &
e0231715 1383 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1384 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1385 kvm_run->debug.arch.pc =
1386 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1387 kvm_run->debug.arch.exception = DB_VECTOR;
1388 return 0;
1389 }
1390
1391 return 1;
d0bfb940
JK		 1392}
1393
851ba692 1394static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1395{
851ba692
AK		 1396 struct kvm_run *kvm_run = svm->vcpu.run;
1397
d0bfb940
JK		 1398 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1399 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1400 kvm_run->debug.arch.exception = BP_VECTOR;
1401 return 0;
1402}
1403
851ba692 1404static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1405{
1406 int er;
1407
851ba692 1408 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1409 if (er != EMULATE_DONE)
7ee5d940 1410 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1411 return 1;
1412}
1413
6b52d186 1414static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1415{
6b52d186 1416 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1417 u32 excp;
1418
1419 if (is_nested(svm)) {
1420 u32 h_excp, n_excp;
1421
1422 h_excp = svm->nested.hsave->control.intercept_exceptions;
1423 n_excp = svm->nested.intercept_exceptions;
1424 h_excp &= ~(1 << NM_VECTOR);
1425 excp = h_excp | n_excp;
1426 } else {
1427 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1428 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1429 }
1430
1431 svm->vmcb->control.intercept_exceptions = excp;
1432
e756fc62 1433 svm->vcpu.fpu_active = 1;
d225157b 1434 update_cr0_intercept(svm);
6b52d186 1435}
a2fa3e9f 1436
6b52d186
AK		 1437static int nm_interception(struct vcpu_svm *svm)
1438{
1439 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1440 return 1;
7807fa6c
AL		 1441}
1442
67ec6607
JR		 1443static bool is_erratum_383(void)
1444{
1445 int err, i;
1446 u64 value;
1447
1448 if (!erratum_383_found)
1449 return false;
1450
1451 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1452 if (err)
1453 return false;
1454
1455 /* Bit 62 may or may not be set for this mce */
1456 value &= ~(1ULL << 62);
1457
1458 if (value != 0xb600000000010015ULL)
1459 return false;
1460
1461 /* Clear MCi_STATUS registers */
1462 for (i = 0; i < 6; ++i)
1463 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1464
1465 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1466 if (!err) {
1467 u32 low, high;
1468
1469 value &= ~(1ULL << 2);
1470 low = lower_32_bits(value);
1471 high = upper_32_bits(value);
1472
1473 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1474 }
1475
1476 /* Flush tlb to evict multi-match entries */
1477 __flush_tlb_all();
1478
1479 return true;
1480}
1481
fe5913e4 1482static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1483{
67ec6607
JR		 1484 if (is_erratum_383()) {
1485 /*
1486 * Erratum 383 triggered. Guest state is corrupt so kill the
1487 * guest.
1488 */
1489 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1490
1491 set_bit(KVM_REQ_TRIPLE_FAULT, &svm->vcpu.requests);
1492
1493 return;
1494 }
1495
53371b50
JR		 1496 /*
1497 * On an #MC intercept the MCE handler is not called automatically in
1498 * the host. So do it by hand here.
1499 */
1500 asm volatile (
1501 "int $0x12\n");
1502 /* not sure if we ever come back to this point */
1503
fe5913e4
JR		 1504 return;
1505}
1506
1507static int mc_interception(struct vcpu_svm *svm)
1508{
53371b50
JR		 1509 return 1;
1510}
1511
851ba692 1512static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1513{
851ba692
AK		 1514 struct kvm_run *kvm_run = svm->vcpu.run;
1515
46fe4ddd
JR		 1516 /*
1517 * VMCB is undefined after a SHUTDOWN intercept
1518 * so reinitialize it.
1519 */
a2fa3e9f 1520 clear_page(svm->vmcb);
e6101a96 1521 init_vmcb(svm);
46fe4ddd
JR		 1522
1523 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1524 return 0;
1525}
1526
851ba692 1527static int io_interception(struct vcpu_svm *svm)
6aa8b732 1528{
cf8f70bf 1529 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1530 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1531 int size, in, string;
039576c0 1532 unsigned port;
6aa8b732 1533
e756fc62 1534 ++svm->vcpu.stat.io_exits;
e70669ab 1535 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1536 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf
GN		 1537 if (string || in)
1538 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
1539
039576c0
AK		 1540 port = io_info >> 16;
1541 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1542 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1543 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1544
1545 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1546}
1547
851ba692 1548static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1549{
1550 return 1;
1551}
1552
851ba692 1553static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1554{
1555 ++svm->vcpu.stat.irq_exits;
1556 return 1;
1557}
1558
851ba692 1559static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1560{
1561 return 1;
1562}
1563
851ba692 1564static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1565{
5fdbf976 1566 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1567 skip_emulated_instruction(&svm->vcpu);
1568 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1569}
1570
851ba692 1571static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1572{
5fdbf976 1573 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1574 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1575 kvm_emulate_hypercall(&svm->vcpu);
1576 return 1;
02e235bc
AK		 1577}
1578
c0725420
AG		 1579static int nested_svm_check_permissions(struct vcpu_svm *svm)
1580{
f6801dff 1581 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1582 || !is_paging(&svm->vcpu)) {
1583 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1584 return 1;
1585 }
1586
1587 if (svm->vmcb->save.cpl) {
1588 kvm_inject_gp(&svm->vcpu, 0);
1589 return 1;
1590 }
1591
1592 return 0;
1593}
1594
cf74a78b
AG		 1595static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1596 bool has_error_code, u32 error_code)
1597{
b8e88bc8
JR		 1598 int vmexit;
1599
0295ad7d
JR		 1600 if (!is_nested(svm))
1601 return 0;
cf74a78b 1602
0295ad7d
JR		 1603 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1604 svm->vmcb->control.exit_code_hi = 0;
1605 svm->vmcb->control.exit_info_1 = error_code;
1606 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1607
b8e88bc8
JR		 1608 vmexit = nested_svm_intercept(svm);
1609 if (vmexit == NESTED_EXIT_DONE)
1610 svm->nested.exit_required = true;
1611
1612 return vmexit;
cf74a78b
AG		 1613}
1614
8fe54654
JR		 1615/* This function returns true if it is save to enable the irq window */
1616static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1617{
26666957 1618 if (!is_nested(svm))
8fe54654 1619 return true;
cf74a78b 1620
26666957 1621 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1622 return true;
cf74a78b 1623
26666957 1624 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1625 return false;
cf74a78b 1626
197717d5
JR		 1627 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1628 svm->vmcb->control.exit_info_1 = 0;
1629 svm->vmcb->control.exit_info_2 = 0;
26666957 1630
cd3ff653
JR		 1631 if (svm->nested.intercept & 1ULL) {
1632 /*
1633 * The #vmexit can't be emulated here directly because this
1634 * code path runs with irqs and preemtion disabled. A
1635 * #vmexit emulation might sleep. Only signal request for
1636 * the #vmexit here.
1637 */
1638 svm->nested.exit_required = true;
236649de 1639 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1640 return false;
cf74a78b
AG		 1641 }
1642
8fe54654 1643 return true;
cf74a78b
AG		 1644}
1645
887f500c
JR		 1646/* This function returns true if it is save to enable the nmi window */
1647static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1648{
1649 if (!is_nested(svm))
1650 return true;
1651
1652 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1653 return true;
1654
1655 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1656 svm->nested.exit_required = true;
1657
1658 return false;
cf74a78b
AG		 1659}
1660
7597f129 1661static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1662{
1663 struct page *page;
1664
6c3bd3d7
JR		 1665 might_sleep();
1666
34f80cfa 1667 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1668 if (is_error_page(page))
1669 goto error;
1670
7597f129
JR		 1671 *_page = page;
1672
1673 return kmap(page);
34f80cfa
JR		 1674
1675error:
1676 kvm_release_page_clean(page);
1677 kvm_inject_gp(&svm->vcpu, 0);
1678
1679 return NULL;
1680}
1681
7597f129 1682static void nested_svm_unmap(struct page *page)
34f80cfa 1683{
7597f129 1684 kunmap(page);
34f80cfa
JR		 1685 kvm_release_page_dirty(page);
1686}
34f80cfa 1687
ce2ac085
JR		 1688static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1689{
1690 unsigned port;
1691 u8 val, bit;
1692 u64 gpa;
34f80cfa 1693
ce2ac085
JR		 1694 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1695 return NESTED_EXIT_HOST;
34f80cfa 1696
ce2ac085
JR		 1697 port = svm->vmcb->control.exit_info_1 >> 16;
1698 gpa = svm->nested.vmcb_iopm + (port / 8);
1699 bit = port % 8;
1700 val = 0;
1701
1702 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1703 val &= (1 << bit);
1704
1705 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1706}
1707
d2477826 1708static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1709{
0d6b3537
JR		 1710 u32 offset, msr, value;
1711 int write, mask;
4c2161ae 1712
3d62d9aa 1713 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1714 return NESTED_EXIT_HOST;
3d62d9aa 1715
0d6b3537
JR		 1716 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1717 offset = svm_msrpm_offset(msr);
1718 write = svm->vmcb->control.exit_info_1 & 1;
1719 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1720
0d6b3537
JR		 1721 if (offset == MSR_INVALID)
1722 return NESTED_EXIT_DONE;
4c2161ae 1723
0d6b3537
JR		 1724 /* Offset is in 32 bit units but need in 8 bit units */
1725 offset *= 4;
4c2161ae 1726
0d6b3537
JR		 1727 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1728 return NESTED_EXIT_DONE;
3d62d9aa 1729
0d6b3537 1730 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1731}
1732
410e4d57 1733static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1734{
cf74a78b 1735 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1736
410e4d57
JR		 1737 switch (exit_code) {
1738 case SVM_EXIT_INTR:
1739 case SVM_EXIT_NMI:
ff47a49b 1740 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1741 return NESTED_EXIT_HOST;
410e4d57 1742 case SVM_EXIT_NPF:
e0231715 1743 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1744 if (npt_enabled)
1745 return NESTED_EXIT_HOST;
1746 break;
410e4d57 1747 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1748 /* When we're shadowing, trap PFs */
410e4d57
JR		 1749 if (!npt_enabled)
1750 return NESTED_EXIT_HOST;
1751 break;
66a562f7
JR		 1752 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1753 nm_interception(svm);
1754 break;
410e4d57
JR		 1755 default:
1756 break;
cf74a78b
AG		 1757 }
1758
410e4d57
JR		 1759 return NESTED_EXIT_CONTINUE;
1760}
1761
1762/*
1763 * If this function returns true, this #vmexit was already handled
1764 */
b8e88bc8 1765static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1766{
1767 u32 exit_code = svm->vmcb->control.exit_code;
1768 int vmexit = NESTED_EXIT_HOST;
1769
cf74a78b 1770 switch (exit_code) {
9c4e40b9 1771 case SVM_EXIT_MSR:
3d62d9aa 1772 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1773 break;
ce2ac085
JR		 1774 case SVM_EXIT_IOIO:
1775 vmexit = nested_svm_intercept_ioio(svm);
1776 break;
cf74a78b
AG		 1777 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1778 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1779 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1780 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1781 break;
1782 }
1783 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1784 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1785 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1786 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1787 break;
1788 }
1789 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1790 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1791 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1792 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1793 break;
1794 }
1795 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1796 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1797 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1798 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1799 break;
1800 }
1801 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1802 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1803 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1804 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1805 break;
1806 }
228070b1
JR		 1807 case SVM_EXIT_ERR: {
1808 vmexit = NESTED_EXIT_DONE;
1809 break;
1810 }
cf74a78b
AG		 1811 default: {
1812 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1813 if (svm->nested.intercept & exit_bits)
410e4d57 1814 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1815 }
1816 }
1817
b8e88bc8
JR		 1818 return vmexit;
1819}
1820
1821static int nested_svm_exit_handled(struct vcpu_svm *svm)
1822{
1823 int vmexit;
1824
1825 vmexit = nested_svm_intercept(svm);
1826
1827 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1828 nested_svm_vmexit(svm);
9c4e40b9
JR		 1829
1830 return vmexit;
cf74a78b
AG		 1831}
1832
0460a979
JR		 1833static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1834{
1835 struct vmcb_control_area *dst = &dst_vmcb->control;
1836 struct vmcb_control_area *from = &from_vmcb->control;
1837
1838 dst->intercept_cr_read = from->intercept_cr_read;
1839 dst->intercept_cr_write = from->intercept_cr_write;
1840 dst->intercept_dr_read = from->intercept_dr_read;
1841 dst->intercept_dr_write = from->intercept_dr_write;
1842 dst->intercept_exceptions = from->intercept_exceptions;
1843 dst->intercept = from->intercept;
1844 dst->iopm_base_pa = from->iopm_base_pa;
1845 dst->msrpm_base_pa = from->msrpm_base_pa;
1846 dst->tsc_offset = from->tsc_offset;
1847 dst->asid = from->asid;
1848 dst->tlb_ctl = from->tlb_ctl;
1849 dst->int_ctl = from->int_ctl;
1850 dst->int_vector = from->int_vector;
1851 dst->int_state = from->int_state;
1852 dst->exit_code = from->exit_code;
1853 dst->exit_code_hi = from->exit_code_hi;
1854 dst->exit_info_1 = from->exit_info_1;
1855 dst->exit_info_2 = from->exit_info_2;
1856 dst->exit_int_info = from->exit_int_info;
1857 dst->exit_int_info_err = from->exit_int_info_err;
1858 dst->nested_ctl = from->nested_ctl;
1859 dst->event_inj = from->event_inj;
1860 dst->event_inj_err = from->event_inj_err;
1861 dst->nested_cr3 = from->nested_cr3;
1862 dst->lbr_ctl = from->lbr_ctl;
1863}
1864
34f80cfa 1865static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1866{
34f80cfa 1867 struct vmcb *nested_vmcb;
e6aa9abd 1868 struct vmcb *hsave = svm->nested.hsave;
33740e40 1869 struct vmcb *vmcb = svm->vmcb;
7597f129 1870 struct page *page;
cf74a78b 1871
17897f36
JR		 1872 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1873 vmcb->control.exit_info_1,
1874 vmcb->control.exit_info_2,
1875 vmcb->control.exit_int_info,
1876 vmcb->control.exit_int_info_err);
1877
7597f129 1878 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1879 if (!nested_vmcb)
1880 return 1;
1881
06fc7772
JR		 1882 /* Exit nested SVM mode */
1883 svm->nested.vmcb = 0;
1884
cf74a78b 1885 /* Give the current vmcb to the guest */
33740e40
JR		 1886 disable_gif(svm);
1887
1888 nested_vmcb->save.es = vmcb->save.es;
1889 nested_vmcb->save.cs = vmcb->save.cs;
1890 nested_vmcb->save.ss = vmcb->save.ss;
1891 nested_vmcb->save.ds = vmcb->save.ds;
1892 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1893 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1894 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 1895 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1896 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1897 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1898 nested_vmcb->save.rflags = vmcb->save.rflags;
1899 nested_vmcb->save.rip = vmcb->save.rip;
1900 nested_vmcb->save.rsp = vmcb->save.rsp;
1901 nested_vmcb->save.rax = vmcb->save.rax;
1902 nested_vmcb->save.dr7 = vmcb->save.dr7;
1903 nested_vmcb->save.dr6 = vmcb->save.dr6;
1904 nested_vmcb->save.cpl = vmcb->save.cpl;
1905
1906 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1907 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1908 nested_vmcb->control.int_state = vmcb->control.int_state;
1909 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1910 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1911 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1912 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1913 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1914 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1915
1916 /*
1917 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1918 * to make sure that we do not lose injected events. So check event_inj
1919 * here and copy it to exit_int_info if it is valid.
1920 * Exit_int_info and event_inj can't be both valid because the case
1921 * below only happens on a VMRUN instruction intercept which has
1922 * no valid exit_int_info set.
1923 */
1924 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1925 struct vmcb_control_area *nc = &nested_vmcb->control;
1926
1927 nc->exit_int_info = vmcb->control.event_inj;
1928 nc->exit_int_info_err = vmcb->control.event_inj_err;
1929 }
1930
33740e40
JR		 1931 nested_vmcb->control.tlb_ctl = 0;
1932 nested_vmcb->control.event_inj = 0;
1933 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1934
1935 /* We always set V_INTR_MASKING and remember the old value in hflags */
1936 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1937 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1938
cf74a78b 1939 /* Restore the original control entries */
0460a979 1940 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1941
219b65dc
AG		 1942 kvm_clear_exception_queue(&svm->vcpu);
1943 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1944
1945 /* Restore selected save entries */
1946 svm->vmcb->save.es = hsave->save.es;
1947 svm->vmcb->save.cs = hsave->save.cs;
1948 svm->vmcb->save.ss = hsave->save.ss;
1949 svm->vmcb->save.ds = hsave->save.ds;
1950 svm->vmcb->save.gdtr = hsave->save.gdtr;
1951 svm->vmcb->save.idtr = hsave->save.idtr;
1952 svm->vmcb->save.rflags = hsave->save.rflags;
1953 svm_set_efer(&svm->vcpu, hsave->save.efer);
1954 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1955 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1956 if (npt_enabled) {
1957 svm->vmcb->save.cr3 = hsave->save.cr3;
1958 svm->vcpu.arch.cr3 = hsave->save.cr3;
1959 } else {
1960 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1961 }
1962 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1963 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1964 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1965 svm->vmcb->save.dr7 = 0;
1966 svm->vmcb->save.cpl = 0;
1967 svm->vmcb->control.exit_int_info = 0;
1968
7597f129 1969 nested_svm_unmap(page);
cf74a78b
AG		 1970
1971 kvm_mmu_reset_context(&svm->vcpu);
1972 kvm_mmu_load(&svm->vcpu);
1973
1974 return 0;
1975}
3d6368ef 1976
9738b2c9 1977static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1978{
323c3d80
JR		 1979 /*
1980 * This function merges the msr permission bitmaps of kvm and the
1981 * nested vmcb. It is omptimized in that it only merges the parts where
1982 * the kvm msr permission bitmap may contain zero bits
1983 */
3d6368ef 1984 int i;
9738b2c9 1985
323c3d80
JR		 1986 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1987 return true;
9738b2c9 1988
323c3d80
JR		 1989 for (i = 0; i < MSRPM_OFFSETS; i++) {
1990 u32 value, p;
1991 u64 offset;
9738b2c9 1992
323c3d80
JR		 1993 if (msrpm_offsets[i] == 0xffffffff)
1994 break;
3d6368ef 1995
0d6b3537
JR		 1996 p = msrpm_offsets[i];
1997 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 1998
1999 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2000 return false;
2001
2002 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2003 }
3d6368ef 2004
323c3d80 2005 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2006
2007 return true;
3d6368ef
AG		 2008}
2009
9738b2c9 2010static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2011{
9738b2c9 2012 struct vmcb *nested_vmcb;
e6aa9abd 2013 struct vmcb *hsave = svm->nested.hsave;
defbba56 2014 struct vmcb *vmcb = svm->vmcb;
7597f129 2015 struct page *page;
06fc7772 2016 u64 vmcb_gpa;
3d6368ef 2017
06fc7772 2018 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2019
7597f129 2020 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2021 if (!nested_vmcb)
2022 return false;
2023
ecf1405d 2024 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
0ac406de
JR		 2025 nested_vmcb->save.rip,
2026 nested_vmcb->control.int_ctl,
2027 nested_vmcb->control.event_inj,
2028 nested_vmcb->control.nested_ctl);
2029
2e554e8d
JR		 2030 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2031 nested_vmcb->control.intercept_cr_write,
2032 nested_vmcb->control.intercept_exceptions,
2033 nested_vmcb->control.intercept);
2034
3d6368ef 2035 /* Clear internal status */
219b65dc
AG		 2036 kvm_clear_exception_queue(&svm->vcpu);
2037 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2038
e0231715
JR		 2039 /*
2040 * Save the old vmcb, so we don't need to pick what we save, but can
2041 * restore everything when a VMEXIT occurs
2042 */
defbba56
JR		 2043 hsave->save.es = vmcb->save.es;
2044 hsave->save.cs = vmcb->save.cs;
2045 hsave->save.ss = vmcb->save.ss;
2046 hsave->save.ds = vmcb->save.ds;
2047 hsave->save.gdtr = vmcb->save.gdtr;
2048 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2049 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2050 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2051 hsave->save.cr4 = svm->vcpu.arch.cr4;
2052 hsave->save.rflags = vmcb->save.rflags;
2053 hsave->save.rip = svm->next_rip;
2054 hsave->save.rsp = vmcb->save.rsp;
2055 hsave->save.rax = vmcb->save.rax;
2056 if (npt_enabled)
2057 hsave->save.cr3 = vmcb->save.cr3;
2058 else
2059 hsave->save.cr3 = svm->vcpu.arch.cr3;
2060
0460a979 2061 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2062
2063 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2064 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2065 else
2066 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2067
2068 /* Load the nested guest state */
2069 svm->vmcb->save.es = nested_vmcb->save.es;
2070 svm->vmcb->save.cs = nested_vmcb->save.cs;
2071 svm->vmcb->save.ss = nested_vmcb->save.ss;
2072 svm->vmcb->save.ds = nested_vmcb->save.ds;
2073 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2074 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2075 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2076 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2077 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2078 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2079 if (npt_enabled) {
2080 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2081 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2082 } else
3d6368ef 2083 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2084
2085 /* Guest paging mode is active - reset mmu */
2086 kvm_mmu_reset_context(&svm->vcpu);
2087
defbba56 2088 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2089 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2090 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2091 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2092
3d6368ef
AG		 2093 /* In case we don't even reach vcpu_run, the fields are not updated */
2094 svm->vmcb->save.rax = nested_vmcb->save.rax;
2095 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2096 svm->vmcb->save.rip = nested_vmcb->save.rip;
2097 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2098 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2099 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2100
f7138538 2101 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2102 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2103
aad42c64
JR		 2104 /* cache intercepts */
2105 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2106 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2107 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2108 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2109 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2110 svm->nested.intercept = nested_vmcb->control.intercept;
2111
3d6368ef 2112 force_new_asid(&svm->vcpu);
3d6368ef 2113 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2114 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2115 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2116 else
2117 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2118
88ab24ad
JR		 2119 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2120 /* We only want the cr8 intercept bits of the guest */
2121 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2122 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2123 }
2124
0d945bd9
JR		 2125 /* We don't want to see VMMCALLs from a nested guest */
2126 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2127
e0231715
JR		 2128 /*
2129 * We don't want a nested guest to be more powerful than the guest, so
2130 * all intercepts are ORed
2131 */
88ab24ad
JR		 2132 svm->vmcb->control.intercept_cr_read |=
2133 nested_vmcb->control.intercept_cr_read;
2134 svm->vmcb->control.intercept_cr_write |=
2135 nested_vmcb->control.intercept_cr_write;
2136 svm->vmcb->control.intercept_dr_read |=
2137 nested_vmcb->control.intercept_dr_read;
2138 svm->vmcb->control.intercept_dr_write |=
2139 nested_vmcb->control.intercept_dr_write;
2140 svm->vmcb->control.intercept_exceptions |=
2141 nested_vmcb->control.intercept_exceptions;
2142
2143 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2144
2145 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2146 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2147 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2148 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2149 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2150 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2151
7597f129 2152 nested_svm_unmap(page);
9738b2c9 2153
06fc7772
JR		 2154 /* nested_vmcb is our indicator if nested SVM is activated */
2155 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2156
2af9194d 2157 enable_gif(svm);
3d6368ef 2158
9738b2c9 2159 return true;
3d6368ef
AG		 2160}
2161
9966bf68 2162static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2163{
2164 to_vmcb->save.fs = from_vmcb->save.fs;
2165 to_vmcb->save.gs = from_vmcb->save.gs;
2166 to_vmcb->save.tr = from_vmcb->save.tr;
2167 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2168 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2169 to_vmcb->save.star = from_vmcb->save.star;
2170 to_vmcb->save.lstar = from_vmcb->save.lstar;
2171 to_vmcb->save.cstar = from_vmcb->save.cstar;
2172 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2173 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2174 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2175 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2176}
2177
851ba692 2178static int vmload_interception(struct vcpu_svm *svm)
5542675b 2179{
9966bf68 2180 struct vmcb *nested_vmcb;
7597f129 2181 struct page *page;
9966bf68 2182
5542675b
AG		 2183 if (nested_svm_check_permissions(svm))
2184 return 1;
2185
2186 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2187 skip_emulated_instruction(&svm->vcpu);
2188
7597f129 2189 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2190 if (!nested_vmcb)
2191 return 1;
2192
2193 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2194 nested_svm_unmap(page);
5542675b
AG		 2195
2196 return 1;
2197}
2198
851ba692 2199static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2200{
9966bf68 2201 struct vmcb *nested_vmcb;
7597f129 2202 struct page *page;
9966bf68 2203
5542675b
AG		 2204 if (nested_svm_check_permissions(svm))
2205 return 1;
2206
2207 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2208 skip_emulated_instruction(&svm->vcpu);
2209
7597f129 2210 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2211 if (!nested_vmcb)
2212 return 1;
2213
2214 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2215 nested_svm_unmap(page);
5542675b
AG		 2216
2217 return 1;
2218}
2219
851ba692 2220static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2221{
3d6368ef
AG		 2222 if (nested_svm_check_permissions(svm))
2223 return 1;
2224
2225 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2226 skip_emulated_instruction(&svm->vcpu);
2227
9738b2c9 2228 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2229 return 1;
2230
9738b2c9 2231 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2232 goto failed;
2233
2234 return 1;
2235
2236failed:
2237
2238 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2239 svm->vmcb->control.exit_code_hi = 0;
2240 svm->vmcb->control.exit_info_1 = 0;
2241 svm->vmcb->control.exit_info_2 = 0;
2242
2243 nested_svm_vmexit(svm);
3d6368ef
AG		 2244
2245 return 1;
2246}
2247
851ba692 2248static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2249{
2250 if (nested_svm_check_permissions(svm))
2251 return 1;
2252
2253 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2254 skip_emulated_instruction(&svm->vcpu);
2255
2af9194d 2256 enable_gif(svm);
1371d904
AG		 2257
2258 return 1;
2259}
2260
851ba692 2261static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2262{
2263 if (nested_svm_check_permissions(svm))
2264 return 1;
2265
2266 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2267 skip_emulated_instruction(&svm->vcpu);
2268
2af9194d 2269 disable_gif(svm);
1371d904
AG		 2270
2271 /* After a CLGI no interrupts should come */
2272 svm_clear_vintr(svm);
2273 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2274
2275 return 1;
2276}
2277
851ba692 2278static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2279{
2280 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2281
ec1ff790
JR		 2282 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2283 vcpu->arch.regs[VCPU_REGS_RAX]);
2284
ff092385
AG		 2285 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2286 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2287
2288 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2289 skip_emulated_instruction(&svm->vcpu);
2290 return 1;
2291}
2292
532a46b9
JR		 2293static int skinit_interception(struct vcpu_svm *svm)
2294{
2295 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2296
2297 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2298 return 1;
2299}
2300
851ba692 2301static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2302{
7ee5d940 2303 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2304 return 1;
2305}
2306
851ba692 2307static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2308{
37817f29 2309 u16 tss_selector;
64a7ec06
GN		 2310 int reason;
2311 int int_type = svm->vmcb->control.exit_int_info &
2312 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2313 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2314 uint32_t type =
2315 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2316 uint32_t idt_v =
2317 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2318 bool has_error_code = false;
2319 u32 error_code = 0;
37817f29
IE		 2320
2321 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2322
37817f29
IE		 2323 if (svm->vmcb->control.exit_info_2 &
2324 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2325 reason = TASK_SWITCH_IRET;
2326 else if (svm->vmcb->control.exit_info_2 &
2327 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2328 reason = TASK_SWITCH_JMP;
fe8e7f83 2329 else if (idt_v)
64a7ec06
GN		 2330 reason = TASK_SWITCH_GATE;
2331 else
2332 reason = TASK_SWITCH_CALL;
2333
fe8e7f83
GN		 2334 if (reason == TASK_SWITCH_GATE) {
2335 switch (type) {
2336 case SVM_EXITINTINFO_TYPE_NMI:
2337 svm->vcpu.arch.nmi_injected = false;
2338 break;
2339 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2340 if (svm->vmcb->control.exit_info_2 &
2341 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2342 has_error_code = true;
2343 error_code =
2344 (u32)svm->vmcb->control.exit_info_2;
2345 }
fe8e7f83
GN		 2346 kvm_clear_exception_queue(&svm->vcpu);
2347 break;
2348 case SVM_EXITINTINFO_TYPE_INTR:
2349 kvm_clear_interrupt_queue(&svm->vcpu);
2350 break;
2351 default:
2352 break;
2353 }
2354 }
64a7ec06 2355
8317c298
GN		 2356 if (reason != TASK_SWITCH_GATE ||
2357 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2358 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2359 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2360 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2361
acb54517
GN		 2362 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2363 has_error_code, error_code) == EMULATE_FAIL) {
2364 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2365 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2366 svm->vcpu.run->internal.ndata = 0;
2367 return 0;
2368 }
2369 return 1;
6aa8b732
AK		 2370}
2371
851ba692 2372static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2373{
5fdbf976 2374 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2375 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2376 return 1;
6aa8b732
AK		 2377}
2378
851ba692 2379static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2380{
2381 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2382 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2383 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2384 return 1;
2385}
2386
851ba692 2387static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2388{
851ba692 2389 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2390 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2391 return 1;
2392}
2393
851ba692 2394static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2395{
851ba692 2396 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2397 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2398 return 1;
2399}
2400
851ba692 2401static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2402{
851ba692
AK		 2403 struct kvm_run *kvm_run = svm->vcpu.run;
2404
0a5fff19
GN		 2405 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2406 /* instruction emulation calls kvm_set_cr8() */
851ba692 2407 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2408 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2409 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2410 return 1;
95ba8273 2411 }
0a5fff19
GN		 2412 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2413 return 1;
1d075434
JR		 2414 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2415 return 0;
2416}
2417
6aa8b732
AK		 2418static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2419{
a2fa3e9f
GH		 2420 struct vcpu_svm *svm = to_svm(vcpu);
2421
6aa8b732 2422 switch (ecx) {
af24a4e4 2423 case MSR_IA32_TSC: {
20824f30 2424 u64 tsc_offset;
6aa8b732 2425
20824f30
JR		 2426 if (is_nested(svm))
2427 tsc_offset = svm->nested.hsave->control.tsc_offset;
2428 else
2429 tsc_offset = svm->vmcb->control.tsc_offset;
2430
2431 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2432 break;
2433 }
0e859cac 2434 case MSR_K6_STAR:
a2fa3e9f 2435 *data = svm->vmcb->save.star;
6aa8b732 2436 break;
0e859cac 2437#ifdef CONFIG_X86_64
6aa8b732 2438 case MSR_LSTAR:
a2fa3e9f 2439 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2440 break;
2441 case MSR_CSTAR:
a2fa3e9f 2442 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2443 break;
2444 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2445 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2446 break;
2447 case MSR_SYSCALL_MASK:
a2fa3e9f 2448 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2449 break;
2450#endif
2451 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2452 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2453 break;
2454 case MSR_IA32_SYSENTER_EIP:
017cb99e 2455 *data = svm->sysenter_eip;
6aa8b732
AK		 2456 break;
2457 case MSR_IA32_SYSENTER_ESP:
017cb99e 2458 *data = svm->sysenter_esp;
6aa8b732 2459 break;
e0231715
JR		 2460 /*
2461 * Nobody will change the following 5 values in the VMCB so we can
2462 * safely return them on rdmsr. They will always be 0 until LBRV is
2463 * implemented.
2464 */
a2938c80
JR		 2465 case MSR_IA32_DEBUGCTLMSR:
2466 *data = svm->vmcb->save.dbgctl;
2467 break;
2468 case MSR_IA32_LASTBRANCHFROMIP:
2469 *data = svm->vmcb->save.br_from;
2470 break;
2471 case MSR_IA32_LASTBRANCHTOIP:
2472 *data = svm->vmcb->save.br_to;
2473 break;
2474 case MSR_IA32_LASTINTFROMIP:
2475 *data = svm->vmcb->save.last_excp_from;
2476 break;
2477 case MSR_IA32_LASTINTTOIP:
2478 *data = svm->vmcb->save.last_excp_to;
2479 break;
b286d5d8 2480 case MSR_VM_HSAVE_PA:
e6aa9abd 2481 *data = svm->nested.hsave_msr;
b286d5d8 2482 break;
eb6f302e 2483 case MSR_VM_CR:
4a810181 2484 *data = svm->nested.vm_cr_msr;
eb6f302e 2485 break;
c8a73f18
AG		 2486 case MSR_IA32_UCODE_REV:
2487 *data = 0x01000065;
2488 break;
6aa8b732 2489 default:
3bab1f5d 2490 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2491 }
2492 return 0;
2493}
2494
851ba692 2495static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2496{
ad312c7c 2497 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2498 u64 data;
2499
59200273
AK		 2500 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2501 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2502 kvm_inject_gp(&svm->vcpu, 0);
59200273 2503 } else {
229456fc 2504 trace_kvm_msr_read(ecx, data);
af9ca2d7 2505
5fdbf976 2506 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2507 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2508 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2509 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2510 }
2511 return 1;
2512}
2513
4a810181
JR		 2514static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2515{
2516 struct vcpu_svm *svm = to_svm(vcpu);
2517 int svm_dis, chg_mask;
2518
2519 if (data & ~SVM_VM_CR_VALID_MASK)
2520 return 1;
2521
2522 chg_mask = SVM_VM_CR_VALID_MASK;
2523
2524 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2525 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2526
2527 svm->nested.vm_cr_msr &= ~chg_mask;
2528 svm->nested.vm_cr_msr |= (data & chg_mask);
2529
2530 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2531
2532 /* check for svm_disable while efer.svme is set */
2533 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2534 return 1;
2535
2536 return 0;
2537}
2538
6aa8b732
AK		 2539static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2540{
a2fa3e9f
GH		 2541 struct vcpu_svm *svm = to_svm(vcpu);
2542
6aa8b732 2543 switch (ecx) {
af24a4e4 2544 case MSR_IA32_TSC: {
20824f30
JR		 2545 u64 tsc_offset = data - native_read_tsc();
2546 u64 g_tsc_offset = 0;
2547
2548 if (is_nested(svm)) {
2549 g_tsc_offset = svm->vmcb->control.tsc_offset -
2550 svm->nested.hsave->control.tsc_offset;
2551 svm->nested.hsave->control.tsc_offset = tsc_offset;
2552 }
2553
2554 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2555
6aa8b732
AK		 2556 break;
2557 }
0e859cac 2558 case MSR_K6_STAR:
a2fa3e9f 2559 svm->vmcb->save.star = data;
6aa8b732 2560 break;
49b14f24 2561#ifdef CONFIG_X86_64
6aa8b732 2562 case MSR_LSTAR:
a2fa3e9f 2563 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2564 break;
2565 case MSR_CSTAR:
a2fa3e9f 2566 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2567 break;
2568 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2569 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2570 break;
2571 case MSR_SYSCALL_MASK:
a2fa3e9f 2572 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2573 break;
2574#endif
2575 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2576 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2577 break;
2578 case MSR_IA32_SYSENTER_EIP:
017cb99e 2579 svm->sysenter_eip = data;
a2fa3e9f 2580 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2581 break;
2582 case MSR_IA32_SYSENTER_ESP:
017cb99e 2583 svm->sysenter_esp = data;
a2fa3e9f 2584 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2585 break;
a2938c80 2586 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2587 if (!svm_has(SVM_FEATURE_LBRV)) {
2588 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2589 __func__, data);
24e09cbf
JR		 2590 break;
2591 }
2592 if (data & DEBUGCTL_RESERVED_BITS)
2593 return 1;
2594
2595 svm->vmcb->save.dbgctl = data;
2596 if (data & (1ULL<<0))
2597 svm_enable_lbrv(svm);
2598 else
2599 svm_disable_lbrv(svm);
a2938c80 2600 break;
b286d5d8 2601 case MSR_VM_HSAVE_PA:
e6aa9abd 2602 svm->nested.hsave_msr = data;
62b9abaa 2603 break;
3c5d0a44 2604 case MSR_VM_CR:
4a810181 2605 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2606 case MSR_VM_IGNNE:
3c5d0a44
AG		 2607 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2608 break;
6aa8b732 2609 default:
3bab1f5d 2610 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2611 }
2612 return 0;
2613}
2614
851ba692 2615static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2616{
ad312c7c 2617 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2618 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2619 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2620
af9ca2d7 2621
5fdbf976 2622 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2623 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2624 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2625 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2626 } else {
2627 trace_kvm_msr_write(ecx, data);
e756fc62 2628 skip_emulated_instruction(&svm->vcpu);
59200273 2629 }
6aa8b732
AK		 2630 return 1;
2631}
2632
851ba692 2633static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2634{
e756fc62 2635 if (svm->vmcb->control.exit_info_1)
851ba692 2636 return wrmsr_interception(svm);
6aa8b732 2637 else
851ba692 2638 return rdmsr_interception(svm);
6aa8b732
AK		 2639}
2640
851ba692 2641static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2642{
851ba692
AK		 2643 struct kvm_run *kvm_run = svm->vcpu.run;
2644
f0b85051 2645 svm_clear_vintr(svm);
85f455f7 2646 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2647 /*
2648 * If the user space waits to inject interrupts, exit as soon as
2649 * possible
2650 */
8061823a
GN		 2651 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2652 kvm_run->request_interrupt_window &&
2653 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2654 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2655 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2656 return 0;
2657 }
2658
2659 return 1;
2660}
2661
565d0998
ML		 2662static int pause_interception(struct vcpu_svm *svm)
2663{
2664 kvm_vcpu_on_spin(&(svm->vcpu));
2665 return 1;
2666}
2667
851ba692 2668static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2669 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2670 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2671 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2672 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2673 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2674 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2675 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2676 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2677 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2678 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2679 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2680 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2681 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2682 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2683 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2684 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2685 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2686 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2687 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2688 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2689 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2690 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2691 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2692 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2693 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2694 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2695 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2696 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2697 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2698 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2699 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2700 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2701 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2702 [SVM_EXIT_SMI] = nop_on_interception,
2703 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2704 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2705 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2706 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2707 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2708 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2709 [SVM_EXIT_HLT] = halt_interception,
a7052897 2710 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2711 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2712 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2713 [SVM_EXIT_MSR] = msr_interception,
2714 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2715 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2716 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2717 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2718 [SVM_EXIT_VMLOAD] = vmload_interception,
2719 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2720 [SVM_EXIT_STGI] = stgi_interception,
2721 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2722 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2723 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2724 [SVM_EXIT_MONITOR] = invalid_op_interception,
2725 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2726 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2727};
2728
3f10c846
JR		 2729void dump_vmcb(struct kvm_vcpu *vcpu)
2730{
2731 struct vcpu_svm *svm = to_svm(vcpu);
2732 struct vmcb_control_area *control = &svm->vmcb->control;
2733 struct vmcb_save_area *save = &svm->vmcb->save;
2734
2735 pr_err("VMCB Control Area:\n");
2736 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2737 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2738 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2739 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2740 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2741 pr_err("intercepts: %016llx\n", control->intercept);
2742 pr_err("pause filter count: %d\n", control->pause_filter_count);
2743 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2744 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2745 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2746 pr_err("asid: %d\n", control->asid);
2747 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2748 pr_err("int_ctl: %08x\n", control->int_ctl);
2749 pr_err("int_vector: %08x\n", control->int_vector);
2750 pr_err("int_state: %08x\n", control->int_state);
2751 pr_err("exit_code: %08x\n", control->exit_code);
2752 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2753 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2754 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2755 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2756 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2757 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2758 pr_err("event_inj: %08x\n", control->event_inj);
2759 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2760 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2761 pr_err("next_rip: %016llx\n", control->next_rip);
2762 pr_err("VMCB State Save Area:\n");
2763 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2764 save->es.selector, save->es.attrib,
2765 save->es.limit, save->es.base);
2766 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2767 save->cs.selector, save->cs.attrib,
2768 save->cs.limit, save->cs.base);
2769 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2770 save->ss.selector, save->ss.attrib,
2771 save->ss.limit, save->ss.base);
2772 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2773 save->ds.selector, save->ds.attrib,
2774 save->ds.limit, save->ds.base);
2775 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2776 save->fs.selector, save->fs.attrib,
2777 save->fs.limit, save->fs.base);
2778 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2779 save->gs.selector, save->gs.attrib,
2780 save->gs.limit, save->gs.base);
2781 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2782 save->gdtr.selector, save->gdtr.attrib,
2783 save->gdtr.limit, save->gdtr.base);
2784 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2785 save->ldtr.selector, save->ldtr.attrib,
2786 save->ldtr.limit, save->ldtr.base);
2787 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2788 save->idtr.selector, save->idtr.attrib,
2789 save->idtr.limit, save->idtr.base);
2790 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2791 save->tr.selector, save->tr.attrib,
2792 save->tr.limit, save->tr.base);
2793 pr_err("cpl: %d efer: %016llx\n",
2794 save->cpl, save->efer);
2795 pr_err("cr0: %016llx cr2: %016llx\n",
2796 save->cr0, save->cr2);
2797 pr_err("cr3: %016llx cr4: %016llx\n",
2798 save->cr3, save->cr4);
2799 pr_err("dr6: %016llx dr7: %016llx\n",
2800 save->dr6, save->dr7);
2801 pr_err("rip: %016llx rflags: %016llx\n",
2802 save->rip, save->rflags);
2803 pr_err("rsp: %016llx rax: %016llx\n",
2804 save->rsp, save->rax);
2805 pr_err("star: %016llx lstar: %016llx\n",
2806 save->star, save->lstar);
2807 pr_err("cstar: %016llx sfmask: %016llx\n",
2808 save->cstar, save->sfmask);
2809 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2810 save->kernel_gs_base, save->sysenter_cs);
2811 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2812 save->sysenter_esp, save->sysenter_eip);
2813 pr_err("gpat: %016llx dbgctl: %016llx\n",
2814 save->g_pat, save->dbgctl);
2815 pr_err("br_from: %016llx br_to: %016llx\n",
2816 save->br_from, save->br_to);
2817 pr_err("excp_from: %016llx excp_to: %016llx\n",
2818 save->last_excp_from, save->last_excp_to);
2819
2820}
2821
851ba692 2822static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2823{
04d2cc77 2824 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2825 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2826 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2827
5bfd8b54 2828 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 2829
2be4fc7a
JR		 2830 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2831 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2832 if (npt_enabled)
2833 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2834
cd3ff653
JR		 2835 if (unlikely(svm->nested.exit_required)) {
2836 nested_svm_vmexit(svm);
2837 svm->nested.exit_required = false;
2838
2839 return 1;
2840 }
2841
cf74a78b 2842 if (is_nested(svm)) {
410e4d57
JR		 2843 int vmexit;
2844
d8cabddf
JR		 2845 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2846 svm->vmcb->control.exit_info_1,
2847 svm->vmcb->control.exit_info_2,
2848 svm->vmcb->control.exit_int_info,
2849 svm->vmcb->control.exit_int_info_err);
2850
410e4d57
JR		 2851 vmexit = nested_svm_exit_special(svm);
2852
2853 if (vmexit == NESTED_EXIT_CONTINUE)
2854 vmexit = nested_svm_exit_handled(svm);
2855
2856 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2857 return 1;
cf74a78b
AG		 2858 }
2859
a5c3832d
JR		 2860 svm_complete_interrupts(svm);
2861
04d2cc77
AK		 2862 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2863 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2864 kvm_run->fail_entry.hardware_entry_failure_reason
2865 = svm->vmcb->control.exit_code;
3f10c846
JR		 2866 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2867 dump_vmcb(vcpu);
04d2cc77
AK		 2868 return 0;
2869 }
2870
a2fa3e9f 2871 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2872 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2873 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2874 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2875 "exit_code 0x%x\n",
b8688d51 2876 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2877 exit_code);
2878
9d8f549d 2879 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2880 || !svm_exit_handlers[exit_code]) {
6aa8b732 2881 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2882 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2883 return 0;
2884 }
2885
851ba692 2886 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2887}
2888
2889static void reload_tss(struct kvm_vcpu *vcpu)
2890{
2891 int cpu = raw_smp_processor_id();
2892
0fe1e009
TH		 2893 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2894 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2895 load_TR_desc();
2896}
2897
e756fc62 2898static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2899{
2900 int cpu = raw_smp_processor_id();
2901
0fe1e009 2902 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2903
a2fa3e9f 2904 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2905 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2906 if (svm->asid_generation != sd->asid_generation)
2907 new_asid(svm, sd);
6aa8b732
AK		 2908}
2909
95ba8273
GN		 2910static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2911{
2912 struct vcpu_svm *svm = to_svm(vcpu);
2913
2914 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2915 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 2916 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 2917 ++vcpu->stat.nmi_injections;
2918}
6aa8b732 2919
85f455f7 2920static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2921{
2922 struct vmcb_control_area *control;
2923
229456fc 2924 trace_kvm_inj_virq(irq);
af9ca2d7 2925
fa89a817 2926 ++svm->vcpu.stat.irq_injections;
e756fc62 2927 control = &svm->vmcb->control;
85f455f7 2928 control->int_vector = irq;
6aa8b732
AK		 2929 control->int_ctl &= ~V_INTR_PRIO_MASK;
2930 control->int_ctl |= V_IRQ_MASK |
2931 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2932}
2933
66fd3f7f 2934static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2935{
2936 struct vcpu_svm *svm = to_svm(vcpu);
2937
2af9194d 2938 BUG_ON(!(gif_set(svm)));
cf74a78b 2939
219b65dc
AG		 2940 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2941 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2942}
2943
95ba8273 2944static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2945{
2946 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2947
88ab24ad
JR		 2948 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2949 return;
2950
95ba8273 2951 if (irr == -1)
aaacfc9a
JR		 2952 return;
2953
95ba8273
GN		 2954 if (tpr >= irr)
2955 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2956}
aaacfc9a 2957
95ba8273
GN		 2958static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2959{
2960 struct vcpu_svm *svm = to_svm(vcpu);
2961 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 2962 int ret;
2963 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2964 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2965 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2966
2967 return ret;
aaacfc9a
JR		 2968}
2969
3cfc3092
JK		 2970static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2971{
2972 struct vcpu_svm *svm = to_svm(vcpu);
2973
2974 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2975}
2976
2977static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2978{
2979 struct vcpu_svm *svm = to_svm(vcpu);
2980
2981 if (masked) {
2982 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 2983 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 2984 } else {
2985 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 2986 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 2987 }
2988}
2989
78646121
GN		 2990static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2991{
2992 struct vcpu_svm *svm = to_svm(vcpu);
2993 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2994 int ret;
2995
2996 if (!gif_set(svm) ||
2997 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2998 return 0;
2999
3000 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3001
3002 if (is_nested(svm))
3003 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3004
3005 return ret;
78646121
GN		 3006}
3007
9222be18 3008static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3009{
219b65dc 3010 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3011
e0231715
JR		 3012 /*
3013 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3014 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3015 * get that intercept, this function will be called again though and
3016 * we'll get the vintr intercept.
3017 */
8fe54654 3018 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3019 svm_set_vintr(svm);
3020 svm_inject_irq(svm, 0x0);
3021 }
85f455f7
ED		 3022}
3023
95ba8273 3024static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3025{
04d2cc77 3026 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3027
44c11430
GN		 3028 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3029 == HF_NMI_MASK)
3030 return; /* IRET will cause a vm exit */
3031
e0231715
JR		 3032 /*
3033 * Something prevents NMI from been injected. Single step over possible
3034 * problem (IRET or exception injection or interrupt shadow)
3035 */
6be7d306 3036 svm->nmi_singlestep = true;
44c11430
GN		 3037 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3038 update_db_intercept(vcpu);
c1150d8c
DL		 3039}
3040
cbc94022
IE		 3041static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3042{
3043 return 0;
3044}
3045
d9e368d6
AK		 3046static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3047{
3048 force_new_asid(vcpu);
3049}
3050
04d2cc77
AK		 3051static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3052{
3053}
3054
d7bf8221
JR		 3055static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3056{
3057 struct vcpu_svm *svm = to_svm(vcpu);
3058
88ab24ad
JR		 3059 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3060 return;
3061
d7bf8221
JR		 3062 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3063 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3064 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3065 }
3066}
3067
649d6864
JR		 3068static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3069{
3070 struct vcpu_svm *svm = to_svm(vcpu);
3071 u64 cr8;
3072
88ab24ad
JR		 3073 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3074 return;
3075
649d6864
JR		 3076 cr8 = kvm_get_cr8(vcpu);
3077 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3078 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3079}
3080
9222be18
GN		 3081static void svm_complete_interrupts(struct vcpu_svm *svm)
3082{
3083 u8 vector;
3084 int type;
3085 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3086 unsigned int3_injected = svm->int3_injected;
3087
3088 svm->int3_injected = 0;
9222be18 3089
44c11430
GN		 3090 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3091 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3092
9222be18
GN		 3093 svm->vcpu.arch.nmi_injected = false;
3094 kvm_clear_exception_queue(&svm->vcpu);
3095 kvm_clear_interrupt_queue(&svm->vcpu);
3096
3097 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3098 return;
3099
3100 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3101 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3102
3103 switch (type) {
3104 case SVM_EXITINTINFO_TYPE_NMI:
3105 svm->vcpu.arch.nmi_injected = true;
3106 break;
3107 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3108 /*
3109 * In case of software exceptions, do not reinject the vector,
3110 * but re-execute the instruction instead. Rewind RIP first
3111 * if we emulated INT3 before.
3112 */
3113 if (kvm_exception_is_soft(vector)) {
3114 if (vector == BP_VECTOR && int3_injected &&
3115 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3116 kvm_rip_write(&svm->vcpu,
3117 kvm_rip_read(&svm->vcpu) -
3118 int3_injected);
9222be18 3119 break;
66b7138f 3120 }
9222be18
GN		 3121 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3122 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3123 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3124
3125 } else
ce7ddec4 3126 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3127 break;
3128 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3129 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3130 break;
3131 default:
3132 break;
3133 }
3134}
3135
80e31d4f
AK		 3136#ifdef CONFIG_X86_64
3137#define R "r"
3138#else
3139#define R "e"
3140#endif
3141
851ba692 3142static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3143{
a2fa3e9f 3144 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 3145 u16 fs_selector;
3146 u16 gs_selector;
3147 u16 ldt_selector;
d9e368d6 3148
2041a06a
JR		 3149 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3150 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3151 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3152
cd3ff653
JR		 3153 /*
3154 * A vmexit emulation is required before the vcpu can be executed
3155 * again.
3156 */
3157 if (unlikely(svm->nested.exit_required))
3158 return;
3159
e756fc62 3160 pre_svm_run(svm);
6aa8b732 3161
649d6864
JR		 3162 sync_lapic_to_cr8(vcpu);
3163
6aa8b732 3164 save_host_msrs(vcpu);
d6e88aec
AK		 3165 fs_selector = kvm_read_fs();
3166 gs_selector = kvm_read_gs();
3167 ldt_selector = kvm_read_ldt();
cda0ffdd 3168 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 3169 /* required for live migration with NPT */
3170 if (npt_enabled)
3171 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 3172
04d2cc77
AK		 3173 clgi();
3174
3175 local_irq_enable();
36241b8c 3176
6aa8b732 3177 asm volatile (
80e31d4f
AK		 3178 "push %%"R"bp; \n\t"
3179 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3180 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3181 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3182 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3183 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3184 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3185#ifdef CONFIG_X86_64
fb3f0f51
RR		 3186 "mov %c[r8](%[svm]), %%r8 \n\t"
3187 "mov %c[r9](%[svm]), %%r9 \n\t"
3188 "mov %c[r10](%[svm]), %%r10 \n\t"
3189 "mov %c[r11](%[svm]), %%r11 \n\t"
3190 "mov %c[r12](%[svm]), %%r12 \n\t"
3191 "mov %c[r13](%[svm]), %%r13 \n\t"
3192 "mov %c[r14](%[svm]), %%r14 \n\t"
3193 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3194#endif
3195
6aa8b732 3196 /* Enter guest mode */
80e31d4f
AK		 3197 "push %%"R"ax \n\t"
3198 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3199 __ex(SVM_VMLOAD) "\n\t"
3200 __ex(SVM_VMRUN) "\n\t"
3201 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3202 "pop %%"R"ax \n\t"
6aa8b732
AK		 3203
3204 /* Save guest registers, load host registers */
80e31d4f
AK		 3205 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3206 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3207 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3208 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3209 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3210 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3211#ifdef CONFIG_X86_64
fb3f0f51
RR		 3212 "mov %%r8, %c[r8](%[svm]) \n\t"
3213 "mov %%r9, %c[r9](%[svm]) \n\t"
3214 "mov %%r10, %c[r10](%[svm]) \n\t"
3215 "mov %%r11, %c[r11](%[svm]) \n\t"
3216 "mov %%r12, %c[r12](%[svm]) \n\t"
3217 "mov %%r13, %c[r13](%[svm]) \n\t"
3218 "mov %%r14, %c[r14](%[svm]) \n\t"
3219 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3220#endif
80e31d4f 3221 "pop %%"R"bp"
6aa8b732 3222 :
fb3f0f51 3223 : [svm]"a"(svm),
6aa8b732 3224 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3225 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3226 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3227 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3228 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3229 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3230 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3231#ifdef CONFIG_X86_64
ad312c7c
ZX		 3232 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3233 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3234 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3235 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3236 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3237 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3238 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3239 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3240#endif
54a08c04 3241 : "cc", "memory"
80e31d4f 3242 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3243#ifdef CONFIG_X86_64
54a08c04
LV		 3244 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3245#endif
3246 );
6aa8b732 3247
ad312c7c 3248 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3249 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3250 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3251 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3252
d6e88aec
AK		 3253 kvm_load_fs(fs_selector);
3254 kvm_load_gs(gs_selector);
3255 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3256 load_host_msrs(vcpu);
3257
3258 reload_tss(vcpu);
3259
56ba47dd
AK		 3260 local_irq_disable();
3261
3262 stgi();
3263
d7bf8221
JR		 3264 sync_cr8_to_lapic(vcpu);
3265
a2fa3e9f 3266 svm->next_rip = 0;
9222be18 3267
6de4f3ad
AK		 3268 if (npt_enabled) {
3269 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3270 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3271 }
fe5913e4
JR		 3272
3273 /*
3274 * We need to handle MC intercepts here before the vcpu has a chance to
3275 * change the physical cpu
3276 */
3277 if (unlikely(svm->vmcb->control.exit_code ==
3278 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3279 svm_handle_mce(svm);
6aa8b732
AK		 3280}
3281
80e31d4f
AK		 3282#undef R
3283
6aa8b732
AK		 3284static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3285{
a2fa3e9f
GH		 3286 struct vcpu_svm *svm = to_svm(vcpu);
3287
709ddebf
JR		 3288 if (npt_enabled) {
3289 svm->vmcb->control.nested_cr3 = root;
3290 force_new_asid(vcpu);
3291 return;
3292 }
3293
a2fa3e9f 3294 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3295 force_new_asid(vcpu);
3296}
3297
6aa8b732
AK		 3298static int is_disabled(void)
3299{
6031a61c
JR		 3300 u64 vm_cr;
3301
3302 rdmsrl(MSR_VM_CR, vm_cr);
3303 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3304 return 1;
3305
6aa8b732
AK		 3306 return 0;
3307}
3308
102d8325
IM		 3309static void
3310svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3311{
3312 /*
3313 * Patch in the VMMCALL instruction:
3314 */
3315 hypercall[0] = 0x0f;
3316 hypercall[1] = 0x01;
3317 hypercall[2] = 0xd9;
102d8325
IM		 3318}
3319
002c7f7c
YS		 3320static void svm_check_processor_compat(void *rtn)
3321{
3322 *(int *)rtn = 0;
3323}
3324
774ead3a
AK		 3325static bool svm_cpu_has_accelerated_tpr(void)
3326{
3327 return false;
3328}
3329
67253af5
SY		 3330static int get_npt_level(void)
3331{
3332#ifdef CONFIG_X86_64
3333 return PT64_ROOT_LEVEL;
3334#else
3335 return PT32E_ROOT_LEVEL;
3336#endif
3337}
3338
4b12f0de 3339static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3340{
3341 return 0;
3342}
3343
0e851880
SY		 3344static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3345{
3346}
3347
d4330ef2
JR		 3348static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3349{
c2c63a49
JR		 3350 switch (func) {
3351 case 0x8000000A:
3352 entry->eax = 1; /* SVM revision 1 */
3353 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3354 ASID emulation to nested SVM */
3355 entry->ecx = 0; /* Reserved */
3356 entry->edx = 0; /* Do not support any additional features */
3357
3358 break;
3359 }
d4330ef2
JR		 3360}
3361
229456fc 3362static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3363 { SVM_EXIT_READ_CR0, "read_cr0" },
3364 { SVM_EXIT_READ_CR3, "read_cr3" },
3365 { SVM_EXIT_READ_CR4, "read_cr4" },
3366 { SVM_EXIT_READ_CR8, "read_cr8" },
3367 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3368 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3369 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3370 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3371 { SVM_EXIT_READ_DR0, "read_dr0" },
3372 { SVM_EXIT_READ_DR1, "read_dr1" },
3373 { SVM_EXIT_READ_DR2, "read_dr2" },
3374 { SVM_EXIT_READ_DR3, "read_dr3" },
3375 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3376 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3377 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3378 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3379 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3380 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3381 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3382 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3383 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3384 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3385 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3386 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3387 { SVM_EXIT_INTR, "interrupt" },
3388 { SVM_EXIT_NMI, "nmi" },
3389 { SVM_EXIT_SMI, "smi" },
3390 { SVM_EXIT_INIT, "init" },
3391 { SVM_EXIT_VINTR, "vintr" },
3392 { SVM_EXIT_CPUID, "cpuid" },
3393 { SVM_EXIT_INVD, "invd" },
3394 { SVM_EXIT_HLT, "hlt" },
3395 { SVM_EXIT_INVLPG, "invlpg" },
3396 { SVM_EXIT_INVLPGA, "invlpga" },
3397 { SVM_EXIT_IOIO, "io" },
3398 { SVM_EXIT_MSR, "msr" },
3399 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3400 { SVM_EXIT_SHUTDOWN, "shutdown" },
3401 { SVM_EXIT_VMRUN, "vmrun" },
3402 { SVM_EXIT_VMMCALL, "hypercall" },
3403 { SVM_EXIT_VMLOAD, "vmload" },
3404 { SVM_EXIT_VMSAVE, "vmsave" },
3405 { SVM_EXIT_STGI, "stgi" },
3406 { SVM_EXIT_CLGI, "clgi" },
3407 { SVM_EXIT_SKINIT, "skinit" },
3408 { SVM_EXIT_WBINVD, "wbinvd" },
3409 { SVM_EXIT_MONITOR, "monitor" },
3410 { SVM_EXIT_MWAIT, "mwait" },
3411 { SVM_EXIT_NPF, "npf" },
3412 { -1, NULL }
3413};
3414
17cc3935 3415static int svm_get_lpage_level(void)
344f414f 3416{
17cc3935 3417 return PT_PDPE_LEVEL;
344f414f
JR		 3418}
3419
4e47c7a6
SY		 3420static bool svm_rdtscp_supported(void)
3421{
3422 return false;
3423}
3424
02daab21
AK		 3425static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3426{
3427 struct vcpu_svm *svm = to_svm(vcpu);
3428
02daab21 3429 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3430 if (is_nested(svm))
3431 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3432 update_cr0_intercept(svm);
02daab21
AK		 3433}
3434
cbdd1bea 3435static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3436 .cpu_has_kvm_support = has_svm,
3437 .disabled_by_bios = is_disabled,
3438 .hardware_setup = svm_hardware_setup,
3439 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3440 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3441 .hardware_enable = svm_hardware_enable,
3442 .hardware_disable = svm_hardware_disable,
774ead3a 3443 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3444
3445 .vcpu_create = svm_create_vcpu,
3446 .vcpu_free = svm_free_vcpu,
04d2cc77 3447 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3448
04d2cc77 3449 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3450 .vcpu_load = svm_vcpu_load,
3451 .vcpu_put = svm_vcpu_put,
3452
3453 .set_guest_debug = svm_guest_debug,
3454 .get_msr = svm_get_msr,
3455 .set_msr = svm_set_msr,
3456 .get_segment_base = svm_get_segment_base,
3457 .get_segment = svm_get_segment,
3458 .set_segment = svm_set_segment,
2e4d2653 3459 .get_cpl = svm_get_cpl,
1747fb71 3460 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3461 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3462 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3463 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3464 .set_cr3 = svm_set_cr3,
3465 .set_cr4 = svm_set_cr4,
3466 .set_efer = svm_set_efer,
3467 .get_idt = svm_get_idt,
3468 .set_idt = svm_set_idt,
3469 .get_gdt = svm_get_gdt,
3470 .set_gdt = svm_set_gdt,
020df079 3471 .set_dr7 = svm_set_dr7,
6de4f3ad 3472 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3473 .get_rflags = svm_get_rflags,
3474 .set_rflags = svm_set_rflags,
6b52d186 3475 .fpu_activate = svm_fpu_activate,
02daab21 3476 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3477
6aa8b732 3478 .tlb_flush = svm_flush_tlb,
6aa8b732 3479
6aa8b732 3480 .run = svm_vcpu_run,
04d2cc77 3481 .handle_exit = handle_exit,
6aa8b732 3482 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3483 .set_interrupt_shadow = svm_set_interrupt_shadow,
3484 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3485 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3486 .set_irq = svm_set_irq,
95ba8273 3487 .set_nmi = svm_inject_nmi,
298101da 3488 .queue_exception = svm_queue_exception,
78646121 3489 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3490 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3491 .get_nmi_mask = svm_get_nmi_mask,
3492 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3493 .enable_nmi_window = enable_nmi_window,
3494 .enable_irq_window = enable_irq_window,
3495 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3496
3497 .set_tss_addr = svm_set_tss_addr,
67253af5 3498 .get_tdp_level = get_npt_level,
4b12f0de 3499 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3500
3501 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3502 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3503
3504 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3505
3506 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3507
3508 .set_supported_cpuid = svm_set_supported_cpuid,
6aa8b732
AK		 3509};
3510
3511static int __init svm_init(void)
3512{
cb498ea2 3513 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3514 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3515}
3516
3517static void __exit svm_exit(void)
3518{
cb498ea2 3519 kvm_exit();
6aa8b732
AK		 3520}
3521
3522module_init(svm_init)
3523module_exit(svm_exit)
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