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49ba9447 | 1 | /**@file\r |
2 | Platform PEI driver\r | |
3 | \r | |
a1726e30 | 4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
eec7d420 | 5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r |
6 | \r | |
b26f0cf9 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
49ba9447 | 8 | \r |
9 | **/\r | |
10 | \r | |
11 | //\r | |
12 | // The package level header files this module uses\r | |
13 | //\r | |
14 | #include <PiPei.h>\r | |
15 | \r | |
16 | //\r | |
17 | // The Library classes this module consumes\r | |
18 | //\r | |
5133d1f1 | 19 | #include <Library/BaseLib.h>\r |
49ba9447 | 20 | #include <Library/DebugLib.h>\r |
21 | #include <Library/HobLib.h>\r | |
22 | #include <Library/IoLib.h>\r | |
77ba993c | 23 | #include <Library/MemoryAllocationLib.h>\r |
24 | #include <Library/PcdLib.h>\r | |
49ba9447 | 25 | #include <Library/PciLib.h>\r |
26 | #include <Library/PeimEntryPoint.h>\r | |
9ed65b10 | 27 | #include <Library/PeiServicesLib.h>\r |
7cdba634 | 28 | #include <Library/QemuFwCfgLib.h>\r |
687f7521 | 29 | #include <Library/QemuFwCfgS3Lib.h>\r |
49ba9447 | 30 | #include <Library/ResourcePublicationLib.h>\r |
31 | #include <Guid/MemoryTypeInformation.h>\r | |
9ed65b10 | 32 | #include <Ppi/MasterBootMode.h>\r |
931a0c74 | 33 | #include <IndustryStandard/Pci22.h>\r |
97380beb | 34 | #include <OvmfPlatforms.h>\r |
49ba9447 | 35 | \r |
36 | #include "Platform.h"\r | |
3ca15914 | 37 | #include "Cmos.h"\r |
49ba9447 | 38 | \r |
39 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
40 | { EfiACPIMemoryNVS, 0x004 },\r | |
991d9563 | 41 | { EfiACPIReclaimMemory, 0x008 },\r |
55cdb67a | 42 | { EfiReservedMemoryType, 0x004 },\r |
991d9563 | 43 | { EfiRuntimeServicesData, 0x024 },\r |
44 | { EfiRuntimeServicesCode, 0x030 },\r | |
45 | { EfiBootServicesCode, 0x180 },\r | |
46 | { EfiBootServicesData, 0xF00 },\r | |
49ba9447 | 47 | { EfiMaxMemoryType, 0x000 }\r |
48 | };\r | |
49 | \r | |
50 | \r | |
9ed65b10 | 51 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r |
52 | {\r | |
53 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
54 | &gEfiPeiMasterBootModePpiGuid,\r | |
55 | NULL\r | |
56 | }\r | |
57 | };\r | |
58 | \r | |
59 | \r | |
589756c7 PA |
60 | UINT16 mHostBridgeDevId;\r |
61 | \r | |
979420df JJ |
62 | EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r |
63 | \r | |
7cdba634 JJ |
64 | BOOLEAN mS3Supported = FALSE;\r |
65 | \r | |
45a70db3 | 66 | UINT32 mMaxCpuCount;\r |
979420df | 67 | \r |
49ba9447 | 68 | VOID\r |
69 | AddIoMemoryBaseSizeHob (\r | |
70 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
71 | UINT64 MemorySize\r | |
72 | )\r | |
73 | {\r | |
991d9563 | 74 | BuildResourceDescriptorHob (\r |
75 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
49ba9447 | 76 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
77 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
78 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
991d9563 | 79 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 80 | MemoryBase,\r |
81 | MemorySize\r | |
82 | );\r | |
83 | }\r | |
84 | \r | |
eec7d420 | 85 | VOID\r |
86 | AddReservedMemoryBaseSizeHob (\r | |
87 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
cdef34ec LE |
88 | UINT64 MemorySize,\r |
89 | BOOLEAN Cacheable\r | |
eec7d420 | 90 | )\r |
91 | {\r | |
92 | BuildResourceDescriptorHob (\r | |
93 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
94 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
95 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
96 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
cdef34ec LE |
97 | (Cacheable ?\r |
98 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
99 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
100 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r | |
101 | 0\r | |
102 | ) |\r | |
eec7d420 | 103 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
104 | MemoryBase,\r | |
105 | MemorySize\r | |
106 | );\r | |
107 | }\r | |
49ba9447 | 108 | \r |
109 | VOID\r | |
110 | AddIoMemoryRangeHob (\r | |
111 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
112 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
113 | )\r | |
114 | {\r | |
115 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
116 | }\r | |
117 | \r | |
118 | \r | |
119 | VOID\r | |
120 | AddMemoryBaseSizeHob (\r | |
121 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
122 | UINT64 MemorySize\r | |
123 | )\r | |
124 | {\r | |
991d9563 | 125 | BuildResourceDescriptorHob (\r |
126 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
49ba9447 | 127 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
128 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
129 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
130 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
131 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
132 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
991d9563 | 133 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 134 | MemoryBase,\r |
135 | MemorySize\r | |
136 | );\r | |
137 | }\r | |
138 | \r | |
139 | \r | |
140 | VOID\r | |
141 | AddMemoryRangeHob (\r | |
142 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
143 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
144 | )\r | |
145 | {\r | |
146 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
147 | }\r | |
148 | \r | |
c0e10976 | 149 | \r |
bb6a9a93 | 150 | VOID\r |
4b455f7b | 151 | MemMapInitialization (\r |
bb6a9a93 WL |
152 | VOID\r |
153 | )\r | |
154 | {\r | |
32e083c7 LE |
155 | UINT64 PciIoBase;\r |
156 | UINT64 PciIoSize;\r | |
157 | RETURN_STATUS PcdStatus;\r | |
c4df7fd0 LE |
158 | \r |
159 | PciIoBase = 0xC000;\r | |
160 | PciIoSize = 0x4000;\r | |
161 | \r | |
bb6a9a93 WL |
162 | //\r |
163 | // Create Memory Type Information HOB\r | |
164 | //\r | |
165 | BuildGuidDataHob (\r | |
166 | &gEfiMemoryTypeInformationGuid,\r | |
167 | mDefaultMemoryTypeInformation,\r | |
168 | sizeof(mDefaultMemoryTypeInformation)\r | |
169 | );\r | |
170 | \r | |
bb6a9a93 WL |
171 | //\r |
172 | // Video memory + Legacy BIOS region\r | |
173 | //\r | |
174 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
175 | \r | |
4b455f7b | 176 | if (!mXen) {\r |
305cd4f7 | 177 | UINT32 TopOfLowRam;\r |
7b8fe635 | 178 | UINT64 PciExBarBase;\r |
c68d3a69 | 179 | UINT32 PciBase;\r |
03845e90 | 180 | UINT32 PciSize;\r |
c68d3a69 | 181 | \r |
305cd4f7 | 182 | TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r |
02d6f4ce | 183 | PciExBarBase = 0;\r |
c68d3a69 LE |
184 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
185 | //\r | |
eb4d62b0 LE |
186 | // The MMCONFIG area is expected to fall between the top of low RAM and\r |
187 | // the base of the 32-bit PCI host aperture.\r | |
c68d3a69 | 188 | //\r |
7b8fe635 | 189 | PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r |
eb4d62b0 | 190 | ASSERT (TopOfLowRam <= PciExBarBase);\r |
7b8fe635 | 191 | ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r |
eb4d62b0 | 192 | PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r |
c68d3a69 | 193 | } else {\r |
49edde15 LE |
194 | ASSERT (TopOfLowRam <= mQemuUc32Base);\r |
195 | PciBase = mQemuUc32Base;\r | |
c68d3a69 | 196 | }\r |
49ba9447 | 197 | \r |
4b455f7b JJ |
198 | //\r |
199 | // address purpose size\r | |
200 | // ------------ -------- -------------------------\r | |
201 | // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r | |
202 | // 0xFC000000 gap 44 MB\r | |
203 | // 0xFEC00000 IO-APIC 4 KB\r | |
204 | // 0xFEC01000 gap 1020 KB\r | |
205 | // 0xFED00000 HPET 1 KB\r | |
90721ba5 PA |
206 | // 0xFED00400 gap 111 KB\r |
207 | // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r | |
208 | // 0xFED20000 gap 896 KB\r | |
4b455f7b JJ |
209 | // 0xFEE00000 LAPIC 1 MB\r |
210 | //\r | |
d4534984 | 211 | PciSize = 0xFC000000 - PciBase;\r |
03845e90 | 212 | AddIoMemoryBaseSizeHob (PciBase, PciSize);\r |
32e083c7 LE |
213 | PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r |
214 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
215 | PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r | |
216 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
217 | \r | |
4b455f7b JJ |
218 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r |
219 | AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r | |
90721ba5 PA |
220 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
221 | AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r | |
7b8fe635 LE |
222 | //\r |
223 | // Note: there should be an\r | |
224 | //\r | |
225 | // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r | |
226 | //\r | |
227 | // call below, just like the one above for RCBA. However, Linux insists\r | |
228 | // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r | |
229 | // "reserved memory" -- Linux does not content itself with a simple gap\r | |
230 | // in the memory map wherever the MCFG ACPI table points to.\r | |
231 | //\r | |
232 | // This appears to be a safety measure. The PCI Firmware Specification\r | |
233 | // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r | |
234 | // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r | |
235 | // [...]". (Emphasis added here.)\r | |
236 | //\r | |
237 | // Normally we add memory resource descriptor HOBs in\r | |
238 | // QemuInitializeRam(), and pre-allocate from those with memory\r | |
239 | // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r | |
240 | // is most definitely not RAM; so, as an exception, cover it with\r | |
241 | // uncacheable reserved memory right here.\r | |
242 | //\r | |
243 | AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r | |
244 | BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r | |
245 | EfiReservedMemoryType);\r | |
90721ba5 | 246 | }\r |
4b455f7b | 247 | AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r |
bba734ab LE |
248 | \r |
249 | //\r | |
250 | // On Q35, the IO Port space is available for PCI resource allocations from\r | |
251 | // 0x6000 up.\r | |
252 | //\r | |
253 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
254 | PciIoBase = 0x6000;\r | |
255 | PciIoSize = 0xA000;\r | |
256 | ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r | |
257 | }\r | |
4b455f7b | 258 | }\r |
c4df7fd0 LE |
259 | \r |
260 | //\r | |
261 | // Add PCI IO Port space available for PCI resource allocations.\r | |
262 | //\r | |
263 | BuildResourceDescriptorHob (\r | |
264 | EFI_RESOURCE_IO,\r | |
265 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
266 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
267 | PciIoBase,\r | |
268 | PciIoSize\r | |
269 | );\r | |
32e083c7 LE |
270 | PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r |
271 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
272 | PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r | |
273 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
49ba9447 | 274 | }\r |
275 | \r | |
ab081a50 LE |
276 | EFI_STATUS\r |
277 | GetNamedFwCfgBoolean (\r | |
278 | IN CHAR8 *FwCfgFileName,\r | |
279 | OUT BOOLEAN *Setting\r | |
280 | )\r | |
281 | {\r | |
282 | EFI_STATUS Status;\r | |
283 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
284 | UINTN FwCfgSize;\r | |
285 | UINT8 Value[3];\r | |
286 | \r | |
287 | Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r | |
288 | if (EFI_ERROR (Status)) {\r | |
289 | return Status;\r | |
290 | }\r | |
291 | if (FwCfgSize > sizeof Value) {\r | |
292 | return EFI_BAD_BUFFER_SIZE;\r | |
293 | }\r | |
294 | QemuFwCfgSelectItem (FwCfgItem);\r | |
295 | QemuFwCfgReadBytes (FwCfgSize, Value);\r | |
296 | \r | |
297 | if ((FwCfgSize == 1) ||\r | |
298 | (FwCfgSize == 2 && Value[1] == '\n') ||\r | |
299 | (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r | |
300 | switch (Value[0]) {\r | |
301 | case '0':\r | |
302 | case 'n':\r | |
303 | case 'N':\r | |
304 | *Setting = FALSE;\r | |
305 | return EFI_SUCCESS;\r | |
306 | \r | |
307 | case '1':\r | |
308 | case 'y':\r | |
309 | case 'Y':\r | |
310 | *Setting = TRUE;\r | |
311 | return EFI_SUCCESS;\r | |
312 | \r | |
313 | default:\r | |
314 | break;\r | |
315 | }\r | |
316 | }\r | |
317 | return EFI_PROTOCOL_ERROR;\r | |
318 | }\r | |
319 | \r | |
320 | #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r | |
321 | do { \\r | |
32e083c7 LE |
322 | BOOLEAN Setting; \\r |
323 | RETURN_STATUS PcdStatus; \\r | |
ab081a50 LE |
324 | \\r |
325 | if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r | |
326 | "opt/ovmf/" #TokenName, &Setting))) { \\r | |
32e083c7 LE |
327 | PcdStatus = PcdSetBoolS (TokenName, Setting); \\r |
328 | ASSERT_RETURN_ERROR (PcdStatus); \\r | |
ab081a50 LE |
329 | } \\r |
330 | } while (0)\r | |
331 | \r | |
332 | VOID\r | |
333 | NoexecDxeInitialization (\r | |
334 | VOID\r | |
335 | )\r | |
336 | {\r | |
337 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r | |
338 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r | |
339 | }\r | |
49ba9447 | 340 | \r |
7b8fe635 LE |
341 | VOID\r |
342 | PciExBarInitialization (\r | |
343 | VOID\r | |
344 | )\r | |
345 | {\r | |
346 | union {\r | |
347 | UINT64 Uint64;\r | |
348 | UINT32 Uint32[2];\r | |
349 | } PciExBarBase;\r | |
350 | \r | |
351 | //\r | |
352 | // We only support the 256MB size for the MMCONFIG area:\r | |
353 | // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r | |
354 | //\r | |
355 | // The masks used below enforce the Q35 requirements that the MMCONFIG area\r | |
356 | // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r | |
357 | //\r | |
358 | // Note that (b) also ensures that the minimum address width we have\r | |
359 | // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r | |
360 | // for DXE's page tables to cover the MMCONFIG area.\r | |
361 | //\r | |
362 | PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
363 | ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r | |
364 | ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r | |
365 | \r | |
366 | //\r | |
367 | // Clear the PCIEXBAREN bit first, before programming the high register.\r | |
368 | //\r | |
369 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r | |
370 | \r | |
371 | //\r | |
372 | // Program the high register. Then program the low register, setting the\r | |
373 | // MMCONFIG area size and enabling decoding at once.\r | |
374 | //\r | |
375 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r | |
376 | PciWrite32 (\r | |
377 | DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r | |
378 | PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r | |
379 | );\r | |
380 | }\r | |
381 | \r | |
49ba9447 | 382 | VOID\r |
383 | MiscInitialization (\r | |
0e20a186 | 384 | VOID\r |
49ba9447 | 385 | )\r |
386 | {\r | |
32e083c7 LE |
387 | UINTN PmCmd;\r |
388 | UINTN Pmba;\r | |
389 | UINT32 PmbaAndVal;\r | |
390 | UINT32 PmbaOrVal;\r | |
391 | UINTN AcpiCtlReg;\r | |
392 | UINT8 AcpiEnBit;\r | |
393 | RETURN_STATUS PcdStatus;\r | |
97380beb | 394 | \r |
49ba9447 | 395 | //\r |
396 | // Disable A20 Mask\r | |
397 | //\r | |
55cdb67a | 398 | IoOr8 (0x92, BIT1);\r |
49ba9447 | 399 | \r |
400 | //\r | |
86a14b0a LE |
401 | // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r |
402 | // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r | |
403 | // S3 resume as well, so we build it unconditionally.)\r | |
49ba9447 | 404 | //\r |
86a14b0a | 405 | BuildCpuHob (mPhysMemAddressWidth, 16);\r |
c756b2ab | 406 | \r |
97380beb | 407 | //\r |
589756c7 | 408 | // Determine platform type and save Host Bridge DID to PCD\r |
97380beb | 409 | //\r |
589756c7 | 410 | switch (mHostBridgeDevId) {\r |
97380beb | 411 | case INTEL_82441_DEVICE_ID:\r |
e2ab3f81 | 412 | PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r |
da372167 | 413 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r |
1466b76f LE |
414 | PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r |
415 | PmbaOrVal = PIIX4_PMBA_VALUE;\r | |
da372167 LE |
416 | AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r |
417 | AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r | |
97380beb GS |
418 | break;\r |
419 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
e2ab3f81 | 420 | PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r |
bc9d05d6 | 421 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r |
1466b76f LE |
422 | PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r |
423 | PmbaOrVal = ICH9_PMBASE_VALUE;\r | |
bc9d05d6 LE |
424 | AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r |
425 | AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r | |
97380beb GS |
426 | break;\r |
427 | default:\r | |
428 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
589756c7 | 429 | __FUNCTION__, mHostBridgeDevId));\r |
97380beb GS |
430 | ASSERT (FALSE);\r |
431 | return;\r | |
432 | }\r | |
32e083c7 LE |
433 | PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r |
434 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
97380beb | 435 | \r |
0e20a186 | 436 | //\r |
e2ab3f81 GS |
437 | // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r |
438 | // has been configured (e.g., by Xen) and skip the setup here.\r | |
439 | // This matches the logic in AcpiTimerLibConstructor ().\r | |
0e20a186 | 440 | //\r |
e2ab3f81 | 441 | if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r |
eec7d420 | 442 | //\r |
e2ab3f81 | 443 | // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r |
931a0c74 | 444 | // 1. set PMBA\r |
eec7d420 | 445 | //\r |
1466b76f | 446 | PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r |
931a0c74 | 447 | \r |
448 | //\r | |
449 | // 2. set PCICMD/IOSE\r | |
450 | //\r | |
97380beb | 451 | PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r |
931a0c74 | 452 | \r |
453 | //\r | |
e2ab3f81 | 454 | // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r |
931a0c74 | 455 | //\r |
e2ab3f81 | 456 | PciOr8 (AcpiCtlReg, AcpiEnBit);\r |
eec7d420 | 457 | }\r |
90721ba5 PA |
458 | \r |
459 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
460 | //\r | |
461 | // Set Root Complex Register Block BAR\r | |
462 | //\r | |
463 | PciWrite32 (\r | |
464 | POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r | |
465 | ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r | |
466 | );\r | |
7b8fe635 LE |
467 | \r |
468 | //\r | |
469 | // Set PCI Express Register Range Base Address\r | |
470 | //\r | |
471 | PciExBarInitialization ();\r | |
90721ba5 | 472 | }\r |
49ba9447 | 473 | }\r |
474 | \r | |
475 | \r | |
9ed65b10 | 476 | VOID\r |
477 | BootModeInitialization (\r | |
8f5ca05b | 478 | VOID\r |
9ed65b10 | 479 | )\r |
480 | {\r | |
8f5ca05b LE |
481 | EFI_STATUS Status;\r |
482 | \r | |
483 | if (CmosRead8 (0xF) == 0xFE) {\r | |
979420df | 484 | mBootMode = BOOT_ON_S3_RESUME;\r |
8f5ca05b | 485 | }\r |
9be75189 | 486 | CmosWrite8 (0xF, 0x00);\r |
667bf1e4 | 487 | \r |
979420df | 488 | Status = PeiServicesSetBootMode (mBootMode);\r |
667bf1e4 | 489 | ASSERT_EFI_ERROR (Status);\r |
490 | \r | |
491 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
492 | ASSERT_EFI_ERROR (Status);\r | |
9ed65b10 | 493 | }\r |
494 | \r | |
495 | \r | |
77ba993c | 496 | VOID\r |
497 | ReserveEmuVariableNvStore (\r | |
498 | )\r | |
499 | {\r | |
500 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
32e083c7 | 501 | RETURN_STATUS PcdStatus;\r |
77ba993c | 502 | \r |
503 | //\r | |
504 | // Allocate storage for NV variables early on so it will be\r | |
505 | // at a consistent address. Since VM memory is preserved\r | |
506 | // across reboots, this allows the NV variable storage to survive\r | |
507 | // a VM reboot.\r | |
508 | //\r | |
509 | VariableStore =\r | |
510 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
c9e7907d LE |
511 | AllocateRuntimePages (\r |
512 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r | |
27f58ea1 | 513 | );\r |
77ba993c | 514 | DEBUG ((EFI_D_INFO,\r |
c9e7907d | 515 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r |
77ba993c | 516 | VariableStore,\r |
c9e7907d | 517 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r |
77ba993c | 518 | ));\r |
32e083c7 LE |
519 | PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r |
520 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
77ba993c | 521 | }\r |
522 | \r | |
523 | \r | |
3ca15914 | 524 | VOID\r |
525 | DebugDumpCmos (\r | |
526 | VOID\r | |
527 | )\r | |
528 | {\r | |
6394c35a | 529 | UINT32 Loop;\r |
3ca15914 | 530 | \r |
531 | DEBUG ((EFI_D_INFO, "CMOS:\n"));\r | |
532 | \r | |
533 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
534 | if ((Loop % 0x10) == 0) {\r | |
535 | DEBUG ((EFI_D_INFO, "%02x:", Loop));\r | |
536 | }\r | |
537 | DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r | |
538 | if ((Loop % 0x10) == 0xf) {\r | |
539 | DEBUG ((EFI_D_INFO, "\n"));\r | |
540 | }\r | |
541 | }\r | |
542 | }\r | |
543 | \r | |
544 | \r | |
5133d1f1 LE |
545 | VOID\r |
546 | S3Verification (\r | |
547 | VOID\r | |
548 | )\r | |
549 | {\r | |
550 | #if defined (MDE_CPU_X64)\r | |
551 | if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r | |
552 | DEBUG ((EFI_D_ERROR,\r | |
553 | "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r | |
554 | DEBUG ((EFI_D_ERROR,\r | |
555 | "%a: Please disable S3 on the QEMU command line (see the README),\n",\r | |
556 | __FUNCTION__));\r | |
557 | DEBUG ((EFI_D_ERROR,\r | |
558 | "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r | |
559 | ASSERT (FALSE);\r | |
560 | CpuDeadLoop ();\r | |
561 | }\r | |
562 | #endif\r | |
563 | }\r | |
564 | \r | |
565 | \r | |
45a70db3 LE |
566 | /**\r |
567 | Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.\r | |
568 | Set the mMaxCpuCount variable.\r | |
569 | **/\r | |
570 | VOID\r | |
571 | MaxCpuCountInitialization (\r | |
572 | VOID\r | |
573 | )\r | |
574 | {\r | |
575 | UINT16 ProcessorCount;\r | |
576 | RETURN_STATUS PcdStatus;\r | |
577 | \r | |
578 | QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r | |
579 | ProcessorCount = QemuFwCfgRead16 ();\r | |
580 | //\r | |
581 | // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount\r | |
582 | // from the PCD default. No change to PCDs.\r | |
583 | //\r | |
584 | if (ProcessorCount == 0) {\r | |
585 | mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r | |
586 | return;\r | |
587 | }\r | |
588 | //\r | |
589 | // Otherwise, set mMaxCpuCount to the value reported by QEMU.\r | |
590 | //\r | |
591 | mMaxCpuCount = ProcessorCount;\r | |
592 | //\r | |
593 | // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)\r | |
594 | // to wait, in the initial AP bringup, exactly as long as it takes for all of\r | |
595 | // the APs to report in. For this, we set the longest representable timeout\r | |
596 | // (approx. 71 minutes).\r | |
597 | //\r | |
598 | PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);\r | |
599 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
600 | PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);\r | |
601 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
602 | DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,\r | |
603 | ProcessorCount));\r | |
604 | }\r | |
605 | \r | |
606 | \r | |
49ba9447 | 607 | /**\r |
608 | Perform Platform PEI initialization.\r | |
609 | \r | |
610 | @param FileHandle Handle of the file being invoked.\r | |
611 | @param PeiServices Describes the list of possible PEI Services.\r | |
612 | \r | |
613 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
614 | \r | |
615 | **/\r | |
616 | EFI_STATUS\r | |
617 | EFIAPI\r | |
618 | InitializePlatform (\r | |
619 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
620 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
621 | )\r | |
622 | {\r | |
a1726e30 SZ |
623 | EFI_STATUS Status;\r |
624 | \r | |
7707c9fd | 625 | DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r |
49ba9447 | 626 | \r |
3ca15914 | 627 | DebugDumpCmos ();\r |
628 | \r | |
b98b4941 | 629 | XenDetect ();\r |
c7ea55b9 | 630 | \r |
7cdba634 JJ |
631 | if (QemuFwCfgS3Enabled ()) {\r |
632 | DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r | |
633 | mS3Supported = TRUE;\r | |
a1726e30 SZ |
634 | Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r |
635 | ASSERT_EFI_ERROR (Status);\r | |
7cdba634 JJ |
636 | }\r |
637 | \r | |
5133d1f1 | 638 | S3Verification ();\r |
869b17cc | 639 | BootModeInitialization ();\r |
bc89fe48 | 640 | AddressWidthInitialization ();\r |
45a70db3 | 641 | MaxCpuCountInitialization ();\r |
869b17cc | 642 | \r |
d5e06444 LE |
643 | //\r |
644 | // Query Host Bridge DID\r | |
645 | //\r | |
646 | mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
647 | \r | |
23bfb5c0 LE |
648 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r |
649 | Q35TsegMbytesInitialization ();\r | |
650 | }\r | |
651 | \r | |
f76e9eba JJ |
652 | PublishPeiMemory ();\r |
653 | \r | |
49edde15 LE |
654 | QemuUc32BaseInitialization ();\r |
655 | \r | |
2818c158 | 656 | InitializeRamRegions ();\r |
49ba9447 | 657 | \r |
b621bb0a | 658 | if (mXen) {\r |
c7ea55b9 | 659 | DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r |
b98b4941 | 660 | InitializeXen ();\r |
c7ea55b9 | 661 | }\r |
eec7d420 | 662 | \r |
bd386eaf | 663 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
5e167d7e LE |
664 | if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r |
665 | ReserveEmuVariableNvStore ();\r | |
666 | }\r | |
bd386eaf | 667 | PeiFvInitialization ();\r |
bd386eaf | 668 | MemMapInitialization ();\r |
ab081a50 | 669 | NoexecDxeInitialization ();\r |
bd386eaf | 670 | }\r |
49ba9447 | 671 | \r |
d20ae95a | 672 | InstallClearCacheCallback ();\r |
13b5d743 | 673 | AmdSevInitialize ();\r |
0e20a186 | 674 | MiscInitialization ();\r |
dbab9949 | 675 | InstallFeatureControlCallback ();\r |
49ba9447 | 676 | \r |
677 | return EFI_SUCCESS;\r | |
678 | }\r |