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49ba9447 | 1 | /**@file\r |
2 | Platform PEI driver\r | |
3 | \r | |
a1726e30 | 4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
eec7d420 | 5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r |
6 | \r | |
b26f0cf9 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
49ba9447 | 8 | \r |
9 | **/\r | |
10 | \r | |
11 | //\r | |
12 | // The package level header files this module uses\r | |
13 | //\r | |
14 | #include <PiPei.h>\r | |
15 | \r | |
16 | //\r | |
17 | // The Library classes this module consumes\r | |
18 | //\r | |
5133d1f1 | 19 | #include <Library/BaseLib.h>\r |
49ba9447 | 20 | #include <Library/DebugLib.h>\r |
21 | #include <Library/HobLib.h>\r | |
22 | #include <Library/IoLib.h>\r | |
77ba993c | 23 | #include <Library/MemoryAllocationLib.h>\r |
24 | #include <Library/PcdLib.h>\r | |
49ba9447 | 25 | #include <Library/PciLib.h>\r |
26 | #include <Library/PeimEntryPoint.h>\r | |
9ed65b10 | 27 | #include <Library/PeiServicesLib.h>\r |
7cdba634 | 28 | #include <Library/QemuFwCfgLib.h>\r |
687f7521 | 29 | #include <Library/QemuFwCfgS3Lib.h>\r |
49ba9447 | 30 | #include <Library/ResourcePublicationLib.h>\r |
31 | #include <Guid/MemoryTypeInformation.h>\r | |
9ed65b10 | 32 | #include <Ppi/MasterBootMode.h>\r |
83357313 | 33 | #include <IndustryStandard/I440FxPiix4.h>\r |
931a0c74 | 34 | #include <IndustryStandard/Pci22.h>\r |
83357313 LE |
35 | #include <IndustryStandard/Q35MchIch9.h>\r |
36 | #include <IndustryStandard/QemuCpuHotplug.h>\r | |
97380beb | 37 | #include <OvmfPlatforms.h>\r |
49ba9447 | 38 | \r |
39 | #include "Platform.h"\r | |
3ca15914 | 40 | #include "Cmos.h"\r |
49ba9447 | 41 | \r |
42 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
43 | { EfiACPIMemoryNVS, 0x004 },\r | |
991d9563 | 44 | { EfiACPIReclaimMemory, 0x008 },\r |
55cdb67a | 45 | { EfiReservedMemoryType, 0x004 },\r |
991d9563 | 46 | { EfiRuntimeServicesData, 0x024 },\r |
47 | { EfiRuntimeServicesCode, 0x030 },\r | |
48 | { EfiBootServicesCode, 0x180 },\r | |
49 | { EfiBootServicesData, 0xF00 },\r | |
49ba9447 | 50 | { EfiMaxMemoryType, 0x000 }\r |
51 | };\r | |
52 | \r | |
53 | \r | |
9ed65b10 | 54 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r |
55 | {\r | |
56 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
57 | &gEfiPeiMasterBootModePpiGuid,\r | |
58 | NULL\r | |
59 | }\r | |
60 | };\r | |
61 | \r | |
62 | \r | |
589756c7 PA |
63 | UINT16 mHostBridgeDevId;\r |
64 | \r | |
979420df JJ |
65 | EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r |
66 | \r | |
7cdba634 JJ |
67 | BOOLEAN mS3Supported = FALSE;\r |
68 | \r | |
45a70db3 | 69 | UINT32 mMaxCpuCount;\r |
979420df | 70 | \r |
49ba9447 | 71 | VOID\r |
72 | AddIoMemoryBaseSizeHob (\r | |
73 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
74 | UINT64 MemorySize\r | |
75 | )\r | |
76 | {\r | |
991d9563 | 77 | BuildResourceDescriptorHob (\r |
78 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
49ba9447 | 79 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
80 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
81 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
991d9563 | 82 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 83 | MemoryBase,\r |
84 | MemorySize\r | |
85 | );\r | |
86 | }\r | |
87 | \r | |
eec7d420 | 88 | VOID\r |
89 | AddReservedMemoryBaseSizeHob (\r | |
90 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
cdef34ec LE |
91 | UINT64 MemorySize,\r |
92 | BOOLEAN Cacheable\r | |
eec7d420 | 93 | )\r |
94 | {\r | |
95 | BuildResourceDescriptorHob (\r | |
96 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
97 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
98 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
99 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
cdef34ec LE |
100 | (Cacheable ?\r |
101 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
102 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
103 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r | |
104 | 0\r | |
105 | ) |\r | |
eec7d420 | 106 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
107 | MemoryBase,\r | |
108 | MemorySize\r | |
109 | );\r | |
110 | }\r | |
49ba9447 | 111 | \r |
112 | VOID\r | |
113 | AddIoMemoryRangeHob (\r | |
114 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
115 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
116 | )\r | |
117 | {\r | |
118 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
119 | }\r | |
120 | \r | |
121 | \r | |
122 | VOID\r | |
123 | AddMemoryBaseSizeHob (\r | |
124 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
125 | UINT64 MemorySize\r | |
126 | )\r | |
127 | {\r | |
991d9563 | 128 | BuildResourceDescriptorHob (\r |
129 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
49ba9447 | 130 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
131 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
132 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
133 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
134 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
135 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
991d9563 | 136 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 137 | MemoryBase,\r |
138 | MemorySize\r | |
139 | );\r | |
140 | }\r | |
141 | \r | |
142 | \r | |
143 | VOID\r | |
144 | AddMemoryRangeHob (\r | |
145 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
146 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
147 | )\r | |
148 | {\r | |
149 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
150 | }\r | |
151 | \r | |
c0e10976 | 152 | \r |
bb6a9a93 | 153 | VOID\r |
4b455f7b | 154 | MemMapInitialization (\r |
bb6a9a93 WL |
155 | VOID\r |
156 | )\r | |
157 | {\r | |
32e083c7 LE |
158 | UINT64 PciIoBase;\r |
159 | UINT64 PciIoSize;\r | |
160 | RETURN_STATUS PcdStatus;\r | |
c4df7fd0 LE |
161 | \r |
162 | PciIoBase = 0xC000;\r | |
163 | PciIoSize = 0x4000;\r | |
164 | \r | |
bb6a9a93 WL |
165 | //\r |
166 | // Create Memory Type Information HOB\r | |
167 | //\r | |
168 | BuildGuidDataHob (\r | |
169 | &gEfiMemoryTypeInformationGuid,\r | |
170 | mDefaultMemoryTypeInformation,\r | |
171 | sizeof(mDefaultMemoryTypeInformation)\r | |
172 | );\r | |
173 | \r | |
bb6a9a93 WL |
174 | //\r |
175 | // Video memory + Legacy BIOS region\r | |
176 | //\r | |
177 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
178 | \r | |
4b455f7b | 179 | if (!mXen) {\r |
305cd4f7 | 180 | UINT32 TopOfLowRam;\r |
7b8fe635 | 181 | UINT64 PciExBarBase;\r |
c68d3a69 | 182 | UINT32 PciBase;\r |
03845e90 | 183 | UINT32 PciSize;\r |
c68d3a69 | 184 | \r |
305cd4f7 | 185 | TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r |
02d6f4ce | 186 | PciExBarBase = 0;\r |
c68d3a69 LE |
187 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
188 | //\r | |
eb4d62b0 LE |
189 | // The MMCONFIG area is expected to fall between the top of low RAM and\r |
190 | // the base of the 32-bit PCI host aperture.\r | |
c68d3a69 | 191 | //\r |
7b8fe635 | 192 | PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r |
eb4d62b0 | 193 | ASSERT (TopOfLowRam <= PciExBarBase);\r |
7b8fe635 | 194 | ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r |
eb4d62b0 | 195 | PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r |
c68d3a69 | 196 | } else {\r |
49edde15 LE |
197 | ASSERT (TopOfLowRam <= mQemuUc32Base);\r |
198 | PciBase = mQemuUc32Base;\r | |
c68d3a69 | 199 | }\r |
49ba9447 | 200 | \r |
4b455f7b JJ |
201 | //\r |
202 | // address purpose size\r | |
203 | // ------------ -------- -------------------------\r | |
204 | // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r | |
205 | // 0xFC000000 gap 44 MB\r | |
206 | // 0xFEC00000 IO-APIC 4 KB\r | |
207 | // 0xFEC01000 gap 1020 KB\r | |
208 | // 0xFED00000 HPET 1 KB\r | |
90721ba5 PA |
209 | // 0xFED00400 gap 111 KB\r |
210 | // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r | |
211 | // 0xFED20000 gap 896 KB\r | |
4b455f7b JJ |
212 | // 0xFEE00000 LAPIC 1 MB\r |
213 | //\r | |
d4534984 | 214 | PciSize = 0xFC000000 - PciBase;\r |
03845e90 | 215 | AddIoMemoryBaseSizeHob (PciBase, PciSize);\r |
32e083c7 LE |
216 | PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r |
217 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
218 | PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r | |
219 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
220 | \r | |
4b455f7b JJ |
221 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r |
222 | AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r | |
90721ba5 PA |
223 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
224 | AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r | |
7b8fe635 LE |
225 | //\r |
226 | // Note: there should be an\r | |
227 | //\r | |
228 | // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r | |
229 | //\r | |
230 | // call below, just like the one above for RCBA. However, Linux insists\r | |
231 | // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r | |
232 | // "reserved memory" -- Linux does not content itself with a simple gap\r | |
233 | // in the memory map wherever the MCFG ACPI table points to.\r | |
234 | //\r | |
235 | // This appears to be a safety measure. The PCI Firmware Specification\r | |
236 | // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r | |
237 | // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r | |
238 | // [...]". (Emphasis added here.)\r | |
239 | //\r | |
240 | // Normally we add memory resource descriptor HOBs in\r | |
241 | // QemuInitializeRam(), and pre-allocate from those with memory\r | |
242 | // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r | |
243 | // is most definitely not RAM; so, as an exception, cover it with\r | |
244 | // uncacheable reserved memory right here.\r | |
245 | //\r | |
246 | AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r | |
247 | BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r | |
248 | EfiReservedMemoryType);\r | |
90721ba5 | 249 | }\r |
4b455f7b | 250 | AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r |
bba734ab LE |
251 | \r |
252 | //\r | |
253 | // On Q35, the IO Port space is available for PCI resource allocations from\r | |
254 | // 0x6000 up.\r | |
255 | //\r | |
256 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
257 | PciIoBase = 0x6000;\r | |
258 | PciIoSize = 0xA000;\r | |
259 | ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r | |
260 | }\r | |
4b455f7b | 261 | }\r |
c4df7fd0 LE |
262 | \r |
263 | //\r | |
264 | // Add PCI IO Port space available for PCI resource allocations.\r | |
265 | //\r | |
266 | BuildResourceDescriptorHob (\r | |
267 | EFI_RESOURCE_IO,\r | |
268 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
269 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
270 | PciIoBase,\r | |
271 | PciIoSize\r | |
272 | );\r | |
32e083c7 LE |
273 | PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r |
274 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
275 | PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r | |
276 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
49ba9447 | 277 | }\r |
278 | \r | |
ab081a50 LE |
279 | EFI_STATUS\r |
280 | GetNamedFwCfgBoolean (\r | |
281 | IN CHAR8 *FwCfgFileName,\r | |
282 | OUT BOOLEAN *Setting\r | |
283 | )\r | |
284 | {\r | |
285 | EFI_STATUS Status;\r | |
286 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
287 | UINTN FwCfgSize;\r | |
288 | UINT8 Value[3];\r | |
289 | \r | |
290 | Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r | |
291 | if (EFI_ERROR (Status)) {\r | |
292 | return Status;\r | |
293 | }\r | |
294 | if (FwCfgSize > sizeof Value) {\r | |
295 | return EFI_BAD_BUFFER_SIZE;\r | |
296 | }\r | |
297 | QemuFwCfgSelectItem (FwCfgItem);\r | |
298 | QemuFwCfgReadBytes (FwCfgSize, Value);\r | |
299 | \r | |
300 | if ((FwCfgSize == 1) ||\r | |
301 | (FwCfgSize == 2 && Value[1] == '\n') ||\r | |
302 | (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r | |
303 | switch (Value[0]) {\r | |
304 | case '0':\r | |
305 | case 'n':\r | |
306 | case 'N':\r | |
307 | *Setting = FALSE;\r | |
308 | return EFI_SUCCESS;\r | |
309 | \r | |
310 | case '1':\r | |
311 | case 'y':\r | |
312 | case 'Y':\r | |
313 | *Setting = TRUE;\r | |
314 | return EFI_SUCCESS;\r | |
315 | \r | |
316 | default:\r | |
317 | break;\r | |
318 | }\r | |
319 | }\r | |
320 | return EFI_PROTOCOL_ERROR;\r | |
321 | }\r | |
322 | \r | |
323 | #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r | |
324 | do { \\r | |
32e083c7 LE |
325 | BOOLEAN Setting; \\r |
326 | RETURN_STATUS PcdStatus; \\r | |
ab081a50 LE |
327 | \\r |
328 | if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r | |
329 | "opt/ovmf/" #TokenName, &Setting))) { \\r | |
32e083c7 LE |
330 | PcdStatus = PcdSetBoolS (TokenName, Setting); \\r |
331 | ASSERT_RETURN_ERROR (PcdStatus); \\r | |
ab081a50 LE |
332 | } \\r |
333 | } while (0)\r | |
334 | \r | |
335 | VOID\r | |
336 | NoexecDxeInitialization (\r | |
337 | VOID\r | |
338 | )\r | |
339 | {\r | |
340 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r | |
341 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r | |
342 | }\r | |
49ba9447 | 343 | \r |
7b8fe635 LE |
344 | VOID\r |
345 | PciExBarInitialization (\r | |
346 | VOID\r | |
347 | )\r | |
348 | {\r | |
349 | union {\r | |
350 | UINT64 Uint64;\r | |
351 | UINT32 Uint32[2];\r | |
352 | } PciExBarBase;\r | |
353 | \r | |
354 | //\r | |
355 | // We only support the 256MB size for the MMCONFIG area:\r | |
356 | // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r | |
357 | //\r | |
358 | // The masks used below enforce the Q35 requirements that the MMCONFIG area\r | |
359 | // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r | |
360 | //\r | |
361 | // Note that (b) also ensures that the minimum address width we have\r | |
362 | // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r | |
363 | // for DXE's page tables to cover the MMCONFIG area.\r | |
364 | //\r | |
365 | PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
366 | ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r | |
367 | ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r | |
368 | \r | |
369 | //\r | |
370 | // Clear the PCIEXBAREN bit first, before programming the high register.\r | |
371 | //\r | |
372 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r | |
373 | \r | |
374 | //\r | |
375 | // Program the high register. Then program the low register, setting the\r | |
376 | // MMCONFIG area size and enabling decoding at once.\r | |
377 | //\r | |
378 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r | |
379 | PciWrite32 (\r | |
380 | DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r | |
381 | PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r | |
382 | );\r | |
383 | }\r | |
384 | \r | |
49ba9447 | 385 | VOID\r |
386 | MiscInitialization (\r | |
0e20a186 | 387 | VOID\r |
49ba9447 | 388 | )\r |
389 | {\r | |
32e083c7 LE |
390 | UINTN PmCmd;\r |
391 | UINTN Pmba;\r | |
392 | UINT32 PmbaAndVal;\r | |
393 | UINT32 PmbaOrVal;\r | |
394 | UINTN AcpiCtlReg;\r | |
395 | UINT8 AcpiEnBit;\r | |
396 | RETURN_STATUS PcdStatus;\r | |
97380beb | 397 | \r |
49ba9447 | 398 | //\r |
399 | // Disable A20 Mask\r | |
400 | //\r | |
55cdb67a | 401 | IoOr8 (0x92, BIT1);\r |
49ba9447 | 402 | \r |
403 | //\r | |
86a14b0a LE |
404 | // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r |
405 | // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r | |
406 | // S3 resume as well, so we build it unconditionally.)\r | |
49ba9447 | 407 | //\r |
86a14b0a | 408 | BuildCpuHob (mPhysMemAddressWidth, 16);\r |
c756b2ab | 409 | \r |
97380beb | 410 | //\r |
589756c7 | 411 | // Determine platform type and save Host Bridge DID to PCD\r |
97380beb | 412 | //\r |
589756c7 | 413 | switch (mHostBridgeDevId) {\r |
97380beb | 414 | case INTEL_82441_DEVICE_ID:\r |
e2ab3f81 | 415 | PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r |
da372167 | 416 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r |
1466b76f LE |
417 | PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r |
418 | PmbaOrVal = PIIX4_PMBA_VALUE;\r | |
da372167 LE |
419 | AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r |
420 | AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r | |
97380beb GS |
421 | break;\r |
422 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
e2ab3f81 | 423 | PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r |
bc9d05d6 | 424 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r |
1466b76f LE |
425 | PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r |
426 | PmbaOrVal = ICH9_PMBASE_VALUE;\r | |
bc9d05d6 LE |
427 | AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r |
428 | AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r | |
97380beb GS |
429 | break;\r |
430 | default:\r | |
431 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
589756c7 | 432 | __FUNCTION__, mHostBridgeDevId));\r |
97380beb GS |
433 | ASSERT (FALSE);\r |
434 | return;\r | |
435 | }\r | |
32e083c7 LE |
436 | PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r |
437 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
97380beb | 438 | \r |
0e20a186 | 439 | //\r |
e2ab3f81 GS |
440 | // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r |
441 | // has been configured (e.g., by Xen) and skip the setup here.\r | |
442 | // This matches the logic in AcpiTimerLibConstructor ().\r | |
0e20a186 | 443 | //\r |
e2ab3f81 | 444 | if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r |
eec7d420 | 445 | //\r |
e2ab3f81 | 446 | // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r |
931a0c74 | 447 | // 1. set PMBA\r |
eec7d420 | 448 | //\r |
1466b76f | 449 | PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r |
931a0c74 | 450 | \r |
451 | //\r | |
452 | // 2. set PCICMD/IOSE\r | |
453 | //\r | |
97380beb | 454 | PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r |
931a0c74 | 455 | \r |
456 | //\r | |
e2ab3f81 | 457 | // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r |
931a0c74 | 458 | //\r |
e2ab3f81 | 459 | PciOr8 (AcpiCtlReg, AcpiEnBit);\r |
eec7d420 | 460 | }\r |
90721ba5 PA |
461 | \r |
462 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
463 | //\r | |
464 | // Set Root Complex Register Block BAR\r | |
465 | //\r | |
466 | PciWrite32 (\r | |
467 | POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r | |
468 | ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r | |
469 | );\r | |
7b8fe635 LE |
470 | \r |
471 | //\r | |
472 | // Set PCI Express Register Range Base Address\r | |
473 | //\r | |
474 | PciExBarInitialization ();\r | |
90721ba5 | 475 | }\r |
49ba9447 | 476 | }\r |
477 | \r | |
478 | \r | |
9ed65b10 | 479 | VOID\r |
480 | BootModeInitialization (\r | |
8f5ca05b | 481 | VOID\r |
9ed65b10 | 482 | )\r |
483 | {\r | |
8f5ca05b LE |
484 | EFI_STATUS Status;\r |
485 | \r | |
486 | if (CmosRead8 (0xF) == 0xFE) {\r | |
979420df | 487 | mBootMode = BOOT_ON_S3_RESUME;\r |
8f5ca05b | 488 | }\r |
9be75189 | 489 | CmosWrite8 (0xF, 0x00);\r |
667bf1e4 | 490 | \r |
979420df | 491 | Status = PeiServicesSetBootMode (mBootMode);\r |
667bf1e4 | 492 | ASSERT_EFI_ERROR (Status);\r |
493 | \r | |
494 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
495 | ASSERT_EFI_ERROR (Status);\r | |
9ed65b10 | 496 | }\r |
497 | \r | |
498 | \r | |
77ba993c | 499 | VOID\r |
500 | ReserveEmuVariableNvStore (\r | |
501 | )\r | |
502 | {\r | |
503 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
32e083c7 | 504 | RETURN_STATUS PcdStatus;\r |
77ba993c | 505 | \r |
506 | //\r | |
507 | // Allocate storage for NV variables early on so it will be\r | |
508 | // at a consistent address. Since VM memory is preserved\r | |
509 | // across reboots, this allows the NV variable storage to survive\r | |
510 | // a VM reboot.\r | |
511 | //\r | |
512 | VariableStore =\r | |
513 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
c9e7907d LE |
514 | AllocateRuntimePages (\r |
515 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r | |
27f58ea1 | 516 | );\r |
77ba993c | 517 | DEBUG ((EFI_D_INFO,\r |
c9e7907d | 518 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r |
77ba993c | 519 | VariableStore,\r |
c9e7907d | 520 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r |
77ba993c | 521 | ));\r |
32e083c7 LE |
522 | PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r |
523 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
77ba993c | 524 | }\r |
525 | \r | |
526 | \r | |
3ca15914 | 527 | VOID\r |
528 | DebugDumpCmos (\r | |
529 | VOID\r | |
530 | )\r | |
531 | {\r | |
6394c35a | 532 | UINT32 Loop;\r |
3ca15914 | 533 | \r |
534 | DEBUG ((EFI_D_INFO, "CMOS:\n"));\r | |
535 | \r | |
536 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
537 | if ((Loop % 0x10) == 0) {\r | |
538 | DEBUG ((EFI_D_INFO, "%02x:", Loop));\r | |
539 | }\r | |
540 | DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r | |
541 | if ((Loop % 0x10) == 0xf) {\r | |
542 | DEBUG ((EFI_D_INFO, "\n"));\r | |
543 | }\r | |
544 | }\r | |
545 | }\r | |
546 | \r | |
547 | \r | |
5133d1f1 LE |
548 | VOID\r |
549 | S3Verification (\r | |
550 | VOID\r | |
551 | )\r | |
552 | {\r | |
553 | #if defined (MDE_CPU_X64)\r | |
554 | if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r | |
555 | DEBUG ((EFI_D_ERROR,\r | |
556 | "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r | |
557 | DEBUG ((EFI_D_ERROR,\r | |
558 | "%a: Please disable S3 on the QEMU command line (see the README),\n",\r | |
559 | __FUNCTION__));\r | |
560 | DEBUG ((EFI_D_ERROR,\r | |
561 | "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r | |
562 | ASSERT (FALSE);\r | |
563 | CpuDeadLoop ();\r | |
564 | }\r | |
565 | #endif\r | |
566 | }\r | |
567 | \r | |
568 | \r | |
45a70db3 | 569 | /**\r |
83357313 LE |
570 | Fetch the boot CPU count and the possible CPU count from QEMU, and expose\r |
571 | them to UefiCpuPkg modules. Set the mMaxCpuCount variable.\r | |
45a70db3 LE |
572 | **/\r |
573 | VOID\r | |
574 | MaxCpuCountInitialization (\r | |
575 | VOID\r | |
576 | )\r | |
577 | {\r | |
83357313 | 578 | UINT16 BootCpuCount;\r |
45a70db3 LE |
579 | RETURN_STATUS PcdStatus;\r |
580 | \r | |
45a70db3 | 581 | //\r |
83357313 | 582 | // Try to fetch the boot CPU count.\r |
45a70db3 | 583 | //\r |
83357313 LE |
584 | QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r |
585 | BootCpuCount = QemuFwCfgRead16 ();\r | |
586 | if (BootCpuCount == 0) {\r | |
587 | //\r | |
588 | // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let\r | |
589 | // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or\r | |
590 | // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached\r | |
591 | // first).\r | |
592 | //\r | |
593 | DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));\r | |
45a70db3 | 594 | mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r |
83357313 LE |
595 | } else {\r |
596 | //\r | |
597 | // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to\r | |
598 | // (BootCpuCount - 1) precisely, regardless of timeout.\r | |
599 | //\r | |
600 | // Now try to fetch the possible CPU count.\r | |
601 | //\r | |
602 | UINTN CpuHpBase;\r | |
603 | UINT32 CmdData2;\r | |
604 | \r | |
605 | CpuHpBase = ((mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?\r | |
606 | ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);\r | |
607 | \r | |
608 | //\r | |
609 | // If only legacy mode is available in the CPU hotplug register block, or\r | |
610 | // the register block is completely missing, then the writes below are\r | |
611 | // no-ops.\r | |
612 | //\r | |
613 | // 1. Switch the hotplug register block to modern mode.\r | |
614 | //\r | |
615 | IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);\r | |
616 | //\r | |
617 | // 2. Select a valid CPU for deterministic reading of\r | |
618 | // QEMU_CPUHP_R_CMD_DATA2.\r | |
619 | //\r | |
620 | // CPU#0 is always valid; it is the always present and non-removable\r | |
621 | // BSP.\r | |
622 | //\r | |
623 | IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);\r | |
624 | //\r | |
625 | // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to\r | |
626 | // read as zero, and which does not invalidate the selector. (The\r | |
627 | // selector may change, but it must not become invalid.)\r | |
628 | //\r | |
629 | // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.\r | |
630 | //\r | |
631 | IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING);\r | |
632 | //\r | |
633 | // 4. Read QEMU_CPUHP_R_CMD_DATA2.\r | |
634 | //\r | |
635 | // If the register block is entirely missing, then this is an unassigned\r | |
636 | // IO read, returning all-bits-one.\r | |
637 | //\r | |
638 | // If only legacy mode is available, then bit#0 stands for CPU#0 in the\r | |
639 | // "CPU present bitmap". CPU#0 is always present.\r | |
640 | //\r | |
641 | // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning\r | |
642 | // all-bits-zero), or it is specified to read as zero after the above\r | |
643 | // steps. Both cases confirm modern mode.\r | |
644 | //\r | |
645 | CmdData2 = IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2);\r | |
646 | DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=0x%x\n", __FUNCTION__, CmdData2));\r | |
647 | if (CmdData2 != 0) {\r | |
648 | //\r | |
649 | // QEMU doesn't support the modern CPU hotplug interface. Assume that the\r | |
650 | // possible CPU count equals the boot CPU count (precluding hotplug).\r | |
651 | //\r | |
652 | DEBUG ((DEBUG_WARN, "%a: modern CPU hotplug interface unavailable\n",\r | |
653 | __FUNCTION__));\r | |
654 | mMaxCpuCount = BootCpuCount;\r | |
655 | } else {\r | |
656 | //\r | |
657 | // Grab the possible CPU count from the modern CPU hotplug interface.\r | |
658 | //\r | |
659 | UINT32 Present, Possible, Selected;\r | |
660 | \r | |
661 | Present = 0;\r | |
662 | Possible = 0;\r | |
663 | \r | |
664 | //\r | |
665 | // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures\r | |
666 | // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,\r | |
667 | // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending\r | |
668 | // hotplug events; therefore, select CPU#0 forcibly.\r | |
669 | //\r | |
670 | IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);\r | |
671 | \r | |
672 | do {\r | |
673 | UINT8 CpuStatus;\r | |
674 | \r | |
675 | //\r | |
676 | // Read the status of the currently selected CPU. This will help with a\r | |
677 | // sanity check against "BootCpuCount".\r | |
678 | //\r | |
679 | CpuStatus = IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT);\r | |
680 | if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {\r | |
681 | ++Present;\r | |
682 | }\r | |
683 | //\r | |
684 | // Attempt to select the next CPU.\r | |
685 | //\r | |
686 | ++Possible;\r | |
687 | IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);\r | |
688 | //\r | |
689 | // If the selection is successful, then the following read will return\r | |
690 | // the selector (which we know is positive at this point). Otherwise,\r | |
691 | // the read will return 0.\r | |
692 | //\r | |
693 | Selected = IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA);\r | |
694 | ASSERT (Selected == Possible || Selected == 0);\r | |
695 | } while (Selected > 0);\r | |
696 | \r | |
697 | //\r | |
698 | // Sanity check: fw_cfg and the modern CPU hotplug interface should\r | |
699 | // return the same boot CPU count.\r | |
700 | //\r | |
701 | if (BootCpuCount != Present) {\r | |
702 | DEBUG ((DEBUG_WARN, "%a: QEMU v2.7 reset bug: BootCpuCount=%d "\r | |
703 | "Present=%u\n", __FUNCTION__, BootCpuCount, Present));\r | |
704 | //\r | |
705 | // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus\r | |
706 | // platform reset (including S3), was corrected in QEMU commit\r | |
707 | // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device added\r | |
708 | // CPUs", 2016-11-16), part of release v2.8.0.\r | |
709 | //\r | |
710 | BootCpuCount = (UINT16)Present;\r | |
711 | }\r | |
712 | \r | |
713 | mMaxCpuCount = Possible;\r | |
714 | }\r | |
45a70db3 | 715 | }\r |
83357313 LE |
716 | \r |
717 | DEBUG ((DEBUG_INFO, "%a: BootCpuCount=%d mMaxCpuCount=%u\n", __FUNCTION__,\r | |
718 | BootCpuCount, mMaxCpuCount));\r | |
719 | ASSERT (BootCpuCount <= mMaxCpuCount);\r | |
720 | \r | |
721 | PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);\r | |
45a70db3 | 722 | ASSERT_RETURN_ERROR (PcdStatus);\r |
83357313 | 723 | PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, mMaxCpuCount);\r |
45a70db3 | 724 | ASSERT_RETURN_ERROR (PcdStatus);\r |
45a70db3 LE |
725 | }\r |
726 | \r | |
727 | \r | |
49ba9447 | 728 | /**\r |
729 | Perform Platform PEI initialization.\r | |
730 | \r | |
731 | @param FileHandle Handle of the file being invoked.\r | |
732 | @param PeiServices Describes the list of possible PEI Services.\r | |
733 | \r | |
734 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
735 | \r | |
736 | **/\r | |
737 | EFI_STATUS\r | |
738 | EFIAPI\r | |
739 | InitializePlatform (\r | |
740 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
741 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
742 | )\r | |
743 | {\r | |
a1726e30 SZ |
744 | EFI_STATUS Status;\r |
745 | \r | |
7707c9fd | 746 | DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r |
49ba9447 | 747 | \r |
3ca15914 | 748 | DebugDumpCmos ();\r |
749 | \r | |
b98b4941 | 750 | XenDetect ();\r |
c7ea55b9 | 751 | \r |
7cdba634 JJ |
752 | if (QemuFwCfgS3Enabled ()) {\r |
753 | DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r | |
754 | mS3Supported = TRUE;\r | |
a1726e30 SZ |
755 | Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r |
756 | ASSERT_EFI_ERROR (Status);\r | |
7cdba634 JJ |
757 | }\r |
758 | \r | |
5133d1f1 | 759 | S3Verification ();\r |
869b17cc | 760 | BootModeInitialization ();\r |
bc89fe48 | 761 | AddressWidthInitialization ();\r |
869b17cc | 762 | \r |
d5e06444 LE |
763 | //\r |
764 | // Query Host Bridge DID\r | |
765 | //\r | |
766 | mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
767 | \r | |
83357313 LE |
768 | MaxCpuCountInitialization ();\r |
769 | \r | |
23bfb5c0 LE |
770 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r |
771 | Q35TsegMbytesInitialization ();\r | |
772 | }\r | |
773 | \r | |
f76e9eba JJ |
774 | PublishPeiMemory ();\r |
775 | \r | |
49edde15 LE |
776 | QemuUc32BaseInitialization ();\r |
777 | \r | |
2818c158 | 778 | InitializeRamRegions ();\r |
49ba9447 | 779 | \r |
b621bb0a | 780 | if (mXen) {\r |
c7ea55b9 | 781 | DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r |
b98b4941 | 782 | InitializeXen ();\r |
c7ea55b9 | 783 | }\r |
eec7d420 | 784 | \r |
bd386eaf | 785 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
5e167d7e LE |
786 | if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r |
787 | ReserveEmuVariableNvStore ();\r | |
788 | }\r | |
bd386eaf | 789 | PeiFvInitialization ();\r |
bd386eaf | 790 | MemMapInitialization ();\r |
ab081a50 | 791 | NoexecDxeInitialization ();\r |
bd386eaf | 792 | }\r |
49ba9447 | 793 | \r |
d20ae95a | 794 | InstallClearCacheCallback ();\r |
13b5d743 | 795 | AmdSevInitialize ();\r |
0e20a186 | 796 | MiscInitialization ();\r |
dbab9949 | 797 | InstallFeatureControlCallback ();\r |
49ba9447 | 798 | \r |
799 | return EFI_SUCCESS;\r | |
800 | }\r |