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target-i386: kvm_check_features_against_host(): Use feature_word_info
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
c6dc6f63 26
1de7afc9
PB		 27#include "qemu/option.h"
28#include "qemu/config-file.h"
7b1b5d19 29#include "qapi/qmp/qerror.h"
c6dc6f63 30
7b1b5d19 31#include "qapi/visitor.h"
9c17d615 32#include "sysemu/arch_init.h"
71ad61d3 33
28f52cc0
VR		 34#include "hyperv.h"
35
65dee380 36#include "hw/hw.h"
b834b508 37#if defined(CONFIG_KVM)
ef8621b1 38#include <linux/kvm_para.h>
b834b508 39#endif
65dee380 40
9c17d615 41#include "sysemu/sysemu.h"
bdeec802
IM		 42#ifndef CONFIG_USER_ONLY
43#include "hw/xen.h"
44#include "hw/sysbus.h"
449994eb 45#include "hw/apic_internal.h"
bdeec802
IM		 46#endif
47
c6dc6f63
AP		 48/* feature flags taken from "Intel Processor Identification and the CPUID
49 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
50 * between feature naming conventions, aliases may be added.
51 */
52static const char *feature_name[] = {
53 "fpu", "vme", "de", "pse",
54 "tsc", "msr", "pae", "mce",
55 "cx8", "apic", NULL, "sep",
56 "mtrr", "pge", "mca", "cmov",
57 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
58 NULL, "ds" /* Intel dts */, "acpi", "mmx",
59 "fxsr", "sse", "sse2", "ss",
60 "ht" /* Intel htt */, "tm", "ia64", "pbe",
61};
62static const char *ext_feature_name[] = {
f370be3c 63 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 64 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 65 "tm2", "ssse3", "cid", NULL,
e117f772 66 "fma", "cx16", "xtpr", "pdcm",
434acb81 67 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 68 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 69 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 70 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 71};
3b671a40
EH		 72/* Feature names that are already defined on feature_name[] but are set on
73 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
74 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
75 * if and only if CPU vendor is AMD.
76 */
c6dc6f63 77static const char *ext2_feature_name[] = {
3b671a40
EH		 78 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
79 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
80 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
81 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
82 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
83 "nx|xd", NULL, "mmxext", NULL /* mmx */,
84 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 85 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 86};
87static const char *ext3_feature_name[] = {
88 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
89 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 90 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 91 "skinit", "wdt", NULL, "lwp",
92 "fma4", "tce", NULL, "nodeid_msr",
93 NULL, "tbm", "topoext", "perfctr_core",
94 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 95 NULL, NULL, NULL, NULL,
96};
97
98static const char *kvm_feature_name[] = {
c3d39807
DS		 99 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
100 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 107};
108
296acb64
JR		 109static const char *svm_feature_name[] = {
110 "npt", "lbrv", "svm_lock", "nrip_save",
111 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
112 NULL, NULL, "pause_filter", NULL,
113 "pfthreshold", NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
118};
119
a9321a4d 120static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 121 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
122 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 123 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 124 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
125};
126
5ef57876
EH		 127typedef struct FeatureWordInfo {
128 const char **feat_names;
bffd67b0
EH		 129 uint32_t cpuid_eax; /* Input EAX for CPUID */
130 int cpuid_reg; /* R_* register constant */
5ef57876
EH		 131} FeatureWordInfo;
132
133static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 134 [FEAT_1_EDX] = {
135 .feat_names = feature_name,
136 .cpuid_eax = 1, .cpuid_reg = R_EDX,
137 },
138 [FEAT_1_ECX] = {
139 .feat_names = ext_feature_name,
140 .cpuid_eax = 1, .cpuid_reg = R_ECX,
141 },
142 [FEAT_8000_0001_EDX] = {
143 .feat_names = ext2_feature_name,
144 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
145 },
146 [FEAT_8000_0001_ECX] = {
147 .feat_names = ext3_feature_name,
148 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
149 },
150 [FEAT_KVM] = {
151 .feat_names = kvm_feature_name,
152 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
153 },
154 [FEAT_SVM] = {
155 .feat_names = svm_feature_name,
156 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
157 },
158 [FEAT_7_0_EBX] = {
159 .feat_names = cpuid_7_0_ebx_feature_name,
160 .cpuid_eax = 7, .cpuid_reg = R_EBX,
161 },
5ef57876
EH		 162};
163
8b4beddc
EH		 164const char *get_register_name_32(unsigned int reg)
165{
166 static const char *reg_names[CPU_NB_REGS32] = {
167 [R_EAX] = "EAX",
168 [R_ECX] = "ECX",
169 [R_EDX] = "EDX",
170 [R_EBX] = "EBX",
171 [R_ESP] = "ESP",
172 [R_EBP] = "EBP",
173 [R_ESI] = "ESI",
174 [R_EDI] = "EDI",
175 };
176
177 if (reg > CPU_NB_REGS32) {
178 return NULL;
179 }
180 return reg_names[reg];
181}
182
c6dc6f63
AP		 183/* collects per-function cpuid data
184 */
185typedef struct model_features_t {
186 uint32_t *guest_feat;
187 uint32_t *host_feat;
bffd67b0 188 FeatureWord feat_word;
8b4beddc 189} model_features_t;
c6dc6f63
AP		 190
191int check_cpuid = 0;
192int enforce_cpuid = 0;
193
dc59944b
MT		 194#if defined(CONFIG_KVM)
195static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
196 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 197 (1 << KVM_FEATURE_CLOCKSOURCE2) |
198 (1 << KVM_FEATURE_ASYNC_PF) |
199 (1 << KVM_FEATURE_STEAL_TIME) |
200 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
201static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
202#else
203static uint32_t kvm_default_features = 0;
204static const uint32_t kvm_pv_eoi_features = 0;
205#endif
206
207void enable_kvm_pv_eoi(void)
208{
209 kvm_default_features |= kvm_pv_eoi_features;
210}
211
bb44e0d1
JK		 212void host_cpuid(uint32_t function, uint32_t count,
213 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 214{
215#if defined(CONFIG_KVM)
a1fd24af
AL		 216 uint32_t vec[4];
217
218#ifdef __x86_64__
219 asm volatile("cpuid"
220 : "=a"(vec[0]), "=b"(vec[1]),
221 "=c"(vec[2]), "=d"(vec[3])
222 : "0"(function), "c"(count) : "cc");
223#else
224 asm volatile("pusha \n\t"
225 "cpuid \n\t"
226 "mov %%eax, 0(%2) \n\t"
227 "mov %%ebx, 4(%2) \n\t"
228 "mov %%ecx, 8(%2) \n\t"
229 "mov %%edx, 12(%2) \n\t"
230 "popa"
231 : : "a"(function), "c"(count), "S"(vec)
232 : "memory", "cc");
233#endif
234
bdde476a 235 if (eax)
a1fd24af 236 *eax = vec[0];
bdde476a 237 if (ebx)
a1fd24af 238 *ebx = vec[1];
bdde476a 239 if (ecx)
a1fd24af 240 *ecx = vec[2];
bdde476a 241 if (edx)
a1fd24af 242 *edx = vec[3];
bdde476a
AP		 243#endif
244}
c6dc6f63
AP		 245
246#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
247
248/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
249 * a substring. ex if !NULL points to the first char after a substring,
250 * otherwise the string is assumed to sized by a terminating nul.
251 * Return lexical ordering of *s1:*s2.
252 */
253static int sstrcmp(const char *s1, const char *e1, const char *s2,
254 const char *e2)
255{
256 for (;;) {
257 if (!*s1 || !*s2 || *s1 != *s2)
258 return (*s1 - *s2);
259 ++s1, ++s2;
260 if (s1 == e1 && s2 == e2)
261 return (0);
262 else if (s1 == e1)
263 return (*s2);
264 else if (s2 == e2)
265 return (*s1);
266 }
267}
268
269/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
270 * '|' delimited (possibly empty) strings in which case search for a match
271 * within the alternatives proceeds left to right. Return 0 for success,
272 * non-zero otherwise.
273 */
274static int altcmp(const char *s, const char *e, const char *altstr)
275{
276 const char *p, *q;
277
278 for (q = p = altstr; ; ) {
279 while (*p && *p != '|')
280 ++p;
281 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
282 return (0);
283 if (!*p)
284 return (1);
285 else
286 q = ++p;
287 }
288}
289
290/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 291 * *pval and return true, otherwise return false
c6dc6f63 292 */
e41e0fc6
JK		 293static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
294 const char **featureset)
c6dc6f63
AP		 295{
296 uint32_t mask;
297 const char **ppc;
e41e0fc6 298 bool found = false;
c6dc6f63 299
e41e0fc6 300 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 301 if (*ppc && !altcmp(s, e, *ppc)) {
302 *pval |= mask;
e41e0fc6 303 found = true;
c6dc6f63 304 }
e41e0fc6
JK		 305 }
306 return found;
c6dc6f63
AP		 307}
308
5ef57876
EH		 309static void add_flagname_to_bitmaps(const char *flagname,
310 FeatureWordArray words)
c6dc6f63 311{
5ef57876
EH		 312 FeatureWord w;
313 for (w = 0; w < FEATURE_WORDS; w++) {
314 FeatureWordInfo *wi = &feature_word_info[w];
315 if (wi->feat_names &&
316 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
317 break;
318 }
319 }
320 if (w == FEATURE_WORDS) {
321 fprintf(stderr, "CPU feature %s not found\n", flagname);
322 }
c6dc6f63
AP		 323}
324
325typedef struct x86_def_t {
326 struct x86_def_t *next;
327 const char *name;
328 uint32_t level;
329 uint32_t vendor1, vendor2, vendor3;
330 int family;
331 int model;
332 int stepping;
b862d1fe 333 int tsc_khz;
296acb64
JR		 334 uint32_t features, ext_features, ext2_features, ext3_features;
335 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 336 uint32_t xlevel;
337 char model_id[48];
338 int vendor_override;
b3baa152
BW		 339 /* Store the results of Centaur's CPUID instructions */
340 uint32_t ext4_features;
341 uint32_t xlevel2;
13526728
EH		 342 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
343 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 344} x86_def_t;
345
346#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
347#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
348 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
349#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
350 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
351 CPUID_PSE36 | CPUID_FXSR)
352#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
353#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
354 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
355 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
356 CPUID_PAE | CPUID_SEP | CPUID_APIC)
357
551a2dec
AP		 358#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
359 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
360 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
361 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
362 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 363 /* partly implemented:
364 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
365 CPUID_PSE36 (needed for Solaris) */
366 /* missing:
367 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 368#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
a0a70681 369 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 370 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 371 /* missing:
372 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 373 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
60032ac0 374#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 375 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
376 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 377 /* missing:
378 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 379#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
380 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 381#define TCG_SVM_FEATURES 0
a9321a4d 382#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
551a2dec 383
c6dc6f63
AP		 384/* maintains list of cpu model definitions
385 */
386static x86_def_t *x86_defs = {NULL};
387
388/* built-in cpu model definitions (deprecated)
389 */
390static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 391 {
392 .name = "qemu64",
393 .level = 4,
394 .vendor1 = CPUID_VENDOR_AMD_1,
395 .vendor2 = CPUID_VENDOR_AMD_2,
396 .vendor3 = CPUID_VENDOR_AMD_3,
397 .family = 6,
398 .model = 2,
399 .stepping = 3,
400 .features = PPRO_FEATURES |
c6dc6f63 401 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 402 CPUID_PSE36,
403 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
60032ac0 404 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 405 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
406 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
407 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
408 .xlevel = 0x8000000A,
c6dc6f63
AP		 409 },
410 {
411 .name = "phenom",
412 .level = 5,
413 .vendor1 = CPUID_VENDOR_AMD_1,
414 .vendor2 = CPUID_VENDOR_AMD_2,
415 .vendor3 = CPUID_VENDOR_AMD_3,
416 .family = 16,
417 .model = 2,
418 .stepping = 3,
c6dc6f63
AP		 419 .features = PPRO_FEATURES |
420 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 421 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 422 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
423 CPUID_EXT_POPCNT,
60032ac0 424 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 425 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
426 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 427 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 428 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
429 CPUID_EXT3_CR8LEG,
430 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
431 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
432 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
433 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 434 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 435 .xlevel = 0x8000001A,
436 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
437 },
438 {
439 .name = "core2duo",
440 .level = 10,
ebe8b9c6
IM		 441 .vendor1 = CPUID_VENDOR_INTEL_1,
442 .vendor2 = CPUID_VENDOR_INTEL_2,
443 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 444 .family = 6,
445 .model = 15,
446 .stepping = 11,
c6dc6f63
AP		 447 .features = PPRO_FEATURES |
448 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 449 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
450 CPUID_HT | CPUID_TM | CPUID_PBE,
451 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
452 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
453 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 454 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
455 .ext3_features = CPUID_EXT3_LAHF_LM,
456 .xlevel = 0x80000008,
457 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
458 },
459 {
460 .name = "kvm64",
461 .level = 5,
462 .vendor1 = CPUID_VENDOR_INTEL_1,
463 .vendor2 = CPUID_VENDOR_INTEL_2,
464 .vendor3 = CPUID_VENDOR_INTEL_3,
465 .family = 15,
466 .model = 6,
467 .stepping = 1,
468 /* Missing: CPUID_VME, CPUID_HT */
469 .features = PPRO_FEATURES |
470 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
471 CPUID_PSE36,
472 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
473 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
474 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
60032ac0 475 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 476 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
477 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
478 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
479 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
480 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
481 .ext3_features = 0,
482 .xlevel = 0x80000008,
483 .model_id = "Common KVM processor"
484 },
c6dc6f63
AP		 485 {
486 .name = "qemu32",
487 .level = 4,
ebe8b9c6
IM		 488 .vendor1 = CPUID_VENDOR_INTEL_1,
489 .vendor2 = CPUID_VENDOR_INTEL_2,
490 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 491 .family = 6,
492 .model = 3,
493 .stepping = 3,
494 .features = PPRO_FEATURES,
495 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 496 .xlevel = 0x80000004,
c6dc6f63 497 },
eafaf1e5
AP		 498 {
499 .name = "kvm32",
500 .level = 5,
ebe8b9c6
IM		 501 .vendor1 = CPUID_VENDOR_INTEL_1,
502 .vendor2 = CPUID_VENDOR_INTEL_2,
503 .vendor3 = CPUID_VENDOR_INTEL_3,
eafaf1e5
AP		 504 .family = 15,
505 .model = 6,
506 .stepping = 1,
507 .features = PPRO_FEATURES |
508 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
509 .ext_features = CPUID_EXT_SSE3,
60032ac0 510 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
eafaf1e5
AP		 511 .ext3_features = 0,
512 .xlevel = 0x80000008,
513 .model_id = "Common 32-bit KVM processor"
514 },
c6dc6f63
AP		 515 {
516 .name = "coreduo",
517 .level = 10,
ebe8b9c6
IM		 518 .vendor1 = CPUID_VENDOR_INTEL_1,
519 .vendor2 = CPUID_VENDOR_INTEL_2,
520 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 521 .family = 6,
522 .model = 14,
523 .stepping = 8,
c6dc6f63 524 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 525 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
526 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
527 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
528 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 529 .ext2_features = CPUID_EXT2_NX,
530 .xlevel = 0x80000008,
531 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
532 },
533 {
534 .name = "486",
58012d66 535 .level = 1,
ebe8b9c6
IM		 536 .vendor1 = CPUID_VENDOR_INTEL_1,
537 .vendor2 = CPUID_VENDOR_INTEL_2,
538 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 539 .family = 4,
540 .model = 0,
541 .stepping = 0,
542 .features = I486_FEATURES,
543 .xlevel = 0,
544 },
545 {
546 .name = "pentium",
547 .level = 1,
ebe8b9c6
IM		 548 .vendor1 = CPUID_VENDOR_INTEL_1,
549 .vendor2 = CPUID_VENDOR_INTEL_2,
550 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 551 .family = 5,
552 .model = 4,
553 .stepping = 3,
554 .features = PENTIUM_FEATURES,
555 .xlevel = 0,
556 },
557 {
558 .name = "pentium2",
559 .level = 2,
ebe8b9c6
IM		 560 .vendor1 = CPUID_VENDOR_INTEL_1,
561 .vendor2 = CPUID_VENDOR_INTEL_2,
562 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 563 .family = 6,
564 .model = 5,
565 .stepping = 2,
566 .features = PENTIUM2_FEATURES,
567 .xlevel = 0,
568 },
569 {
570 .name = "pentium3",
571 .level = 2,
ebe8b9c6
IM		 572 .vendor1 = CPUID_VENDOR_INTEL_1,
573 .vendor2 = CPUID_VENDOR_INTEL_2,
574 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 575 .family = 6,
576 .model = 7,
577 .stepping = 3,
578 .features = PENTIUM3_FEATURES,
579 .xlevel = 0,
580 },
581 {
582 .name = "athlon",
583 .level = 2,
584 .vendor1 = CPUID_VENDOR_AMD_1,
585 .vendor2 = CPUID_VENDOR_AMD_2,
586 .vendor3 = CPUID_VENDOR_AMD_3,
587 .family = 6,
588 .model = 2,
589 .stepping = 3,
60032ac0
EH		 590 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
591 CPUID_MCA,
592 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
593 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 594 .xlevel = 0x80000008,
c6dc6f63
AP		 595 },
596 {
597 .name = "n270",
598 /* original is on level 10 */
599 .level = 5,
ebe8b9c6
IM		 600 .vendor1 = CPUID_VENDOR_INTEL_1,
601 .vendor2 = CPUID_VENDOR_INTEL_2,
602 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 603 .family = 6,
604 .model = 28,
605 .stepping = 2,
606 .features = PPRO_FEATURES |
8560efed
AJ		 607 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
608 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 609 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 610 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
611 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
60032ac0
EH		 612 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
613 CPUID_EXT2_NX,
8560efed 614 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 615 .xlevel = 0x8000000A,
616 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
617 },
3eca4642
EH		 618 {
619 .name = "Conroe",
620 .level = 2,
621 .vendor1 = CPUID_VENDOR_INTEL_1,
622 .vendor2 = CPUID_VENDOR_INTEL_2,
623 .vendor3 = CPUID_VENDOR_INTEL_3,
624 .family = 6,
625 .model = 2,
626 .stepping = 3,
627 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
628 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
629 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
630 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
631 CPUID_DE | CPUID_FP87,
632 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
633 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
634 .ext3_features = CPUID_EXT3_LAHF_LM,
635 .xlevel = 0x8000000A,
636 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
637 },
638 {
639 .name = "Penryn",
640 .level = 2,
641 .vendor1 = CPUID_VENDOR_INTEL_1,
642 .vendor2 = CPUID_VENDOR_INTEL_2,
643 .vendor3 = CPUID_VENDOR_INTEL_3,
644 .family = 6,
645 .model = 2,
646 .stepping = 3,
647 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
648 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
649 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
650 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
651 CPUID_DE | CPUID_FP87,
652 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
653 CPUID_EXT_SSE3,
654 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
655 .ext3_features = CPUID_EXT3_LAHF_LM,
656 .xlevel = 0x8000000A,
657 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
658 },
659 {
660 .name = "Nehalem",
661 .level = 2,
662 .vendor1 = CPUID_VENDOR_INTEL_1,
663 .vendor2 = CPUID_VENDOR_INTEL_2,
664 .vendor3 = CPUID_VENDOR_INTEL_3,
665 .family = 6,
666 .model = 2,
667 .stepping = 3,
668 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
669 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
670 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
671 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
672 CPUID_DE | CPUID_FP87,
673 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
674 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
675 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
676 .ext3_features = CPUID_EXT3_LAHF_LM,
677 .xlevel = 0x8000000A,
678 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
679 },
680 {
681 .name = "Westmere",
682 .level = 11,
683 .vendor1 = CPUID_VENDOR_INTEL_1,
684 .vendor2 = CPUID_VENDOR_INTEL_2,
685 .vendor3 = CPUID_VENDOR_INTEL_3,
686 .family = 6,
687 .model = 44,
688 .stepping = 1,
689 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
690 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
691 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
692 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
693 CPUID_DE | CPUID_FP87,
694 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
695 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
696 CPUID_EXT_SSE3,
697 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
698 .ext3_features = CPUID_EXT3_LAHF_LM,
699 .xlevel = 0x8000000A,
700 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
701 },
702 {
703 .name = "SandyBridge",
704 .level = 0xd,
705 .vendor1 = CPUID_VENDOR_INTEL_1,
706 .vendor2 = CPUID_VENDOR_INTEL_2,
707 .vendor3 = CPUID_VENDOR_INTEL_3,
708 .family = 6,
709 .model = 42,
710 .stepping = 1,
711 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
712 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
713 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
714 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
715 CPUID_DE | CPUID_FP87,
716 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
717 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
718 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
719 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
720 CPUID_EXT_SSE3,
721 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
722 CPUID_EXT2_SYSCALL,
723 .ext3_features = CPUID_EXT3_LAHF_LM,
724 .xlevel = 0x8000000A,
725 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
726 },
37507094
EH		 727 {
728 .name = "Haswell",
729 .level = 0xd,
730 .vendor1 = CPUID_VENDOR_INTEL_1,
731 .vendor2 = CPUID_VENDOR_INTEL_2,
732 .vendor3 = CPUID_VENDOR_INTEL_3,
733 .family = 6,
734 .model = 60,
735 .stepping = 1,
736 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
737 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 738 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 739 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
740 CPUID_DE | CPUID_FP87,
741 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
742 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
743 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
744 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
745 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
746 CPUID_EXT_PCID,
80ae4160
EH		 747 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
748 CPUID_EXT2_SYSCALL,
37507094
EH		 749 .ext3_features = CPUID_EXT3_LAHF_LM,
750 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
751 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
752 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
753 CPUID_7_0_EBX_RTM,
754 .xlevel = 0x8000000A,
755 .model_id = "Intel Core Processor (Haswell)",
756 },
3eca4642
EH		 757 {
758 .name = "Opteron_G1",
759 .level = 5,
760 .vendor1 = CPUID_VENDOR_AMD_1,
761 .vendor2 = CPUID_VENDOR_AMD_2,
762 .vendor3 = CPUID_VENDOR_AMD_3,
763 .family = 15,
764 .model = 6,
765 .stepping = 1,
766 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
767 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
768 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
769 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
770 CPUID_DE | CPUID_FP87,
771 .ext_features = CPUID_EXT_SSE3,
772 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
773 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
774 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
775 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
776 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
777 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
778 .xlevel = 0x80000008,
779 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
780 },
781 {
782 .name = "Opteron_G2",
783 .level = 5,
784 .vendor1 = CPUID_VENDOR_AMD_1,
785 .vendor2 = CPUID_VENDOR_AMD_2,
786 .vendor3 = CPUID_VENDOR_AMD_3,
787 .family = 15,
788 .model = 6,
789 .stepping = 1,
790 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
791 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
792 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
793 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
794 CPUID_DE | CPUID_FP87,
795 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
796 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
797 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
798 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
799 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
800 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
801 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
802 CPUID_EXT2_DE | CPUID_EXT2_FPU,
803 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
804 .xlevel = 0x80000008,
805 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
806 },
807 {
808 .name = "Opteron_G3",
809 .level = 5,
810 .vendor1 = CPUID_VENDOR_AMD_1,
811 .vendor2 = CPUID_VENDOR_AMD_2,
812 .vendor3 = CPUID_VENDOR_AMD_3,
813 .family = 15,
814 .model = 6,
815 .stepping = 1,
816 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
817 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
818 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
819 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
820 CPUID_DE | CPUID_FP87,
821 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
822 CPUID_EXT_SSE3,
823 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
824 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
825 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
826 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
827 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
828 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
829 CPUID_EXT2_DE | CPUID_EXT2_FPU,
830 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
831 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
832 .xlevel = 0x80000008,
833 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
834 },
835 {
836 .name = "Opteron_G4",
837 .level = 0xd,
838 .vendor1 = CPUID_VENDOR_AMD_1,
839 .vendor2 = CPUID_VENDOR_AMD_2,
840 .vendor3 = CPUID_VENDOR_AMD_3,
841 .family = 21,
842 .model = 1,
843 .stepping = 2,
844 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
845 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
846 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
847 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
848 CPUID_DE | CPUID_FP87,
849 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
850 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
851 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
852 CPUID_EXT_SSE3,
853 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
854 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
855 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
856 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
857 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
858 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
859 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
860 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
861 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
862 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
863 CPUID_EXT3_LAHF_LM,
864 .xlevel = 0x8000001A,
865 .model_id = "AMD Opteron 62xx class CPU",
866 },
021941b9
AP		 867 {
868 .name = "Opteron_G5",
869 .level = 0xd,
870 .vendor1 = CPUID_VENDOR_AMD_1,
871 .vendor2 = CPUID_VENDOR_AMD_2,
872 .vendor3 = CPUID_VENDOR_AMD_3,
873 .family = 21,
874 .model = 2,
875 .stepping = 0,
876 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
877 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
878 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
879 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
880 CPUID_DE | CPUID_FP87,
881 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
882 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
883 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
884 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
885 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
886 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
887 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
888 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
889 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
890 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
891 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
892 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
893 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
894 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
895 CPUID_EXT3_LAHF_LM,
896 .xlevel = 0x8000001A,
897 .model_id = "AMD Opteron 63xx class CPU",
898 },
c6dc6f63
AP		 899};
900
e4ab0d6b 901#ifdef CONFIG_KVM
c6dc6f63
AP		 902static int cpu_x86_fill_model_id(char *str)
903{
904 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
905 int i;
906
907 for (i = 0; i < 3; i++) {
908 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
909 memcpy(str + i * 16 + 0, &eax, 4);
910 memcpy(str + i * 16 + 4, &ebx, 4);
911 memcpy(str + i * 16 + 8, &ecx, 4);
912 memcpy(str + i * 16 + 12, &edx, 4);
913 }
914 return 0;
915}
e4ab0d6b 916#endif
c6dc6f63 917
6e746f30
EH		 918/* Fill a x86_def_t struct with information about the host CPU, and
919 * the CPU features supported by the host hardware + host kernel
920 *
921 * This function may be called only if KVM is enabled.
922 */
923static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 924{
e4ab0d6b 925#ifdef CONFIG_KVM
12869995 926 KVMState *s = kvm_state;
c6dc6f63
AP		 927 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
928
6e746f30
EH		 929 assert(kvm_enabled());
930
c6dc6f63
AP		 931 x86_cpu_def->name = "host";
932 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
c6dc6f63
AP		 933 x86_cpu_def->vendor1 = ebx;
934 x86_cpu_def->vendor2 = edx;
935 x86_cpu_def->vendor3 = ecx;
936
937 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
938 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
939 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
940 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 941
12869995
EH		 942 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
943 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
944 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 945
6e746f30 946 if (x86_cpu_def->level >= 7) {
12869995
EH		 947 x86_cpu_def->cpuid_7_0_ebx_features =
948 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728
EH		 949 } else {
950 x86_cpu_def->cpuid_7_0_ebx_features = 0;
951 }
952
12869995
EH		 953 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
954 x86_cpu_def->ext2_features =
955 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
956 x86_cpu_def->ext3_features =
957 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 958
c6dc6f63
AP		 959 cpu_x86_fill_model_id(x86_cpu_def->model_id);
960 x86_cpu_def->vendor_override = 0;
961
b3baa152
BW		 962 /* Call Centaur's CPUID instruction. */
963 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
964 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
965 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
966 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
12869995 967 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
b3baa152
BW		 968 if (eax >= 0xC0000001) {
969 /* Support VIA max extended level */
970 x86_cpu_def->xlevel2 = eax;
971 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
12869995
EH		 972 x86_cpu_def->ext4_features =
973 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
b3baa152
BW		 974 }
975 }
296acb64 976
fcb93c03
EH		 977 /* Other KVM-specific feature fields: */
978 x86_cpu_def->svm_features =
979 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
bd004bef
EH		 980 x86_cpu_def->kvm_features =
981 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 982
e4ab0d6b 983#endif /* CONFIG_KVM */
c6dc6f63
AP		 984}
985
bffd67b0 986static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 987{
988 int i;
989
990 for (i = 0; i < 32; ++i)
991 if (1 << i & mask) {
bffd67b0 992 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 993 assert(reg);
994 fprintf(stderr, "warning: host doesn't support requested feature: "
995 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 996 f->cpuid_eax, reg,
997 f->feat_names[i] ? "." : "",
998 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 999 break;
1000 }
1001 return 0;
1002}
1003
1004/* best effort attempt to inform user requested cpu flags aren't making
e8beac00 1005 * their way to the guest.
6e746f30
EH		 1006 *
1007 * This function may be called only if KVM is enabled.
c6dc6f63 1008 */
6e746f30 1009static int kvm_check_features_against_host(x86_def_t *guest_def)
c6dc6f63
AP		 1010{
1011 x86_def_t host_def;
1012 uint32_t mask;
1013 int rv, i;
1014 struct model_features_t ft[] = {
1015 {&guest_def->features, &host_def.features,
bffd67b0 1016 FEAT_1_EDX },
c6dc6f63 1017 {&guest_def->ext_features, &host_def.ext_features,
bffd67b0 1018 FEAT_1_ECX },
c6dc6f63 1019 {&guest_def->ext2_features, &host_def.ext2_features,
bffd67b0 1020 FEAT_8000_0001_EDX },
c6dc6f63 1021 {&guest_def->ext3_features, &host_def.ext3_features,
bffd67b0 1022 FEAT_8000_0001_ECX },
8b4beddc 1023 };
c6dc6f63 1024
6e746f30
EH		 1025 assert(kvm_enabled());
1026
1027 kvm_cpu_fill_host(&host_def);
bffd67b0
EH		 1028 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1029 FeatureWord w = ft[i].feat_word;
1030 FeatureWordInfo *wi = &feature_word_info[w];
1031 for (mask = 1; mask; mask <<= 1) {
e8beac00 1032 if (*ft[i].guest_feat & mask &&
c6dc6f63 1033 !(*ft[i].host_feat & mask)) {
bffd67b0
EH		 1034 unavailable_host_feature(wi, mask);
1035 rv = 1;
1036 }
1037 }
1038 }
c6dc6f63
AP		 1039 return rv;
1040}
1041
95b8519d
AF		 1042static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1043 const char *name, Error **errp)
1044{
1045 X86CPU *cpu = X86_CPU(obj);
1046 CPUX86State *env = &cpu->env;
1047 int64_t value;
1048
1049 value = (env->cpuid_version >> 8) & 0xf;
1050 if (value == 0xf) {
1051 value += (env->cpuid_version >> 20) & 0xff;
1052 }
1053 visit_type_int(v, &value, name, errp);
1054}
1055
71ad61d3
AF		 1056static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1057 const char *name, Error **errp)
ed5e1ec3 1058{
71ad61d3
AF		 1059 X86CPU *cpu = X86_CPU(obj);
1060 CPUX86State *env = &cpu->env;
1061 const int64_t min = 0;
1062 const int64_t max = 0xff + 0xf;
1063 int64_t value;
1064
1065 visit_type_int(v, &value, name, errp);
1066 if (error_is_set(errp)) {
1067 return;
1068 }
1069 if (value < min || value > max) {
1070 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1071 name ? name : "null", value, min, max);
1072 return;
1073 }
1074
ed5e1ec3 1075 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1076 if (value > 0x0f) {
1077 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1078 } else {
71ad61d3 1079 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1080 }
1081}
1082
67e30c83
AF		 1083static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1084 const char *name, Error **errp)
1085{
1086 X86CPU *cpu = X86_CPU(obj);
1087 CPUX86State *env = &cpu->env;
1088 int64_t value;
1089
1090 value = (env->cpuid_version >> 4) & 0xf;
1091 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1092 visit_type_int(v, &value, name, errp);
1093}
1094
c5291a4f
AF		 1095static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1096 const char *name, Error **errp)
b0704cbd 1097{
c5291a4f
AF		 1098 X86CPU *cpu = X86_CPU(obj);
1099 CPUX86State *env = &cpu->env;
1100 const int64_t min = 0;
1101 const int64_t max = 0xff;
1102 int64_t value;
1103
1104 visit_type_int(v, &value, name, errp);
1105 if (error_is_set(errp)) {
1106 return;
1107 }
1108 if (value < min || value > max) {
1109 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1110 name ? name : "null", value, min, max);
1111 return;
1112 }
1113
b0704cbd 1114 env->cpuid_version &= ~0xf00f0;
c5291a4f 1115 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1116}
1117
35112e41
AF		 1118static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1119 void *opaque, const char *name,
1120 Error **errp)
1121{
1122 X86CPU *cpu = X86_CPU(obj);
1123 CPUX86State *env = &cpu->env;
1124 int64_t value;
1125
1126 value = env->cpuid_version & 0xf;
1127 visit_type_int(v, &value, name, errp);
1128}
1129
036e2222
AF		 1130static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1131 void *opaque, const char *name,
1132 Error **errp)
38c3dc46 1133{
036e2222
AF		 1134 X86CPU *cpu = X86_CPU(obj);
1135 CPUX86State *env = &cpu->env;
1136 const int64_t min = 0;
1137 const int64_t max = 0xf;
1138 int64_t value;
1139
1140 visit_type_int(v, &value, name, errp);
1141 if (error_is_set(errp)) {
1142 return;
1143 }
1144 if (value < min || value > max) {
1145 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1146 name ? name : "null", value, min, max);
1147 return;
1148 }
1149
38c3dc46 1150 env->cpuid_version &= ~0xf;
036e2222 1151 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1152}
1153
8e1898bf
AF		 1154static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1155 const char *name, Error **errp)
1156{
1157 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1158
fa029887 1159 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1160}
1161
1162static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1163 const char *name, Error **errp)
1164{
1165 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1166
fa029887 1167 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1168}
1169
16b93aa8
AF		 1170static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1171 const char *name, Error **errp)
1172{
1173 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1174
fa029887 1175 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1176}
1177
1178static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1179 const char *name, Error **errp)
1180{
1181 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1182
fa029887 1183 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1184}
1185
d480e1af
AF		 1186static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1187{
1188 X86CPU *cpu = X86_CPU(obj);
1189 CPUX86State *env = &cpu->env;
1190 char *value;
1191 int i;
1192
9df694ee 1193 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
d480e1af
AF		 1194 for (i = 0; i < 4; i++) {
1195 value[i ] = env->cpuid_vendor1 >> (8 * i);
1196 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1197 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1198 }
9df694ee 1199 value[CPUID_VENDOR_SZ] = '\0';
d480e1af
AF		 1200 return value;
1201}
1202
1203static void x86_cpuid_set_vendor(Object *obj, const char *value,
1204 Error **errp)
1205{
1206 X86CPU *cpu = X86_CPU(obj);
1207 CPUX86State *env = &cpu->env;
1208 int i;
1209
9df694ee 1210 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1211 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1212 "vendor", value);
1213 return;
1214 }
1215
1216 env->cpuid_vendor1 = 0;
1217 env->cpuid_vendor2 = 0;
1218 env->cpuid_vendor3 = 0;
1219 for (i = 0; i < 4; i++) {
1220 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1221 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1222 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1223 }
1224 env->cpuid_vendor_override = 1;
1225}
1226
63e886eb
AF		 1227static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1228{
1229 X86CPU *cpu = X86_CPU(obj);
1230 CPUX86State *env = &cpu->env;
1231 char *value;
1232 int i;
1233
1234 value = g_malloc(48 + 1);
1235 for (i = 0; i < 48; i++) {
1236 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1237 }
1238 value[48] = '\0';
1239 return value;
1240}
1241
938d4c25
AF		 1242static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1243 Error **errp)
dcce6675 1244{
938d4c25
AF		 1245 X86CPU *cpu = X86_CPU(obj);
1246 CPUX86State *env = &cpu->env;
dcce6675
AF		 1247 int c, len, i;
1248
1249 if (model_id == NULL) {
1250 model_id = "";
1251 }
1252 len = strlen(model_id);
d0a6acf4 1253 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1254 for (i = 0; i < 48; i++) {
1255 if (i >= len) {
1256 c = '\0';
1257 } else {
1258 c = (uint8_t)model_id[i];
1259 }
1260 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1261 }
1262}
1263
89e48965
AF		 1264static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1265 const char *name, Error **errp)
1266{
1267 X86CPU *cpu = X86_CPU(obj);
1268 int64_t value;
1269
1270 value = cpu->env.tsc_khz * 1000;
1271 visit_type_int(v, &value, name, errp);
1272}
1273
1274static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1275 const char *name, Error **errp)
1276{
1277 X86CPU *cpu = X86_CPU(obj);
1278 const int64_t min = 0;
2e84849a 1279 const int64_t max = INT64_MAX;
89e48965
AF		 1280 int64_t value;
1281
1282 visit_type_int(v, &value, name, errp);
1283 if (error_is_set(errp)) {
1284 return;
1285 }
1286 if (value < min || value > max) {
1287 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1288 name ? name : "null", value, min, max);
1289 return;
1290 }
1291
1292 cpu->env.tsc_khz = value / 1000;
1293}
1294
8f961357 1295static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
c6dc6f63 1296{
c6dc6f63
AP		 1297 x86_def_t *def;
1298
9f3fb565
EH		 1299 for (def = x86_defs; def; def = def->next) {
1300 if (name && !strcmp(name, def->name)) {
c6dc6f63 1301 break;
9f3fb565
EH		 1302 }
1303 }
04c5b17a 1304 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
6e746f30 1305 kvm_cpu_fill_host(x86_cpu_def);
c6dc6f63 1306 } else if (!def) {
8f961357 1307 return -1;
c6dc6f63
AP		 1308 } else {
1309 memcpy(x86_cpu_def, def, sizeof(*def));
1310 }
1311
8f961357
EH		 1312 return 0;
1313}
1314
1315/* Parse "+feature,-feature,feature=foo" CPU feature string
1316 */
1317static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1318{
1319 unsigned int i;
1320 char *featurestr; /* Single 'key=value" string being parsed */
1321 /* Features to be added */
5ef57876
EH		 1322 FeatureWordArray plus_features = {
1323 [FEAT_KVM] = kvm_default_features,
1324 };
8f961357 1325 /* Features to be removed */
5ef57876 1326 FeatureWordArray minus_features = { 0 };
8f961357
EH		 1327 uint32_t numvalue;
1328
5ef57876 1329 add_flagname_to_bitmaps("hypervisor", plus_features);
c6dc6f63 1330
8f961357 1331 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1332
1333 while (featurestr) {
1334 char *val;
1335 if (featurestr[0] == '+') {
5ef57876 1336 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1337 } else if (featurestr[0] == '-') {
5ef57876 1338 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1339 } else if ((val = strchr(featurestr, '='))) {
1340 *val = 0; val++;
1341 if (!strcmp(featurestr, "family")) {
1342 char *err;
1343 numvalue = strtoul(val, &err, 0);
a88a677f 1344 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 1345 fprintf(stderr, "bad numerical value %s\n", val);
1346 goto error;
1347 }
1348 x86_cpu_def->family = numvalue;
1349 } else if (!strcmp(featurestr, "model")) {
1350 char *err;
1351 numvalue = strtoul(val, &err, 0);
1352 if (!*val || *err || numvalue > 0xff) {
1353 fprintf(stderr, "bad numerical value %s\n", val);
1354 goto error;
1355 }
1356 x86_cpu_def->model = numvalue;
1357 } else if (!strcmp(featurestr, "stepping")) {
1358 char *err;
1359 numvalue = strtoul(val, &err, 0);
1360 if (!*val || *err || numvalue > 0xf) {
1361 fprintf(stderr, "bad numerical value %s\n", val);
1362 goto error;
1363 }
1364 x86_cpu_def->stepping = numvalue ;
1365 } else if (!strcmp(featurestr, "level")) {
1366 char *err;
1367 numvalue = strtoul(val, &err, 0);
1368 if (!*val || *err) {
1369 fprintf(stderr, "bad numerical value %s\n", val);
1370 goto error;
1371 }
1372 x86_cpu_def->level = numvalue;
1373 } else if (!strcmp(featurestr, "xlevel")) {
1374 char *err;
1375 numvalue = strtoul(val, &err, 0);
1376 if (!*val || *err) {
1377 fprintf(stderr, "bad numerical value %s\n", val);
1378 goto error;
1379 }
1380 if (numvalue < 0x80000000) {
2f7a21c4 1381 numvalue += 0x80000000;
c6dc6f63
AP		 1382 }
1383 x86_cpu_def->xlevel = numvalue;
1384 } else if (!strcmp(featurestr, "vendor")) {
1385 if (strlen(val) != 12) {
1386 fprintf(stderr, "vendor string must be 12 chars long\n");
1387 goto error;
1388 }
1389 x86_cpu_def->vendor1 = 0;
1390 x86_cpu_def->vendor2 = 0;
1391 x86_cpu_def->vendor3 = 0;
1392 for(i = 0; i < 4; i++) {
1393 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1394 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1395 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1396 }
1397 x86_cpu_def->vendor_override = 1;
1398 } else if (!strcmp(featurestr, "model_id")) {
1399 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1400 val);
b862d1fe
JR		 1401 } else if (!strcmp(featurestr, "tsc_freq")) {
1402 int64_t tsc_freq;
1403 char *err;
1404
1405 tsc_freq = strtosz_suffix_unit(val, &err,
1406 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1407 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 1408 fprintf(stderr, "bad numerical value %s\n", val);
1409 goto error;
1410 }
1411 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 1412 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1413 char *err;
1414 numvalue = strtoul(val, &err, 0);
1415 if (!*val || *err) {
1416 fprintf(stderr, "bad numerical value %s\n", val);
1417 goto error;
1418 }
1419 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1420 } else {
1421 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1422 goto error;
1423 }
1424 } else if (!strcmp(featurestr, "check")) {
1425 check_cpuid = 1;
1426 } else if (!strcmp(featurestr, "enforce")) {
1427 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1428 } else if (!strcmp(featurestr, "hv_relaxed")) {
1429 hyperv_enable_relaxed_timing(true);
1430 } else if (!strcmp(featurestr, "hv_vapic")) {
1431 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1432 } else {
1433 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1434 goto error;
1435 }
1436 featurestr = strtok(NULL, ",");
1437 }
5ef57876
EH		 1438 x86_cpu_def->features |= plus_features[FEAT_1_EDX];
1439 x86_cpu_def->ext_features |= plus_features[FEAT_1_ECX];
1440 x86_cpu_def->ext2_features |= plus_features[FEAT_8000_0001_EDX];
1441 x86_cpu_def->ext3_features |= plus_features[FEAT_8000_0001_ECX];
1442 x86_cpu_def->kvm_features |= plus_features[FEAT_KVM];
1443 x86_cpu_def->svm_features |= plus_features[FEAT_SVM];
1444 x86_cpu_def->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1445 x86_cpu_def->features &= ~minus_features[FEAT_1_EDX];
1446 x86_cpu_def->ext_features &= ~minus_features[FEAT_1_ECX];
1447 x86_cpu_def->ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1448 x86_cpu_def->ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1449 x86_cpu_def->kvm_features &= ~minus_features[FEAT_KVM];
1450 x86_cpu_def->svm_features &= ~minus_features[FEAT_SVM];
1451 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
6e746f30
EH		 1452 if (check_cpuid && kvm_enabled()) {
1453 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
c6dc6f63
AP		 1454 goto error;
1455 }
c6dc6f63
AP		 1456 return 0;
1457
1458error:
c6dc6f63
AP		 1459 return -1;
1460}
1461
1462/* generate a composite string into buf of all cpuid names in featureset
1463 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1464 * if flags, suppress names undefined in featureset.
1465 */
1466static void listflags(char *buf, int bufsize, uint32_t fbits,
1467 const char **featureset, uint32_t flags)
1468{
1469 const char **p = &featureset[31];
1470 char *q, *b, bit;
1471 int nc;
1472
1473 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1474 *buf = '\0';
1475 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1476 if (fbits & 1 << bit && (*p || !flags)) {
1477 if (*p)
1478 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1479 else
1480 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1481 if (bufsize <= nc) {
1482 if (b) {
1483 memcpy(b, "...", sizeof("..."));
1484 }
1485 return;
1486 }
1487 q += nc;
1488 bufsize -= nc;
1489 }
1490}
1491
e916cbf8
PM		 1492/* generate CPU information. */
1493void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1494{
c6dc6f63
AP		 1495 x86_def_t *def;
1496 char buf[256];
1497
c6dc6f63 1498 for (def = x86_defs; def; def = def->next) {
c04321b3 1499 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1500 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1501 }
ed2c54d4
AP		 1502 if (kvm_enabled()) {
1503 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1504 }
6cdf8854
PM		 1505 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1506 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
4a19e505 1507 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1508 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
4a19e505 1509 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1510 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
4a19e505 1511 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1512 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
4a19e505 1513 (*cpu_fprintf)(f, " %s\n", buf);
c6dc6f63
AP		 1514}
1515
76b64a7a 1516CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1517{
1518 CpuDefinitionInfoList *cpu_list = NULL;
1519 x86_def_t *def;
1520
1521 for (def = x86_defs; def; def = def->next) {
1522 CpuDefinitionInfoList *entry;
1523 CpuDefinitionInfo *info;
1524
1525 info = g_malloc0(sizeof(*info));
1526 info->name = g_strdup(def->name);
1527
1528 entry = g_malloc0(sizeof(*entry));
1529 entry->value = info;
1530 entry->next = cpu_list;
1531 cpu_list = entry;
1532 }
1533
1534 return cpu_list;
1535}
1536
bc74b7db
EH		 1537#ifdef CONFIG_KVM
1538static void filter_features_for_kvm(X86CPU *cpu)
1539{
1540 CPUX86State *env = &cpu->env;
1541 KVMState *s = kvm_state;
1542
b8091f24
EH		 1543 env->cpuid_features &=
1544 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1545 env->cpuid_ext_features &=
1546 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1547 env->cpuid_ext2_features &=
1548 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1549 env->cpuid_ext3_features &=
1550 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1551 env->cpuid_svm_features &=
1552 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
ffa8c11f
EH		 1553 env->cpuid_7_0_ebx_features &=
1554 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
bc74b7db 1555 env->cpuid_kvm_features &=
b8091f24
EH		 1556 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1557 env->cpuid_ext4_features &=
1558 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
bc74b7db
EH		 1559
1560}
1561#endif
1562
61dcd775 1563int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1564{
61dcd775 1565 CPUX86State *env = &cpu->env;
c6dc6f63 1566 x86_def_t def1, *def = &def1;
71ad61d3 1567 Error *error = NULL;
8f961357
EH		 1568 char *name, *features;
1569 gchar **model_pieces;
c6dc6f63 1570
db0ad1ba
JR		 1571 memset(def, 0, sizeof(*def));
1572
8f961357
EH		 1573 model_pieces = g_strsplit(cpu_model, ",", 2);
1574 if (!model_pieces[0]) {
1575 goto error;
1576 }
1577 name = model_pieces[0];
1578 features = model_pieces[1];
1579
1580 if (cpu_x86_find_by_name(def, name) < 0) {
1581 goto error;
1582 }
1583
1584 if (cpu_x86_parse_featurestr(def, features) < 0) {
1585 goto error;
1586 }
ebe8b9c6
IM		 1587 assert(def->vendor1);
1588 env->cpuid_vendor1 = def->vendor1;
1589 env->cpuid_vendor2 = def->vendor2;
1590 env->cpuid_vendor3 = def->vendor3;
c6dc6f63 1591 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1592 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1593 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1594 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1595 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1596 env->cpuid_features = def->features;
c6dc6f63
AP		 1597 env->cpuid_ext_features = def->ext_features;
1598 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1599 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1600 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1601 env->cpuid_kvm_features = def->kvm_features;
296acb64 1602 env->cpuid_svm_features = def->svm_features;
b3baa152 1603 env->cpuid_ext4_features = def->ext4_features;
a9321a4d 1604 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
b3baa152 1605 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1606 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1607 "tsc-frequency", &error);
3b671a40 1608
938d4c25 1609 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
18eb473f
IM		 1610 if (error) {
1611 fprintf(stderr, "%s\n", error_get_pretty(error));
71ad61d3 1612 error_free(error);
8f961357 1613 goto error;
71ad61d3 1614 }
8f961357
EH		 1615
1616 g_strfreev(model_pieces);
c6dc6f63 1617 return 0;
8f961357
EH		 1618error:
1619 g_strfreev(model_pieces);
1620 return -1;
c6dc6f63
AP		 1621}
1622
1623#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1624
0e26b7b8
BS		 1625void cpu_clear_apic_feature(CPUX86State *env)
1626{
1627 env->cpuid_features &= ~CPUID_APIC;
1628}
1629
c6dc6f63
AP		 1630#endif /* !CONFIG_USER_ONLY */
1631
c04321b3 1632/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1633 */
1634void x86_cpudef_setup(void)
1635{
93bfef4c
CV		 1636 int i, j;
1637 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1638
1639 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291
EH		 1640 x86_def_t *def = &builtin_x86_defs[i];
1641 def->next = x86_defs;
93bfef4c
CV		 1642
1643 /* Look for specific "cpudef" models that */
09faecf2 1644 /* have the QEMU version in .model_id */
93bfef4c 1645 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1646 if (strcmp(model_with_versions[j], def->name) == 0) {
1647 pstrcpy(def->model_id, sizeof(def->model_id),
1648 "QEMU Virtual CPU version ");
1649 pstrcat(def->model_id, sizeof(def->model_id),
1650 qemu_get_version());
93bfef4c
CV		 1651 break;
1652 }
1653 }
1654
bc3e1291 1655 x86_defs = def;
c6dc6f63 1656 }
c6dc6f63
AP		 1657}
1658
c6dc6f63
AP		 1659static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1660 uint32_t *ecx, uint32_t *edx)
1661{
1662 *ebx = env->cpuid_vendor1;
1663 *edx = env->cpuid_vendor2;
1664 *ecx = env->cpuid_vendor3;
1665
1666 /* sysenter isn't supported on compatibility mode on AMD, syscall
1667 * isn't supported in compatibility mode on Intel.
1668 * Normally we advertise the actual cpu vendor, but you can override
1669 * this if you want to use KVM's sysenter/syscall emulation
1670 * in compatibility mode and when doing cross vendor migration
1671 */
89354998 1672 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1673 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1674 }
1675}
1676
1677void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1678 uint32_t *eax, uint32_t *ebx,
1679 uint32_t *ecx, uint32_t *edx)
1680{
a60f24b5
AF		 1681 X86CPU *cpu = x86_env_get_cpu(env);
1682 CPUState *cs = CPU(cpu);
1683
c6dc6f63
AP		 1684 /* test if maximum index reached */
1685 if (index & 0x80000000) {
b3baa152
BW		 1686 if (index > env->cpuid_xlevel) {
1687 if (env->cpuid_xlevel2 > 0) {
1688 /* Handle the Centaur's CPUID instruction. */
1689 if (index > env->cpuid_xlevel2) {
1690 index = env->cpuid_xlevel2;
1691 } else if (index < 0xC0000000) {
1692 index = env->cpuid_xlevel;
1693 }
1694 } else {
57f26ae7
EH		 1695 /* Intel documentation states that invalid EAX input will
1696 * return the same information as EAX=cpuid_level
1697 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1698 */
1699 index = env->cpuid_level;
b3baa152
BW		 1700 }
1701 }
c6dc6f63
AP		 1702 } else {
1703 if (index > env->cpuid_level)
1704 index = env->cpuid_level;
1705 }
1706
1707 switch(index) {
1708 case 0:
1709 *eax = env->cpuid_level;
1710 get_cpuid_vendor(env, ebx, ecx, edx);
1711 break;
1712 case 1:
1713 *eax = env->cpuid_version;
1714 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1715 *ecx = env->cpuid_ext_features;
1716 *edx = env->cpuid_features;
ce3960eb
AF		 1717 if (cs->nr_cores * cs->nr_threads > 1) {
1718 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 1719 *edx |= 1 << 28; /* HTT bit */
1720 }
1721 break;
1722 case 2:
1723 /* cache info: needed for Pentium Pro compatibility */
1724 *eax = 1;
1725 *ebx = 0;
1726 *ecx = 0;
1727 *edx = 0x2c307d;
1728 break;
1729 case 4:
1730 /* cache info: needed for Core compatibility */
ce3960eb
AF		 1731 if (cs->nr_cores > 1) {
1732 *eax = (cs->nr_cores - 1) << 26;
c6dc6f63 1733 } else {
2f7a21c4 1734 *eax = 0;
c6dc6f63
AP		 1735 }
1736 switch (count) {
1737 case 0: /* L1 dcache info */
1738 *eax |= 0x0000121;
1739 *ebx = 0x1c0003f;
1740 *ecx = 0x000003f;
1741 *edx = 0x0000001;
1742 break;
1743 case 1: /* L1 icache info */
1744 *eax |= 0x0000122;
1745 *ebx = 0x1c0003f;
1746 *ecx = 0x000003f;
1747 *edx = 0x0000001;
1748 break;
1749 case 2: /* L2 cache info */
1750 *eax |= 0x0000143;
ce3960eb
AF		 1751 if (cs->nr_threads > 1) {
1752 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63
AP		 1753 }
1754 *ebx = 0x3c0003f;
1755 *ecx = 0x0000fff;
1756 *edx = 0x0000001;
1757 break;
1758 default: /* end of info */
1759 *eax = 0;
1760 *ebx = 0;
1761 *ecx = 0;
1762 *edx = 0;
1763 break;
1764 }
1765 break;
1766 case 5:
1767 /* mwait info: needed for Core compatibility */
1768 *eax = 0; /* Smallest monitor-line size in bytes */
1769 *ebx = 0; /* Largest monitor-line size in bytes */
1770 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1771 *edx = 0;
1772 break;
1773 case 6:
1774 /* Thermal and Power Leaf */
1775 *eax = 0;
1776 *ebx = 0;
1777 *ecx = 0;
1778 *edx = 0;
1779 break;
f7911686 1780 case 7:
13526728
EH		 1781 /* Structured Extended Feature Flags Enumeration Leaf */
1782 if (count == 0) {
1783 *eax = 0; /* Maximum ECX value for sub-leaves */
a9321a4d 1784 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
13526728
EH		 1785 *ecx = 0; /* Reserved */
1786 *edx = 0; /* Reserved */
f7911686
YW		 1787 } else {
1788 *eax = 0;
1789 *ebx = 0;
1790 *ecx = 0;
1791 *edx = 0;
1792 }
1793 break;
c6dc6f63
AP		 1794 case 9:
1795 /* Direct Cache Access Information Leaf */
1796 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1797 *ebx = 0;
1798 *ecx = 0;
1799 *edx = 0;
1800 break;
1801 case 0xA:
1802 /* Architectural Performance Monitoring Leaf */
a0fa8208 1803 if (kvm_enabled()) {
a60f24b5 1804 KVMState *s = cs->kvm_state;
a0fa8208
GN		 1805
1806 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1807 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1808 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1809 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1810 } else {
1811 *eax = 0;
1812 *ebx = 0;
1813 *ecx = 0;
1814 *edx = 0;
1815 }
c6dc6f63 1816 break;
51e49430
SY		 1817 case 0xD:
1818 /* Processor Extended State */
1819 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1820 *eax = 0;
1821 *ebx = 0;
1822 *ecx = 0;
1823 *edx = 0;
1824 break;
1825 }
1826 if (kvm_enabled()) {
a60f24b5 1827 KVMState *s = cs->kvm_state;
ba9bc59e
JK		 1828
1829 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1830 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1831 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1832 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1833 } else {
1834 *eax = 0;
1835 *ebx = 0;
1836 *ecx = 0;
1837 *edx = 0;
1838 }
1839 break;
c6dc6f63
AP		 1840 case 0x80000000:
1841 *eax = env->cpuid_xlevel;
1842 *ebx = env->cpuid_vendor1;
1843 *edx = env->cpuid_vendor2;
1844 *ecx = env->cpuid_vendor3;
1845 break;
1846 case 0x80000001:
1847 *eax = env->cpuid_version;
1848 *ebx = 0;
1849 *ecx = env->cpuid_ext3_features;
1850 *edx = env->cpuid_ext2_features;
1851
1852 /* The Linux kernel checks for the CMPLegacy bit and
1853 * discards multiple thread information if it is set.
1854 * So dont set it here for Intel to make Linux guests happy.
1855 */
ce3960eb 1856 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 1857 uint32_t tebx, tecx, tedx;
1858 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1859 if (tebx != CPUID_VENDOR_INTEL_1 ||
1860 tedx != CPUID_VENDOR_INTEL_2 ||
1861 tecx != CPUID_VENDOR_INTEL_3) {
1862 *ecx |= 1 << 1; /* CmpLegacy bit */
1863 }
1864 }
c6dc6f63
AP		 1865 break;
1866 case 0x80000002:
1867 case 0x80000003:
1868 case 0x80000004:
1869 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1870 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1871 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1872 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1873 break;
1874 case 0x80000005:
1875 /* cache info (L1 cache) */
1876 *eax = 0x01ff01ff;
1877 *ebx = 0x01ff01ff;
1878 *ecx = 0x40020140;
1879 *edx = 0x40020140;
1880 break;
1881 case 0x80000006:
1882 /* cache info (L2 cache) */
1883 *eax = 0;
1884 *ebx = 0x42004200;
1885 *ecx = 0x02008140;
1886 *edx = 0;
1887 break;
1888 case 0x80000008:
1889 /* virtual & phys address size in low 2 bytes. */
1890/* XXX: This value must match the one used in the MMU code. */
1891 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1892 /* 64 bit processor */
1893/* XXX: The physical address space is limited to 42 bits in exec.c. */
1894 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1895 } else {
1896 if (env->cpuid_features & CPUID_PSE36)
1897 *eax = 0x00000024; /* 36 bits physical */
1898 else
1899 *eax = 0x00000020; /* 32 bits physical */
1900 }
1901 *ebx = 0;
1902 *ecx = 0;
1903 *edx = 0;
ce3960eb
AF		 1904 if (cs->nr_cores * cs->nr_threads > 1) {
1905 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 1906 }
1907 break;
1908 case 0x8000000A:
9f3fb565
EH		 1909 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1910 *eax = 0x00000001; /* SVM Revision */
1911 *ebx = 0x00000010; /* nr of ASIDs */
1912 *ecx = 0;
1913 *edx = env->cpuid_svm_features; /* optional features */
1914 } else {
1915 *eax = 0;
1916 *ebx = 0;
1917 *ecx = 0;
1918 *edx = 0;
1919 }
c6dc6f63 1920 break;
b3baa152
BW		 1921 case 0xC0000000:
1922 *eax = env->cpuid_xlevel2;
1923 *ebx = 0;
1924 *ecx = 0;
1925 *edx = 0;
1926 break;
1927 case 0xC0000001:
1928 /* Support for VIA CPU's CPUID instruction */
1929 *eax = env->cpuid_version;
1930 *ebx = 0;
1931 *ecx = 0;
1932 *edx = env->cpuid_ext4_features;
1933 break;
1934 case 0xC0000002:
1935 case 0xC0000003:
1936 case 0xC0000004:
1937 /* Reserved for the future, and now filled with zero */
1938 *eax = 0;
1939 *ebx = 0;
1940 *ecx = 0;
1941 *edx = 0;
1942 break;
c6dc6f63
AP		 1943 default:
1944 /* reserved values: zero */
1945 *eax = 0;
1946 *ebx = 0;
1947 *ecx = 0;
1948 *edx = 0;
1949 break;
1950 }
1951}
5fd2087a
AF		 1952
1953/* CPUClass::reset() */
1954static void x86_cpu_reset(CPUState *s)
1955{
1956 X86CPU *cpu = X86_CPU(s);
1957 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1958 CPUX86State *env = &cpu->env;
c1958aea
AF		 1959 int i;
1960
1961 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 1962 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
6fd2a026 1963 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
c1958aea 1964 }
5fd2087a
AF		 1965
1966 xcc->parent_reset(s);
1967
c1958aea
AF		 1968
1969 memset(env, 0, offsetof(CPUX86State, breakpoints));
1970
1971 tlb_flush(env, 1);
1972
1973 env->old_exception = -1;
1974
1975 /* init to reset state */
1976
1977#ifdef CONFIG_SOFTMMU
1978 env->hflags |= HF_SOFTMMU_MASK;
1979#endif
1980 env->hflags2 |= HF2_GIF_MASK;
1981
1982 cpu_x86_update_cr0(env, 0x60000010);
1983 env->a20_mask = ~0x0;
1984 env->smbase = 0x30000;
1985
1986 env->idt.limit = 0xffff;
1987 env->gdt.limit = 0xffff;
1988 env->ldt.limit = 0xffff;
1989 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1990 env->tr.limit = 0xffff;
1991 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1992
1993 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1994 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1995 DESC_R_MASK | DESC_A_MASK);
1996 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1997 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1998 DESC_A_MASK);
1999 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2000 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2001 DESC_A_MASK);
2002 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2003 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2004 DESC_A_MASK);
2005 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2006 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2007 DESC_A_MASK);
2008 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2009 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2010 DESC_A_MASK);
2011
2012 env->eip = 0xfff0;
2013 env->regs[R_EDX] = env->cpuid_version;
2014
2015 env->eflags = 0x2;
2016
2017 /* FPU init */
2018 for (i = 0; i < 8; i++) {
2019 env->fptags[i] = 1;
2020 }
2021 env->fpuc = 0x37f;
2022
2023 env->mxcsr = 0x1f80;
2024
2025 env->pat = 0x0007040600070406ULL;
2026 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2027
2028 memset(env->dr, 0, sizeof(env->dr));
2029 env->dr[6] = DR6_FIXED_1;
2030 env->dr[7] = DR7_FIXED_1;
2031 cpu_breakpoint_remove_all(env, BP_CPU);
2032 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 2033
2034#if !defined(CONFIG_USER_ONLY)
2035 /* We hard-wire the BSP to the first CPU. */
55e5c285 2036 if (s->cpu_index == 0) {
dd673288
IM		 2037 apic_designate_bsp(env->apic_state);
2038 }
2039
2040 env->halted = !cpu_is_bsp(cpu);
2041#endif
5fd2087a
AF		 2042}
2043
dd673288
IM		 2044#ifndef CONFIG_USER_ONLY
2045bool cpu_is_bsp(X86CPU *cpu)
2046{
2047 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2048}
65dee380
IM		 2049
2050/* TODO: remove me, when reset over QOM tree is implemented */
2051static void x86_cpu_machine_reset_cb(void *opaque)
2052{
2053 X86CPU *cpu = opaque;
2054 cpu_reset(CPU(cpu));
2055}
dd673288
IM		 2056#endif
2057
de024815
AF		 2058static void mce_init(X86CPU *cpu)
2059{
2060 CPUX86State *cenv = &cpu->env;
2061 unsigned int bank;
2062
2063 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2064 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2065 (CPUID_MCE | CPUID_MCA)) {
2066 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2067 cenv->mcg_ctl = ~(uint64_t)0;
2068 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2069 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2070 }
2071 }
2072}
2073
bdeec802
IM		 2074#define MSI_ADDR_BASE 0xfee00000
2075
2076#ifndef CONFIG_USER_ONLY
2077static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2078{
2079 static int apic_mapped;
2080 CPUX86State *env = &cpu->env;
449994eb 2081 APICCommonState *apic;
bdeec802
IM		 2082 const char *apic_type = "apic";
2083
2084 if (kvm_irqchip_in_kernel()) {
2085 apic_type = "kvm-apic";
2086 } else if (xen_enabled()) {
2087 apic_type = "xen-apic";
2088 }
2089
2090 env->apic_state = qdev_try_create(NULL, apic_type);
2091 if (env->apic_state == NULL) {
2092 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2093 return;
2094 }
2095
2096 object_property_add_child(OBJECT(cpu), "apic",
2097 OBJECT(env->apic_state), NULL);
2098 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2099 /* TODO: convert to link<> */
449994eb 2100 apic = APIC_COMMON(env->apic_state);
60671e58 2101 apic->cpu = cpu;
bdeec802
IM		 2102
2103 if (qdev_init(env->apic_state)) {
2104 error_setg(errp, "APIC device '%s' could not be initialized",
2105 object_get_typename(OBJECT(env->apic_state)));
2106 return;
2107 }
2108
2109 /* XXX: mapping more APICs at the same memory location */
2110 if (apic_mapped == 0) {
2111 /* NOTE: the APIC is directly connected to the CPU - it is not
2112 on the global memory bus. */
2113 /* XXX: what if the base changes? */
2114 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2115 apic_mapped = 1;
2116 }
2117}
2118#endif
2119
7a059953
AF		 2120void x86_cpu_realize(Object *obj, Error **errp)
2121{
2122 X86CPU *cpu = X86_CPU(obj);
b34d12d1
IM		 2123 CPUX86State *env = &cpu->env;
2124
2125 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2126 env->cpuid_level = 7;
2127 }
7a059953 2128
9b15cd9e
IM		 2129 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2130 * CPUID[1].EDX.
2131 */
2132 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2133 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2134 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2135 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2136 env->cpuid_ext2_features |= (env->cpuid_features
2137 & CPUID_EXT2_AMD_ALIASES);
2138 }
2139
4586f157
IM		 2140 if (!kvm_enabled()) {
2141 env->cpuid_features &= TCG_FEATURES;
2142 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2143 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2144#ifdef TARGET_X86_64
2145 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2146#endif
2147 );
2148 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2149 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2150 } else {
2151#ifdef CONFIG_KVM
2152 filter_features_for_kvm(cpu);
2153#endif
2154 }
2155
65dee380
IM		 2156#ifndef CONFIG_USER_ONLY
2157 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802
IM		 2158
2159 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2160 x86_cpu_apic_init(cpu, errp);
2161 if (error_is_set(errp)) {
2162 return;
2163 }
2164 }
65dee380
IM		 2165#endif
2166
7a059953
AF		 2167 mce_init(cpu);
2168 qemu_init_vcpu(&cpu->env);
65dee380 2169 cpu_reset(CPU(cpu));
7a059953
AF		 2170}
2171
de024815
AF		 2172static void x86_cpu_initfn(Object *obj)
2173{
55e5c285 2174 CPUState *cs = CPU(obj);
de024815
AF		 2175 X86CPU *cpu = X86_CPU(obj);
2176 CPUX86State *env = &cpu->env;
d65e9815 2177 static int inited;
de024815
AF		 2178
2179 cpu_exec_init(env);
71ad61d3
AF		 2180
2181 object_property_add(obj, "family", "int",
95b8519d 2182 x86_cpuid_version_get_family,
71ad61d3 2183 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2184 object_property_add(obj, "model", "int",
67e30c83 2185 x86_cpuid_version_get_model,
c5291a4f 2186 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2187 object_property_add(obj, "stepping", "int",
35112e41 2188 x86_cpuid_version_get_stepping,
036e2222 2189 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2190 object_property_add(obj, "level", "int",
2191 x86_cpuid_get_level,
2192 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2193 object_property_add(obj, "xlevel", "int",
2194 x86_cpuid_get_xlevel,
2195 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2196 object_property_add_str(obj, "vendor",
2197 x86_cpuid_get_vendor,
2198 x86_cpuid_set_vendor, NULL);
938d4c25 2199 object_property_add_str(obj, "model-id",
63e886eb 2200 x86_cpuid_get_model_id,
938d4c25 2201 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2202 object_property_add(obj, "tsc-frequency", "int",
2203 x86_cpuid_get_tsc_freq,
2204 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 2205
55e5c285 2206 env->cpuid_apic_id = cs->cpu_index;
d65e9815
IM		 2207
2208 /* init various static tables used in TCG mode */
2209 if (tcg_enabled() && !inited) {
2210 inited = 1;
2211 optimize_flags_init();
2212#ifndef CONFIG_USER_ONLY
2213 cpu_set_debug_excp_handler(breakpoint_handler);
2214#endif
2215 }
de024815
AF		 2216}
2217
5fd2087a
AF		 2218static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2219{
2220 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2221 CPUClass *cc = CPU_CLASS(oc);
2222
2223 xcc->parent_reset = cc->reset;
2224 cc->reset = x86_cpu_reset;
2225}
2226
2227static const TypeInfo x86_cpu_type_info = {
2228 .name = TYPE_X86_CPU,
2229 .parent = TYPE_CPU,
2230 .instance_size = sizeof(X86CPU),
de024815 2231 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2232 .abstract = false,
2233 .class_size = sizeof(X86CPUClass),
2234 .class_init = x86_cpu_common_class_init,
2235};
2236
2237static void x86_cpu_register_types(void)
2238{
2239 type_register_static(&x86_cpu_type_info);
2240}
2241
2242type_init(x86_cpu_register_types)
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