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49ba9447 | 1 | /**@file\r |
2 | Platform PEI driver\r | |
3 | \r | |
a1726e30 | 4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
eec7d420 | 5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r |
6 | \r | |
56d7640a | 7 | This program and the accompanying materials\r |
49ba9447 | 8 | are licensed and made available under the terms and conditions of the BSD License\r |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | //\r | |
18 | // The package level header files this module uses\r | |
19 | //\r | |
20 | #include <PiPei.h>\r | |
21 | \r | |
22 | //\r | |
23 | // The Library classes this module consumes\r | |
24 | //\r | |
5133d1f1 | 25 | #include <Library/BaseLib.h>\r |
49ba9447 | 26 | #include <Library/DebugLib.h>\r |
27 | #include <Library/HobLib.h>\r | |
28 | #include <Library/IoLib.h>\r | |
77ba993c | 29 | #include <Library/MemoryAllocationLib.h>\r |
30 | #include <Library/PcdLib.h>\r | |
49ba9447 | 31 | #include <Library/PciLib.h>\r |
32 | #include <Library/PeimEntryPoint.h>\r | |
9ed65b10 | 33 | #include <Library/PeiServicesLib.h>\r |
7cdba634 | 34 | #include <Library/QemuFwCfgLib.h>\r |
49ba9447 | 35 | #include <Library/ResourcePublicationLib.h>\r |
36 | #include <Guid/MemoryTypeInformation.h>\r | |
9ed65b10 | 37 | #include <Ppi/MasterBootMode.h>\r |
931a0c74 | 38 | #include <IndustryStandard/Pci22.h>\r |
97380beb | 39 | #include <OvmfPlatforms.h>\r |
49ba9447 | 40 | \r |
41 | #include "Platform.h"\r | |
3ca15914 | 42 | #include "Cmos.h"\r |
49ba9447 | 43 | \r |
44 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
45 | { EfiACPIMemoryNVS, 0x004 },\r | |
991d9563 | 46 | { EfiACPIReclaimMemory, 0x008 },\r |
55cdb67a | 47 | { EfiReservedMemoryType, 0x004 },\r |
991d9563 | 48 | { EfiRuntimeServicesData, 0x024 },\r |
49 | { EfiRuntimeServicesCode, 0x030 },\r | |
50 | { EfiBootServicesCode, 0x180 },\r | |
51 | { EfiBootServicesData, 0xF00 },\r | |
49ba9447 | 52 | { EfiMaxMemoryType, 0x000 }\r |
53 | };\r | |
54 | \r | |
55 | \r | |
9ed65b10 | 56 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r |
57 | {\r | |
58 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
59 | &gEfiPeiMasterBootModePpiGuid,\r | |
60 | NULL\r | |
61 | }\r | |
62 | };\r | |
63 | \r | |
64 | \r | |
589756c7 PA |
65 | UINT16 mHostBridgeDevId;\r |
66 | \r | |
979420df JJ |
67 | EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r |
68 | \r | |
7cdba634 JJ |
69 | BOOLEAN mS3Supported = FALSE;\r |
70 | \r | |
979420df | 71 | \r |
49ba9447 | 72 | VOID\r |
73 | AddIoMemoryBaseSizeHob (\r | |
74 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
75 | UINT64 MemorySize\r | |
76 | )\r | |
77 | {\r | |
991d9563 | 78 | BuildResourceDescriptorHob (\r |
79 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
49ba9447 | 80 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
81 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
82 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
991d9563 | 83 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 84 | MemoryBase,\r |
85 | MemorySize\r | |
86 | );\r | |
87 | }\r | |
88 | \r | |
eec7d420 | 89 | VOID\r |
90 | AddReservedMemoryBaseSizeHob (\r | |
91 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
cdef34ec LE |
92 | UINT64 MemorySize,\r |
93 | BOOLEAN Cacheable\r | |
eec7d420 | 94 | )\r |
95 | {\r | |
96 | BuildResourceDescriptorHob (\r | |
97 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
98 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
99 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
100 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
cdef34ec LE |
101 | (Cacheable ?\r |
102 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
103 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
104 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r | |
105 | 0\r | |
106 | ) |\r | |
eec7d420 | 107 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
108 | MemoryBase,\r | |
109 | MemorySize\r | |
110 | );\r | |
111 | }\r | |
49ba9447 | 112 | \r |
113 | VOID\r | |
114 | AddIoMemoryRangeHob (\r | |
115 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
116 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
117 | )\r | |
118 | {\r | |
119 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
120 | }\r | |
121 | \r | |
122 | \r | |
123 | VOID\r | |
124 | AddMemoryBaseSizeHob (\r | |
125 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
126 | UINT64 MemorySize\r | |
127 | )\r | |
128 | {\r | |
991d9563 | 129 | BuildResourceDescriptorHob (\r |
130 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
49ba9447 | 131 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
132 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
133 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
134 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
135 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
136 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
991d9563 | 137 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 138 | MemoryBase,\r |
139 | MemorySize\r | |
140 | );\r | |
141 | }\r | |
142 | \r | |
143 | \r | |
144 | VOID\r | |
145 | AddMemoryRangeHob (\r | |
146 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
147 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
148 | )\r | |
149 | {\r | |
150 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
151 | }\r | |
152 | \r | |
c0e10976 | 153 | \r |
bb6a9a93 | 154 | VOID\r |
4b455f7b | 155 | MemMapInitialization (\r |
bb6a9a93 WL |
156 | VOID\r |
157 | )\r | |
158 | {\r | |
bb6a9a93 WL |
159 | //\r |
160 | // Create Memory Type Information HOB\r | |
161 | //\r | |
162 | BuildGuidDataHob (\r | |
163 | &gEfiMemoryTypeInformationGuid,\r | |
164 | mDefaultMemoryTypeInformation,\r | |
165 | sizeof(mDefaultMemoryTypeInformation)\r | |
166 | );\r | |
167 | \r | |
168 | //\r | |
169 | // Add PCI IO Port space available for PCI resource allocations.\r | |
170 | //\r | |
171 | BuildResourceDescriptorHob (\r | |
172 | EFI_RESOURCE_IO,\r | |
173 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
174 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
e705f899 LE |
175 | PcdGet64 (PcdPciIoBase),\r |
176 | PcdGet64 (PcdPciIoSize)\r | |
bb6a9a93 WL |
177 | );\r |
178 | \r | |
179 | //\r | |
180 | // Video memory + Legacy BIOS region\r | |
181 | //\r | |
182 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
183 | \r | |
4b455f7b JJ |
184 | if (!mXen) {\r |
185 | UINT32 TopOfLowRam;\r | |
7b8fe635 | 186 | UINT64 PciExBarBase;\r |
c68d3a69 | 187 | UINT32 PciBase;\r |
03845e90 | 188 | UINT32 PciSize;\r |
c68d3a69 | 189 | \r |
4b455f7b | 190 | TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r |
02d6f4ce | 191 | PciExBarBase = 0;\r |
c68d3a69 LE |
192 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
193 | //\r | |
7b8fe635 LE |
194 | // The MMCONFIG area is expected to fall between the top of low RAM and\r |
195 | // the base of the 32-bit PCI host aperture.\r | |
c68d3a69 | 196 | //\r |
7b8fe635 LE |
197 | PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r |
198 | ASSERT (TopOfLowRam <= PciExBarBase);\r | |
199 | ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r | |
200 | PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r | |
c68d3a69 LE |
201 | } else {\r |
202 | PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r | |
203 | }\r | |
49ba9447 | 204 | \r |
4b455f7b JJ |
205 | //\r |
206 | // address purpose size\r | |
207 | // ------------ -------- -------------------------\r | |
208 | // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r | |
209 | // 0xFC000000 gap 44 MB\r | |
210 | // 0xFEC00000 IO-APIC 4 KB\r | |
211 | // 0xFEC01000 gap 1020 KB\r | |
212 | // 0xFED00000 HPET 1 KB\r | |
90721ba5 PA |
213 | // 0xFED00400 gap 111 KB\r |
214 | // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r | |
215 | // 0xFED20000 gap 896 KB\r | |
4b455f7b JJ |
216 | // 0xFEE00000 LAPIC 1 MB\r |
217 | //\r | |
03845e90 LE |
218 | PciSize = 0xFC000000 - PciBase;\r |
219 | AddIoMemoryBaseSizeHob (PciBase, PciSize);\r | |
220 | PcdSet64 (PcdPciMmio32Base, PciBase);\r | |
221 | PcdSet64 (PcdPciMmio32Size, PciSize);\r | |
4b455f7b JJ |
222 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r |
223 | AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r | |
90721ba5 PA |
224 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
225 | AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r | |
7b8fe635 LE |
226 | //\r |
227 | // Note: there should be an\r | |
228 | //\r | |
229 | // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r | |
230 | //\r | |
231 | // call below, just like the one above for RCBA. However, Linux insists\r | |
232 | // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r | |
233 | // "reserved memory" -- Linux does not content itself with a simple gap\r | |
234 | // in the memory map wherever the MCFG ACPI table points to.\r | |
235 | //\r | |
236 | // This appears to be a safety measure. The PCI Firmware Specification\r | |
237 | // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r | |
238 | // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r | |
239 | // [...]". (Emphasis added here.)\r | |
240 | //\r | |
241 | // Normally we add memory resource descriptor HOBs in\r | |
242 | // QemuInitializeRam(), and pre-allocate from those with memory\r | |
243 | // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r | |
244 | // is most definitely not RAM; so, as an exception, cover it with\r | |
245 | // uncacheable reserved memory right here.\r | |
246 | //\r | |
247 | AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r | |
248 | BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r | |
249 | EfiReservedMemoryType);\r | |
90721ba5 | 250 | }\r |
4b455f7b | 251 | AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r |
4b455f7b | 252 | }\r |
49ba9447 | 253 | }\r |
254 | \r | |
ab081a50 LE |
255 | EFI_STATUS\r |
256 | GetNamedFwCfgBoolean (\r | |
257 | IN CHAR8 *FwCfgFileName,\r | |
258 | OUT BOOLEAN *Setting\r | |
259 | )\r | |
260 | {\r | |
261 | EFI_STATUS Status;\r | |
262 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
263 | UINTN FwCfgSize;\r | |
264 | UINT8 Value[3];\r | |
265 | \r | |
266 | Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r | |
267 | if (EFI_ERROR (Status)) {\r | |
268 | return Status;\r | |
269 | }\r | |
270 | if (FwCfgSize > sizeof Value) {\r | |
271 | return EFI_BAD_BUFFER_SIZE;\r | |
272 | }\r | |
273 | QemuFwCfgSelectItem (FwCfgItem);\r | |
274 | QemuFwCfgReadBytes (FwCfgSize, Value);\r | |
275 | \r | |
276 | if ((FwCfgSize == 1) ||\r | |
277 | (FwCfgSize == 2 && Value[1] == '\n') ||\r | |
278 | (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r | |
279 | switch (Value[0]) {\r | |
280 | case '0':\r | |
281 | case 'n':\r | |
282 | case 'N':\r | |
283 | *Setting = FALSE;\r | |
284 | return EFI_SUCCESS;\r | |
285 | \r | |
286 | case '1':\r | |
287 | case 'y':\r | |
288 | case 'Y':\r | |
289 | *Setting = TRUE;\r | |
290 | return EFI_SUCCESS;\r | |
291 | \r | |
292 | default:\r | |
293 | break;\r | |
294 | }\r | |
295 | }\r | |
296 | return EFI_PROTOCOL_ERROR;\r | |
297 | }\r | |
298 | \r | |
299 | #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r | |
300 | do { \\r | |
301 | BOOLEAN Setting; \\r | |
302 | \\r | |
303 | if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r | |
304 | "opt/ovmf/" #TokenName, &Setting))) { \\r | |
305 | PcdSetBool (TokenName, Setting); \\r | |
306 | } \\r | |
307 | } while (0)\r | |
308 | \r | |
309 | VOID\r | |
310 | NoexecDxeInitialization (\r | |
311 | VOID\r | |
312 | )\r | |
313 | {\r | |
314 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r | |
315 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r | |
316 | }\r | |
49ba9447 | 317 | \r |
7b8fe635 LE |
318 | VOID\r |
319 | PciExBarInitialization (\r | |
320 | VOID\r | |
321 | )\r | |
322 | {\r | |
323 | union {\r | |
324 | UINT64 Uint64;\r | |
325 | UINT32 Uint32[2];\r | |
326 | } PciExBarBase;\r | |
327 | \r | |
328 | //\r | |
329 | // We only support the 256MB size for the MMCONFIG area:\r | |
330 | // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r | |
331 | //\r | |
332 | // The masks used below enforce the Q35 requirements that the MMCONFIG area\r | |
333 | // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r | |
334 | //\r | |
335 | // Note that (b) also ensures that the minimum address width we have\r | |
336 | // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r | |
337 | // for DXE's page tables to cover the MMCONFIG area.\r | |
338 | //\r | |
339 | PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
340 | ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r | |
341 | ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r | |
342 | \r | |
343 | //\r | |
344 | // Clear the PCIEXBAREN bit first, before programming the high register.\r | |
345 | //\r | |
346 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r | |
347 | \r | |
348 | //\r | |
349 | // Program the high register. Then program the low register, setting the\r | |
350 | // MMCONFIG area size and enabling decoding at once.\r | |
351 | //\r | |
352 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r | |
353 | PciWrite32 (\r | |
354 | DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r | |
355 | PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r | |
356 | );\r | |
357 | }\r | |
358 | \r | |
49ba9447 | 359 | VOID\r |
360 | MiscInitialization (\r | |
0e20a186 | 361 | VOID\r |
49ba9447 | 362 | )\r |
363 | {\r | |
97380beb GS |
364 | UINTN PmCmd;\r |
365 | UINTN Pmba;\r | |
e2ab3f81 GS |
366 | UINTN AcpiCtlReg;\r |
367 | UINT8 AcpiEnBit;\r | |
97380beb | 368 | \r |
49ba9447 | 369 | //\r |
370 | // Disable A20 Mask\r | |
371 | //\r | |
55cdb67a | 372 | IoOr8 (0x92, BIT1);\r |
49ba9447 | 373 | \r |
374 | //\r | |
86a14b0a LE |
375 | // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r |
376 | // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r | |
377 | // S3 resume as well, so we build it unconditionally.)\r | |
49ba9447 | 378 | //\r |
86a14b0a | 379 | BuildCpuHob (mPhysMemAddressWidth, 16);\r |
c756b2ab | 380 | \r |
97380beb | 381 | //\r |
589756c7 | 382 | // Determine platform type and save Host Bridge DID to PCD\r |
97380beb | 383 | //\r |
589756c7 | 384 | switch (mHostBridgeDevId) {\r |
97380beb | 385 | case INTEL_82441_DEVICE_ID:\r |
e2ab3f81 | 386 | PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r |
da372167 LE |
387 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r |
388 | AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r | |
389 | AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r | |
97380beb GS |
390 | break;\r |
391 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
e2ab3f81 | 392 | PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r |
bc9d05d6 LE |
393 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r |
394 | AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r | |
395 | AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r | |
97380beb GS |
396 | break;\r |
397 | default:\r | |
398 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
589756c7 | 399 | __FUNCTION__, mHostBridgeDevId));\r |
97380beb GS |
400 | ASSERT (FALSE);\r |
401 | return;\r | |
402 | }\r | |
589756c7 | 403 | PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r |
97380beb | 404 | \r |
0e20a186 | 405 | //\r |
e2ab3f81 GS |
406 | // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r |
407 | // has been configured (e.g., by Xen) and skip the setup here.\r | |
408 | // This matches the logic in AcpiTimerLibConstructor ().\r | |
0e20a186 | 409 | //\r |
e2ab3f81 | 410 | if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r |
eec7d420 | 411 | //\r |
e2ab3f81 | 412 | // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r |
931a0c74 | 413 | // 1. set PMBA\r |
eec7d420 | 414 | //\r |
07d3ba07 | 415 | PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);\r |
931a0c74 | 416 | \r |
417 | //\r | |
418 | // 2. set PCICMD/IOSE\r | |
419 | //\r | |
97380beb | 420 | PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r |
931a0c74 | 421 | \r |
422 | //\r | |
e2ab3f81 | 423 | // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r |
931a0c74 | 424 | //\r |
e2ab3f81 | 425 | PciOr8 (AcpiCtlReg, AcpiEnBit);\r |
eec7d420 | 426 | }\r |
90721ba5 PA |
427 | \r |
428 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
429 | //\r | |
430 | // Set Root Complex Register Block BAR\r | |
431 | //\r | |
432 | PciWrite32 (\r | |
433 | POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r | |
434 | ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r | |
435 | );\r | |
7b8fe635 LE |
436 | \r |
437 | //\r | |
438 | // Set PCI Express Register Range Base Address\r | |
439 | //\r | |
440 | PciExBarInitialization ();\r | |
90721ba5 | 441 | }\r |
49ba9447 | 442 | }\r |
443 | \r | |
444 | \r | |
9ed65b10 | 445 | VOID\r |
446 | BootModeInitialization (\r | |
8f5ca05b | 447 | VOID\r |
9ed65b10 | 448 | )\r |
449 | {\r | |
8f5ca05b LE |
450 | EFI_STATUS Status;\r |
451 | \r | |
452 | if (CmosRead8 (0xF) == 0xFE) {\r | |
979420df | 453 | mBootMode = BOOT_ON_S3_RESUME;\r |
8f5ca05b | 454 | }\r |
9be75189 | 455 | CmosWrite8 (0xF, 0x00);\r |
667bf1e4 | 456 | \r |
979420df | 457 | Status = PeiServicesSetBootMode (mBootMode);\r |
667bf1e4 | 458 | ASSERT_EFI_ERROR (Status);\r |
459 | \r | |
460 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
461 | ASSERT_EFI_ERROR (Status);\r | |
9ed65b10 | 462 | }\r |
463 | \r | |
464 | \r | |
77ba993c | 465 | VOID\r |
466 | ReserveEmuVariableNvStore (\r | |
467 | )\r | |
468 | {\r | |
469 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
470 | \r | |
471 | //\r | |
472 | // Allocate storage for NV variables early on so it will be\r | |
473 | // at a consistent address. Since VM memory is preserved\r | |
474 | // across reboots, this allows the NV variable storage to survive\r | |
475 | // a VM reboot.\r | |
476 | //\r | |
477 | VariableStore =\r | |
478 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
9edb2933 | 479 | AllocateAlignedRuntimePages (\r |
cce992ac WL |
480 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r |
481 | PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r | |
27f58ea1 | 482 | );\r |
77ba993c | 483 | DEBUG ((EFI_D_INFO,\r |
484 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r | |
485 | VariableStore,\r | |
29a3f139 | 486 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r |
77ba993c | 487 | ));\r |
488 | PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r | |
489 | }\r | |
490 | \r | |
491 | \r | |
3ca15914 | 492 | VOID\r |
493 | DebugDumpCmos (\r | |
494 | VOID\r | |
495 | )\r | |
496 | {\r | |
6394c35a | 497 | UINT32 Loop;\r |
3ca15914 | 498 | \r |
499 | DEBUG ((EFI_D_INFO, "CMOS:\n"));\r | |
500 | \r | |
501 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
502 | if ((Loop % 0x10) == 0) {\r | |
503 | DEBUG ((EFI_D_INFO, "%02x:", Loop));\r | |
504 | }\r | |
505 | DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r | |
506 | if ((Loop % 0x10) == 0xf) {\r | |
507 | DEBUG ((EFI_D_INFO, "\n"));\r | |
508 | }\r | |
509 | }\r | |
510 | }\r | |
511 | \r | |
512 | \r | |
5133d1f1 LE |
513 | VOID\r |
514 | S3Verification (\r | |
515 | VOID\r | |
516 | )\r | |
517 | {\r | |
518 | #if defined (MDE_CPU_X64)\r | |
519 | if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r | |
520 | DEBUG ((EFI_D_ERROR,\r | |
521 | "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r | |
522 | DEBUG ((EFI_D_ERROR,\r | |
523 | "%a: Please disable S3 on the QEMU command line (see the README),\n",\r | |
524 | __FUNCTION__));\r | |
525 | DEBUG ((EFI_D_ERROR,\r | |
526 | "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r | |
527 | ASSERT (FALSE);\r | |
528 | CpuDeadLoop ();\r | |
529 | }\r | |
530 | #endif\r | |
531 | }\r | |
532 | \r | |
533 | \r | |
49ba9447 | 534 | /**\r |
535 | Perform Platform PEI initialization.\r | |
536 | \r | |
537 | @param FileHandle Handle of the file being invoked.\r | |
538 | @param PeiServices Describes the list of possible PEI Services.\r | |
539 | \r | |
540 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
541 | \r | |
542 | **/\r | |
543 | EFI_STATUS\r | |
544 | EFIAPI\r | |
545 | InitializePlatform (\r | |
546 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
547 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
548 | )\r | |
549 | {\r | |
a1726e30 SZ |
550 | EFI_STATUS Status;\r |
551 | \r | |
49ba9447 | 552 | DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r |
553 | \r | |
3ca15914 | 554 | DebugDumpCmos ();\r |
555 | \r | |
b98b4941 | 556 | XenDetect ();\r |
c7ea55b9 | 557 | \r |
7cdba634 JJ |
558 | if (QemuFwCfgS3Enabled ()) {\r |
559 | DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r | |
560 | mS3Supported = TRUE;\r | |
a1726e30 SZ |
561 | Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r |
562 | ASSERT_EFI_ERROR (Status);\r | |
7cdba634 JJ |
563 | }\r |
564 | \r | |
5133d1f1 | 565 | S3Verification ();\r |
869b17cc | 566 | BootModeInitialization ();\r |
bc89fe48 | 567 | AddressWidthInitialization ();\r |
869b17cc | 568 | \r |
f76e9eba JJ |
569 | PublishPeiMemory ();\r |
570 | \r | |
2818c158 | 571 | InitializeRamRegions ();\r |
49ba9447 | 572 | \r |
b621bb0a | 573 | if (mXen) {\r |
c7ea55b9 | 574 | DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r |
b98b4941 | 575 | InitializeXen ();\r |
c7ea55b9 | 576 | }\r |
eec7d420 | 577 | \r |
589756c7 PA |
578 | //\r |
579 | // Query Host Bridge DID\r | |
580 | //\r | |
581 | mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
582 | \r | |
bd386eaf JJ |
583 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
584 | ReserveEmuVariableNvStore ();\r | |
bd386eaf | 585 | PeiFvInitialization ();\r |
bd386eaf | 586 | MemMapInitialization ();\r |
ab081a50 | 587 | NoexecDxeInitialization ();\r |
bd386eaf | 588 | }\r |
49ba9447 | 589 | \r |
0e20a186 | 590 | MiscInitialization ();\r |
49ba9447 | 591 | \r |
592 | return EFI_SUCCESS;\r | |
593 | }\r |