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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
85f455f7 | 18 | #include "irq.h" |
1d737c8a | 19 | #include "mmu.h" |
e495606d | 20 | |
edf88417 | 21 | #include <linux/kvm_host.h> |
6aa8b732 | 22 | #include <linux/module.h> |
9d8f549d | 23 | #include <linux/kernel.h> |
6aa8b732 AK |
24 | #include <linux/mm.h> |
25 | #include <linux/highmem.h> | |
e8edc6e0 | 26 | #include <linux/sched.h> |
c7addb90 | 27 | #include <linux/moduleparam.h> |
229456fc | 28 | #include <linux/ftrace_event.h> |
5fdbf976 | 29 | #include "kvm_cache_regs.h" |
35920a35 | 30 | #include "x86.h" |
e495606d | 31 | |
6aa8b732 | 32 | #include <asm/io.h> |
3b3be0d1 | 33 | #include <asm/desc.h> |
13673a90 | 34 | #include <asm/vmx.h> |
6210e37b | 35 | #include <asm/virtext.h> |
a0861c02 | 36 | #include <asm/mce.h> |
6aa8b732 | 37 | |
229456fc MT |
38 | #include "trace.h" |
39 | ||
4ecac3fd AK |
40 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
41 | ||
6aa8b732 AK |
42 | MODULE_AUTHOR("Qumranet"); |
43 | MODULE_LICENSE("GPL"); | |
44 | ||
4462d21a | 45 | static int __read_mostly bypass_guest_pf = 1; |
c1f8bc04 | 46 | module_param(bypass_guest_pf, bool, S_IRUGO); |
c7addb90 | 47 | |
4462d21a | 48 | static int __read_mostly enable_vpid = 1; |
736caefe | 49 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 50 | |
4462d21a | 51 | static int __read_mostly flexpriority_enabled = 1; |
736caefe | 52 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 53 | |
4462d21a | 54 | static int __read_mostly enable_ept = 1; |
736caefe | 55 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 56 | |
3a624e29 NK |
57 | static int __read_mostly enable_unrestricted_guest = 1; |
58 | module_param_named(unrestricted_guest, | |
59 | enable_unrestricted_guest, bool, S_IRUGO); | |
60 | ||
4462d21a | 61 | static int __read_mostly emulate_invalid_guest_state = 0; |
c1f8bc04 | 62 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 63 | |
cdc0e244 AK |
64 | #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \ |
65 | (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD) | |
66 | #define KVM_GUEST_CR0_MASK \ | |
67 | (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
68 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \ | |
02daab21 | 69 | (X86_CR0_WP | X86_CR0_NE | X86_CR0_MP) |
cdc0e244 AK |
70 | #define KVM_VM_CR0_ALWAYS_ON \ |
71 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
72 | #define KVM_CR4_GUEST_OWNED_BITS \ |
73 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
74 | | X86_CR4_OSXMMEXCPT) | |
75 | ||
cdc0e244 AK |
76 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
77 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
78 | ||
4b8d54f9 ZE |
79 | /* |
80 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
81 | * ple_gap: upper bound on the amount of time between two successive | |
82 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
83 | * According to test, this time is usually small than 41 cycles. | |
84 | * ple_window: upper bound on the amount of time a guest is allowed to execute | |
85 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
86 | * less than 2^12 cycles | |
87 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
88 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
89 | */ | |
90 | #define KVM_VMX_DEFAULT_PLE_GAP 41 | |
91 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
92 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; | |
93 | module_param(ple_gap, int, S_IRUGO); | |
94 | ||
95 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
96 | module_param(ple_window, int, S_IRUGO); | |
97 | ||
a2fa3e9f GH |
98 | struct vmcs { |
99 | u32 revision_id; | |
100 | u32 abort; | |
101 | char data[0]; | |
102 | }; | |
103 | ||
26bb0981 AK |
104 | struct shared_msr_entry { |
105 | unsigned index; | |
106 | u64 data; | |
d5696725 | 107 | u64 mask; |
26bb0981 AK |
108 | }; |
109 | ||
a2fa3e9f | 110 | struct vcpu_vmx { |
fb3f0f51 | 111 | struct kvm_vcpu vcpu; |
543e4243 | 112 | struct list_head local_vcpus_link; |
313dbd49 | 113 | unsigned long host_rsp; |
a2fa3e9f | 114 | int launched; |
29bd8a78 | 115 | u8 fail; |
1155f76a | 116 | u32 idt_vectoring_info; |
26bb0981 | 117 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
118 | int nmsrs; |
119 | int save_nmsrs; | |
a2fa3e9f | 120 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
121 | u64 msr_host_kernel_gs_base; |
122 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f GH |
123 | #endif |
124 | struct vmcs *vmcs; | |
125 | struct { | |
126 | int loaded; | |
127 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
128 | int gs_ldt_reload_needed; |
129 | int fs_reload_needed; | |
d77c26fc | 130 | } host_state; |
9c8cba37 | 131 | struct { |
7ffd92c5 AK |
132 | int vm86_active; |
133 | u8 save_iopl; | |
134 | struct kvm_save_segment { | |
135 | u16 selector; | |
136 | unsigned long base; | |
137 | u32 limit; | |
138 | u32 ar; | |
139 | } tr, es, ds, fs, gs; | |
9c8cba37 AK |
140 | struct { |
141 | bool pending; | |
142 | u8 vector; | |
143 | unsigned rip; | |
144 | } irq; | |
145 | } rmode; | |
2384d2b3 | 146 | int vpid; |
04fa4d32 | 147 | bool emulation_required; |
3b86cd99 JK |
148 | |
149 | /* Support for vnmi-less CPUs */ | |
150 | int soft_vnmi_blocked; | |
151 | ktime_t entry_time; | |
152 | s64 vnmi_blocked_time; | |
a0861c02 | 153 | u32 exit_reason; |
4e47c7a6 SY |
154 | |
155 | bool rdtscp_enabled; | |
a2fa3e9f GH |
156 | }; |
157 | ||
158 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
159 | { | |
fb3f0f51 | 160 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
161 | } |
162 | ||
b7ebfb05 | 163 | static int init_rmode(struct kvm *kvm); |
4e1096d2 | 164 | static u64 construct_eptp(unsigned long root_hpa); |
75880a01 | 165 | |
6aa8b732 AK |
166 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
167 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
543e4243 | 168 | static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu); |
6aa8b732 | 169 | |
3e7c73e9 AK |
170 | static unsigned long *vmx_io_bitmap_a; |
171 | static unsigned long *vmx_io_bitmap_b; | |
5897297b AK |
172 | static unsigned long *vmx_msr_bitmap_legacy; |
173 | static unsigned long *vmx_msr_bitmap_longmode; | |
fdef3ad1 | 174 | |
2384d2b3 SY |
175 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
176 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
177 | ||
1c3d14fe | 178 | static struct vmcs_config { |
6aa8b732 AK |
179 | int size; |
180 | int order; | |
181 | u32 revision_id; | |
1c3d14fe YS |
182 | u32 pin_based_exec_ctrl; |
183 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 184 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
185 | u32 vmexit_ctrl; |
186 | u32 vmentry_ctrl; | |
187 | } vmcs_config; | |
6aa8b732 | 188 | |
efff9e53 | 189 | static struct vmx_capability { |
d56f546d SY |
190 | u32 ept; |
191 | u32 vpid; | |
192 | } vmx_capability; | |
193 | ||
6aa8b732 AK |
194 | #define VMX_SEGMENT_FIELD(seg) \ |
195 | [VCPU_SREG_##seg] = { \ | |
196 | .selector = GUEST_##seg##_SELECTOR, \ | |
197 | .base = GUEST_##seg##_BASE, \ | |
198 | .limit = GUEST_##seg##_LIMIT, \ | |
199 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
200 | } | |
201 | ||
202 | static struct kvm_vmx_segment_field { | |
203 | unsigned selector; | |
204 | unsigned base; | |
205 | unsigned limit; | |
206 | unsigned ar_bytes; | |
207 | } kvm_vmx_segment_fields[] = { | |
208 | VMX_SEGMENT_FIELD(CS), | |
209 | VMX_SEGMENT_FIELD(DS), | |
210 | VMX_SEGMENT_FIELD(ES), | |
211 | VMX_SEGMENT_FIELD(FS), | |
212 | VMX_SEGMENT_FIELD(GS), | |
213 | VMX_SEGMENT_FIELD(SS), | |
214 | VMX_SEGMENT_FIELD(TR), | |
215 | VMX_SEGMENT_FIELD(LDTR), | |
216 | }; | |
217 | ||
26bb0981 AK |
218 | static u64 host_efer; |
219 | ||
6de4f3ad AK |
220 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
221 | ||
4d56c8a7 AK |
222 | /* |
223 | * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it | |
224 | * away by decrementing the array size. | |
225 | */ | |
6aa8b732 | 226 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 227 | #ifdef CONFIG_X86_64 |
44ea2b17 | 228 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 229 | #endif |
4e47c7a6 | 230 | MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR, |
6aa8b732 | 231 | }; |
9d8f549d | 232 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 233 | |
6aa8b732 AK |
234 | static inline int is_page_fault(u32 intr_info) |
235 | { | |
236 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
237 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 238 | (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); |
6aa8b732 AK |
239 | } |
240 | ||
2ab455cc AL |
241 | static inline int is_no_device(u32 intr_info) |
242 | { | |
243 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
244 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 245 | (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); |
2ab455cc AL |
246 | } |
247 | ||
7aa81cc0 AL |
248 | static inline int is_invalid_opcode(u32 intr_info) |
249 | { | |
250 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
251 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 252 | (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); |
7aa81cc0 AL |
253 | } |
254 | ||
6aa8b732 AK |
255 | static inline int is_external_interrupt(u32 intr_info) |
256 | { | |
257 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
258 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
259 | } | |
260 | ||
a0861c02 AK |
261 | static inline int is_machine_check(u32 intr_info) |
262 | { | |
263 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
264 | INTR_INFO_VALID_MASK)) == | |
265 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
266 | } | |
267 | ||
25c5f225 SY |
268 | static inline int cpu_has_vmx_msr_bitmap(void) |
269 | { | |
04547156 | 270 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
271 | } |
272 | ||
6e5d865c YS |
273 | static inline int cpu_has_vmx_tpr_shadow(void) |
274 | { | |
04547156 | 275 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
276 | } |
277 | ||
278 | static inline int vm_need_tpr_shadow(struct kvm *kvm) | |
279 | { | |
04547156 | 280 | return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)); |
6e5d865c YS |
281 | } |
282 | ||
f78e0e2e SY |
283 | static inline int cpu_has_secondary_exec_ctrls(void) |
284 | { | |
04547156 SY |
285 | return vmcs_config.cpu_based_exec_ctrl & |
286 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
287 | } |
288 | ||
774ead3a | 289 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 290 | { |
04547156 SY |
291 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
292 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
293 | } | |
294 | ||
295 | static inline bool cpu_has_vmx_flexpriority(void) | |
296 | { | |
297 | return cpu_has_vmx_tpr_shadow() && | |
298 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
299 | } |
300 | ||
e799794e MT |
301 | static inline bool cpu_has_vmx_ept_execute_only(void) |
302 | { | |
303 | return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT); | |
304 | } | |
305 | ||
306 | static inline bool cpu_has_vmx_eptp_uncacheable(void) | |
307 | { | |
308 | return !!(vmx_capability.ept & VMX_EPTP_UC_BIT); | |
309 | } | |
310 | ||
311 | static inline bool cpu_has_vmx_eptp_writeback(void) | |
312 | { | |
313 | return !!(vmx_capability.ept & VMX_EPTP_WB_BIT); | |
314 | } | |
315 | ||
316 | static inline bool cpu_has_vmx_ept_2m_page(void) | |
317 | { | |
318 | return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT); | |
319 | } | |
320 | ||
878403b7 SY |
321 | static inline bool cpu_has_vmx_ept_1g_page(void) |
322 | { | |
323 | return !!(vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT); | |
324 | } | |
325 | ||
d56f546d SY |
326 | static inline int cpu_has_vmx_invept_individual_addr(void) |
327 | { | |
04547156 | 328 | return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT); |
d56f546d SY |
329 | } |
330 | ||
331 | static inline int cpu_has_vmx_invept_context(void) | |
332 | { | |
04547156 | 333 | return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT); |
d56f546d SY |
334 | } |
335 | ||
336 | static inline int cpu_has_vmx_invept_global(void) | |
337 | { | |
04547156 | 338 | return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT); |
d56f546d SY |
339 | } |
340 | ||
341 | static inline int cpu_has_vmx_ept(void) | |
342 | { | |
04547156 SY |
343 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
344 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
345 | } |
346 | ||
3a624e29 NK |
347 | static inline int cpu_has_vmx_unrestricted_guest(void) |
348 | { | |
349 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
350 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
351 | } | |
352 | ||
4b8d54f9 ZE |
353 | static inline int cpu_has_vmx_ple(void) |
354 | { | |
355 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
356 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
357 | } | |
358 | ||
f78e0e2e SY |
359 | static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm) |
360 | { | |
04547156 SY |
361 | return flexpriority_enabled && |
362 | (cpu_has_vmx_virtualize_apic_accesses()) && | |
363 | (irqchip_in_kernel(kvm)); | |
f78e0e2e SY |
364 | } |
365 | ||
2384d2b3 SY |
366 | static inline int cpu_has_vmx_vpid(void) |
367 | { | |
04547156 SY |
368 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
369 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
370 | } |
371 | ||
4e47c7a6 SY |
372 | static inline int cpu_has_vmx_rdtscp(void) |
373 | { | |
374 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
375 | SECONDARY_EXEC_RDTSCP; | |
376 | } | |
377 | ||
f08864b4 SY |
378 | static inline int cpu_has_virtual_nmis(void) |
379 | { | |
380 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
381 | } | |
382 | ||
04547156 SY |
383 | static inline bool report_flexpriority(void) |
384 | { | |
385 | return flexpriority_enabled; | |
386 | } | |
387 | ||
8b9cf98c | 388 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
389 | { |
390 | int i; | |
391 | ||
a2fa3e9f | 392 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 393 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
394 | return i; |
395 | return -1; | |
396 | } | |
397 | ||
2384d2b3 SY |
398 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
399 | { | |
400 | struct { | |
401 | u64 vpid : 16; | |
402 | u64 rsvd : 48; | |
403 | u64 gva; | |
404 | } operand = { vpid, 0, gva }; | |
405 | ||
4ecac3fd | 406 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
407 | /* CF==1 or ZF==1 --> rc = -1 */ |
408 | "; ja 1f ; ud2 ; 1:" | |
409 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
410 | } | |
411 | ||
1439442c SY |
412 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
413 | { | |
414 | struct { | |
415 | u64 eptp, gpa; | |
416 | } operand = {eptp, gpa}; | |
417 | ||
4ecac3fd | 418 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
419 | /* CF==1 or ZF==1 --> rc = -1 */ |
420 | "; ja 1f ; ud2 ; 1:\n" | |
421 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
422 | } | |
423 | ||
26bb0981 | 424 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
425 | { |
426 | int i; | |
427 | ||
8b9cf98c | 428 | i = __find_msr_index(vmx, msr); |
a75beee6 | 429 | if (i >= 0) |
a2fa3e9f | 430 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 431 | return NULL; |
7725f0ba AK |
432 | } |
433 | ||
6aa8b732 AK |
434 | static void vmcs_clear(struct vmcs *vmcs) |
435 | { | |
436 | u64 phys_addr = __pa(vmcs); | |
437 | u8 error; | |
438 | ||
4ecac3fd | 439 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
6aa8b732 AK |
440 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
441 | : "cc", "memory"); | |
442 | if (error) | |
443 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
444 | vmcs, phys_addr); | |
445 | } | |
446 | ||
447 | static void __vcpu_clear(void *arg) | |
448 | { | |
8b9cf98c | 449 | struct vcpu_vmx *vmx = arg; |
d3b2c338 | 450 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 451 | |
8b9cf98c | 452 | if (vmx->vcpu.cpu == cpu) |
a2fa3e9f GH |
453 | vmcs_clear(vmx->vmcs); |
454 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
6aa8b732 | 455 | per_cpu(current_vmcs, cpu) = NULL; |
ad312c7c | 456 | rdtscll(vmx->vcpu.arch.host_tsc); |
543e4243 AK |
457 | list_del(&vmx->local_vcpus_link); |
458 | vmx->vcpu.cpu = -1; | |
459 | vmx->launched = 0; | |
6aa8b732 AK |
460 | } |
461 | ||
8b9cf98c | 462 | static void vcpu_clear(struct vcpu_vmx *vmx) |
8d0be2b3 | 463 | { |
eae5ecb5 AK |
464 | if (vmx->vcpu.cpu == -1) |
465 | return; | |
8691e5a8 | 466 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1); |
8d0be2b3 AK |
467 | } |
468 | ||
2384d2b3 SY |
469 | static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx) |
470 | { | |
471 | if (vmx->vpid == 0) | |
472 | return; | |
473 | ||
474 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
475 | } | |
476 | ||
1439442c SY |
477 | static inline void ept_sync_global(void) |
478 | { | |
479 | if (cpu_has_vmx_invept_global()) | |
480 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
481 | } | |
482 | ||
483 | static inline void ept_sync_context(u64 eptp) | |
484 | { | |
089d034e | 485 | if (enable_ept) { |
1439442c SY |
486 | if (cpu_has_vmx_invept_context()) |
487 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
488 | else | |
489 | ept_sync_global(); | |
490 | } | |
491 | } | |
492 | ||
493 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) | |
494 | { | |
089d034e | 495 | if (enable_ept) { |
1439442c SY |
496 | if (cpu_has_vmx_invept_individual_addr()) |
497 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, | |
498 | eptp, gpa); | |
499 | else | |
500 | ept_sync_context(eptp); | |
501 | } | |
502 | } | |
503 | ||
6aa8b732 AK |
504 | static unsigned long vmcs_readl(unsigned long field) |
505 | { | |
506 | unsigned long value; | |
507 | ||
4ecac3fd | 508 | asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX) |
6aa8b732 AK |
509 | : "=a"(value) : "d"(field) : "cc"); |
510 | return value; | |
511 | } | |
512 | ||
513 | static u16 vmcs_read16(unsigned long field) | |
514 | { | |
515 | return vmcs_readl(field); | |
516 | } | |
517 | ||
518 | static u32 vmcs_read32(unsigned long field) | |
519 | { | |
520 | return vmcs_readl(field); | |
521 | } | |
522 | ||
523 | static u64 vmcs_read64(unsigned long field) | |
524 | { | |
05b3e0c2 | 525 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
526 | return vmcs_readl(field); |
527 | #else | |
528 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
529 | #endif | |
530 | } | |
531 | ||
e52de1b8 AK |
532 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
533 | { | |
534 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
535 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
536 | dump_stack(); | |
537 | } | |
538 | ||
6aa8b732 AK |
539 | static void vmcs_writel(unsigned long field, unsigned long value) |
540 | { | |
541 | u8 error; | |
542 | ||
4ecac3fd | 543 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 544 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
545 | if (unlikely(error)) |
546 | vmwrite_error(field, value); | |
6aa8b732 AK |
547 | } |
548 | ||
549 | static void vmcs_write16(unsigned long field, u16 value) | |
550 | { | |
551 | vmcs_writel(field, value); | |
552 | } | |
553 | ||
554 | static void vmcs_write32(unsigned long field, u32 value) | |
555 | { | |
556 | vmcs_writel(field, value); | |
557 | } | |
558 | ||
559 | static void vmcs_write64(unsigned long field, u64 value) | |
560 | { | |
6aa8b732 | 561 | vmcs_writel(field, value); |
7682f2d0 | 562 | #ifndef CONFIG_X86_64 |
6aa8b732 AK |
563 | asm volatile (""); |
564 | vmcs_writel(field+1, value >> 32); | |
565 | #endif | |
566 | } | |
567 | ||
2ab455cc AL |
568 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
569 | { | |
570 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
571 | } | |
572 | ||
573 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
574 | { | |
575 | vmcs_writel(field, vmcs_readl(field) | mask); | |
576 | } | |
577 | ||
abd3f2d6 AK |
578 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
579 | { | |
580 | u32 eb; | |
581 | ||
02daab21 AK |
582 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
583 | | (1u << NM_VECTOR); | |
e8a48342 AK |
584 | /* |
585 | * Unconditionally intercept #DB so we can maintain dr6 without | |
586 | * reading it every exit. | |
587 | */ | |
588 | eb |= 1u << DB_VECTOR; | |
d0bfb940 | 589 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
d0bfb940 JK |
590 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
591 | eb |= 1u << BP_VECTOR; | |
592 | } | |
7ffd92c5 | 593 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 594 | eb = ~0; |
089d034e | 595 | if (enable_ept) |
1439442c | 596 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
02daab21 AK |
597 | if (vcpu->fpu_active) |
598 | eb &= ~(1u << NM_VECTOR); | |
abd3f2d6 AK |
599 | vmcs_write32(EXCEPTION_BITMAP, eb); |
600 | } | |
601 | ||
33ed6329 AK |
602 | static void reload_tss(void) |
603 | { | |
33ed6329 AK |
604 | /* |
605 | * VT restores TR but not its size. Useless. | |
606 | */ | |
607 | struct descriptor_table gdt; | |
a5f61300 | 608 | struct desc_struct *descs; |
33ed6329 | 609 | |
d6e88aec | 610 | kvm_get_gdt(&gdt); |
33ed6329 AK |
611 | descs = (void *)gdt.base; |
612 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
613 | load_TR_desc(); | |
33ed6329 AK |
614 | } |
615 | ||
92c0d900 | 616 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 617 | { |
3a34a881 | 618 | u64 guest_efer; |
51c6cf66 AK |
619 | u64 ignore_bits; |
620 | ||
26bb0981 | 621 | guest_efer = vmx->vcpu.arch.shadow_efer; |
3a34a881 | 622 | |
51c6cf66 AK |
623 | /* |
624 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
625 | * outside long mode | |
626 | */ | |
627 | ignore_bits = EFER_NX | EFER_SCE; | |
628 | #ifdef CONFIG_X86_64 | |
629 | ignore_bits |= EFER_LMA | EFER_LME; | |
630 | /* SCE is meaningful only in long mode on Intel */ | |
631 | if (guest_efer & EFER_LMA) | |
632 | ignore_bits &= ~(u64)EFER_SCE; | |
633 | #endif | |
51c6cf66 AK |
634 | guest_efer &= ~ignore_bits; |
635 | guest_efer |= host_efer & ignore_bits; | |
26bb0981 | 636 | vmx->guest_msrs[efer_offset].data = guest_efer; |
d5696725 | 637 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; |
26bb0981 | 638 | return true; |
51c6cf66 AK |
639 | } |
640 | ||
04d2cc77 | 641 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 642 | { |
04d2cc77 | 643 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 644 | int i; |
04d2cc77 | 645 | |
a2fa3e9f | 646 | if (vmx->host_state.loaded) |
33ed6329 AK |
647 | return; |
648 | ||
a2fa3e9f | 649 | vmx->host_state.loaded = 1; |
33ed6329 AK |
650 | /* |
651 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
652 | * allow segment selectors with cpl > 0 or ti == 1. | |
653 | */ | |
d6e88aec | 654 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 655 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
d6e88aec | 656 | vmx->host_state.fs_sel = kvm_read_fs(); |
152d3f2f | 657 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 658 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
659 | vmx->host_state.fs_reload_needed = 0; |
660 | } else { | |
33ed6329 | 661 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 662 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 663 | } |
d6e88aec | 664 | vmx->host_state.gs_sel = kvm_read_gs(); |
a2fa3e9f GH |
665 | if (!(vmx->host_state.gs_sel & 7)) |
666 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
667 | else { |
668 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 669 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
670 | } |
671 | ||
672 | #ifdef CONFIG_X86_64 | |
673 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
674 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
675 | #else | |
a2fa3e9f GH |
676 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
677 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 678 | #endif |
707c0874 AK |
679 | |
680 | #ifdef CONFIG_X86_64 | |
44ea2b17 AK |
681 | if (is_long_mode(&vmx->vcpu)) { |
682 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); | |
683 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
684 | } | |
707c0874 | 685 | #endif |
26bb0981 AK |
686 | for (i = 0; i < vmx->save_nmsrs; ++i) |
687 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
688 | vmx->guest_msrs[i].data, |
689 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
690 | } |
691 | ||
a9b21b62 | 692 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 693 | { |
15ad7146 | 694 | unsigned long flags; |
33ed6329 | 695 | |
a2fa3e9f | 696 | if (!vmx->host_state.loaded) |
33ed6329 AK |
697 | return; |
698 | ||
e1beb1d3 | 699 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 700 | vmx->host_state.loaded = 0; |
152d3f2f | 701 | if (vmx->host_state.fs_reload_needed) |
d6e88aec | 702 | kvm_load_fs(vmx->host_state.fs_sel); |
152d3f2f | 703 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 704 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 AK |
705 | /* |
706 | * If we have to reload gs, we must take care to | |
707 | * preserve our gs base. | |
708 | */ | |
15ad7146 | 709 | local_irq_save(flags); |
d6e88aec | 710 | kvm_load_gs(vmx->host_state.gs_sel); |
33ed6329 AK |
711 | #ifdef CONFIG_X86_64 |
712 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); | |
713 | #endif | |
15ad7146 | 714 | local_irq_restore(flags); |
33ed6329 | 715 | } |
152d3f2f | 716 | reload_tss(); |
44ea2b17 AK |
717 | #ifdef CONFIG_X86_64 |
718 | if (is_long_mode(&vmx->vcpu)) { | |
719 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
720 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); | |
721 | } | |
722 | #endif | |
33ed6329 AK |
723 | } |
724 | ||
a9b21b62 AK |
725 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
726 | { | |
727 | preempt_disable(); | |
728 | __vmx_load_host_state(vmx); | |
729 | preempt_enable(); | |
730 | } | |
731 | ||
6aa8b732 AK |
732 | /* |
733 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
734 | * vcpu mutex is already taken. | |
735 | */ | |
15ad7146 | 736 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 737 | { |
a2fa3e9f GH |
738 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
739 | u64 phys_addr = __pa(vmx->vmcs); | |
019960ae | 740 | u64 tsc_this, delta, new_offset; |
6aa8b732 | 741 | |
a3d7f85f | 742 | if (vcpu->cpu != cpu) { |
8b9cf98c | 743 | vcpu_clear(vmx); |
2f599714 | 744 | kvm_migrate_timers(vcpu); |
eb5109e3 | 745 | set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests); |
543e4243 AK |
746 | local_irq_disable(); |
747 | list_add(&vmx->local_vcpus_link, | |
748 | &per_cpu(vcpus_on_cpu, cpu)); | |
749 | local_irq_enable(); | |
a3d7f85f | 750 | } |
6aa8b732 | 751 | |
a2fa3e9f | 752 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { |
6aa8b732 AK |
753 | u8 error; |
754 | ||
a2fa3e9f | 755 | per_cpu(current_vmcs, cpu) = vmx->vmcs; |
4ecac3fd | 756 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" |
6aa8b732 AK |
757 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
758 | : "cc"); | |
759 | if (error) | |
760 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
a2fa3e9f | 761 | vmx->vmcs, phys_addr); |
6aa8b732 AK |
762 | } |
763 | ||
764 | if (vcpu->cpu != cpu) { | |
765 | struct descriptor_table dt; | |
766 | unsigned long sysenter_esp; | |
767 | ||
768 | vcpu->cpu = cpu; | |
769 | /* | |
770 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
771 | * processors. | |
772 | */ | |
d6e88aec AK |
773 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
774 | kvm_get_gdt(&dt); | |
6aa8b732 AK |
775 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ |
776 | ||
777 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
778 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
7700270e AK |
779 | |
780 | /* | |
781 | * Make sure the time stamp counter is monotonous. | |
782 | */ | |
783 | rdtscll(tsc_this); | |
019960ae AK |
784 | if (tsc_this < vcpu->arch.host_tsc) { |
785 | delta = vcpu->arch.host_tsc - tsc_this; | |
786 | new_offset = vmcs_read64(TSC_OFFSET) + delta; | |
787 | vmcs_write64(TSC_OFFSET, new_offset); | |
788 | } | |
6aa8b732 | 789 | } |
6aa8b732 AK |
790 | } |
791 | ||
792 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
793 | { | |
a9b21b62 | 794 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
795 | } |
796 | ||
5fd86fcf AK |
797 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
798 | { | |
799 | if (vcpu->fpu_active) | |
800 | return; | |
801 | vcpu->fpu_active = 1; | |
707d92fa | 802 | vmcs_clear_bits(GUEST_CR0, X86_CR0_TS); |
4d4ec087 | 803 | if (kvm_read_cr0_bits(vcpu, X86_CR0_TS)) |
707d92fa | 804 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf | 805 | update_exception_bitmap(vcpu); |
edcafe3c AK |
806 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
807 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
5fd86fcf AK |
808 | } |
809 | ||
edcafe3c AK |
810 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
811 | ||
5fd86fcf AK |
812 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) |
813 | { | |
edcafe3c | 814 | vmx_decache_cr0_guest_bits(vcpu); |
707d92fa | 815 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf | 816 | update_exception_bitmap(vcpu); |
edcafe3c AK |
817 | vcpu->arch.cr0_guest_owned_bits = 0; |
818 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
819 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf AK |
820 | } |
821 | ||
6aa8b732 AK |
822 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
823 | { | |
345dcaa8 AK |
824 | unsigned long rflags; |
825 | ||
826 | rflags = vmcs_readl(GUEST_RFLAGS); | |
827 | if (to_vmx(vcpu)->rmode.vm86_active) | |
828 | rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM); | |
829 | return rflags; | |
6aa8b732 AK |
830 | } |
831 | ||
832 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
833 | { | |
7ffd92c5 | 834 | if (to_vmx(vcpu)->rmode.vm86_active) |
053de044 | 835 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
836 | vmcs_writel(GUEST_RFLAGS, rflags); |
837 | } | |
838 | ||
2809f5d2 GC |
839 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
840 | { | |
841 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
842 | int ret = 0; | |
843 | ||
844 | if (interruptibility & GUEST_INTR_STATE_STI) | |
845 | ret |= X86_SHADOW_INT_STI; | |
846 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) | |
847 | ret |= X86_SHADOW_INT_MOV_SS; | |
848 | ||
849 | return ret & mask; | |
850 | } | |
851 | ||
852 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
853 | { | |
854 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
855 | u32 interruptibility = interruptibility_old; | |
856 | ||
857 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
858 | ||
859 | if (mask & X86_SHADOW_INT_MOV_SS) | |
860 | interruptibility |= GUEST_INTR_STATE_MOV_SS; | |
861 | if (mask & X86_SHADOW_INT_STI) | |
862 | interruptibility |= GUEST_INTR_STATE_STI; | |
863 | ||
864 | if ((interruptibility != interruptibility_old)) | |
865 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
866 | } | |
867 | ||
6aa8b732 AK |
868 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
869 | { | |
870 | unsigned long rip; | |
6aa8b732 | 871 | |
5fdbf976 | 872 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 873 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 874 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 875 | |
2809f5d2 GC |
876 | /* skipping an emulated instruction also counts */ |
877 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
878 | } |
879 | ||
298101da AK |
880 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
881 | bool has_error_code, u32 error_code) | |
882 | { | |
77ab6db0 | 883 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8ab2d2e2 | 884 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 885 | |
8ab2d2e2 | 886 | if (has_error_code) { |
77ab6db0 | 887 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
888 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
889 | } | |
77ab6db0 | 890 | |
7ffd92c5 | 891 | if (vmx->rmode.vm86_active) { |
77ab6db0 JK |
892 | vmx->rmode.irq.pending = true; |
893 | vmx->rmode.irq.vector = nr; | |
894 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | |
ae0bb3e0 GN |
895 | if (kvm_exception_is_soft(nr)) |
896 | vmx->rmode.irq.rip += | |
897 | vmx->vcpu.arch.event_exit_inst_len; | |
8ab2d2e2 JK |
898 | intr_info |= INTR_TYPE_SOFT_INTR; |
899 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
77ab6db0 JK |
900 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); |
901 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); | |
902 | return; | |
903 | } | |
904 | ||
66fd3f7f GN |
905 | if (kvm_exception_is_soft(nr)) { |
906 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
907 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
908 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
909 | } else | |
910 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
911 | ||
912 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
913 | } |
914 | ||
4e47c7a6 SY |
915 | static bool vmx_rdtscp_supported(void) |
916 | { | |
917 | return cpu_has_vmx_rdtscp(); | |
918 | } | |
919 | ||
a75beee6 ED |
920 | /* |
921 | * Swap MSR entry in host/guest MSR entry array. | |
922 | */ | |
8b9cf98c | 923 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 924 | { |
26bb0981 | 925 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
926 | |
927 | tmp = vmx->guest_msrs[to]; | |
928 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
929 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
930 | } |
931 | ||
e38aea3e AK |
932 | /* |
933 | * Set up the vmcs to automatically save and restore system | |
934 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
935 | * mode, as fiddling with msrs is very expensive. | |
936 | */ | |
8b9cf98c | 937 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 938 | { |
26bb0981 | 939 | int save_nmsrs, index; |
5897297b | 940 | unsigned long *msr_bitmap; |
e38aea3e | 941 | |
33f9c505 | 942 | vmx_load_host_state(vmx); |
a75beee6 ED |
943 | save_nmsrs = 0; |
944 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 945 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 946 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 947 | if (index >= 0) |
8b9cf98c RR |
948 | move_msr_up(vmx, index, save_nmsrs++); |
949 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 950 | if (index >= 0) |
8b9cf98c RR |
951 | move_msr_up(vmx, index, save_nmsrs++); |
952 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 953 | if (index >= 0) |
8b9cf98c | 954 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 SY |
955 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
956 | if (index >= 0 && vmx->rdtscp_enabled) | |
957 | move_msr_up(vmx, index, save_nmsrs++); | |
a75beee6 ED |
958 | /* |
959 | * MSR_K6_STAR is only needed on long mode guests, and only | |
960 | * if efer.sce is enabled. | |
961 | */ | |
8b9cf98c | 962 | index = __find_msr_index(vmx, MSR_K6_STAR); |
ad312c7c | 963 | if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE)) |
8b9cf98c | 964 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
965 | } |
966 | #endif | |
92c0d900 AK |
967 | index = __find_msr_index(vmx, MSR_EFER); |
968 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 969 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 970 | |
26bb0981 | 971 | vmx->save_nmsrs = save_nmsrs; |
5897297b AK |
972 | |
973 | if (cpu_has_vmx_msr_bitmap()) { | |
974 | if (is_long_mode(&vmx->vcpu)) | |
975 | msr_bitmap = vmx_msr_bitmap_longmode; | |
976 | else | |
977 | msr_bitmap = vmx_msr_bitmap_legacy; | |
978 | ||
979 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
980 | } | |
e38aea3e AK |
981 | } |
982 | ||
6aa8b732 AK |
983 | /* |
984 | * reads and returns guest's timestamp counter "register" | |
985 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
986 | */ | |
987 | static u64 guest_read_tsc(void) | |
988 | { | |
989 | u64 host_tsc, tsc_offset; | |
990 | ||
991 | rdtscll(host_tsc); | |
992 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
993 | return host_tsc + tsc_offset; | |
994 | } | |
995 | ||
996 | /* | |
997 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
998 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
999 | */ | |
53f658b3 | 1000 | static void guest_write_tsc(u64 guest_tsc, u64 host_tsc) |
6aa8b732 | 1001 | { |
6aa8b732 AK |
1002 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); |
1003 | } | |
1004 | ||
6aa8b732 AK |
1005 | /* |
1006 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1007 | * Returns 0 on success, non-0 otherwise. | |
1008 | * Assumes vcpu_load() was already called. | |
1009 | */ | |
1010 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1011 | { | |
1012 | u64 data; | |
26bb0981 | 1013 | struct shared_msr_entry *msr; |
6aa8b732 AK |
1014 | |
1015 | if (!pdata) { | |
1016 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
1017 | return -EINVAL; | |
1018 | } | |
1019 | ||
1020 | switch (msr_index) { | |
05b3e0c2 | 1021 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1022 | case MSR_FS_BASE: |
1023 | data = vmcs_readl(GUEST_FS_BASE); | |
1024 | break; | |
1025 | case MSR_GS_BASE: | |
1026 | data = vmcs_readl(GUEST_GS_BASE); | |
1027 | break; | |
44ea2b17 AK |
1028 | case MSR_KERNEL_GS_BASE: |
1029 | vmx_load_host_state(to_vmx(vcpu)); | |
1030 | data = to_vmx(vcpu)->msr_guest_kernel_gs_base; | |
1031 | break; | |
26bb0981 | 1032 | #endif |
6aa8b732 | 1033 | case MSR_EFER: |
3bab1f5d | 1034 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
af24a4e4 | 1035 | case MSR_IA32_TSC: |
6aa8b732 AK |
1036 | data = guest_read_tsc(); |
1037 | break; | |
1038 | case MSR_IA32_SYSENTER_CS: | |
1039 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
1040 | break; | |
1041 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 1042 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
1043 | break; |
1044 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 1045 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 1046 | break; |
4e47c7a6 SY |
1047 | case MSR_TSC_AUX: |
1048 | if (!to_vmx(vcpu)->rdtscp_enabled) | |
1049 | return 1; | |
1050 | /* Otherwise falls through */ | |
6aa8b732 | 1051 | default: |
26bb0981 | 1052 | vmx_load_host_state(to_vmx(vcpu)); |
8b9cf98c | 1053 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d | 1054 | if (msr) { |
542423b0 | 1055 | vmx_load_host_state(to_vmx(vcpu)); |
3bab1f5d AK |
1056 | data = msr->data; |
1057 | break; | |
6aa8b732 | 1058 | } |
3bab1f5d | 1059 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
1060 | } |
1061 | ||
1062 | *pdata = data; | |
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | /* | |
1067 | * Writes msr value into into the appropriate "register". | |
1068 | * Returns 0 on success, non-0 otherwise. | |
1069 | * Assumes vcpu_load() was already called. | |
1070 | */ | |
1071 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
1072 | { | |
a2fa3e9f | 1073 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 1074 | struct shared_msr_entry *msr; |
53f658b3 | 1075 | u64 host_tsc; |
2cc51560 ED |
1076 | int ret = 0; |
1077 | ||
6aa8b732 | 1078 | switch (msr_index) { |
3bab1f5d | 1079 | case MSR_EFER: |
a9b21b62 | 1080 | vmx_load_host_state(vmx); |
2cc51560 | 1081 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
2cc51560 | 1082 | break; |
16175a79 | 1083 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1084 | case MSR_FS_BASE: |
1085 | vmcs_writel(GUEST_FS_BASE, data); | |
1086 | break; | |
1087 | case MSR_GS_BASE: | |
1088 | vmcs_writel(GUEST_GS_BASE, data); | |
1089 | break; | |
44ea2b17 AK |
1090 | case MSR_KERNEL_GS_BASE: |
1091 | vmx_load_host_state(vmx); | |
1092 | vmx->msr_guest_kernel_gs_base = data; | |
1093 | break; | |
6aa8b732 AK |
1094 | #endif |
1095 | case MSR_IA32_SYSENTER_CS: | |
1096 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
1097 | break; | |
1098 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 1099 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
1100 | break; |
1101 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 1102 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 1103 | break; |
af24a4e4 | 1104 | case MSR_IA32_TSC: |
53f658b3 MT |
1105 | rdtscll(host_tsc); |
1106 | guest_write_tsc(data, host_tsc); | |
6aa8b732 | 1107 | break; |
468d472f SY |
1108 | case MSR_IA32_CR_PAT: |
1109 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
1110 | vmcs_write64(GUEST_IA32_PAT, data); | |
1111 | vcpu->arch.pat = data; | |
1112 | break; | |
1113 | } | |
4e47c7a6 SY |
1114 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
1115 | break; | |
1116 | case MSR_TSC_AUX: | |
1117 | if (!vmx->rdtscp_enabled) | |
1118 | return 1; | |
1119 | /* Check reserved bit, higher 32 bits should be zero */ | |
1120 | if ((data >> 32) != 0) | |
1121 | return 1; | |
1122 | /* Otherwise falls through */ | |
6aa8b732 | 1123 | default: |
8b9cf98c | 1124 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 1125 | if (msr) { |
542423b0 | 1126 | vmx_load_host_state(vmx); |
3bab1f5d AK |
1127 | msr->data = data; |
1128 | break; | |
6aa8b732 | 1129 | } |
2cc51560 | 1130 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
1131 | } |
1132 | ||
2cc51560 | 1133 | return ret; |
6aa8b732 AK |
1134 | } |
1135 | ||
5fdbf976 | 1136 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 1137 | { |
5fdbf976 MT |
1138 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
1139 | switch (reg) { | |
1140 | case VCPU_REGS_RSP: | |
1141 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
1142 | break; | |
1143 | case VCPU_REGS_RIP: | |
1144 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
1145 | break; | |
6de4f3ad AK |
1146 | case VCPU_EXREG_PDPTR: |
1147 | if (enable_ept) | |
1148 | ept_save_pdptrs(vcpu); | |
1149 | break; | |
5fdbf976 MT |
1150 | default: |
1151 | break; | |
1152 | } | |
6aa8b732 AK |
1153 | } |
1154 | ||
355be0b9 | 1155 | static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
6aa8b732 | 1156 | { |
ae675ef0 JK |
1157 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1158 | vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]); | |
1159 | else | |
1160 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
1161 | ||
abd3f2d6 | 1162 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
1163 | } |
1164 | ||
1165 | static __init int cpu_has_kvm_support(void) | |
1166 | { | |
6210e37b | 1167 | return cpu_has_vmx(); |
6aa8b732 AK |
1168 | } |
1169 | ||
1170 | static __init int vmx_disabled_by_bios(void) | |
1171 | { | |
1172 | u64 msr; | |
1173 | ||
1174 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
9ea542fa SY |
1175 | return (msr & (FEATURE_CONTROL_LOCKED | |
1176 | FEATURE_CONTROL_VMXON_ENABLED)) | |
1177 | == FEATURE_CONTROL_LOCKED; | |
62b3ffb8 | 1178 | /* locked but not enabled */ |
6aa8b732 AK |
1179 | } |
1180 | ||
10474ae8 | 1181 | static int hardware_enable(void *garbage) |
6aa8b732 AK |
1182 | { |
1183 | int cpu = raw_smp_processor_id(); | |
1184 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
1185 | u64 old; | |
1186 | ||
10474ae8 AG |
1187 | if (read_cr4() & X86_CR4_VMXE) |
1188 | return -EBUSY; | |
1189 | ||
543e4243 | 1190 | INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu)); |
6aa8b732 | 1191 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
9ea542fa SY |
1192 | if ((old & (FEATURE_CONTROL_LOCKED | |
1193 | FEATURE_CONTROL_VMXON_ENABLED)) | |
1194 | != (FEATURE_CONTROL_LOCKED | | |
1195 | FEATURE_CONTROL_VMXON_ENABLED)) | |
6aa8b732 | 1196 | /* enable and lock */ |
62b3ffb8 | 1197 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | |
9ea542fa SY |
1198 | FEATURE_CONTROL_LOCKED | |
1199 | FEATURE_CONTROL_VMXON_ENABLED); | |
66aee91a | 1200 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
4ecac3fd AK |
1201 | asm volatile (ASM_VMX_VMXON_RAX |
1202 | : : "a"(&phys_addr), "m"(phys_addr) | |
6aa8b732 | 1203 | : "memory", "cc"); |
10474ae8 AG |
1204 | |
1205 | ept_sync_global(); | |
1206 | ||
1207 | return 0; | |
6aa8b732 AK |
1208 | } |
1209 | ||
543e4243 AK |
1210 | static void vmclear_local_vcpus(void) |
1211 | { | |
1212 | int cpu = raw_smp_processor_id(); | |
1213 | struct vcpu_vmx *vmx, *n; | |
1214 | ||
1215 | list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu), | |
1216 | local_vcpus_link) | |
1217 | __vcpu_clear(vmx); | |
1218 | } | |
1219 | ||
710ff4a8 EH |
1220 | |
1221 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
1222 | * tricks. | |
1223 | */ | |
1224 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 1225 | { |
4ecac3fd | 1226 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
e693d71b | 1227 | write_cr4(read_cr4() & ~X86_CR4_VMXE); |
6aa8b732 AK |
1228 | } |
1229 | ||
710ff4a8 EH |
1230 | static void hardware_disable(void *garbage) |
1231 | { | |
1232 | vmclear_local_vcpus(); | |
1233 | kvm_cpu_vmxoff(); | |
1234 | } | |
1235 | ||
1c3d14fe | 1236 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 1237 | u32 msr, u32 *result) |
1c3d14fe YS |
1238 | { |
1239 | u32 vmx_msr_low, vmx_msr_high; | |
1240 | u32 ctl = ctl_min | ctl_opt; | |
1241 | ||
1242 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1243 | ||
1244 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
1245 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
1246 | ||
1247 | /* Ensure minimum (required) set of control bits are supported. */ | |
1248 | if (ctl_min & ~ctl) | |
002c7f7c | 1249 | return -EIO; |
1c3d14fe YS |
1250 | |
1251 | *result = ctl; | |
1252 | return 0; | |
1253 | } | |
1254 | ||
002c7f7c | 1255 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
1256 | { |
1257 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 1258 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
1259 | u32 _pin_based_exec_control = 0; |
1260 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 1261 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
1262 | u32 _vmexit_control = 0; |
1263 | u32 _vmentry_control = 0; | |
1264 | ||
1265 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
f08864b4 | 1266 | opt = PIN_BASED_VIRTUAL_NMIS; |
1c3d14fe YS |
1267 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
1268 | &_pin_based_exec_control) < 0) | |
002c7f7c | 1269 | return -EIO; |
1c3d14fe YS |
1270 | |
1271 | min = CPU_BASED_HLT_EXITING | | |
1272 | #ifdef CONFIG_X86_64 | |
1273 | CPU_BASED_CR8_LOAD_EXITING | | |
1274 | CPU_BASED_CR8_STORE_EXITING | | |
1275 | #endif | |
d56f546d SY |
1276 | CPU_BASED_CR3_LOAD_EXITING | |
1277 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
1278 | CPU_BASED_USE_IO_BITMAPS | |
1279 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 1280 | CPU_BASED_USE_TSC_OFFSETING | |
59708670 SY |
1281 | CPU_BASED_MWAIT_EXITING | |
1282 | CPU_BASED_MONITOR_EXITING | | |
a7052897 | 1283 | CPU_BASED_INVLPG_EXITING; |
f78e0e2e | 1284 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 1285 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 1286 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
1287 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1288 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 1289 | return -EIO; |
6e5d865c YS |
1290 | #ifdef CONFIG_X86_64 |
1291 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
1292 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
1293 | ~CPU_BASED_CR8_STORE_EXITING; | |
1294 | #endif | |
f78e0e2e | 1295 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
1296 | min2 = 0; |
1297 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
2384d2b3 | 1298 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 1299 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 1300 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 1301 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 SY |
1302 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
1303 | SECONDARY_EXEC_RDTSCP; | |
d56f546d SY |
1304 | if (adjust_vmx_controls(min2, opt2, |
1305 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
1306 | &_cpu_based_2nd_exec_control) < 0) |
1307 | return -EIO; | |
1308 | } | |
1309 | #ifndef CONFIG_X86_64 | |
1310 | if (!(_cpu_based_2nd_exec_control & | |
1311 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
1312 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1313 | #endif | |
d56f546d | 1314 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
1315 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
1316 | enabled */ | |
5fff7d27 GN |
1317 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
1318 | CPU_BASED_CR3_STORE_EXITING | | |
1319 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
1320 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
1321 | vmx_capability.ept, vmx_capability.vpid); | |
1322 | } | |
1c3d14fe YS |
1323 | |
1324 | min = 0; | |
1325 | #ifdef CONFIG_X86_64 | |
1326 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1327 | #endif | |
468d472f | 1328 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT; |
1c3d14fe YS |
1329 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
1330 | &_vmexit_control) < 0) | |
002c7f7c | 1331 | return -EIO; |
1c3d14fe | 1332 | |
468d472f SY |
1333 | min = 0; |
1334 | opt = VM_ENTRY_LOAD_IA32_PAT; | |
1c3d14fe YS |
1335 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
1336 | &_vmentry_control) < 0) | |
002c7f7c | 1337 | return -EIO; |
6aa8b732 | 1338 | |
c68876fd | 1339 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
1340 | |
1341 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
1342 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 1343 | return -EIO; |
1c3d14fe YS |
1344 | |
1345 | #ifdef CONFIG_X86_64 | |
1346 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
1347 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 1348 | return -EIO; |
1c3d14fe YS |
1349 | #endif |
1350 | ||
1351 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
1352 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 1353 | return -EIO; |
1c3d14fe | 1354 | |
002c7f7c YS |
1355 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
1356 | vmcs_conf->order = get_order(vmcs_config.size); | |
1357 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 1358 | |
002c7f7c YS |
1359 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
1360 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 1361 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
1362 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
1363 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe YS |
1364 | |
1365 | return 0; | |
c68876fd | 1366 | } |
6aa8b732 AK |
1367 | |
1368 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
1369 | { | |
1370 | int node = cpu_to_node(cpu); | |
1371 | struct page *pages; | |
1372 | struct vmcs *vmcs; | |
1373 | ||
6484eb3e | 1374 | pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
1375 | if (!pages) |
1376 | return NULL; | |
1377 | vmcs = page_address(pages); | |
1c3d14fe YS |
1378 | memset(vmcs, 0, vmcs_config.size); |
1379 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
1380 | return vmcs; |
1381 | } | |
1382 | ||
1383 | static struct vmcs *alloc_vmcs(void) | |
1384 | { | |
d3b2c338 | 1385 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
1386 | } |
1387 | ||
1388 | static void free_vmcs(struct vmcs *vmcs) | |
1389 | { | |
1c3d14fe | 1390 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
1391 | } |
1392 | ||
39959588 | 1393 | static void free_kvm_area(void) |
6aa8b732 AK |
1394 | { |
1395 | int cpu; | |
1396 | ||
3230bb47 | 1397 | for_each_possible_cpu(cpu) { |
6aa8b732 | 1398 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
1399 | per_cpu(vmxarea, cpu) = NULL; |
1400 | } | |
6aa8b732 AK |
1401 | } |
1402 | ||
6aa8b732 AK |
1403 | static __init int alloc_kvm_area(void) |
1404 | { | |
1405 | int cpu; | |
1406 | ||
3230bb47 | 1407 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
1408 | struct vmcs *vmcs; |
1409 | ||
1410 | vmcs = alloc_vmcs_cpu(cpu); | |
1411 | if (!vmcs) { | |
1412 | free_kvm_area(); | |
1413 | return -ENOMEM; | |
1414 | } | |
1415 | ||
1416 | per_cpu(vmxarea, cpu) = vmcs; | |
1417 | } | |
1418 | return 0; | |
1419 | } | |
1420 | ||
1421 | static __init int hardware_setup(void) | |
1422 | { | |
002c7f7c YS |
1423 | if (setup_vmcs_config(&vmcs_config) < 0) |
1424 | return -EIO; | |
50a37eb4 JR |
1425 | |
1426 | if (boot_cpu_has(X86_FEATURE_NX)) | |
1427 | kvm_enable_efer_bits(EFER_NX); | |
1428 | ||
93ba03c2 SY |
1429 | if (!cpu_has_vmx_vpid()) |
1430 | enable_vpid = 0; | |
1431 | ||
3a624e29 | 1432 | if (!cpu_has_vmx_ept()) { |
93ba03c2 | 1433 | enable_ept = 0; |
3a624e29 NK |
1434 | enable_unrestricted_guest = 0; |
1435 | } | |
1436 | ||
1437 | if (!cpu_has_vmx_unrestricted_guest()) | |
1438 | enable_unrestricted_guest = 0; | |
93ba03c2 SY |
1439 | |
1440 | if (!cpu_has_vmx_flexpriority()) | |
1441 | flexpriority_enabled = 0; | |
1442 | ||
95ba8273 GN |
1443 | if (!cpu_has_vmx_tpr_shadow()) |
1444 | kvm_x86_ops->update_cr8_intercept = NULL; | |
1445 | ||
54dee993 MT |
1446 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) |
1447 | kvm_disable_largepages(); | |
1448 | ||
4b8d54f9 ZE |
1449 | if (!cpu_has_vmx_ple()) |
1450 | ple_gap = 0; | |
1451 | ||
6aa8b732 AK |
1452 | return alloc_kvm_area(); |
1453 | } | |
1454 | ||
1455 | static __exit void hardware_unsetup(void) | |
1456 | { | |
1457 | free_kvm_area(); | |
1458 | } | |
1459 | ||
6aa8b732 AK |
1460 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
1461 | { | |
1462 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1463 | ||
6af11b9e | 1464 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
1465 | vmcs_write16(sf->selector, save->selector); |
1466 | vmcs_writel(sf->base, save->base); | |
1467 | vmcs_write32(sf->limit, save->limit); | |
1468 | vmcs_write32(sf->ar_bytes, save->ar); | |
1469 | } else { | |
1470 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
1471 | << AR_DPL_SHIFT; | |
1472 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1473 | } | |
1474 | } | |
1475 | ||
1476 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1477 | { | |
1478 | unsigned long flags; | |
a89a8fb9 | 1479 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 1480 | |
a89a8fb9 | 1481 | vmx->emulation_required = 1; |
7ffd92c5 | 1482 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 1483 | |
7ffd92c5 AK |
1484 | vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base); |
1485 | vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit); | |
1486 | vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar); | |
6aa8b732 AK |
1487 | |
1488 | flags = vmcs_readl(GUEST_RFLAGS); | |
053de044 | 1489 | flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM); |
7ffd92c5 | 1490 | flags |= (vmx->rmode.save_iopl << IOPL_SHIFT); |
6aa8b732 AK |
1491 | vmcs_writel(GUEST_RFLAGS, flags); |
1492 | ||
66aee91a RR |
1493 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
1494 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
1495 | |
1496 | update_exception_bitmap(vcpu); | |
1497 | ||
a89a8fb9 MG |
1498 | if (emulate_invalid_guest_state) |
1499 | return; | |
1500 | ||
7ffd92c5 AK |
1501 | fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es); |
1502 | fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds); | |
1503 | fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs); | |
1504 | fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs); | |
6aa8b732 AK |
1505 | |
1506 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1507 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1508 | ||
1509 | vmcs_write16(GUEST_CS_SELECTOR, | |
1510 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1511 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1512 | } | |
1513 | ||
d77c26fc | 1514 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 1515 | { |
bfc6d222 | 1516 | if (!kvm->arch.tss_addr) { |
bc6678a3 MT |
1517 | struct kvm_memslots *slots; |
1518 | gfn_t base_gfn; | |
1519 | ||
1520 | slots = rcu_dereference(kvm->memslots); | |
1521 | base_gfn = kvm->memslots->memslots[0].base_gfn + | |
46a26bf5 | 1522 | kvm->memslots->memslots[0].npages - 3; |
cbc94022 IE |
1523 | return base_gfn << PAGE_SHIFT; |
1524 | } | |
bfc6d222 | 1525 | return kvm->arch.tss_addr; |
6aa8b732 AK |
1526 | } |
1527 | ||
1528 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1529 | { | |
1530 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1531 | ||
1532 | save->selector = vmcs_read16(sf->selector); | |
1533 | save->base = vmcs_readl(sf->base); | |
1534 | save->limit = vmcs_read32(sf->limit); | |
1535 | save->ar = vmcs_read32(sf->ar_bytes); | |
15b00f32 JK |
1536 | vmcs_write16(sf->selector, save->base >> 4); |
1537 | vmcs_write32(sf->base, save->base & 0xfffff); | |
6aa8b732 AK |
1538 | vmcs_write32(sf->limit, 0xffff); |
1539 | vmcs_write32(sf->ar_bytes, 0xf3); | |
1540 | } | |
1541 | ||
1542 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1543 | { | |
1544 | unsigned long flags; | |
a89a8fb9 | 1545 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 1546 | |
3a624e29 NK |
1547 | if (enable_unrestricted_guest) |
1548 | return; | |
1549 | ||
a89a8fb9 | 1550 | vmx->emulation_required = 1; |
7ffd92c5 | 1551 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 1552 | |
7ffd92c5 | 1553 | vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
6aa8b732 AK |
1554 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
1555 | ||
7ffd92c5 | 1556 | vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
6aa8b732 AK |
1557 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
1558 | ||
7ffd92c5 | 1559 | vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
6aa8b732 AK |
1560 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
1561 | ||
1562 | flags = vmcs_readl(GUEST_RFLAGS); | |
7ffd92c5 | 1563 | vmx->rmode.save_iopl |
ad312c7c | 1564 | = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; |
6aa8b732 | 1565 | |
053de044 | 1566 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
1567 | |
1568 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 1569 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
1570 | update_exception_bitmap(vcpu); |
1571 | ||
a89a8fb9 MG |
1572 | if (emulate_invalid_guest_state) |
1573 | goto continue_rmode; | |
1574 | ||
6aa8b732 AK |
1575 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); |
1576 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1577 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1578 | ||
1579 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 1580 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
1581 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
1582 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
1583 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
1584 | ||
7ffd92c5 AK |
1585 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es); |
1586 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds); | |
1587 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs); | |
1588 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs); | |
75880a01 | 1589 | |
a89a8fb9 | 1590 | continue_rmode: |
8668a3c4 | 1591 | kvm_mmu_reset_context(vcpu); |
b7ebfb05 | 1592 | init_rmode(vcpu->kvm); |
6aa8b732 AK |
1593 | } |
1594 | ||
401d10de AS |
1595 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
1596 | { | |
1597 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
1598 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
1599 | ||
1600 | if (!msr) | |
1601 | return; | |
401d10de | 1602 | |
44ea2b17 AK |
1603 | /* |
1604 | * Force kernel_gs_base reloading before EFER changes, as control | |
1605 | * of this msr depends on is_long_mode(). | |
1606 | */ | |
1607 | vmx_load_host_state(to_vmx(vcpu)); | |
401d10de AS |
1608 | vcpu->arch.shadow_efer = efer; |
1609 | if (!msr) | |
1610 | return; | |
1611 | if (efer & EFER_LMA) { | |
1612 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1613 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1614 | VM_ENTRY_IA32E_MODE); | |
1615 | msr->data = efer; | |
1616 | } else { | |
1617 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1618 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1619 | ~VM_ENTRY_IA32E_MODE); | |
1620 | ||
1621 | msr->data = efer & ~EFER_LME; | |
1622 | } | |
1623 | setup_msrs(vmx); | |
1624 | } | |
1625 | ||
05b3e0c2 | 1626 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1627 | |
1628 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1629 | { | |
1630 | u32 guest_tr_ar; | |
1631 | ||
1632 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1633 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1634 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
b8688d51 | 1635 | __func__); |
6aa8b732 AK |
1636 | vmcs_write32(GUEST_TR_AR_BYTES, |
1637 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1638 | | AR_TYPE_BUSY_64_TSS); | |
1639 | } | |
ad312c7c | 1640 | vcpu->arch.shadow_efer |= EFER_LMA; |
401d10de | 1641 | vmx_set_efer(vcpu, vcpu->arch.shadow_efer); |
6aa8b732 AK |
1642 | } |
1643 | ||
1644 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1645 | { | |
ad312c7c | 1646 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
6aa8b732 AK |
1647 | |
1648 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1649 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1650 | & ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1651 | } |
1652 | ||
1653 | #endif | |
1654 | ||
2384d2b3 SY |
1655 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
1656 | { | |
1657 | vpid_sync_vcpu_all(to_vmx(vcpu)); | |
089d034e | 1658 | if (enable_ept) |
4e1096d2 | 1659 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
2384d2b3 SY |
1660 | } |
1661 | ||
e8467fda AK |
1662 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1663 | { | |
1664 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
1665 | ||
1666 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
1667 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
1668 | } | |
1669 | ||
25c4c276 | 1670 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 1671 | { |
fc78f519 AK |
1672 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
1673 | ||
1674 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
1675 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
1676 | } |
1677 | ||
1439442c SY |
1678 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
1679 | { | |
6de4f3ad AK |
1680 | if (!test_bit(VCPU_EXREG_PDPTR, |
1681 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
1682 | return; | |
1683 | ||
1439442c | 1684 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
1439442c SY |
1685 | vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]); |
1686 | vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]); | |
1687 | vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]); | |
1688 | vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]); | |
1689 | } | |
1690 | } | |
1691 | ||
8f5d549f AK |
1692 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
1693 | { | |
1694 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1695 | vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0); | |
1696 | vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
1697 | vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
1698 | vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
1699 | } | |
6de4f3ad AK |
1700 | |
1701 | __set_bit(VCPU_EXREG_PDPTR, | |
1702 | (unsigned long *)&vcpu->arch.regs_avail); | |
1703 | __set_bit(VCPU_EXREG_PDPTR, | |
1704 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
1705 | } |
1706 | ||
1439442c SY |
1707 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1708 | ||
1709 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
1710 | unsigned long cr0, | |
1711 | struct kvm_vcpu *vcpu) | |
1712 | { | |
1713 | if (!(cr0 & X86_CR0_PG)) { | |
1714 | /* From paging/starting to nonpaging */ | |
1715 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1716 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
1717 | (CPU_BASED_CR3_LOAD_EXITING | |
1718 | CPU_BASED_CR3_STORE_EXITING)); | |
1719 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 1720 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
1721 | } else if (!is_paging(vcpu)) { |
1722 | /* From nonpaging to paging */ | |
1723 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1724 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
1725 | ~(CPU_BASED_CR3_LOAD_EXITING | |
1726 | CPU_BASED_CR3_STORE_EXITING)); | |
1727 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 1728 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 1729 | } |
95eb84a7 SY |
1730 | |
1731 | if (!(cr0 & X86_CR0_WP)) | |
1732 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
1733 | } |
1734 | ||
6aa8b732 AK |
1735 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1736 | { | |
7ffd92c5 | 1737 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
1738 | unsigned long hw_cr0; |
1739 | ||
1740 | if (enable_unrestricted_guest) | |
1741 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST) | |
1742 | | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; | |
1743 | else | |
1744 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON; | |
1439442c | 1745 | |
7ffd92c5 | 1746 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1747 | enter_pmode(vcpu); |
1748 | ||
7ffd92c5 | 1749 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1750 | enter_rmode(vcpu); |
1751 | ||
05b3e0c2 | 1752 | #ifdef CONFIG_X86_64 |
ad312c7c | 1753 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 1754 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 1755 | enter_lmode(vcpu); |
707d92fa | 1756 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
1757 | exit_lmode(vcpu); |
1758 | } | |
1759 | #endif | |
1760 | ||
089d034e | 1761 | if (enable_ept) |
1439442c SY |
1762 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
1763 | ||
02daab21 AK |
1764 | if (!vcpu->fpu_active) |
1765 | hw_cr0 |= X86_CR0_TS; | |
1766 | ||
6aa8b732 | 1767 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 1768 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 1769 | vcpu->arch.cr0 = cr0; |
6aa8b732 AK |
1770 | } |
1771 | ||
1439442c SY |
1772 | static u64 construct_eptp(unsigned long root_hpa) |
1773 | { | |
1774 | u64 eptp; | |
1775 | ||
1776 | /* TODO write the value reading from MSR */ | |
1777 | eptp = VMX_EPT_DEFAULT_MT | | |
1778 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
1779 | eptp |= (root_hpa & PAGE_MASK); | |
1780 | ||
1781 | return eptp; | |
1782 | } | |
1783 | ||
6aa8b732 AK |
1784 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
1785 | { | |
1439442c SY |
1786 | unsigned long guest_cr3; |
1787 | u64 eptp; | |
1788 | ||
1789 | guest_cr3 = cr3; | |
089d034e | 1790 | if (enable_ept) { |
1439442c SY |
1791 | eptp = construct_eptp(cr3); |
1792 | vmcs_write64(EPT_POINTER, eptp); | |
1439442c | 1793 | guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 : |
b927a3ce | 1794 | vcpu->kvm->arch.ept_identity_map_addr; |
7c93be44 | 1795 | ept_load_pdptrs(vcpu); |
1439442c SY |
1796 | } |
1797 | ||
2384d2b3 | 1798 | vmx_flush_tlb(vcpu); |
1439442c | 1799 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
1800 | } |
1801 | ||
1802 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1803 | { | |
7ffd92c5 | 1804 | unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ? |
1439442c SY |
1805 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); |
1806 | ||
ad312c7c | 1807 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
1808 | if (enable_ept) { |
1809 | if (!is_paging(vcpu)) { | |
1810 | hw_cr4 &= ~X86_CR4_PAE; | |
1811 | hw_cr4 |= X86_CR4_PSE; | |
1812 | } else if (!(cr4 & X86_CR4_PAE)) { | |
1813 | hw_cr4 &= ~X86_CR4_PAE; | |
1814 | } | |
1815 | } | |
1439442c SY |
1816 | |
1817 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
1818 | vmcs_writel(GUEST_CR4, hw_cr4); | |
6aa8b732 AK |
1819 | } |
1820 | ||
6aa8b732 AK |
1821 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
1822 | { | |
1823 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1824 | ||
1825 | return vmcs_readl(sf->base); | |
1826 | } | |
1827 | ||
1828 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1829 | struct kvm_segment *var, int seg) | |
1830 | { | |
1831 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1832 | u32 ar; | |
1833 | ||
1834 | var->base = vmcs_readl(sf->base); | |
1835 | var->limit = vmcs_read32(sf->limit); | |
1836 | var->selector = vmcs_read16(sf->selector); | |
1837 | ar = vmcs_read32(sf->ar_bytes); | |
9fd4a3b7 | 1838 | if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state) |
6aa8b732 AK |
1839 | ar = 0; |
1840 | var->type = ar & 15; | |
1841 | var->s = (ar >> 4) & 1; | |
1842 | var->dpl = (ar >> 5) & 3; | |
1843 | var->present = (ar >> 7) & 1; | |
1844 | var->avl = (ar >> 12) & 1; | |
1845 | var->l = (ar >> 13) & 1; | |
1846 | var->db = (ar >> 14) & 1; | |
1847 | var->g = (ar >> 15) & 1; | |
1848 | var->unusable = (ar >> 16) & 1; | |
1849 | } | |
1850 | ||
2e4d2653 IE |
1851 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
1852 | { | |
4d4ec087 | 1853 | if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) /* if real mode */ |
2e4d2653 IE |
1854 | return 0; |
1855 | ||
1856 | if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */ | |
1857 | return 3; | |
1858 | ||
eab4b8aa | 1859 | return vmcs_read16(GUEST_CS_SELECTOR) & 3; |
2e4d2653 IE |
1860 | } |
1861 | ||
653e3108 | 1862 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 1863 | { |
6aa8b732 AK |
1864 | u32 ar; |
1865 | ||
653e3108 | 1866 | if (var->unusable) |
6aa8b732 AK |
1867 | ar = 1 << 16; |
1868 | else { | |
1869 | ar = var->type & 15; | |
1870 | ar |= (var->s & 1) << 4; | |
1871 | ar |= (var->dpl & 3) << 5; | |
1872 | ar |= (var->present & 1) << 7; | |
1873 | ar |= (var->avl & 1) << 12; | |
1874 | ar |= (var->l & 1) << 13; | |
1875 | ar |= (var->db & 1) << 14; | |
1876 | ar |= (var->g & 1) << 15; | |
1877 | } | |
f7fbf1fd UL |
1878 | if (ar == 0) /* a 0 value means unusable */ |
1879 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
1880 | |
1881 | return ar; | |
1882 | } | |
1883 | ||
1884 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
1885 | struct kvm_segment *var, int seg) | |
1886 | { | |
7ffd92c5 | 1887 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
653e3108 AK |
1888 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
1889 | u32 ar; | |
1890 | ||
7ffd92c5 AK |
1891 | if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) { |
1892 | vmx->rmode.tr.selector = var->selector; | |
1893 | vmx->rmode.tr.base = var->base; | |
1894 | vmx->rmode.tr.limit = var->limit; | |
1895 | vmx->rmode.tr.ar = vmx_segment_access_rights(var); | |
653e3108 AK |
1896 | return; |
1897 | } | |
1898 | vmcs_writel(sf->base, var->base); | |
1899 | vmcs_write32(sf->limit, var->limit); | |
1900 | vmcs_write16(sf->selector, var->selector); | |
7ffd92c5 | 1901 | if (vmx->rmode.vm86_active && var->s) { |
653e3108 AK |
1902 | /* |
1903 | * Hack real-mode segments into vm86 compatibility. | |
1904 | */ | |
1905 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
1906 | vmcs_writel(sf->base, 0xf0000); | |
1907 | ar = 0xf3; | |
1908 | } else | |
1909 | ar = vmx_segment_access_rights(var); | |
3a624e29 NK |
1910 | |
1911 | /* | |
1912 | * Fix the "Accessed" bit in AR field of segment registers for older | |
1913 | * qemu binaries. | |
1914 | * IA32 arch specifies that at the time of processor reset the | |
1915 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
1916 | * is setting it to 0 in the usedland code. This causes invalid guest | |
1917 | * state vmexit when "unrestricted guest" mode is turned on. | |
1918 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
1919 | * tree. Newer qemu binaries with that qemu fix would not need this | |
1920 | * kvm hack. | |
1921 | */ | |
1922 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
1923 | ar |= 0x1; /* Accessed */ | |
1924 | ||
6aa8b732 AK |
1925 | vmcs_write32(sf->ar_bytes, ar); |
1926 | } | |
1927 | ||
6aa8b732 AK |
1928 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
1929 | { | |
1930 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1931 | ||
1932 | *db = (ar >> 14) & 1; | |
1933 | *l = (ar >> 13) & 1; | |
1934 | } | |
1935 | ||
1936 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1937 | { | |
1938 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
1939 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
1940 | } | |
1941 | ||
1942 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1943 | { | |
1944 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
1945 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
1946 | } | |
1947 | ||
1948 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1949 | { | |
1950 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
1951 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
1952 | } | |
1953 | ||
1954 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1955 | { | |
1956 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
1957 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
1958 | } | |
1959 | ||
648dfaa7 MG |
1960 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
1961 | { | |
1962 | struct kvm_segment var; | |
1963 | u32 ar; | |
1964 | ||
1965 | vmx_get_segment(vcpu, &var, seg); | |
1966 | ar = vmx_segment_access_rights(&var); | |
1967 | ||
1968 | if (var.base != (var.selector << 4)) | |
1969 | return false; | |
1970 | if (var.limit != 0xffff) | |
1971 | return false; | |
1972 | if (ar != 0xf3) | |
1973 | return false; | |
1974 | ||
1975 | return true; | |
1976 | } | |
1977 | ||
1978 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
1979 | { | |
1980 | struct kvm_segment cs; | |
1981 | unsigned int cs_rpl; | |
1982 | ||
1983 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
1984 | cs_rpl = cs.selector & SELECTOR_RPL_MASK; | |
1985 | ||
1872a3f4 AK |
1986 | if (cs.unusable) |
1987 | return false; | |
648dfaa7 MG |
1988 | if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK)) |
1989 | return false; | |
1990 | if (!cs.s) | |
1991 | return false; | |
1872a3f4 | 1992 | if (cs.type & AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
1993 | if (cs.dpl > cs_rpl) |
1994 | return false; | |
1872a3f4 | 1995 | } else { |
648dfaa7 MG |
1996 | if (cs.dpl != cs_rpl) |
1997 | return false; | |
1998 | } | |
1999 | if (!cs.present) | |
2000 | return false; | |
2001 | ||
2002 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
2003 | return true; | |
2004 | } | |
2005 | ||
2006 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
2007 | { | |
2008 | struct kvm_segment ss; | |
2009 | unsigned int ss_rpl; | |
2010 | ||
2011 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
2012 | ss_rpl = ss.selector & SELECTOR_RPL_MASK; | |
2013 | ||
1872a3f4 AK |
2014 | if (ss.unusable) |
2015 | return true; | |
2016 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
2017 | return false; |
2018 | if (!ss.s) | |
2019 | return false; | |
2020 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
2021 | return false; | |
2022 | if (!ss.present) | |
2023 | return false; | |
2024 | ||
2025 | return true; | |
2026 | } | |
2027 | ||
2028 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
2029 | { | |
2030 | struct kvm_segment var; | |
2031 | unsigned int rpl; | |
2032 | ||
2033 | vmx_get_segment(vcpu, &var, seg); | |
2034 | rpl = var.selector & SELECTOR_RPL_MASK; | |
2035 | ||
1872a3f4 AK |
2036 | if (var.unusable) |
2037 | return true; | |
648dfaa7 MG |
2038 | if (!var.s) |
2039 | return false; | |
2040 | if (!var.present) | |
2041 | return false; | |
2042 | if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) { | |
2043 | if (var.dpl < rpl) /* DPL < RPL */ | |
2044 | return false; | |
2045 | } | |
2046 | ||
2047 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
2048 | * rights flags | |
2049 | */ | |
2050 | return true; | |
2051 | } | |
2052 | ||
2053 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
2054 | { | |
2055 | struct kvm_segment tr; | |
2056 | ||
2057 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
2058 | ||
1872a3f4 AK |
2059 | if (tr.unusable) |
2060 | return false; | |
648dfaa7 MG |
2061 | if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
2062 | return false; | |
1872a3f4 | 2063 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
2064 | return false; |
2065 | if (!tr.present) | |
2066 | return false; | |
2067 | ||
2068 | return true; | |
2069 | } | |
2070 | ||
2071 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
2072 | { | |
2073 | struct kvm_segment ldtr; | |
2074 | ||
2075 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
2076 | ||
1872a3f4 AK |
2077 | if (ldtr.unusable) |
2078 | return true; | |
648dfaa7 MG |
2079 | if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
2080 | return false; | |
2081 | if (ldtr.type != 2) | |
2082 | return false; | |
2083 | if (!ldtr.present) | |
2084 | return false; | |
2085 | ||
2086 | return true; | |
2087 | } | |
2088 | ||
2089 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
2090 | { | |
2091 | struct kvm_segment cs, ss; | |
2092 | ||
2093 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
2094 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
2095 | ||
2096 | return ((cs.selector & SELECTOR_RPL_MASK) == | |
2097 | (ss.selector & SELECTOR_RPL_MASK)); | |
2098 | } | |
2099 | ||
2100 | /* | |
2101 | * Check if guest state is valid. Returns true if valid, false if | |
2102 | * not. | |
2103 | * We assume that registers are always usable | |
2104 | */ | |
2105 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
2106 | { | |
2107 | /* real mode guest state checks */ | |
4d4ec087 | 2108 | if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) { |
648dfaa7 MG |
2109 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
2110 | return false; | |
2111 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
2112 | return false; | |
2113 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
2114 | return false; | |
2115 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
2116 | return false; | |
2117 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
2118 | return false; | |
2119 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
2120 | return false; | |
2121 | } else { | |
2122 | /* protected mode guest state checks */ | |
2123 | if (!cs_ss_rpl_check(vcpu)) | |
2124 | return false; | |
2125 | if (!code_segment_valid(vcpu)) | |
2126 | return false; | |
2127 | if (!stack_segment_valid(vcpu)) | |
2128 | return false; | |
2129 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
2130 | return false; | |
2131 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
2132 | return false; | |
2133 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
2134 | return false; | |
2135 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
2136 | return false; | |
2137 | if (!tr_valid(vcpu)) | |
2138 | return false; | |
2139 | if (!ldtr_valid(vcpu)) | |
2140 | return false; | |
2141 | } | |
2142 | /* TODO: | |
2143 | * - Add checks on RIP | |
2144 | * - Add checks on RFLAGS | |
2145 | */ | |
2146 | ||
2147 | return true; | |
2148 | } | |
2149 | ||
d77c26fc | 2150 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 2151 | { |
6aa8b732 | 2152 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; |
195aefde | 2153 | u16 data = 0; |
10589a46 | 2154 | int ret = 0; |
195aefde | 2155 | int r; |
6aa8b732 | 2156 | |
195aefde IE |
2157 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
2158 | if (r < 0) | |
10589a46 | 2159 | goto out; |
195aefde | 2160 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
2161 | r = kvm_write_guest_page(kvm, fn++, &data, |
2162 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 2163 | if (r < 0) |
10589a46 | 2164 | goto out; |
195aefde IE |
2165 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
2166 | if (r < 0) | |
10589a46 | 2167 | goto out; |
195aefde IE |
2168 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
2169 | if (r < 0) | |
10589a46 | 2170 | goto out; |
195aefde | 2171 | data = ~0; |
10589a46 MT |
2172 | r = kvm_write_guest_page(kvm, fn, &data, |
2173 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
2174 | sizeof(u8)); | |
195aefde | 2175 | if (r < 0) |
10589a46 MT |
2176 | goto out; |
2177 | ||
2178 | ret = 1; | |
2179 | out: | |
10589a46 | 2180 | return ret; |
6aa8b732 AK |
2181 | } |
2182 | ||
b7ebfb05 SY |
2183 | static int init_rmode_identity_map(struct kvm *kvm) |
2184 | { | |
2185 | int i, r, ret; | |
2186 | pfn_t identity_map_pfn; | |
2187 | u32 tmp; | |
2188 | ||
089d034e | 2189 | if (!enable_ept) |
b7ebfb05 SY |
2190 | return 1; |
2191 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { | |
2192 | printk(KERN_ERR "EPT: identity-mapping pagetable " | |
2193 | "haven't been allocated!\n"); | |
2194 | return 0; | |
2195 | } | |
2196 | if (likely(kvm->arch.ept_identity_pagetable_done)) | |
2197 | return 1; | |
2198 | ret = 0; | |
b927a3ce | 2199 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
b7ebfb05 SY |
2200 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
2201 | if (r < 0) | |
2202 | goto out; | |
2203 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
2204 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
2205 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
2206 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
2207 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
2208 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
2209 | if (r < 0) | |
2210 | goto out; | |
2211 | } | |
2212 | kvm->arch.ept_identity_pagetable_done = true; | |
2213 | ret = 1; | |
2214 | out: | |
2215 | return ret; | |
2216 | } | |
2217 | ||
6aa8b732 AK |
2218 | static void seg_setup(int seg) |
2219 | { | |
2220 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
3a624e29 | 2221 | unsigned int ar; |
6aa8b732 AK |
2222 | |
2223 | vmcs_write16(sf->selector, 0); | |
2224 | vmcs_writel(sf->base, 0); | |
2225 | vmcs_write32(sf->limit, 0xffff); | |
3a624e29 NK |
2226 | if (enable_unrestricted_guest) { |
2227 | ar = 0x93; | |
2228 | if (seg == VCPU_SREG_CS) | |
2229 | ar |= 0x08; /* code segment */ | |
2230 | } else | |
2231 | ar = 0xf3; | |
2232 | ||
2233 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
2234 | } |
2235 | ||
f78e0e2e SY |
2236 | static int alloc_apic_access_page(struct kvm *kvm) |
2237 | { | |
2238 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2239 | int r = 0; | |
2240 | ||
79fac95e | 2241 | mutex_lock(&kvm->slots_lock); |
bfc6d222 | 2242 | if (kvm->arch.apic_access_page) |
f78e0e2e SY |
2243 | goto out; |
2244 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
2245 | kvm_userspace_mem.flags = 0; | |
2246 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
2247 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
2248 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2249 | if (r) | |
2250 | goto out; | |
72dc67a6 | 2251 | |
bfc6d222 | 2252 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); |
f78e0e2e | 2253 | out: |
79fac95e | 2254 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
2255 | return r; |
2256 | } | |
2257 | ||
b7ebfb05 SY |
2258 | static int alloc_identity_pagetable(struct kvm *kvm) |
2259 | { | |
2260 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2261 | int r = 0; | |
2262 | ||
79fac95e | 2263 | mutex_lock(&kvm->slots_lock); |
b7ebfb05 SY |
2264 | if (kvm->arch.ept_identity_pagetable) |
2265 | goto out; | |
2266 | kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
2267 | kvm_userspace_mem.flags = 0; | |
b927a3ce SY |
2268 | kvm_userspace_mem.guest_phys_addr = |
2269 | kvm->arch.ept_identity_map_addr; | |
b7ebfb05 SY |
2270 | kvm_userspace_mem.memory_size = PAGE_SIZE; |
2271 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2272 | if (r) | |
2273 | goto out; | |
2274 | ||
b7ebfb05 | 2275 | kvm->arch.ept_identity_pagetable = gfn_to_page(kvm, |
b927a3ce | 2276 | kvm->arch.ept_identity_map_addr >> PAGE_SHIFT); |
b7ebfb05 | 2277 | out: |
79fac95e | 2278 | mutex_unlock(&kvm->slots_lock); |
b7ebfb05 SY |
2279 | return r; |
2280 | } | |
2281 | ||
2384d2b3 SY |
2282 | static void allocate_vpid(struct vcpu_vmx *vmx) |
2283 | { | |
2284 | int vpid; | |
2285 | ||
2286 | vmx->vpid = 0; | |
919818ab | 2287 | if (!enable_vpid) |
2384d2b3 SY |
2288 | return; |
2289 | spin_lock(&vmx_vpid_lock); | |
2290 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
2291 | if (vpid < VMX_NR_VPIDS) { | |
2292 | vmx->vpid = vpid; | |
2293 | __set_bit(vpid, vmx_vpid_bitmap); | |
2294 | } | |
2295 | spin_unlock(&vmx_vpid_lock); | |
2296 | } | |
2297 | ||
5897297b | 2298 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr) |
25c5f225 | 2299 | { |
3e7c73e9 | 2300 | int f = sizeof(unsigned long); |
25c5f225 SY |
2301 | |
2302 | if (!cpu_has_vmx_msr_bitmap()) | |
2303 | return; | |
2304 | ||
2305 | /* | |
2306 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
2307 | * have the write-low and read-high bitmap offsets the wrong way round. | |
2308 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
2309 | */ | |
25c5f225 | 2310 | if (msr <= 0x1fff) { |
3e7c73e9 AK |
2311 | __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */ |
2312 | __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */ | |
25c5f225 SY |
2313 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
2314 | msr &= 0x1fff; | |
3e7c73e9 AK |
2315 | __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */ |
2316 | __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */ | |
25c5f225 | 2317 | } |
25c5f225 SY |
2318 | } |
2319 | ||
5897297b AK |
2320 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
2321 | { | |
2322 | if (!longmode_only) | |
2323 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr); | |
2324 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr); | |
2325 | } | |
2326 | ||
6aa8b732 AK |
2327 | /* |
2328 | * Sets up the vmcs for emulated real mode. | |
2329 | */ | |
8b9cf98c | 2330 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 2331 | { |
468d472f | 2332 | u32 host_sysenter_cs, msr_low, msr_high; |
6aa8b732 | 2333 | u32 junk; |
53f658b3 | 2334 | u64 host_pat, tsc_this, tsc_base; |
6aa8b732 AK |
2335 | unsigned long a; |
2336 | struct descriptor_table dt; | |
2337 | int i; | |
cd2276a7 | 2338 | unsigned long kvm_vmx_return; |
6e5d865c | 2339 | u32 exec_control; |
6aa8b732 | 2340 | |
6aa8b732 | 2341 | /* I/O */ |
3e7c73e9 AK |
2342 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
2343 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 2344 | |
25c5f225 | 2345 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 2346 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 2347 | |
6aa8b732 AK |
2348 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
2349 | ||
6aa8b732 | 2350 | /* Control */ |
1c3d14fe YS |
2351 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
2352 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c YS |
2353 | |
2354 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
2355 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
2356 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
2357 | #ifdef CONFIG_X86_64 | |
2358 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
2359 | CPU_BASED_CR8_LOAD_EXITING; | |
2360 | #endif | |
2361 | } | |
089d034e | 2362 | if (!enable_ept) |
d56f546d | 2363 | exec_control |= CPU_BASED_CR3_STORE_EXITING | |
83dbc83a MT |
2364 | CPU_BASED_CR3_LOAD_EXITING | |
2365 | CPU_BASED_INVLPG_EXITING; | |
6e5d865c | 2366 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); |
6aa8b732 | 2367 | |
83ff3b9d SY |
2368 | if (cpu_has_secondary_exec_ctrls()) { |
2369 | exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
2370 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2371 | exec_control &= | |
2372 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
2384d2b3 SY |
2373 | if (vmx->vpid == 0) |
2374 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
046d8710 | 2375 | if (!enable_ept) { |
d56f546d | 2376 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; |
046d8710 SY |
2377 | enable_unrestricted_guest = 0; |
2378 | } | |
3a624e29 NK |
2379 | if (!enable_unrestricted_guest) |
2380 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
4b8d54f9 ZE |
2381 | if (!ple_gap) |
2382 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
83ff3b9d SY |
2383 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
2384 | } | |
f78e0e2e | 2385 | |
4b8d54f9 ZE |
2386 | if (ple_gap) { |
2387 | vmcs_write32(PLE_GAP, ple_gap); | |
2388 | vmcs_write32(PLE_WINDOW, ple_window); | |
2389 | } | |
2390 | ||
c7addb90 AK |
2391 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); |
2392 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
6aa8b732 AK |
2393 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
2394 | ||
2395 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
2396 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
2397 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
2398 | ||
2399 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
2400 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
2401 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
d6e88aec AK |
2402 | vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */ |
2403 | vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */ | |
6aa8b732 | 2404 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
05b3e0c2 | 2405 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2406 | rdmsrl(MSR_FS_BASE, a); |
2407 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
2408 | rdmsrl(MSR_GS_BASE, a); | |
2409 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
2410 | #else | |
2411 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
2412 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
2413 | #endif | |
2414 | ||
2415 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
2416 | ||
d6e88aec | 2417 | kvm_get_idt(&dt); |
6aa8b732 AK |
2418 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ |
2419 | ||
d77c26fc | 2420 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
cd2276a7 | 2421 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ |
2cc51560 ED |
2422 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
2423 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
2424 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); | |
6aa8b732 AK |
2425 | |
2426 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
2427 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
2428 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
2429 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
2430 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
2431 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
2432 | ||
468d472f SY |
2433 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { |
2434 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); | |
2435 | host_pat = msr_low | ((u64) msr_high << 32); | |
2436 | vmcs_write64(HOST_IA32_PAT, host_pat); | |
2437 | } | |
2438 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
2439 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); | |
2440 | host_pat = msr_low | ((u64) msr_high << 32); | |
2441 | /* Write the default value follow host pat */ | |
2442 | vmcs_write64(GUEST_IA32_PAT, host_pat); | |
2443 | /* Keep arch.pat sync with GUEST_IA32_PAT */ | |
2444 | vmx->vcpu.arch.pat = host_pat; | |
2445 | } | |
2446 | ||
6aa8b732 AK |
2447 | for (i = 0; i < NR_VMX_MSR; ++i) { |
2448 | u32 index = vmx_msr_index[i]; | |
2449 | u32 data_low, data_high; | |
a2fa3e9f | 2450 | int j = vmx->nmsrs; |
6aa8b732 AK |
2451 | |
2452 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
2453 | continue; | |
432bd6cb AK |
2454 | if (wrmsr_safe(index, data_low, data_high) < 0) |
2455 | continue; | |
26bb0981 AK |
2456 | vmx->guest_msrs[j].index = i; |
2457 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 2458 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 2459 | ++vmx->nmsrs; |
6aa8b732 | 2460 | } |
6aa8b732 | 2461 | |
1c3d14fe | 2462 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
2463 | |
2464 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
2465 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
2466 | ||
e00c8cf2 | 2467 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
4c38609a | 2468 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; |
ce03e4f2 AK |
2469 | if (enable_ept) |
2470 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
4c38609a | 2471 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
e00c8cf2 | 2472 | |
53f658b3 MT |
2473 | tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc; |
2474 | rdtscll(tsc_this); | |
2475 | if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc) | |
2476 | tsc_base = tsc_this; | |
2477 | ||
2478 | guest_write_tsc(0, tsc_base); | |
f78e0e2e | 2479 | |
e00c8cf2 AK |
2480 | return 0; |
2481 | } | |
2482 | ||
b7ebfb05 SY |
2483 | static int init_rmode(struct kvm *kvm) |
2484 | { | |
2485 | if (!init_rmode_tss(kvm)) | |
2486 | return 0; | |
2487 | if (!init_rmode_identity_map(kvm)) | |
2488 | return 0; | |
2489 | return 1; | |
2490 | } | |
2491 | ||
e00c8cf2 AK |
2492 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) |
2493 | { | |
2494 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2495 | u64 msr; | |
f656ce01 | 2496 | int ret, idx; |
e00c8cf2 | 2497 | |
5fdbf976 | 2498 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
f656ce01 | 2499 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
b7ebfb05 | 2500 | if (!init_rmode(vmx->vcpu.kvm)) { |
e00c8cf2 AK |
2501 | ret = -ENOMEM; |
2502 | goto out; | |
2503 | } | |
2504 | ||
7ffd92c5 | 2505 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 2506 | |
3b86cd99 JK |
2507 | vmx->soft_vnmi_blocked = 0; |
2508 | ||
ad312c7c | 2509 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 2510 | kvm_set_cr8(&vmx->vcpu, 0); |
e00c8cf2 | 2511 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 2512 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) |
e00c8cf2 AK |
2513 | msr |= MSR_IA32_APICBASE_BSP; |
2514 | kvm_set_apic_base(&vmx->vcpu, msr); | |
2515 | ||
2516 | fx_init(&vmx->vcpu); | |
2517 | ||
5706be0d | 2518 | seg_setup(VCPU_SREG_CS); |
e00c8cf2 AK |
2519 | /* |
2520 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
2521 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
2522 | */ | |
c5af89b6 | 2523 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) { |
e00c8cf2 AK |
2524 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
2525 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
2526 | } else { | |
ad312c7c ZX |
2527 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); |
2528 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
e00c8cf2 | 2529 | } |
e00c8cf2 AK |
2530 | |
2531 | seg_setup(VCPU_SREG_DS); | |
2532 | seg_setup(VCPU_SREG_ES); | |
2533 | seg_setup(VCPU_SREG_FS); | |
2534 | seg_setup(VCPU_SREG_GS); | |
2535 | seg_setup(VCPU_SREG_SS); | |
2536 | ||
2537 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
2538 | vmcs_writel(GUEST_TR_BASE, 0); | |
2539 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
2540 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
2541 | ||
2542 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
2543 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
2544 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
2545 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
2546 | ||
2547 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
2548 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
2549 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
2550 | ||
2551 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
c5af89b6 | 2552 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) |
5fdbf976 | 2553 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 2554 | else |
5fdbf976 MT |
2555 | kvm_rip_write(vcpu, 0); |
2556 | kvm_register_write(vcpu, VCPU_REGS_RSP, 0); | |
e00c8cf2 | 2557 | |
e00c8cf2 AK |
2558 | vmcs_writel(GUEST_DR7, 0x400); |
2559 | ||
2560 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
2561 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
2562 | ||
2563 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
2564 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
2565 | ||
2566 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
2567 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
2568 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
2569 | ||
e00c8cf2 AK |
2570 | /* Special registers */ |
2571 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
2572 | ||
2573 | setup_msrs(vmx); | |
2574 | ||
6aa8b732 AK |
2575 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
2576 | ||
f78e0e2e SY |
2577 | if (cpu_has_vmx_tpr_shadow()) { |
2578 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
2579 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
2580 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
ad312c7c | 2581 | page_to_phys(vmx->vcpu.arch.apic->regs_page)); |
f78e0e2e SY |
2582 | vmcs_write32(TPR_THRESHOLD, 0); |
2583 | } | |
2584 | ||
2585 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2586 | vmcs_write64(APIC_ACCESS_ADDR, | |
bfc6d222 | 2587 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); |
6aa8b732 | 2588 | |
2384d2b3 SY |
2589 | if (vmx->vpid != 0) |
2590 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
2591 | ||
fa40052c | 2592 | vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
4d4ec087 | 2593 | vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */ |
8b9cf98c | 2594 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 2595 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
2596 | vmx_fpu_activate(&vmx->vcpu); |
2597 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 2598 | |
2384d2b3 SY |
2599 | vpid_sync_vcpu_all(vmx); |
2600 | ||
3200f405 | 2601 | ret = 0; |
6aa8b732 | 2602 | |
a89a8fb9 MG |
2603 | /* HACK: Don't enable emulation on guest boot/reset */ |
2604 | vmx->emulation_required = 0; | |
2605 | ||
6aa8b732 | 2606 | out: |
f656ce01 | 2607 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
6aa8b732 AK |
2608 | return ret; |
2609 | } | |
2610 | ||
3b86cd99 JK |
2611 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
2612 | { | |
2613 | u32 cpu_based_vm_exec_control; | |
2614 | ||
2615 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2616 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
2617 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2618 | } | |
2619 | ||
2620 | static void enable_nmi_window(struct kvm_vcpu *vcpu) | |
2621 | { | |
2622 | u32 cpu_based_vm_exec_control; | |
2623 | ||
2624 | if (!cpu_has_virtual_nmis()) { | |
2625 | enable_irq_window(vcpu); | |
2626 | return; | |
2627 | } | |
2628 | ||
2629 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2630 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
2631 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2632 | } | |
2633 | ||
66fd3f7f | 2634 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 2635 | { |
9c8cba37 | 2636 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
2637 | uint32_t intr; |
2638 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 2639 | |
229456fc | 2640 | trace_kvm_inj_virq(irq); |
2714d1d3 | 2641 | |
fa89a817 | 2642 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 2643 | if (vmx->rmode.vm86_active) { |
9c8cba37 AK |
2644 | vmx->rmode.irq.pending = true; |
2645 | vmx->rmode.irq.vector = irq; | |
5fdbf976 | 2646 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); |
ae0bb3e0 GN |
2647 | if (vcpu->arch.interrupt.soft) |
2648 | vmx->rmode.irq.rip += | |
2649 | vmx->vcpu.arch.event_exit_inst_len; | |
9c5623e3 AK |
2650 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2651 | irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK); | |
2652 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
5fdbf976 | 2653 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); |
85f455f7 ED |
2654 | return; |
2655 | } | |
66fd3f7f GN |
2656 | intr = irq | INTR_INFO_VALID_MASK; |
2657 | if (vcpu->arch.interrupt.soft) { | |
2658 | intr |= INTR_TYPE_SOFT_INTR; | |
2659 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2660 | vmx->vcpu.arch.event_exit_inst_len); | |
2661 | } else | |
2662 | intr |= INTR_TYPE_EXT_INTR; | |
2663 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
2664 | } |
2665 | ||
f08864b4 SY |
2666 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
2667 | { | |
66a5a347 JK |
2668 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2669 | ||
3b86cd99 JK |
2670 | if (!cpu_has_virtual_nmis()) { |
2671 | /* | |
2672 | * Tracking the NMI-blocked state in software is built upon | |
2673 | * finding the next open IRQ window. This, in turn, depends on | |
2674 | * well-behaving guests: They have to keep IRQs disabled at | |
2675 | * least as long as the NMI handler runs. Otherwise we may | |
2676 | * cause NMI nesting, maybe breaking the guest. But as this is | |
2677 | * highly unlikely, we can live with the residual risk. | |
2678 | */ | |
2679 | vmx->soft_vnmi_blocked = 1; | |
2680 | vmx->vnmi_blocked_time = 0; | |
2681 | } | |
2682 | ||
487b391d | 2683 | ++vcpu->stat.nmi_injections; |
7ffd92c5 | 2684 | if (vmx->rmode.vm86_active) { |
66a5a347 JK |
2685 | vmx->rmode.irq.pending = true; |
2686 | vmx->rmode.irq.vector = NMI_VECTOR; | |
2687 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | |
2688 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2689 | NMI_VECTOR | INTR_TYPE_SOFT_INTR | | |
2690 | INTR_INFO_VALID_MASK); | |
2691 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
2692 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); | |
2693 | return; | |
2694 | } | |
f08864b4 SY |
2695 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2696 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
2697 | } |
2698 | ||
c4282df9 | 2699 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
33f089ca | 2700 | { |
3b86cd99 | 2701 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
c4282df9 | 2702 | return 0; |
33f089ca | 2703 | |
c4282df9 GN |
2704 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
2705 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS | | |
2706 | GUEST_INTR_STATE_NMI)); | |
33f089ca JK |
2707 | } |
2708 | ||
3cfc3092 JK |
2709 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
2710 | { | |
2711 | if (!cpu_has_virtual_nmis()) | |
2712 | return to_vmx(vcpu)->soft_vnmi_blocked; | |
2713 | else | |
2714 | return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
2715 | GUEST_INTR_STATE_NMI); | |
2716 | } | |
2717 | ||
2718 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
2719 | { | |
2720 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2721 | ||
2722 | if (!cpu_has_virtual_nmis()) { | |
2723 | if (vmx->soft_vnmi_blocked != masked) { | |
2724 | vmx->soft_vnmi_blocked = masked; | |
2725 | vmx->vnmi_blocked_time = 0; | |
2726 | } | |
2727 | } else { | |
2728 | if (masked) | |
2729 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
2730 | GUEST_INTR_STATE_NMI); | |
2731 | else | |
2732 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
2733 | GUEST_INTR_STATE_NMI); | |
2734 | } | |
2735 | } | |
2736 | ||
78646121 GN |
2737 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
2738 | { | |
c4282df9 GN |
2739 | return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && |
2740 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
2741 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
2742 | } |
2743 | ||
cbc94022 IE |
2744 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2745 | { | |
2746 | int ret; | |
2747 | struct kvm_userspace_memory_region tss_mem = { | |
6fe63979 | 2748 | .slot = TSS_PRIVATE_MEMSLOT, |
cbc94022 IE |
2749 | .guest_phys_addr = addr, |
2750 | .memory_size = PAGE_SIZE * 3, | |
2751 | .flags = 0, | |
2752 | }; | |
2753 | ||
2754 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
2755 | if (ret) | |
2756 | return ret; | |
bfc6d222 | 2757 | kvm->arch.tss_addr = addr; |
cbc94022 IE |
2758 | return 0; |
2759 | } | |
2760 | ||
6aa8b732 AK |
2761 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, |
2762 | int vec, u32 err_code) | |
2763 | { | |
b3f37707 NK |
2764 | /* |
2765 | * Instruction with address size override prefix opcode 0x67 | |
2766 | * Cause the #SS fault with 0 error code in VM86 mode. | |
2767 | */ | |
2768 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
851ba692 | 2769 | if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE) |
6aa8b732 | 2770 | return 1; |
77ab6db0 JK |
2771 | /* |
2772 | * Forward all other exceptions that are valid in real mode. | |
2773 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
2774 | * the required debugging infrastructure rework. | |
2775 | */ | |
2776 | switch (vec) { | |
77ab6db0 | 2777 | case DB_VECTOR: |
d0bfb940 JK |
2778 | if (vcpu->guest_debug & |
2779 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
2780 | return 0; | |
2781 | kvm_queue_exception(vcpu, vec); | |
2782 | return 1; | |
77ab6db0 | 2783 | case BP_VECTOR: |
d0bfb940 JK |
2784 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
2785 | return 0; | |
2786 | /* fall through */ | |
2787 | case DE_VECTOR: | |
77ab6db0 JK |
2788 | case OF_VECTOR: |
2789 | case BR_VECTOR: | |
2790 | case UD_VECTOR: | |
2791 | case DF_VECTOR: | |
2792 | case SS_VECTOR: | |
2793 | case GP_VECTOR: | |
2794 | case MF_VECTOR: | |
2795 | kvm_queue_exception(vcpu, vec); | |
2796 | return 1; | |
2797 | } | |
6aa8b732 AK |
2798 | return 0; |
2799 | } | |
2800 | ||
a0861c02 AK |
2801 | /* |
2802 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
2803 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
2804 | * We pass a fake environment to the machine check handler because we want | |
2805 | * the guest to be always treated like user space, no matter what context | |
2806 | * it used internally. | |
2807 | */ | |
2808 | static void kvm_machine_check(void) | |
2809 | { | |
2810 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
2811 | struct pt_regs regs = { | |
2812 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
2813 | .flags = X86_EFLAGS_IF, | |
2814 | }; | |
2815 | ||
2816 | do_machine_check(®s, 0); | |
2817 | #endif | |
2818 | } | |
2819 | ||
851ba692 | 2820 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
2821 | { |
2822 | /* already handled by vcpu_run */ | |
2823 | return 1; | |
2824 | } | |
2825 | ||
851ba692 | 2826 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 2827 | { |
1155f76a | 2828 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 2829 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 2830 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 2831 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
2832 | u32 vect_info; |
2833 | enum emulation_result er; | |
2834 | ||
1155f76a | 2835 | vect_info = vmx->idt_vectoring_info; |
6aa8b732 AK |
2836 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
2837 | ||
a0861c02 | 2838 | if (is_machine_check(intr_info)) |
851ba692 | 2839 | return handle_machine_check(vcpu); |
a0861c02 | 2840 | |
6aa8b732 | 2841 | if ((vect_info & VECTORING_INFO_VALID_MASK) && |
65ac7264 AK |
2842 | !is_page_fault(intr_info)) { |
2843 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2844 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
2845 | vcpu->run->internal.ndata = 2; | |
2846 | vcpu->run->internal.data[0] = vect_info; | |
2847 | vcpu->run->internal.data[1] = intr_info; | |
2848 | return 0; | |
2849 | } | |
6aa8b732 | 2850 | |
e4a41889 | 2851 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
1b6269db | 2852 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc AL |
2853 | |
2854 | if (is_no_device(intr_info)) { | |
5fd86fcf | 2855 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
2856 | return 1; |
2857 | } | |
2858 | ||
7aa81cc0 | 2859 | if (is_invalid_opcode(intr_info)) { |
851ba692 | 2860 | er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 2861 | if (er != EMULATE_DONE) |
7ee5d940 | 2862 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
2863 | return 1; |
2864 | } | |
2865 | ||
6aa8b732 | 2866 | error_code = 0; |
5fdbf976 | 2867 | rip = kvm_rip_read(vcpu); |
2e11384c | 2868 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 AK |
2869 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
2870 | if (is_page_fault(intr_info)) { | |
1439442c | 2871 | /* EPT won't cause page fault directly */ |
089d034e | 2872 | if (enable_ept) |
1439442c | 2873 | BUG(); |
6aa8b732 | 2874 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
229456fc MT |
2875 | trace_kvm_page_fault(cr2, error_code); |
2876 | ||
3298b75c | 2877 | if (kvm_event_needs_reinjection(vcpu)) |
577bdc49 | 2878 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
3067714c | 2879 | return kvm_mmu_page_fault(vcpu, cr2, error_code); |
6aa8b732 AK |
2880 | } |
2881 | ||
7ffd92c5 | 2882 | if (vmx->rmode.vm86_active && |
6aa8b732 | 2883 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
72d6e5a0 | 2884 | error_code)) { |
ad312c7c ZX |
2885 | if (vcpu->arch.halt_request) { |
2886 | vcpu->arch.halt_request = 0; | |
72d6e5a0 AK |
2887 | return kvm_emulate_halt(vcpu); |
2888 | } | |
6aa8b732 | 2889 | return 1; |
72d6e5a0 | 2890 | } |
6aa8b732 | 2891 | |
d0bfb940 | 2892 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
42dbaa5a JK |
2893 | switch (ex_no) { |
2894 | case DB_VECTOR: | |
2895 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
2896 | if (!(vcpu->guest_debug & | |
2897 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
2898 | vcpu->arch.dr6 = dr6 | DR6_FIXED_1; | |
2899 | kvm_queue_exception(vcpu, DB_VECTOR); | |
2900 | return 1; | |
2901 | } | |
2902 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
2903 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
2904 | /* fall through */ | |
2905 | case BP_VECTOR: | |
6aa8b732 | 2906 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
d0bfb940 JK |
2907 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
2908 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
2909 | break; |
2910 | default: | |
d0bfb940 JK |
2911 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
2912 | kvm_run->ex.exception = ex_no; | |
2913 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 2914 | break; |
6aa8b732 | 2915 | } |
6aa8b732 AK |
2916 | return 0; |
2917 | } | |
2918 | ||
851ba692 | 2919 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 2920 | { |
1165f5fe | 2921 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
2922 | return 1; |
2923 | } | |
2924 | ||
851ba692 | 2925 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 2926 | { |
851ba692 | 2927 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
988ad74f AK |
2928 | return 0; |
2929 | } | |
6aa8b732 | 2930 | |
851ba692 | 2931 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 2932 | { |
bfdaab09 | 2933 | unsigned long exit_qualification; |
34c33d16 | 2934 | int size, in, string; |
039576c0 | 2935 | unsigned port; |
6aa8b732 | 2936 | |
1165f5fe | 2937 | ++vcpu->stat.io_exits; |
bfdaab09 | 2938 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 2939 | string = (exit_qualification & 16) != 0; |
e70669ab LV |
2940 | |
2941 | if (string) { | |
851ba692 | 2942 | if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO) |
e70669ab LV |
2943 | return 0; |
2944 | return 1; | |
2945 | } | |
2946 | ||
2947 | size = (exit_qualification & 7) + 1; | |
2948 | in = (exit_qualification & 8) != 0; | |
039576c0 | 2949 | port = exit_qualification >> 16; |
e70669ab | 2950 | |
e93f36bc | 2951 | skip_emulated_instruction(vcpu); |
851ba692 | 2952 | return kvm_emulate_pio(vcpu, in, size, port); |
6aa8b732 AK |
2953 | } |
2954 | ||
102d8325 IM |
2955 | static void |
2956 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2957 | { | |
2958 | /* | |
2959 | * Patch in the VMCALL instruction: | |
2960 | */ | |
2961 | hypercall[0] = 0x0f; | |
2962 | hypercall[1] = 0x01; | |
2963 | hypercall[2] = 0xc1; | |
102d8325 IM |
2964 | } |
2965 | ||
851ba692 | 2966 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 2967 | { |
229456fc | 2968 | unsigned long exit_qualification, val; |
6aa8b732 AK |
2969 | int cr; |
2970 | int reg; | |
2971 | ||
bfdaab09 | 2972 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2973 | cr = exit_qualification & 15; |
2974 | reg = (exit_qualification >> 8) & 15; | |
2975 | switch ((exit_qualification >> 4) & 3) { | |
2976 | case 0: /* mov to cr */ | |
229456fc MT |
2977 | val = kvm_register_read(vcpu, reg); |
2978 | trace_kvm_cr_write(cr, val); | |
6aa8b732 AK |
2979 | switch (cr) { |
2980 | case 0: | |
229456fc | 2981 | kvm_set_cr0(vcpu, val); |
6aa8b732 AK |
2982 | skip_emulated_instruction(vcpu); |
2983 | return 1; | |
2984 | case 3: | |
229456fc | 2985 | kvm_set_cr3(vcpu, val); |
6aa8b732 AK |
2986 | skip_emulated_instruction(vcpu); |
2987 | return 1; | |
2988 | case 4: | |
229456fc | 2989 | kvm_set_cr4(vcpu, val); |
6aa8b732 AK |
2990 | skip_emulated_instruction(vcpu); |
2991 | return 1; | |
0a5fff19 GN |
2992 | case 8: { |
2993 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
2994 | u8 cr8 = kvm_register_read(vcpu, reg); | |
2995 | kvm_set_cr8(vcpu, cr8); | |
2996 | skip_emulated_instruction(vcpu); | |
2997 | if (irqchip_in_kernel(vcpu->kvm)) | |
2998 | return 1; | |
2999 | if (cr8_prev <= cr8) | |
3000 | return 1; | |
851ba692 | 3001 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
3002 | return 0; |
3003 | } | |
6aa8b732 AK |
3004 | }; |
3005 | break; | |
25c4c276 | 3006 | case 2: /* clts */ |
edcafe3c | 3007 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); |
4d4ec087 | 3008 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
25c4c276 AL |
3009 | skip_emulated_instruction(vcpu); |
3010 | return 1; | |
6aa8b732 AK |
3011 | case 1: /*mov from cr*/ |
3012 | switch (cr) { | |
3013 | case 3: | |
5fdbf976 | 3014 | kvm_register_write(vcpu, reg, vcpu->arch.cr3); |
229456fc | 3015 | trace_kvm_cr_read(cr, vcpu->arch.cr3); |
6aa8b732 AK |
3016 | skip_emulated_instruction(vcpu); |
3017 | return 1; | |
3018 | case 8: | |
229456fc MT |
3019 | val = kvm_get_cr8(vcpu); |
3020 | kvm_register_write(vcpu, reg, val); | |
3021 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
3022 | skip_emulated_instruction(vcpu); |
3023 | return 1; | |
3024 | } | |
3025 | break; | |
3026 | case 3: /* lmsw */ | |
a1f83a74 | 3027 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 3028 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 3029 | kvm_lmsw(vcpu, val); |
6aa8b732 AK |
3030 | |
3031 | skip_emulated_instruction(vcpu); | |
3032 | return 1; | |
3033 | default: | |
3034 | break; | |
3035 | } | |
851ba692 | 3036 | vcpu->run->exit_reason = 0; |
f0242478 | 3037 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
3038 | (int)(exit_qualification >> 4) & 3, cr); |
3039 | return 0; | |
3040 | } | |
3041 | ||
138ac8d8 JK |
3042 | static int check_dr_alias(struct kvm_vcpu *vcpu) |
3043 | { | |
3044 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) { | |
3045 | kvm_queue_exception(vcpu, UD_VECTOR); | |
3046 | return -1; | |
3047 | } | |
3048 | return 0; | |
3049 | } | |
3050 | ||
851ba692 | 3051 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3052 | { |
bfdaab09 | 3053 | unsigned long exit_qualification; |
6aa8b732 AK |
3054 | unsigned long val; |
3055 | int dr, reg; | |
3056 | ||
f2483415 | 3057 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
3058 | if (!kvm_require_cpl(vcpu, 0)) |
3059 | return 1; | |
42dbaa5a JK |
3060 | dr = vmcs_readl(GUEST_DR7); |
3061 | if (dr & DR7_GD) { | |
3062 | /* | |
3063 | * As the vm-exit takes precedence over the debug trap, we | |
3064 | * need to emulate the latter, either for the host or the | |
3065 | * guest debugging itself. | |
3066 | */ | |
3067 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 AK |
3068 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
3069 | vcpu->run->debug.arch.dr7 = dr; | |
3070 | vcpu->run->debug.arch.pc = | |
42dbaa5a JK |
3071 | vmcs_readl(GUEST_CS_BASE) + |
3072 | vmcs_readl(GUEST_RIP); | |
851ba692 AK |
3073 | vcpu->run->debug.arch.exception = DB_VECTOR; |
3074 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
3075 | return 0; |
3076 | } else { | |
3077 | vcpu->arch.dr7 &= ~DR7_GD; | |
3078 | vcpu->arch.dr6 |= DR6_BD; | |
3079 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
3080 | kvm_queue_exception(vcpu, DB_VECTOR); | |
3081 | return 1; | |
3082 | } | |
3083 | } | |
3084 | ||
bfdaab09 | 3085 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
42dbaa5a JK |
3086 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; |
3087 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); | |
3088 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
6aa8b732 | 3089 | switch (dr) { |
42dbaa5a JK |
3090 | case 0 ... 3: |
3091 | val = vcpu->arch.db[dr]; | |
3092 | break; | |
138ac8d8 JK |
3093 | case 4: |
3094 | if (check_dr_alias(vcpu) < 0) | |
3095 | return 1; | |
3096 | /* fall through */ | |
6aa8b732 | 3097 | case 6: |
42dbaa5a | 3098 | val = vcpu->arch.dr6; |
6aa8b732 | 3099 | break; |
138ac8d8 JK |
3100 | case 5: |
3101 | if (check_dr_alias(vcpu) < 0) | |
3102 | return 1; | |
3103 | /* fall through */ | |
3104 | default: /* 7 */ | |
42dbaa5a | 3105 | val = vcpu->arch.dr7; |
6aa8b732 | 3106 | break; |
6aa8b732 | 3107 | } |
5fdbf976 | 3108 | kvm_register_write(vcpu, reg, val); |
6aa8b732 | 3109 | } else { |
42dbaa5a JK |
3110 | val = vcpu->arch.regs[reg]; |
3111 | switch (dr) { | |
3112 | case 0 ... 3: | |
3113 | vcpu->arch.db[dr] = val; | |
3114 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
3115 | vcpu->arch.eff_db[dr] = val; | |
3116 | break; | |
138ac8d8 JK |
3117 | case 4: |
3118 | if (check_dr_alias(vcpu) < 0) | |
f2483415 | 3119 | return 1; |
138ac8d8 | 3120 | /* fall through */ |
42dbaa5a JK |
3121 | case 6: |
3122 | if (val & 0xffffffff00000000ULL) { | |
f2483415 JK |
3123 | kvm_inject_gp(vcpu, 0); |
3124 | return 1; | |
42dbaa5a JK |
3125 | } |
3126 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; | |
3127 | break; | |
138ac8d8 JK |
3128 | case 5: |
3129 | if (check_dr_alias(vcpu) < 0) | |
3130 | return 1; | |
3131 | /* fall through */ | |
3132 | default: /* 7 */ | |
42dbaa5a | 3133 | if (val & 0xffffffff00000000ULL) { |
f2483415 JK |
3134 | kvm_inject_gp(vcpu, 0); |
3135 | return 1; | |
42dbaa5a JK |
3136 | } |
3137 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; | |
3138 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
3139 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
3140 | vcpu->arch.switch_db_regs = | |
3141 | (val & DR7_BP_EN_MASK); | |
3142 | } | |
3143 | break; | |
3144 | } | |
6aa8b732 | 3145 | } |
6aa8b732 AK |
3146 | skip_emulated_instruction(vcpu); |
3147 | return 1; | |
3148 | } | |
3149 | ||
851ba692 | 3150 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 3151 | { |
06465c5a AK |
3152 | kvm_emulate_cpuid(vcpu); |
3153 | return 1; | |
6aa8b732 AK |
3154 | } |
3155 | ||
851ba692 | 3156 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3157 | { |
ad312c7c | 3158 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
3159 | u64 data; |
3160 | ||
3161 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
c1a5d4f9 | 3162 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
3163 | return 1; |
3164 | } | |
3165 | ||
229456fc | 3166 | trace_kvm_msr_read(ecx, data); |
2714d1d3 | 3167 | |
6aa8b732 | 3168 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
3169 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
3170 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
3171 | skip_emulated_instruction(vcpu); |
3172 | return 1; | |
3173 | } | |
3174 | ||
851ba692 | 3175 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3176 | { |
ad312c7c ZX |
3177 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
3178 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
3179 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 3180 | |
229456fc | 3181 | trace_kvm_msr_write(ecx, data); |
2714d1d3 | 3182 | |
6aa8b732 | 3183 | if (vmx_set_msr(vcpu, ecx, data) != 0) { |
c1a5d4f9 | 3184 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
3185 | return 1; |
3186 | } | |
3187 | ||
3188 | skip_emulated_instruction(vcpu); | |
3189 | return 1; | |
3190 | } | |
3191 | ||
851ba692 | 3192 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c YS |
3193 | { |
3194 | return 1; | |
3195 | } | |
3196 | ||
851ba692 | 3197 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3198 | { |
85f455f7 ED |
3199 | u32 cpu_based_vm_exec_control; |
3200 | ||
3201 | /* clear pending irq */ | |
3202 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3203 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
3204 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 | 3205 | |
a26bf12a | 3206 | ++vcpu->stat.irq_window_exits; |
2714d1d3 | 3207 | |
c1150d8c DL |
3208 | /* |
3209 | * If the user space waits to inject interrupts, exit as soon as | |
3210 | * possible | |
3211 | */ | |
8061823a | 3212 | if (!irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 3213 | vcpu->run->request_interrupt_window && |
8061823a | 3214 | !kvm_cpu_has_interrupt(vcpu)) { |
851ba692 | 3215 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
c1150d8c DL |
3216 | return 0; |
3217 | } | |
6aa8b732 AK |
3218 | return 1; |
3219 | } | |
3220 | ||
851ba692 | 3221 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
3222 | { |
3223 | skip_emulated_instruction(vcpu); | |
d3bef15f | 3224 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
3225 | } |
3226 | ||
851ba692 | 3227 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 3228 | { |
510043da | 3229 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
3230 | kvm_emulate_hypercall(vcpu); |
3231 | return 1; | |
c21415e8 IM |
3232 | } |
3233 | ||
851ba692 | 3234 | static int handle_vmx_insn(struct kvm_vcpu *vcpu) |
e3c7cb6a AK |
3235 | { |
3236 | kvm_queue_exception(vcpu, UD_VECTOR); | |
3237 | return 1; | |
3238 | } | |
3239 | ||
851ba692 | 3240 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 3241 | { |
f9c617f6 | 3242 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
3243 | |
3244 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
3245 | skip_emulated_instruction(vcpu); | |
3246 | return 1; | |
3247 | } | |
3248 | ||
851ba692 | 3249 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 ED |
3250 | { |
3251 | skip_emulated_instruction(vcpu); | |
3252 | /* TODO: Add support for VT-d/pass-through device */ | |
3253 | return 1; | |
3254 | } | |
3255 | ||
851ba692 | 3256 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 3257 | { |
f9c617f6 | 3258 | unsigned long exit_qualification; |
f78e0e2e SY |
3259 | enum emulation_result er; |
3260 | unsigned long offset; | |
3261 | ||
f9c617f6 | 3262 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
f78e0e2e SY |
3263 | offset = exit_qualification & 0xffful; |
3264 | ||
851ba692 | 3265 | er = emulate_instruction(vcpu, 0, 0, 0); |
f78e0e2e SY |
3266 | |
3267 | if (er != EMULATE_DONE) { | |
3268 | printk(KERN_ERR | |
3269 | "Fail to handle apic access vmexit! Offset is 0x%lx\n", | |
3270 | offset); | |
7f582ab6 | 3271 | return -ENOEXEC; |
f78e0e2e SY |
3272 | } |
3273 | return 1; | |
3274 | } | |
3275 | ||
851ba692 | 3276 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 3277 | { |
60637aac | 3278 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 IE |
3279 | unsigned long exit_qualification; |
3280 | u16 tss_selector; | |
64a7ec06 GN |
3281 | int reason, type, idt_v; |
3282 | ||
3283 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
3284 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); | |
37817f29 IE |
3285 | |
3286 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
3287 | ||
3288 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
3289 | if (reason == TASK_SWITCH_GATE && idt_v) { |
3290 | switch (type) { | |
3291 | case INTR_TYPE_NMI_INTR: | |
3292 | vcpu->arch.nmi_injected = false; | |
3293 | if (cpu_has_virtual_nmis()) | |
3294 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3295 | GUEST_INTR_STATE_NMI); | |
3296 | break; | |
3297 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 3298 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
3299 | kvm_clear_interrupt_queue(vcpu); |
3300 | break; | |
3301 | case INTR_TYPE_HARD_EXCEPTION: | |
3302 | case INTR_TYPE_SOFT_EXCEPTION: | |
3303 | kvm_clear_exception_queue(vcpu); | |
3304 | break; | |
3305 | default: | |
3306 | break; | |
3307 | } | |
60637aac | 3308 | } |
37817f29 IE |
3309 | tss_selector = exit_qualification; |
3310 | ||
64a7ec06 GN |
3311 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
3312 | type != INTR_TYPE_EXT_INTR && | |
3313 | type != INTR_TYPE_NMI_INTR)) | |
3314 | skip_emulated_instruction(vcpu); | |
3315 | ||
42dbaa5a JK |
3316 | if (!kvm_task_switch(vcpu, tss_selector, reason)) |
3317 | return 0; | |
3318 | ||
3319 | /* clear all local breakpoint enable flags */ | |
3320 | vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55); | |
3321 | ||
3322 | /* | |
3323 | * TODO: What about debug traps on tss switch? | |
3324 | * Are we supposed to inject them and update dr6? | |
3325 | */ | |
3326 | ||
3327 | return 1; | |
37817f29 IE |
3328 | } |
3329 | ||
851ba692 | 3330 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 3331 | { |
f9c617f6 | 3332 | unsigned long exit_qualification; |
1439442c | 3333 | gpa_t gpa; |
1439442c | 3334 | int gla_validity; |
1439442c | 3335 | |
f9c617f6 | 3336 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c SY |
3337 | |
3338 | if (exit_qualification & (1 << 6)) { | |
3339 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); | |
7f582ab6 | 3340 | return -EINVAL; |
1439442c SY |
3341 | } |
3342 | ||
3343 | gla_validity = (exit_qualification >> 7) & 0x3; | |
3344 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
3345 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
3346 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
3347 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
f9c617f6 | 3348 | vmcs_readl(GUEST_LINEAR_ADDRESS)); |
1439442c SY |
3349 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", |
3350 | (long unsigned int)exit_qualification); | |
851ba692 AK |
3351 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
3352 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION; | |
596ae895 | 3353 | return 0; |
1439442c SY |
3354 | } |
3355 | ||
3356 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
229456fc | 3357 | trace_kvm_page_fault(gpa, exit_qualification); |
49cd7d22 | 3358 | return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0); |
1439442c SY |
3359 | } |
3360 | ||
68f89400 MT |
3361 | static u64 ept_rsvd_mask(u64 spte, int level) |
3362 | { | |
3363 | int i; | |
3364 | u64 mask = 0; | |
3365 | ||
3366 | for (i = 51; i > boot_cpu_data.x86_phys_bits; i--) | |
3367 | mask |= (1ULL << i); | |
3368 | ||
3369 | if (level > 2) | |
3370 | /* bits 7:3 reserved */ | |
3371 | mask |= 0xf8; | |
3372 | else if (level == 2) { | |
3373 | if (spte & (1ULL << 7)) | |
3374 | /* 2MB ref, bits 20:12 reserved */ | |
3375 | mask |= 0x1ff000; | |
3376 | else | |
3377 | /* bits 6:3 reserved */ | |
3378 | mask |= 0x78; | |
3379 | } | |
3380 | ||
3381 | return mask; | |
3382 | } | |
3383 | ||
3384 | static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte, | |
3385 | int level) | |
3386 | { | |
3387 | printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level); | |
3388 | ||
3389 | /* 010b (write-only) */ | |
3390 | WARN_ON((spte & 0x7) == 0x2); | |
3391 | ||
3392 | /* 110b (write/execute) */ | |
3393 | WARN_ON((spte & 0x7) == 0x6); | |
3394 | ||
3395 | /* 100b (execute-only) and value not supported by logical processor */ | |
3396 | if (!cpu_has_vmx_ept_execute_only()) | |
3397 | WARN_ON((spte & 0x7) == 0x4); | |
3398 | ||
3399 | /* not 000b */ | |
3400 | if ((spte & 0x7)) { | |
3401 | u64 rsvd_bits = spte & ept_rsvd_mask(spte, level); | |
3402 | ||
3403 | if (rsvd_bits != 0) { | |
3404 | printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n", | |
3405 | __func__, rsvd_bits); | |
3406 | WARN_ON(1); | |
3407 | } | |
3408 | ||
3409 | if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) { | |
3410 | u64 ept_mem_type = (spte & 0x38) >> 3; | |
3411 | ||
3412 | if (ept_mem_type == 2 || ept_mem_type == 3 || | |
3413 | ept_mem_type == 7) { | |
3414 | printk(KERN_ERR "%s: ept_mem_type=0x%llx\n", | |
3415 | __func__, ept_mem_type); | |
3416 | WARN_ON(1); | |
3417 | } | |
3418 | } | |
3419 | } | |
3420 | } | |
3421 | ||
851ba692 | 3422 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 MT |
3423 | { |
3424 | u64 sptes[4]; | |
3425 | int nr_sptes, i; | |
3426 | gpa_t gpa; | |
3427 | ||
3428 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
3429 | ||
3430 | printk(KERN_ERR "EPT: Misconfiguration.\n"); | |
3431 | printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa); | |
3432 | ||
3433 | nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes); | |
3434 | ||
3435 | for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i) | |
3436 | ept_misconfig_inspect_spte(vcpu, sptes[i-1], i); | |
3437 | ||
851ba692 AK |
3438 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
3439 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
3440 | |
3441 | return 0; | |
3442 | } | |
3443 | ||
851ba692 | 3444 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 SY |
3445 | { |
3446 | u32 cpu_based_vm_exec_control; | |
3447 | ||
3448 | /* clear pending NMI */ | |
3449 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3450 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
3451 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
3452 | ++vcpu->stat.nmi_window_exits; | |
3453 | ||
3454 | return 1; | |
3455 | } | |
3456 | ||
80ced186 | 3457 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 3458 | { |
8b3079a5 AK |
3459 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3460 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 3461 | int ret = 1; |
ea953ef0 MG |
3462 | |
3463 | while (!guest_state_valid(vcpu)) { | |
851ba692 | 3464 | err = emulate_instruction(vcpu, 0, 0, 0); |
ea953ef0 | 3465 | |
80ced186 MG |
3466 | if (err == EMULATE_DO_MMIO) { |
3467 | ret = 0; | |
3468 | goto out; | |
3469 | } | |
1d5a4d9b GT |
3470 | |
3471 | if (err != EMULATE_DONE) { | |
80ced186 MG |
3472 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
3473 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
a9c7399d | 3474 | vcpu->run->internal.ndata = 0; |
80ced186 MG |
3475 | ret = 0; |
3476 | goto out; | |
ea953ef0 MG |
3477 | } |
3478 | ||
3479 | if (signal_pending(current)) | |
80ced186 | 3480 | goto out; |
ea953ef0 MG |
3481 | if (need_resched()) |
3482 | schedule(); | |
3483 | } | |
3484 | ||
80ced186 MG |
3485 | vmx->emulation_required = 0; |
3486 | out: | |
3487 | return ret; | |
ea953ef0 MG |
3488 | } |
3489 | ||
4b8d54f9 ZE |
3490 | /* |
3491 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
3492 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
3493 | */ | |
9fb41ba8 | 3494 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 ZE |
3495 | { |
3496 | skip_emulated_instruction(vcpu); | |
3497 | kvm_vcpu_on_spin(vcpu); | |
3498 | ||
3499 | return 1; | |
3500 | } | |
3501 | ||
59708670 SY |
3502 | static int handle_invalid_op(struct kvm_vcpu *vcpu) |
3503 | { | |
3504 | kvm_queue_exception(vcpu, UD_VECTOR); | |
3505 | return 1; | |
3506 | } | |
3507 | ||
6aa8b732 AK |
3508 | /* |
3509 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
3510 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
3511 | * to be done to userspace and return 0. | |
3512 | */ | |
851ba692 | 3513 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
3514 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
3515 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 3516 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 3517 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 3518 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
3519 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
3520 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
3521 | [EXIT_REASON_CPUID] = handle_cpuid, | |
3522 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
3523 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
3524 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
3525 | [EXIT_REASON_HLT] = handle_halt, | |
a7052897 | 3526 | [EXIT_REASON_INVLPG] = handle_invlpg, |
c21415e8 | 3527 | [EXIT_REASON_VMCALL] = handle_vmcall, |
e3c7cb6a AK |
3528 | [EXIT_REASON_VMCLEAR] = handle_vmx_insn, |
3529 | [EXIT_REASON_VMLAUNCH] = handle_vmx_insn, | |
3530 | [EXIT_REASON_VMPTRLD] = handle_vmx_insn, | |
3531 | [EXIT_REASON_VMPTRST] = handle_vmx_insn, | |
3532 | [EXIT_REASON_VMREAD] = handle_vmx_insn, | |
3533 | [EXIT_REASON_VMRESUME] = handle_vmx_insn, | |
3534 | [EXIT_REASON_VMWRITE] = handle_vmx_insn, | |
3535 | [EXIT_REASON_VMOFF] = handle_vmx_insn, | |
3536 | [EXIT_REASON_VMON] = handle_vmx_insn, | |
f78e0e2e SY |
3537 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
3538 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
e5edaa01 | 3539 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
37817f29 | 3540 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 3541 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
3542 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
3543 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 3544 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
59708670 SY |
3545 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op, |
3546 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op, | |
6aa8b732 AK |
3547 | }; |
3548 | ||
3549 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 3550 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 AK |
3551 | |
3552 | /* | |
3553 | * The guest has exited. See if we can fix it or if we need userspace | |
3554 | * assistance. | |
3555 | */ | |
851ba692 | 3556 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3557 | { |
29bd8a78 | 3558 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 3559 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 3560 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 3561 | |
229456fc | 3562 | trace_kvm_exit(exit_reason, kvm_rip_read(vcpu)); |
2714d1d3 | 3563 | |
80ced186 MG |
3564 | /* If guest state is invalid, start emulating */ |
3565 | if (vmx->emulation_required && emulate_invalid_guest_state) | |
3566 | return handle_invalid_guest_state(vcpu); | |
1d5a4d9b | 3567 | |
1439442c SY |
3568 | /* Access CR3 don't cause VMExit in paging mode, so we need |
3569 | * to sync with guest real CR3. */ | |
6de4f3ad | 3570 | if (enable_ept && is_paging(vcpu)) |
1439442c | 3571 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); |
1439442c | 3572 | |
29bd8a78 | 3573 | if (unlikely(vmx->fail)) { |
851ba692 AK |
3574 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
3575 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
3576 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
3577 | return 0; | |
3578 | } | |
6aa8b732 | 3579 | |
d77c26fc | 3580 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 3581 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac JK |
3582 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
3583 | exit_reason != EXIT_REASON_TASK_SWITCH)) | |
3584 | printk(KERN_WARNING "%s: unexpected, valid vectoring info " | |
3585 | "(0x%x) and exit reason is 0x%x\n", | |
3586 | __func__, vectoring_info, exit_reason); | |
3b86cd99 JK |
3587 | |
3588 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) { | |
c4282df9 | 3589 | if (vmx_interrupt_allowed(vcpu)) { |
3b86cd99 | 3590 | vmx->soft_vnmi_blocked = 0; |
3b86cd99 | 3591 | } else if (vmx->vnmi_blocked_time > 1000000000LL && |
4531220b | 3592 | vcpu->arch.nmi_pending) { |
3b86cd99 JK |
3593 | /* |
3594 | * This CPU don't support us in finding the end of an | |
3595 | * NMI-blocked window if the guest runs with IRQs | |
3596 | * disabled. So we pull the trigger after 1 s of | |
3597 | * futile waiting, but inform the user about this. | |
3598 | */ | |
3599 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
3600 | "state on VCPU %d after 1 s timeout\n", | |
3601 | __func__, vcpu->vcpu_id); | |
3602 | vmx->soft_vnmi_blocked = 0; | |
3b86cd99 | 3603 | } |
3b86cd99 JK |
3604 | } |
3605 | ||
6aa8b732 AK |
3606 | if (exit_reason < kvm_vmx_max_exit_handlers |
3607 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 3608 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 3609 | else { |
851ba692 AK |
3610 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
3611 | vcpu->run->hw.hardware_exit_reason = exit_reason; | |
6aa8b732 AK |
3612 | } |
3613 | return 0; | |
3614 | } | |
3615 | ||
95ba8273 | 3616 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 3617 | { |
95ba8273 | 3618 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
3619 | vmcs_write32(TPR_THRESHOLD, 0); |
3620 | return; | |
3621 | } | |
3622 | ||
95ba8273 | 3623 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
3624 | } |
3625 | ||
cf393f75 AK |
3626 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
3627 | { | |
3628 | u32 exit_intr_info; | |
7b4a25cb | 3629 | u32 idt_vectoring_info = vmx->idt_vectoring_info; |
cf393f75 AK |
3630 | bool unblock_nmi; |
3631 | u8 vector; | |
668f612f AK |
3632 | int type; |
3633 | bool idtv_info_valid; | |
cf393f75 AK |
3634 | |
3635 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
20f65983 | 3636 | |
a0861c02 AK |
3637 | vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); |
3638 | ||
3639 | /* Handle machine checks before interrupts are enabled */ | |
3640 | if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) | |
3641 | || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI | |
3642 | && is_machine_check(exit_intr_info))) | |
3643 | kvm_machine_check(); | |
3644 | ||
20f65983 GN |
3645 | /* We need to handle NMIs before interrupts are enabled */ |
3646 | if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && | |
229456fc | 3647 | (exit_intr_info & INTR_INFO_VALID_MASK)) |
20f65983 | 3648 | asm("int $2"); |
20f65983 GN |
3649 | |
3650 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
3651 | ||
cf393f75 AK |
3652 | if (cpu_has_virtual_nmis()) { |
3653 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
3654 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
3655 | /* | |
7b4a25cb | 3656 | * SDM 3: 27.7.1.2 (September 2008) |
cf393f75 AK |
3657 | * Re-set bit "block by NMI" before VM entry if vmexit caused by |
3658 | * a guest IRET fault. | |
7b4a25cb GN |
3659 | * SDM 3: 23.2.2 (September 2008) |
3660 | * Bit 12 is undefined in any of the following cases: | |
3661 | * If the VM exit sets the valid bit in the IDT-vectoring | |
3662 | * information field. | |
3663 | * If the VM exit is due to a double fault. | |
cf393f75 | 3664 | */ |
7b4a25cb GN |
3665 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && |
3666 | vector != DF_VECTOR && !idtv_info_valid) | |
cf393f75 AK |
3667 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, |
3668 | GUEST_INTR_STATE_NMI); | |
3b86cd99 JK |
3669 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
3670 | vmx->vnmi_blocked_time += | |
3671 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | |
668f612f | 3672 | |
37b96e98 GN |
3673 | vmx->vcpu.arch.nmi_injected = false; |
3674 | kvm_clear_exception_queue(&vmx->vcpu); | |
3675 | kvm_clear_interrupt_queue(&vmx->vcpu); | |
3676 | ||
3677 | if (!idtv_info_valid) | |
3678 | return; | |
3679 | ||
668f612f AK |
3680 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
3681 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 3682 | |
64a7ec06 | 3683 | switch (type) { |
37b96e98 GN |
3684 | case INTR_TYPE_NMI_INTR: |
3685 | vmx->vcpu.arch.nmi_injected = true; | |
668f612f | 3686 | /* |
7b4a25cb | 3687 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
3688 | * Clear bit "block by NMI" before VM entry if a NMI |
3689 | * delivery faulted. | |
668f612f | 3690 | */ |
37b96e98 GN |
3691 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, |
3692 | GUEST_INTR_STATE_NMI); | |
3693 | break; | |
37b96e98 | 3694 | case INTR_TYPE_SOFT_EXCEPTION: |
66fd3f7f GN |
3695 | vmx->vcpu.arch.event_exit_inst_len = |
3696 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
3697 | /* fall through */ | |
3698 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 3699 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
37b96e98 GN |
3700 | u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE); |
3701 | kvm_queue_exception_e(&vmx->vcpu, vector, err); | |
35920a35 AK |
3702 | } else |
3703 | kvm_queue_exception(&vmx->vcpu, vector); | |
37b96e98 | 3704 | break; |
66fd3f7f GN |
3705 | case INTR_TYPE_SOFT_INTR: |
3706 | vmx->vcpu.arch.event_exit_inst_len = | |
3707 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
3708 | /* fall through */ | |
37b96e98 | 3709 | case INTR_TYPE_EXT_INTR: |
66fd3f7f GN |
3710 | kvm_queue_interrupt(&vmx->vcpu, vector, |
3711 | type == INTR_TYPE_SOFT_INTR); | |
37b96e98 GN |
3712 | break; |
3713 | default: | |
3714 | break; | |
f7d9238f | 3715 | } |
cf393f75 AK |
3716 | } |
3717 | ||
9c8cba37 AK |
3718 | /* |
3719 | * Failure to inject an interrupt should give us the information | |
3720 | * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs | |
3721 | * when fetching the interrupt redirection bitmap in the real-mode | |
3722 | * tss, this doesn't happen. So we do it ourselves. | |
3723 | */ | |
3724 | static void fixup_rmode_irq(struct vcpu_vmx *vmx) | |
3725 | { | |
3726 | vmx->rmode.irq.pending = 0; | |
5fdbf976 | 3727 | if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip) |
9c8cba37 | 3728 | return; |
5fdbf976 | 3729 | kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip); |
9c8cba37 AK |
3730 | if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) { |
3731 | vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK; | |
3732 | vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR; | |
3733 | return; | |
3734 | } | |
3735 | vmx->idt_vectoring_info = | |
3736 | VECTORING_INFO_VALID_MASK | |
3737 | | INTR_TYPE_EXT_INTR | |
3738 | | vmx->rmode.irq.vector; | |
3739 | } | |
3740 | ||
c801949d AK |
3741 | #ifdef CONFIG_X86_64 |
3742 | #define R "r" | |
3743 | #define Q "q" | |
3744 | #else | |
3745 | #define R "e" | |
3746 | #define Q "l" | |
3747 | #endif | |
3748 | ||
851ba692 | 3749 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3750 | { |
a2fa3e9f | 3751 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
e6adf283 | 3752 | |
3b86cd99 JK |
3753 | /* Record the guest's net vcpu time for enforced NMI injections. */ |
3754 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | |
3755 | vmx->entry_time = ktime_get(); | |
3756 | ||
80ced186 MG |
3757 | /* Don't enter VMX if guest state is invalid, let the exit handler |
3758 | start emulation until we arrive back to a valid state */ | |
3759 | if (vmx->emulation_required && emulate_invalid_guest_state) | |
a89a8fb9 | 3760 | return; |
a89a8fb9 | 3761 | |
5fdbf976 MT |
3762 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
3763 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
3764 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
3765 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
3766 | ||
787ff736 GN |
3767 | /* When single-stepping over STI and MOV SS, we must clear the |
3768 | * corresponding interruptibility bits in the guest state. Otherwise | |
3769 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
3770 | * exceptions being set, but that's not correct for the guest debugging | |
3771 | * case. */ | |
3772 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
3773 | vmx_set_interrupt_shadow(vcpu, 0); | |
3774 | ||
e6adf283 AK |
3775 | /* |
3776 | * Loading guest fpu may have cleared host cr0.ts | |
3777 | */ | |
3778 | vmcs_writel(HOST_CR0, read_cr0()); | |
3779 | ||
e8a48342 AK |
3780 | if (vcpu->arch.switch_db_regs) |
3781 | set_debugreg(vcpu->arch.dr6, 6); | |
42dbaa5a | 3782 | |
d77c26fc | 3783 | asm( |
6aa8b732 | 3784 | /* Store host registers */ |
c801949d AK |
3785 | "push %%"R"dx; push %%"R"bp;" |
3786 | "push %%"R"cx \n\t" | |
313dbd49 AK |
3787 | "cmp %%"R"sp, %c[host_rsp](%0) \n\t" |
3788 | "je 1f \n\t" | |
3789 | "mov %%"R"sp, %c[host_rsp](%0) \n\t" | |
4ecac3fd | 3790 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 3791 | "1: \n\t" |
d3edefc0 AK |
3792 | /* Reload cr2 if changed */ |
3793 | "mov %c[cr2](%0), %%"R"ax \n\t" | |
3794 | "mov %%cr2, %%"R"dx \n\t" | |
3795 | "cmp %%"R"ax, %%"R"dx \n\t" | |
3796 | "je 2f \n\t" | |
3797 | "mov %%"R"ax, %%cr2 \n\t" | |
3798 | "2: \n\t" | |
6aa8b732 | 3799 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 3800 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 3801 | /* Load guest registers. Don't clobber flags. */ |
c801949d AK |
3802 | "mov %c[rax](%0), %%"R"ax \n\t" |
3803 | "mov %c[rbx](%0), %%"R"bx \n\t" | |
3804 | "mov %c[rdx](%0), %%"R"dx \n\t" | |
3805 | "mov %c[rsi](%0), %%"R"si \n\t" | |
3806 | "mov %c[rdi](%0), %%"R"di \n\t" | |
3807 | "mov %c[rbp](%0), %%"R"bp \n\t" | |
05b3e0c2 | 3808 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
3809 | "mov %c[r8](%0), %%r8 \n\t" |
3810 | "mov %c[r9](%0), %%r9 \n\t" | |
3811 | "mov %c[r10](%0), %%r10 \n\t" | |
3812 | "mov %c[r11](%0), %%r11 \n\t" | |
3813 | "mov %c[r12](%0), %%r12 \n\t" | |
3814 | "mov %c[r13](%0), %%r13 \n\t" | |
3815 | "mov %c[r14](%0), %%r14 \n\t" | |
3816 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 3817 | #endif |
c801949d AK |
3818 | "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */ |
3819 | ||
6aa8b732 | 3820 | /* Enter guest mode */ |
cd2276a7 | 3821 | "jne .Llaunched \n\t" |
4ecac3fd | 3822 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
cd2276a7 | 3823 | "jmp .Lkvm_vmx_return \n\t" |
4ecac3fd | 3824 | ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t" |
cd2276a7 | 3825 | ".Lkvm_vmx_return: " |
6aa8b732 | 3826 | /* Save guest registers, load host registers, keep flags */ |
c801949d AK |
3827 | "xchg %0, (%%"R"sp) \n\t" |
3828 | "mov %%"R"ax, %c[rax](%0) \n\t" | |
3829 | "mov %%"R"bx, %c[rbx](%0) \n\t" | |
3830 | "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t" | |
3831 | "mov %%"R"dx, %c[rdx](%0) \n\t" | |
3832 | "mov %%"R"si, %c[rsi](%0) \n\t" | |
3833 | "mov %%"R"di, %c[rdi](%0) \n\t" | |
3834 | "mov %%"R"bp, %c[rbp](%0) \n\t" | |
05b3e0c2 | 3835 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
3836 | "mov %%r8, %c[r8](%0) \n\t" |
3837 | "mov %%r9, %c[r9](%0) \n\t" | |
3838 | "mov %%r10, %c[r10](%0) \n\t" | |
3839 | "mov %%r11, %c[r11](%0) \n\t" | |
3840 | "mov %%r12, %c[r12](%0) \n\t" | |
3841 | "mov %%r13, %c[r13](%0) \n\t" | |
3842 | "mov %%r14, %c[r14](%0) \n\t" | |
3843 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 3844 | #endif |
c801949d AK |
3845 | "mov %%cr2, %%"R"ax \n\t" |
3846 | "mov %%"R"ax, %c[cr2](%0) \n\t" | |
3847 | ||
3848 | "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t" | |
e08aa78a AK |
3849 | "setbe %c[fail](%0) \n\t" |
3850 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
3851 | [launched]"i"(offsetof(struct vcpu_vmx, launched)), | |
3852 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), | |
313dbd49 | 3853 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
3854 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
3855 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
3856 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3857 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3858 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3859 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3860 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 3861 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3862 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
3863 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
3864 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
3865 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
3866 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
3867 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
3868 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
3869 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 3870 | #endif |
ad312c7c | 3871 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)) |
c2036300 | 3872 | : "cc", "memory" |
c801949d | 3873 | , R"bx", R"di", R"si" |
c2036300 | 3874 | #ifdef CONFIG_X86_64 |
c2036300 LV |
3875 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
3876 | #endif | |
3877 | ); | |
6aa8b732 | 3878 | |
6de4f3ad AK |
3879 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
3880 | | (1 << VCPU_EXREG_PDPTR)); | |
5fdbf976 MT |
3881 | vcpu->arch.regs_dirty = 0; |
3882 | ||
e8a48342 AK |
3883 | if (vcpu->arch.switch_db_regs) |
3884 | get_debugreg(vcpu->arch.dr6, 6); | |
42dbaa5a | 3885 | |
1155f76a | 3886 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
9c8cba37 AK |
3887 | if (vmx->rmode.irq.pending) |
3888 | fixup_rmode_irq(vmx); | |
1155f76a | 3889 | |
d77c26fc | 3890 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
15ad7146 | 3891 | vmx->launched = 1; |
1b6269db | 3892 | |
cf393f75 | 3893 | vmx_complete_interrupts(vmx); |
6aa8b732 AK |
3894 | } |
3895 | ||
c801949d AK |
3896 | #undef R |
3897 | #undef Q | |
3898 | ||
6aa8b732 AK |
3899 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) |
3900 | { | |
a2fa3e9f GH |
3901 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3902 | ||
3903 | if (vmx->vmcs) { | |
543e4243 | 3904 | vcpu_clear(vmx); |
a2fa3e9f GH |
3905 | free_vmcs(vmx->vmcs); |
3906 | vmx->vmcs = NULL; | |
6aa8b732 AK |
3907 | } |
3908 | } | |
3909 | ||
3910 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
3911 | { | |
fb3f0f51 RR |
3912 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3913 | ||
2384d2b3 SY |
3914 | spin_lock(&vmx_vpid_lock); |
3915 | if (vmx->vpid != 0) | |
3916 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
3917 | spin_unlock(&vmx_vpid_lock); | |
6aa8b732 | 3918 | vmx_free_vmcs(vcpu); |
fb3f0f51 RR |
3919 | kfree(vmx->guest_msrs); |
3920 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 3921 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
3922 | } |
3923 | ||
fb3f0f51 | 3924 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 3925 | { |
fb3f0f51 | 3926 | int err; |
c16f862d | 3927 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 3928 | int cpu; |
6aa8b732 | 3929 | |
a2fa3e9f | 3930 | if (!vmx) |
fb3f0f51 RR |
3931 | return ERR_PTR(-ENOMEM); |
3932 | ||
2384d2b3 SY |
3933 | allocate_vpid(vmx); |
3934 | ||
fb3f0f51 RR |
3935 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
3936 | if (err) | |
3937 | goto free_vcpu; | |
965b58a5 | 3938 | |
a2fa3e9f | 3939 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
fb3f0f51 RR |
3940 | if (!vmx->guest_msrs) { |
3941 | err = -ENOMEM; | |
3942 | goto uninit_vcpu; | |
3943 | } | |
965b58a5 | 3944 | |
a2fa3e9f GH |
3945 | vmx->vmcs = alloc_vmcs(); |
3946 | if (!vmx->vmcs) | |
fb3f0f51 | 3947 | goto free_msrs; |
a2fa3e9f GH |
3948 | |
3949 | vmcs_clear(vmx->vmcs); | |
3950 | ||
15ad7146 AK |
3951 | cpu = get_cpu(); |
3952 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
8b9cf98c | 3953 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 3954 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 3955 | put_cpu(); |
fb3f0f51 RR |
3956 | if (err) |
3957 | goto free_vmcs; | |
5e4a0b3c MT |
3958 | if (vm_need_virtualize_apic_accesses(kvm)) |
3959 | if (alloc_apic_access_page(kvm) != 0) | |
3960 | goto free_vmcs; | |
fb3f0f51 | 3961 | |
b927a3ce SY |
3962 | if (enable_ept) { |
3963 | if (!kvm->arch.ept_identity_map_addr) | |
3964 | kvm->arch.ept_identity_map_addr = | |
3965 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
b7ebfb05 SY |
3966 | if (alloc_identity_pagetable(kvm) != 0) |
3967 | goto free_vmcs; | |
b927a3ce | 3968 | } |
b7ebfb05 | 3969 | |
fb3f0f51 RR |
3970 | return &vmx->vcpu; |
3971 | ||
3972 | free_vmcs: | |
3973 | free_vmcs(vmx->vmcs); | |
3974 | free_msrs: | |
fb3f0f51 RR |
3975 | kfree(vmx->guest_msrs); |
3976 | uninit_vcpu: | |
3977 | kvm_vcpu_uninit(&vmx->vcpu); | |
3978 | free_vcpu: | |
a4770347 | 3979 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 3980 | return ERR_PTR(err); |
6aa8b732 AK |
3981 | } |
3982 | ||
002c7f7c YS |
3983 | static void __init vmx_check_processor_compat(void *rtn) |
3984 | { | |
3985 | struct vmcs_config vmcs_conf; | |
3986 | ||
3987 | *(int *)rtn = 0; | |
3988 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
3989 | *(int *)rtn = -EIO; | |
3990 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
3991 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
3992 | smp_processor_id()); | |
3993 | *(int *)rtn = -EIO; | |
3994 | } | |
3995 | } | |
3996 | ||
67253af5 SY |
3997 | static int get_ept_level(void) |
3998 | { | |
3999 | return VMX_EPT_DEFAULT_GAW + 1; | |
4000 | } | |
4001 | ||
4b12f0de | 4002 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 4003 | { |
4b12f0de SY |
4004 | u64 ret; |
4005 | ||
522c68c4 SY |
4006 | /* For VT-d and EPT combination |
4007 | * 1. MMIO: always map as UC | |
4008 | * 2. EPT with VT-d: | |
4009 | * a. VT-d without snooping control feature: can't guarantee the | |
4010 | * result, try to trust guest. | |
4011 | * b. VT-d with snooping control feature: snooping control feature of | |
4012 | * VT-d engine can guarantee the cache correctness. Just set it | |
4013 | * to WB to keep consistent with host. So the same as item 3. | |
4014 | * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep | |
4015 | * consistent with host MTRR | |
4016 | */ | |
4b12f0de SY |
4017 | if (is_mmio) |
4018 | ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT; | |
522c68c4 SY |
4019 | else if (vcpu->kvm->arch.iommu_domain && |
4020 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY)) | |
4021 | ret = kvm_get_guest_memory_type(vcpu, gfn) << | |
4022 | VMX_EPT_MT_EPTE_SHIFT; | |
4b12f0de | 4023 | else |
522c68c4 SY |
4024 | ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) |
4025 | | VMX_EPT_IGMT_BIT; | |
4b12f0de SY |
4026 | |
4027 | return ret; | |
64d4d521 SY |
4028 | } |
4029 | ||
f4c9e87c AK |
4030 | #define _ER(x) { EXIT_REASON_##x, #x } |
4031 | ||
229456fc | 4032 | static const struct trace_print_flags vmx_exit_reasons_str[] = { |
f4c9e87c AK |
4033 | _ER(EXCEPTION_NMI), |
4034 | _ER(EXTERNAL_INTERRUPT), | |
4035 | _ER(TRIPLE_FAULT), | |
4036 | _ER(PENDING_INTERRUPT), | |
4037 | _ER(NMI_WINDOW), | |
4038 | _ER(TASK_SWITCH), | |
4039 | _ER(CPUID), | |
4040 | _ER(HLT), | |
4041 | _ER(INVLPG), | |
4042 | _ER(RDPMC), | |
4043 | _ER(RDTSC), | |
4044 | _ER(VMCALL), | |
4045 | _ER(VMCLEAR), | |
4046 | _ER(VMLAUNCH), | |
4047 | _ER(VMPTRLD), | |
4048 | _ER(VMPTRST), | |
4049 | _ER(VMREAD), | |
4050 | _ER(VMRESUME), | |
4051 | _ER(VMWRITE), | |
4052 | _ER(VMOFF), | |
4053 | _ER(VMON), | |
4054 | _ER(CR_ACCESS), | |
4055 | _ER(DR_ACCESS), | |
4056 | _ER(IO_INSTRUCTION), | |
4057 | _ER(MSR_READ), | |
4058 | _ER(MSR_WRITE), | |
4059 | _ER(MWAIT_INSTRUCTION), | |
4060 | _ER(MONITOR_INSTRUCTION), | |
4061 | _ER(PAUSE_INSTRUCTION), | |
4062 | _ER(MCE_DURING_VMENTRY), | |
4063 | _ER(TPR_BELOW_THRESHOLD), | |
4064 | _ER(APIC_ACCESS), | |
4065 | _ER(EPT_VIOLATION), | |
4066 | _ER(EPT_MISCONFIG), | |
4067 | _ER(WBINVD), | |
229456fc MT |
4068 | { -1, NULL } |
4069 | }; | |
4070 | ||
f4c9e87c AK |
4071 | #undef _ER |
4072 | ||
17cc3935 | 4073 | static int vmx_get_lpage_level(void) |
344f414f | 4074 | { |
878403b7 SY |
4075 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
4076 | return PT_DIRECTORY_LEVEL; | |
4077 | else | |
4078 | /* For shadow and EPT supported 1GB page */ | |
4079 | return PT_PDPE_LEVEL; | |
344f414f JR |
4080 | } |
4081 | ||
4e47c7a6 SY |
4082 | static inline u32 bit(int bitno) |
4083 | { | |
4084 | return 1 << (bitno & 31); | |
4085 | } | |
4086 | ||
0e851880 SY |
4087 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
4088 | { | |
4e47c7a6 SY |
4089 | struct kvm_cpuid_entry2 *best; |
4090 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4091 | u32 exec_control; | |
4092 | ||
4093 | vmx->rdtscp_enabled = false; | |
4094 | if (vmx_rdtscp_supported()) { | |
4095 | exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
4096 | if (exec_control & SECONDARY_EXEC_RDTSCP) { | |
4097 | best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
4098 | if (best && (best->edx & bit(X86_FEATURE_RDTSCP))) | |
4099 | vmx->rdtscp_enabled = true; | |
4100 | else { | |
4101 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
4102 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
4103 | exec_control); | |
4104 | } | |
4105 | } | |
4106 | } | |
0e851880 SY |
4107 | } |
4108 | ||
cbdd1bea | 4109 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
4110 | .cpu_has_kvm_support = cpu_has_kvm_support, |
4111 | .disabled_by_bios = vmx_disabled_by_bios, | |
4112 | .hardware_setup = hardware_setup, | |
4113 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 4114 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
4115 | .hardware_enable = hardware_enable, |
4116 | .hardware_disable = hardware_disable, | |
04547156 | 4117 | .cpu_has_accelerated_tpr = report_flexpriority, |
6aa8b732 AK |
4118 | |
4119 | .vcpu_create = vmx_create_vcpu, | |
4120 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 4121 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 4122 | |
04d2cc77 | 4123 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
4124 | .vcpu_load = vmx_vcpu_load, |
4125 | .vcpu_put = vmx_vcpu_put, | |
4126 | ||
4127 | .set_guest_debug = set_guest_debug, | |
4128 | .get_msr = vmx_get_msr, | |
4129 | .set_msr = vmx_set_msr, | |
4130 | .get_segment_base = vmx_get_segment_base, | |
4131 | .get_segment = vmx_get_segment, | |
4132 | .set_segment = vmx_set_segment, | |
2e4d2653 | 4133 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 4134 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 4135 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
25c4c276 | 4136 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 4137 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
4138 | .set_cr3 = vmx_set_cr3, |
4139 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 4140 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
4141 | .get_idt = vmx_get_idt, |
4142 | .set_idt = vmx_set_idt, | |
4143 | .get_gdt = vmx_get_gdt, | |
4144 | .set_gdt = vmx_set_gdt, | |
5fdbf976 | 4145 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
4146 | .get_rflags = vmx_get_rflags, |
4147 | .set_rflags = vmx_set_rflags, | |
02daab21 | 4148 | .fpu_deactivate = vmx_fpu_deactivate, |
6aa8b732 AK |
4149 | |
4150 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 4151 | |
6aa8b732 | 4152 | .run = vmx_vcpu_run, |
6062d012 | 4153 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 4154 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4155 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
4156 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 4157 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 4158 | .set_irq = vmx_inject_irq, |
95ba8273 | 4159 | .set_nmi = vmx_inject_nmi, |
298101da | 4160 | .queue_exception = vmx_queue_exception, |
78646121 | 4161 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 4162 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
4163 | .get_nmi_mask = vmx_get_nmi_mask, |
4164 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
4165 | .enable_nmi_window = enable_nmi_window, |
4166 | .enable_irq_window = enable_irq_window, | |
4167 | .update_cr8_intercept = update_cr8_intercept, | |
95ba8273 | 4168 | |
cbc94022 | 4169 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 4170 | .get_tdp_level = get_ept_level, |
4b12f0de | 4171 | .get_mt_mask = vmx_get_mt_mask, |
229456fc MT |
4172 | |
4173 | .exit_reasons_str = vmx_exit_reasons_str, | |
17cc3935 | 4174 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
4175 | |
4176 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
4177 | |
4178 | .rdtscp_supported = vmx_rdtscp_supported, | |
6aa8b732 AK |
4179 | }; |
4180 | ||
4181 | static int __init vmx_init(void) | |
4182 | { | |
26bb0981 AK |
4183 | int r, i; |
4184 | ||
4185 | rdmsrl_safe(MSR_EFER, &host_efer); | |
4186 | ||
4187 | for (i = 0; i < NR_VMX_MSR; ++i) | |
4188 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
fdef3ad1 | 4189 | |
3e7c73e9 | 4190 | vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL); |
fdef3ad1 HQ |
4191 | if (!vmx_io_bitmap_a) |
4192 | return -ENOMEM; | |
4193 | ||
3e7c73e9 | 4194 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); |
fdef3ad1 HQ |
4195 | if (!vmx_io_bitmap_b) { |
4196 | r = -ENOMEM; | |
4197 | goto out; | |
4198 | } | |
4199 | ||
5897297b AK |
4200 | vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL); |
4201 | if (!vmx_msr_bitmap_legacy) { | |
25c5f225 SY |
4202 | r = -ENOMEM; |
4203 | goto out1; | |
4204 | } | |
4205 | ||
5897297b AK |
4206 | vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL); |
4207 | if (!vmx_msr_bitmap_longmode) { | |
4208 | r = -ENOMEM; | |
4209 | goto out2; | |
4210 | } | |
4211 | ||
fdef3ad1 HQ |
4212 | /* |
4213 | * Allow direct access to the PC debug port (it is often used for I/O | |
4214 | * delays, but the vmexits simply slow things down). | |
4215 | */ | |
3e7c73e9 AK |
4216 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); |
4217 | clear_bit(0x80, vmx_io_bitmap_a); | |
fdef3ad1 | 4218 | |
3e7c73e9 | 4219 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); |
fdef3ad1 | 4220 | |
5897297b AK |
4221 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); |
4222 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
25c5f225 | 4223 | |
2384d2b3 SY |
4224 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
4225 | ||
cb498ea2 | 4226 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); |
fdef3ad1 | 4227 | if (r) |
5897297b | 4228 | goto out3; |
25c5f225 | 4229 | |
5897297b AK |
4230 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
4231 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
4232 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
4233 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
4234 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
4235 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
fdef3ad1 | 4236 | |
089d034e | 4237 | if (enable_ept) { |
1439442c | 4238 | bypass_guest_pf = 0; |
5fdbcb9d | 4239 | kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | |
2aaf69dc | 4240 | VMX_EPT_WRITABLE_MASK); |
534e38b4 | 4241 | kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, |
4b12f0de | 4242 | VMX_EPT_EXECUTABLE_MASK); |
5fdbcb9d SY |
4243 | kvm_enable_tdp(); |
4244 | } else | |
4245 | kvm_disable_tdp(); | |
1439442c | 4246 | |
c7addb90 AK |
4247 | if (bypass_guest_pf) |
4248 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
4249 | ||
fdef3ad1 HQ |
4250 | return 0; |
4251 | ||
5897297b AK |
4252 | out3: |
4253 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
25c5f225 | 4254 | out2: |
5897297b | 4255 | free_page((unsigned long)vmx_msr_bitmap_legacy); |
fdef3ad1 | 4256 | out1: |
3e7c73e9 | 4257 | free_page((unsigned long)vmx_io_bitmap_b); |
fdef3ad1 | 4258 | out: |
3e7c73e9 | 4259 | free_page((unsigned long)vmx_io_bitmap_a); |
fdef3ad1 | 4260 | return r; |
6aa8b732 AK |
4261 | } |
4262 | ||
4263 | static void __exit vmx_exit(void) | |
4264 | { | |
5897297b AK |
4265 | free_page((unsigned long)vmx_msr_bitmap_legacy); |
4266 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
3e7c73e9 AK |
4267 | free_page((unsigned long)vmx_io_bitmap_b); |
4268 | free_page((unsigned long)vmx_io_bitmap_a); | |
fdef3ad1 | 4269 | |
cb498ea2 | 4270 | kvm_exit(); |
6aa8b732 AK |
4271 | } |
4272 | ||
4273 | module_init(vmx_init) | |
4274 | module_exit(vmx_exit) |