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target-i386: Print deprecation warning if xlevel < 0x80000000
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf
EH		 26#include "sysemu/cpus.h"
27#include "topology.h"
c6dc6f63 28
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
7b1b5d19 33#include "qapi/visitor.h"
9c17d615 34#include "sysemu/arch_init.h"
71ad61d3 35
28f52cc0
VR		 36#include "hyperv.h"
37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
bdeec802
IM		 44#ifndef CONFIG_USER_ONLY
45#include "hw/xen.h"
46#include "hw/sysbus.h"
449994eb 47#include "hw/apic_internal.h"
bdeec802
IM		 48#endif
49
c6dc6f63
AP		 50/* feature flags taken from "Intel Processor Identification and the CPUID
51 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
52 * between feature naming conventions, aliases may be added.
53 */
54static const char *feature_name[] = {
55 "fpu", "vme", "de", "pse",
56 "tsc", "msr", "pae", "mce",
57 "cx8", "apic", NULL, "sep",
58 "mtrr", "pge", "mca", "cmov",
59 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
60 NULL, "ds" /* Intel dts */, "acpi", "mmx",
61 "fxsr", "sse", "sse2", "ss",
62 "ht" /* Intel htt */, "tm", "ia64", "pbe",
63};
64static const char *ext_feature_name[] = {
f370be3c 65 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 66 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 67 "tm2", "ssse3", "cid", NULL,
e117f772 68 "fma", "cx16", "xtpr", "pdcm",
434acb81 69 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 70 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 71 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 72 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 73};
3b671a40
EH		 74/* Feature names that are already defined on feature_name[] but are set on
75 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
76 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
77 * if and only if CPU vendor is AMD.
78 */
c6dc6f63 79static const char *ext2_feature_name[] = {
3b671a40
EH		 80 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
81 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
82 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
83 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
84 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
85 "nx|xd", NULL, "mmxext", NULL /* mmx */,
86 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 87 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 88};
89static const char *ext3_feature_name[] = {
90 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
91 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 92 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 93 "skinit", "wdt", NULL, "lwp",
94 "fma4", "tce", NULL, "nodeid_msr",
95 NULL, "tbm", "topoext", "perfctr_core",
96 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 97 NULL, NULL, NULL, NULL,
98};
99
89e49c8b
EH		 100static const char *ext4_feature_name[] = {
101 NULL, NULL, "xstore", "xstore-en",
102 NULL, NULL, "xcrypt", "xcrypt-en",
103 "ace2", "ace2-en", "phe", "phe-en",
104 "pmm", "pmm-en", NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
107 NULL, NULL, NULL, NULL,
108 NULL, NULL, NULL, NULL,
109};
110
c6dc6f63 111static const char *kvm_feature_name[] = {
c3d39807
DS		 112 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
113 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 NULL, NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 120};
121
296acb64
JR		 122static const char *svm_feature_name[] = {
123 "npt", "lbrv", "svm_lock", "nrip_save",
124 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
125 NULL, NULL, "pause_filter", NULL,
126 "pfthreshold", NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131};
132
a9321a4d 133static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 134 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
135 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 136 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 137 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
138};
139
5ef57876
EH		 140typedef struct FeatureWordInfo {
141 const char **feat_names;
bffd67b0
EH		 142 uint32_t cpuid_eax; /* Input EAX for CPUID */
143 int cpuid_reg; /* R_* register constant */
5ef57876
EH		 144} FeatureWordInfo;
145
146static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 147 [FEAT_1_EDX] = {
148 .feat_names = feature_name,
149 .cpuid_eax = 1, .cpuid_reg = R_EDX,
150 },
151 [FEAT_1_ECX] = {
152 .feat_names = ext_feature_name,
153 .cpuid_eax = 1, .cpuid_reg = R_ECX,
154 },
155 [FEAT_8000_0001_EDX] = {
156 .feat_names = ext2_feature_name,
157 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
158 },
159 [FEAT_8000_0001_ECX] = {
160 .feat_names = ext3_feature_name,
161 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
162 },
89e49c8b
EH		 163 [FEAT_C000_0001_EDX] = {
164 .feat_names = ext4_feature_name,
165 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
166 },
bffd67b0
EH		 167 [FEAT_KVM] = {
168 .feat_names = kvm_feature_name,
169 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
170 },
171 [FEAT_SVM] = {
172 .feat_names = svm_feature_name,
173 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
174 },
175 [FEAT_7_0_EBX] = {
176 .feat_names = cpuid_7_0_ebx_feature_name,
177 .cpuid_eax = 7, .cpuid_reg = R_EBX,
178 },
5ef57876
EH		 179};
180
8b4beddc
EH		 181const char *get_register_name_32(unsigned int reg)
182{
183 static const char *reg_names[CPU_NB_REGS32] = {
184 [R_EAX] = "EAX",
185 [R_ECX] = "ECX",
186 [R_EDX] = "EDX",
187 [R_EBX] = "EBX",
188 [R_ESP] = "ESP",
189 [R_EBP] = "EBP",
190 [R_ESI] = "ESI",
191 [R_EDI] = "EDI",
192 };
193
194 if (reg > CPU_NB_REGS32) {
195 return NULL;
196 }
197 return reg_names[reg];
198}
199
c6dc6f63
AP		 200/* collects per-function cpuid data
201 */
202typedef struct model_features_t {
203 uint32_t *guest_feat;
204 uint32_t *host_feat;
bffd67b0 205 FeatureWord feat_word;
8b4beddc 206} model_features_t;
c6dc6f63
AP		 207
208int check_cpuid = 0;
209int enforce_cpuid = 0;
210
dc59944b
MT		 211static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
212 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 213 (1 << KVM_FEATURE_CLOCKSOURCE2) |
214 (1 << KVM_FEATURE_ASYNC_PF) |
215 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 216 (1 << KVM_FEATURE_PV_EOI) |
dc59944b 217 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
dc59944b 218
29694758 219void disable_kvm_pv_eoi(void)
dc59944b 220{
29694758 221 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
dc59944b
MT		 222}
223
bb44e0d1
JK		 224void host_cpuid(uint32_t function, uint32_t count,
225 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 226{
227#if defined(CONFIG_KVM)
a1fd24af
AL		 228 uint32_t vec[4];
229
230#ifdef __x86_64__
231 asm volatile("cpuid"
232 : "=a"(vec[0]), "=b"(vec[1]),
233 "=c"(vec[2]), "=d"(vec[3])
234 : "0"(function), "c"(count) : "cc");
235#else
236 asm volatile("pusha \n\t"
237 "cpuid \n\t"
238 "mov %%eax, 0(%2) \n\t"
239 "mov %%ebx, 4(%2) \n\t"
240 "mov %%ecx, 8(%2) \n\t"
241 "mov %%edx, 12(%2) \n\t"
242 "popa"
243 : : "a"(function), "c"(count), "S"(vec)
244 : "memory", "cc");
245#endif
246
bdde476a 247 if (eax)
a1fd24af 248 *eax = vec[0];
bdde476a 249 if (ebx)
a1fd24af 250 *ebx = vec[1];
bdde476a 251 if (ecx)
a1fd24af 252 *ecx = vec[2];
bdde476a 253 if (edx)
a1fd24af 254 *edx = vec[3];
bdde476a
AP		 255#endif
256}
c6dc6f63
AP		 257
258#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
259
260/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
261 * a substring. ex if !NULL points to the first char after a substring,
262 * otherwise the string is assumed to sized by a terminating nul.
263 * Return lexical ordering of *s1:*s2.
264 */
265static int sstrcmp(const char *s1, const char *e1, const char *s2,
266 const char *e2)
267{
268 for (;;) {
269 if (!*s1 || !*s2 || *s1 != *s2)
270 return (*s1 - *s2);
271 ++s1, ++s2;
272 if (s1 == e1 && s2 == e2)
273 return (0);
274 else if (s1 == e1)
275 return (*s2);
276 else if (s2 == e2)
277 return (*s1);
278 }
279}
280
281/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
282 * '|' delimited (possibly empty) strings in which case search for a match
283 * within the alternatives proceeds left to right. Return 0 for success,
284 * non-zero otherwise.
285 */
286static int altcmp(const char *s, const char *e, const char *altstr)
287{
288 const char *p, *q;
289
290 for (q = p = altstr; ; ) {
291 while (*p && *p != '|')
292 ++p;
293 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
294 return (0);
295 if (!*p)
296 return (1);
297 else
298 q = ++p;
299 }
300}
301
302/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 303 * *pval and return true, otherwise return false
c6dc6f63 304 */
e41e0fc6
JK		 305static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
306 const char **featureset)
c6dc6f63
AP		 307{
308 uint32_t mask;
309 const char **ppc;
e41e0fc6 310 bool found = false;
c6dc6f63 311
e41e0fc6 312 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 313 if (*ppc && !altcmp(s, e, *ppc)) {
314 *pval |= mask;
e41e0fc6 315 found = true;
c6dc6f63 316 }
e41e0fc6
JK		 317 }
318 return found;
c6dc6f63
AP		 319}
320
5ef57876
EH		 321static void add_flagname_to_bitmaps(const char *flagname,
322 FeatureWordArray words)
c6dc6f63 323{
5ef57876
EH		 324 FeatureWord w;
325 for (w = 0; w < FEATURE_WORDS; w++) {
326 FeatureWordInfo *wi = &feature_word_info[w];
327 if (wi->feat_names &&
328 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
329 break;
330 }
331 }
332 if (w == FEATURE_WORDS) {
333 fprintf(stderr, "CPU feature %s not found\n", flagname);
334 }
c6dc6f63
AP		 335}
336
337typedef struct x86_def_t {
c6dc6f63
AP		 338 const char *name;
339 uint32_t level;
340 uint32_t vendor1, vendor2, vendor3;
341 int family;
342 int model;
343 int stepping;
b862d1fe 344 int tsc_khz;
296acb64
JR		 345 uint32_t features, ext_features, ext2_features, ext3_features;
346 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 347 uint32_t xlevel;
348 char model_id[48];
349 int vendor_override;
b3baa152
BW		 350 /* Store the results of Centaur's CPUID instructions */
351 uint32_t ext4_features;
352 uint32_t xlevel2;
13526728
EH		 353 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
354 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 355} x86_def_t;
356
357#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
358#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
359 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
360#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
361 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
362 CPUID_PSE36 | CPUID_FXSR)
363#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
364#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
365 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
366 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
367 CPUID_PAE | CPUID_SEP | CPUID_APIC)
368
551a2dec
AP		 369#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
370 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
371 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
372 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
373 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 374 /* partly implemented:
375 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
376 CPUID_PSE36 (needed for Solaris) */
377 /* missing:
378 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 379#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
a0a70681 380 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 381 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 382 /* missing:
383 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 384 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
60032ac0 385#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 386 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
387 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 388 /* missing:
389 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 390#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
391 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 392#define TCG_SVM_FEATURES 0
a9321a4d 393#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
551a2dec 394
7fc9b714 395/* built-in CPU model definitions
c6dc6f63
AP		 396 */
397static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 398 {
399 .name = "qemu64",
400 .level = 4,
401 .vendor1 = CPUID_VENDOR_AMD_1,
402 .vendor2 = CPUID_VENDOR_AMD_2,
403 .vendor3 = CPUID_VENDOR_AMD_3,
404 .family = 6,
405 .model = 2,
406 .stepping = 3,
407 .features = PPRO_FEATURES |
c6dc6f63 408 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 409 CPUID_PSE36,
410 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
60032ac0 411 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 412 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
413 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
414 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
415 .xlevel = 0x8000000A,
c6dc6f63
AP		 416 },
417 {
418 .name = "phenom",
419 .level = 5,
420 .vendor1 = CPUID_VENDOR_AMD_1,
421 .vendor2 = CPUID_VENDOR_AMD_2,
422 .vendor3 = CPUID_VENDOR_AMD_3,
423 .family = 16,
424 .model = 2,
425 .stepping = 3,
c6dc6f63
AP		 426 .features = PPRO_FEATURES |
427 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 428 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 429 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
430 CPUID_EXT_POPCNT,
60032ac0 431 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 432 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
433 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 434 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 435 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
436 CPUID_EXT3_CR8LEG,
437 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
438 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
439 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
440 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 441 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 442 .xlevel = 0x8000001A,
443 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
444 },
445 {
446 .name = "core2duo",
447 .level = 10,
ebe8b9c6
IM		 448 .vendor1 = CPUID_VENDOR_INTEL_1,
449 .vendor2 = CPUID_VENDOR_INTEL_2,
450 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 451 .family = 6,
452 .model = 15,
453 .stepping = 11,
c6dc6f63
AP		 454 .features = PPRO_FEATURES |
455 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 456 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
457 CPUID_HT | CPUID_TM | CPUID_PBE,
458 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
459 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
460 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 461 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
462 .ext3_features = CPUID_EXT3_LAHF_LM,
463 .xlevel = 0x80000008,
464 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
465 },
466 {
467 .name = "kvm64",
468 .level = 5,
469 .vendor1 = CPUID_VENDOR_INTEL_1,
470 .vendor2 = CPUID_VENDOR_INTEL_2,
471 .vendor3 = CPUID_VENDOR_INTEL_3,
472 .family = 15,
473 .model = 6,
474 .stepping = 1,
475 /* Missing: CPUID_VME, CPUID_HT */
476 .features = PPRO_FEATURES |
477 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
478 CPUID_PSE36,
479 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
480 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
481 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
60032ac0 482 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 483 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
484 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
485 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
486 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
487 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
488 .ext3_features = 0,
489 .xlevel = 0x80000008,
490 .model_id = "Common KVM processor"
491 },
c6dc6f63
AP		 492 {
493 .name = "qemu32",
494 .level = 4,
ebe8b9c6
IM		 495 .vendor1 = CPUID_VENDOR_INTEL_1,
496 .vendor2 = CPUID_VENDOR_INTEL_2,
497 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 498 .family = 6,
499 .model = 3,
500 .stepping = 3,
501 .features = PPRO_FEATURES,
502 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 503 .xlevel = 0x80000004,
c6dc6f63 504 },
eafaf1e5
AP		 505 {
506 .name = "kvm32",
507 .level = 5,
ebe8b9c6
IM		 508 .vendor1 = CPUID_VENDOR_INTEL_1,
509 .vendor2 = CPUID_VENDOR_INTEL_2,
510 .vendor3 = CPUID_VENDOR_INTEL_3,
eafaf1e5
AP		 511 .family = 15,
512 .model = 6,
513 .stepping = 1,
514 .features = PPRO_FEATURES |
515 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
516 .ext_features = CPUID_EXT_SSE3,
60032ac0 517 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
eafaf1e5
AP		 518 .ext3_features = 0,
519 .xlevel = 0x80000008,
520 .model_id = "Common 32-bit KVM processor"
521 },
c6dc6f63
AP		 522 {
523 .name = "coreduo",
524 .level = 10,
ebe8b9c6
IM		 525 .vendor1 = CPUID_VENDOR_INTEL_1,
526 .vendor2 = CPUID_VENDOR_INTEL_2,
527 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 528 .family = 6,
529 .model = 14,
530 .stepping = 8,
c6dc6f63 531 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 532 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
533 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
534 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
535 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 536 .ext2_features = CPUID_EXT2_NX,
537 .xlevel = 0x80000008,
538 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
539 },
540 {
541 .name = "486",
58012d66 542 .level = 1,
ebe8b9c6
IM		 543 .vendor1 = CPUID_VENDOR_INTEL_1,
544 .vendor2 = CPUID_VENDOR_INTEL_2,
545 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 546 .family = 4,
547 .model = 0,
548 .stepping = 0,
549 .features = I486_FEATURES,
550 .xlevel = 0,
551 },
552 {
553 .name = "pentium",
554 .level = 1,
ebe8b9c6
IM		 555 .vendor1 = CPUID_VENDOR_INTEL_1,
556 .vendor2 = CPUID_VENDOR_INTEL_2,
557 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 558 .family = 5,
559 .model = 4,
560 .stepping = 3,
561 .features = PENTIUM_FEATURES,
562 .xlevel = 0,
563 },
564 {
565 .name = "pentium2",
566 .level = 2,
ebe8b9c6
IM		 567 .vendor1 = CPUID_VENDOR_INTEL_1,
568 .vendor2 = CPUID_VENDOR_INTEL_2,
569 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 570 .family = 6,
571 .model = 5,
572 .stepping = 2,
573 .features = PENTIUM2_FEATURES,
574 .xlevel = 0,
575 },
576 {
577 .name = "pentium3",
578 .level = 2,
ebe8b9c6
IM		 579 .vendor1 = CPUID_VENDOR_INTEL_1,
580 .vendor2 = CPUID_VENDOR_INTEL_2,
581 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 582 .family = 6,
583 .model = 7,
584 .stepping = 3,
585 .features = PENTIUM3_FEATURES,
586 .xlevel = 0,
587 },
588 {
589 .name = "athlon",
590 .level = 2,
591 .vendor1 = CPUID_VENDOR_AMD_1,
592 .vendor2 = CPUID_VENDOR_AMD_2,
593 .vendor3 = CPUID_VENDOR_AMD_3,
594 .family = 6,
595 .model = 2,
596 .stepping = 3,
60032ac0
EH		 597 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
598 CPUID_MCA,
599 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
600 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 601 .xlevel = 0x80000008,
c6dc6f63
AP		 602 },
603 {
604 .name = "n270",
605 /* original is on level 10 */
606 .level = 5,
ebe8b9c6
IM		 607 .vendor1 = CPUID_VENDOR_INTEL_1,
608 .vendor2 = CPUID_VENDOR_INTEL_2,
609 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 610 .family = 6,
611 .model = 28,
612 .stepping = 2,
613 .features = PPRO_FEATURES |
8560efed
AJ		 614 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
615 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 616 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 617 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
618 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
60032ac0
EH		 619 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
620 CPUID_EXT2_NX,
8560efed 621 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 622 .xlevel = 0x8000000A,
623 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
624 },
3eca4642
EH		 625 {
626 .name = "Conroe",
627 .level = 2,
628 .vendor1 = CPUID_VENDOR_INTEL_1,
629 .vendor2 = CPUID_VENDOR_INTEL_2,
630 .vendor3 = CPUID_VENDOR_INTEL_3,
631 .family = 6,
632 .model = 2,
633 .stepping = 3,
634 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
635 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
636 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
637 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
638 CPUID_DE | CPUID_FP87,
639 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
640 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
641 .ext3_features = CPUID_EXT3_LAHF_LM,
642 .xlevel = 0x8000000A,
643 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
644 },
645 {
646 .name = "Penryn",
647 .level = 2,
648 .vendor1 = CPUID_VENDOR_INTEL_1,
649 .vendor2 = CPUID_VENDOR_INTEL_2,
650 .vendor3 = CPUID_VENDOR_INTEL_3,
651 .family = 6,
652 .model = 2,
653 .stepping = 3,
654 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
655 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
656 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
657 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
658 CPUID_DE | CPUID_FP87,
659 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
660 CPUID_EXT_SSE3,
661 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
662 .ext3_features = CPUID_EXT3_LAHF_LM,
663 .xlevel = 0x8000000A,
664 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
665 },
666 {
667 .name = "Nehalem",
668 .level = 2,
669 .vendor1 = CPUID_VENDOR_INTEL_1,
670 .vendor2 = CPUID_VENDOR_INTEL_2,
671 .vendor3 = CPUID_VENDOR_INTEL_3,
672 .family = 6,
673 .model = 2,
674 .stepping = 3,
675 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
676 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
677 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
678 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
679 CPUID_DE | CPUID_FP87,
680 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
681 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
682 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
683 .ext3_features = CPUID_EXT3_LAHF_LM,
684 .xlevel = 0x8000000A,
685 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
686 },
687 {
688 .name = "Westmere",
689 .level = 11,
690 .vendor1 = CPUID_VENDOR_INTEL_1,
691 .vendor2 = CPUID_VENDOR_INTEL_2,
692 .vendor3 = CPUID_VENDOR_INTEL_3,
693 .family = 6,
694 .model = 44,
695 .stepping = 1,
696 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
697 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
698 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
699 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
700 CPUID_DE | CPUID_FP87,
701 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
702 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
703 CPUID_EXT_SSE3,
704 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
705 .ext3_features = CPUID_EXT3_LAHF_LM,
706 .xlevel = 0x8000000A,
707 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
708 },
709 {
710 .name = "SandyBridge",
711 .level = 0xd,
712 .vendor1 = CPUID_VENDOR_INTEL_1,
713 .vendor2 = CPUID_VENDOR_INTEL_2,
714 .vendor3 = CPUID_VENDOR_INTEL_3,
715 .family = 6,
716 .model = 42,
717 .stepping = 1,
718 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
719 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
720 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
721 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
722 CPUID_DE | CPUID_FP87,
723 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
724 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
725 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
726 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
727 CPUID_EXT_SSE3,
728 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
729 CPUID_EXT2_SYSCALL,
730 .ext3_features = CPUID_EXT3_LAHF_LM,
731 .xlevel = 0x8000000A,
732 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
733 },
37507094
EH		 734 {
735 .name = "Haswell",
736 .level = 0xd,
737 .vendor1 = CPUID_VENDOR_INTEL_1,
738 .vendor2 = CPUID_VENDOR_INTEL_2,
739 .vendor3 = CPUID_VENDOR_INTEL_3,
740 .family = 6,
741 .model = 60,
742 .stepping = 1,
743 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
744 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 745 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 746 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
747 CPUID_DE | CPUID_FP87,
748 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
749 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
750 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
751 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
752 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
753 CPUID_EXT_PCID,
80ae4160
EH		 754 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
755 CPUID_EXT2_SYSCALL,
37507094
EH		 756 .ext3_features = CPUID_EXT3_LAHF_LM,
757 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
758 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
759 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
760 CPUID_7_0_EBX_RTM,
761 .xlevel = 0x8000000A,
762 .model_id = "Intel Core Processor (Haswell)",
763 },
3eca4642
EH		 764 {
765 .name = "Opteron_G1",
766 .level = 5,
767 .vendor1 = CPUID_VENDOR_AMD_1,
768 .vendor2 = CPUID_VENDOR_AMD_2,
769 .vendor3 = CPUID_VENDOR_AMD_3,
770 .family = 15,
771 .model = 6,
772 .stepping = 1,
773 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
774 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
775 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
776 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
777 CPUID_DE | CPUID_FP87,
778 .ext_features = CPUID_EXT_SSE3,
779 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
780 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
781 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
782 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
783 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
784 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
785 .xlevel = 0x80000008,
786 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
787 },
788 {
789 .name = "Opteron_G2",
790 .level = 5,
791 .vendor1 = CPUID_VENDOR_AMD_1,
792 .vendor2 = CPUID_VENDOR_AMD_2,
793 .vendor3 = CPUID_VENDOR_AMD_3,
794 .family = 15,
795 .model = 6,
796 .stepping = 1,
797 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
798 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
799 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
800 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
801 CPUID_DE | CPUID_FP87,
802 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
803 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
804 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
805 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
806 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
807 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
808 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
809 CPUID_EXT2_DE | CPUID_EXT2_FPU,
810 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
811 .xlevel = 0x80000008,
812 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
813 },
814 {
815 .name = "Opteron_G3",
816 .level = 5,
817 .vendor1 = CPUID_VENDOR_AMD_1,
818 .vendor2 = CPUID_VENDOR_AMD_2,
819 .vendor3 = CPUID_VENDOR_AMD_3,
820 .family = 15,
821 .model = 6,
822 .stepping = 1,
823 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
824 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
825 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
826 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
827 CPUID_DE | CPUID_FP87,
828 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
829 CPUID_EXT_SSE3,
830 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
831 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
832 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
833 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
834 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
835 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
836 CPUID_EXT2_DE | CPUID_EXT2_FPU,
837 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
838 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
839 .xlevel = 0x80000008,
840 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
841 },
842 {
843 .name = "Opteron_G4",
844 .level = 0xd,
845 .vendor1 = CPUID_VENDOR_AMD_1,
846 .vendor2 = CPUID_VENDOR_AMD_2,
847 .vendor3 = CPUID_VENDOR_AMD_3,
848 .family = 21,
849 .model = 1,
850 .stepping = 2,
851 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
852 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
853 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
854 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
855 CPUID_DE | CPUID_FP87,
856 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
857 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
858 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
859 CPUID_EXT_SSE3,
860 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
861 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
862 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
863 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
864 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
865 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
866 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
867 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
868 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
869 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
870 CPUID_EXT3_LAHF_LM,
871 .xlevel = 0x8000001A,
872 .model_id = "AMD Opteron 62xx class CPU",
873 },
021941b9
AP		 874 {
875 .name = "Opteron_G5",
876 .level = 0xd,
877 .vendor1 = CPUID_VENDOR_AMD_1,
878 .vendor2 = CPUID_VENDOR_AMD_2,
879 .vendor3 = CPUID_VENDOR_AMD_3,
880 .family = 21,
881 .model = 2,
882 .stepping = 0,
883 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
884 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
885 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
886 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
887 CPUID_DE | CPUID_FP87,
888 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
889 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
890 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
891 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
892 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
893 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
894 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
895 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
896 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
897 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
898 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
899 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
900 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
901 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
902 CPUID_EXT3_LAHF_LM,
903 .xlevel = 0x8000001A,
904 .model_id = "AMD Opteron 63xx class CPU",
905 },
c6dc6f63
AP		 906};
907
e4ab0d6b 908#ifdef CONFIG_KVM
c6dc6f63
AP		 909static int cpu_x86_fill_model_id(char *str)
910{
911 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
912 int i;
913
914 for (i = 0; i < 3; i++) {
915 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
916 memcpy(str + i * 16 + 0, &eax, 4);
917 memcpy(str + i * 16 + 4, &ebx, 4);
918 memcpy(str + i * 16 + 8, &ecx, 4);
919 memcpy(str + i * 16 + 12, &edx, 4);
920 }
921 return 0;
922}
e4ab0d6b 923#endif
c6dc6f63 924
6e746f30
EH		 925/* Fill a x86_def_t struct with information about the host CPU, and
926 * the CPU features supported by the host hardware + host kernel
927 *
928 * This function may be called only if KVM is enabled.
929 */
930static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 931{
e4ab0d6b 932#ifdef CONFIG_KVM
12869995 933 KVMState *s = kvm_state;
c6dc6f63
AP		 934 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
935
6e746f30
EH		 936 assert(kvm_enabled());
937
c6dc6f63
AP		 938 x86_cpu_def->name = "host";
939 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
c6dc6f63
AP		 940 x86_cpu_def->vendor1 = ebx;
941 x86_cpu_def->vendor2 = edx;
942 x86_cpu_def->vendor3 = ecx;
943
944 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
945 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
946 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
947 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 948
12869995
EH		 949 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
950 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
951 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 952
6e746f30 953 if (x86_cpu_def->level >= 7) {
12869995
EH		 954 x86_cpu_def->cpuid_7_0_ebx_features =
955 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728
EH		 956 } else {
957 x86_cpu_def->cpuid_7_0_ebx_features = 0;
958 }
959
12869995
EH		 960 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
961 x86_cpu_def->ext2_features =
962 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
963 x86_cpu_def->ext3_features =
964 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 965
c6dc6f63
AP		 966 cpu_x86_fill_model_id(x86_cpu_def->model_id);
967 x86_cpu_def->vendor_override = 0;
968
b3baa152
BW		 969 /* Call Centaur's CPUID instruction. */
970 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
971 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
972 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
973 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
12869995 974 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
b3baa152
BW		 975 if (eax >= 0xC0000001) {
976 /* Support VIA max extended level */
977 x86_cpu_def->xlevel2 = eax;
978 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
12869995
EH		 979 x86_cpu_def->ext4_features =
980 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
b3baa152
BW		 981 }
982 }
296acb64 983
fcb93c03
EH		 984 /* Other KVM-specific feature fields: */
985 x86_cpu_def->svm_features =
986 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
bd004bef
EH		 987 x86_cpu_def->kvm_features =
988 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 989
e4ab0d6b 990#endif /* CONFIG_KVM */
c6dc6f63
AP		 991}
992
bffd67b0 993static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 994{
995 int i;
996
997 for (i = 0; i < 32; ++i)
998 if (1 << i & mask) {
bffd67b0 999 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1000 assert(reg);
1001 fprintf(stderr, "warning: host doesn't support requested feature: "
1002 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1003 f->cpuid_eax, reg,
1004 f->feat_names[i] ? "." : "",
1005 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 1006 break;
1007 }
1008 return 0;
1009}
1010
07ca5945
EH		 1011/* Check if all requested cpu flags are making their way to the guest
1012 *
1013 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 1014 *
1015 * This function may be called only if KVM is enabled.
c6dc6f63 1016 */
5ec01c2e 1017static int kvm_check_features_against_host(X86CPU *cpu)
c6dc6f63 1018{
5ec01c2e 1019 CPUX86State *env = &cpu->env;
c6dc6f63
AP		 1020 x86_def_t host_def;
1021 uint32_t mask;
1022 int rv, i;
1023 struct model_features_t ft[] = {
5ec01c2e 1024 {&env->cpuid_features, &host_def.features,
bffd67b0 1025 FEAT_1_EDX },
5ec01c2e 1026 {&env->cpuid_ext_features, &host_def.ext_features,
bffd67b0 1027 FEAT_1_ECX },
5ec01c2e 1028 {&env->cpuid_ext2_features, &host_def.ext2_features,
bffd67b0 1029 FEAT_8000_0001_EDX },
5ec01c2e 1030 {&env->cpuid_ext3_features, &host_def.ext3_features,
bffd67b0 1031 FEAT_8000_0001_ECX },
5ec01c2e 1032 {&env->cpuid_ext4_features, &host_def.ext4_features,
07ca5945 1033 FEAT_C000_0001_EDX },
5ec01c2e 1034 {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
07ca5945 1035 FEAT_7_0_EBX },
5ec01c2e 1036 {&env->cpuid_svm_features, &host_def.svm_features,
07ca5945 1037 FEAT_SVM },
5ec01c2e 1038 {&env->cpuid_kvm_features, &host_def.kvm_features,
07ca5945 1039 FEAT_KVM },
8b4beddc 1040 };
c6dc6f63 1041
6e746f30
EH		 1042 assert(kvm_enabled());
1043
1044 kvm_cpu_fill_host(&host_def);
bffd67b0
EH		 1045 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1046 FeatureWord w = ft[i].feat_word;
1047 FeatureWordInfo *wi = &feature_word_info[w];
1048 for (mask = 1; mask; mask <<= 1) {
e8beac00 1049 if (*ft[i].guest_feat & mask &&
c6dc6f63 1050 !(*ft[i].host_feat & mask)) {
bffd67b0
EH		 1051 unavailable_host_feature(wi, mask);
1052 rv = 1;
1053 }
1054 }
1055 }
c6dc6f63
AP		 1056 return rv;
1057}
1058
95b8519d
AF		 1059static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1060 const char *name, Error **errp)
1061{
1062 X86CPU *cpu = X86_CPU(obj);
1063 CPUX86State *env = &cpu->env;
1064 int64_t value;
1065
1066 value = (env->cpuid_version >> 8) & 0xf;
1067 if (value == 0xf) {
1068 value += (env->cpuid_version >> 20) & 0xff;
1069 }
1070 visit_type_int(v, &value, name, errp);
1071}
1072
71ad61d3
AF		 1073static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1074 const char *name, Error **errp)
ed5e1ec3 1075{
71ad61d3
AF		 1076 X86CPU *cpu = X86_CPU(obj);
1077 CPUX86State *env = &cpu->env;
1078 const int64_t min = 0;
1079 const int64_t max = 0xff + 0xf;
1080 int64_t value;
1081
1082 visit_type_int(v, &value, name, errp);
1083 if (error_is_set(errp)) {
1084 return;
1085 }
1086 if (value < min || value > max) {
1087 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1088 name ? name : "null", value, min, max);
1089 return;
1090 }
1091
ed5e1ec3 1092 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1093 if (value > 0x0f) {
1094 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1095 } else {
71ad61d3 1096 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1097 }
1098}
1099
67e30c83
AF		 1100static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1101 const char *name, Error **errp)
1102{
1103 X86CPU *cpu = X86_CPU(obj);
1104 CPUX86State *env = &cpu->env;
1105 int64_t value;
1106
1107 value = (env->cpuid_version >> 4) & 0xf;
1108 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1109 visit_type_int(v, &value, name, errp);
1110}
1111
c5291a4f
AF		 1112static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1113 const char *name, Error **errp)
b0704cbd 1114{
c5291a4f
AF		 1115 X86CPU *cpu = X86_CPU(obj);
1116 CPUX86State *env = &cpu->env;
1117 const int64_t min = 0;
1118 const int64_t max = 0xff;
1119 int64_t value;
1120
1121 visit_type_int(v, &value, name, errp);
1122 if (error_is_set(errp)) {
1123 return;
1124 }
1125 if (value < min || value > max) {
1126 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1127 name ? name : "null", value, min, max);
1128 return;
1129 }
1130
b0704cbd 1131 env->cpuid_version &= ~0xf00f0;
c5291a4f 1132 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1133}
1134
35112e41
AF		 1135static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1136 void *opaque, const char *name,
1137 Error **errp)
1138{
1139 X86CPU *cpu = X86_CPU(obj);
1140 CPUX86State *env = &cpu->env;
1141 int64_t value;
1142
1143 value = env->cpuid_version & 0xf;
1144 visit_type_int(v, &value, name, errp);
1145}
1146
036e2222
AF		 1147static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1148 void *opaque, const char *name,
1149 Error **errp)
38c3dc46 1150{
036e2222
AF		 1151 X86CPU *cpu = X86_CPU(obj);
1152 CPUX86State *env = &cpu->env;
1153 const int64_t min = 0;
1154 const int64_t max = 0xf;
1155 int64_t value;
1156
1157 visit_type_int(v, &value, name, errp);
1158 if (error_is_set(errp)) {
1159 return;
1160 }
1161 if (value < min || value > max) {
1162 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1163 name ? name : "null", value, min, max);
1164 return;
1165 }
1166
38c3dc46 1167 env->cpuid_version &= ~0xf;
036e2222 1168 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1169}
1170
8e1898bf
AF		 1171static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1172 const char *name, Error **errp)
1173{
1174 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1175
fa029887 1176 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1177}
1178
1179static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1180 const char *name, Error **errp)
1181{
1182 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1183
fa029887 1184 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1185}
1186
16b93aa8
AF		 1187static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1188 const char *name, Error **errp)
1189{
1190 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1191
fa029887 1192 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1193}
1194
1195static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1196 const char *name, Error **errp)
1197{
1198 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1199
fa029887 1200 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1201}
1202
d480e1af
AF		 1203static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1204{
1205 X86CPU *cpu = X86_CPU(obj);
1206 CPUX86State *env = &cpu->env;
1207 char *value;
1208 int i;
1209
9df694ee 1210 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
d480e1af
AF		 1211 for (i = 0; i < 4; i++) {
1212 value[i ] = env->cpuid_vendor1 >> (8 * i);
1213 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1214 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1215 }
9df694ee 1216 value[CPUID_VENDOR_SZ] = '\0';
d480e1af
AF		 1217 return value;
1218}
1219
1220static void x86_cpuid_set_vendor(Object *obj, const char *value,
1221 Error **errp)
1222{
1223 X86CPU *cpu = X86_CPU(obj);
1224 CPUX86State *env = &cpu->env;
1225 int i;
1226
9df694ee 1227 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1228 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1229 "vendor", value);
1230 return;
1231 }
1232
1233 env->cpuid_vendor1 = 0;
1234 env->cpuid_vendor2 = 0;
1235 env->cpuid_vendor3 = 0;
1236 for (i = 0; i < 4; i++) {
1237 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1238 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1239 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1240 }
1241 env->cpuid_vendor_override = 1;
1242}
1243
63e886eb
AF		 1244static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1245{
1246 X86CPU *cpu = X86_CPU(obj);
1247 CPUX86State *env = &cpu->env;
1248 char *value;
1249 int i;
1250
1251 value = g_malloc(48 + 1);
1252 for (i = 0; i < 48; i++) {
1253 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1254 }
1255 value[48] = '\0';
1256 return value;
1257}
1258
938d4c25
AF		 1259static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1260 Error **errp)
dcce6675 1261{
938d4c25
AF		 1262 X86CPU *cpu = X86_CPU(obj);
1263 CPUX86State *env = &cpu->env;
dcce6675
AF		 1264 int c, len, i;
1265
1266 if (model_id == NULL) {
1267 model_id = "";
1268 }
1269 len = strlen(model_id);
d0a6acf4 1270 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1271 for (i = 0; i < 48; i++) {
1272 if (i >= len) {
1273 c = '\0';
1274 } else {
1275 c = (uint8_t)model_id[i];
1276 }
1277 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1278 }
1279}
1280
89e48965
AF		 1281static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1282 const char *name, Error **errp)
1283{
1284 X86CPU *cpu = X86_CPU(obj);
1285 int64_t value;
1286
1287 value = cpu->env.tsc_khz * 1000;
1288 visit_type_int(v, &value, name, errp);
1289}
1290
1291static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1292 const char *name, Error **errp)
1293{
1294 X86CPU *cpu = X86_CPU(obj);
1295 const int64_t min = 0;
2e84849a 1296 const int64_t max = INT64_MAX;
89e48965
AF		 1297 int64_t value;
1298
1299 visit_type_int(v, &value, name, errp);
1300 if (error_is_set(errp)) {
1301 return;
1302 }
1303 if (value < min || value > max) {
1304 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1305 name ? name : "null", value, min, max);
1306 return;
1307 }
1308
1309 cpu->env.tsc_khz = value / 1000;
1310}
1311
8f961357 1312static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
c6dc6f63 1313{
c6dc6f63 1314 x86_def_t *def;
7fc9b714 1315 int i;
c6dc6f63 1316
4bfe910d
AF		 1317 if (name == NULL) {
1318 return -1;
9f3fb565 1319 }
4bfe910d 1320 if (kvm_enabled() && strcmp(name, "host") == 0) {
6e746f30 1321 kvm_cpu_fill_host(x86_cpu_def);
4bfe910d 1322 return 0;
c6dc6f63
AP		 1323 }
1324
7fc9b714
AF		 1325 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1326 def = &builtin_x86_defs[i];
4bfe910d
AF		 1327 if (strcmp(name, def->name) == 0) {
1328 memcpy(x86_cpu_def, def, sizeof(*def));
1329 return 0;
1330 }
1331 }
1332
1333 return -1;
8f961357
EH		 1334}
1335
1336/* Parse "+feature,-feature,feature=foo" CPU feature string
1337 */
1338static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1339{
1340 unsigned int i;
1341 char *featurestr; /* Single 'key=value" string being parsed */
1342 /* Features to be added */
077c68c3 1343 FeatureWordArray plus_features = { 0 };
8f961357 1344 /* Features to be removed */
5ef57876 1345 FeatureWordArray minus_features = { 0 };
8f961357
EH		 1346 uint32_t numvalue;
1347
8f961357 1348 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1349
1350 while (featurestr) {
1351 char *val;
1352 if (featurestr[0] == '+') {
5ef57876 1353 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1354 } else if (featurestr[0] == '-') {
5ef57876 1355 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1356 } else if ((val = strchr(featurestr, '='))) {
1357 *val = 0; val++;
1358 if (!strcmp(featurestr, "family")) {
1359 char *err;
1360 numvalue = strtoul(val, &err, 0);
a88a677f 1361 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 1362 fprintf(stderr, "bad numerical value %s\n", val);
1363 goto error;
1364 }
1365 x86_cpu_def->family = numvalue;
1366 } else if (!strcmp(featurestr, "model")) {
1367 char *err;
1368 numvalue = strtoul(val, &err, 0);
1369 if (!*val || *err || numvalue > 0xff) {
1370 fprintf(stderr, "bad numerical value %s\n", val);
1371 goto error;
1372 }
1373 x86_cpu_def->model = numvalue;
1374 } else if (!strcmp(featurestr, "stepping")) {
1375 char *err;
1376 numvalue = strtoul(val, &err, 0);
1377 if (!*val || *err || numvalue > 0xf) {
1378 fprintf(stderr, "bad numerical value %s\n", val);
1379 goto error;
1380 }
1381 x86_cpu_def->stepping = numvalue ;
1382 } else if (!strcmp(featurestr, "level")) {
1383 char *err;
1384 numvalue = strtoul(val, &err, 0);
1385 if (!*val || *err) {
1386 fprintf(stderr, "bad numerical value %s\n", val);
1387 goto error;
1388 }
1389 x86_cpu_def->level = numvalue;
1390 } else if (!strcmp(featurestr, "xlevel")) {
1391 char *err;
1392 numvalue = strtoul(val, &err, 0);
1393 if (!*val || *err) {
1394 fprintf(stderr, "bad numerical value %s\n", val);
1395 goto error;
1396 }
1397 if (numvalue < 0x80000000) {
8ba8a698
IM		 1398 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1399 ", fixup will be removed in future versions\n");
2f7a21c4 1400 numvalue += 0x80000000;
c6dc6f63
AP		 1401 }
1402 x86_cpu_def->xlevel = numvalue;
1403 } else if (!strcmp(featurestr, "vendor")) {
1404 if (strlen(val) != 12) {
1405 fprintf(stderr, "vendor string must be 12 chars long\n");
1406 goto error;
1407 }
1408 x86_cpu_def->vendor1 = 0;
1409 x86_cpu_def->vendor2 = 0;
1410 x86_cpu_def->vendor3 = 0;
1411 for(i = 0; i < 4; i++) {
1412 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1413 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1414 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1415 }
1416 x86_cpu_def->vendor_override = 1;
1417 } else if (!strcmp(featurestr, "model_id")) {
1418 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1419 val);
b862d1fe
JR		 1420 } else if (!strcmp(featurestr, "tsc_freq")) {
1421 int64_t tsc_freq;
1422 char *err;
1423
1424 tsc_freq = strtosz_suffix_unit(val, &err,
1425 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1426 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 1427 fprintf(stderr, "bad numerical value %s\n", val);
1428 goto error;
1429 }
1430 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 1431 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1432 char *err;
1433 numvalue = strtoul(val, &err, 0);
1434 if (!*val || *err) {
1435 fprintf(stderr, "bad numerical value %s\n", val);
1436 goto error;
1437 }
1438 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1439 } else {
1440 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1441 goto error;
1442 }
1443 } else if (!strcmp(featurestr, "check")) {
1444 check_cpuid = 1;
1445 } else if (!strcmp(featurestr, "enforce")) {
1446 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1447 } else if (!strcmp(featurestr, "hv_relaxed")) {
1448 hyperv_enable_relaxed_timing(true);
1449 } else if (!strcmp(featurestr, "hv_vapic")) {
1450 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1451 } else {
1452 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1453 goto error;
1454 }
1455 featurestr = strtok(NULL, ",");
1456 }
5ef57876
EH		 1457 x86_cpu_def->features |= plus_features[FEAT_1_EDX];
1458 x86_cpu_def->ext_features |= plus_features[FEAT_1_ECX];
1459 x86_cpu_def->ext2_features |= plus_features[FEAT_8000_0001_EDX];
1460 x86_cpu_def->ext3_features |= plus_features[FEAT_8000_0001_ECX];
89e49c8b 1461 x86_cpu_def->ext4_features |= plus_features[FEAT_C000_0001_EDX];
5ef57876
EH		 1462 x86_cpu_def->kvm_features |= plus_features[FEAT_KVM];
1463 x86_cpu_def->svm_features |= plus_features[FEAT_SVM];
1464 x86_cpu_def->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1465 x86_cpu_def->features &= ~minus_features[FEAT_1_EDX];
1466 x86_cpu_def->ext_features &= ~minus_features[FEAT_1_ECX];
1467 x86_cpu_def->ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1468 x86_cpu_def->ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
89e49c8b 1469 x86_cpu_def->ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
5ef57876
EH		 1470 x86_cpu_def->kvm_features &= ~minus_features[FEAT_KVM];
1471 x86_cpu_def->svm_features &= ~minus_features[FEAT_SVM];
1472 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63
AP		 1473 return 0;
1474
1475error:
c6dc6f63
AP		 1476 return -1;
1477}
1478
1479/* generate a composite string into buf of all cpuid names in featureset
1480 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1481 * if flags, suppress names undefined in featureset.
1482 */
1483static void listflags(char *buf, int bufsize, uint32_t fbits,
1484 const char **featureset, uint32_t flags)
1485{
1486 const char **p = &featureset[31];
1487 char *q, *b, bit;
1488 int nc;
1489
1490 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1491 *buf = '\0';
1492 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1493 if (fbits & 1 << bit && (*p || !flags)) {
1494 if (*p)
1495 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1496 else
1497 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1498 if (bufsize <= nc) {
1499 if (b) {
1500 memcpy(b, "...", sizeof("..."));
1501 }
1502 return;
1503 }
1504 q += nc;
1505 bufsize -= nc;
1506 }
1507}
1508
e916cbf8
PM		 1509/* generate CPU information. */
1510void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1511{
c6dc6f63
AP		 1512 x86_def_t *def;
1513 char buf[256];
7fc9b714 1514 int i;
c6dc6f63 1515
7fc9b714
AF		 1516 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1517 def = &builtin_x86_defs[i];
c04321b3 1518 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1519 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1520 }
ed2c54d4
AP		 1521 if (kvm_enabled()) {
1522 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1523 }
6cdf8854
PM		 1524 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1525 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
4a19e505 1526 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1527 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
4a19e505 1528 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1529 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
4a19e505 1530 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1531 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
4a19e505 1532 (*cpu_fprintf)(f, " %s\n", buf);
c6dc6f63
AP		 1533}
1534
76b64a7a 1535CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1536{
1537 CpuDefinitionInfoList *cpu_list = NULL;
1538 x86_def_t *def;
7fc9b714 1539 int i;
e3966126 1540
7fc9b714 1541 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1542 CpuDefinitionInfoList *entry;
1543 CpuDefinitionInfo *info;
1544
7fc9b714 1545 def = &builtin_x86_defs[i];
e3966126
AL		 1546 info = g_malloc0(sizeof(*info));
1547 info->name = g_strdup(def->name);
1548
1549 entry = g_malloc0(sizeof(*entry));
1550 entry->value = info;
1551 entry->next = cpu_list;
1552 cpu_list = entry;
1553 }
1554
1555 return cpu_list;
1556}
1557
bc74b7db
EH		 1558#ifdef CONFIG_KVM
1559static void filter_features_for_kvm(X86CPU *cpu)
1560{
1561 CPUX86State *env = &cpu->env;
1562 KVMState *s = kvm_state;
1563
b8091f24
EH		 1564 env->cpuid_features &=
1565 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1566 env->cpuid_ext_features &=
1567 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1568 env->cpuid_ext2_features &=
1569 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1570 env->cpuid_ext3_features &=
1571 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1572 env->cpuid_svm_features &=
1573 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
ffa8c11f
EH		 1574 env->cpuid_7_0_ebx_features &=
1575 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
bc74b7db 1576 env->cpuid_kvm_features &=
b8091f24
EH		 1577 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1578 env->cpuid_ext4_features &=
1579 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
bc74b7db
EH		 1580
1581}
1582#endif
1583
61dcd775 1584int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1585{
61dcd775 1586 CPUX86State *env = &cpu->env;
c6dc6f63 1587 x86_def_t def1, *def = &def1;
71ad61d3 1588 Error *error = NULL;
8f961357
EH		 1589 char *name, *features;
1590 gchar **model_pieces;
c6dc6f63 1591
db0ad1ba
JR		 1592 memset(def, 0, sizeof(*def));
1593
8f961357
EH		 1594 model_pieces = g_strsplit(cpu_model, ",", 2);
1595 if (!model_pieces[0]) {
fa2db3c4
IM		 1596 error_setg(&error, "Invalid/empty CPU model name");
1597 goto out;
8f961357
EH		 1598 }
1599 name = model_pieces[0];
1600 features = model_pieces[1];
1601
1602 if (cpu_x86_find_by_name(def, name) < 0) {
fa2db3c4
IM		 1603 error_setg(&error, "Unable to find CPU definition: %s", name);
1604 goto out;
8f961357
EH		 1605 }
1606
aa87d458
EH		 1607 if (kvm_enabled()) {
1608 def->kvm_features |= kvm_default_features;
1609 }
077c68c3
IM		 1610 def->ext_features |= CPUID_EXT_HYPERVISOR;
1611
8f961357 1612 if (cpu_x86_parse_featurestr(def, features) < 0) {
fa2db3c4
IM		 1613 error_setg(&error, "Invalid cpu_model string format: %s", cpu_model);
1614 goto out;
8f961357 1615 }
ebe8b9c6
IM		 1616 assert(def->vendor1);
1617 env->cpuid_vendor1 = def->vendor1;
1618 env->cpuid_vendor2 = def->vendor2;
1619 env->cpuid_vendor3 = def->vendor3;
c6dc6f63 1620 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1621 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1622 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1623 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1624 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1625 env->cpuid_features = def->features;
c6dc6f63
AP		 1626 env->cpuid_ext_features = def->ext_features;
1627 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1628 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1629 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1630 env->cpuid_kvm_features = def->kvm_features;
296acb64 1631 env->cpuid_svm_features = def->svm_features;
b3baa152 1632 env->cpuid_ext4_features = def->ext4_features;
a9321a4d 1633 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
b3baa152 1634 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1635 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1636 "tsc-frequency", &error);
3b671a40 1637
938d4c25 1638 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
fa2db3c4
IM		 1639
1640out:
1641 g_strfreev(model_pieces);
18eb473f
IM		 1642 if (error) {
1643 fprintf(stderr, "%s\n", error_get_pretty(error));
71ad61d3 1644 error_free(error);
fa2db3c4 1645 return -1;
71ad61d3 1646 }
c6dc6f63
AP		 1647 return 0;
1648}
1649
1650#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1651
0e26b7b8
BS		 1652void cpu_clear_apic_feature(CPUX86State *env)
1653{
1654 env->cpuid_features &= ~CPUID_APIC;
1655}
1656
c6dc6f63
AP		 1657#endif /* !CONFIG_USER_ONLY */
1658
c04321b3 1659/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1660 */
1661void x86_cpudef_setup(void)
1662{
93bfef4c
CV		 1663 int i, j;
1664 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1665
1666 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291 1667 x86_def_t *def = &builtin_x86_defs[i];
93bfef4c
CV		 1668
1669 /* Look for specific "cpudef" models that */
09faecf2 1670 /* have the QEMU version in .model_id */
93bfef4c 1671 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1672 if (strcmp(model_with_versions[j], def->name) == 0) {
1673 pstrcpy(def->model_id, sizeof(def->model_id),
1674 "QEMU Virtual CPU version ");
1675 pstrcat(def->model_id, sizeof(def->model_id),
1676 qemu_get_version());
93bfef4c
CV		 1677 break;
1678 }
1679 }
c6dc6f63 1680 }
c6dc6f63
AP		 1681}
1682
c6dc6f63
AP		 1683static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1684 uint32_t *ecx, uint32_t *edx)
1685{
1686 *ebx = env->cpuid_vendor1;
1687 *edx = env->cpuid_vendor2;
1688 *ecx = env->cpuid_vendor3;
1689
1690 /* sysenter isn't supported on compatibility mode on AMD, syscall
1691 * isn't supported in compatibility mode on Intel.
1692 * Normally we advertise the actual cpu vendor, but you can override
1693 * this if you want to use KVM's sysenter/syscall emulation
1694 * in compatibility mode and when doing cross vendor migration
1695 */
89354998 1696 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1697 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1698 }
1699}
1700
1701void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1702 uint32_t *eax, uint32_t *ebx,
1703 uint32_t *ecx, uint32_t *edx)
1704{
a60f24b5
AF		 1705 X86CPU *cpu = x86_env_get_cpu(env);
1706 CPUState *cs = CPU(cpu);
1707
c6dc6f63
AP		 1708 /* test if maximum index reached */
1709 if (index & 0x80000000) {
b3baa152
BW		 1710 if (index > env->cpuid_xlevel) {
1711 if (env->cpuid_xlevel2 > 0) {
1712 /* Handle the Centaur's CPUID instruction. */
1713 if (index > env->cpuid_xlevel2) {
1714 index = env->cpuid_xlevel2;
1715 } else if (index < 0xC0000000) {
1716 index = env->cpuid_xlevel;
1717 }
1718 } else {
57f26ae7
EH		 1719 /* Intel documentation states that invalid EAX input will
1720 * return the same information as EAX=cpuid_level
1721 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1722 */
1723 index = env->cpuid_level;
b3baa152
BW		 1724 }
1725 }
c6dc6f63
AP		 1726 } else {
1727 if (index > env->cpuid_level)
1728 index = env->cpuid_level;
1729 }
1730
1731 switch(index) {
1732 case 0:
1733 *eax = env->cpuid_level;
1734 get_cpuid_vendor(env, ebx, ecx, edx);
1735 break;
1736 case 1:
1737 *eax = env->cpuid_version;
1738 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1739 *ecx = env->cpuid_ext_features;
1740 *edx = env->cpuid_features;
ce3960eb
AF		 1741 if (cs->nr_cores * cs->nr_threads > 1) {
1742 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 1743 *edx |= 1 << 28; /* HTT bit */
1744 }
1745 break;
1746 case 2:
1747 /* cache info: needed for Pentium Pro compatibility */
1748 *eax = 1;
1749 *ebx = 0;
1750 *ecx = 0;
1751 *edx = 0x2c307d;
1752 break;
1753 case 4:
1754 /* cache info: needed for Core compatibility */
ce3960eb
AF		 1755 if (cs->nr_cores > 1) {
1756 *eax = (cs->nr_cores - 1) << 26;
c6dc6f63 1757 } else {
2f7a21c4 1758 *eax = 0;
c6dc6f63
AP		 1759 }
1760 switch (count) {
1761 case 0: /* L1 dcache info */
1762 *eax |= 0x0000121;
1763 *ebx = 0x1c0003f;
1764 *ecx = 0x000003f;
1765 *edx = 0x0000001;
1766 break;
1767 case 1: /* L1 icache info */
1768 *eax |= 0x0000122;
1769 *ebx = 0x1c0003f;
1770 *ecx = 0x000003f;
1771 *edx = 0x0000001;
1772 break;
1773 case 2: /* L2 cache info */
1774 *eax |= 0x0000143;
ce3960eb
AF		 1775 if (cs->nr_threads > 1) {
1776 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63
AP		 1777 }
1778 *ebx = 0x3c0003f;
1779 *ecx = 0x0000fff;
1780 *edx = 0x0000001;
1781 break;
1782 default: /* end of info */
1783 *eax = 0;
1784 *ebx = 0;
1785 *ecx = 0;
1786 *edx = 0;
1787 break;
1788 }
1789 break;
1790 case 5:
1791 /* mwait info: needed for Core compatibility */
1792 *eax = 0; /* Smallest monitor-line size in bytes */
1793 *ebx = 0; /* Largest monitor-line size in bytes */
1794 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1795 *edx = 0;
1796 break;
1797 case 6:
1798 /* Thermal and Power Leaf */
1799 *eax = 0;
1800 *ebx = 0;
1801 *ecx = 0;
1802 *edx = 0;
1803 break;
f7911686 1804 case 7:
13526728
EH		 1805 /* Structured Extended Feature Flags Enumeration Leaf */
1806 if (count == 0) {
1807 *eax = 0; /* Maximum ECX value for sub-leaves */
a9321a4d 1808 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
13526728
EH		 1809 *ecx = 0; /* Reserved */
1810 *edx = 0; /* Reserved */
f7911686
YW		 1811 } else {
1812 *eax = 0;
1813 *ebx = 0;
1814 *ecx = 0;
1815 *edx = 0;
1816 }
1817 break;
c6dc6f63
AP		 1818 case 9:
1819 /* Direct Cache Access Information Leaf */
1820 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1821 *ebx = 0;
1822 *ecx = 0;
1823 *edx = 0;
1824 break;
1825 case 0xA:
1826 /* Architectural Performance Monitoring Leaf */
a0fa8208 1827 if (kvm_enabled()) {
a60f24b5 1828 KVMState *s = cs->kvm_state;
a0fa8208
GN		 1829
1830 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1831 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1832 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1833 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1834 } else {
1835 *eax = 0;
1836 *ebx = 0;
1837 *ecx = 0;
1838 *edx = 0;
1839 }
c6dc6f63 1840 break;
51e49430
SY		 1841 case 0xD:
1842 /* Processor Extended State */
1843 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1844 *eax = 0;
1845 *ebx = 0;
1846 *ecx = 0;
1847 *edx = 0;
1848 break;
1849 }
1850 if (kvm_enabled()) {
a60f24b5 1851 KVMState *s = cs->kvm_state;
ba9bc59e
JK		 1852
1853 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1854 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1855 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1856 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1857 } else {
1858 *eax = 0;
1859 *ebx = 0;
1860 *ecx = 0;
1861 *edx = 0;
1862 }
1863 break;
c6dc6f63
AP		 1864 case 0x80000000:
1865 *eax = env->cpuid_xlevel;
1866 *ebx = env->cpuid_vendor1;
1867 *edx = env->cpuid_vendor2;
1868 *ecx = env->cpuid_vendor3;
1869 break;
1870 case 0x80000001:
1871 *eax = env->cpuid_version;
1872 *ebx = 0;
1873 *ecx = env->cpuid_ext3_features;
1874 *edx = env->cpuid_ext2_features;
1875
1876 /* The Linux kernel checks for the CMPLegacy bit and
1877 * discards multiple thread information if it is set.
1878 * So dont set it here for Intel to make Linux guests happy.
1879 */
ce3960eb 1880 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 1881 uint32_t tebx, tecx, tedx;
1882 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1883 if (tebx != CPUID_VENDOR_INTEL_1 ||
1884 tedx != CPUID_VENDOR_INTEL_2 ||
1885 tecx != CPUID_VENDOR_INTEL_3) {
1886 *ecx |= 1 << 1; /* CmpLegacy bit */
1887 }
1888 }
c6dc6f63
AP		 1889 break;
1890 case 0x80000002:
1891 case 0x80000003:
1892 case 0x80000004:
1893 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1894 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1895 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1896 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1897 break;
1898 case 0x80000005:
1899 /* cache info (L1 cache) */
1900 *eax = 0x01ff01ff;
1901 *ebx = 0x01ff01ff;
1902 *ecx = 0x40020140;
1903 *edx = 0x40020140;
1904 break;
1905 case 0x80000006:
1906 /* cache info (L2 cache) */
1907 *eax = 0;
1908 *ebx = 0x42004200;
1909 *ecx = 0x02008140;
1910 *edx = 0;
1911 break;
1912 case 0x80000008:
1913 /* virtual & phys address size in low 2 bytes. */
1914/* XXX: This value must match the one used in the MMU code. */
1915 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1916 /* 64 bit processor */
1917/* XXX: The physical address space is limited to 42 bits in exec.c. */
1918 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1919 } else {
1920 if (env->cpuid_features & CPUID_PSE36)
1921 *eax = 0x00000024; /* 36 bits physical */
1922 else
1923 *eax = 0x00000020; /* 32 bits physical */
1924 }
1925 *ebx = 0;
1926 *ecx = 0;
1927 *edx = 0;
ce3960eb
AF		 1928 if (cs->nr_cores * cs->nr_threads > 1) {
1929 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 1930 }
1931 break;
1932 case 0x8000000A:
9f3fb565
EH		 1933 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1934 *eax = 0x00000001; /* SVM Revision */
1935 *ebx = 0x00000010; /* nr of ASIDs */
1936 *ecx = 0;
1937 *edx = env->cpuid_svm_features; /* optional features */
1938 } else {
1939 *eax = 0;
1940 *ebx = 0;
1941 *ecx = 0;
1942 *edx = 0;
1943 }
c6dc6f63 1944 break;
b3baa152
BW		 1945 case 0xC0000000:
1946 *eax = env->cpuid_xlevel2;
1947 *ebx = 0;
1948 *ecx = 0;
1949 *edx = 0;
1950 break;
1951 case 0xC0000001:
1952 /* Support for VIA CPU's CPUID instruction */
1953 *eax = env->cpuid_version;
1954 *ebx = 0;
1955 *ecx = 0;
1956 *edx = env->cpuid_ext4_features;
1957 break;
1958 case 0xC0000002:
1959 case 0xC0000003:
1960 case 0xC0000004:
1961 /* Reserved for the future, and now filled with zero */
1962 *eax = 0;
1963 *ebx = 0;
1964 *ecx = 0;
1965 *edx = 0;
1966 break;
c6dc6f63
AP		 1967 default:
1968 /* reserved values: zero */
1969 *eax = 0;
1970 *ebx = 0;
1971 *ecx = 0;
1972 *edx = 0;
1973 break;
1974 }
1975}
5fd2087a
AF		 1976
1977/* CPUClass::reset() */
1978static void x86_cpu_reset(CPUState *s)
1979{
1980 X86CPU *cpu = X86_CPU(s);
1981 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1982 CPUX86State *env = &cpu->env;
c1958aea
AF		 1983 int i;
1984
1985 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 1986 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
6fd2a026 1987 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
c1958aea 1988 }
5fd2087a
AF		 1989
1990 xcc->parent_reset(s);
1991
c1958aea
AF		 1992
1993 memset(env, 0, offsetof(CPUX86State, breakpoints));
1994
1995 tlb_flush(env, 1);
1996
1997 env->old_exception = -1;
1998
1999 /* init to reset state */
2000
2001#ifdef CONFIG_SOFTMMU
2002 env->hflags |= HF_SOFTMMU_MASK;
2003#endif
2004 env->hflags2 |= HF2_GIF_MASK;
2005
2006 cpu_x86_update_cr0(env, 0x60000010);
2007 env->a20_mask = ~0x0;
2008 env->smbase = 0x30000;
2009
2010 env->idt.limit = 0xffff;
2011 env->gdt.limit = 0xffff;
2012 env->ldt.limit = 0xffff;
2013 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2014 env->tr.limit = 0xffff;
2015 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2016
2017 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2018 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2019 DESC_R_MASK | DESC_A_MASK);
2020 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2021 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2022 DESC_A_MASK);
2023 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2024 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2025 DESC_A_MASK);
2026 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2027 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2028 DESC_A_MASK);
2029 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2030 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2031 DESC_A_MASK);
2032 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2033 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2034 DESC_A_MASK);
2035
2036 env->eip = 0xfff0;
2037 env->regs[R_EDX] = env->cpuid_version;
2038
2039 env->eflags = 0x2;
2040
2041 /* FPU init */
2042 for (i = 0; i < 8; i++) {
2043 env->fptags[i] = 1;
2044 }
2045 env->fpuc = 0x37f;
2046
2047 env->mxcsr = 0x1f80;
2048
2049 env->pat = 0x0007040600070406ULL;
2050 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2051
2052 memset(env->dr, 0, sizeof(env->dr));
2053 env->dr[6] = DR6_FIXED_1;
2054 env->dr[7] = DR7_FIXED_1;
2055 cpu_breakpoint_remove_all(env, BP_CPU);
2056 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 2057
2058#if !defined(CONFIG_USER_ONLY)
2059 /* We hard-wire the BSP to the first CPU. */
55e5c285 2060 if (s->cpu_index == 0) {
dd673288
IM		 2061 apic_designate_bsp(env->apic_state);
2062 }
2063
2064 env->halted = !cpu_is_bsp(cpu);
2065#endif
5fd2087a
AF		 2066}
2067
dd673288
IM		 2068#ifndef CONFIG_USER_ONLY
2069bool cpu_is_bsp(X86CPU *cpu)
2070{
2071 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2072}
65dee380
IM		 2073
2074/* TODO: remove me, when reset over QOM tree is implemented */
2075static void x86_cpu_machine_reset_cb(void *opaque)
2076{
2077 X86CPU *cpu = opaque;
2078 cpu_reset(CPU(cpu));
2079}
dd673288
IM		 2080#endif
2081
de024815
AF		 2082static void mce_init(X86CPU *cpu)
2083{
2084 CPUX86State *cenv = &cpu->env;
2085 unsigned int bank;
2086
2087 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2088 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2089 (CPUID_MCE | CPUID_MCA)) {
2090 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2091 cenv->mcg_ctl = ~(uint64_t)0;
2092 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2093 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2094 }
2095 }
2096}
2097
bdeec802
IM		 2098#define MSI_ADDR_BASE 0xfee00000
2099
2100#ifndef CONFIG_USER_ONLY
2101static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2102{
2103 static int apic_mapped;
2104 CPUX86State *env = &cpu->env;
449994eb 2105 APICCommonState *apic;
bdeec802
IM		 2106 const char *apic_type = "apic";
2107
2108 if (kvm_irqchip_in_kernel()) {
2109 apic_type = "kvm-apic";
2110 } else if (xen_enabled()) {
2111 apic_type = "xen-apic";
2112 }
2113
2114 env->apic_state = qdev_try_create(NULL, apic_type);
2115 if (env->apic_state == NULL) {
2116 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2117 return;
2118 }
2119
2120 object_property_add_child(OBJECT(cpu), "apic",
2121 OBJECT(env->apic_state), NULL);
2122 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2123 /* TODO: convert to link<> */
449994eb 2124 apic = APIC_COMMON(env->apic_state);
60671e58 2125 apic->cpu = cpu;
bdeec802
IM		 2126
2127 if (qdev_init(env->apic_state)) {
2128 error_setg(errp, "APIC device '%s' could not be initialized",
2129 object_get_typename(OBJECT(env->apic_state)));
2130 return;
2131 }
2132
2133 /* XXX: mapping more APICs at the same memory location */
2134 if (apic_mapped == 0) {
2135 /* NOTE: the APIC is directly connected to the CPU - it is not
2136 on the global memory bus. */
2137 /* XXX: what if the base changes? */
1356b98d 2138 sysbus_mmio_map(SYS_BUS_DEVICE(env->apic_state), 0, MSI_ADDR_BASE);
bdeec802
IM		 2139 apic_mapped = 1;
2140 }
2141}
2142#endif
2143
7a059953
AF		 2144void x86_cpu_realize(Object *obj, Error **errp)
2145{
2146 X86CPU *cpu = X86_CPU(obj);
b34d12d1
IM		 2147 CPUX86State *env = &cpu->env;
2148
2149 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2150 env->cpuid_level = 7;
2151 }
7a059953 2152
9b15cd9e
IM		 2153 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2154 * CPUID[1].EDX.
2155 */
2156 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2157 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2158 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2159 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2160 env->cpuid_ext2_features |= (env->cpuid_features
2161 & CPUID_EXT2_AMD_ALIASES);
2162 }
2163
4586f157
IM		 2164 if (!kvm_enabled()) {
2165 env->cpuid_features &= TCG_FEATURES;
2166 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2167 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2168#ifdef TARGET_X86_64
2169 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2170#endif
2171 );
2172 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2173 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2174 } else {
2175#ifdef CONFIG_KVM
2176 filter_features_for_kvm(cpu);
2177#endif
5ec01c2e
IM		 2178 if (check_cpuid && kvm_check_features_against_host(cpu)
2179 && enforce_cpuid) {
2180 error_setg(errp, "Host's CPU doesn't support requested features");
2181 return;
2182 }
4586f157
IM		 2183 }
2184
65dee380
IM		 2185#ifndef CONFIG_USER_ONLY
2186 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802
IM		 2187
2188 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2189 x86_cpu_apic_init(cpu, errp);
2190 if (error_is_set(errp)) {
2191 return;
2192 }
2193 }
65dee380
IM		 2194#endif
2195
7a059953
AF		 2196 mce_init(cpu);
2197 qemu_init_vcpu(&cpu->env);
65dee380 2198 cpu_reset(CPU(cpu));
7a059953
AF		 2199}
2200
8932cfdf
EH		 2201/* Enables contiguous-apic-ID mode, for compatibility */
2202static bool compat_apic_id_mode;
2203
2204void enable_compat_apic_id_mode(void)
2205{
2206 compat_apic_id_mode = true;
2207}
2208
cb41bad3
EH		 2209/* Calculates initial APIC ID for a specific CPU index
2210 *
2211 * Currently we need to be able to calculate the APIC ID from the CPU index
2212 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2213 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2214 * all CPUs up to max_cpus.
2215 */
2216uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2217{
8932cfdf
EH		 2218 uint32_t correct_id;
2219 static bool warned;
2220
2221 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2222 if (compat_apic_id_mode) {
2223 if (cpu_index != correct_id && !warned) {
2224 error_report("APIC IDs set in compatibility mode, "
2225 "CPU topology won't match the configuration");
2226 warned = true;
2227 }
2228 return cpu_index;
2229 } else {
2230 return correct_id;
2231 }
cb41bad3
EH		 2232}
2233
de024815
AF		 2234static void x86_cpu_initfn(Object *obj)
2235{
55e5c285 2236 CPUState *cs = CPU(obj);
de024815
AF		 2237 X86CPU *cpu = X86_CPU(obj);
2238 CPUX86State *env = &cpu->env;
d65e9815 2239 static int inited;
de024815
AF		 2240
2241 cpu_exec_init(env);
71ad61d3
AF		 2242
2243 object_property_add(obj, "family", "int",
95b8519d 2244 x86_cpuid_version_get_family,
71ad61d3 2245 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2246 object_property_add(obj, "model", "int",
67e30c83 2247 x86_cpuid_version_get_model,
c5291a4f 2248 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2249 object_property_add(obj, "stepping", "int",
35112e41 2250 x86_cpuid_version_get_stepping,
036e2222 2251 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2252 object_property_add(obj, "level", "int",
2253 x86_cpuid_get_level,
2254 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2255 object_property_add(obj, "xlevel", "int",
2256 x86_cpuid_get_xlevel,
2257 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2258 object_property_add_str(obj, "vendor",
2259 x86_cpuid_get_vendor,
2260 x86_cpuid_set_vendor, NULL);
938d4c25 2261 object_property_add_str(obj, "model-id",
63e886eb 2262 x86_cpuid_get_model_id,
938d4c25 2263 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2264 object_property_add(obj, "tsc-frequency", "int",
2265 x86_cpuid_get_tsc_freq,
2266 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 2267
cb41bad3 2268 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815
IM		 2269
2270 /* init various static tables used in TCG mode */
2271 if (tcg_enabled() && !inited) {
2272 inited = 1;
2273 optimize_flags_init();
2274#ifndef CONFIG_USER_ONLY
2275 cpu_set_debug_excp_handler(breakpoint_handler);
2276#endif
2277 }
de024815
AF		 2278}
2279
5fd2087a
AF		 2280static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2281{
2282 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2283 CPUClass *cc = CPU_CLASS(oc);
2284
2285 xcc->parent_reset = cc->reset;
2286 cc->reset = x86_cpu_reset;
2287}
2288
2289static const TypeInfo x86_cpu_type_info = {
2290 .name = TYPE_X86_CPU,
2291 .parent = TYPE_CPU,
2292 .instance_size = sizeof(X86CPU),
de024815 2293 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2294 .abstract = false,
2295 .class_size = sizeof(X86CPUClass),
2296 .class_init = x86_cpu_common_class_init,
2297};
2298
2299static void x86_cpu_register_types(void)
2300{
2301 type_register_static(&x86_cpu_type_info);
2302}
2303
2304type_init(x86_cpu_register_types)
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