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KVM: SVM: Implement MMU helper functions for Nested Nested Paging
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
221d059d 7 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
6aa8b732 34
63d1142f 35#include <asm/virtext.h>
229456fc 36#include "trace.h"
63d1142f 37
4ecac3fd
AK		 38#define __ex(x) __kvm_handle_fault_on_reboot(x)
39
6aa8b732
AK		 40MODULE_AUTHOR("Qumranet");
41MODULE_LICENSE("GPL");
42
43#define IOPM_ALLOC_ORDER 2
44#define MSRPM_ALLOC_ORDER 1
45
6aa8b732
AK		 46#define SEG_TYPE_LDT 2
47#define SEG_TYPE_BUSY_TSS16 3
48
6bc31bdc
AP		 49#define SVM_FEATURE_NPT (1 << 0)
50#define SVM_FEATURE_LBRV (1 << 1)
51#define SVM_FEATURE_SVML (1 << 2)
52#define SVM_FEATURE_NRIP (1 << 3)
53#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 54
410e4d57
JR		 55#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
56#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
57#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
58
24e09cbf
JR		 59#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
60
67ec6607
JR		 61static bool erratum_383_found __read_mostly;
62
6c8166a7
AK		 63static const u32 host_save_user_msrs[] = {
64#ifdef CONFIG_X86_64
65 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
66 MSR_FS_BASE,
67#endif
68 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
69};
70
71#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
72
73struct kvm_vcpu;
74
e6aa9abd
JR		 75struct nested_state {
76 struct vmcb *hsave;
77 u64 hsave_msr;
4a810181 78 u64 vm_cr_msr;
e6aa9abd
JR		 79 u64 vmcb;
80
81 /* These are the merged vectors */
82 u32 *msrpm;
83
84 /* gpa pointers to the real vectors */
85 u64 vmcb_msrpm;
ce2ac085 86 u64 vmcb_iopm;
aad42c64 87
cd3ff653
JR		 88 /* A VMEXIT is required but not yet emulated */
89 bool exit_required;
90
cda00082
JR		 91 /*
92 * If we vmexit during an instruction emulation we need this to restore
93 * the l1 guest rip after the emulation
94 */
95 unsigned long vmexit_rip;
96 unsigned long vmexit_rsp;
97 unsigned long vmexit_rax;
98
aad42c64
JR		 99 /* cache for intercepts of the guest */
100 u16 intercept_cr_read;
101 u16 intercept_cr_write;
102 u16 intercept_dr_read;
103 u16 intercept_dr_write;
104 u32 intercept_exceptions;
105 u64 intercept;
106
5bd2edc3
JR		 107 /* Nested Paging related state */
108 u64 nested_cr3;
e6aa9abd
JR		 109};
110
323c3d80
JR		 111#define MSRPM_OFFSETS 16
112static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
113
6c8166a7
AK		 114struct vcpu_svm {
115 struct kvm_vcpu vcpu;
116 struct vmcb *vmcb;
117 unsigned long vmcb_pa;
118 struct svm_cpu_data *svm_data;
119 uint64_t asid_generation;
120 uint64_t sysenter_esp;
121 uint64_t sysenter_eip;
122
123 u64 next_rip;
124
125 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
126 u64 host_gs_base;
6c8166a7
AK		 127
128 u32 *msrpm;
6c8166a7 129
e6aa9abd 130 struct nested_state nested;
6be7d306
JK		 131
132 bool nmi_singlestep;
66b7138f
JK		 133
134 unsigned int3_injected;
135 unsigned long int3_rip;
6c8166a7
AK		 136};
137
455716fa
JR		 138#define MSR_INVALID 0xffffffffU
139
ac72a9b7
JR		 140static struct svm_direct_access_msrs {
141 u32 index; /* Index of the MSR */
142 bool always; /* True if intercept is always on */
143} direct_access_msrs[] = {
8c06585d 144 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 145 { .index = MSR_IA32_SYSENTER_CS, .always = true },
146#ifdef CONFIG_X86_64
147 { .index = MSR_GS_BASE, .always = true },
148 { .index = MSR_FS_BASE, .always = true },
149 { .index = MSR_KERNEL_GS_BASE, .always = true },
150 { .index = MSR_LSTAR, .always = true },
151 { .index = MSR_CSTAR, .always = true },
152 { .index = MSR_SYSCALL_MASK, .always = true },
153#endif
154 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
155 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
156 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
157 { .index = MSR_IA32_LASTINTTOIP, .always = false },
158 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 159};
160
709ddebf
JR		 161/* enable NPT for AMD64 and X86 with PAE */
162#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
163static bool npt_enabled = true;
164#else
e0231715 165static bool npt_enabled;
709ddebf 166#endif
6c7dac72
JR		 167static int npt = 1;
168
169module_param(npt, int, S_IRUGO);
e3da3acd 170
4b6e4dca 171static int nested = 1;
236de055
AG		 172module_param(nested, int, S_IRUGO);
173
44874f84 174static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 175static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 176
410e4d57 177static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 178static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 179static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 180static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
181 bool has_error_code, u32 error_code);
182
a2fa3e9f
GH		 183static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
184{
fb3f0f51 185 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 186}
187
3d6368ef
AG		 188static inline bool is_nested(struct vcpu_svm *svm)
189{
e6aa9abd 190 return svm->nested.vmcb;
3d6368ef
AG		 191}
192
2af9194d
JR		 193static inline void enable_gif(struct vcpu_svm *svm)
194{
195 svm->vcpu.arch.hflags |= HF_GIF_MASK;
196}
197
198static inline void disable_gif(struct vcpu_svm *svm)
199{
200 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
201}
202
203static inline bool gif_set(struct vcpu_svm *svm)
204{
205 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
206}
207
4866d5e3 208static unsigned long iopm_base;
6aa8b732
AK		 209
210struct kvm_ldttss_desc {
211 u16 limit0;
212 u16 base0;
e0231715
JR		 213 unsigned base1:8, type:5, dpl:2, p:1;
214 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 215 u32 base3;
216 u32 zero1;
217} __attribute__((packed));
218
219struct svm_cpu_data {
220 int cpu;
221
5008fdf5
AK		 222 u64 asid_generation;
223 u32 max_asid;
224 u32 next_asid;
6aa8b732
AK		 225 struct kvm_ldttss_desc *tss_desc;
226
227 struct page *save_area;
228};
229
230static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 231static uint32_t svm_features;
6aa8b732
AK		 232
233struct svm_init_data {
234 int cpu;
235 int r;
236};
237
238static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
239
9d8f549d 240#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 241#define MSRS_RANGE_SIZE 2048
242#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
243
455716fa
JR		 244static u32 svm_msrpm_offset(u32 msr)
245{
246 u32 offset;
247 int i;
248
249 for (i = 0; i < NUM_MSR_MAPS; i++) {
250 if (msr < msrpm_ranges[i] ||
251 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
252 continue;
253
254 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
255 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
256
257 /* Now we have the u8 offset - but need the u32 offset */
258 return offset / 4;
259 }
260
261 /* MSR not in any range */
262 return MSR_INVALID;
263}
264
6aa8b732
AK		 265#define MAX_INST_SIZE 15
266
80b7706e
JR		 267static inline u32 svm_has(u32 feat)
268{
269 return svm_features & feat;
270}
271
6aa8b732
AK		 272static inline void clgi(void)
273{
4ecac3fd 274 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 275}
276
277static inline void stgi(void)
278{
4ecac3fd 279 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 280}
281
282static inline void invlpga(unsigned long addr, u32 asid)
283{
e0231715 284 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 285}
286
6aa8b732
AK		 287static inline void force_new_asid(struct kvm_vcpu *vcpu)
288{
a2fa3e9f 289 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 290}
291
292static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
293{
294 force_new_asid(vcpu);
295}
296
297static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
298{
6dc696d4 299 vcpu->arch.efer = efer;
709ddebf 300 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 301 efer &= ~EFER_LME;
6aa8b732 302
9962d032 303 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
6aa8b732
AK		 304}
305
6aa8b732
AK		 306static int is_external_interrupt(u32 info)
307{
308 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
309 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
310}
311
2809f5d2
GC		 312static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
313{
314 struct vcpu_svm *svm = to_svm(vcpu);
315 u32 ret = 0;
316
317 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 318 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 319 return ret & mask;
320}
321
322static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
323{
324 struct vcpu_svm *svm = to_svm(vcpu);
325
326 if (mask == 0)
327 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
328 else
329 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
330
331}
332
6aa8b732
AK		 333static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
334{
a2fa3e9f
GH		 335 struct vcpu_svm *svm = to_svm(vcpu);
336
6bc31bdc
AP		 337 if (svm->vmcb->control.next_rip != 0)
338 svm->next_rip = svm->vmcb->control.next_rip;
339
a2fa3e9f 340 if (!svm->next_rip) {
851ba692 341 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 342 EMULATE_DONE)
343 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 344 return;
345 }
5fdbf976
MT		 346 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
347 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
348 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 349
5fdbf976 350 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 351 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 352}
353
116a4752 354static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 355 bool has_error_code, u32 error_code,
356 bool reinject)
116a4752
JK		 357{
358 struct vcpu_svm *svm = to_svm(vcpu);
359
e0231715
JR		 360 /*
361 * If we are within a nested VM we'd better #VMEXIT and let the guest
362 * handle the exception
363 */
ce7ddec4
JR		 364 if (!reinject &&
365 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 366 return;
367
66b7138f
JK		 368 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
369 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
370
371 /*
372 * For guest debugging where we have to reinject #BP if some
373 * INT3 is guest-owned:
374 * Emulate nRIP by moving RIP forward. Will fail if injection
375 * raises a fault that is not intercepted. Still better than
376 * failing in all cases.
377 */
378 skip_emulated_instruction(&svm->vcpu);
379 rip = kvm_rip_read(&svm->vcpu);
380 svm->int3_rip = rip + svm->vmcb->save.cs.base;
381 svm->int3_injected = rip - old_rip;
382 }
383
116a4752
JK		 384 svm->vmcb->control.event_inj = nr
385 | SVM_EVTINJ_VALID
386 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
387 | SVM_EVTINJ_TYPE_EXEPT;
388 svm->vmcb->control.event_inj_err = error_code;
389}
390
67ec6607
JR		 391static void svm_init_erratum_383(void)
392{
393 u32 low, high;
394 int err;
395 u64 val;
396
1be85a6d 397 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 398 return;
399
400 /* Use _safe variants to not break nested virtualization */
401 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
402 if (err)
403 return;
404
405 val |= (1ULL << 47);
406
407 low = lower_32_bits(val);
408 high = upper_32_bits(val);
409
410 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
411
412 erratum_383_found = true;
413}
414
6aa8b732
AK		 415static int has_svm(void)
416{
63d1142f 417 const char *msg;
6aa8b732 418
63d1142f 419 if (!cpu_has_svm(&msg)) {
ff81ff10 420 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 421 return 0;
422 }
423
6aa8b732
AK		 424 return 1;
425}
426
427static void svm_hardware_disable(void *garbage)
428{
2c8dceeb 429 cpu_svm_disable();
6aa8b732
AK		 430}
431
10474ae8 432static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 433{
434
0fe1e009 435 struct svm_cpu_data *sd;
6aa8b732 436 uint64_t efer;
89a27f4d 437 struct desc_ptr gdt_descr;
6aa8b732
AK		 438 struct desc_struct *gdt;
439 int me = raw_smp_processor_id();
440
10474ae8
AG		 441 rdmsrl(MSR_EFER, efer);
442 if (efer & EFER_SVME)
443 return -EBUSY;
444
6aa8b732 445 if (!has_svm()) {
e6732a5a
ZA		 446 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
447 me);
10474ae8 448 return -EINVAL;
6aa8b732 449 }
0fe1e009 450 sd = per_cpu(svm_data, me);
6aa8b732 451
0fe1e009 452 if (!sd) {
e6732a5a 453 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 454 me);
10474ae8 455 return -EINVAL;
6aa8b732
AK		 456 }
457
0fe1e009
TH		 458 sd->asid_generation = 1;
459 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
460 sd->next_asid = sd->max_asid + 1;
6aa8b732 461
d6ab1ed4 462 native_store_gdt(&gdt_descr);
89a27f4d 463 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 464 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 465
9962d032 466 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 467
d0316554 468 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 469
67ec6607
JR		 470 svm_init_erratum_383();
471
10474ae8 472 return 0;
6aa8b732
AK		 473}
474
0da1db75
JR		 475static void svm_cpu_uninit(int cpu)
476{
0fe1e009 477 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 478
0fe1e009 479 if (!sd)
0da1db75
JR		 480 return;
481
482 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 483 __free_page(sd->save_area);
484 kfree(sd);
0da1db75
JR		 485}
486
6aa8b732
AK		 487static int svm_cpu_init(int cpu)
488{
0fe1e009 489 struct svm_cpu_data *sd;
6aa8b732
AK		 490 int r;
491
0fe1e009
TH		 492 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
493 if (!sd)
6aa8b732 494 return -ENOMEM;
0fe1e009
TH		 495 sd->cpu = cpu;
496 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 497 r = -ENOMEM;
0fe1e009 498 if (!sd->save_area)
6aa8b732
AK		 499 goto err_1;
500
0fe1e009 501 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 502
503 return 0;
504
505err_1:
0fe1e009 506 kfree(sd);
6aa8b732
AK		 507 return r;
508
509}
510
ac72a9b7
JR		 511static bool valid_msr_intercept(u32 index)
512{
513 int i;
514
515 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
516 if (direct_access_msrs[i].index == index)
517 return true;
518
519 return false;
520}
521
bfc733a7
RR		 522static void set_msr_interception(u32 *msrpm, unsigned msr,
523 int read, int write)
6aa8b732 524{
455716fa
JR		 525 u8 bit_read, bit_write;
526 unsigned long tmp;
527 u32 offset;
6aa8b732 528
ac72a9b7
JR		 529 /*
530 * If this warning triggers extend the direct_access_msrs list at the
531 * beginning of the file
532 */
533 WARN_ON(!valid_msr_intercept(msr));
534
455716fa
JR		 535 offset = svm_msrpm_offset(msr);
536 bit_read = 2 * (msr & 0x0f);
537 bit_write = 2 * (msr & 0x0f) + 1;
538 tmp = msrpm[offset];
539
540 BUG_ON(offset == MSR_INVALID);
541
542 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
543 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
544
545 msrpm[offset] = tmp;
6aa8b732
AK		 546}
547
f65c229c 548static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 549{
550 int i;
551
f65c229c
JR		 552 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
553
ac72a9b7
JR		 554 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
555 if (!direct_access_msrs[i].always)
556 continue;
557
558 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
559 }
f65c229c
JR		 560}
561
323c3d80
JR		 562static void add_msr_offset(u32 offset)
563{
564 int i;
565
566 for (i = 0; i < MSRPM_OFFSETS; ++i) {
567
568 /* Offset already in list? */
569 if (msrpm_offsets[i] == offset)
bfc733a7 570 return;
323c3d80
JR		 571
572 /* Slot used by another offset? */
573 if (msrpm_offsets[i] != MSR_INVALID)
574 continue;
575
576 /* Add offset to list */
577 msrpm_offsets[i] = offset;
578
579 return;
6aa8b732 580 }
323c3d80
JR		 581
582 /*
583 * If this BUG triggers the msrpm_offsets table has an overflow. Just
584 * increase MSRPM_OFFSETS in this case.
585 */
bfc733a7 586 BUG();
6aa8b732
AK		 587}
588
323c3d80 589static void init_msrpm_offsets(void)
f65c229c 590{
323c3d80 591 int i;
f65c229c 592
323c3d80
JR		 593 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
594
595 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
596 u32 offset;
597
598 offset = svm_msrpm_offset(direct_access_msrs[i].index);
599 BUG_ON(offset == MSR_INVALID);
600
601 add_msr_offset(offset);
602 }
f65c229c
JR		 603}
604
24e09cbf
JR		 605static void svm_enable_lbrv(struct vcpu_svm *svm)
606{
607 u32 *msrpm = svm->msrpm;
608
609 svm->vmcb->control.lbr_ctl = 1;
610 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
611 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
612 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
613 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
614}
615
616static void svm_disable_lbrv(struct vcpu_svm *svm)
617{
618 u32 *msrpm = svm->msrpm;
619
620 svm->vmcb->control.lbr_ctl = 0;
621 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
622 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
623 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
624 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
625}
626
6aa8b732
AK		 627static __init int svm_hardware_setup(void)
628{
629 int cpu;
630 struct page *iopm_pages;
f65c229c 631 void *iopm_va;
6aa8b732
AK		 632 int r;
633
6aa8b732
AK		 634 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
635
636 if (!iopm_pages)
637 return -ENOMEM;
c8681339
AL		 638
639 iopm_va = page_address(iopm_pages);
640 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 641 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
642
323c3d80
JR		 643 init_msrpm_offsets();
644
50a37eb4
JR		 645 if (boot_cpu_has(X86_FEATURE_NX))
646 kvm_enable_efer_bits(EFER_NX);
647
1b2fd70c
AG		 648 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
649 kvm_enable_efer_bits(EFER_FFXSR);
650
236de055
AG		 651 if (nested) {
652 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 653 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 654 }
655
3230bb47 656 for_each_possible_cpu(cpu) {
6aa8b732
AK		 657 r = svm_cpu_init(cpu);
658 if (r)
f65c229c 659 goto err;
6aa8b732 660 }
33bd6a0b
JR		 661
662 svm_features = cpuid_edx(SVM_CPUID_FUNC);
663
e3da3acd
JR		 664 if (!svm_has(SVM_FEATURE_NPT))
665 npt_enabled = false;
666
6c7dac72
JR		 667 if (npt_enabled && !npt) {
668 printk(KERN_INFO "kvm: Nested Paging disabled\n");
669 npt_enabled = false;
670 }
671
18552672 672 if (npt_enabled) {
e3da3acd 673 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 674 kvm_enable_tdp();
5f4cb662
JR		 675 } else
676 kvm_disable_tdp();
e3da3acd 677
6aa8b732
AK		 678 return 0;
679
f65c229c 680err:
6aa8b732
AK		 681 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
682 iopm_base = 0;
683 return r;
684}
685
686static __exit void svm_hardware_unsetup(void)
687{
0da1db75
JR		 688 int cpu;
689
3230bb47 690 for_each_possible_cpu(cpu)
0da1db75
JR		 691 svm_cpu_uninit(cpu);
692
6aa8b732 693 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 694 iopm_base = 0;
6aa8b732
AK		 695}
696
697static void init_seg(struct vmcb_seg *seg)
698{
699 seg->selector = 0;
700 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 701 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 702 seg->limit = 0xffff;
703 seg->base = 0;
704}
705
706static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
707{
708 seg->selector = 0;
709 seg->attrib = SVM_SELECTOR_P_MASK | type;
710 seg->limit = 0xffff;
711 seg->base = 0;
712}
713
f4e1b3c8
ZA		 714static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
715{
716 struct vcpu_svm *svm = to_svm(vcpu);
717 u64 g_tsc_offset = 0;
718
719 if (is_nested(svm)) {
720 g_tsc_offset = svm->vmcb->control.tsc_offset -
721 svm->nested.hsave->control.tsc_offset;
722 svm->nested.hsave->control.tsc_offset = offset;
723 }
724
725 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
726}
727
e48672fa
ZA		 728static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
729{
730 struct vcpu_svm *svm = to_svm(vcpu);
731
732 svm->vmcb->control.tsc_offset += adjustment;
733 if (is_nested(svm))
734 svm->nested.hsave->control.tsc_offset += adjustment;
735}
736
e6101a96 737static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 738{
e6101a96
JR		 739 struct vmcb_control_area *control = &svm->vmcb->control;
740 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 741
bff78274
AK		 742 svm->vcpu.fpu_active = 1;
743
e0231715 744 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 745 INTERCEPT_CR3_MASK |
649d6864 746 INTERCEPT_CR4_MASK;
6aa8b732 747
e0231715 748 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 749 INTERCEPT_CR3_MASK |
80a8119c
AK		 750 INTERCEPT_CR4_MASK |
751 INTERCEPT_CR8_MASK;
6aa8b732 752
e0231715 753 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 754 INTERCEPT_DR1_MASK |
755 INTERCEPT_DR2_MASK |
727f5a23
JK		 756 INTERCEPT_DR3_MASK |
757 INTERCEPT_DR4_MASK |
758 INTERCEPT_DR5_MASK |
759 INTERCEPT_DR6_MASK |
760 INTERCEPT_DR7_MASK;
6aa8b732 761
e0231715 762 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 763 INTERCEPT_DR1_MASK |
764 INTERCEPT_DR2_MASK |
765 INTERCEPT_DR3_MASK |
727f5a23 766 INTERCEPT_DR4_MASK |
6aa8b732 767 INTERCEPT_DR5_MASK |
727f5a23 768 INTERCEPT_DR6_MASK |
6aa8b732
AK		 769 INTERCEPT_DR7_MASK;
770
7aa81cc0 771 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 772 (1 << UD_VECTOR) |
773 (1 << MC_VECTOR);
6aa8b732
AK		 774
775
e0231715 776 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 777 (1ULL << INTERCEPT_NMI) |
0152527b 778 (1ULL << INTERCEPT_SMI) |
d225157b 779 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 780 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 781 (1ULL << INTERCEPT_INVD) |
6aa8b732 782 (1ULL << INTERCEPT_HLT) |
a7052897 783 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 784 (1ULL << INTERCEPT_INVLPGA) |
785 (1ULL << INTERCEPT_IOIO_PROT) |
786 (1ULL << INTERCEPT_MSR_PROT) |
787 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 788 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 789 (1ULL << INTERCEPT_VMRUN) |
790 (1ULL << INTERCEPT_VMMCALL) |
791 (1ULL << INTERCEPT_VMLOAD) |
792 (1ULL << INTERCEPT_VMSAVE) |
793 (1ULL << INTERCEPT_STGI) |
794 (1ULL << INTERCEPT_CLGI) |
916ce236 795 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 796 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 797 (1ULL << INTERCEPT_MONITOR) |
798 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 799
800 control->iopm_base_pa = iopm_base;
f65c229c 801 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 802 control->int_ctl = V_INTR_MASKING_MASK;
803
804 init_seg(&save->es);
805 init_seg(&save->ss);
806 init_seg(&save->ds);
807 init_seg(&save->fs);
808 init_seg(&save->gs);
809
810 save->cs.selector = 0xf000;
811 /* Executable/Readable Code Segment */
812 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
813 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
814 save->cs.limit = 0xffff;
d92899a0
AK		 815 /*
816 * cs.base should really be 0xffff0000, but vmx can't handle that, so
817 * be consistent with it.
818 *
819 * Replace when we have real mode working for vmx.
820 */
821 save->cs.base = 0xf0000;
6aa8b732
AK		 822
823 save->gdtr.limit = 0xffff;
824 save->idtr.limit = 0xffff;
825
826 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
827 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
828
eaa48512 829 svm_set_efer(&svm->vcpu, 0);
d77c26fc 830 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 831 save->dr7 = 0x400;
832 save->rflags = 2;
833 save->rip = 0x0000fff0;
5fdbf976 834 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 835
e0231715
JR		 836 /*
837 * This is the guest-visible cr0 value.
18fa000a 838 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 839 */
678041ad
MT		 840 svm->vcpu.arch.cr0 = 0;
841 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
18fa000a 842
66aee91a 843 save->cr4 = X86_CR4_PAE;
6aa8b732 844 /* rdx = ?? */
709ddebf
JR		 845
846 if (npt_enabled) {
847 /* Setup VMCB for Nested Paging */
848 control->nested_ctl = 1;
a7052897
MT		 849 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
850 (1ULL << INTERCEPT_INVLPG));
709ddebf 851 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 852 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
853 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 854 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 855 save->cr3 = 0;
856 save->cr4 = 0;
857 }
a79d2f18 858 force_new_asid(&svm->vcpu);
1371d904 859
e6aa9abd 860 svm->nested.vmcb = 0;
2af9194d
JR		 861 svm->vcpu.arch.hflags = 0;
862
565d0998
ML		 863 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
864 control->pause_filter_count = 3000;
865 control->intercept |= (1ULL << INTERCEPT_PAUSE);
866 }
867
2af9194d 868 enable_gif(svm);
6aa8b732
AK		 869}
870
e00c8cf2 871static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 872{
873 struct vcpu_svm *svm = to_svm(vcpu);
874
e6101a96 875 init_vmcb(svm);
70433389 876
c5af89b6 877 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 878 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 879 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
880 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 881 }
5fdbf976
MT		 882 vcpu->arch.regs_avail = ~0;
883 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 884
885 return 0;
04d2cc77
AK		 886}
887
fb3f0f51 888static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 889{
a2fa3e9f 890 struct vcpu_svm *svm;
6aa8b732 891 struct page *page;
f65c229c 892 struct page *msrpm_pages;
b286d5d8 893 struct page *hsave_page;
3d6368ef 894 struct page *nested_msrpm_pages;
fb3f0f51 895 int err;
6aa8b732 896
c16f862d 897 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 898 if (!svm) {
899 err = -ENOMEM;
900 goto out;
901 }
902
903 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
904 if (err)
905 goto free_svm;
906
b7af4043 907 err = -ENOMEM;
6aa8b732 908 page = alloc_page(GFP_KERNEL);
b7af4043 909 if (!page)
fb3f0f51 910 goto uninit;
6aa8b732 911
f65c229c
JR		 912 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
913 if (!msrpm_pages)
b7af4043 914 goto free_page1;
3d6368ef
AG		 915
916 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
917 if (!nested_msrpm_pages)
b7af4043 918 goto free_page2;
f65c229c 919
b286d5d8
AG		 920 hsave_page = alloc_page(GFP_KERNEL);
921 if (!hsave_page)
b7af4043
TY		 922 goto free_page3;
923
e6aa9abd 924 svm->nested.hsave = page_address(hsave_page);
b286d5d8 925
b7af4043
TY		 926 svm->msrpm = page_address(msrpm_pages);
927 svm_vcpu_init_msrpm(svm->msrpm);
928
e6aa9abd 929 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 930 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 931
a2fa3e9f
GH		 932 svm->vmcb = page_address(page);
933 clear_page(svm->vmcb);
934 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
935 svm->asid_generation = 0;
e6101a96 936 init_vmcb(svm);
99e3e30a 937 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 938
10ab25cd
JK		 939 err = fx_init(&svm->vcpu);
940 if (err)
941 goto free_page4;
942
ad312c7c 943 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 944 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 945 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 946
fb3f0f51 947 return &svm->vcpu;
36241b8c 948
10ab25cd
JK		 949free_page4:
950 __free_page(hsave_page);
b7af4043
TY		 951free_page3:
952 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
953free_page2:
954 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
955free_page1:
956 __free_page(page);
fb3f0f51
RR		 957uninit:
958 kvm_vcpu_uninit(&svm->vcpu);
959free_svm:
a4770347 960 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 961out:
962 return ERR_PTR(err);
6aa8b732
AK		 963}
964
965static void svm_free_vcpu(struct kvm_vcpu *vcpu)
966{
a2fa3e9f
GH		 967 struct vcpu_svm *svm = to_svm(vcpu);
968
fb3f0f51 969 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 970 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 971 __free_page(virt_to_page(svm->nested.hsave));
972 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 973 kvm_vcpu_uninit(vcpu);
a4770347 974 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 975}
976
15ad7146 977static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 978{
a2fa3e9f 979 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 980 int i;
0cc5064d 981
0cc5064d 982 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 983 svm->asid_generation = 0;
0cc5064d 984 }
94dfbdb3
AL		 985
986 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 987 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 988}
989
990static void svm_vcpu_put(struct kvm_vcpu *vcpu)
991{
a2fa3e9f 992 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 993 int i;
994
e1beb1d3 995 ++vcpu->stat.host_state_reload;
94dfbdb3 996 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 997 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 998}
999
6aa8b732
AK		 1000static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1001{
a2fa3e9f 1002 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 1003}
1004
1005static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1006{
a2fa3e9f 1007 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1008}
1009
6de4f3ad
AK		 1010static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1011{
1012 switch (reg) {
1013 case VCPU_EXREG_PDPTR:
1014 BUG_ON(!npt_enabled);
ff03a073 1015 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
6de4f3ad
AK		 1016 break;
1017 default:
1018 BUG();
1019 }
1020}
1021
f0b85051
AG		 1022static void svm_set_vintr(struct vcpu_svm *svm)
1023{
1024 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1025}
1026
1027static void svm_clear_vintr(struct vcpu_svm *svm)
1028{
1029 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1030}
1031
6aa8b732
AK		 1032static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1033{
a2fa3e9f 1034 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1035
1036 switch (seg) {
1037 case VCPU_SREG_CS: return &save->cs;
1038 case VCPU_SREG_DS: return &save->ds;
1039 case VCPU_SREG_ES: return &save->es;
1040 case VCPU_SREG_FS: return &save->fs;
1041 case VCPU_SREG_GS: return &save->gs;
1042 case VCPU_SREG_SS: return &save->ss;
1043 case VCPU_SREG_TR: return &save->tr;
1044 case VCPU_SREG_LDTR: return &save->ldtr;
1045 }
1046 BUG();
8b6d44c7 1047 return NULL;
6aa8b732
AK		 1048}
1049
1050static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1051{
1052 struct vmcb_seg *s = svm_seg(vcpu, seg);
1053
1054 return s->base;
1055}
1056
1057static void svm_get_segment(struct kvm_vcpu *vcpu,
1058 struct kvm_segment *var, int seg)
1059{
1060 struct vmcb_seg *s = svm_seg(vcpu, seg);
1061
1062 var->base = s->base;
1063 var->limit = s->limit;
1064 var->selector = s->selector;
1065 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1066 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1067 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1068 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1069 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1070 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1071 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1072 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1073
e0231715
JR		 1074 /*
1075 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1076 * for cross vendor migration purposes by "not present"
1077 */
1078 var->unusable = !var->present || (var->type == 0);
1079
1fbdc7a5
AP		 1080 switch (seg) {
1081 case VCPU_SREG_CS:
1082 /*
1083 * SVM always stores 0 for the 'G' bit in the CS selector in
1084 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1085 * Intel's VMENTRY has a check on the 'G' bit.
1086 */
25022acc 1087 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1088 break;
1089 case VCPU_SREG_TR:
1090 /*
1091 * Work around a bug where the busy flag in the tr selector
1092 * isn't exposed
1093 */
c0d09828 1094 var->type |= 0x2;
1fbdc7a5
AP		 1095 break;
1096 case VCPU_SREG_DS:
1097 case VCPU_SREG_ES:
1098 case VCPU_SREG_FS:
1099 case VCPU_SREG_GS:
1100 /*
1101 * The accessed bit must always be set in the segment
1102 * descriptor cache, although it can be cleared in the
1103 * descriptor, the cached bit always remains at 1. Since
1104 * Intel has a check on this, set it here to support
1105 * cross-vendor migration.
1106 */
1107 if (!var->unusable)
1108 var->type |= 0x1;
1109 break;
b586eb02 1110 case VCPU_SREG_SS:
e0231715
JR		 1111 /*
1112 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1113 * descriptor is left as 1, although the whole segment has
1114 * been made unusable. Clear it here to pass an Intel VMX
1115 * entry check when cross vendor migrating.
1116 */
1117 if (var->unusable)
1118 var->db = 0;
1119 break;
1fbdc7a5 1120 }
6aa8b732
AK		 1121}
1122
2e4d2653
IE		 1123static int svm_get_cpl(struct kvm_vcpu *vcpu)
1124{
1125 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1126
1127 return save->cpl;
1128}
1129
89a27f4d 1130static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1131{
a2fa3e9f
GH		 1132 struct vcpu_svm *svm = to_svm(vcpu);
1133
89a27f4d
GN		 1134 dt->size = svm->vmcb->save.idtr.limit;
1135 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1136}
1137
89a27f4d 1138static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1139{
a2fa3e9f
GH		 1140 struct vcpu_svm *svm = to_svm(vcpu);
1141
89a27f4d
GN		 1142 svm->vmcb->save.idtr.limit = dt->size;
1143 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1144}
1145
89a27f4d 1146static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1147{
a2fa3e9f
GH		 1148 struct vcpu_svm *svm = to_svm(vcpu);
1149
89a27f4d
GN		 1150 dt->size = svm->vmcb->save.gdtr.limit;
1151 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1152}
1153
89a27f4d 1154static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1155{
a2fa3e9f
GH		 1156 struct vcpu_svm *svm = to_svm(vcpu);
1157
89a27f4d
GN		 1158 svm->vmcb->save.gdtr.limit = dt->size;
1159 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1160}
1161
e8467fda
AK		 1162static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1163{
1164}
1165
25c4c276 1166static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1167{
1168}
1169
d225157b
AK		 1170static void update_cr0_intercept(struct vcpu_svm *svm)
1171{
66a562f7 1172 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1173 ulong gcr0 = svm->vcpu.arch.cr0;
1174 u64 *hcr0 = &svm->vmcb->save.cr0;
1175
1176 if (!svm->vcpu.fpu_active)
1177 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1178 else
1179 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1180 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1181
1182
1183 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1184 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1185 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1186 if (is_nested(svm)) {
1187 struct vmcb *hsave = svm->nested.hsave;
1188
1189 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1190 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1191 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1192 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1193 }
d225157b
AK		 1194 } else {
1195 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1196 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1197 if (is_nested(svm)) {
1198 struct vmcb *hsave = svm->nested.hsave;
1199
1200 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1201 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1202 }
d225157b
AK		 1203 }
1204}
1205
6aa8b732
AK		 1206static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1207{
a2fa3e9f
GH		 1208 struct vcpu_svm *svm = to_svm(vcpu);
1209
7f5d8b56
JR		 1210 if (is_nested(svm)) {
1211 /*
1212 * We are here because we run in nested mode, the host kvm
1213 * intercepts cr0 writes but the l1 hypervisor does not.
1214 * But the L1 hypervisor may intercept selective cr0 writes.
1215 * This needs to be checked here.
1216 */
1217 unsigned long old, new;
1218
1219 /* Remove bits that would trigger a real cr0 write intercept */
1220 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1221 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1222
1223 if (old == new) {
1224 /* cr0 write with ts and mp unchanged */
1225 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
cda00082
JR		 1226 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1227 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1228 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1229 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7f5d8b56 1230 return;
cda00082 1231 }
7f5d8b56
JR		 1232 }
1233 }
1234
05b3e0c2 1235#ifdef CONFIG_X86_64
f6801dff 1236 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1237 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1238 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1239 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1240 }
1241
d77c26fc 1242 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1243 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1244 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1245 }
1246 }
1247#endif
ad312c7c 1248 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1249
1250 if (!npt_enabled)
1251 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1252
1253 if (!vcpu->fpu_active)
334df50a 1254 cr0 |= X86_CR0_TS;
709ddebf
JR		 1255 /*
1256 * re-enable caching here because the QEMU bios
1257 * does not do it - this results in some delay at
1258 * reboot
1259 */
1260 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1261 svm->vmcb->save.cr0 = cr0;
d225157b 1262 update_cr0_intercept(svm);
6aa8b732
AK		 1263}
1264
1265static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1266{
6394b649 1267 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1268 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1269
1270 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1271 force_new_asid(vcpu);
6394b649 1272
ec077263
JR		 1273 vcpu->arch.cr4 = cr4;
1274 if (!npt_enabled)
1275 cr4 |= X86_CR4_PAE;
6394b649 1276 cr4 |= host_cr4_mce;
ec077263 1277 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1278}
1279
1280static void svm_set_segment(struct kvm_vcpu *vcpu,
1281 struct kvm_segment *var, int seg)
1282{
a2fa3e9f 1283 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1284 struct vmcb_seg *s = svm_seg(vcpu, seg);
1285
1286 s->base = var->base;
1287 s->limit = var->limit;
1288 s->selector = var->selector;
1289 if (var->unusable)
1290 s->attrib = 0;
1291 else {
1292 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1293 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1294 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1295 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1296 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1297 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1298 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1299 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1300 }
1301 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1302 svm->vmcb->save.cpl
1303 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1304 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1305
1306}
1307
44c11430 1308static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1309{
d0bfb940
JK		 1310 struct vcpu_svm *svm = to_svm(vcpu);
1311
d0bfb940
JK		 1312 svm->vmcb->control.intercept_exceptions &=
1313 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1314
6be7d306 1315 if (svm->nmi_singlestep)
44c11430
GN		 1316 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1317
d0bfb940
JK		 1318 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1319 if (vcpu->guest_debug &
1320 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1321 svm->vmcb->control.intercept_exceptions |=
1322 1 << DB_VECTOR;
1323 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1324 svm->vmcb->control.intercept_exceptions |=
1325 1 << BP_VECTOR;
1326 } else
1327 vcpu->guest_debug = 0;
44c11430
GN		 1328}
1329
355be0b9 1330static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1331{
44c11430
GN		 1332 struct vcpu_svm *svm = to_svm(vcpu);
1333
ae675ef0
JK		 1334 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1335 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1336 else
1337 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1338
355be0b9 1339 update_db_intercept(vcpu);
6aa8b732
AK		 1340}
1341
1342static void load_host_msrs(struct kvm_vcpu *vcpu)
1343{
94dfbdb3 1344#ifdef CONFIG_X86_64
a2fa3e9f 1345 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1346#endif
6aa8b732
AK		 1347}
1348
1349static void save_host_msrs(struct kvm_vcpu *vcpu)
1350{
94dfbdb3 1351#ifdef CONFIG_X86_64
a2fa3e9f 1352 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1353#endif
6aa8b732
AK		 1354}
1355
0fe1e009 1356static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1357{
0fe1e009
TH		 1358 if (sd->next_asid > sd->max_asid) {
1359 ++sd->asid_generation;
1360 sd->next_asid = 1;
a2fa3e9f 1361 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1362 }
1363
0fe1e009
TH		 1364 svm->asid_generation = sd->asid_generation;
1365 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1366}
1367
020df079 1368static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1369{
42dbaa5a 1370 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1371
020df079 1372 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1373}
1374
851ba692 1375static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1376{
6aa8b732
AK		 1377 u64 fault_address;
1378 u32 error_code;
6aa8b732 1379
a2fa3e9f
GH		 1380 fault_address = svm->vmcb->control.exit_info_2;
1381 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1382
229456fc 1383 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1384 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1385 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1386 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1387}
1388
851ba692 1389static int db_interception(struct vcpu_svm *svm)
d0bfb940 1390{
851ba692
AK		 1391 struct kvm_run *kvm_run = svm->vcpu.run;
1392
d0bfb940 1393 if (!(svm->vcpu.guest_debug &
44c11430 1394 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1395 !svm->nmi_singlestep) {
d0bfb940
JK		 1396 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1397 return 1;
1398 }
44c11430 1399
6be7d306
JK		 1400 if (svm->nmi_singlestep) {
1401 svm->nmi_singlestep = false;
44c11430
GN		 1402 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1403 svm->vmcb->save.rflags &=
1404 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1405 update_db_intercept(&svm->vcpu);
1406 }
1407
1408 if (svm->vcpu.guest_debug &
e0231715 1409 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1410 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1411 kvm_run->debug.arch.pc =
1412 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1413 kvm_run->debug.arch.exception = DB_VECTOR;
1414 return 0;
1415 }
1416
1417 return 1;
d0bfb940
JK		 1418}
1419
851ba692 1420static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1421{
851ba692
AK		 1422 struct kvm_run *kvm_run = svm->vcpu.run;
1423
d0bfb940
JK		 1424 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1425 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1426 kvm_run->debug.arch.exception = BP_VECTOR;
1427 return 0;
1428}
1429
851ba692 1430static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1431{
1432 int er;
1433
851ba692 1434 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1435 if (er != EMULATE_DONE)
7ee5d940 1436 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1437 return 1;
1438}
1439
6b52d186 1440static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1441{
6b52d186 1442 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1443 u32 excp;
1444
1445 if (is_nested(svm)) {
1446 u32 h_excp, n_excp;
1447
1448 h_excp = svm->nested.hsave->control.intercept_exceptions;
1449 n_excp = svm->nested.intercept_exceptions;
1450 h_excp &= ~(1 << NM_VECTOR);
1451 excp = h_excp | n_excp;
1452 } else {
1453 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1454 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1455 }
1456
1457 svm->vmcb->control.intercept_exceptions = excp;
1458
e756fc62 1459 svm->vcpu.fpu_active = 1;
d225157b 1460 update_cr0_intercept(svm);
6b52d186 1461}
a2fa3e9f 1462
6b52d186
AK		 1463static int nm_interception(struct vcpu_svm *svm)
1464{
1465 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1466 return 1;
7807fa6c
AL		 1467}
1468
67ec6607
JR		 1469static bool is_erratum_383(void)
1470{
1471 int err, i;
1472 u64 value;
1473
1474 if (!erratum_383_found)
1475 return false;
1476
1477 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1478 if (err)
1479 return false;
1480
1481 /* Bit 62 may or may not be set for this mce */
1482 value &= ~(1ULL << 62);
1483
1484 if (value != 0xb600000000010015ULL)
1485 return false;
1486
1487 /* Clear MCi_STATUS registers */
1488 for (i = 0; i < 6; ++i)
1489 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1490
1491 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1492 if (!err) {
1493 u32 low, high;
1494
1495 value &= ~(1ULL << 2);
1496 low = lower_32_bits(value);
1497 high = upper_32_bits(value);
1498
1499 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1500 }
1501
1502 /* Flush tlb to evict multi-match entries */
1503 __flush_tlb_all();
1504
1505 return true;
1506}
1507
fe5913e4 1508static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1509{
67ec6607
JR		 1510 if (is_erratum_383()) {
1511 /*
1512 * Erratum 383 triggered. Guest state is corrupt so kill the
1513 * guest.
1514 */
1515 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1516
a8eeb04a 1517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1518
1519 return;
1520 }
1521
53371b50
JR		 1522 /*
1523 * On an #MC intercept the MCE handler is not called automatically in
1524 * the host. So do it by hand here.
1525 */
1526 asm volatile (
1527 "int $0x12\n");
1528 /* not sure if we ever come back to this point */
1529
fe5913e4
JR		 1530 return;
1531}
1532
1533static int mc_interception(struct vcpu_svm *svm)
1534{
53371b50
JR		 1535 return 1;
1536}
1537
851ba692 1538static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1539{
851ba692
AK		 1540 struct kvm_run *kvm_run = svm->vcpu.run;
1541
46fe4ddd
JR		 1542 /*
1543 * VMCB is undefined after a SHUTDOWN intercept
1544 * so reinitialize it.
1545 */
a2fa3e9f 1546 clear_page(svm->vmcb);
e6101a96 1547 init_vmcb(svm);
46fe4ddd
JR		 1548
1549 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1550 return 0;
1551}
1552
851ba692 1553static int io_interception(struct vcpu_svm *svm)
6aa8b732 1554{
cf8f70bf 1555 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1556 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1557 int size, in, string;
039576c0 1558 unsigned port;
6aa8b732 1559
e756fc62 1560 ++svm->vcpu.stat.io_exits;
e70669ab 1561 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1562 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1563 if (string || in)
6d77dbfc 1564 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1565
039576c0
AK		 1566 port = io_info >> 16;
1567 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1568 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1569 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1570
1571 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1572}
1573
851ba692 1574static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1575{
1576 return 1;
1577}
1578
851ba692 1579static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1580{
1581 ++svm->vcpu.stat.irq_exits;
1582 return 1;
1583}
1584
851ba692 1585static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1586{
1587 return 1;
1588}
1589
851ba692 1590static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1591{
5fdbf976 1592 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1593 skip_emulated_instruction(&svm->vcpu);
1594 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1595}
1596
851ba692 1597static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1598{
5fdbf976 1599 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1600 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1601 kvm_emulate_hypercall(&svm->vcpu);
1602 return 1;
02e235bc
AK		 1603}
1604
5bd2edc3
JR		 1605static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1606{
1607 struct vcpu_svm *svm = to_svm(vcpu);
1608
1609 return svm->nested.nested_cr3;
1610}
1611
1612static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1613 unsigned long root)
1614{
1615 struct vcpu_svm *svm = to_svm(vcpu);
1616
1617 svm->vmcb->control.nested_cr3 = root;
1618 force_new_asid(vcpu);
1619}
1620
1621static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu)
1622{
1623 struct vcpu_svm *svm = to_svm(vcpu);
1624
1625 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1626 svm->vmcb->control.exit_code_hi = 0;
1627 svm->vmcb->control.exit_info_1 = vcpu->arch.fault.error_code;
1628 svm->vmcb->control.exit_info_2 = vcpu->arch.fault.address;
1629
1630 nested_svm_vmexit(svm);
1631}
1632
c0725420
AG		 1633static int nested_svm_check_permissions(struct vcpu_svm *svm)
1634{
f6801dff 1635 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1636 || !is_paging(&svm->vcpu)) {
1637 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1638 return 1;
1639 }
1640
1641 if (svm->vmcb->save.cpl) {
1642 kvm_inject_gp(&svm->vcpu, 0);
1643 return 1;
1644 }
1645
1646 return 0;
1647}
1648
cf74a78b
AG		 1649static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1650 bool has_error_code, u32 error_code)
1651{
b8e88bc8
JR		 1652 int vmexit;
1653
0295ad7d
JR		 1654 if (!is_nested(svm))
1655 return 0;
cf74a78b 1656
0295ad7d
JR		 1657 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1658 svm->vmcb->control.exit_code_hi = 0;
1659 svm->vmcb->control.exit_info_1 = error_code;
1660 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1661
b8e88bc8
JR		 1662 vmexit = nested_svm_intercept(svm);
1663 if (vmexit == NESTED_EXIT_DONE)
1664 svm->nested.exit_required = true;
1665
1666 return vmexit;
cf74a78b
AG		 1667}
1668
8fe54654
JR		 1669/* This function returns true if it is save to enable the irq window */
1670static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1671{
26666957 1672 if (!is_nested(svm))
8fe54654 1673 return true;
cf74a78b 1674
26666957 1675 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1676 return true;
cf74a78b 1677
26666957 1678 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1679 return false;
cf74a78b 1680
197717d5
JR		 1681 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1682 svm->vmcb->control.exit_info_1 = 0;
1683 svm->vmcb->control.exit_info_2 = 0;
26666957 1684
cd3ff653
JR		 1685 if (svm->nested.intercept & 1ULL) {
1686 /*
1687 * The #vmexit can't be emulated here directly because this
1688 * code path runs with irqs and preemtion disabled. A
1689 * #vmexit emulation might sleep. Only signal request for
1690 * the #vmexit here.
1691 */
1692 svm->nested.exit_required = true;
236649de 1693 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1694 return false;
cf74a78b
AG		 1695 }
1696
8fe54654 1697 return true;
cf74a78b
AG		 1698}
1699
887f500c
JR		 1700/* This function returns true if it is save to enable the nmi window */
1701static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1702{
1703 if (!is_nested(svm))
1704 return true;
1705
1706 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1707 return true;
1708
1709 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1710 svm->nested.exit_required = true;
1711
1712 return false;
cf74a78b
AG		 1713}
1714
7597f129 1715static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1716{
1717 struct page *page;
1718
6c3bd3d7
JR		 1719 might_sleep();
1720
34f80cfa 1721 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1722 if (is_error_page(page))
1723 goto error;
1724
7597f129
JR		 1725 *_page = page;
1726
1727 return kmap(page);
34f80cfa
JR		 1728
1729error:
1730 kvm_release_page_clean(page);
1731 kvm_inject_gp(&svm->vcpu, 0);
1732
1733 return NULL;
1734}
1735
7597f129 1736static void nested_svm_unmap(struct page *page)
34f80cfa 1737{
7597f129 1738 kunmap(page);
34f80cfa
JR		 1739 kvm_release_page_dirty(page);
1740}
34f80cfa 1741
ce2ac085
JR		 1742static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1743{
1744 unsigned port;
1745 u8 val, bit;
1746 u64 gpa;
34f80cfa 1747
ce2ac085
JR		 1748 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1749 return NESTED_EXIT_HOST;
34f80cfa 1750
ce2ac085
JR		 1751 port = svm->vmcb->control.exit_info_1 >> 16;
1752 gpa = svm->nested.vmcb_iopm + (port / 8);
1753 bit = port % 8;
1754 val = 0;
1755
1756 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1757 val &= (1 << bit);
1758
1759 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1760}
1761
d2477826 1762static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1763{
0d6b3537
JR		 1764 u32 offset, msr, value;
1765 int write, mask;
4c2161ae 1766
3d62d9aa 1767 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1768 return NESTED_EXIT_HOST;
3d62d9aa 1769
0d6b3537
JR		 1770 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1771 offset = svm_msrpm_offset(msr);
1772 write = svm->vmcb->control.exit_info_1 & 1;
1773 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1774
0d6b3537
JR		 1775 if (offset == MSR_INVALID)
1776 return NESTED_EXIT_DONE;
4c2161ae 1777
0d6b3537
JR		 1778 /* Offset is in 32 bit units but need in 8 bit units */
1779 offset *= 4;
4c2161ae 1780
0d6b3537
JR		 1781 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1782 return NESTED_EXIT_DONE;
3d62d9aa 1783
0d6b3537 1784 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1785}
1786
410e4d57 1787static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1788{
cf74a78b 1789 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1790
410e4d57
JR		 1791 switch (exit_code) {
1792 case SVM_EXIT_INTR:
1793 case SVM_EXIT_NMI:
ff47a49b 1794 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1795 return NESTED_EXIT_HOST;
410e4d57 1796 case SVM_EXIT_NPF:
e0231715 1797 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1798 if (npt_enabled)
1799 return NESTED_EXIT_HOST;
1800 break;
410e4d57 1801 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1802 /* When we're shadowing, trap PFs */
410e4d57
JR		 1803 if (!npt_enabled)
1804 return NESTED_EXIT_HOST;
1805 break;
66a562f7
JR		 1806 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1807 nm_interception(svm);
1808 break;
410e4d57
JR		 1809 default:
1810 break;
cf74a78b
AG		 1811 }
1812
410e4d57
JR		 1813 return NESTED_EXIT_CONTINUE;
1814}
1815
1816/*
1817 * If this function returns true, this #vmexit was already handled
1818 */
b8e88bc8 1819static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1820{
1821 u32 exit_code = svm->vmcb->control.exit_code;
1822 int vmexit = NESTED_EXIT_HOST;
1823
cf74a78b 1824 switch (exit_code) {
9c4e40b9 1825 case SVM_EXIT_MSR:
3d62d9aa 1826 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1827 break;
ce2ac085
JR		 1828 case SVM_EXIT_IOIO:
1829 vmexit = nested_svm_intercept_ioio(svm);
1830 break;
cf74a78b
AG		 1831 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1832 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1833 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1834 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1835 break;
1836 }
1837 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1838 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1839 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1840 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1841 break;
1842 }
1843 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1844 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1845 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1846 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1847 break;
1848 }
1849 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1850 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1851 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1852 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1853 break;
1854 }
1855 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1856 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1857 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1858 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1859 break;
1860 }
228070b1
JR		 1861 case SVM_EXIT_ERR: {
1862 vmexit = NESTED_EXIT_DONE;
1863 break;
1864 }
cf74a78b
AG		 1865 default: {
1866 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1867 if (svm->nested.intercept & exit_bits)
410e4d57 1868 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1869 }
1870 }
1871
b8e88bc8
JR		 1872 return vmexit;
1873}
1874
1875static int nested_svm_exit_handled(struct vcpu_svm *svm)
1876{
1877 int vmexit;
1878
1879 vmexit = nested_svm_intercept(svm);
1880
1881 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1882 nested_svm_vmexit(svm);
9c4e40b9
JR		 1883
1884 return vmexit;
cf74a78b
AG		 1885}
1886
0460a979
JR		 1887static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1888{
1889 struct vmcb_control_area *dst = &dst_vmcb->control;
1890 struct vmcb_control_area *from = &from_vmcb->control;
1891
1892 dst->intercept_cr_read = from->intercept_cr_read;
1893 dst->intercept_cr_write = from->intercept_cr_write;
1894 dst->intercept_dr_read = from->intercept_dr_read;
1895 dst->intercept_dr_write = from->intercept_dr_write;
1896 dst->intercept_exceptions = from->intercept_exceptions;
1897 dst->intercept = from->intercept;
1898 dst->iopm_base_pa = from->iopm_base_pa;
1899 dst->msrpm_base_pa = from->msrpm_base_pa;
1900 dst->tsc_offset = from->tsc_offset;
1901 dst->asid = from->asid;
1902 dst->tlb_ctl = from->tlb_ctl;
1903 dst->int_ctl = from->int_ctl;
1904 dst->int_vector = from->int_vector;
1905 dst->int_state = from->int_state;
1906 dst->exit_code = from->exit_code;
1907 dst->exit_code_hi = from->exit_code_hi;
1908 dst->exit_info_1 = from->exit_info_1;
1909 dst->exit_info_2 = from->exit_info_2;
1910 dst->exit_int_info = from->exit_int_info;
1911 dst->exit_int_info_err = from->exit_int_info_err;
1912 dst->nested_ctl = from->nested_ctl;
1913 dst->event_inj = from->event_inj;
1914 dst->event_inj_err = from->event_inj_err;
1915 dst->nested_cr3 = from->nested_cr3;
1916 dst->lbr_ctl = from->lbr_ctl;
1917}
1918
34f80cfa 1919static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1920{
34f80cfa 1921 struct vmcb *nested_vmcb;
e6aa9abd 1922 struct vmcb *hsave = svm->nested.hsave;
33740e40 1923 struct vmcb *vmcb = svm->vmcb;
7597f129 1924 struct page *page;
cf74a78b 1925
17897f36
JR		 1926 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1927 vmcb->control.exit_info_1,
1928 vmcb->control.exit_info_2,
1929 vmcb->control.exit_int_info,
1930 vmcb->control.exit_int_info_err);
1931
7597f129 1932 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1933 if (!nested_vmcb)
1934 return 1;
1935
06fc7772
JR		 1936 /* Exit nested SVM mode */
1937 svm->nested.vmcb = 0;
1938
cf74a78b 1939 /* Give the current vmcb to the guest */
33740e40
JR		 1940 disable_gif(svm);
1941
1942 nested_vmcb->save.es = vmcb->save.es;
1943 nested_vmcb->save.cs = vmcb->save.cs;
1944 nested_vmcb->save.ss = vmcb->save.ss;
1945 nested_vmcb->save.ds = vmcb->save.ds;
1946 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1947 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 1948 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 1949 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 1950 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1951 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1952 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1953 nested_vmcb->save.rflags = vmcb->save.rflags;
1954 nested_vmcb->save.rip = vmcb->save.rip;
1955 nested_vmcb->save.rsp = vmcb->save.rsp;
1956 nested_vmcb->save.rax = vmcb->save.rax;
1957 nested_vmcb->save.dr7 = vmcb->save.dr7;
1958 nested_vmcb->save.dr6 = vmcb->save.dr6;
1959 nested_vmcb->save.cpl = vmcb->save.cpl;
1960
1961 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1962 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1963 nested_vmcb->control.int_state = vmcb->control.int_state;
1964 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1965 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1966 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1967 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1968 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1969 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 1970 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 1971
1972 /*
1973 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1974 * to make sure that we do not lose injected events. So check event_inj
1975 * here and copy it to exit_int_info if it is valid.
1976 * Exit_int_info and event_inj can't be both valid because the case
1977 * below only happens on a VMRUN instruction intercept which has
1978 * no valid exit_int_info set.
1979 */
1980 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1981 struct vmcb_control_area *nc = &nested_vmcb->control;
1982
1983 nc->exit_int_info = vmcb->control.event_inj;
1984 nc->exit_int_info_err = vmcb->control.event_inj_err;
1985 }
1986
33740e40
JR		 1987 nested_vmcb->control.tlb_ctl = 0;
1988 nested_vmcb->control.event_inj = 0;
1989 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1990
1991 /* We always set V_INTR_MASKING and remember the old value in hflags */
1992 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1993 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1994
cf74a78b 1995 /* Restore the original control entries */
0460a979 1996 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1997
219b65dc
AG		 1998 kvm_clear_exception_queue(&svm->vcpu);
1999 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 2000
2001 /* Restore selected save entries */
2002 svm->vmcb->save.es = hsave->save.es;
2003 svm->vmcb->save.cs = hsave->save.cs;
2004 svm->vmcb->save.ss = hsave->save.ss;
2005 svm->vmcb->save.ds = hsave->save.ds;
2006 svm->vmcb->save.gdtr = hsave->save.gdtr;
2007 svm->vmcb->save.idtr = hsave->save.idtr;
2008 svm->vmcb->save.rflags = hsave->save.rflags;
2009 svm_set_efer(&svm->vcpu, hsave->save.efer);
2010 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2011 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2012 if (npt_enabled) {
2013 svm->vmcb->save.cr3 = hsave->save.cr3;
2014 svm->vcpu.arch.cr3 = hsave->save.cr3;
2015 } else {
2390218b 2016 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 2017 }
2018 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2019 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2020 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2021 svm->vmcb->save.dr7 = 0;
2022 svm->vmcb->save.cpl = 0;
2023 svm->vmcb->control.exit_int_info = 0;
2024
7597f129 2025 nested_svm_unmap(page);
cf74a78b
AG		 2026
2027 kvm_mmu_reset_context(&svm->vcpu);
2028 kvm_mmu_load(&svm->vcpu);
2029
2030 return 0;
2031}
3d6368ef 2032
9738b2c9 2033static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 2034{
323c3d80
JR		 2035 /*
2036 * This function merges the msr permission bitmaps of kvm and the
2037 * nested vmcb. It is omptimized in that it only merges the parts where
2038 * the kvm msr permission bitmap may contain zero bits
2039 */
3d6368ef 2040 int i;
9738b2c9 2041
323c3d80
JR		 2042 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2043 return true;
9738b2c9 2044
323c3d80
JR		 2045 for (i = 0; i < MSRPM_OFFSETS; i++) {
2046 u32 value, p;
2047 u64 offset;
9738b2c9 2048
323c3d80
JR		 2049 if (msrpm_offsets[i] == 0xffffffff)
2050 break;
3d6368ef 2051
0d6b3537
JR		 2052 p = msrpm_offsets[i];
2053 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2054
2055 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2056 return false;
2057
2058 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2059 }
3d6368ef 2060
323c3d80 2061 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2062
2063 return true;
3d6368ef
AG		 2064}
2065
52c65a30
JR		 2066static bool nested_vmcb_checks(struct vmcb *vmcb)
2067{
2068 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2069 return false;
2070
dbe77584
JR		 2071 if (vmcb->control.asid == 0)
2072 return false;
2073
52c65a30
JR		 2074 return true;
2075}
2076
9738b2c9 2077static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2078{
9738b2c9 2079 struct vmcb *nested_vmcb;
e6aa9abd 2080 struct vmcb *hsave = svm->nested.hsave;
defbba56 2081 struct vmcb *vmcb = svm->vmcb;
7597f129 2082 struct page *page;
06fc7772 2083 u64 vmcb_gpa;
3d6368ef 2084
06fc7772 2085 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2086
7597f129 2087 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2088 if (!nested_vmcb)
2089 return false;
2090
52c65a30
JR		 2091 if (!nested_vmcb_checks(nested_vmcb)) {
2092 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2093 nested_vmcb->control.exit_code_hi = 0;
2094 nested_vmcb->control.exit_info_1 = 0;
2095 nested_vmcb->control.exit_info_2 = 0;
2096
2097 nested_svm_unmap(page);
2098
2099 return false;
2100 }
2101
b75f4eb3 2102 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
0ac406de
JR		 2103 nested_vmcb->save.rip,
2104 nested_vmcb->control.int_ctl,
2105 nested_vmcb->control.event_inj,
2106 nested_vmcb->control.nested_ctl);
2107
2e554e8d
JR		 2108 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2109 nested_vmcb->control.intercept_cr_write,
2110 nested_vmcb->control.intercept_exceptions,
2111 nested_vmcb->control.intercept);
2112
3d6368ef 2113 /* Clear internal status */
219b65dc
AG		 2114 kvm_clear_exception_queue(&svm->vcpu);
2115 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2116
e0231715
JR		 2117 /*
2118 * Save the old vmcb, so we don't need to pick what we save, but can
2119 * restore everything when a VMEXIT occurs
2120 */
defbba56
JR		 2121 hsave->save.es = vmcb->save.es;
2122 hsave->save.cs = vmcb->save.cs;
2123 hsave->save.ss = vmcb->save.ss;
2124 hsave->save.ds = vmcb->save.ds;
2125 hsave->save.gdtr = vmcb->save.gdtr;
2126 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2127 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2128 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2129 hsave->save.cr4 = svm->vcpu.arch.cr4;
2130 hsave->save.rflags = vmcb->save.rflags;
b75f4eb3 2131 hsave->save.rip = kvm_rip_read(&svm->vcpu);
defbba56
JR		 2132 hsave->save.rsp = vmcb->save.rsp;
2133 hsave->save.rax = vmcb->save.rax;
2134 if (npt_enabled)
2135 hsave->save.cr3 = vmcb->save.cr3;
2136 else
2137 hsave->save.cr3 = svm->vcpu.arch.cr3;
2138
0460a979 2139 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2140
2141 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2142 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2143 else
2144 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2145
2146 /* Load the nested guest state */
2147 svm->vmcb->save.es = nested_vmcb->save.es;
2148 svm->vmcb->save.cs = nested_vmcb->save.cs;
2149 svm->vmcb->save.ss = nested_vmcb->save.ss;
2150 svm->vmcb->save.ds = nested_vmcb->save.ds;
2151 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2152 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2153 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2154 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2155 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2156 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2157 if (npt_enabled) {
2158 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2159 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2160 } else
2390218b 2161 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2162
2163 /* Guest paging mode is active - reset mmu */
2164 kvm_mmu_reset_context(&svm->vcpu);
2165
defbba56 2166 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2167 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2168 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2169 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2170
3d6368ef
AG		 2171 /* In case we don't even reach vcpu_run, the fields are not updated */
2172 svm->vmcb->save.rax = nested_vmcb->save.rax;
2173 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2174 svm->vmcb->save.rip = nested_vmcb->save.rip;
2175 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2176 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2177 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2178
f7138538 2179 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2180 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2181
aad42c64
JR		 2182 /* cache intercepts */
2183 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2184 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2185 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2186 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2187 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2188 svm->nested.intercept = nested_vmcb->control.intercept;
2189
3d6368ef 2190 force_new_asid(&svm->vcpu);
3d6368ef 2191 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2192 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2193 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2194 else
2195 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2196
88ab24ad
JR		 2197 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2198 /* We only want the cr8 intercept bits of the guest */
2199 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2200 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2201 }
2202
0d945bd9
JR		 2203 /* We don't want to see VMMCALLs from a nested guest */
2204 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2205
e0231715
JR		 2206 /*
2207 * We don't want a nested guest to be more powerful than the guest, so
2208 * all intercepts are ORed
2209 */
88ab24ad
JR		 2210 svm->vmcb->control.intercept_cr_read |=
2211 nested_vmcb->control.intercept_cr_read;
2212 svm->vmcb->control.intercept_cr_write |=
2213 nested_vmcb->control.intercept_cr_write;
2214 svm->vmcb->control.intercept_dr_read |=
2215 nested_vmcb->control.intercept_dr_read;
2216 svm->vmcb->control.intercept_dr_write |=
2217 nested_vmcb->control.intercept_dr_write;
2218 svm->vmcb->control.intercept_exceptions |=
2219 nested_vmcb->control.intercept_exceptions;
2220
2221 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2222
2223 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2224 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2225 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2226 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2227 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2228 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2229
7597f129 2230 nested_svm_unmap(page);
9738b2c9 2231
06fc7772
JR		 2232 /* nested_vmcb is our indicator if nested SVM is activated */
2233 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2234
2af9194d 2235 enable_gif(svm);
3d6368ef 2236
9738b2c9 2237 return true;
3d6368ef
AG		 2238}
2239
9966bf68 2240static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2241{
2242 to_vmcb->save.fs = from_vmcb->save.fs;
2243 to_vmcb->save.gs = from_vmcb->save.gs;
2244 to_vmcb->save.tr = from_vmcb->save.tr;
2245 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2246 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2247 to_vmcb->save.star = from_vmcb->save.star;
2248 to_vmcb->save.lstar = from_vmcb->save.lstar;
2249 to_vmcb->save.cstar = from_vmcb->save.cstar;
2250 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2251 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2252 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2253 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2254}
2255
851ba692 2256static int vmload_interception(struct vcpu_svm *svm)
5542675b 2257{
9966bf68 2258 struct vmcb *nested_vmcb;
7597f129 2259 struct page *page;
9966bf68 2260
5542675b
AG		 2261 if (nested_svm_check_permissions(svm))
2262 return 1;
2263
2264 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2265 skip_emulated_instruction(&svm->vcpu);
2266
7597f129 2267 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2268 if (!nested_vmcb)
2269 return 1;
2270
2271 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2272 nested_svm_unmap(page);
5542675b
AG		 2273
2274 return 1;
2275}
2276
851ba692 2277static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2278{
9966bf68 2279 struct vmcb *nested_vmcb;
7597f129 2280 struct page *page;
9966bf68 2281
5542675b
AG		 2282 if (nested_svm_check_permissions(svm))
2283 return 1;
2284
2285 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2286 skip_emulated_instruction(&svm->vcpu);
2287
7597f129 2288 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2289 if (!nested_vmcb)
2290 return 1;
2291
2292 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2293 nested_svm_unmap(page);
5542675b
AG		 2294
2295 return 1;
2296}
2297
851ba692 2298static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2299{
3d6368ef
AG		 2300 if (nested_svm_check_permissions(svm))
2301 return 1;
2302
b75f4eb3
RJ		 2303 /* Save rip after vmrun instruction */
2304 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3d6368ef 2305
9738b2c9 2306 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2307 return 1;
2308
9738b2c9 2309 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2310 goto failed;
2311
2312 return 1;
2313
2314failed:
2315
2316 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2317 svm->vmcb->control.exit_code_hi = 0;
2318 svm->vmcb->control.exit_info_1 = 0;
2319 svm->vmcb->control.exit_info_2 = 0;
2320
2321 nested_svm_vmexit(svm);
3d6368ef
AG		 2322
2323 return 1;
2324}
2325
851ba692 2326static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2327{
2328 if (nested_svm_check_permissions(svm))
2329 return 1;
2330
2331 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2332 skip_emulated_instruction(&svm->vcpu);
2333
2af9194d 2334 enable_gif(svm);
1371d904
AG		 2335
2336 return 1;
2337}
2338
851ba692 2339static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2340{
2341 if (nested_svm_check_permissions(svm))
2342 return 1;
2343
2344 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2345 skip_emulated_instruction(&svm->vcpu);
2346
2af9194d 2347 disable_gif(svm);
1371d904
AG		 2348
2349 /* After a CLGI no interrupts should come */
2350 svm_clear_vintr(svm);
2351 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2352
2353 return 1;
2354}
2355
851ba692 2356static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2357{
2358 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2359
ec1ff790
JR		 2360 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2361 vcpu->arch.regs[VCPU_REGS_RAX]);
2362
ff092385
AG		 2363 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2364 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2365
2366 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2367 skip_emulated_instruction(&svm->vcpu);
2368 return 1;
2369}
2370
532a46b9
JR		 2371static int skinit_interception(struct vcpu_svm *svm)
2372{
2373 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2374
2375 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2376 return 1;
2377}
2378
851ba692 2379static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2380{
7ee5d940 2381 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2382 return 1;
2383}
2384
851ba692 2385static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2386{
37817f29 2387 u16 tss_selector;
64a7ec06
GN		 2388 int reason;
2389 int int_type = svm->vmcb->control.exit_int_info &
2390 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2391 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2392 uint32_t type =
2393 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2394 uint32_t idt_v =
2395 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2396 bool has_error_code = false;
2397 u32 error_code = 0;
37817f29
IE		 2398
2399 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2400
37817f29
IE		 2401 if (svm->vmcb->control.exit_info_2 &
2402 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2403 reason = TASK_SWITCH_IRET;
2404 else if (svm->vmcb->control.exit_info_2 &
2405 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2406 reason = TASK_SWITCH_JMP;
fe8e7f83 2407 else if (idt_v)
64a7ec06
GN		 2408 reason = TASK_SWITCH_GATE;
2409 else
2410 reason = TASK_SWITCH_CALL;
2411
fe8e7f83
GN		 2412 if (reason == TASK_SWITCH_GATE) {
2413 switch (type) {
2414 case SVM_EXITINTINFO_TYPE_NMI:
2415 svm->vcpu.arch.nmi_injected = false;
2416 break;
2417 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2418 if (svm->vmcb->control.exit_info_2 &
2419 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2420 has_error_code = true;
2421 error_code =
2422 (u32)svm->vmcb->control.exit_info_2;
2423 }
fe8e7f83
GN		 2424 kvm_clear_exception_queue(&svm->vcpu);
2425 break;
2426 case SVM_EXITINTINFO_TYPE_INTR:
2427 kvm_clear_interrupt_queue(&svm->vcpu);
2428 break;
2429 default:
2430 break;
2431 }
2432 }
64a7ec06 2433
8317c298
GN		 2434 if (reason != TASK_SWITCH_GATE ||
2435 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2436 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2437 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2438 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2439
acb54517
GN		 2440 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2441 has_error_code, error_code) == EMULATE_FAIL) {
2442 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2443 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2444 svm->vcpu.run->internal.ndata = 0;
2445 return 0;
2446 }
2447 return 1;
6aa8b732
AK		 2448}
2449
851ba692 2450static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2451{
5fdbf976 2452 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2453 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2454 return 1;
6aa8b732
AK		 2455}
2456
851ba692 2457static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2458{
2459 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2460 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2461 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2462 return 1;
2463}
2464
851ba692 2465static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2466{
6d77dbfc 2467 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2468}
2469
851ba692 2470static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2471{
6d77dbfc 2472 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2473}
2474
cda00082
JR		 2475static int cr0_write_interception(struct vcpu_svm *svm)
2476{
2477 struct kvm_vcpu *vcpu = &svm->vcpu;
2478 int r;
2479
2480 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2481
2482 if (svm->nested.vmexit_rip) {
2483 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2484 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2485 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2486 svm->nested.vmexit_rip = 0;
2487 }
2488
2489 return r == EMULATE_DONE;
2490}
2491
851ba692 2492static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2493{
851ba692
AK		 2494 struct kvm_run *kvm_run = svm->vcpu.run;
2495
0a5fff19
GN		 2496 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2497 /* instruction emulation calls kvm_set_cr8() */
851ba692 2498 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2499 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2500 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2501 return 1;
95ba8273 2502 }
0a5fff19
GN		 2503 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2504 return 1;
1d075434
JR		 2505 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2506 return 0;
2507}
2508
6aa8b732
AK		 2509static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2510{
a2fa3e9f
GH		 2511 struct vcpu_svm *svm = to_svm(vcpu);
2512
6aa8b732 2513 switch (ecx) {
af24a4e4 2514 case MSR_IA32_TSC: {
20824f30 2515 u64 tsc_offset;
6aa8b732 2516
20824f30
JR		 2517 if (is_nested(svm))
2518 tsc_offset = svm->nested.hsave->control.tsc_offset;
2519 else
2520 tsc_offset = svm->vmcb->control.tsc_offset;
2521
2522 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2523 break;
2524 }
8c06585d 2525 case MSR_STAR:
a2fa3e9f 2526 *data = svm->vmcb->save.star;
6aa8b732 2527 break;
0e859cac 2528#ifdef CONFIG_X86_64
6aa8b732 2529 case MSR_LSTAR:
a2fa3e9f 2530 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2531 break;
2532 case MSR_CSTAR:
a2fa3e9f 2533 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2534 break;
2535 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2536 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2537 break;
2538 case MSR_SYSCALL_MASK:
a2fa3e9f 2539 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2540 break;
2541#endif
2542 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2543 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2544 break;
2545 case MSR_IA32_SYSENTER_EIP:
017cb99e 2546 *data = svm->sysenter_eip;
6aa8b732
AK		 2547 break;
2548 case MSR_IA32_SYSENTER_ESP:
017cb99e 2549 *data = svm->sysenter_esp;
6aa8b732 2550 break;
e0231715
JR		 2551 /*
2552 * Nobody will change the following 5 values in the VMCB so we can
2553 * safely return them on rdmsr. They will always be 0 until LBRV is
2554 * implemented.
2555 */
a2938c80
JR		 2556 case MSR_IA32_DEBUGCTLMSR:
2557 *data = svm->vmcb->save.dbgctl;
2558 break;
2559 case MSR_IA32_LASTBRANCHFROMIP:
2560 *data = svm->vmcb->save.br_from;
2561 break;
2562 case MSR_IA32_LASTBRANCHTOIP:
2563 *data = svm->vmcb->save.br_to;
2564 break;
2565 case MSR_IA32_LASTINTFROMIP:
2566 *data = svm->vmcb->save.last_excp_from;
2567 break;
2568 case MSR_IA32_LASTINTTOIP:
2569 *data = svm->vmcb->save.last_excp_to;
2570 break;
b286d5d8 2571 case MSR_VM_HSAVE_PA:
e6aa9abd 2572 *data = svm->nested.hsave_msr;
b286d5d8 2573 break;
eb6f302e 2574 case MSR_VM_CR:
4a810181 2575 *data = svm->nested.vm_cr_msr;
eb6f302e 2576 break;
c8a73f18
AG		 2577 case MSR_IA32_UCODE_REV:
2578 *data = 0x01000065;
2579 break;
6aa8b732 2580 default:
3bab1f5d 2581 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2582 }
2583 return 0;
2584}
2585
851ba692 2586static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2587{
ad312c7c 2588 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2589 u64 data;
2590
59200273
AK		 2591 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2592 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2593 kvm_inject_gp(&svm->vcpu, 0);
59200273 2594 } else {
229456fc 2595 trace_kvm_msr_read(ecx, data);
af9ca2d7 2596
5fdbf976 2597 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2598 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2599 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2600 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2601 }
2602 return 1;
2603}
2604
4a810181
JR		 2605static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2606{
2607 struct vcpu_svm *svm = to_svm(vcpu);
2608 int svm_dis, chg_mask;
2609
2610 if (data & ~SVM_VM_CR_VALID_MASK)
2611 return 1;
2612
2613 chg_mask = SVM_VM_CR_VALID_MASK;
2614
2615 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2616 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2617
2618 svm->nested.vm_cr_msr &= ~chg_mask;
2619 svm->nested.vm_cr_msr |= (data & chg_mask);
2620
2621 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2622
2623 /* check for svm_disable while efer.svme is set */
2624 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2625 return 1;
2626
2627 return 0;
2628}
2629
6aa8b732
AK		 2630static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2631{
a2fa3e9f
GH		 2632 struct vcpu_svm *svm = to_svm(vcpu);
2633
6aa8b732 2634 switch (ecx) {
f4e1b3c8 2635 case MSR_IA32_TSC:
99e3e30a 2636 kvm_write_tsc(vcpu, data);
6aa8b732 2637 break;
8c06585d 2638 case MSR_STAR:
a2fa3e9f 2639 svm->vmcb->save.star = data;
6aa8b732 2640 break;
49b14f24 2641#ifdef CONFIG_X86_64
6aa8b732 2642 case MSR_LSTAR:
a2fa3e9f 2643 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2644 break;
2645 case MSR_CSTAR:
a2fa3e9f 2646 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2647 break;
2648 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2649 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2650 break;
2651 case MSR_SYSCALL_MASK:
a2fa3e9f 2652 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2653 break;
2654#endif
2655 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2656 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2657 break;
2658 case MSR_IA32_SYSENTER_EIP:
017cb99e 2659 svm->sysenter_eip = data;
a2fa3e9f 2660 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2661 break;
2662 case MSR_IA32_SYSENTER_ESP:
017cb99e 2663 svm->sysenter_esp = data;
a2fa3e9f 2664 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2665 break;
a2938c80 2666 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2667 if (!svm_has(SVM_FEATURE_LBRV)) {
2668 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2669 __func__, data);
24e09cbf
JR		 2670 break;
2671 }
2672 if (data & DEBUGCTL_RESERVED_BITS)
2673 return 1;
2674
2675 svm->vmcb->save.dbgctl = data;
2676 if (data & (1ULL<<0))
2677 svm_enable_lbrv(svm);
2678 else
2679 svm_disable_lbrv(svm);
a2938c80 2680 break;
b286d5d8 2681 case MSR_VM_HSAVE_PA:
e6aa9abd 2682 svm->nested.hsave_msr = data;
62b9abaa 2683 break;
3c5d0a44 2684 case MSR_VM_CR:
4a810181 2685 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2686 case MSR_VM_IGNNE:
3c5d0a44
AG		 2687 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2688 break;
6aa8b732 2689 default:
3bab1f5d 2690 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2691 }
2692 return 0;
2693}
2694
851ba692 2695static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2696{
ad312c7c 2697 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2698 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2699 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2700
af9ca2d7 2701
5fdbf976 2702 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2703 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2704 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2705 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2706 } else {
2707 trace_kvm_msr_write(ecx, data);
e756fc62 2708 skip_emulated_instruction(&svm->vcpu);
59200273 2709 }
6aa8b732
AK		 2710 return 1;
2711}
2712
851ba692 2713static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2714{
e756fc62 2715 if (svm->vmcb->control.exit_info_1)
851ba692 2716 return wrmsr_interception(svm);
6aa8b732 2717 else
851ba692 2718 return rdmsr_interception(svm);
6aa8b732
AK		 2719}
2720
851ba692 2721static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2722{
851ba692
AK		 2723 struct kvm_run *kvm_run = svm->vcpu.run;
2724
f0b85051 2725 svm_clear_vintr(svm);
85f455f7 2726 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2727 /*
2728 * If the user space waits to inject interrupts, exit as soon as
2729 * possible
2730 */
8061823a
GN		 2731 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2732 kvm_run->request_interrupt_window &&
2733 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2734 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2735 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2736 return 0;
2737 }
2738
2739 return 1;
2740}
2741
565d0998
ML		 2742static int pause_interception(struct vcpu_svm *svm)
2743{
2744 kvm_vcpu_on_spin(&(svm->vcpu));
2745 return 1;
2746}
2747
851ba692 2748static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2749 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2750 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2751 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2752 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2753 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
cda00082 2754 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
e0231715
JR		 2755 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2756 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2757 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2758 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2759 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2760 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2761 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2762 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2763 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2764 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2765 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2766 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2767 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2768 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2769 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2770 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2771 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2772 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2773 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2774 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2775 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2776 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2777 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2778 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2779 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2780 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2781 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2782 [SVM_EXIT_SMI] = nop_on_interception,
2783 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2784 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2785 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2786 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2787 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2788 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2789 [SVM_EXIT_HLT] = halt_interception,
a7052897 2790 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2791 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2792 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2793 [SVM_EXIT_MSR] = msr_interception,
2794 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2795 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2796 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2797 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2798 [SVM_EXIT_VMLOAD] = vmload_interception,
2799 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2800 [SVM_EXIT_STGI] = stgi_interception,
2801 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2802 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2803 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2804 [SVM_EXIT_MONITOR] = invalid_op_interception,
2805 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2806 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2807};
2808
3f10c846
JR		 2809void dump_vmcb(struct kvm_vcpu *vcpu)
2810{
2811 struct vcpu_svm *svm = to_svm(vcpu);
2812 struct vmcb_control_area *control = &svm->vmcb->control;
2813 struct vmcb_save_area *save = &svm->vmcb->save;
2814
2815 pr_err("VMCB Control Area:\n");
2816 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2817 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2818 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2819 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2820 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2821 pr_err("intercepts: %016llx\n", control->intercept);
2822 pr_err("pause filter count: %d\n", control->pause_filter_count);
2823 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2824 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2825 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2826 pr_err("asid: %d\n", control->asid);
2827 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2828 pr_err("int_ctl: %08x\n", control->int_ctl);
2829 pr_err("int_vector: %08x\n", control->int_vector);
2830 pr_err("int_state: %08x\n", control->int_state);
2831 pr_err("exit_code: %08x\n", control->exit_code);
2832 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2833 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2834 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2835 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2836 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2837 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2838 pr_err("event_inj: %08x\n", control->event_inj);
2839 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2840 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2841 pr_err("next_rip: %016llx\n", control->next_rip);
2842 pr_err("VMCB State Save Area:\n");
2843 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2844 save->es.selector, save->es.attrib,
2845 save->es.limit, save->es.base);
2846 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2847 save->cs.selector, save->cs.attrib,
2848 save->cs.limit, save->cs.base);
2849 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2850 save->ss.selector, save->ss.attrib,
2851 save->ss.limit, save->ss.base);
2852 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2853 save->ds.selector, save->ds.attrib,
2854 save->ds.limit, save->ds.base);
2855 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2856 save->fs.selector, save->fs.attrib,
2857 save->fs.limit, save->fs.base);
2858 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2859 save->gs.selector, save->gs.attrib,
2860 save->gs.limit, save->gs.base);
2861 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2862 save->gdtr.selector, save->gdtr.attrib,
2863 save->gdtr.limit, save->gdtr.base);
2864 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2865 save->ldtr.selector, save->ldtr.attrib,
2866 save->ldtr.limit, save->ldtr.base);
2867 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2868 save->idtr.selector, save->idtr.attrib,
2869 save->idtr.limit, save->idtr.base);
2870 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2871 save->tr.selector, save->tr.attrib,
2872 save->tr.limit, save->tr.base);
2873 pr_err("cpl: %d efer: %016llx\n",
2874 save->cpl, save->efer);
2875 pr_err("cr0: %016llx cr2: %016llx\n",
2876 save->cr0, save->cr2);
2877 pr_err("cr3: %016llx cr4: %016llx\n",
2878 save->cr3, save->cr4);
2879 pr_err("dr6: %016llx dr7: %016llx\n",
2880 save->dr6, save->dr7);
2881 pr_err("rip: %016llx rflags: %016llx\n",
2882 save->rip, save->rflags);
2883 pr_err("rsp: %016llx rax: %016llx\n",
2884 save->rsp, save->rax);
2885 pr_err("star: %016llx lstar: %016llx\n",
2886 save->star, save->lstar);
2887 pr_err("cstar: %016llx sfmask: %016llx\n",
2888 save->cstar, save->sfmask);
2889 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2890 save->kernel_gs_base, save->sysenter_cs);
2891 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2892 save->sysenter_esp, save->sysenter_eip);
2893 pr_err("gpat: %016llx dbgctl: %016llx\n",
2894 save->g_pat, save->dbgctl);
2895 pr_err("br_from: %016llx br_to: %016llx\n",
2896 save->br_from, save->br_to);
2897 pr_err("excp_from: %016llx excp_to: %016llx\n",
2898 save->last_excp_from, save->last_excp_to);
2899
2900}
2901
851ba692 2902static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2903{
04d2cc77 2904 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2905 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2906 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2907
5bfd8b54 2908 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 2909
2be4fc7a
JR		 2910 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2911 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2912 if (npt_enabled)
2913 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2914
cd3ff653
JR		 2915 if (unlikely(svm->nested.exit_required)) {
2916 nested_svm_vmexit(svm);
2917 svm->nested.exit_required = false;
2918
2919 return 1;
2920 }
2921
cf74a78b 2922 if (is_nested(svm)) {
410e4d57
JR		 2923 int vmexit;
2924
d8cabddf
JR		 2925 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2926 svm->vmcb->control.exit_info_1,
2927 svm->vmcb->control.exit_info_2,
2928 svm->vmcb->control.exit_int_info,
2929 svm->vmcb->control.exit_int_info_err);
2930
410e4d57
JR		 2931 vmexit = nested_svm_exit_special(svm);
2932
2933 if (vmexit == NESTED_EXIT_CONTINUE)
2934 vmexit = nested_svm_exit_handled(svm);
2935
2936 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2937 return 1;
cf74a78b
AG		 2938 }
2939
a5c3832d
JR		 2940 svm_complete_interrupts(svm);
2941
04d2cc77
AK		 2942 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2943 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2944 kvm_run->fail_entry.hardware_entry_failure_reason
2945 = svm->vmcb->control.exit_code;
3f10c846
JR		 2946 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2947 dump_vmcb(vcpu);
04d2cc77
AK		 2948 return 0;
2949 }
2950
a2fa3e9f 2951 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2952 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2953 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2954 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2955 "exit_code 0x%x\n",
b8688d51 2956 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2957 exit_code);
2958
9d8f549d 2959 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2960 || !svm_exit_handlers[exit_code]) {
6aa8b732 2961 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2962 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2963 return 0;
2964 }
2965
851ba692 2966 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2967}
2968
2969static void reload_tss(struct kvm_vcpu *vcpu)
2970{
2971 int cpu = raw_smp_processor_id();
2972
0fe1e009
TH		 2973 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2974 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2975 load_TR_desc();
2976}
2977
e756fc62 2978static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2979{
2980 int cpu = raw_smp_processor_id();
2981
0fe1e009 2982 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2983
a2fa3e9f 2984 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2985 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2986 if (svm->asid_generation != sd->asid_generation)
2987 new_asid(svm, sd);
6aa8b732
AK		 2988}
2989
95ba8273
GN		 2990static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2991{
2992 struct vcpu_svm *svm = to_svm(vcpu);
2993
2994 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2995 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 2996 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 2997 ++vcpu->stat.nmi_injections;
2998}
6aa8b732 2999
85f455f7 3000static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 3001{
3002 struct vmcb_control_area *control;
3003
e756fc62 3004 control = &svm->vmcb->control;
85f455f7 3005 control->int_vector = irq;
6aa8b732
AK		 3006 control->int_ctl &= ~V_INTR_PRIO_MASK;
3007 control->int_ctl |= V_IRQ_MASK |
3008 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3009}
3010
66fd3f7f 3011static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3012{
3013 struct vcpu_svm *svm = to_svm(vcpu);
3014
2af9194d 3015 BUG_ON(!(gif_set(svm)));
cf74a78b 3016
9fb2d2b4
GN		 3017 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3018 ++vcpu->stat.irq_injections;
3019
219b65dc
AG		 3020 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3021 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3022}
3023
95ba8273 3024static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3025{
3026 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3027
88ab24ad
JR		 3028 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3029 return;
3030
95ba8273 3031 if (irr == -1)
aaacfc9a
JR		 3032 return;
3033
95ba8273
GN		 3034 if (tpr >= irr)
3035 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
3036}
aaacfc9a 3037
95ba8273
GN		 3038static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3039{
3040 struct vcpu_svm *svm = to_svm(vcpu);
3041 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 3042 int ret;
3043 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3044 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3045 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3046
3047 return ret;
aaacfc9a
JR		 3048}
3049
3cfc3092
JK		 3050static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3051{
3052 struct vcpu_svm *svm = to_svm(vcpu);
3053
3054 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3055}
3056
3057static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3058{
3059 struct vcpu_svm *svm = to_svm(vcpu);
3060
3061 if (masked) {
3062 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 3063 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3064 } else {
3065 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 3066 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3067 }
3068}
3069
78646121
GN		 3070static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3071{
3072 struct vcpu_svm *svm = to_svm(vcpu);
3073 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3074 int ret;
3075
3076 if (!gif_set(svm) ||
3077 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3078 return 0;
3079
3080 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3081
3082 if (is_nested(svm))
3083 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3084
3085 return ret;
78646121
GN		 3086}
3087
9222be18 3088static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3089{
219b65dc 3090 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3091
e0231715
JR		 3092 /*
3093 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3094 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3095 * get that intercept, this function will be called again though and
3096 * we'll get the vintr intercept.
3097 */
8fe54654 3098 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3099 svm_set_vintr(svm);
3100 svm_inject_irq(svm, 0x0);
3101 }
85f455f7
ED		 3102}
3103
95ba8273 3104static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3105{
04d2cc77 3106 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3107
44c11430
GN		 3108 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3109 == HF_NMI_MASK)
3110 return; /* IRET will cause a vm exit */
3111
e0231715
JR		 3112 /*
3113 * Something prevents NMI from been injected. Single step over possible
3114 * problem (IRET or exception injection or interrupt shadow)
3115 */
6be7d306 3116 svm->nmi_singlestep = true;
44c11430
GN		 3117 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3118 update_db_intercept(vcpu);
c1150d8c
DL		 3119}
3120
cbc94022
IE		 3121static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3122{
3123 return 0;
3124}
3125
d9e368d6
AK		 3126static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3127{
3128 force_new_asid(vcpu);
3129}
3130
04d2cc77
AK		 3131static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3132{
3133}
3134
d7bf8221
JR		 3135static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3136{
3137 struct vcpu_svm *svm = to_svm(vcpu);
3138
88ab24ad
JR		 3139 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3140 return;
3141
d7bf8221
JR		 3142 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3143 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3144 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3145 }
3146}
3147
649d6864
JR		 3148static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3149{
3150 struct vcpu_svm *svm = to_svm(vcpu);
3151 u64 cr8;
3152
88ab24ad
JR		 3153 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3154 return;
3155
649d6864
JR		 3156 cr8 = kvm_get_cr8(vcpu);
3157 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3158 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3159}
3160
9222be18
GN		 3161static void svm_complete_interrupts(struct vcpu_svm *svm)
3162{
3163 u8 vector;
3164 int type;
3165 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3166 unsigned int3_injected = svm->int3_injected;
3167
3168 svm->int3_injected = 0;
9222be18 3169
44c11430
GN		 3170 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3171 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3172
9222be18
GN		 3173 svm->vcpu.arch.nmi_injected = false;
3174 kvm_clear_exception_queue(&svm->vcpu);
3175 kvm_clear_interrupt_queue(&svm->vcpu);
3176
3177 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3178 return;
3179
3180 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3181 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3182
3183 switch (type) {
3184 case SVM_EXITINTINFO_TYPE_NMI:
3185 svm->vcpu.arch.nmi_injected = true;
3186 break;
3187 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3188 /*
3189 * In case of software exceptions, do not reinject the vector,
3190 * but re-execute the instruction instead. Rewind RIP first
3191 * if we emulated INT3 before.
3192 */
3193 if (kvm_exception_is_soft(vector)) {
3194 if (vector == BP_VECTOR && int3_injected &&
3195 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3196 kvm_rip_write(&svm->vcpu,
3197 kvm_rip_read(&svm->vcpu) -
3198 int3_injected);
9222be18 3199 break;
66b7138f 3200 }
9222be18
GN		 3201 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3202 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3203 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3204
3205 } else
ce7ddec4 3206 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3207 break;
3208 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3209 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3210 break;
3211 default:
3212 break;
3213 }
3214}
3215
80e31d4f
AK		 3216#ifdef CONFIG_X86_64
3217#define R "r"
3218#else
3219#define R "e"
3220#endif
3221
851ba692 3222static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3223{
a2fa3e9f 3224 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 3225 u16 fs_selector;
3226 u16 gs_selector;
3227 u16 ldt_selector;
d9e368d6 3228
2041a06a
JR		 3229 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3230 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3231 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3232
cd3ff653
JR		 3233 /*
3234 * A vmexit emulation is required before the vcpu can be executed
3235 * again.
3236 */
3237 if (unlikely(svm->nested.exit_required))
3238 return;
3239
e756fc62 3240 pre_svm_run(svm);
6aa8b732 3241
649d6864
JR		 3242 sync_lapic_to_cr8(vcpu);
3243
6aa8b732 3244 save_host_msrs(vcpu);
9581d442
AK		 3245 savesegment(fs, fs_selector);
3246 savesegment(gs, gs_selector);
d6e88aec 3247 ldt_selector = kvm_read_ldt();
cda0ffdd 3248 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3249
04d2cc77
AK		 3250 clgi();
3251
3252 local_irq_enable();
36241b8c 3253
6aa8b732 3254 asm volatile (
80e31d4f
AK		 3255 "push %%"R"bp; \n\t"
3256 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3257 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3258 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3259 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3260 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3261 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3262#ifdef CONFIG_X86_64
fb3f0f51
RR		 3263 "mov %c[r8](%[svm]), %%r8 \n\t"
3264 "mov %c[r9](%[svm]), %%r9 \n\t"
3265 "mov %c[r10](%[svm]), %%r10 \n\t"
3266 "mov %c[r11](%[svm]), %%r11 \n\t"
3267 "mov %c[r12](%[svm]), %%r12 \n\t"
3268 "mov %c[r13](%[svm]), %%r13 \n\t"
3269 "mov %c[r14](%[svm]), %%r14 \n\t"
3270 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3271#endif
3272
6aa8b732 3273 /* Enter guest mode */
80e31d4f
AK		 3274 "push %%"R"ax \n\t"
3275 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3276 __ex(SVM_VMLOAD) "\n\t"
3277 __ex(SVM_VMRUN) "\n\t"
3278 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3279 "pop %%"R"ax \n\t"
6aa8b732
AK		 3280
3281 /* Save guest registers, load host registers */
80e31d4f
AK		 3282 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3283 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3284 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3285 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3286 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3287 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3288#ifdef CONFIG_X86_64
fb3f0f51
RR		 3289 "mov %%r8, %c[r8](%[svm]) \n\t"
3290 "mov %%r9, %c[r9](%[svm]) \n\t"
3291 "mov %%r10, %c[r10](%[svm]) \n\t"
3292 "mov %%r11, %c[r11](%[svm]) \n\t"
3293 "mov %%r12, %c[r12](%[svm]) \n\t"
3294 "mov %%r13, %c[r13](%[svm]) \n\t"
3295 "mov %%r14, %c[r14](%[svm]) \n\t"
3296 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3297#endif
80e31d4f 3298 "pop %%"R"bp"
6aa8b732 3299 :
fb3f0f51 3300 : [svm]"a"(svm),
6aa8b732 3301 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3302 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3303 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3304 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3305 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3306 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3307 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3308#ifdef CONFIG_X86_64
ad312c7c
ZX		 3309 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3310 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3311 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3312 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3313 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3314 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3315 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3316 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3317#endif
54a08c04 3318 : "cc", "memory"
80e31d4f 3319 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3320#ifdef CONFIG_X86_64
54a08c04
LV		 3321 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3322#endif
3323 );
6aa8b732 3324
ad312c7c 3325 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3326 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3327 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3328 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3329
6aa8b732 3330 load_host_msrs(vcpu);
9581d442
AK		 3331 loadsegment(fs, fs_selector);
3332#ifdef CONFIG_X86_64
3333 load_gs_index(gs_selector);
3334 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
3335#else
3336 loadsegment(gs, gs_selector);
3337#endif
3338 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3339
3340 reload_tss(vcpu);
3341
56ba47dd
AK		 3342 local_irq_disable();
3343
3344 stgi();
3345
d7bf8221
JR		 3346 sync_cr8_to_lapic(vcpu);
3347
a2fa3e9f 3348 svm->next_rip = 0;
9222be18 3349
6de4f3ad
AK		 3350 if (npt_enabled) {
3351 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3352 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3353 }
fe5913e4
JR		 3354
3355 /*
3356 * We need to handle MC intercepts here before the vcpu has a chance to
3357 * change the physical cpu
3358 */
3359 if (unlikely(svm->vmcb->control.exit_code ==
3360 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3361 svm_handle_mce(svm);
6aa8b732
AK		 3362}
3363
80e31d4f
AK		 3364#undef R
3365
6aa8b732
AK		 3366static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3367{
a2fa3e9f
GH		 3368 struct vcpu_svm *svm = to_svm(vcpu);
3369
3370 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3371 force_new_asid(vcpu);
3372}
3373
1c97f0a0
JR		 3374static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3375{
3376 struct vcpu_svm *svm = to_svm(vcpu);
3377
3378 svm->vmcb->control.nested_cr3 = root;
3379
3380 /* Also sync guest cr3 here in case we live migrate */
3381 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3382
3383 force_new_asid(vcpu);
3384}
3385
6aa8b732
AK		 3386static int is_disabled(void)
3387{
6031a61c
JR		 3388 u64 vm_cr;
3389
3390 rdmsrl(MSR_VM_CR, vm_cr);
3391 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3392 return 1;
3393
6aa8b732
AK		 3394 return 0;
3395}
3396
102d8325
IM		 3397static void
3398svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3399{
3400 /*
3401 * Patch in the VMMCALL instruction:
3402 */
3403 hypercall[0] = 0x0f;
3404 hypercall[1] = 0x01;
3405 hypercall[2] = 0xd9;
102d8325
IM		 3406}
3407
002c7f7c
YS		 3408static void svm_check_processor_compat(void *rtn)
3409{
3410 *(int *)rtn = 0;
3411}
3412
774ead3a
AK		 3413static bool svm_cpu_has_accelerated_tpr(void)
3414{
3415 return false;
3416}
3417
67253af5
SY		 3418static int get_npt_level(void)
3419{
3420#ifdef CONFIG_X86_64
3421 return PT64_ROOT_LEVEL;
3422#else
3423 return PT32E_ROOT_LEVEL;
3424#endif
3425}
3426
4b12f0de 3427static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3428{
3429 return 0;
3430}
3431
0e851880
SY		 3432static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3433{
3434}
3435
d4330ef2
JR		 3436static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3437{
c2c63a49
JR		 3438 switch (func) {
3439 case 0x8000000A:
3440 entry->eax = 1; /* SVM revision 1 */
3441 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3442 ASID emulation to nested SVM */
3443 entry->ecx = 0; /* Reserved */
7a190667
JR		 3444 entry->edx = 0; /* Per default do not support any
3445 additional features */
3446
3447 /* Support next_rip if host supports it */
3448 if (svm_has(SVM_FEATURE_NRIP))
3449 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49
JR		 3450
3451 break;
3452 }
d4330ef2
JR		 3453}
3454
229456fc 3455static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3456 { SVM_EXIT_READ_CR0, "read_cr0" },
3457 { SVM_EXIT_READ_CR3, "read_cr3" },
3458 { SVM_EXIT_READ_CR4, "read_cr4" },
3459 { SVM_EXIT_READ_CR8, "read_cr8" },
3460 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3461 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3462 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3463 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3464 { SVM_EXIT_READ_DR0, "read_dr0" },
3465 { SVM_EXIT_READ_DR1, "read_dr1" },
3466 { SVM_EXIT_READ_DR2, "read_dr2" },
3467 { SVM_EXIT_READ_DR3, "read_dr3" },
3468 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3469 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3470 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3471 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3472 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3473 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3474 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3475 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3476 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3477 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3478 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3479 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3480 { SVM_EXIT_INTR, "interrupt" },
3481 { SVM_EXIT_NMI, "nmi" },
3482 { SVM_EXIT_SMI, "smi" },
3483 { SVM_EXIT_INIT, "init" },
3484 { SVM_EXIT_VINTR, "vintr" },
3485 { SVM_EXIT_CPUID, "cpuid" },
3486 { SVM_EXIT_INVD, "invd" },
3487 { SVM_EXIT_HLT, "hlt" },
3488 { SVM_EXIT_INVLPG, "invlpg" },
3489 { SVM_EXIT_INVLPGA, "invlpga" },
3490 { SVM_EXIT_IOIO, "io" },
3491 { SVM_EXIT_MSR, "msr" },
3492 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3493 { SVM_EXIT_SHUTDOWN, "shutdown" },
3494 { SVM_EXIT_VMRUN, "vmrun" },
3495 { SVM_EXIT_VMMCALL, "hypercall" },
3496 { SVM_EXIT_VMLOAD, "vmload" },
3497 { SVM_EXIT_VMSAVE, "vmsave" },
3498 { SVM_EXIT_STGI, "stgi" },
3499 { SVM_EXIT_CLGI, "clgi" },
3500 { SVM_EXIT_SKINIT, "skinit" },
3501 { SVM_EXIT_WBINVD, "wbinvd" },
3502 { SVM_EXIT_MONITOR, "monitor" },
3503 { SVM_EXIT_MWAIT, "mwait" },
3504 { SVM_EXIT_NPF, "npf" },
3505 { -1, NULL }
3506};
3507
17cc3935 3508static int svm_get_lpage_level(void)
344f414f 3509{
17cc3935 3510 return PT_PDPE_LEVEL;
344f414f
JR		 3511}
3512
4e47c7a6
SY		 3513static bool svm_rdtscp_supported(void)
3514{
3515 return false;
3516}
3517
f5f48ee1
SY		 3518static bool svm_has_wbinvd_exit(void)
3519{
3520 return true;
3521}
3522
02daab21
AK		 3523static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3524{
3525 struct vcpu_svm *svm = to_svm(vcpu);
3526
02daab21 3527 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3528 if (is_nested(svm))
3529 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3530 update_cr0_intercept(svm);
02daab21
AK		 3531}
3532
cbdd1bea 3533static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3534 .cpu_has_kvm_support = has_svm,
3535 .disabled_by_bios = is_disabled,
3536 .hardware_setup = svm_hardware_setup,
3537 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3538 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3539 .hardware_enable = svm_hardware_enable,
3540 .hardware_disable = svm_hardware_disable,
774ead3a 3541 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3542
3543 .vcpu_create = svm_create_vcpu,
3544 .vcpu_free = svm_free_vcpu,
04d2cc77 3545 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3546
04d2cc77 3547 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3548 .vcpu_load = svm_vcpu_load,
3549 .vcpu_put = svm_vcpu_put,
3550
3551 .set_guest_debug = svm_guest_debug,
3552 .get_msr = svm_get_msr,
3553 .set_msr = svm_set_msr,
3554 .get_segment_base = svm_get_segment_base,
3555 .get_segment = svm_get_segment,
3556 .set_segment = svm_set_segment,
2e4d2653 3557 .get_cpl = svm_get_cpl,
1747fb71 3558 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3559 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3560 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3561 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3562 .set_cr3 = svm_set_cr3,
3563 .set_cr4 = svm_set_cr4,
3564 .set_efer = svm_set_efer,
3565 .get_idt = svm_get_idt,
3566 .set_idt = svm_set_idt,
3567 .get_gdt = svm_get_gdt,
3568 .set_gdt = svm_set_gdt,
020df079 3569 .set_dr7 = svm_set_dr7,
6de4f3ad 3570 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3571 .get_rflags = svm_get_rflags,
3572 .set_rflags = svm_set_rflags,
6b52d186 3573 .fpu_activate = svm_fpu_activate,
02daab21 3574 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3575
6aa8b732 3576 .tlb_flush = svm_flush_tlb,
6aa8b732 3577
6aa8b732 3578 .run = svm_vcpu_run,
04d2cc77 3579 .handle_exit = handle_exit,
6aa8b732 3580 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3581 .set_interrupt_shadow = svm_set_interrupt_shadow,
3582 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3583 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3584 .set_irq = svm_set_irq,
95ba8273 3585 .set_nmi = svm_inject_nmi,
298101da 3586 .queue_exception = svm_queue_exception,
78646121 3587 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3588 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3589 .get_nmi_mask = svm_get_nmi_mask,
3590 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3591 .enable_nmi_window = enable_nmi_window,
3592 .enable_irq_window = enable_irq_window,
3593 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3594
3595 .set_tss_addr = svm_set_tss_addr,
67253af5 3596 .get_tdp_level = get_npt_level,
4b12f0de 3597 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3598
3599 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3600 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3601
3602 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3603
3604 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3605
3606 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3607
3608 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a
ZA		 3609
3610 .write_tsc_offset = svm_write_tsc_offset,
e48672fa 3611 .adjust_tsc_offset = svm_adjust_tsc_offset,
1c97f0a0
JR		 3612
3613 .set_tdp_cr3 = set_tdp_cr3,
6aa8b732
AK		 3614};
3615
3616static int __init svm_init(void)
3617{
cb498ea2 3618 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3619 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3620}
3621
3622static void __exit svm_exit(void)
3623{
cb498ea2 3624 kvm_exit();
6aa8b732
AK		 3625}
3626
3627module_init(svm_init)
3628module_exit(svm_exit)
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