]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/x86/kvm/svm.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: X86: Don't report L2 emulation failures to user-space
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
9611c187 7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
631bc487 34#include <asm/kvm_para.h>
6aa8b732 35
63d1142f 36#include <asm/virtext.h>
229456fc 37#include "trace.h"
63d1142f 38
4ecac3fd
AK		 39#define __ex(x) __kvm_handle_fault_on_reboot(x)
40
6aa8b732
AK		 41MODULE_AUTHOR("Qumranet");
42MODULE_LICENSE("GPL");
43
44#define IOPM_ALLOC_ORDER 2
45#define MSRPM_ALLOC_ORDER 1
46
6aa8b732
AK		 47#define SEG_TYPE_LDT 2
48#define SEG_TYPE_BUSY_TSS16 3
49
6bc31bdc
AP		 50#define SVM_FEATURE_NPT (1 << 0)
51#define SVM_FEATURE_LBRV (1 << 1)
52#define SVM_FEATURE_SVML (1 << 2)
53#define SVM_FEATURE_NRIP (1 << 3)
54#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 55
410e4d57
JR		 56#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
24e09cbf
JR		 60#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
67ec6607
JR		 62static bool erratum_383_found __read_mostly;
63
6c8166a7
AK		 64static const u32 host_save_user_msrs[] = {
65#ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68#endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70};
71
72#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74struct kvm_vcpu;
75
e6aa9abd
JR		 76struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
4a810181 79 u64 vm_cr_msr;
e6aa9abd
JR		 80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
ce2ac085 87 u64 vmcb_iopm;
aad42c64 88
cd3ff653
JR		 89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
cda00082
JR		 92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
aad42c64
JR		 100 /* cache for intercepts of the guest */
101 u16 intercept_cr_read;
102 u16 intercept_cr_write;
103 u16 intercept_dr_read;
104 u16 intercept_dr_write;
105 u32 intercept_exceptions;
106 u64 intercept;
107
5bd2edc3
JR		 108 /* Nested Paging related state */
109 u64 nested_cr3;
e6aa9abd
JR		 110};
111
323c3d80
JR		 112#define MSRPM_OFFSETS 16
113static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
114
6c8166a7
AK		 115struct vcpu_svm {
116 struct kvm_vcpu vcpu;
117 struct vmcb *vmcb;
118 unsigned long vmcb_pa;
119 struct svm_cpu_data *svm_data;
120 uint64_t asid_generation;
121 uint64_t sysenter_esp;
122 uint64_t sysenter_eip;
123
124 u64 next_rip;
125
126 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
afe9e66f 127 struct {
dacccfdd
AK		 128 u16 fs;
129 u16 gs;
130 u16 ldt;
afe9e66f
AK		 131 u64 gs_base;
132 } host;
6c8166a7
AK		 133
134 u32 *msrpm;
6c8166a7 135
e6aa9abd 136 struct nested_state nested;
6be7d306
JK		 137
138 bool nmi_singlestep;
66b7138f
JK		 139
140 unsigned int3_injected;
141 unsigned long int3_rip;
631bc487 142 u32 apf_reason;
6c8166a7
AK		 143};
144
455716fa
JR		 145#define MSR_INVALID 0xffffffffU
146
ac72a9b7
JR		 147static struct svm_direct_access_msrs {
148 u32 index; /* Index of the MSR */
149 bool always; /* True if intercept is always on */
150} direct_access_msrs[] = {
8c06585d 151 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 152 { .index = MSR_IA32_SYSENTER_CS, .always = true },
153#ifdef CONFIG_X86_64
154 { .index = MSR_GS_BASE, .always = true },
155 { .index = MSR_FS_BASE, .always = true },
156 { .index = MSR_KERNEL_GS_BASE, .always = true },
157 { .index = MSR_LSTAR, .always = true },
158 { .index = MSR_CSTAR, .always = true },
159 { .index = MSR_SYSCALL_MASK, .always = true },
160#endif
161 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
162 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
163 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
164 { .index = MSR_IA32_LASTINTTOIP, .always = false },
165 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 166};
167
709ddebf
JR		 168/* enable NPT for AMD64 and X86 with PAE */
169#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
170static bool npt_enabled = true;
171#else
e0231715 172static bool npt_enabled;
709ddebf 173#endif
6c7dac72
JR		 174static int npt = 1;
175
176module_param(npt, int, S_IRUGO);
e3da3acd 177
4b6e4dca 178static int nested = 1;
236de055
AG		 179module_param(nested, int, S_IRUGO);
180
44874f84 181static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 182static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 183
410e4d57 184static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 185static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 186static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 187static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
188 bool has_error_code, u32 error_code);
189
a2fa3e9f
GH		 190static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
191{
fb3f0f51 192 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 193}
194
2af9194d
JR		 195static inline void enable_gif(struct vcpu_svm *svm)
196{
197 svm->vcpu.arch.hflags |= HF_GIF_MASK;
198}
199
200static inline void disable_gif(struct vcpu_svm *svm)
201{
202 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
203}
204
205static inline bool gif_set(struct vcpu_svm *svm)
206{
207 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
208}
209
4866d5e3 210static unsigned long iopm_base;
6aa8b732
AK		 211
212struct kvm_ldttss_desc {
213 u16 limit0;
214 u16 base0;
e0231715
JR		 215 unsigned base1:8, type:5, dpl:2, p:1;
216 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 217 u32 base3;
218 u32 zero1;
219} __attribute__((packed));
220
221struct svm_cpu_data {
222 int cpu;
223
5008fdf5
AK		 224 u64 asid_generation;
225 u32 max_asid;
226 u32 next_asid;
6aa8b732
AK		 227 struct kvm_ldttss_desc *tss_desc;
228
229 struct page *save_area;
230};
231
232static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 233static uint32_t svm_features;
6aa8b732
AK		 234
235struct svm_init_data {
236 int cpu;
237 int r;
238};
239
240static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
241
9d8f549d 242#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 243#define MSRS_RANGE_SIZE 2048
244#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
245
455716fa
JR		 246static u32 svm_msrpm_offset(u32 msr)
247{
248 u32 offset;
249 int i;
250
251 for (i = 0; i < NUM_MSR_MAPS; i++) {
252 if (msr < msrpm_ranges[i] ||
253 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
254 continue;
255
256 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
257 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
258
259 /* Now we have the u8 offset - but need the u32 offset */
260 return offset / 4;
261 }
262
263 /* MSR not in any range */
264 return MSR_INVALID;
265}
266
6aa8b732
AK		 267#define MAX_INST_SIZE 15
268
6aa8b732
AK		 269static inline void clgi(void)
270{
4ecac3fd 271 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 272}
273
274static inline void stgi(void)
275{
4ecac3fd 276 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 277}
278
279static inline void invlpga(unsigned long addr, u32 asid)
280{
e0231715 281 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 282}
283
6aa8b732
AK		 284static inline void force_new_asid(struct kvm_vcpu *vcpu)
285{
a2fa3e9f 286 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 287}
288
289static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
290{
291 force_new_asid(vcpu);
292}
293
4b16184c
JR		 294static int get_npt_level(void)
295{
296#ifdef CONFIG_X86_64
297 return PT64_ROOT_LEVEL;
298#else
299 return PT32E_ROOT_LEVEL;
300#endif
301}
302
6aa8b732
AK		 303static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
304{
6dc696d4 305 vcpu->arch.efer = efer;
709ddebf 306 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 307 efer &= ~EFER_LME;
6aa8b732 308
9962d032 309 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
6aa8b732
AK		 310}
311
6aa8b732
AK		 312static int is_external_interrupt(u32 info)
313{
314 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
315 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
316}
317
2809f5d2
GC		 318static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
319{
320 struct vcpu_svm *svm = to_svm(vcpu);
321 u32 ret = 0;
322
323 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 324 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 325 return ret & mask;
326}
327
328static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
329{
330 struct vcpu_svm *svm = to_svm(vcpu);
331
332 if (mask == 0)
333 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
334 else
335 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
336
337}
338
6aa8b732
AK		 339static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
340{
a2fa3e9f
GH		 341 struct vcpu_svm *svm = to_svm(vcpu);
342
6bc31bdc
AP		 343 if (svm->vmcb->control.next_rip != 0)
344 svm->next_rip = svm->vmcb->control.next_rip;
345
a2fa3e9f 346 if (!svm->next_rip) {
851ba692 347 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 348 EMULATE_DONE)
349 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 350 return;
351 }
5fdbf976
MT		 352 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
353 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
354 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 355
5fdbf976 356 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 357 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 358}
359
116a4752 360static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 361 bool has_error_code, u32 error_code,
362 bool reinject)
116a4752
JK		 363{
364 struct vcpu_svm *svm = to_svm(vcpu);
365
e0231715
JR		 366 /*
367 * If we are within a nested VM we'd better #VMEXIT and let the guest
368 * handle the exception
369 */
ce7ddec4
JR		 370 if (!reinject &&
371 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 372 return;
373
2a6b20b8 374 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
66b7138f
JK		 375 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
376
377 /*
378 * For guest debugging where we have to reinject #BP if some
379 * INT3 is guest-owned:
380 * Emulate nRIP by moving RIP forward. Will fail if injection
381 * raises a fault that is not intercepted. Still better than
382 * failing in all cases.
383 */
384 skip_emulated_instruction(&svm->vcpu);
385 rip = kvm_rip_read(&svm->vcpu);
386 svm->int3_rip = rip + svm->vmcb->save.cs.base;
387 svm->int3_injected = rip - old_rip;
388 }
389
116a4752
JK		 390 svm->vmcb->control.event_inj = nr
391 | SVM_EVTINJ_VALID
392 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
393 | SVM_EVTINJ_TYPE_EXEPT;
394 svm->vmcb->control.event_inj_err = error_code;
395}
396
67ec6607
JR		 397static void svm_init_erratum_383(void)
398{
399 u32 low, high;
400 int err;
401 u64 val;
402
1be85a6d 403 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 404 return;
405
406 /* Use _safe variants to not break nested virtualization */
407 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
408 if (err)
409 return;
410
411 val |= (1ULL << 47);
412
413 low = lower_32_bits(val);
414 high = upper_32_bits(val);
415
416 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
417
418 erratum_383_found = true;
419}
420
6aa8b732
AK		 421static int has_svm(void)
422{
63d1142f 423 const char *msg;
6aa8b732 424
63d1142f 425 if (!cpu_has_svm(&msg)) {
ff81ff10 426 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 427 return 0;
428 }
429
6aa8b732
AK		 430 return 1;
431}
432
433static void svm_hardware_disable(void *garbage)
434{
2c8dceeb 435 cpu_svm_disable();
6aa8b732
AK		 436}
437
10474ae8 438static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 439{
440
0fe1e009 441 struct svm_cpu_data *sd;
6aa8b732 442 uint64_t efer;
89a27f4d 443 struct desc_ptr gdt_descr;
6aa8b732
AK		 444 struct desc_struct *gdt;
445 int me = raw_smp_processor_id();
446
10474ae8
AG		 447 rdmsrl(MSR_EFER, efer);
448 if (efer & EFER_SVME)
449 return -EBUSY;
450
6aa8b732 451 if (!has_svm()) {
e6732a5a
ZA		 452 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
453 me);
10474ae8 454 return -EINVAL;
6aa8b732 455 }
0fe1e009 456 sd = per_cpu(svm_data, me);
6aa8b732 457
0fe1e009 458 if (!sd) {
e6732a5a 459 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 460 me);
10474ae8 461 return -EINVAL;
6aa8b732
AK		 462 }
463
0fe1e009
TH		 464 sd->asid_generation = 1;
465 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
466 sd->next_asid = sd->max_asid + 1;
6aa8b732 467
d6ab1ed4 468 native_store_gdt(&gdt_descr);
89a27f4d 469 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 470 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 471
9962d032 472 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 473
d0316554 474 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 475
67ec6607
JR		 476 svm_init_erratum_383();
477
10474ae8 478 return 0;
6aa8b732
AK		 479}
480
0da1db75
JR		 481static void svm_cpu_uninit(int cpu)
482{
0fe1e009 483 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 484
0fe1e009 485 if (!sd)
0da1db75
JR		 486 return;
487
488 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 489 __free_page(sd->save_area);
490 kfree(sd);
0da1db75
JR		 491}
492
6aa8b732
AK		 493static int svm_cpu_init(int cpu)
494{
0fe1e009 495 struct svm_cpu_data *sd;
6aa8b732
AK		 496 int r;
497
0fe1e009
TH		 498 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
499 if (!sd)
6aa8b732 500 return -ENOMEM;
0fe1e009
TH		 501 sd->cpu = cpu;
502 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 503 r = -ENOMEM;
0fe1e009 504 if (!sd->save_area)
6aa8b732
AK		 505 goto err_1;
506
0fe1e009 507 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 508
509 return 0;
510
511err_1:
0fe1e009 512 kfree(sd);
6aa8b732
AK		 513 return r;
514
515}
516
ac72a9b7
JR		 517static bool valid_msr_intercept(u32 index)
518{
519 int i;
520
521 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
522 if (direct_access_msrs[i].index == index)
523 return true;
524
525 return false;
526}
527
bfc733a7
RR		 528static void set_msr_interception(u32 *msrpm, unsigned msr,
529 int read, int write)
6aa8b732 530{
455716fa
JR		 531 u8 bit_read, bit_write;
532 unsigned long tmp;
533 u32 offset;
6aa8b732 534
ac72a9b7
JR		 535 /*
536 * If this warning triggers extend the direct_access_msrs list at the
537 * beginning of the file
538 */
539 WARN_ON(!valid_msr_intercept(msr));
540
455716fa
JR		 541 offset = svm_msrpm_offset(msr);
542 bit_read = 2 * (msr & 0x0f);
543 bit_write = 2 * (msr & 0x0f) + 1;
544 tmp = msrpm[offset];
545
546 BUG_ON(offset == MSR_INVALID);
547
548 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
549 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
550
551 msrpm[offset] = tmp;
6aa8b732
AK		 552}
553
f65c229c 554static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 555{
556 int i;
557
f65c229c
JR		 558 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
559
ac72a9b7
JR		 560 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
561 if (!direct_access_msrs[i].always)
562 continue;
563
564 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
565 }
f65c229c
JR		 566}
567
323c3d80
JR		 568static void add_msr_offset(u32 offset)
569{
570 int i;
571
572 for (i = 0; i < MSRPM_OFFSETS; ++i) {
573
574 /* Offset already in list? */
575 if (msrpm_offsets[i] == offset)
bfc733a7 576 return;
323c3d80
JR		 577
578 /* Slot used by another offset? */
579 if (msrpm_offsets[i] != MSR_INVALID)
580 continue;
581
582 /* Add offset to list */
583 msrpm_offsets[i] = offset;
584
585 return;
6aa8b732 586 }
323c3d80
JR		 587
588 /*
589 * If this BUG triggers the msrpm_offsets table has an overflow. Just
590 * increase MSRPM_OFFSETS in this case.
591 */
bfc733a7 592 BUG();
6aa8b732
AK		 593}
594
323c3d80 595static void init_msrpm_offsets(void)
f65c229c 596{
323c3d80 597 int i;
f65c229c 598
323c3d80
JR		 599 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
600
601 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
602 u32 offset;
603
604 offset = svm_msrpm_offset(direct_access_msrs[i].index);
605 BUG_ON(offset == MSR_INVALID);
606
607 add_msr_offset(offset);
608 }
f65c229c
JR		 609}
610
24e09cbf
JR		 611static void svm_enable_lbrv(struct vcpu_svm *svm)
612{
613 u32 *msrpm = svm->msrpm;
614
615 svm->vmcb->control.lbr_ctl = 1;
616 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
617 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
618 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
619 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
620}
621
622static void svm_disable_lbrv(struct vcpu_svm *svm)
623{
624 u32 *msrpm = svm->msrpm;
625
626 svm->vmcb->control.lbr_ctl = 0;
627 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
628 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
629 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
630 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
631}
632
6aa8b732
AK		 633static __init int svm_hardware_setup(void)
634{
635 int cpu;
636 struct page *iopm_pages;
f65c229c 637 void *iopm_va;
6aa8b732
AK		 638 int r;
639
6aa8b732
AK		 640 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
641
642 if (!iopm_pages)
643 return -ENOMEM;
c8681339
AL		 644
645 iopm_va = page_address(iopm_pages);
646 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 647 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
648
323c3d80
JR		 649 init_msrpm_offsets();
650
50a37eb4
JR		 651 if (boot_cpu_has(X86_FEATURE_NX))
652 kvm_enable_efer_bits(EFER_NX);
653
1b2fd70c
AG		 654 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
655 kvm_enable_efer_bits(EFER_FFXSR);
656
236de055
AG		 657 if (nested) {
658 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 659 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 660 }
661
3230bb47 662 for_each_possible_cpu(cpu) {
6aa8b732
AK		 663 r = svm_cpu_init(cpu);
664 if (r)
f65c229c 665 goto err;
6aa8b732 666 }
33bd6a0b
JR		 667
668 svm_features = cpuid_edx(SVM_CPUID_FUNC);
669
2a6b20b8 670 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 671 npt_enabled = false;
672
6c7dac72
JR		 673 if (npt_enabled && !npt) {
674 printk(KERN_INFO "kvm: Nested Paging disabled\n");
675 npt_enabled = false;
676 }
677
18552672 678 if (npt_enabled) {
e3da3acd 679 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 680 kvm_enable_tdp();
5f4cb662
JR		 681 } else
682 kvm_disable_tdp();
e3da3acd 683
6aa8b732
AK		 684 return 0;
685
f65c229c 686err:
6aa8b732
AK		 687 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
688 iopm_base = 0;
689 return r;
690}
691
692static __exit void svm_hardware_unsetup(void)
693{
0da1db75
JR		 694 int cpu;
695
3230bb47 696 for_each_possible_cpu(cpu)
0da1db75
JR		 697 svm_cpu_uninit(cpu);
698
6aa8b732 699 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 700 iopm_base = 0;
6aa8b732
AK		 701}
702
703static void init_seg(struct vmcb_seg *seg)
704{
705 seg->selector = 0;
706 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 707 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 708 seg->limit = 0xffff;
709 seg->base = 0;
710}
711
712static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
713{
714 seg->selector = 0;
715 seg->attrib = SVM_SELECTOR_P_MASK | type;
716 seg->limit = 0xffff;
717 seg->base = 0;
718}
719
f4e1b3c8
ZA		 720static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
721{
722 struct vcpu_svm *svm = to_svm(vcpu);
723 u64 g_tsc_offset = 0;
724
2030753d 725 if (is_guest_mode(vcpu)) {
f4e1b3c8
ZA		 726 g_tsc_offset = svm->vmcb->control.tsc_offset -
727 svm->nested.hsave->control.tsc_offset;
728 svm->nested.hsave->control.tsc_offset = offset;
729 }
730
731 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
732}
733
e48672fa
ZA		 734static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
735{
736 struct vcpu_svm *svm = to_svm(vcpu);
737
738 svm->vmcb->control.tsc_offset += adjustment;
2030753d 739 if (is_guest_mode(vcpu))
e48672fa
ZA		 740 svm->nested.hsave->control.tsc_offset += adjustment;
741}
742
e6101a96 743static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 744{
e6101a96
JR		 745 struct vmcb_control_area *control = &svm->vmcb->control;
746 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 747
bff78274
AK		 748 svm->vcpu.fpu_active = 1;
749
e0231715 750 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 751 INTERCEPT_CR3_MASK |
649d6864 752 INTERCEPT_CR4_MASK;
6aa8b732 753
e0231715 754 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 755 INTERCEPT_CR3_MASK |
80a8119c
AK		 756 INTERCEPT_CR4_MASK |
757 INTERCEPT_CR8_MASK;
6aa8b732 758
e0231715 759 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 760 INTERCEPT_DR1_MASK |
761 INTERCEPT_DR2_MASK |
727f5a23
JK		 762 INTERCEPT_DR3_MASK |
763 INTERCEPT_DR4_MASK |
764 INTERCEPT_DR5_MASK |
765 INTERCEPT_DR6_MASK |
766 INTERCEPT_DR7_MASK;
6aa8b732 767
e0231715 768 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 769 INTERCEPT_DR1_MASK |
770 INTERCEPT_DR2_MASK |
771 INTERCEPT_DR3_MASK |
727f5a23 772 INTERCEPT_DR4_MASK |
6aa8b732 773 INTERCEPT_DR5_MASK |
727f5a23 774 INTERCEPT_DR6_MASK |
6aa8b732
AK		 775 INTERCEPT_DR7_MASK;
776
7aa81cc0 777 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 778 (1 << UD_VECTOR) |
779 (1 << MC_VECTOR);
6aa8b732
AK		 780
781
e0231715 782 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 783 (1ULL << INTERCEPT_NMI) |
0152527b 784 (1ULL << INTERCEPT_SMI) |
d225157b 785 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 786 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 787 (1ULL << INTERCEPT_INVD) |
6aa8b732 788 (1ULL << INTERCEPT_HLT) |
a7052897 789 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 790 (1ULL << INTERCEPT_INVLPGA) |
791 (1ULL << INTERCEPT_IOIO_PROT) |
792 (1ULL << INTERCEPT_MSR_PROT) |
793 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 794 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 795 (1ULL << INTERCEPT_VMRUN) |
796 (1ULL << INTERCEPT_VMMCALL) |
797 (1ULL << INTERCEPT_VMLOAD) |
798 (1ULL << INTERCEPT_VMSAVE) |
799 (1ULL << INTERCEPT_STGI) |
800 (1ULL << INTERCEPT_CLGI) |
916ce236 801 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 802 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 803 (1ULL << INTERCEPT_MONITOR) |
804 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 805
806 control->iopm_base_pa = iopm_base;
f65c229c 807 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 808 control->int_ctl = V_INTR_MASKING_MASK;
809
810 init_seg(&save->es);
811 init_seg(&save->ss);
812 init_seg(&save->ds);
813 init_seg(&save->fs);
814 init_seg(&save->gs);
815
816 save->cs.selector = 0xf000;
817 /* Executable/Readable Code Segment */
818 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
819 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
820 save->cs.limit = 0xffff;
d92899a0
AK		 821 /*
822 * cs.base should really be 0xffff0000, but vmx can't handle that, so
823 * be consistent with it.
824 *
825 * Replace when we have real mode working for vmx.
826 */
827 save->cs.base = 0xf0000;
6aa8b732
AK		 828
829 save->gdtr.limit = 0xffff;
830 save->idtr.limit = 0xffff;
831
832 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
833 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
834
eaa48512 835 svm_set_efer(&svm->vcpu, 0);
d77c26fc 836 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 837 save->dr7 = 0x400;
838 save->rflags = 2;
839 save->rip = 0x0000fff0;
5fdbf976 840 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 841
e0231715
JR		 842 /*
843 * This is the guest-visible cr0 value.
18fa000a 844 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 845 */
678041ad
MT		 846 svm->vcpu.arch.cr0 = 0;
847 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
18fa000a 848
66aee91a 849 save->cr4 = X86_CR4_PAE;
6aa8b732 850 /* rdx = ?? */
709ddebf
JR		 851
852 if (npt_enabled) {
853 /* Setup VMCB for Nested Paging */
854 control->nested_ctl = 1;
a7052897
MT		 855 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
856 (1ULL << INTERCEPT_INVLPG));
709ddebf 857 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 858 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
859 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 860 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 861 save->cr3 = 0;
862 save->cr4 = 0;
863 }
a79d2f18 864 force_new_asid(&svm->vcpu);
1371d904 865
e6aa9abd 866 svm->nested.vmcb = 0;
2af9194d
JR		 867 svm->vcpu.arch.hflags = 0;
868
2a6b20b8 869 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
565d0998
ML		 870 control->pause_filter_count = 3000;
871 control->intercept |= (1ULL << INTERCEPT_PAUSE);
872 }
873
2af9194d 874 enable_gif(svm);
6aa8b732
AK		 875}
876
e00c8cf2 877static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 878{
879 struct vcpu_svm *svm = to_svm(vcpu);
880
e6101a96 881 init_vmcb(svm);
70433389 882
c5af89b6 883 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 884 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 885 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
886 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 887 }
5fdbf976
MT		 888 vcpu->arch.regs_avail = ~0;
889 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 890
891 return 0;
04d2cc77
AK		 892}
893
fb3f0f51 894static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 895{
a2fa3e9f 896 struct vcpu_svm *svm;
6aa8b732 897 struct page *page;
f65c229c 898 struct page *msrpm_pages;
b286d5d8 899 struct page *hsave_page;
3d6368ef 900 struct page *nested_msrpm_pages;
fb3f0f51 901 int err;
6aa8b732 902
c16f862d 903 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 904 if (!svm) {
905 err = -ENOMEM;
906 goto out;
907 }
908
909 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
910 if (err)
911 goto free_svm;
912
b7af4043 913 err = -ENOMEM;
6aa8b732 914 page = alloc_page(GFP_KERNEL);
b7af4043 915 if (!page)
fb3f0f51 916 goto uninit;
6aa8b732 917
f65c229c
JR		 918 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
919 if (!msrpm_pages)
b7af4043 920 goto free_page1;
3d6368ef
AG		 921
922 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
923 if (!nested_msrpm_pages)
b7af4043 924 goto free_page2;
f65c229c 925
b286d5d8
AG		 926 hsave_page = alloc_page(GFP_KERNEL);
927 if (!hsave_page)
b7af4043
TY		 928 goto free_page3;
929
e6aa9abd 930 svm->nested.hsave = page_address(hsave_page);
b286d5d8 931
b7af4043
TY		 932 svm->msrpm = page_address(msrpm_pages);
933 svm_vcpu_init_msrpm(svm->msrpm);
934
e6aa9abd 935 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 936 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 937
a2fa3e9f
GH		 938 svm->vmcb = page_address(page);
939 clear_page(svm->vmcb);
940 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
941 svm->asid_generation = 0;
e6101a96 942 init_vmcb(svm);
99e3e30a 943 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 944
10ab25cd
JK		 945 err = fx_init(&svm->vcpu);
946 if (err)
947 goto free_page4;
948
ad312c7c 949 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 950 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 951 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 952
fb3f0f51 953 return &svm->vcpu;
36241b8c 954
10ab25cd
JK		 955free_page4:
956 __free_page(hsave_page);
b7af4043
TY		 957free_page3:
958 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
959free_page2:
960 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
961free_page1:
962 __free_page(page);
fb3f0f51
RR		 963uninit:
964 kvm_vcpu_uninit(&svm->vcpu);
965free_svm:
a4770347 966 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 967out:
968 return ERR_PTR(err);
6aa8b732
AK		 969}
970
971static void svm_free_vcpu(struct kvm_vcpu *vcpu)
972{
a2fa3e9f
GH		 973 struct vcpu_svm *svm = to_svm(vcpu);
974
fb3f0f51 975 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 976 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 977 __free_page(virt_to_page(svm->nested.hsave));
978 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 979 kvm_vcpu_uninit(vcpu);
a4770347 980 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 981}
982
15ad7146 983static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 984{
a2fa3e9f 985 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 986 int i;
0cc5064d 987
0cc5064d 988 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 989 svm->asid_generation = 0;
0cc5064d 990 }
94dfbdb3 991
82ca2d10
AK		 992#ifdef CONFIG_X86_64
993 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
994#endif
dacccfdd
AK		 995 savesegment(fs, svm->host.fs);
996 savesegment(gs, svm->host.gs);
997 svm->host.ldt = kvm_read_ldt();
998
94dfbdb3 999 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1000 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1001}
1002
1003static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1004{
a2fa3e9f 1005 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1006 int i;
1007
e1beb1d3 1008 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1009 kvm_load_ldt(svm->host.ldt);
1010#ifdef CONFIG_X86_64
1011 loadsegment(fs, svm->host.fs);
1012 load_gs_index(svm->host.gs);
1013 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1014#else
1015 loadsegment(gs, svm->host.gs);
1016#endif
94dfbdb3 1017 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1018 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1019}
1020
6aa8b732
AK		 1021static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1022{
a2fa3e9f 1023 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 1024}
1025
1026static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1027{
a2fa3e9f 1028 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1029}
1030
6de4f3ad
AK		 1031static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1032{
1033 switch (reg) {
1034 case VCPU_EXREG_PDPTR:
1035 BUG_ON(!npt_enabled);
ff03a073 1036 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
6de4f3ad
AK		 1037 break;
1038 default:
1039 BUG();
1040 }
1041}
1042
f0b85051
AG		 1043static void svm_set_vintr(struct vcpu_svm *svm)
1044{
1045 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1046}
1047
1048static void svm_clear_vintr(struct vcpu_svm *svm)
1049{
1050 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1051}
1052
6aa8b732
AK		 1053static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1054{
a2fa3e9f 1055 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1056
1057 switch (seg) {
1058 case VCPU_SREG_CS: return &save->cs;
1059 case VCPU_SREG_DS: return &save->ds;
1060 case VCPU_SREG_ES: return &save->es;
1061 case VCPU_SREG_FS: return &save->fs;
1062 case VCPU_SREG_GS: return &save->gs;
1063 case VCPU_SREG_SS: return &save->ss;
1064 case VCPU_SREG_TR: return &save->tr;
1065 case VCPU_SREG_LDTR: return &save->ldtr;
1066 }
1067 BUG();
8b6d44c7 1068 return NULL;
6aa8b732
AK		 1069}
1070
1071static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1072{
1073 struct vmcb_seg *s = svm_seg(vcpu, seg);
1074
1075 return s->base;
1076}
1077
1078static void svm_get_segment(struct kvm_vcpu *vcpu,
1079 struct kvm_segment *var, int seg)
1080{
1081 struct vmcb_seg *s = svm_seg(vcpu, seg);
1082
1083 var->base = s->base;
1084 var->limit = s->limit;
1085 var->selector = s->selector;
1086 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1087 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1088 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1089 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1090 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1091 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1092 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1093 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1094
e0231715
JR		 1095 /*
1096 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1097 * for cross vendor migration purposes by "not present"
1098 */
1099 var->unusable = !var->present || (var->type == 0);
1100
1fbdc7a5
AP		 1101 switch (seg) {
1102 case VCPU_SREG_CS:
1103 /*
1104 * SVM always stores 0 for the 'G' bit in the CS selector in
1105 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1106 * Intel's VMENTRY has a check on the 'G' bit.
1107 */
25022acc 1108 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1109 break;
1110 case VCPU_SREG_TR:
1111 /*
1112 * Work around a bug where the busy flag in the tr selector
1113 * isn't exposed
1114 */
c0d09828 1115 var->type |= 0x2;
1fbdc7a5
AP		 1116 break;
1117 case VCPU_SREG_DS:
1118 case VCPU_SREG_ES:
1119 case VCPU_SREG_FS:
1120 case VCPU_SREG_GS:
1121 /*
1122 * The accessed bit must always be set in the segment
1123 * descriptor cache, although it can be cleared in the
1124 * descriptor, the cached bit always remains at 1. Since
1125 * Intel has a check on this, set it here to support
1126 * cross-vendor migration.
1127 */
1128 if (!var->unusable)
1129 var->type |= 0x1;
1130 break;
b586eb02 1131 case VCPU_SREG_SS:
e0231715
JR		 1132 /*
1133 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1134 * descriptor is left as 1, although the whole segment has
1135 * been made unusable. Clear it here to pass an Intel VMX
1136 * entry check when cross vendor migrating.
1137 */
1138 if (var->unusable)
1139 var->db = 0;
1140 break;
1fbdc7a5 1141 }
6aa8b732
AK		 1142}
1143
2e4d2653
IE		 1144static int svm_get_cpl(struct kvm_vcpu *vcpu)
1145{
1146 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1147
1148 return save->cpl;
1149}
1150
89a27f4d 1151static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1152{
a2fa3e9f
GH		 1153 struct vcpu_svm *svm = to_svm(vcpu);
1154
89a27f4d
GN		 1155 dt->size = svm->vmcb->save.idtr.limit;
1156 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1157}
1158
89a27f4d 1159static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1160{
a2fa3e9f
GH		 1161 struct vcpu_svm *svm = to_svm(vcpu);
1162
89a27f4d
GN		 1163 svm->vmcb->save.idtr.limit = dt->size;
1164 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1165}
1166
89a27f4d 1167static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1168{
a2fa3e9f
GH		 1169 struct vcpu_svm *svm = to_svm(vcpu);
1170
89a27f4d
GN		 1171 dt->size = svm->vmcb->save.gdtr.limit;
1172 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1173}
1174
89a27f4d 1175static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1176{
a2fa3e9f
GH		 1177 struct vcpu_svm *svm = to_svm(vcpu);
1178
89a27f4d
GN		 1179 svm->vmcb->save.gdtr.limit = dt->size;
1180 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1181}
1182
e8467fda
AK		 1183static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1184{
1185}
1186
25c4c276 1187static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1188{
1189}
1190
d225157b
AK		 1191static void update_cr0_intercept(struct vcpu_svm *svm)
1192{
66a562f7 1193 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1194 ulong gcr0 = svm->vcpu.arch.cr0;
1195 u64 *hcr0 = &svm->vmcb->save.cr0;
1196
1197 if (!svm->vcpu.fpu_active)
1198 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1199 else
1200 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1201 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1202
1203
1204 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1205 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1206 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
2030753d 1207 if (is_guest_mode(&svm->vcpu)) {
66a562f7
JR		 1208 struct vmcb *hsave = svm->nested.hsave;
1209
1210 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1211 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1212 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1213 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1214 }
d225157b
AK		 1215 } else {
1216 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1217 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
2030753d 1218 if (is_guest_mode(&svm->vcpu)) {
66a562f7
JR		 1219 struct vmcb *hsave = svm->nested.hsave;
1220
1221 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1222 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1223 }
d225157b
AK		 1224 }
1225}
1226
6aa8b732
AK		 1227static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1228{
a2fa3e9f
GH		 1229 struct vcpu_svm *svm = to_svm(vcpu);
1230
2030753d 1231 if (is_guest_mode(vcpu)) {
7f5d8b56
JR		 1232 /*
1233 * We are here because we run in nested mode, the host kvm
1234 * intercepts cr0 writes but the l1 hypervisor does not.
1235 * But the L1 hypervisor may intercept selective cr0 writes.
1236 * This needs to be checked here.
1237 */
1238 unsigned long old, new;
1239
1240 /* Remove bits that would trigger a real cr0 write intercept */
1241 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1242 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1243
1244 if (old == new) {
1245 /* cr0 write with ts and mp unchanged */
1246 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
cda00082
JR		 1247 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1248 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1249 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1250 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7f5d8b56 1251 return;
cda00082 1252 }
7f5d8b56
JR		 1253 }
1254 }
1255
05b3e0c2 1256#ifdef CONFIG_X86_64
f6801dff 1257 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1258 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1259 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1260 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1261 }
1262
d77c26fc 1263 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1264 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1265 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1266 }
1267 }
1268#endif
ad312c7c 1269 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1270
1271 if (!npt_enabled)
1272 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1273
1274 if (!vcpu->fpu_active)
334df50a 1275 cr0 |= X86_CR0_TS;
709ddebf
JR		 1276 /*
1277 * re-enable caching here because the QEMU bios
1278 * does not do it - this results in some delay at
1279 * reboot
1280 */
1281 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1282 svm->vmcb->save.cr0 = cr0;
d225157b 1283 update_cr0_intercept(svm);
6aa8b732
AK		 1284}
1285
1286static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1287{
6394b649 1288 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1289 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1290
1291 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1292 force_new_asid(vcpu);
6394b649 1293
ec077263
JR		 1294 vcpu->arch.cr4 = cr4;
1295 if (!npt_enabled)
1296 cr4 |= X86_CR4_PAE;
6394b649 1297 cr4 |= host_cr4_mce;
ec077263 1298 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1299}
1300
1301static void svm_set_segment(struct kvm_vcpu *vcpu,
1302 struct kvm_segment *var, int seg)
1303{
a2fa3e9f 1304 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1305 struct vmcb_seg *s = svm_seg(vcpu, seg);
1306
1307 s->base = var->base;
1308 s->limit = var->limit;
1309 s->selector = var->selector;
1310 if (var->unusable)
1311 s->attrib = 0;
1312 else {
1313 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1314 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1315 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1316 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1317 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1318 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1319 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1320 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1321 }
1322 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1323 svm->vmcb->save.cpl
1324 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1325 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1326
1327}
1328
44c11430 1329static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1330{
d0bfb940
JK		 1331 struct vcpu_svm *svm = to_svm(vcpu);
1332
d0bfb940
JK		 1333 svm->vmcb->control.intercept_exceptions &=
1334 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1335
6be7d306 1336 if (svm->nmi_singlestep)
44c11430
GN		 1337 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1338
d0bfb940
JK		 1339 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1340 if (vcpu->guest_debug &
1341 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1342 svm->vmcb->control.intercept_exceptions |=
1343 1 << DB_VECTOR;
1344 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1345 svm->vmcb->control.intercept_exceptions |=
1346 1 << BP_VECTOR;
1347 } else
1348 vcpu->guest_debug = 0;
44c11430
GN		 1349}
1350
355be0b9 1351static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1352{
44c11430
GN		 1353 struct vcpu_svm *svm = to_svm(vcpu);
1354
ae675ef0
JK		 1355 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1356 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1357 else
1358 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1359
355be0b9 1360 update_db_intercept(vcpu);
6aa8b732
AK		 1361}
1362
0fe1e009 1363static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1364{
0fe1e009
TH		 1365 if (sd->next_asid > sd->max_asid) {
1366 ++sd->asid_generation;
1367 sd->next_asid = 1;
a2fa3e9f 1368 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1369 }
1370
0fe1e009
TH		 1371 svm->asid_generation = sd->asid_generation;
1372 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1373}
1374
020df079 1375static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1376{
42dbaa5a 1377 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1378
020df079 1379 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1380}
1381
851ba692 1382static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1383{
631bc487 1384 u64 fault_address = svm->vmcb->control.exit_info_2;
6aa8b732 1385 u32 error_code;
631bc487 1386 int r = 1;
6aa8b732 1387
631bc487
GN		 1388 switch (svm->apf_reason) {
1389 default:
1390 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1391
631bc487
GN		 1392 trace_kvm_page_fault(fault_address, error_code);
1393 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1394 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1395 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1396 break;
1397 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1398 svm->apf_reason = 0;
1399 local_irq_disable();
1400 kvm_async_pf_task_wait(fault_address);
1401 local_irq_enable();
1402 break;
1403 case KVM_PV_REASON_PAGE_READY:
1404 svm->apf_reason = 0;
1405 local_irq_disable();
1406 kvm_async_pf_task_wake(fault_address);
1407 local_irq_enable();
1408 break;
1409 }
1410 return r;
6aa8b732
AK		 1411}
1412
851ba692 1413static int db_interception(struct vcpu_svm *svm)
d0bfb940 1414{
851ba692
AK		 1415 struct kvm_run *kvm_run = svm->vcpu.run;
1416
d0bfb940 1417 if (!(svm->vcpu.guest_debug &
44c11430 1418 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1419 !svm->nmi_singlestep) {
d0bfb940
JK		 1420 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1421 return 1;
1422 }
44c11430 1423
6be7d306
JK		 1424 if (svm->nmi_singlestep) {
1425 svm->nmi_singlestep = false;
44c11430
GN		 1426 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1427 svm->vmcb->save.rflags &=
1428 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1429 update_db_intercept(&svm->vcpu);
1430 }
1431
1432 if (svm->vcpu.guest_debug &
e0231715 1433 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1434 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1435 kvm_run->debug.arch.pc =
1436 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1437 kvm_run->debug.arch.exception = DB_VECTOR;
1438 return 0;
1439 }
1440
1441 return 1;
d0bfb940
JK		 1442}
1443
851ba692 1444static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1445{
851ba692
AK		 1446 struct kvm_run *kvm_run = svm->vcpu.run;
1447
d0bfb940
JK		 1448 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1449 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1450 kvm_run->debug.arch.exception = BP_VECTOR;
1451 return 0;
1452}
1453
851ba692 1454static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1455{
1456 int er;
1457
851ba692 1458 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1459 if (er != EMULATE_DONE)
7ee5d940 1460 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1461 return 1;
1462}
1463
6b52d186 1464static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1465{
6b52d186 1466 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1467 u32 excp;
1468
2030753d 1469 if (is_guest_mode(vcpu)) {
66a562f7
JR		 1470 u32 h_excp, n_excp;
1471
1472 h_excp = svm->nested.hsave->control.intercept_exceptions;
1473 n_excp = svm->nested.intercept_exceptions;
1474 h_excp &= ~(1 << NM_VECTOR);
1475 excp = h_excp | n_excp;
1476 } else {
1477 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1478 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1479 }
1480
1481 svm->vmcb->control.intercept_exceptions = excp;
1482
e756fc62 1483 svm->vcpu.fpu_active = 1;
d225157b 1484 update_cr0_intercept(svm);
6b52d186 1485}
a2fa3e9f 1486
6b52d186
AK		 1487static int nm_interception(struct vcpu_svm *svm)
1488{
1489 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1490 return 1;
7807fa6c
AL		 1491}
1492
67ec6607
JR		 1493static bool is_erratum_383(void)
1494{
1495 int err, i;
1496 u64 value;
1497
1498 if (!erratum_383_found)
1499 return false;
1500
1501 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1502 if (err)
1503 return false;
1504
1505 /* Bit 62 may or may not be set for this mce */
1506 value &= ~(1ULL << 62);
1507
1508 if (value != 0xb600000000010015ULL)
1509 return false;
1510
1511 /* Clear MCi_STATUS registers */
1512 for (i = 0; i < 6; ++i)
1513 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1514
1515 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1516 if (!err) {
1517 u32 low, high;
1518
1519 value &= ~(1ULL << 2);
1520 low = lower_32_bits(value);
1521 high = upper_32_bits(value);
1522
1523 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1524 }
1525
1526 /* Flush tlb to evict multi-match entries */
1527 __flush_tlb_all();
1528
1529 return true;
1530}
1531
fe5913e4 1532static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1533{
67ec6607
JR		 1534 if (is_erratum_383()) {
1535 /*
1536 * Erratum 383 triggered. Guest state is corrupt so kill the
1537 * guest.
1538 */
1539 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1540
a8eeb04a 1541 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1542
1543 return;
1544 }
1545
53371b50
JR		 1546 /*
1547 * On an #MC intercept the MCE handler is not called automatically in
1548 * the host. So do it by hand here.
1549 */
1550 asm volatile (
1551 "int $0x12\n");
1552 /* not sure if we ever come back to this point */
1553
fe5913e4
JR		 1554 return;
1555}
1556
1557static int mc_interception(struct vcpu_svm *svm)
1558{
53371b50
JR		 1559 return 1;
1560}
1561
851ba692 1562static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1563{
851ba692
AK		 1564 struct kvm_run *kvm_run = svm->vcpu.run;
1565
46fe4ddd
JR		 1566 /*
1567 * VMCB is undefined after a SHUTDOWN intercept
1568 * so reinitialize it.
1569 */
a2fa3e9f 1570 clear_page(svm->vmcb);
e6101a96 1571 init_vmcb(svm);
46fe4ddd
JR		 1572
1573 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1574 return 0;
1575}
1576
851ba692 1577static int io_interception(struct vcpu_svm *svm)
6aa8b732 1578{
cf8f70bf 1579 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1580 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1581 int size, in, string;
039576c0 1582 unsigned port;
6aa8b732 1583
e756fc62 1584 ++svm->vcpu.stat.io_exits;
e70669ab 1585 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1586 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1587 if (string || in)
6d77dbfc 1588 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1589
039576c0
AK		 1590 port = io_info >> 16;
1591 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1592 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1593 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1594
1595 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1596}
1597
851ba692 1598static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1599{
1600 return 1;
1601}
1602
851ba692 1603static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1604{
1605 ++svm->vcpu.stat.irq_exits;
1606 return 1;
1607}
1608
851ba692 1609static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1610{
1611 return 1;
1612}
1613
851ba692 1614static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1615{
5fdbf976 1616 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1617 skip_emulated_instruction(&svm->vcpu);
1618 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1619}
1620
851ba692 1621static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1622{
5fdbf976 1623 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1624 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1625 kvm_emulate_hypercall(&svm->vcpu);
1626 return 1;
02e235bc
AK		 1627}
1628
5bd2edc3
JR		 1629static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1630{
1631 struct vcpu_svm *svm = to_svm(vcpu);
1632
1633 return svm->nested.nested_cr3;
1634}
1635
1636static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1637 unsigned long root)
1638{
1639 struct vcpu_svm *svm = to_svm(vcpu);
1640
1641 svm->vmcb->control.nested_cr3 = root;
1642 force_new_asid(vcpu);
1643}
1644
6389ee94
AK		 1645static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1646 struct x86_exception *fault)
5bd2edc3
JR		 1647{
1648 struct vcpu_svm *svm = to_svm(vcpu);
1649
1650 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1651 svm->vmcb->control.exit_code_hi = 0;
6389ee94
AK		 1652 svm->vmcb->control.exit_info_1 = fault->error_code;
1653 svm->vmcb->control.exit_info_2 = fault->address;
5bd2edc3
JR		 1654
1655 nested_svm_vmexit(svm);
1656}
1657
4b16184c
JR		 1658static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1659{
1660 int r;
1661
1662 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1663
1664 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1665 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1666 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1667 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1668 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1669
1670 return r;
1671}
1672
1673static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1674{
1675 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1676}
1677
c0725420
AG		 1678static int nested_svm_check_permissions(struct vcpu_svm *svm)
1679{
f6801dff 1680 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1681 || !is_paging(&svm->vcpu)) {
1682 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1683 return 1;
1684 }
1685
1686 if (svm->vmcb->save.cpl) {
1687 kvm_inject_gp(&svm->vcpu, 0);
1688 return 1;
1689 }
1690
1691 return 0;
1692}
1693
cf74a78b
AG		 1694static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1695 bool has_error_code, u32 error_code)
1696{
b8e88bc8
JR		 1697 int vmexit;
1698
2030753d 1699 if (!is_guest_mode(&svm->vcpu))
0295ad7d 1700 return 0;
cf74a78b 1701
0295ad7d
JR		 1702 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1703 svm->vmcb->control.exit_code_hi = 0;
1704 svm->vmcb->control.exit_info_1 = error_code;
1705 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1706
b8e88bc8
JR		 1707 vmexit = nested_svm_intercept(svm);
1708 if (vmexit == NESTED_EXIT_DONE)
1709 svm->nested.exit_required = true;
1710
1711 return vmexit;
cf74a78b
AG		 1712}
1713
8fe54654
JR		 1714/* This function returns true if it is save to enable the irq window */
1715static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1716{
2030753d 1717 if (!is_guest_mode(&svm->vcpu))
8fe54654 1718 return true;
cf74a78b 1719
26666957 1720 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1721 return true;
cf74a78b 1722
26666957 1723 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1724 return false;
cf74a78b 1725
a0a07cd2
GN		 1726 /*
1727 * if vmexit was already requested (by intercepted exception
1728 * for instance) do not overwrite it with "external interrupt"
1729 * vmexit.
1730 */
1731 if (svm->nested.exit_required)
1732 return false;
1733
197717d5
JR		 1734 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1735 svm->vmcb->control.exit_info_1 = 0;
1736 svm->vmcb->control.exit_info_2 = 0;
26666957 1737
cd3ff653
JR		 1738 if (svm->nested.intercept & 1ULL) {
1739 /*
1740 * The #vmexit can't be emulated here directly because this
1741 * code path runs with irqs and preemtion disabled. A
1742 * #vmexit emulation might sleep. Only signal request for
1743 * the #vmexit here.
1744 */
1745 svm->nested.exit_required = true;
236649de 1746 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1747 return false;
cf74a78b
AG		 1748 }
1749
8fe54654 1750 return true;
cf74a78b
AG		 1751}
1752
887f500c
JR		 1753/* This function returns true if it is save to enable the nmi window */
1754static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1755{
2030753d 1756 if (!is_guest_mode(&svm->vcpu))
887f500c
JR		 1757 return true;
1758
1759 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1760 return true;
1761
1762 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1763 svm->nested.exit_required = true;
1764
1765 return false;
cf74a78b
AG		 1766}
1767
7597f129 1768static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1769{
1770 struct page *page;
1771
6c3bd3d7
JR		 1772 might_sleep();
1773
34f80cfa 1774 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1775 if (is_error_page(page))
1776 goto error;
1777
7597f129
JR		 1778 *_page = page;
1779
1780 return kmap(page);
34f80cfa
JR		 1781
1782error:
1783 kvm_release_page_clean(page);
1784 kvm_inject_gp(&svm->vcpu, 0);
1785
1786 return NULL;
1787}
1788
7597f129 1789static void nested_svm_unmap(struct page *page)
34f80cfa 1790{
7597f129 1791 kunmap(page);
34f80cfa
JR		 1792 kvm_release_page_dirty(page);
1793}
34f80cfa 1794
ce2ac085
JR		 1795static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1796{
1797 unsigned port;
1798 u8 val, bit;
1799 u64 gpa;
34f80cfa 1800
ce2ac085
JR		 1801 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1802 return NESTED_EXIT_HOST;
34f80cfa 1803
ce2ac085
JR		 1804 port = svm->vmcb->control.exit_info_1 >> 16;
1805 gpa = svm->nested.vmcb_iopm + (port / 8);
1806 bit = port % 8;
1807 val = 0;
1808
1809 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1810 val &= (1 << bit);
1811
1812 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1813}
1814
d2477826 1815static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1816{
0d6b3537
JR		 1817 u32 offset, msr, value;
1818 int write, mask;
4c2161ae 1819
3d62d9aa 1820 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1821 return NESTED_EXIT_HOST;
3d62d9aa 1822
0d6b3537
JR		 1823 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1824 offset = svm_msrpm_offset(msr);
1825 write = svm->vmcb->control.exit_info_1 & 1;
1826 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1827
0d6b3537
JR		 1828 if (offset == MSR_INVALID)
1829 return NESTED_EXIT_DONE;
4c2161ae 1830
0d6b3537
JR		 1831 /* Offset is in 32 bit units but need in 8 bit units */
1832 offset *= 4;
4c2161ae 1833
0d6b3537
JR		 1834 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1835 return NESTED_EXIT_DONE;
3d62d9aa 1836
0d6b3537 1837 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1838}
1839
410e4d57 1840static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1841{
cf74a78b 1842 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1843
410e4d57
JR		 1844 switch (exit_code) {
1845 case SVM_EXIT_INTR:
1846 case SVM_EXIT_NMI:
ff47a49b 1847 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1848 return NESTED_EXIT_HOST;
410e4d57 1849 case SVM_EXIT_NPF:
e0231715 1850 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1851 if (npt_enabled)
1852 return NESTED_EXIT_HOST;
1853 break;
410e4d57 1854 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
631bc487
GN		 1855 /* When we're shadowing, trap PFs, but not async PF */
1856 if (!npt_enabled && svm->apf_reason == 0)
410e4d57
JR		 1857 return NESTED_EXIT_HOST;
1858 break;
66a562f7
JR		 1859 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1860 nm_interception(svm);
1861 break;
410e4d57
JR		 1862 default:
1863 break;
cf74a78b
AG		 1864 }
1865
410e4d57
JR		 1866 return NESTED_EXIT_CONTINUE;
1867}
1868
1869/*
1870 * If this function returns true, this #vmexit was already handled
1871 */
b8e88bc8 1872static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1873{
1874 u32 exit_code = svm->vmcb->control.exit_code;
1875 int vmexit = NESTED_EXIT_HOST;
1876
cf74a78b 1877 switch (exit_code) {
9c4e40b9 1878 case SVM_EXIT_MSR:
3d62d9aa 1879 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1880 break;
ce2ac085
JR		 1881 case SVM_EXIT_IOIO:
1882 vmexit = nested_svm_intercept_ioio(svm);
1883 break;
cf74a78b
AG		 1884 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1885 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1886 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1887 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1888 break;
1889 }
1890 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1891 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1892 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1893 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1894 break;
1895 }
1896 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1897 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1898 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1899 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1900 break;
1901 }
1902 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1903 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1904 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1905 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1906 break;
1907 }
1908 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1909 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1910 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1911 vmexit = NESTED_EXIT_DONE;
631bc487
GN		 1912 /* async page fault always cause vmexit */
1913 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
1914 svm->apf_reason != 0)
1915 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1916 break;
1917 }
228070b1
JR		 1918 case SVM_EXIT_ERR: {
1919 vmexit = NESTED_EXIT_DONE;
1920 break;
1921 }
cf74a78b
AG		 1922 default: {
1923 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1924 if (svm->nested.intercept & exit_bits)
410e4d57 1925 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1926 }
1927 }
1928
b8e88bc8
JR		 1929 return vmexit;
1930}
1931
1932static int nested_svm_exit_handled(struct vcpu_svm *svm)
1933{
1934 int vmexit;
1935
1936 vmexit = nested_svm_intercept(svm);
1937
1938 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1939 nested_svm_vmexit(svm);
9c4e40b9
JR		 1940
1941 return vmexit;
cf74a78b
AG		 1942}
1943
0460a979
JR		 1944static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1945{
1946 struct vmcb_control_area *dst = &dst_vmcb->control;
1947 struct vmcb_control_area *from = &from_vmcb->control;
1948
1949 dst->intercept_cr_read = from->intercept_cr_read;
1950 dst->intercept_cr_write = from->intercept_cr_write;
1951 dst->intercept_dr_read = from->intercept_dr_read;
1952 dst->intercept_dr_write = from->intercept_dr_write;
1953 dst->intercept_exceptions = from->intercept_exceptions;
1954 dst->intercept = from->intercept;
1955 dst->iopm_base_pa = from->iopm_base_pa;
1956 dst->msrpm_base_pa = from->msrpm_base_pa;
1957 dst->tsc_offset = from->tsc_offset;
1958 dst->asid = from->asid;
1959 dst->tlb_ctl = from->tlb_ctl;
1960 dst->int_ctl = from->int_ctl;
1961 dst->int_vector = from->int_vector;
1962 dst->int_state = from->int_state;
1963 dst->exit_code = from->exit_code;
1964 dst->exit_code_hi = from->exit_code_hi;
1965 dst->exit_info_1 = from->exit_info_1;
1966 dst->exit_info_2 = from->exit_info_2;
1967 dst->exit_int_info = from->exit_int_info;
1968 dst->exit_int_info_err = from->exit_int_info_err;
1969 dst->nested_ctl = from->nested_ctl;
1970 dst->event_inj = from->event_inj;
1971 dst->event_inj_err = from->event_inj_err;
1972 dst->nested_cr3 = from->nested_cr3;
1973 dst->lbr_ctl = from->lbr_ctl;
1974}
1975
34f80cfa 1976static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1977{
34f80cfa 1978 struct vmcb *nested_vmcb;
e6aa9abd 1979 struct vmcb *hsave = svm->nested.hsave;
33740e40 1980 struct vmcb *vmcb = svm->vmcb;
7597f129 1981 struct page *page;
cf74a78b 1982
17897f36
JR		 1983 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1984 vmcb->control.exit_info_1,
1985 vmcb->control.exit_info_2,
1986 vmcb->control.exit_int_info,
1987 vmcb->control.exit_int_info_err);
1988
7597f129 1989 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1990 if (!nested_vmcb)
1991 return 1;
1992
2030753d
JR		 1993 /* Exit Guest-Mode */
1994 leave_guest_mode(&svm->vcpu);
06fc7772
JR		 1995 svm->nested.vmcb = 0;
1996
cf74a78b 1997 /* Give the current vmcb to the guest */
33740e40
JR		 1998 disable_gif(svm);
1999
2000 nested_vmcb->save.es = vmcb->save.es;
2001 nested_vmcb->save.cs = vmcb->save.cs;
2002 nested_vmcb->save.ss = vmcb->save.ss;
2003 nested_vmcb->save.ds = vmcb->save.ds;
2004 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2005 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 2006 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 2007 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 2008 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 2009 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 2010 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 2011 nested_vmcb->save.rflags = vmcb->save.rflags;
2012 nested_vmcb->save.rip = vmcb->save.rip;
2013 nested_vmcb->save.rsp = vmcb->save.rsp;
2014 nested_vmcb->save.rax = vmcb->save.rax;
2015 nested_vmcb->save.dr7 = vmcb->save.dr7;
2016 nested_vmcb->save.dr6 = vmcb->save.dr6;
2017 nested_vmcb->save.cpl = vmcb->save.cpl;
2018
2019 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2020 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2021 nested_vmcb->control.int_state = vmcb->control.int_state;
2022 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2023 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2024 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2025 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2026 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2027 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 2028 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 2029
2030 /*
2031 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2032 * to make sure that we do not lose injected events. So check event_inj
2033 * here and copy it to exit_int_info if it is valid.
2034 * Exit_int_info and event_inj can't be both valid because the case
2035 * below only happens on a VMRUN instruction intercept which has
2036 * no valid exit_int_info set.
2037 */
2038 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2039 struct vmcb_control_area *nc = &nested_vmcb->control;
2040
2041 nc->exit_int_info = vmcb->control.event_inj;
2042 nc->exit_int_info_err = vmcb->control.event_inj_err;
2043 }
2044
33740e40
JR		 2045 nested_vmcb->control.tlb_ctl = 0;
2046 nested_vmcb->control.event_inj = 0;
2047 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 2048
2049 /* We always set V_INTR_MASKING and remember the old value in hflags */
2050 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2051 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2052
cf74a78b 2053 /* Restore the original control entries */
0460a979 2054 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 2055
219b65dc
AG		 2056 kvm_clear_exception_queue(&svm->vcpu);
2057 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b 2058
4b16184c
JR		 2059 svm->nested.nested_cr3 = 0;
2060
cf74a78b
AG		 2061 /* Restore selected save entries */
2062 svm->vmcb->save.es = hsave->save.es;
2063 svm->vmcb->save.cs = hsave->save.cs;
2064 svm->vmcb->save.ss = hsave->save.ss;
2065 svm->vmcb->save.ds = hsave->save.ds;
2066 svm->vmcb->save.gdtr = hsave->save.gdtr;
2067 svm->vmcb->save.idtr = hsave->save.idtr;
2068 svm->vmcb->save.rflags = hsave->save.rflags;
2069 svm_set_efer(&svm->vcpu, hsave->save.efer);
2070 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2071 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2072 if (npt_enabled) {
2073 svm->vmcb->save.cr3 = hsave->save.cr3;
2074 svm->vcpu.arch.cr3 = hsave->save.cr3;
2075 } else {
2390218b 2076 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 2077 }
2078 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2079 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2080 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2081 svm->vmcb->save.dr7 = 0;
2082 svm->vmcb->save.cpl = 0;
2083 svm->vmcb->control.exit_int_info = 0;
2084
7597f129 2085 nested_svm_unmap(page);
cf74a78b 2086
4b16184c 2087 nested_svm_uninit_mmu_context(&svm->vcpu);
cf74a78b
AG		 2088 kvm_mmu_reset_context(&svm->vcpu);
2089 kvm_mmu_load(&svm->vcpu);
2090
2091 return 0;
2092}
3d6368ef 2093
9738b2c9 2094static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 2095{
323c3d80
JR		 2096 /*
2097 * This function merges the msr permission bitmaps of kvm and the
2098 * nested vmcb. It is omptimized in that it only merges the parts where
2099 * the kvm msr permission bitmap may contain zero bits
2100 */
3d6368ef 2101 int i;
9738b2c9 2102
323c3d80
JR		 2103 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2104 return true;
9738b2c9 2105
323c3d80
JR		 2106 for (i = 0; i < MSRPM_OFFSETS; i++) {
2107 u32 value, p;
2108 u64 offset;
9738b2c9 2109
323c3d80
JR		 2110 if (msrpm_offsets[i] == 0xffffffff)
2111 break;
3d6368ef 2112
0d6b3537
JR		 2113 p = msrpm_offsets[i];
2114 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2115
2116 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2117 return false;
2118
2119 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2120 }
3d6368ef 2121
323c3d80 2122 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2123
2124 return true;
3d6368ef
AG		 2125}
2126
52c65a30
JR		 2127static bool nested_vmcb_checks(struct vmcb *vmcb)
2128{
2129 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2130 return false;
2131
dbe77584
JR		 2132 if (vmcb->control.asid == 0)
2133 return false;
2134
4b16184c
JR		 2135 if (vmcb->control.nested_ctl && !npt_enabled)
2136 return false;
2137
52c65a30
JR		 2138 return true;
2139}
2140
9738b2c9 2141static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2142{
9738b2c9 2143 struct vmcb *nested_vmcb;
e6aa9abd 2144 struct vmcb *hsave = svm->nested.hsave;
defbba56 2145 struct vmcb *vmcb = svm->vmcb;
7597f129 2146 struct page *page;
06fc7772 2147 u64 vmcb_gpa;
3d6368ef 2148
06fc7772 2149 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2150
7597f129 2151 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2152 if (!nested_vmcb)
2153 return false;
2154
52c65a30
JR		 2155 if (!nested_vmcb_checks(nested_vmcb)) {
2156 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2157 nested_vmcb->control.exit_code_hi = 0;
2158 nested_vmcb->control.exit_info_1 = 0;
2159 nested_vmcb->control.exit_info_2 = 0;
2160
2161 nested_svm_unmap(page);
2162
2163 return false;
2164 }
2165
b75f4eb3 2166 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
0ac406de
JR		 2167 nested_vmcb->save.rip,
2168 nested_vmcb->control.int_ctl,
2169 nested_vmcb->control.event_inj,
2170 nested_vmcb->control.nested_ctl);
2171
2e554e8d
JR		 2172 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2173 nested_vmcb->control.intercept_cr_write,
2174 nested_vmcb->control.intercept_exceptions,
2175 nested_vmcb->control.intercept);
2176
3d6368ef 2177 /* Clear internal status */
219b65dc
AG		 2178 kvm_clear_exception_queue(&svm->vcpu);
2179 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2180
e0231715
JR		 2181 /*
2182 * Save the old vmcb, so we don't need to pick what we save, but can
2183 * restore everything when a VMEXIT occurs
2184 */
defbba56
JR		 2185 hsave->save.es = vmcb->save.es;
2186 hsave->save.cs = vmcb->save.cs;
2187 hsave->save.ss = vmcb->save.ss;
2188 hsave->save.ds = vmcb->save.ds;
2189 hsave->save.gdtr = vmcb->save.gdtr;
2190 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2191 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2192 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2193 hsave->save.cr4 = svm->vcpu.arch.cr4;
2194 hsave->save.rflags = vmcb->save.rflags;
b75f4eb3 2195 hsave->save.rip = kvm_rip_read(&svm->vcpu);
defbba56
JR		 2196 hsave->save.rsp = vmcb->save.rsp;
2197 hsave->save.rax = vmcb->save.rax;
2198 if (npt_enabled)
2199 hsave->save.cr3 = vmcb->save.cr3;
2200 else
2201 hsave->save.cr3 = svm->vcpu.arch.cr3;
2202
0460a979 2203 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2204
2205 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2206 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2207 else
2208 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2209
4b16184c
JR		 2210 if (nested_vmcb->control.nested_ctl) {
2211 kvm_mmu_unload(&svm->vcpu);
2212 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2213 nested_svm_init_mmu_context(&svm->vcpu);
2214 }
2215
3d6368ef
AG		 2216 /* Load the nested guest state */
2217 svm->vmcb->save.es = nested_vmcb->save.es;
2218 svm->vmcb->save.cs = nested_vmcb->save.cs;
2219 svm->vmcb->save.ss = nested_vmcb->save.ss;
2220 svm->vmcb->save.ds = nested_vmcb->save.ds;
2221 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2222 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2223 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2224 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2225 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2226 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2227 if (npt_enabled) {
2228 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2229 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2230 } else
2390218b 2231 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2232
2233 /* Guest paging mode is active - reset mmu */
2234 kvm_mmu_reset_context(&svm->vcpu);
2235
defbba56 2236 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2237 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2238 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2239 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2240
3d6368ef
AG		 2241 /* In case we don't even reach vcpu_run, the fields are not updated */
2242 svm->vmcb->save.rax = nested_vmcb->save.rax;
2243 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2244 svm->vmcb->save.rip = nested_vmcb->save.rip;
2245 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2246 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2247 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2248
f7138538 2249 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2250 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2251
aad42c64
JR		 2252 /* cache intercepts */
2253 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2254 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2255 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2256 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2257 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2258 svm->nested.intercept = nested_vmcb->control.intercept;
2259
3d6368ef 2260 force_new_asid(&svm->vcpu);
3d6368ef 2261 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2262 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2263 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2264 else
2265 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2266
88ab24ad
JR		 2267 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2268 /* We only want the cr8 intercept bits of the guest */
2269 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2270 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2271 }
2272
0d945bd9
JR		 2273 /* We don't want to see VMMCALLs from a nested guest */
2274 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2275
e0231715
JR		 2276 /*
2277 * We don't want a nested guest to be more powerful than the guest, so
2278 * all intercepts are ORed
2279 */
88ab24ad
JR		 2280 svm->vmcb->control.intercept_cr_read |=
2281 nested_vmcb->control.intercept_cr_read;
2282 svm->vmcb->control.intercept_cr_write |=
2283 nested_vmcb->control.intercept_cr_write;
2284 svm->vmcb->control.intercept_dr_read |=
2285 nested_vmcb->control.intercept_dr_read;
2286 svm->vmcb->control.intercept_dr_write |=
2287 nested_vmcb->control.intercept_dr_write;
2288 svm->vmcb->control.intercept_exceptions |=
2289 nested_vmcb->control.intercept_exceptions;
2290
2291 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2292
2293 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2294 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2295 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2296 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2297 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2298 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2299
7597f129 2300 nested_svm_unmap(page);
9738b2c9 2301
2030753d
JR		 2302 /* Enter Guest-Mode */
2303 enter_guest_mode(&svm->vcpu);
2304
06fc7772 2305 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2306
2af9194d 2307 enable_gif(svm);
3d6368ef 2308
9738b2c9 2309 return true;
3d6368ef
AG		 2310}
2311
9966bf68 2312static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2313{
2314 to_vmcb->save.fs = from_vmcb->save.fs;
2315 to_vmcb->save.gs = from_vmcb->save.gs;
2316 to_vmcb->save.tr = from_vmcb->save.tr;
2317 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2318 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2319 to_vmcb->save.star = from_vmcb->save.star;
2320 to_vmcb->save.lstar = from_vmcb->save.lstar;
2321 to_vmcb->save.cstar = from_vmcb->save.cstar;
2322 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2323 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2324 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2325 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2326}
2327
851ba692 2328static int vmload_interception(struct vcpu_svm *svm)
5542675b 2329{
9966bf68 2330 struct vmcb *nested_vmcb;
7597f129 2331 struct page *page;
9966bf68 2332
5542675b
AG		 2333 if (nested_svm_check_permissions(svm))
2334 return 1;
2335
2336 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2337 skip_emulated_instruction(&svm->vcpu);
2338
7597f129 2339 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2340 if (!nested_vmcb)
2341 return 1;
2342
2343 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2344 nested_svm_unmap(page);
5542675b
AG		 2345
2346 return 1;
2347}
2348
851ba692 2349static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2350{
9966bf68 2351 struct vmcb *nested_vmcb;
7597f129 2352 struct page *page;
9966bf68 2353
5542675b
AG		 2354 if (nested_svm_check_permissions(svm))
2355 return 1;
2356
2357 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2358 skip_emulated_instruction(&svm->vcpu);
2359
7597f129 2360 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2361 if (!nested_vmcb)
2362 return 1;
2363
2364 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2365 nested_svm_unmap(page);
5542675b
AG		 2366
2367 return 1;
2368}
2369
851ba692 2370static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2371{
3d6368ef
AG		 2372 if (nested_svm_check_permissions(svm))
2373 return 1;
2374
b75f4eb3
RJ		 2375 /* Save rip after vmrun instruction */
2376 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3d6368ef 2377
9738b2c9 2378 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2379 return 1;
2380
9738b2c9 2381 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2382 goto failed;
2383
2384 return 1;
2385
2386failed:
2387
2388 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2389 svm->vmcb->control.exit_code_hi = 0;
2390 svm->vmcb->control.exit_info_1 = 0;
2391 svm->vmcb->control.exit_info_2 = 0;
2392
2393 nested_svm_vmexit(svm);
3d6368ef
AG		 2394
2395 return 1;
2396}
2397
851ba692 2398static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2399{
2400 if (nested_svm_check_permissions(svm))
2401 return 1;
2402
2403 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2404 skip_emulated_instruction(&svm->vcpu);
3842d135 2405 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
1371d904 2406
2af9194d 2407 enable_gif(svm);
1371d904
AG		 2408
2409 return 1;
2410}
2411
851ba692 2412static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2413{
2414 if (nested_svm_check_permissions(svm))
2415 return 1;
2416
2417 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2418 skip_emulated_instruction(&svm->vcpu);
2419
2af9194d 2420 disable_gif(svm);
1371d904
AG		 2421
2422 /* After a CLGI no interrupts should come */
2423 svm_clear_vintr(svm);
2424 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2425
2426 return 1;
2427}
2428
851ba692 2429static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2430{
2431 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2432
ec1ff790
JR		 2433 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2434 vcpu->arch.regs[VCPU_REGS_RAX]);
2435
ff092385
AG		 2436 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2437 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2438
2439 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2440 skip_emulated_instruction(&svm->vcpu);
2441 return 1;
2442}
2443
532a46b9
JR		 2444static int skinit_interception(struct vcpu_svm *svm)
2445{
2446 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2447
2448 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2449 return 1;
2450}
2451
851ba692 2452static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2453{
7ee5d940 2454 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2455 return 1;
2456}
2457
851ba692 2458static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2459{
37817f29 2460 u16 tss_selector;
64a7ec06
GN		 2461 int reason;
2462 int int_type = svm->vmcb->control.exit_int_info &
2463 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2464 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2465 uint32_t type =
2466 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2467 uint32_t idt_v =
2468 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2469 bool has_error_code = false;
2470 u32 error_code = 0;
37817f29
IE		 2471
2472 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2473
37817f29
IE		 2474 if (svm->vmcb->control.exit_info_2 &
2475 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2476 reason = TASK_SWITCH_IRET;
2477 else if (svm->vmcb->control.exit_info_2 &
2478 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2479 reason = TASK_SWITCH_JMP;
fe8e7f83 2480 else if (idt_v)
64a7ec06
GN		 2481 reason = TASK_SWITCH_GATE;
2482 else
2483 reason = TASK_SWITCH_CALL;
2484
fe8e7f83
GN		 2485 if (reason == TASK_SWITCH_GATE) {
2486 switch (type) {
2487 case SVM_EXITINTINFO_TYPE_NMI:
2488 svm->vcpu.arch.nmi_injected = false;
2489 break;
2490 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2491 if (svm->vmcb->control.exit_info_2 &
2492 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2493 has_error_code = true;
2494 error_code =
2495 (u32)svm->vmcb->control.exit_info_2;
2496 }
fe8e7f83
GN		 2497 kvm_clear_exception_queue(&svm->vcpu);
2498 break;
2499 case SVM_EXITINTINFO_TYPE_INTR:
2500 kvm_clear_interrupt_queue(&svm->vcpu);
2501 break;
2502 default:
2503 break;
2504 }
2505 }
64a7ec06 2506
8317c298
GN		 2507 if (reason != TASK_SWITCH_GATE ||
2508 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2509 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2510 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2511 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2512
acb54517
GN		 2513 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2514 has_error_code, error_code) == EMULATE_FAIL) {
2515 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2516 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2517 svm->vcpu.run->internal.ndata = 0;
2518 return 0;
2519 }
2520 return 1;
6aa8b732
AK		 2521}
2522
851ba692 2523static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2524{
5fdbf976 2525 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2526 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2527 return 1;
6aa8b732
AK		 2528}
2529
851ba692 2530static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2531{
2532 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2533 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2534 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2535 return 1;
2536}
2537
851ba692 2538static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2539{
6d77dbfc 2540 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2541}
2542
851ba692 2543static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2544{
6d77dbfc 2545 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2546}
2547
cda00082
JR		 2548static int cr0_write_interception(struct vcpu_svm *svm)
2549{
2550 struct kvm_vcpu *vcpu = &svm->vcpu;
2551 int r;
2552
2553 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2554
2555 if (svm->nested.vmexit_rip) {
2556 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2557 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2558 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2559 svm->nested.vmexit_rip = 0;
2560 }
2561
2562 return r == EMULATE_DONE;
2563}
2564
851ba692 2565static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2566{
851ba692
AK		 2567 struct kvm_run *kvm_run = svm->vcpu.run;
2568
0a5fff19
GN		 2569 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2570 /* instruction emulation calls kvm_set_cr8() */
851ba692 2571 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2572 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2573 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2574 return 1;
95ba8273 2575 }
0a5fff19
GN		 2576 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2577 return 1;
1d075434
JR		 2578 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2579 return 0;
2580}
2581
6aa8b732
AK		 2582static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2583{
a2fa3e9f
GH		 2584 struct vcpu_svm *svm = to_svm(vcpu);
2585
6aa8b732 2586 switch (ecx) {
af24a4e4 2587 case MSR_IA32_TSC: {
20824f30 2588 u64 tsc_offset;
6aa8b732 2589
2030753d 2590 if (is_guest_mode(vcpu))
20824f30
JR		 2591 tsc_offset = svm->nested.hsave->control.tsc_offset;
2592 else
2593 tsc_offset = svm->vmcb->control.tsc_offset;
2594
2595 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2596 break;
2597 }
8c06585d 2598 case MSR_STAR:
a2fa3e9f 2599 *data = svm->vmcb->save.star;
6aa8b732 2600 break;
0e859cac 2601#ifdef CONFIG_X86_64
6aa8b732 2602 case MSR_LSTAR:
a2fa3e9f 2603 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2604 break;
2605 case MSR_CSTAR:
a2fa3e9f 2606 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2607 break;
2608 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2609 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2610 break;
2611 case MSR_SYSCALL_MASK:
a2fa3e9f 2612 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2613 break;
2614#endif
2615 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2616 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2617 break;
2618 case MSR_IA32_SYSENTER_EIP:
017cb99e 2619 *data = svm->sysenter_eip;
6aa8b732
AK		 2620 break;
2621 case MSR_IA32_SYSENTER_ESP:
017cb99e 2622 *data = svm->sysenter_esp;
6aa8b732 2623 break;
e0231715
JR		 2624 /*
2625 * Nobody will change the following 5 values in the VMCB so we can
2626 * safely return them on rdmsr. They will always be 0 until LBRV is
2627 * implemented.
2628 */
a2938c80
JR		 2629 case MSR_IA32_DEBUGCTLMSR:
2630 *data = svm->vmcb->save.dbgctl;
2631 break;
2632 case MSR_IA32_LASTBRANCHFROMIP:
2633 *data = svm->vmcb->save.br_from;
2634 break;
2635 case MSR_IA32_LASTBRANCHTOIP:
2636 *data = svm->vmcb->save.br_to;
2637 break;
2638 case MSR_IA32_LASTINTFROMIP:
2639 *data = svm->vmcb->save.last_excp_from;
2640 break;
2641 case MSR_IA32_LASTINTTOIP:
2642 *data = svm->vmcb->save.last_excp_to;
2643 break;
b286d5d8 2644 case MSR_VM_HSAVE_PA:
e6aa9abd 2645 *data = svm->nested.hsave_msr;
b286d5d8 2646 break;
eb6f302e 2647 case MSR_VM_CR:
4a810181 2648 *data = svm->nested.vm_cr_msr;
eb6f302e 2649 break;
c8a73f18
AG		 2650 case MSR_IA32_UCODE_REV:
2651 *data = 0x01000065;
2652 break;
6aa8b732 2653 default:
3bab1f5d 2654 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2655 }
2656 return 0;
2657}
2658
851ba692 2659static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2660{
ad312c7c 2661 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2662 u64 data;
2663
59200273
AK		 2664 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2665 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2666 kvm_inject_gp(&svm->vcpu, 0);
59200273 2667 } else {
229456fc 2668 trace_kvm_msr_read(ecx, data);
af9ca2d7 2669
5fdbf976 2670 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2671 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2672 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2673 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2674 }
2675 return 1;
2676}
2677
4a810181
JR		 2678static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2679{
2680 struct vcpu_svm *svm = to_svm(vcpu);
2681 int svm_dis, chg_mask;
2682
2683 if (data & ~SVM_VM_CR_VALID_MASK)
2684 return 1;
2685
2686 chg_mask = SVM_VM_CR_VALID_MASK;
2687
2688 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2689 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2690
2691 svm->nested.vm_cr_msr &= ~chg_mask;
2692 svm->nested.vm_cr_msr |= (data & chg_mask);
2693
2694 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2695
2696 /* check for svm_disable while efer.svme is set */
2697 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2698 return 1;
2699
2700 return 0;
2701}
2702
6aa8b732
AK		 2703static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2704{
a2fa3e9f
GH		 2705 struct vcpu_svm *svm = to_svm(vcpu);
2706
6aa8b732 2707 switch (ecx) {
f4e1b3c8 2708 case MSR_IA32_TSC:
99e3e30a 2709 kvm_write_tsc(vcpu, data);
6aa8b732 2710 break;
8c06585d 2711 case MSR_STAR:
a2fa3e9f 2712 svm->vmcb->save.star = data;
6aa8b732 2713 break;
49b14f24 2714#ifdef CONFIG_X86_64
6aa8b732 2715 case MSR_LSTAR:
a2fa3e9f 2716 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2717 break;
2718 case MSR_CSTAR:
a2fa3e9f 2719 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2720 break;
2721 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2722 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2723 break;
2724 case MSR_SYSCALL_MASK:
a2fa3e9f 2725 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2726 break;
2727#endif
2728 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2729 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2730 break;
2731 case MSR_IA32_SYSENTER_EIP:
017cb99e 2732 svm->sysenter_eip = data;
a2fa3e9f 2733 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2734 break;
2735 case MSR_IA32_SYSENTER_ESP:
017cb99e 2736 svm->sysenter_esp = data;
a2fa3e9f 2737 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2738 break;
a2938c80 2739 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 2740 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
24e09cbf 2741 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2742 __func__, data);
24e09cbf
JR		 2743 break;
2744 }
2745 if (data & DEBUGCTL_RESERVED_BITS)
2746 return 1;
2747
2748 svm->vmcb->save.dbgctl = data;
2749 if (data & (1ULL<<0))
2750 svm_enable_lbrv(svm);
2751 else
2752 svm_disable_lbrv(svm);
a2938c80 2753 break;
b286d5d8 2754 case MSR_VM_HSAVE_PA:
e6aa9abd 2755 svm->nested.hsave_msr = data;
62b9abaa 2756 break;
3c5d0a44 2757 case MSR_VM_CR:
4a810181 2758 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2759 case MSR_VM_IGNNE:
3c5d0a44
AG		 2760 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2761 break;
6aa8b732 2762 default:
3bab1f5d 2763 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2764 }
2765 return 0;
2766}
2767
851ba692 2768static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2769{
ad312c7c 2770 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2771 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2772 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2773
af9ca2d7 2774
5fdbf976 2775 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2776 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2777 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2778 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2779 } else {
2780 trace_kvm_msr_write(ecx, data);
e756fc62 2781 skip_emulated_instruction(&svm->vcpu);
59200273 2782 }
6aa8b732
AK		 2783 return 1;
2784}
2785
851ba692 2786static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2787{
e756fc62 2788 if (svm->vmcb->control.exit_info_1)
851ba692 2789 return wrmsr_interception(svm);
6aa8b732 2790 else
851ba692 2791 return rdmsr_interception(svm);
6aa8b732
AK		 2792}
2793
851ba692 2794static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2795{
851ba692
AK		 2796 struct kvm_run *kvm_run = svm->vcpu.run;
2797
3842d135 2798 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2799 svm_clear_vintr(svm);
85f455f7 2800 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2801 /*
2802 * If the user space waits to inject interrupts, exit as soon as
2803 * possible
2804 */
8061823a
GN		 2805 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2806 kvm_run->request_interrupt_window &&
2807 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2808 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2809 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2810 return 0;
2811 }
2812
2813 return 1;
2814}
2815
565d0998
ML		 2816static int pause_interception(struct vcpu_svm *svm)
2817{
2818 kvm_vcpu_on_spin(&(svm->vcpu));
2819 return 1;
2820}
2821
851ba692 2822static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2823 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2824 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2825 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2826 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2827 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
cda00082 2828 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
e0231715
JR		 2829 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2830 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2831 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2832 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2833 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2834 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2835 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2836 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2837 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2838 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2839 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2840 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2841 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2842 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2843 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2844 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2845 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2846 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2847 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2848 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2849 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2850 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2851 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2852 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2853 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2854 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2855 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2856 [SVM_EXIT_SMI] = nop_on_interception,
2857 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2858 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2859 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2860 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2861 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2862 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2863 [SVM_EXIT_HLT] = halt_interception,
a7052897 2864 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2865 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2866 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2867 [SVM_EXIT_MSR] = msr_interception,
2868 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2869 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2870 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2871 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2872 [SVM_EXIT_VMLOAD] = vmload_interception,
2873 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2874 [SVM_EXIT_STGI] = stgi_interception,
2875 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2876 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2877 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2878 [SVM_EXIT_MONITOR] = invalid_op_interception,
2879 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2880 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2881};
2882
3f10c846
JR		 2883void dump_vmcb(struct kvm_vcpu *vcpu)
2884{
2885 struct vcpu_svm *svm = to_svm(vcpu);
2886 struct vmcb_control_area *control = &svm->vmcb->control;
2887 struct vmcb_save_area *save = &svm->vmcb->save;
2888
2889 pr_err("VMCB Control Area:\n");
2890 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2891 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2892 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2893 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2894 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2895 pr_err("intercepts: %016llx\n", control->intercept);
2896 pr_err("pause filter count: %d\n", control->pause_filter_count);
2897 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2898 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2899 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2900 pr_err("asid: %d\n", control->asid);
2901 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2902 pr_err("int_ctl: %08x\n", control->int_ctl);
2903 pr_err("int_vector: %08x\n", control->int_vector);
2904 pr_err("int_state: %08x\n", control->int_state);
2905 pr_err("exit_code: %08x\n", control->exit_code);
2906 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2907 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2908 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2909 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2910 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2911 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2912 pr_err("event_inj: %08x\n", control->event_inj);
2913 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2914 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2915 pr_err("next_rip: %016llx\n", control->next_rip);
2916 pr_err("VMCB State Save Area:\n");
2917 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2918 save->es.selector, save->es.attrib,
2919 save->es.limit, save->es.base);
2920 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2921 save->cs.selector, save->cs.attrib,
2922 save->cs.limit, save->cs.base);
2923 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2924 save->ss.selector, save->ss.attrib,
2925 save->ss.limit, save->ss.base);
2926 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2927 save->ds.selector, save->ds.attrib,
2928 save->ds.limit, save->ds.base);
2929 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2930 save->fs.selector, save->fs.attrib,
2931 save->fs.limit, save->fs.base);
2932 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2933 save->gs.selector, save->gs.attrib,
2934 save->gs.limit, save->gs.base);
2935 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2936 save->gdtr.selector, save->gdtr.attrib,
2937 save->gdtr.limit, save->gdtr.base);
2938 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2939 save->ldtr.selector, save->ldtr.attrib,
2940 save->ldtr.limit, save->ldtr.base);
2941 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2942 save->idtr.selector, save->idtr.attrib,
2943 save->idtr.limit, save->idtr.base);
2944 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2945 save->tr.selector, save->tr.attrib,
2946 save->tr.limit, save->tr.base);
2947 pr_err("cpl: %d efer: %016llx\n",
2948 save->cpl, save->efer);
2949 pr_err("cr0: %016llx cr2: %016llx\n",
2950 save->cr0, save->cr2);
2951 pr_err("cr3: %016llx cr4: %016llx\n",
2952 save->cr3, save->cr4);
2953 pr_err("dr6: %016llx dr7: %016llx\n",
2954 save->dr6, save->dr7);
2955 pr_err("rip: %016llx rflags: %016llx\n",
2956 save->rip, save->rflags);
2957 pr_err("rsp: %016llx rax: %016llx\n",
2958 save->rsp, save->rax);
2959 pr_err("star: %016llx lstar: %016llx\n",
2960 save->star, save->lstar);
2961 pr_err("cstar: %016llx sfmask: %016llx\n",
2962 save->cstar, save->sfmask);
2963 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2964 save->kernel_gs_base, save->sysenter_cs);
2965 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2966 save->sysenter_esp, save->sysenter_eip);
2967 pr_err("gpat: %016llx dbgctl: %016llx\n",
2968 save->g_pat, save->dbgctl);
2969 pr_err("br_from: %016llx br_to: %016llx\n",
2970 save->br_from, save->br_to);
2971 pr_err("excp_from: %016llx excp_to: %016llx\n",
2972 save->last_excp_from, save->last_excp_to);
2973
2974}
2975
586f9607
AK		 2976static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2977{
2978 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2979
2980 *info1 = control->exit_info_1;
2981 *info2 = control->exit_info_2;
2982}
2983
851ba692 2984static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2985{
04d2cc77 2986 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2987 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2988 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2989
aa17911e 2990 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
af9ca2d7 2991
2be4fc7a
JR		 2992 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2993 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2994 if (npt_enabled)
2995 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2996
cd3ff653
JR		 2997 if (unlikely(svm->nested.exit_required)) {
2998 nested_svm_vmexit(svm);
2999 svm->nested.exit_required = false;
3000
3001 return 1;
3002 }
3003
2030753d 3004 if (is_guest_mode(vcpu)) {
410e4d57
JR		 3005 int vmexit;
3006
d8cabddf
JR		 3007 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3008 svm->vmcb->control.exit_info_1,
3009 svm->vmcb->control.exit_info_2,
3010 svm->vmcb->control.exit_int_info,
3011 svm->vmcb->control.exit_int_info_err);
3012
410e4d57
JR		 3013 vmexit = nested_svm_exit_special(svm);
3014
3015 if (vmexit == NESTED_EXIT_CONTINUE)
3016 vmexit = nested_svm_exit_handled(svm);
3017
3018 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 3019 return 1;
cf74a78b
AG		 3020 }
3021
a5c3832d
JR		 3022 svm_complete_interrupts(svm);
3023
04d2cc77
AK		 3024 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3025 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3026 kvm_run->fail_entry.hardware_entry_failure_reason
3027 = svm->vmcb->control.exit_code;
3f10c846
JR		 3028 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3029 dump_vmcb(vcpu);
04d2cc77
AK		 3030 return 0;
3031 }
3032
a2fa3e9f 3033 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 3034 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 3035 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3036 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6aa8b732
AK		 3037 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3038 "exit_code 0x%x\n",
b8688d51 3039 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 3040 exit_code);
3041
9d8f549d 3042 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 3043 || !svm_exit_handlers[exit_code]) {
6aa8b732 3044 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 3045 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 3046 return 0;
3047 }
3048
851ba692 3049 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3050}
3051
3052static void reload_tss(struct kvm_vcpu *vcpu)
3053{
3054 int cpu = raw_smp_processor_id();
3055
0fe1e009
TH		 3056 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3057 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3058 load_TR_desc();
3059}
3060
e756fc62 3061static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 3062{
3063 int cpu = raw_smp_processor_id();
3064
0fe1e009 3065 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 3066
a2fa3e9f 3067 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 3068 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3069 if (svm->asid_generation != sd->asid_generation)
3070 new_asid(svm, sd);
6aa8b732
AK		 3071}
3072
95ba8273
GN		 3073static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3074{
3075 struct vcpu_svm *svm = to_svm(vcpu);
3076
3077 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3078 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 3079 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 3080 ++vcpu->stat.nmi_injections;
3081}
6aa8b732 3082
85f455f7 3083static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 3084{
3085 struct vmcb_control_area *control;
3086
e756fc62 3087 control = &svm->vmcb->control;
85f455f7 3088 control->int_vector = irq;
6aa8b732
AK		 3089 control->int_ctl &= ~V_INTR_PRIO_MASK;
3090 control->int_ctl |= V_IRQ_MASK |
3091 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3092}
3093
66fd3f7f 3094static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3095{
3096 struct vcpu_svm *svm = to_svm(vcpu);
3097
2af9194d 3098 BUG_ON(!(gif_set(svm)));
cf74a78b 3099
9fb2d2b4
GN		 3100 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3101 ++vcpu->stat.irq_injections;
3102
219b65dc
AG		 3103 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3104 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3105}
3106
95ba8273 3107static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3108{
3109 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3110
2030753d 3111 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3112 return;
3113
95ba8273 3114 if (irr == -1)
aaacfc9a
JR		 3115 return;
3116
95ba8273
GN		 3117 if (tpr >= irr)
3118 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
3119}
aaacfc9a 3120
95ba8273
GN		 3121static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3122{
3123 struct vcpu_svm *svm = to_svm(vcpu);
3124 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 3125 int ret;
3126 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3127 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3128 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3129
3130 return ret;
aaacfc9a
JR		 3131}
3132
3cfc3092
JK		 3133static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3134{
3135 struct vcpu_svm *svm = to_svm(vcpu);
3136
3137 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3138}
3139
3140static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3141{
3142 struct vcpu_svm *svm = to_svm(vcpu);
3143
3144 if (masked) {
3145 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 3146 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3147 } else {
3148 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 3149 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3150 }
3151}
3152
78646121
GN		 3153static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3154{
3155 struct vcpu_svm *svm = to_svm(vcpu);
3156 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3157 int ret;
3158
3159 if (!gif_set(svm) ||
3160 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3161 return 0;
3162
3163 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3164
2030753d 3165 if (is_guest_mode(vcpu))
7fcdb510
JR		 3166 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3167
3168 return ret;
78646121
GN		 3169}
3170
9222be18 3171static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3172{
219b65dc 3173 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3174
e0231715
JR		 3175 /*
3176 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3177 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3178 * get that intercept, this function will be called again though and
3179 * we'll get the vintr intercept.
3180 */
8fe54654 3181 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3182 svm_set_vintr(svm);
3183 svm_inject_irq(svm, 0x0);
3184 }
85f455f7
ED		 3185}
3186
95ba8273 3187static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3188{
04d2cc77 3189 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3190
44c11430
GN		 3191 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3192 == HF_NMI_MASK)
3193 return; /* IRET will cause a vm exit */
3194
e0231715
JR		 3195 /*
3196 * Something prevents NMI from been injected. Single step over possible
3197 * problem (IRET or exception injection or interrupt shadow)
3198 */
6be7d306 3199 svm->nmi_singlestep = true;
44c11430
GN		 3200 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3201 update_db_intercept(vcpu);
c1150d8c
DL		 3202}
3203
cbc94022
IE		 3204static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3205{
3206 return 0;
3207}
3208
d9e368d6
AK		 3209static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3210{
3211 force_new_asid(vcpu);
3212}
3213
04d2cc77
AK		 3214static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3215{
3216}
3217
d7bf8221
JR		 3218static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3219{
3220 struct vcpu_svm *svm = to_svm(vcpu);
3221
2030753d 3222 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3223 return;
3224
d7bf8221
JR		 3225 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3226 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3227 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3228 }
3229}
3230
649d6864
JR		 3231static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3232{
3233 struct vcpu_svm *svm = to_svm(vcpu);
3234 u64 cr8;
3235
2030753d 3236 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3237 return;
3238
649d6864
JR		 3239 cr8 = kvm_get_cr8(vcpu);
3240 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3241 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3242}
3243
9222be18
GN		 3244static void svm_complete_interrupts(struct vcpu_svm *svm)
3245{
3246 u8 vector;
3247 int type;
3248 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3249 unsigned int3_injected = svm->int3_injected;
3250
3251 svm->int3_injected = 0;
9222be18 3252
3842d135 3253 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
44c11430 3254 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3255 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3256 }
44c11430 3257
9222be18
GN		 3258 svm->vcpu.arch.nmi_injected = false;
3259 kvm_clear_exception_queue(&svm->vcpu);
3260 kvm_clear_interrupt_queue(&svm->vcpu);
3261
3262 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3263 return;
3264
3842d135
AK		 3265 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3266
9222be18
GN		 3267 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3268 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3269
3270 switch (type) {
3271 case SVM_EXITINTINFO_TYPE_NMI:
3272 svm->vcpu.arch.nmi_injected = true;
3273 break;
3274 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3275 /*
3276 * In case of software exceptions, do not reinject the vector,
3277 * but re-execute the instruction instead. Rewind RIP first
3278 * if we emulated INT3 before.
3279 */
3280 if (kvm_exception_is_soft(vector)) {
3281 if (vector == BP_VECTOR && int3_injected &&
3282 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3283 kvm_rip_write(&svm->vcpu,
3284 kvm_rip_read(&svm->vcpu) -
3285 int3_injected);
9222be18 3286 break;
66b7138f 3287 }
9222be18
GN		 3288 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3289 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3290 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3291
3292 } else
ce7ddec4 3293 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3294 break;
3295 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3296 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3297 break;
3298 default:
3299 break;
3300 }
3301}
3302
b463a6f7
AK		 3303static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3304{
3305 struct vcpu_svm *svm = to_svm(vcpu);
3306 struct vmcb_control_area *control = &svm->vmcb->control;
3307
3308 control->exit_int_info = control->event_inj;
3309 control->exit_int_info_err = control->event_inj_err;
3310 control->event_inj = 0;
3311 svm_complete_interrupts(svm);
3312}
3313
80e31d4f
AK		 3314#ifdef CONFIG_X86_64
3315#define R "r"
3316#else
3317#define R "e"
3318#endif
3319
851ba692 3320static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3321{
a2fa3e9f 3322 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3323
2041a06a
JR		 3324 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3325 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3326 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3327
cd3ff653
JR		 3328 /*
3329 * A vmexit emulation is required before the vcpu can be executed
3330 * again.
3331 */
3332 if (unlikely(svm->nested.exit_required))
3333 return;
3334
e756fc62 3335 pre_svm_run(svm);
6aa8b732 3336
649d6864
JR		 3337 sync_lapic_to_cr8(vcpu);
3338
cda0ffdd 3339 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3340
04d2cc77
AK		 3341 clgi();
3342
3343 local_irq_enable();
36241b8c 3344
6aa8b732 3345 asm volatile (
80e31d4f
AK		 3346 "push %%"R"bp; \n\t"
3347 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3348 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3349 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3350 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3351 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3352 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3353#ifdef CONFIG_X86_64
fb3f0f51
RR		 3354 "mov %c[r8](%[svm]), %%r8 \n\t"
3355 "mov %c[r9](%[svm]), %%r9 \n\t"
3356 "mov %c[r10](%[svm]), %%r10 \n\t"
3357 "mov %c[r11](%[svm]), %%r11 \n\t"
3358 "mov %c[r12](%[svm]), %%r12 \n\t"
3359 "mov %c[r13](%[svm]), %%r13 \n\t"
3360 "mov %c[r14](%[svm]), %%r14 \n\t"
3361 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3362#endif
3363
6aa8b732 3364 /* Enter guest mode */
80e31d4f
AK		 3365 "push %%"R"ax \n\t"
3366 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3367 __ex(SVM_VMLOAD) "\n\t"
3368 __ex(SVM_VMRUN) "\n\t"
3369 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3370 "pop %%"R"ax \n\t"
6aa8b732
AK		 3371
3372 /* Save guest registers, load host registers */
80e31d4f
AK		 3373 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3374 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3375 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3376 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3377 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3378 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3379#ifdef CONFIG_X86_64
fb3f0f51
RR		 3380 "mov %%r8, %c[r8](%[svm]) \n\t"
3381 "mov %%r9, %c[r9](%[svm]) \n\t"
3382 "mov %%r10, %c[r10](%[svm]) \n\t"
3383 "mov %%r11, %c[r11](%[svm]) \n\t"
3384 "mov %%r12, %c[r12](%[svm]) \n\t"
3385 "mov %%r13, %c[r13](%[svm]) \n\t"
3386 "mov %%r14, %c[r14](%[svm]) \n\t"
3387 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3388#endif
80e31d4f 3389 "pop %%"R"bp"
6aa8b732 3390 :
fb3f0f51 3391 : [svm]"a"(svm),
6aa8b732 3392 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3393 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3394 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3395 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3396 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3397 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3398 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3399#ifdef CONFIG_X86_64
ad312c7c
ZX		 3400 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3401 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3402 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3403 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3404 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3405 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3406 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3407 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3408#endif
54a08c04 3409 : "cc", "memory"
80e31d4f 3410 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3411#ifdef CONFIG_X86_64
54a08c04
LV		 3412 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3413#endif
3414 );
6aa8b732 3415
82ca2d10
AK		 3416#ifdef CONFIG_X86_64
3417 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3418#else
dacccfdd 3419 loadsegment(fs, svm->host.fs);
9581d442 3420#endif
6aa8b732
AK		 3421
3422 reload_tss(vcpu);
3423
56ba47dd
AK		 3424 local_irq_disable();
3425
3426 stgi();
3427
13c34e07
AK		 3428 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3429 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3430 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3431 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3432
d7bf8221
JR		 3433 sync_cr8_to_lapic(vcpu);
3434
a2fa3e9f 3435 svm->next_rip = 0;
9222be18 3436
631bc487
GN		 3437 /* if exit due to PF check for async PF */
3438 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3439 svm->apf_reason = kvm_read_and_reset_pf_reason();
3440
6de4f3ad
AK		 3441 if (npt_enabled) {
3442 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3443 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3444 }
fe5913e4
JR		 3445
3446 /*
3447 * We need to handle MC intercepts here before the vcpu has a chance to
3448 * change the physical cpu
3449 */
3450 if (unlikely(svm->vmcb->control.exit_code ==
3451 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3452 svm_handle_mce(svm);
6aa8b732
AK		 3453}
3454
80e31d4f
AK		 3455#undef R
3456
6aa8b732
AK		 3457static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3458{
a2fa3e9f
GH		 3459 struct vcpu_svm *svm = to_svm(vcpu);
3460
3461 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3462 force_new_asid(vcpu);
3463}
3464
1c97f0a0
JR		 3465static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3466{
3467 struct vcpu_svm *svm = to_svm(vcpu);
3468
3469 svm->vmcb->control.nested_cr3 = root;
3470
3471 /* Also sync guest cr3 here in case we live migrate */
3472 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3473
3474 force_new_asid(vcpu);
3475}
3476
6aa8b732
AK		 3477static int is_disabled(void)
3478{
6031a61c
JR		 3479 u64 vm_cr;
3480
3481 rdmsrl(MSR_VM_CR, vm_cr);
3482 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3483 return 1;
3484
6aa8b732
AK		 3485 return 0;
3486}
3487
102d8325
IM		 3488static void
3489svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3490{
3491 /*
3492 * Patch in the VMMCALL instruction:
3493 */
3494 hypercall[0] = 0x0f;
3495 hypercall[1] = 0x01;
3496 hypercall[2] = 0xd9;
102d8325
IM		 3497}
3498
002c7f7c
YS		 3499static void svm_check_processor_compat(void *rtn)
3500{
3501 *(int *)rtn = 0;
3502}
3503
774ead3a
AK		 3504static bool svm_cpu_has_accelerated_tpr(void)
3505{
3506 return false;
3507}
3508
4b12f0de 3509static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3510{
3511 return 0;
3512}
3513
0e851880
SY		 3514static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3515{
3516}
3517
d4330ef2
JR		 3518static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3519{
c2c63a49 3520 switch (func) {
24d1b15f
JR		 3521 case 0x00000001:
3522 /* Mask out xsave bit as long as it is not supported by SVM */
3523 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3524 break;
4c62a2dc
JR		 3525 case 0x80000001:
3526 if (nested)
3527 entry->ecx |= (1 << 2); /* Set SVM bit */
3528 break;
c2c63a49
JR		 3529 case 0x8000000A:
3530 entry->eax = 1; /* SVM revision 1 */
3531 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3532 ASID emulation to nested SVM */
3533 entry->ecx = 0; /* Reserved */
7a190667
JR		 3534 entry->edx = 0; /* Per default do not support any
3535 additional features */
3536
3537 /* Support next_rip if host supports it */
2a6b20b8 3538 if (boot_cpu_has(X86_FEATURE_NRIPS))
7a190667 3539 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49 3540
3d4aeaad
JR		 3541 /* Support NPT for the guest if enabled */
3542 if (npt_enabled)
3543 entry->edx |= SVM_FEATURE_NPT;
3544
c2c63a49
JR		 3545 break;
3546 }
d4330ef2
JR		 3547}
3548
229456fc 3549static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3550 { SVM_EXIT_READ_CR0, "read_cr0" },
3551 { SVM_EXIT_READ_CR3, "read_cr3" },
3552 { SVM_EXIT_READ_CR4, "read_cr4" },
3553 { SVM_EXIT_READ_CR8, "read_cr8" },
3554 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3555 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3556 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3557 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3558 { SVM_EXIT_READ_DR0, "read_dr0" },
3559 { SVM_EXIT_READ_DR1, "read_dr1" },
3560 { SVM_EXIT_READ_DR2, "read_dr2" },
3561 { SVM_EXIT_READ_DR3, "read_dr3" },
3562 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3563 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3564 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3565 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3566 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3567 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3568 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3569 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3570 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3571 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3572 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3573 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3574 { SVM_EXIT_INTR, "interrupt" },
3575 { SVM_EXIT_NMI, "nmi" },
3576 { SVM_EXIT_SMI, "smi" },
3577 { SVM_EXIT_INIT, "init" },
3578 { SVM_EXIT_VINTR, "vintr" },
3579 { SVM_EXIT_CPUID, "cpuid" },
3580 { SVM_EXIT_INVD, "invd" },
3581 { SVM_EXIT_HLT, "hlt" },
3582 { SVM_EXIT_INVLPG, "invlpg" },
3583 { SVM_EXIT_INVLPGA, "invlpga" },
3584 { SVM_EXIT_IOIO, "io" },
3585 { SVM_EXIT_MSR, "msr" },
3586 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3587 { SVM_EXIT_SHUTDOWN, "shutdown" },
3588 { SVM_EXIT_VMRUN, "vmrun" },
3589 { SVM_EXIT_VMMCALL, "hypercall" },
3590 { SVM_EXIT_VMLOAD, "vmload" },
3591 { SVM_EXIT_VMSAVE, "vmsave" },
3592 { SVM_EXIT_STGI, "stgi" },
3593 { SVM_EXIT_CLGI, "clgi" },
3594 { SVM_EXIT_SKINIT, "skinit" },
3595 { SVM_EXIT_WBINVD, "wbinvd" },
3596 { SVM_EXIT_MONITOR, "monitor" },
3597 { SVM_EXIT_MWAIT, "mwait" },
3598 { SVM_EXIT_NPF, "npf" },
3599 { -1, NULL }
3600};
3601
17cc3935 3602static int svm_get_lpage_level(void)
344f414f 3603{
17cc3935 3604 return PT_PDPE_LEVEL;
344f414f
JR		 3605}
3606
4e47c7a6
SY		 3607static bool svm_rdtscp_supported(void)
3608{
3609 return false;
3610}
3611
f5f48ee1
SY		 3612static bool svm_has_wbinvd_exit(void)
3613{
3614 return true;
3615}
3616
02daab21
AK		 3617static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3618{
3619 struct vcpu_svm *svm = to_svm(vcpu);
3620
02daab21 3621 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
2030753d 3622 if (is_guest_mode(vcpu))
66a562f7
JR		 3623 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3624 update_cr0_intercept(svm);
02daab21
AK		 3625}
3626
cbdd1bea 3627static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3628 .cpu_has_kvm_support = has_svm,
3629 .disabled_by_bios = is_disabled,
3630 .hardware_setup = svm_hardware_setup,
3631 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3632 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3633 .hardware_enable = svm_hardware_enable,
3634 .hardware_disable = svm_hardware_disable,
774ead3a 3635 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3636
3637 .vcpu_create = svm_create_vcpu,
3638 .vcpu_free = svm_free_vcpu,
04d2cc77 3639 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3640
04d2cc77 3641 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3642 .vcpu_load = svm_vcpu_load,
3643 .vcpu_put = svm_vcpu_put,
3644
3645 .set_guest_debug = svm_guest_debug,
3646 .get_msr = svm_get_msr,
3647 .set_msr = svm_set_msr,
3648 .get_segment_base = svm_get_segment_base,
3649 .get_segment = svm_get_segment,
3650 .set_segment = svm_set_segment,
2e4d2653 3651 .get_cpl = svm_get_cpl,
1747fb71 3652 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3653 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3654 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3655 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3656 .set_cr3 = svm_set_cr3,
3657 .set_cr4 = svm_set_cr4,
3658 .set_efer = svm_set_efer,
3659 .get_idt = svm_get_idt,
3660 .set_idt = svm_set_idt,
3661 .get_gdt = svm_get_gdt,
3662 .set_gdt = svm_set_gdt,
020df079 3663 .set_dr7 = svm_set_dr7,
6de4f3ad 3664 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3665 .get_rflags = svm_get_rflags,
3666 .set_rflags = svm_set_rflags,
6b52d186 3667 .fpu_activate = svm_fpu_activate,
02daab21 3668 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3669
6aa8b732 3670 .tlb_flush = svm_flush_tlb,
6aa8b732 3671
6aa8b732 3672 .run = svm_vcpu_run,
04d2cc77 3673 .handle_exit = handle_exit,
6aa8b732 3674 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3675 .set_interrupt_shadow = svm_set_interrupt_shadow,
3676 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3677 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3678 .set_irq = svm_set_irq,
95ba8273 3679 .set_nmi = svm_inject_nmi,
298101da 3680 .queue_exception = svm_queue_exception,
b463a6f7 3681 .cancel_injection = svm_cancel_injection,
78646121 3682 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3683 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3684 .get_nmi_mask = svm_get_nmi_mask,
3685 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3686 .enable_nmi_window = enable_nmi_window,
3687 .enable_irq_window = enable_irq_window,
3688 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3689
3690 .set_tss_addr = svm_set_tss_addr,
67253af5 3691 .get_tdp_level = get_npt_level,
4b12f0de 3692 .get_mt_mask = svm_get_mt_mask,
229456fc 3693
586f9607 3694 .get_exit_info = svm_get_exit_info,
229456fc 3695 .exit_reasons_str = svm_exit_reasons_str,
586f9607 3696
17cc3935 3697 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3698
3699 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3700
3701 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3702
3703 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3704
3705 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a
ZA		 3706
3707 .write_tsc_offset = svm_write_tsc_offset,
e48672fa 3708 .adjust_tsc_offset = svm_adjust_tsc_offset,
1c97f0a0
JR		 3709
3710 .set_tdp_cr3 = set_tdp_cr3,
6aa8b732
AK		 3711};
3712
3713static int __init svm_init(void)
3714{
cb498ea2 3715 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3716 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3717}
3718
3719static void __exit svm_exit(void)
3720{
cb498ea2 3721 kvm_exit();
6aa8b732
AK		 3722}
3723
3724module_init(svm_init)
3725module_exit(svm_exit)
Ubuntu Artful kernel mirror