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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
42f61420 | 19 | #include <linux/cpu.h> |
fd63e9ce | 20 | #include <linux/delay.h> |
b60503ba MW |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/genhd.h> | |
4cc09e2d | 24 | #include <linux/hdreg.h> |
5aff9382 | 25 | #include <linux/idr.h> |
b60503ba MW |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kdev_t.h> | |
1fa6aead | 30 | #include <linux/kthread.h> |
b60503ba MW |
31 | #include <linux/kernel.h> |
32 | #include <linux/mm.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
77bf25ea | 35 | #include <linux/mutex.h> |
b60503ba | 36 | #include <linux/pci.h> |
be7b6275 | 37 | #include <linux/poison.h> |
c3bfe717 | 38 | #include <linux/ptrace.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
e1e5e564 | 41 | #include <linux/t10-pi.h> |
b60503ba | 42 | #include <linux/types.h> |
2f8e2c87 | 43 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 44 | #include <asm/unaligned.h> |
797a796a | 45 | |
f11bb3e2 CH |
46 | #include "nvme.h" |
47 | ||
9d43cf64 | 48 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 49 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
50 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
51 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
adf68f21 CH |
52 | |
53 | /* | |
54 | * We handle AEN commands ourselves and don't even let the | |
55 | * block layer know about them. | |
56 | */ | |
57 | #define NVME_NR_AEN_COMMANDS 1 | |
58 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) | |
9d43cf64 | 59 | |
58ffacb5 MW |
60 | static int use_threaded_interrupts; |
61 | module_param(use_threaded_interrupts, int, 0); | |
62 | ||
8ffaadf7 JD |
63 | static bool use_cmb_sqes = true; |
64 | module_param(use_cmb_sqes, bool, 0644); | |
65 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
66 | ||
1fa6aead | 67 | static LIST_HEAD(dev_list); |
9f2482b9 | 68 | static DEFINE_SPINLOCK(dev_list_lock); |
1fa6aead | 69 | static struct task_struct *nvme_thread; |
9a6b9458 | 70 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 71 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 72 | |
1c63dc66 CH |
73 | struct nvme_dev; |
74 | struct nvme_queue; | |
b3fffdef | 75 | |
4cc06521 | 76 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 77 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
5c8809e6 | 78 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev); |
a5cdb68c | 79 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 80 | |
1c63dc66 CH |
81 | /* |
82 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
83 | */ | |
84 | struct nvme_dev { | |
85 | struct list_head node; | |
86 | struct nvme_queue **queues; | |
87 | struct blk_mq_tag_set tagset; | |
88 | struct blk_mq_tag_set admin_tagset; | |
89 | u32 __iomem *dbs; | |
90 | struct device *dev; | |
91 | struct dma_pool *prp_page_pool; | |
92 | struct dma_pool *prp_small_pool; | |
93 | unsigned queue_count; | |
94 | unsigned online_queues; | |
95 | unsigned max_qid; | |
96 | int q_depth; | |
97 | u32 db_stride; | |
1c63dc66 CH |
98 | struct msix_entry *entry; |
99 | void __iomem *bar; | |
1c63dc66 | 100 | struct work_struct reset_work; |
1c63dc66 | 101 | struct work_struct scan_work; |
5c8809e6 | 102 | struct work_struct remove_work; |
9396dec9 | 103 | struct work_struct async_work; |
77bf25ea | 104 | struct mutex shutdown_lock; |
1c63dc66 | 105 | bool subsystem; |
1c63dc66 CH |
106 | void __iomem *cmb; |
107 | dma_addr_t cmb_dma_addr; | |
108 | u64 cmb_size; | |
109 | u32 cmbsz; | |
fd634f41 | 110 | unsigned long flags; |
db3cbfff | 111 | |
fd634f41 | 112 | #define NVME_CTRL_RESETTING 0 |
1c63dc66 CH |
113 | |
114 | struct nvme_ctrl ctrl; | |
db3cbfff | 115 | struct completion ioq_wait; |
4d115420 | 116 | }; |
1fa6aead | 117 | |
1c63dc66 CH |
118 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
119 | { | |
120 | return container_of(ctrl, struct nvme_dev, ctrl); | |
121 | } | |
122 | ||
b60503ba MW |
123 | /* |
124 | * An NVM Express queue. Each device has at least two (one for admin | |
125 | * commands and one for I/O commands). | |
126 | */ | |
127 | struct nvme_queue { | |
128 | struct device *q_dmadev; | |
091b6092 | 129 | struct nvme_dev *dev; |
3193f07b | 130 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
131 | spinlock_t q_lock; |
132 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 133 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 134 | volatile struct nvme_completion *cqes; |
42483228 | 135 | struct blk_mq_tags **tags; |
b60503ba MW |
136 | dma_addr_t sq_dma_addr; |
137 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
138 | u32 __iomem *q_db; |
139 | u16 q_depth; | |
6222d172 | 140 | s16 cq_vector; |
b60503ba MW |
141 | u16 sq_head; |
142 | u16 sq_tail; | |
143 | u16 cq_head; | |
c30341dc | 144 | u16 qid; |
e9539f47 MW |
145 | u8 cq_phase; |
146 | u8 cqe_seen; | |
b60503ba MW |
147 | }; |
148 | ||
71bd150c CH |
149 | /* |
150 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
151 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 152 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
153 | * allocated to store the PRP list. |
154 | */ | |
155 | struct nvme_iod { | |
f4800d6d CH |
156 | struct nvme_queue *nvmeq; |
157 | int aborted; | |
71bd150c | 158 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
159 | int nents; /* Used in scatterlist */ |
160 | int length; /* Of data, in bytes */ | |
161 | dma_addr_t first_dma; | |
bf684057 | 162 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
163 | struct scatterlist *sg; |
164 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
165 | }; |
166 | ||
167 | /* | |
168 | * Check we didin't inadvertently grow the command struct | |
169 | */ | |
170 | static inline void _nvme_check_size(void) | |
171 | { | |
172 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
173 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
174 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
175 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
176 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 177 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 178 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
179 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
180 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
181 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
182 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 183 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
184 | } |
185 | ||
ac3dd5bd JA |
186 | /* |
187 | * Max size of iod being embedded in the request payload | |
188 | */ | |
189 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 190 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
191 | |
192 | /* | |
193 | * Will slightly overestimate the number of pages needed. This is OK | |
194 | * as it only leads to a small amount of wasted memory for the lifetime of | |
195 | * the I/O. | |
196 | */ | |
197 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
198 | { | |
5fd4ce1b CH |
199 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
200 | dev->ctrl.page_size); | |
ac3dd5bd JA |
201 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
202 | } | |
203 | ||
f4800d6d CH |
204 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
205 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 206 | { |
f4800d6d CH |
207 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
208 | sizeof(struct scatterlist) * nseg; | |
209 | } | |
ac3dd5bd | 210 | |
f4800d6d CH |
211 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
212 | { | |
213 | return sizeof(struct nvme_iod) + | |
214 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
215 | } |
216 | ||
a4aea562 MB |
217 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
218 | unsigned int hctx_idx) | |
e85248e5 | 219 | { |
a4aea562 MB |
220 | struct nvme_dev *dev = data; |
221 | struct nvme_queue *nvmeq = dev->queues[0]; | |
222 | ||
42483228 KB |
223 | WARN_ON(hctx_idx != 0); |
224 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
225 | WARN_ON(nvmeq->tags); | |
226 | ||
a4aea562 | 227 | hctx->driver_data = nvmeq; |
42483228 | 228 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 229 | return 0; |
e85248e5 MW |
230 | } |
231 | ||
4af0e21c KB |
232 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
233 | { | |
234 | struct nvme_queue *nvmeq = hctx->driver_data; | |
235 | ||
236 | nvmeq->tags = NULL; | |
237 | } | |
238 | ||
a4aea562 MB |
239 | static int nvme_admin_init_request(void *data, struct request *req, |
240 | unsigned int hctx_idx, unsigned int rq_idx, | |
241 | unsigned int numa_node) | |
22404274 | 242 | { |
a4aea562 | 243 | struct nvme_dev *dev = data; |
f4800d6d | 244 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
245 | struct nvme_queue *nvmeq = dev->queues[0]; |
246 | ||
247 | BUG_ON(!nvmeq); | |
f4800d6d | 248 | iod->nvmeq = nvmeq; |
a4aea562 | 249 | return 0; |
22404274 KB |
250 | } |
251 | ||
a4aea562 MB |
252 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
253 | unsigned int hctx_idx) | |
b60503ba | 254 | { |
a4aea562 | 255 | struct nvme_dev *dev = data; |
42483228 | 256 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 257 | |
42483228 KB |
258 | if (!nvmeq->tags) |
259 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 260 | |
42483228 | 261 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
262 | hctx->driver_data = nvmeq; |
263 | return 0; | |
b60503ba MW |
264 | } |
265 | ||
a4aea562 MB |
266 | static int nvme_init_request(void *data, struct request *req, |
267 | unsigned int hctx_idx, unsigned int rq_idx, | |
268 | unsigned int numa_node) | |
b60503ba | 269 | { |
a4aea562 | 270 | struct nvme_dev *dev = data; |
f4800d6d | 271 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
272 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
273 | ||
274 | BUG_ON(!nvmeq); | |
f4800d6d | 275 | iod->nvmeq = nvmeq; |
a4aea562 MB |
276 | return 0; |
277 | } | |
278 | ||
adf68f21 CH |
279 | static void nvme_complete_async_event(struct nvme_dev *dev, |
280 | struct nvme_completion *cqe) | |
a4aea562 | 281 | { |
adf68f21 CH |
282 | u16 status = le16_to_cpu(cqe->status) >> 1; |
283 | u32 result = le32_to_cpu(cqe->result); | |
a4aea562 | 284 | |
9396dec9 | 285 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) { |
adf68f21 | 286 | ++dev->ctrl.event_limit; |
9396dec9 CH |
287 | queue_work(nvme_workq, &dev->async_work); |
288 | } | |
289 | ||
a5768aa8 KB |
290 | if (status != NVME_SC_SUCCESS) |
291 | return; | |
292 | ||
293 | switch (result & 0xff07) { | |
294 | case NVME_AER_NOTICE_NS_CHANGED: | |
1b3c47c1 | 295 | dev_info(dev->ctrl.device, "rescanning\n"); |
adf68f21 | 296 | queue_work(nvme_workq, &dev->scan_work); |
a5768aa8 | 297 | default: |
1b3c47c1 | 298 | dev_warn(dev->ctrl.device, "async event result %08x\n", result); |
a4aea562 | 299 | } |
b60503ba MW |
300 | } |
301 | ||
302 | /** | |
adf68f21 | 303 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
304 | * @nvmeq: The queue to use |
305 | * @cmd: The command to send | |
306 | * | |
307 | * Safe to use from interrupt context | |
308 | */ | |
e3f879bf SB |
309 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
310 | struct nvme_command *cmd) | |
b60503ba | 311 | { |
a4aea562 MB |
312 | u16 tail = nvmeq->sq_tail; |
313 | ||
8ffaadf7 JD |
314 | if (nvmeq->sq_cmds_io) |
315 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
316 | else | |
317 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
318 | ||
b60503ba MW |
319 | if (++tail == nvmeq->q_depth) |
320 | tail = 0; | |
7547881d | 321 | writel(tail, nvmeq->q_db); |
b60503ba | 322 | nvmeq->sq_tail = tail; |
b60503ba MW |
323 | } |
324 | ||
f4800d6d | 325 | static __le64 **iod_list(struct request *req) |
b60503ba | 326 | { |
f4800d6d CH |
327 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
328 | return (__le64 **)(iod->sg + req->nr_phys_segments); | |
b60503ba MW |
329 | } |
330 | ||
f4800d6d | 331 | static int nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 332 | { |
f4800d6d CH |
333 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
334 | int nseg = rq->nr_phys_segments; | |
335 | unsigned size; | |
ac3dd5bd | 336 | |
f4800d6d CH |
337 | if (rq->cmd_flags & REQ_DISCARD) |
338 | size = sizeof(struct nvme_dsm_range); | |
339 | else | |
340 | size = blk_rq_bytes(rq); | |
ac3dd5bd | 341 | |
f4800d6d CH |
342 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
343 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
344 | if (!iod->sg) | |
345 | return BLK_MQ_RQ_QUEUE_BUSY; | |
346 | } else { | |
347 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
348 | } |
349 | ||
f4800d6d CH |
350 | iod->aborted = 0; |
351 | iod->npages = -1; | |
352 | iod->nents = 0; | |
353 | iod->length = size; | |
354 | return 0; | |
ac3dd5bd JA |
355 | } |
356 | ||
f4800d6d | 357 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 358 | { |
f4800d6d | 359 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 360 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 361 | int i; |
f4800d6d | 362 | __le64 **list = iod_list(req); |
eca18b23 MW |
363 | dma_addr_t prp_dma = iod->first_dma; |
364 | ||
365 | if (iod->npages == 0) | |
366 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
367 | for (i = 0; i < iod->npages; i++) { | |
368 | __le64 *prp_list = list[i]; | |
369 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
370 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
371 | prp_dma = next_prp_dma; | |
372 | } | |
ac3dd5bd | 373 | |
f4800d6d CH |
374 | if (iod->sg != iod->inline_sg) |
375 | kfree(iod->sg); | |
b4ff9c8d KB |
376 | } |
377 | ||
52b68d7e | 378 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
379 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
380 | { | |
381 | if (be32_to_cpu(pi->ref_tag) == v) | |
382 | pi->ref_tag = cpu_to_be32(p); | |
383 | } | |
384 | ||
385 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
386 | { | |
387 | if (be32_to_cpu(pi->ref_tag) == p) | |
388 | pi->ref_tag = cpu_to_be32(v); | |
389 | } | |
390 | ||
391 | /** | |
392 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
393 | * | |
394 | * The virtual start sector is the one that was originally submitted by the | |
395 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
396 | * start sector may be different. Remap protection information to match the | |
397 | * physical LBA on writes, and back to the original seed on reads. | |
398 | * | |
399 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
400 | */ | |
401 | static void nvme_dif_remap(struct request *req, | |
402 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
403 | { | |
404 | struct nvme_ns *ns = req->rq_disk->private_data; | |
405 | struct bio_integrity_payload *bip; | |
406 | struct t10_pi_tuple *pi; | |
407 | void *p, *pmap; | |
408 | u32 i, nlb, ts, phys, virt; | |
409 | ||
410 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
411 | return; | |
412 | ||
413 | bip = bio_integrity(req->bio); | |
414 | if (!bip) | |
415 | return; | |
416 | ||
417 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
418 | |
419 | p = pmap; | |
420 | virt = bip_get_seed(bip); | |
421 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
422 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 423 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
424 | |
425 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
426 | pi = (struct t10_pi_tuple *)p; | |
427 | dif_swap(phys, virt, pi); | |
428 | p += ts; | |
429 | } | |
430 | kunmap_atomic(pmap); | |
431 | } | |
52b68d7e KB |
432 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
433 | static void nvme_dif_remap(struct request *req, | |
434 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
435 | { | |
436 | } | |
437 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
438 | { | |
439 | } | |
440 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
441 | { | |
442 | } | |
52b68d7e KB |
443 | #endif |
444 | ||
f4800d6d | 445 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req, |
69d2b571 | 446 | int total_len) |
ff22b54f | 447 | { |
f4800d6d | 448 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 449 | struct dma_pool *pool; |
eca18b23 MW |
450 | int length = total_len; |
451 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
452 | int dma_len = sg_dma_len(sg); |
453 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 454 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 455 | int offset = dma_addr & (page_size - 1); |
e025344c | 456 | __le64 *prp_list; |
f4800d6d | 457 | __le64 **list = iod_list(req); |
e025344c | 458 | dma_addr_t prp_dma; |
eca18b23 | 459 | int nprps, i; |
ff22b54f | 460 | |
1d090624 | 461 | length -= (page_size - offset); |
ff22b54f | 462 | if (length <= 0) |
69d2b571 | 463 | return true; |
ff22b54f | 464 | |
1d090624 | 465 | dma_len -= (page_size - offset); |
ff22b54f | 466 | if (dma_len) { |
1d090624 | 467 | dma_addr += (page_size - offset); |
ff22b54f MW |
468 | } else { |
469 | sg = sg_next(sg); | |
470 | dma_addr = sg_dma_address(sg); | |
471 | dma_len = sg_dma_len(sg); | |
472 | } | |
473 | ||
1d090624 | 474 | if (length <= page_size) { |
edd10d33 | 475 | iod->first_dma = dma_addr; |
69d2b571 | 476 | return true; |
e025344c SMM |
477 | } |
478 | ||
1d090624 | 479 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
480 | if (nprps <= (256 / 8)) { |
481 | pool = dev->prp_small_pool; | |
eca18b23 | 482 | iod->npages = 0; |
99802a7a MW |
483 | } else { |
484 | pool = dev->prp_page_pool; | |
eca18b23 | 485 | iod->npages = 1; |
99802a7a MW |
486 | } |
487 | ||
69d2b571 | 488 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 489 | if (!prp_list) { |
edd10d33 | 490 | iod->first_dma = dma_addr; |
eca18b23 | 491 | iod->npages = -1; |
69d2b571 | 492 | return false; |
b77954cb | 493 | } |
eca18b23 MW |
494 | list[0] = prp_list; |
495 | iod->first_dma = prp_dma; | |
e025344c SMM |
496 | i = 0; |
497 | for (;;) { | |
1d090624 | 498 | if (i == page_size >> 3) { |
e025344c | 499 | __le64 *old_prp_list = prp_list; |
69d2b571 | 500 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 501 | if (!prp_list) |
69d2b571 | 502 | return false; |
eca18b23 | 503 | list[iod->npages++] = prp_list; |
7523d834 MW |
504 | prp_list[0] = old_prp_list[i - 1]; |
505 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
506 | i = 1; | |
e025344c SMM |
507 | } |
508 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
509 | dma_len -= page_size; |
510 | dma_addr += page_size; | |
511 | length -= page_size; | |
e025344c SMM |
512 | if (length <= 0) |
513 | break; | |
514 | if (dma_len > 0) | |
515 | continue; | |
516 | BUG_ON(dma_len < 0); | |
517 | sg = sg_next(sg); | |
518 | dma_addr = sg_dma_address(sg); | |
519 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
520 | } |
521 | ||
69d2b571 | 522 | return true; |
ff22b54f MW |
523 | } |
524 | ||
f4800d6d | 525 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
ba1ca37e | 526 | struct nvme_command *cmnd) |
d29ec824 | 527 | { |
f4800d6d | 528 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
529 | struct request_queue *q = req->q; |
530 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
531 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
532 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
d29ec824 | 533 | |
ba1ca37e CH |
534 | sg_init_table(iod->sg, req->nr_phys_segments); |
535 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
536 | if (!iod->nents) | |
537 | goto out; | |
d29ec824 | 538 | |
ba1ca37e CH |
539 | ret = BLK_MQ_RQ_QUEUE_BUSY; |
540 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
541 | goto out; | |
d29ec824 | 542 | |
f4800d6d | 543 | if (!nvme_setup_prps(dev, req, blk_rq_bytes(req))) |
ba1ca37e | 544 | goto out_unmap; |
0e5e4f0e | 545 | |
ba1ca37e CH |
546 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
547 | if (blk_integrity_rq(req)) { | |
548 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
549 | goto out_unmap; | |
0e5e4f0e | 550 | |
bf684057 CH |
551 | sg_init_table(&iod->meta_sg, 1); |
552 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 553 | goto out_unmap; |
0e5e4f0e | 554 | |
ba1ca37e CH |
555 | if (rq_data_dir(req)) |
556 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 557 | |
bf684057 | 558 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 559 | goto out_unmap; |
d29ec824 | 560 | } |
00df5cb4 | 561 | |
ba1ca37e CH |
562 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
563 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
564 | if (blk_integrity_rq(req)) | |
bf684057 | 565 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e | 566 | return BLK_MQ_RQ_QUEUE_OK; |
00df5cb4 | 567 | |
ba1ca37e CH |
568 | out_unmap: |
569 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
570 | out: | |
571 | return ret; | |
00df5cb4 MW |
572 | } |
573 | ||
f4800d6d | 574 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 575 | { |
f4800d6d | 576 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
577 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
578 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
579 | ||
580 | if (iod->nents) { | |
581 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
582 | if (blk_integrity_rq(req)) { | |
583 | if (!rq_data_dir(req)) | |
584 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 585 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 586 | } |
e19b127f | 587 | } |
e1e5e564 | 588 | |
f4800d6d | 589 | nvme_free_iod(dev, req); |
d4f6c3ab | 590 | } |
b60503ba | 591 | |
a4aea562 MB |
592 | /* |
593 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
594 | * worth having a special pool for these or additional cases to handle freeing | |
595 | * the iod. | |
596 | */ | |
ba1ca37e | 597 | static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
f4800d6d | 598 | struct request *req, struct nvme_command *cmnd) |
0e5e4f0e | 599 | { |
f4800d6d | 600 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e | 601 | struct nvme_dsm_range *range; |
b60503ba | 602 | |
ba1ca37e CH |
603 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, |
604 | &iod->first_dma); | |
605 | if (!range) | |
606 | return BLK_MQ_RQ_QUEUE_BUSY; | |
f4800d6d | 607 | iod_list(req)[0] = (__le64 *)range; |
ba1ca37e | 608 | iod->npages = 0; |
0e5e4f0e | 609 | |
0e5e4f0e | 610 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
611 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
612 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 613 | |
ba1ca37e CH |
614 | memset(cmnd, 0, sizeof(*cmnd)); |
615 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
616 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
617 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
618 | cmnd->dsm.nr = 0; | |
619 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
620 | return BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 KB |
621 | } |
622 | ||
d29ec824 CH |
623 | /* |
624 | * NOTE: ns is NULL when called on the admin queue. | |
625 | */ | |
a4aea562 MB |
626 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
627 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 628 | { |
a4aea562 MB |
629 | struct nvme_ns *ns = hctx->queue->queuedata; |
630 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 631 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 632 | struct request *req = bd->rq; |
ba1ca37e CH |
633 | struct nvme_command cmnd; |
634 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 635 | |
e1e5e564 KB |
636 | /* |
637 | * If formated with metadata, require the block layer provide a buffer | |
638 | * unless this namespace is formated such that the metadata can be | |
639 | * stripped/generated by the controller with PRACT=1. | |
640 | */ | |
d29ec824 | 641 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
642 | if (!(ns->pi_type && ns->ms == 8) && |
643 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 644 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
645 | return BLK_MQ_RQ_QUEUE_OK; |
646 | } | |
647 | } | |
648 | ||
f4800d6d CH |
649 | ret = nvme_init_iod(req, dev); |
650 | if (ret) | |
651 | return ret; | |
a4aea562 | 652 | |
a4aea562 | 653 | if (req->cmd_flags & REQ_DISCARD) { |
f4800d6d | 654 | ret = nvme_setup_discard(nvmeq, ns, req, &cmnd); |
ba1ca37e CH |
655 | } else { |
656 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
657 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); | |
658 | else if (req->cmd_flags & REQ_FLUSH) | |
659 | nvme_setup_flush(ns, &cmnd); | |
660 | else | |
661 | nvme_setup_rw(ns, req, &cmnd); | |
a4aea562 | 662 | |
ba1ca37e | 663 | if (req->nr_phys_segments) |
f4800d6d | 664 | ret = nvme_map_data(dev, req, &cmnd); |
edd10d33 | 665 | } |
a4aea562 | 666 | |
ba1ca37e CH |
667 | if (ret) |
668 | goto out; | |
a4aea562 | 669 | |
ba1ca37e | 670 | cmnd.common.command_id = req->tag; |
aae239e1 | 671 | blk_mq_start_request(req); |
a4aea562 | 672 | |
ba1ca37e CH |
673 | spin_lock_irq(&nvmeq->q_lock); |
674 | __nvme_submit_cmd(nvmeq, &cmnd); | |
a4aea562 MB |
675 | nvme_process_cq(nvmeq); |
676 | spin_unlock_irq(&nvmeq->q_lock); | |
677 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 678 | out: |
f4800d6d | 679 | nvme_free_iod(dev, req); |
ba1ca37e | 680 | return ret; |
b60503ba | 681 | } |
e1e5e564 | 682 | |
eee417b0 CH |
683 | static void nvme_complete_rq(struct request *req) |
684 | { | |
f4800d6d CH |
685 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
686 | struct nvme_dev *dev = iod->nvmeq->dev; | |
eee417b0 | 687 | int error = 0; |
e1e5e564 | 688 | |
f4800d6d | 689 | nvme_unmap_data(dev, req); |
e1e5e564 | 690 | |
eee417b0 CH |
691 | if (unlikely(req->errors)) { |
692 | if (nvme_req_needs_retry(req, req->errors)) { | |
693 | nvme_requeue_req(req); | |
694 | return; | |
e1e5e564 | 695 | } |
1974b1ae | 696 | |
eee417b0 CH |
697 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) |
698 | error = req->errors; | |
699 | else | |
700 | error = nvme_error_status(req->errors); | |
701 | } | |
a4aea562 | 702 | |
f4800d6d | 703 | if (unlikely(iod->aborted)) { |
1b3c47c1 | 704 | dev_warn(dev->ctrl.device, |
eee417b0 CH |
705 | "completing aborted command with status: %04x\n", |
706 | req->errors); | |
707 | } | |
a4aea562 | 708 | |
eee417b0 | 709 | blk_mq_end_request(req, error); |
b60503ba MW |
710 | } |
711 | ||
a0fa9647 | 712 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 713 | { |
82123460 | 714 | u16 head, phase; |
b60503ba | 715 | |
b60503ba | 716 | head = nvmeq->cq_head; |
82123460 | 717 | phase = nvmeq->cq_phase; |
b60503ba MW |
718 | |
719 | for (;;) { | |
b60503ba | 720 | struct nvme_completion cqe = nvmeq->cqes[head]; |
adf68f21 | 721 | u16 status = le16_to_cpu(cqe.status); |
eee417b0 | 722 | struct request *req; |
adf68f21 CH |
723 | |
724 | if ((status & 1) != phase) | |
b60503ba MW |
725 | break; |
726 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
727 | if (++head == nvmeq->q_depth) { | |
728 | head = 0; | |
82123460 | 729 | phase = !phase; |
b60503ba | 730 | } |
adf68f21 | 731 | |
a0fa9647 JA |
732 | if (tag && *tag == cqe.command_id) |
733 | *tag = -1; | |
adf68f21 | 734 | |
aae239e1 | 735 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 736 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
737 | "invalid id %d completed on queue %d\n", |
738 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
739 | continue; | |
740 | } | |
741 | ||
adf68f21 CH |
742 | /* |
743 | * AEN requests are special as they don't time out and can | |
744 | * survive any kind of queue freeze and often don't respond to | |
745 | * aborts. We don't even bother to allocate a struct request | |
746 | * for them but rather special case them here. | |
747 | */ | |
748 | if (unlikely(nvmeq->qid == 0 && | |
749 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
750 | nvme_complete_async_event(nvmeq->dev, &cqe); | |
751 | continue; | |
752 | } | |
753 | ||
eee417b0 CH |
754 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
755 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { | |
756 | u32 result = le32_to_cpu(cqe.result); | |
757 | req->special = (void *)(uintptr_t)result; | |
758 | } | |
759 | blk_mq_complete_request(req, status >> 1); | |
760 | ||
b60503ba MW |
761 | } |
762 | ||
763 | /* If the controller ignores the cq head doorbell and continuously | |
764 | * writes to the queue, it is theoretically possible to wrap around | |
765 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
766 | * requires that 0.1% of your interrupts are handled, so this isn't | |
767 | * a big problem. | |
768 | */ | |
82123460 | 769 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 770 | return; |
b60503ba | 771 | |
604e8c8d KB |
772 | if (likely(nvmeq->cq_vector >= 0)) |
773 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 774 | nvmeq->cq_head = head; |
82123460 | 775 | nvmeq->cq_phase = phase; |
b60503ba | 776 | |
e9539f47 | 777 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
778 | } |
779 | ||
780 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
781 | { | |
782 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
783 | } |
784 | ||
785 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
786 | { |
787 | irqreturn_t result; | |
788 | struct nvme_queue *nvmeq = data; | |
789 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
790 | nvme_process_cq(nvmeq); |
791 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
792 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
793 | spin_unlock(&nvmeq->q_lock); |
794 | return result; | |
795 | } | |
796 | ||
797 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
798 | { | |
799 | struct nvme_queue *nvmeq = data; | |
800 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
801 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
802 | return IRQ_NONE; | |
803 | return IRQ_WAKE_THREAD; | |
804 | } | |
805 | ||
a0fa9647 JA |
806 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
807 | { | |
808 | struct nvme_queue *nvmeq = hctx->driver_data; | |
809 | ||
810 | if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == | |
811 | nvmeq->cq_phase) { | |
812 | spin_lock_irq(&nvmeq->q_lock); | |
813 | __nvme_process_cq(nvmeq, &tag); | |
814 | spin_unlock_irq(&nvmeq->q_lock); | |
815 | ||
816 | if (tag == -1) | |
817 | return 1; | |
818 | } | |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
9396dec9 | 823 | static void nvme_async_event_work(struct work_struct *work) |
b60503ba | 824 | { |
9396dec9 CH |
825 | struct nvme_dev *dev = container_of(work, struct nvme_dev, async_work); |
826 | struct nvme_queue *nvmeq = dev->queues[0]; | |
a4aea562 | 827 | struct nvme_command c; |
b60503ba | 828 | |
a4aea562 MB |
829 | memset(&c, 0, sizeof(c)); |
830 | c.common.opcode = nvme_admin_async_event; | |
3c0cf138 | 831 | |
9396dec9 CH |
832 | spin_lock_irq(&nvmeq->q_lock); |
833 | while (dev->ctrl.event_limit > 0) { | |
834 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + | |
835 | --dev->ctrl.event_limit; | |
836 | __nvme_submit_cmd(nvmeq, &c); | |
837 | } | |
838 | spin_unlock_irq(&nvmeq->q_lock); | |
f705f837 CH |
839 | } |
840 | ||
b60503ba | 841 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 842 | { |
b60503ba MW |
843 | struct nvme_command c; |
844 | ||
845 | memset(&c, 0, sizeof(c)); | |
846 | c.delete_queue.opcode = opcode; | |
847 | c.delete_queue.qid = cpu_to_le16(id); | |
848 | ||
1c63dc66 | 849 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
850 | } |
851 | ||
b60503ba MW |
852 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
853 | struct nvme_queue *nvmeq) | |
854 | { | |
b60503ba MW |
855 | struct nvme_command c; |
856 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
857 | ||
d29ec824 CH |
858 | /* |
859 | * Note: we (ab)use the fact the the prp fields survive if no data | |
860 | * is attached to the request. | |
861 | */ | |
b60503ba MW |
862 | memset(&c, 0, sizeof(c)); |
863 | c.create_cq.opcode = nvme_admin_create_cq; | |
864 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
865 | c.create_cq.cqid = cpu_to_le16(qid); | |
866 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
867 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
868 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
869 | ||
1c63dc66 | 870 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
871 | } |
872 | ||
873 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
874 | struct nvme_queue *nvmeq) | |
875 | { | |
b60503ba MW |
876 | struct nvme_command c; |
877 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
878 | ||
d29ec824 CH |
879 | /* |
880 | * Note: we (ab)use the fact the the prp fields survive if no data | |
881 | * is attached to the request. | |
882 | */ | |
b60503ba MW |
883 | memset(&c, 0, sizeof(c)); |
884 | c.create_sq.opcode = nvme_admin_create_sq; | |
885 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
886 | c.create_sq.sqid = cpu_to_le16(qid); | |
887 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
888 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
889 | c.create_sq.cqid = cpu_to_le16(qid); | |
890 | ||
1c63dc66 | 891 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
892 | } |
893 | ||
894 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
895 | { | |
896 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
897 | } | |
898 | ||
899 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
900 | { | |
901 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
902 | } | |
903 | ||
e7a2a87d | 904 | static void abort_endio(struct request *req, int error) |
bc5fc7e4 | 905 | { |
f4800d6d CH |
906 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
907 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d CH |
908 | u32 result = (u32)(uintptr_t)req->special; |
909 | u16 status = req->errors; | |
e44ac588 | 910 | |
1b3c47c1 SG |
911 | dev_warn(nvmeq->dev->ctrl.device, |
912 | "Abort status:%x result:%x", status, result); | |
e7a2a87d | 913 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
d29ec824 | 914 | |
e7a2a87d | 915 | blk_mq_free_request(req); |
bc5fc7e4 MW |
916 | } |
917 | ||
31c7c7d2 | 918 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 919 | { |
f4800d6d CH |
920 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
921 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 922 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 923 | struct request *abort_req; |
a4aea562 | 924 | struct nvme_command cmd; |
c30341dc | 925 | |
31c7c7d2 | 926 | /* |
fd634f41 CH |
927 | * Shutdown immediately if controller times out while starting. The |
928 | * reset work will see the pci device disabled when it gets the forced | |
929 | * cancellation error. All outstanding requests are completed on | |
930 | * shutdown, so we return BLK_EH_HANDLED. | |
931 | */ | |
932 | if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) { | |
1b3c47c1 | 933 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
934 | "I/O %d QID %d timeout, disable controller\n", |
935 | req->tag, nvmeq->qid); | |
a5cdb68c | 936 | nvme_dev_disable(dev, false); |
fd634f41 CH |
937 | req->errors = NVME_SC_CANCELLED; |
938 | return BLK_EH_HANDLED; | |
c30341dc KB |
939 | } |
940 | ||
fd634f41 CH |
941 | /* |
942 | * Shutdown the controller immediately and schedule a reset if the | |
943 | * command was already aborted once before and still hasn't been | |
944 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 945 | */ |
f4800d6d | 946 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 947 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
948 | "I/O %d QID %d timeout, reset controller\n", |
949 | req->tag, nvmeq->qid); | |
a5cdb68c | 950 | nvme_dev_disable(dev, false); |
e1569a16 | 951 | queue_work(nvme_workq, &dev->reset_work); |
c30341dc | 952 | |
e1569a16 KB |
953 | /* |
954 | * Mark the request as handled, since the inline shutdown | |
955 | * forces all outstanding requests to complete. | |
956 | */ | |
957 | req->errors = NVME_SC_CANCELLED; | |
958 | return BLK_EH_HANDLED; | |
c30341dc | 959 | } |
c30341dc | 960 | |
f4800d6d | 961 | iod->aborted = 1; |
c30341dc | 962 | |
e7a2a87d | 963 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 964 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 965 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 966 | } |
a4aea562 | 967 | |
c30341dc KB |
968 | memset(&cmd, 0, sizeof(cmd)); |
969 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 970 | cmd.abort.cid = req->tag; |
c30341dc | 971 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 972 | |
1b3c47c1 SG |
973 | dev_warn(nvmeq->dev->ctrl.device, |
974 | "I/O %d QID %d timeout, aborting\n", | |
975 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
976 | |
977 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
978 | BLK_MQ_REQ_NOWAIT); | |
979 | if (IS_ERR(abort_req)) { | |
980 | atomic_inc(&dev->ctrl.abort_limit); | |
981 | return BLK_EH_RESET_TIMER; | |
982 | } | |
983 | ||
984 | abort_req->timeout = ADMIN_TIMEOUT; | |
985 | abort_req->end_io_data = NULL; | |
986 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 987 | |
31c7c7d2 CH |
988 | /* |
989 | * The aborted req will be completed on receiving the abort req. | |
990 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
991 | * as the device then is in a faulty state. | |
992 | */ | |
993 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
994 | } |
995 | ||
42483228 | 996 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 997 | { |
a4aea562 | 998 | struct nvme_queue *nvmeq = data; |
aae239e1 | 999 | int status; |
cef6a948 KB |
1000 | |
1001 | if (!blk_mq_request_started(req)) | |
1002 | return; | |
a09115b2 | 1003 | |
1b3c47c1 | 1004 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 | 1005 | "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid); |
a4aea562 | 1006 | |
1d49c38c | 1007 | status = NVME_SC_ABORT_REQ; |
cef6a948 | 1008 | if (blk_queue_dying(req->q)) |
aae239e1 CH |
1009 | status |= NVME_SC_DNR; |
1010 | blk_mq_complete_request(req, status); | |
a4aea562 | 1011 | } |
22404274 | 1012 | |
a4aea562 MB |
1013 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1014 | { | |
9e866774 MW |
1015 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1016 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1017 | if (nvmeq->sq_cmds) |
1018 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1019 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1020 | kfree(nvmeq); | |
1021 | } | |
1022 | ||
a1a5ef99 | 1023 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1024 | { |
1025 | int i; | |
1026 | ||
a1a5ef99 | 1027 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1028 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1029 | dev->queue_count--; |
a4aea562 | 1030 | dev->queues[i] = NULL; |
f435c282 | 1031 | nvme_free_queue(nvmeq); |
121c7ad4 | 1032 | } |
22404274 KB |
1033 | } |
1034 | ||
4d115420 KB |
1035 | /** |
1036 | * nvme_suspend_queue - put queue into suspended state | |
1037 | * @nvmeq - queue to suspend | |
4d115420 KB |
1038 | */ |
1039 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1040 | { |
2b25d981 | 1041 | int vector; |
b60503ba | 1042 | |
a09115b2 | 1043 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1044 | if (nvmeq->cq_vector == -1) { |
1045 | spin_unlock_irq(&nvmeq->q_lock); | |
1046 | return 1; | |
1047 | } | |
1048 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1049 | nvmeq->dev->online_queues--; |
2b25d981 | 1050 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1051 | spin_unlock_irq(&nvmeq->q_lock); |
1052 | ||
1c63dc66 | 1053 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 1054 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1055 | |
aba2080f MW |
1056 | irq_set_affinity_hint(vector, NULL); |
1057 | free_irq(vector, nvmeq); | |
b60503ba | 1058 | |
4d115420 KB |
1059 | return 0; |
1060 | } | |
b60503ba | 1061 | |
4d115420 KB |
1062 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1063 | { | |
22404274 | 1064 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1065 | if (nvmeq->tags && *nvmeq->tags) |
1066 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1067 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1068 | } |
1069 | ||
a5cdb68c | 1070 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1071 | { |
a5cdb68c | 1072 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
1073 | |
1074 | if (!nvmeq) | |
1075 | return; | |
1076 | if (nvme_suspend_queue(nvmeq)) | |
1077 | return; | |
1078 | ||
a5cdb68c KB |
1079 | if (shutdown) |
1080 | nvme_shutdown_ctrl(&dev->ctrl); | |
1081 | else | |
1082 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
1083 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
1084 | |
1085 | spin_lock_irq(&nvmeq->q_lock); | |
1086 | nvme_process_cq(nvmeq); | |
1087 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1088 | } |
1089 | ||
8ffaadf7 JD |
1090 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1091 | int entry_size) | |
1092 | { | |
1093 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1094 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1095 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1096 | |
1097 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1098 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1099 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1100 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1101 | |
1102 | /* | |
1103 | * Ensure the reduced q_depth is above some threshold where it | |
1104 | * would be better to map queues in system memory with the | |
1105 | * original depth | |
1106 | */ | |
1107 | if (q_depth < 64) | |
1108 | return -ENOMEM; | |
1109 | } | |
1110 | ||
1111 | return q_depth; | |
1112 | } | |
1113 | ||
1114 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1115 | int qid, int depth) | |
1116 | { | |
1117 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1118 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1119 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1120 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1121 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1122 | } else { | |
1123 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1124 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1125 | if (!nvmeq->sq_cmds) | |
1126 | return -ENOMEM; | |
1127 | } | |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
b60503ba | 1132 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1133 | int depth) |
b60503ba | 1134 | { |
a4aea562 | 1135 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1136 | if (!nvmeq) |
1137 | return NULL; | |
1138 | ||
e75ec752 | 1139 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1140 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1141 | if (!nvmeq->cqes) |
1142 | goto free_nvmeq; | |
b60503ba | 1143 | |
8ffaadf7 | 1144 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1145 | goto free_cqdma; |
1146 | ||
e75ec752 | 1147 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1148 | nvmeq->dev = dev; |
3193f07b | 1149 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1150 | dev->ctrl.instance, qid); |
b60503ba MW |
1151 | spin_lock_init(&nvmeq->q_lock); |
1152 | nvmeq->cq_head = 0; | |
82123460 | 1153 | nvmeq->cq_phase = 1; |
b80d5ccc | 1154 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1155 | nvmeq->q_depth = depth; |
c30341dc | 1156 | nvmeq->qid = qid; |
758dd7fd | 1157 | nvmeq->cq_vector = -1; |
a4aea562 | 1158 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1159 | dev->queue_count++; |
1160 | ||
b60503ba MW |
1161 | return nvmeq; |
1162 | ||
1163 | free_cqdma: | |
e75ec752 | 1164 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1165 | nvmeq->cq_dma_addr); |
1166 | free_nvmeq: | |
1167 | kfree(nvmeq); | |
1168 | return NULL; | |
1169 | } | |
1170 | ||
3001082c MW |
1171 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1172 | const char *name) | |
1173 | { | |
58ffacb5 MW |
1174 | if (use_threaded_interrupts) |
1175 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1176 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1177 | name, nvmeq); |
3001082c | 1178 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1179 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1180 | } |
1181 | ||
22404274 | 1182 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1183 | { |
22404274 | 1184 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1185 | |
7be50e93 | 1186 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1187 | nvmeq->sq_tail = 0; |
1188 | nvmeq->cq_head = 0; | |
1189 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1190 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1191 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1192 | dev->online_queues++; |
7be50e93 | 1193 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1194 | } |
1195 | ||
1196 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1197 | { | |
1198 | struct nvme_dev *dev = nvmeq->dev; | |
1199 | int result; | |
3f85d50b | 1200 | |
2b25d981 | 1201 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1202 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1203 | if (result < 0) | |
22404274 | 1204 | return result; |
b60503ba MW |
1205 | |
1206 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1207 | if (result < 0) | |
1208 | goto release_cq; | |
1209 | ||
3193f07b | 1210 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1211 | if (result < 0) |
1212 | goto release_sq; | |
1213 | ||
22404274 | 1214 | nvme_init_queue(nvmeq, qid); |
22404274 | 1215 | return result; |
b60503ba MW |
1216 | |
1217 | release_sq: | |
1218 | adapter_delete_sq(dev, qid); | |
1219 | release_cq: | |
1220 | adapter_delete_cq(dev, qid); | |
22404274 | 1221 | return result; |
b60503ba MW |
1222 | } |
1223 | ||
a4aea562 | 1224 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1225 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1226 | .complete = nvme_complete_rq, |
a4aea562 MB |
1227 | .map_queue = blk_mq_map_queue, |
1228 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1229 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1230 | .init_request = nvme_admin_init_request, |
1231 | .timeout = nvme_timeout, | |
1232 | }; | |
1233 | ||
1234 | static struct blk_mq_ops nvme_mq_ops = { | |
1235 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1236 | .complete = nvme_complete_rq, |
a4aea562 MB |
1237 | .map_queue = blk_mq_map_queue, |
1238 | .init_hctx = nvme_init_hctx, | |
1239 | .init_request = nvme_init_request, | |
1240 | .timeout = nvme_timeout, | |
a0fa9647 | 1241 | .poll = nvme_poll, |
a4aea562 MB |
1242 | }; |
1243 | ||
ea191d2f KB |
1244 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1245 | { | |
1c63dc66 CH |
1246 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
1247 | blk_cleanup_queue(dev->ctrl.admin_q); | |
ea191d2f KB |
1248 | blk_mq_free_tag_set(&dev->admin_tagset); |
1249 | } | |
1250 | } | |
1251 | ||
a4aea562 MB |
1252 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1253 | { | |
1c63dc66 | 1254 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1255 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1256 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1257 | |
1258 | /* | |
1259 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1260 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1261 | */ | |
1262 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1263 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1264 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1265 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1266 | dev->admin_tagset.driver_data = dev; |
1267 | ||
1268 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1269 | return -ENOMEM; | |
1270 | ||
1c63dc66 CH |
1271 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1272 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1273 | blk_mq_free_tag_set(&dev->admin_tagset); |
1274 | return -ENOMEM; | |
1275 | } | |
1c63dc66 | 1276 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1277 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1278 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1279 | return -ENODEV; |
1280 | } | |
0fb59cbc | 1281 | } else |
25646264 | 1282 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1283 | |
1284 | return 0; | |
1285 | } | |
1286 | ||
8d85fce7 | 1287 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1288 | { |
ba47e386 | 1289 | int result; |
b60503ba | 1290 | u32 aqa; |
7a67cbea | 1291 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1292 | struct nvme_queue *nvmeq; |
1293 | ||
7a67cbea | 1294 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1295 | NVME_CAP_NSSRC(cap) : 0; |
1296 | ||
7a67cbea CH |
1297 | if (dev->subsystem && |
1298 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1299 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1300 | |
5fd4ce1b | 1301 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1302 | if (result < 0) |
1303 | return result; | |
b60503ba | 1304 | |
a4aea562 | 1305 | nvmeq = dev->queues[0]; |
cd638946 | 1306 | if (!nvmeq) { |
2b25d981 | 1307 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1308 | if (!nvmeq) |
1309 | return -ENOMEM; | |
cd638946 | 1310 | } |
b60503ba MW |
1311 | |
1312 | aqa = nvmeq->q_depth - 1; | |
1313 | aqa |= aqa << 16; | |
1314 | ||
7a67cbea CH |
1315 | writel(aqa, dev->bar + NVME_REG_AQA); |
1316 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1317 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1318 | |
5fd4ce1b | 1319 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1320 | if (result) |
a4aea562 MB |
1321 | goto free_nvmeq; |
1322 | ||
2b25d981 | 1323 | nvmeq->cq_vector = 0; |
3193f07b | 1324 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1325 | if (result) { |
1326 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1327 | goto free_nvmeq; |
758dd7fd | 1328 | } |
025c557a | 1329 | |
b60503ba | 1330 | return result; |
a4aea562 | 1331 | |
a4aea562 MB |
1332 | free_nvmeq: |
1333 | nvme_free_queues(dev, 0); | |
1334 | return result; | |
b60503ba MW |
1335 | } |
1336 | ||
1fa6aead MW |
1337 | static int nvme_kthread(void *data) |
1338 | { | |
d4b4ff8e | 1339 | struct nvme_dev *dev, *next; |
1fa6aead MW |
1340 | |
1341 | while (!kthread_should_stop()) { | |
564a232c | 1342 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 1343 | spin_lock(&dev_list_lock); |
d4b4ff8e | 1344 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
7a67cbea | 1345 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
dfbac8c7 | 1346 | |
846cc05f CH |
1347 | /* |
1348 | * Skip controllers currently under reset. | |
1349 | */ | |
1350 | if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work)) | |
1351 | continue; | |
dfbac8c7 KB |
1352 | |
1353 | if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || | |
1354 | csts & NVME_CSTS_CFS) { | |
846cc05f | 1355 | if (queue_work(nvme_workq, &dev->reset_work)) { |
1b3c47c1 | 1356 | dev_warn(dev->ctrl.device, |
90667892 | 1357 | "Failed status: %x, reset controller\n", |
7a67cbea | 1358 | readl(dev->bar + NVME_REG_CSTS)); |
90667892 | 1359 | } |
d4b4ff8e KB |
1360 | continue; |
1361 | } | |
1fa6aead MW |
1362 | } |
1363 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 1364 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1365 | } |
1366 | return 0; | |
1367 | } | |
1368 | ||
749941f2 | 1369 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1370 | { |
949928c1 | 1371 | unsigned i, max; |
749941f2 | 1372 | int ret = 0; |
42f61420 | 1373 | |
749941f2 CH |
1374 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1375 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1376 | ret = -ENOMEM; | |
42f61420 | 1377 | break; |
749941f2 CH |
1378 | } |
1379 | } | |
42f61420 | 1380 | |
949928c1 KB |
1381 | max = min(dev->max_qid, dev->queue_count - 1); |
1382 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 CH |
1383 | ret = nvme_create_queue(dev->queues[i], i); |
1384 | if (ret) { | |
2659e57b | 1385 | nvme_free_queues(dev, i); |
42f61420 | 1386 | break; |
2659e57b | 1387 | } |
27e8166c | 1388 | } |
749941f2 CH |
1389 | |
1390 | /* | |
1391 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1392 | * than the desired aount of queues, and even a controller without | |
1393 | * I/O queues an still be used to issue admin commands. This might | |
1394 | * be useful to upgrade a buggy firmware for example. | |
1395 | */ | |
1396 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1397 | } |
1398 | ||
8ffaadf7 JD |
1399 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1400 | { | |
1401 | u64 szu, size, offset; | |
1402 | u32 cmbloc; | |
1403 | resource_size_t bar_size; | |
1404 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1405 | void __iomem *cmb; | |
1406 | dma_addr_t dma_addr; | |
1407 | ||
1408 | if (!use_cmb_sqes) | |
1409 | return NULL; | |
1410 | ||
7a67cbea | 1411 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1412 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1413 | return NULL; | |
1414 | ||
7a67cbea | 1415 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1416 | |
1417 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1418 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1419 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1420 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1421 | ||
1422 | if (offset > bar_size) | |
1423 | return NULL; | |
1424 | ||
1425 | /* | |
1426 | * Controllers may support a CMB size larger than their BAR, | |
1427 | * for example, due to being behind a bridge. Reduce the CMB to | |
1428 | * the reported size of the BAR | |
1429 | */ | |
1430 | if (size > bar_size - offset) | |
1431 | size = bar_size - offset; | |
1432 | ||
1433 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1434 | cmb = ioremap_wc(dma_addr, size); | |
1435 | if (!cmb) | |
1436 | return NULL; | |
1437 | ||
1438 | dev->cmb_dma_addr = dma_addr; | |
1439 | dev->cmb_size = size; | |
1440 | return cmb; | |
1441 | } | |
1442 | ||
1443 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1444 | { | |
1445 | if (dev->cmb) { | |
1446 | iounmap(dev->cmb); | |
1447 | dev->cmb = NULL; | |
1448 | } | |
1449 | } | |
1450 | ||
9d713c2b KB |
1451 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1452 | { | |
b80d5ccc | 1453 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1454 | } |
1455 | ||
8d85fce7 | 1456 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1457 | { |
a4aea562 | 1458 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1459 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1460 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1461 | |
42f61420 | 1462 | nr_io_queues = num_possible_cpus(); |
9a0be7ab CH |
1463 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1464 | if (result < 0) | |
1b23484b | 1465 | return result; |
9a0be7ab CH |
1466 | |
1467 | /* | |
1468 | * Degraded controllers might return an error when setting the queue | |
1469 | * count. We still want to be able to bring them online and offer | |
1470 | * access to the admin queue, as that might be only way to fix them up. | |
1471 | */ | |
1472 | if (result > 0) { | |
1b3c47c1 SG |
1473 | dev_err(dev->ctrl.device, |
1474 | "Could not set queue count (%d)\n", result); | |
9a0be7ab CH |
1475 | nr_io_queues = 0; |
1476 | result = 0; | |
1477 | } | |
b60503ba | 1478 | |
8ffaadf7 JD |
1479 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1480 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1481 | sizeof(struct nvme_command)); | |
1482 | if (result > 0) | |
1483 | dev->q_depth = result; | |
1484 | else | |
1485 | nvme_release_cmb(dev); | |
1486 | } | |
1487 | ||
9d713c2b KB |
1488 | size = db_bar_size(dev, nr_io_queues); |
1489 | if (size > 8192) { | |
f1938f6e | 1490 | iounmap(dev->bar); |
9d713c2b KB |
1491 | do { |
1492 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1493 | if (dev->bar) | |
1494 | break; | |
1495 | if (!--nr_io_queues) | |
1496 | return -ENOMEM; | |
1497 | size = db_bar_size(dev, nr_io_queues); | |
1498 | } while (1); | |
7a67cbea | 1499 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1500 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1501 | } |
1502 | ||
9d713c2b | 1503 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1504 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1505 | |
e32efbfc JA |
1506 | /* |
1507 | * If we enable msix early due to not intx, disable it again before | |
1508 | * setting up the full range we need. | |
1509 | */ | |
1510 | if (!pdev->irq) | |
1511 | pci_disable_msix(pdev); | |
1512 | ||
be577fab | 1513 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1514 | dev->entry[i].entry = i; |
be577fab AG |
1515 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1516 | if (vecs < 0) { | |
1517 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1518 | if (vecs < 0) { | |
1519 | vecs = 1; | |
1520 | } else { | |
1521 | for (i = 0; i < vecs; i++) | |
1522 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1523 | } |
1524 | } | |
1525 | ||
063a8096 MW |
1526 | /* |
1527 | * Should investigate if there's a performance win from allocating | |
1528 | * more queues than interrupt vectors; it might allow the submission | |
1529 | * path to scale better, even if the receive path is limited by the | |
1530 | * number of interrupts. | |
1531 | */ | |
1532 | nr_io_queues = vecs; | |
42f61420 | 1533 | dev->max_qid = nr_io_queues; |
063a8096 | 1534 | |
3193f07b | 1535 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1536 | if (result) { |
1537 | adminq->cq_vector = -1; | |
22404274 | 1538 | goto free_queues; |
758dd7fd | 1539 | } |
749941f2 | 1540 | return nvme_create_io_queues(dev); |
b60503ba | 1541 | |
22404274 | 1542 | free_queues: |
a1a5ef99 | 1543 | nvme_free_queues(dev, 1); |
22404274 | 1544 | return result; |
b60503ba MW |
1545 | } |
1546 | ||
bda4e0fb | 1547 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
a5768aa8 | 1548 | { |
bda4e0fb KB |
1549 | struct nvme_queue *nvmeq; |
1550 | int i; | |
a5768aa8 | 1551 | |
bda4e0fb KB |
1552 | for (i = 0; i < dev->online_queues; i++) { |
1553 | nvmeq = dev->queues[i]; | |
a5768aa8 | 1554 | |
bda4e0fb KB |
1555 | if (!nvmeq->tags || !(*nvmeq->tags)) |
1556 | continue; | |
a5768aa8 | 1557 | |
bda4e0fb KB |
1558 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, |
1559 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
a5768aa8 | 1560 | } |
a5768aa8 KB |
1561 | } |
1562 | ||
a5768aa8 | 1563 | static void nvme_dev_scan(struct work_struct *work) |
a5768aa8 | 1564 | { |
a5768aa8 | 1565 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); |
a5768aa8 KB |
1566 | |
1567 | if (!dev->tagset.tags) | |
1568 | return; | |
5bae7f73 | 1569 | nvme_scan_namespaces(&dev->ctrl); |
bda4e0fb | 1570 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
1571 | } |
1572 | ||
db3cbfff | 1573 | static void nvme_del_queue_end(struct request *req, int error) |
a5768aa8 | 1574 | { |
db3cbfff | 1575 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1576 | |
db3cbfff KB |
1577 | blk_mq_free_request(req); |
1578 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1579 | } |
1580 | ||
db3cbfff | 1581 | static void nvme_del_cq_end(struct request *req, int error) |
a5768aa8 | 1582 | { |
db3cbfff | 1583 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1584 | |
db3cbfff KB |
1585 | if (!error) { |
1586 | unsigned long flags; | |
1587 | ||
1588 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
1589 | nvme_process_cq(nvmeq); | |
1590 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1591 | } |
db3cbfff KB |
1592 | |
1593 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1594 | } |
1595 | ||
db3cbfff | 1596 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1597 | { |
db3cbfff KB |
1598 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1599 | struct request *req; | |
1600 | struct nvme_command cmd; | |
bda4e0fb | 1601 | |
db3cbfff KB |
1602 | memset(&cmd, 0, sizeof(cmd)); |
1603 | cmd.delete_queue.opcode = opcode; | |
1604 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1605 | |
db3cbfff KB |
1606 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); |
1607 | if (IS_ERR(req)) | |
1608 | return PTR_ERR(req); | |
bda4e0fb | 1609 | |
db3cbfff KB |
1610 | req->timeout = ADMIN_TIMEOUT; |
1611 | req->end_io_data = nvmeq; | |
1612 | ||
1613 | blk_execute_rq_nowait(q, NULL, req, false, | |
1614 | opcode == nvme_admin_delete_cq ? | |
1615 | nvme_del_cq_end : nvme_del_queue_end); | |
1616 | return 0; | |
bda4e0fb KB |
1617 | } |
1618 | ||
db3cbfff | 1619 | static void nvme_disable_io_queues(struct nvme_dev *dev) |
a5768aa8 | 1620 | { |
db3cbfff KB |
1621 | int pass; |
1622 | unsigned long timeout; | |
1623 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1624 | |
db3cbfff KB |
1625 | for (pass = 0; pass < 2; pass++) { |
1626 | int sent = 0, i = dev->queue_count - 1; | |
1627 | ||
1628 | reinit_completion(&dev->ioq_wait); | |
1629 | retry: | |
1630 | timeout = ADMIN_TIMEOUT; | |
1631 | for (; i > 0; i--) { | |
1632 | struct nvme_queue *nvmeq = dev->queues[i]; | |
1633 | ||
1634 | if (!pass) | |
1635 | nvme_suspend_queue(nvmeq); | |
1636 | if (nvme_delete_queue(nvmeq, opcode)) | |
1637 | break; | |
1638 | ++sent; | |
1639 | } | |
1640 | while (sent--) { | |
1641 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1642 | if (timeout == 0) | |
1643 | return; | |
1644 | if (i) | |
1645 | goto retry; | |
1646 | } | |
1647 | opcode = nvme_admin_delete_cq; | |
1648 | } | |
a5768aa8 KB |
1649 | } |
1650 | ||
422ef0c7 MW |
1651 | /* |
1652 | * Return: error value if an error occurred setting up the queues or calling | |
1653 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1654 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1655 | * failures should be reported. | |
1656 | */ | |
8d85fce7 | 1657 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1658 | { |
5bae7f73 | 1659 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1660 | dev->tagset.ops = &nvme_mq_ops; |
1661 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1662 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1663 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1664 | dev->tagset.queue_depth = | |
a4aea562 | 1665 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1666 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1667 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1668 | dev->tagset.driver_data = dev; | |
b60503ba | 1669 | |
ffe7704d KB |
1670 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1671 | return 0; | |
5bae7f73 | 1672 | dev->ctrl.tagset = &dev->tagset; |
949928c1 KB |
1673 | } else { |
1674 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1675 | ||
1676 | /* Free previously allocated queues that are no longer usable */ | |
1677 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1678 | } |
949928c1 | 1679 | |
92f7a162 | 1680 | queue_work(nvme_workq, &dev->scan_work); |
e1e5e564 | 1681 | return 0; |
b60503ba MW |
1682 | } |
1683 | ||
0877cb0d KB |
1684 | static int nvme_dev_map(struct nvme_dev *dev) |
1685 | { | |
42f61420 | 1686 | u64 cap; |
0877cb0d | 1687 | int bars, result = -ENOMEM; |
e75ec752 | 1688 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1689 | |
1690 | if (pci_enable_device_mem(pdev)) | |
1691 | return result; | |
1692 | ||
1693 | dev->entry[0].vector = pdev->irq; | |
1694 | pci_set_master(pdev); | |
1695 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
1696 | if (!bars) |
1697 | goto disable_pci; | |
1698 | ||
0877cb0d KB |
1699 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
1700 | goto disable_pci; | |
1701 | ||
e75ec752 CH |
1702 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1703 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1704 | goto disable; |
0877cb0d | 1705 | |
0877cb0d KB |
1706 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1707 | if (!dev->bar) | |
1708 | goto disable; | |
e32efbfc | 1709 | |
7a67cbea | 1710 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 KB |
1711 | result = -ENODEV; |
1712 | goto unmap; | |
1713 | } | |
e32efbfc JA |
1714 | |
1715 | /* | |
1716 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
1717 | * MSIX vec for setup. We'll adjust this later. | |
1718 | */ | |
1719 | if (!pdev->irq) { | |
1720 | result = pci_enable_msix(pdev, dev->entry, 1); | |
1721 | if (result < 0) | |
1722 | goto unmap; | |
1723 | } | |
1724 | ||
7a67cbea CH |
1725 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1726 | ||
42f61420 KB |
1727 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1728 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1729 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1730 | |
1731 | /* | |
1732 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1733 | * some MacBook7,1 to avoid controller resets and data loss. | |
1734 | */ | |
1735 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1736 | dev->q_depth = 2; | |
1737 | dev_warn(dev->dev, "detected Apple NVMe controller, set " | |
1738 | "queue depth=%u to work around controller resets\n", | |
1739 | dev->q_depth); | |
1740 | } | |
1741 | ||
7a67cbea | 1742 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) |
8ffaadf7 | 1743 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1744 | |
a0a3408e KB |
1745 | pci_enable_pcie_error_reporting(pdev); |
1746 | pci_save_state(pdev); | |
0877cb0d KB |
1747 | return 0; |
1748 | ||
0e53d180 KB |
1749 | unmap: |
1750 | iounmap(dev->bar); | |
1751 | dev->bar = NULL; | |
0877cb0d KB |
1752 | disable: |
1753 | pci_release_regions(pdev); | |
1754 | disable_pci: | |
1755 | pci_disable_device(pdev); | |
1756 | return result; | |
1757 | } | |
1758 | ||
1759 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
1760 | { | |
e75ec752 CH |
1761 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1762 | ||
1763 | if (pdev->msi_enabled) | |
1764 | pci_disable_msi(pdev); | |
1765 | else if (pdev->msix_enabled) | |
1766 | pci_disable_msix(pdev); | |
0877cb0d KB |
1767 | |
1768 | if (dev->bar) { | |
1769 | iounmap(dev->bar); | |
1770 | dev->bar = NULL; | |
e75ec752 | 1771 | pci_release_regions(pdev); |
0877cb0d KB |
1772 | } |
1773 | ||
a0a3408e KB |
1774 | if (pci_is_enabled(pdev)) { |
1775 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1776 | pci_disable_device(pdev); |
4d115420 | 1777 | } |
4d115420 KB |
1778 | } |
1779 | ||
7385014c | 1780 | static int nvme_dev_list_add(struct nvme_dev *dev) |
4d115420 | 1781 | { |
7385014c | 1782 | bool start_thread = false; |
4d115420 | 1783 | |
7385014c CH |
1784 | spin_lock(&dev_list_lock); |
1785 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { | |
1786 | start_thread = true; | |
1787 | nvme_thread = NULL; | |
4d115420 | 1788 | } |
7385014c CH |
1789 | list_add(&dev->node, &dev_list); |
1790 | spin_unlock(&dev_list_lock); | |
4d115420 | 1791 | |
7385014c CH |
1792 | if (start_thread) { |
1793 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
1794 | wake_up_all(&nvme_kthread_wait); | |
1795 | } else | |
1796 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
4d115420 | 1797 | |
7385014c CH |
1798 | if (IS_ERR_OR_NULL(nvme_thread)) |
1799 | return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
1800 | ||
1801 | return 0; | |
4d115420 KB |
1802 | } |
1803 | ||
b9afca3e DM |
1804 | /* |
1805 | * Remove the node from the device list and check | |
1806 | * for whether or not we need to stop the nvme_thread. | |
1807 | */ | |
1808 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
1809 | { | |
1810 | struct task_struct *tmp = NULL; | |
1811 | ||
1812 | spin_lock(&dev_list_lock); | |
1813 | list_del_init(&dev->node); | |
1814 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
1815 | tmp = nvme_thread; | |
1816 | nvme_thread = NULL; | |
1817 | } | |
1818 | spin_unlock(&dev_list_lock); | |
1819 | ||
1820 | if (tmp) | |
1821 | kthread_stop(tmp); | |
1822 | } | |
1823 | ||
a5cdb68c | 1824 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1825 | { |
22404274 | 1826 | int i; |
7c1b2450 | 1827 | u32 csts = -1; |
22404274 | 1828 | |
b9afca3e | 1829 | nvme_dev_list_remove(dev); |
1fa6aead | 1830 | |
77bf25ea | 1831 | mutex_lock(&dev->shutdown_lock); |
c9d3bf88 | 1832 | if (dev->bar) { |
25646264 | 1833 | nvme_stop_queues(&dev->ctrl); |
7a67cbea | 1834 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1835 | } |
7c1b2450 | 1836 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 1837 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 1838 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 1839 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
1840 | } |
1841 | } else { | |
1842 | nvme_disable_io_queues(dev); | |
a5cdb68c | 1843 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1844 | } |
f0b50732 | 1845 | nvme_dev_unmap(dev); |
07836e65 KB |
1846 | |
1847 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1848 | nvme_clear_queue(dev->queues[i]); | |
77bf25ea | 1849 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
1850 | } |
1851 | ||
091b6092 MW |
1852 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1853 | { | |
e75ec752 | 1854 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1855 | PAGE_SIZE, PAGE_SIZE, 0); |
1856 | if (!dev->prp_page_pool) | |
1857 | return -ENOMEM; | |
1858 | ||
99802a7a | 1859 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1860 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1861 | 256, 256, 0); |
1862 | if (!dev->prp_small_pool) { | |
1863 | dma_pool_destroy(dev->prp_page_pool); | |
1864 | return -ENOMEM; | |
1865 | } | |
091b6092 MW |
1866 | return 0; |
1867 | } | |
1868 | ||
1869 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1870 | { | |
1871 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1872 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1873 | } |
1874 | ||
1673f1f0 | 1875 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1876 | { |
1673f1f0 | 1877 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1878 | |
e75ec752 | 1879 | put_device(dev->dev); |
4af0e21c KB |
1880 | if (dev->tagset.tags) |
1881 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1882 | if (dev->ctrl.admin_q) |
1883 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
1884 | kfree(dev->queues); |
1885 | kfree(dev->entry); | |
1886 | kfree(dev); | |
1887 | } | |
1888 | ||
fd634f41 | 1889 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 1890 | { |
fd634f41 | 1891 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
3cf519b5 | 1892 | int result; |
5e82e952 | 1893 | |
fd634f41 CH |
1894 | if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags))) |
1895 | goto out; | |
5e82e952 | 1896 | |
fd634f41 CH |
1897 | /* |
1898 | * If we're called to reset a live controller first shut it down before | |
1899 | * moving on. | |
1900 | */ | |
1901 | if (dev->bar) | |
a5cdb68c | 1902 | nvme_dev_disable(dev, false); |
5e82e952 | 1903 | |
fd634f41 | 1904 | set_bit(NVME_CTRL_RESETTING, &dev->flags); |
f0b50732 KB |
1905 | |
1906 | result = nvme_dev_map(dev); | |
1907 | if (result) | |
3cf519b5 | 1908 | goto out; |
f0b50732 KB |
1909 | |
1910 | result = nvme_configure_admin_queue(dev); | |
1911 | if (result) | |
1912 | goto unmap; | |
1913 | ||
a4aea562 | 1914 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1915 | result = nvme_alloc_admin_tags(dev); |
1916 | if (result) | |
1917 | goto disable; | |
b9afca3e | 1918 | |
ce4541f4 CH |
1919 | result = nvme_init_identify(&dev->ctrl); |
1920 | if (result) | |
1921 | goto free_tags; | |
1922 | ||
f0b50732 | 1923 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1924 | if (result) |
0fb59cbc | 1925 | goto free_tags; |
f0b50732 | 1926 | |
adf68f21 | 1927 | dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS; |
9396dec9 | 1928 | queue_work(nvme_workq, &dev->async_work); |
3cf519b5 | 1929 | |
7385014c CH |
1930 | result = nvme_dev_list_add(dev); |
1931 | if (result) | |
1932 | goto remove; | |
3cf519b5 | 1933 | |
2659e57b CH |
1934 | /* |
1935 | * Keep the controller around but remove all namespaces if we don't have | |
1936 | * any working I/O queue. | |
1937 | */ | |
3cf519b5 | 1938 | if (dev->online_queues < 2) { |
1b3c47c1 | 1939 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
5bae7f73 | 1940 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1941 | } else { |
25646264 | 1942 | nvme_start_queues(&dev->ctrl); |
3cf519b5 CH |
1943 | nvme_dev_add(dev); |
1944 | } | |
1945 | ||
fd634f41 | 1946 | clear_bit(NVME_CTRL_RESETTING, &dev->flags); |
3cf519b5 | 1947 | return; |
f0b50732 | 1948 | |
7385014c CH |
1949 | remove: |
1950 | nvme_dev_list_remove(dev); | |
0fb59cbc KB |
1951 | free_tags: |
1952 | nvme_dev_remove_admin(dev); | |
1c63dc66 CH |
1953 | blk_put_queue(dev->ctrl.admin_q); |
1954 | dev->ctrl.admin_q = NULL; | |
4af0e21c | 1955 | dev->queues[0]->tags = NULL; |
f0b50732 | 1956 | disable: |
a5cdb68c | 1957 | nvme_disable_admin_queue(dev, false); |
f0b50732 KB |
1958 | unmap: |
1959 | nvme_dev_unmap(dev); | |
3cf519b5 | 1960 | out: |
5c8809e6 | 1961 | nvme_remove_dead_ctrl(dev); |
f0b50732 KB |
1962 | } |
1963 | ||
5c8809e6 | 1964 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1965 | { |
5c8809e6 | 1966 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1967 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
1968 | |
1969 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 1970 | pci_stop_and_remove_bus_device_locked(pdev); |
1673f1f0 | 1971 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
1972 | } |
1973 | ||
5c8809e6 | 1974 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev) |
de3eff2b | 1975 | { |
1b3c47c1 | 1976 | dev_warn(dev->ctrl.device, "Removing after probe failure\n"); |
1673f1f0 | 1977 | kref_get(&dev->ctrl.kref); |
5c8809e6 | 1978 | if (!schedule_work(&dev->remove_work)) |
1673f1f0 | 1979 | nvme_put_ctrl(&dev->ctrl); |
de3eff2b KB |
1980 | } |
1981 | ||
4cc06521 | 1982 | static int nvme_reset(struct nvme_dev *dev) |
9a6b9458 | 1983 | { |
1c63dc66 | 1984 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 | 1985 | return -ENODEV; |
ffe7704d | 1986 | |
846cc05f CH |
1987 | if (!queue_work(nvme_workq, &dev->reset_work)) |
1988 | return -EBUSY; | |
ffe7704d | 1989 | |
846cc05f | 1990 | flush_work(&dev->reset_work); |
846cc05f | 1991 | return 0; |
9a6b9458 KB |
1992 | } |
1993 | ||
1c63dc66 | 1994 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 1995 | { |
1c63dc66 | 1996 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 1997 | return 0; |
9ca97374 TH |
1998 | } |
1999 | ||
5fd4ce1b | 2000 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2001 | { |
5fd4ce1b CH |
2002 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2003 | return 0; | |
2004 | } | |
4cc06521 | 2005 | |
7fd8930f CH |
2006 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2007 | { | |
2008 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2009 | return 0; | |
4cc06521 KB |
2010 | } |
2011 | ||
5bae7f73 | 2012 | static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) |
4cc06521 | 2013 | { |
5bae7f73 | 2014 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
4cc06521 | 2015 | |
5bae7f73 CH |
2016 | return !dev->bar || dev->online_queues < 2; |
2017 | } | |
4cc06521 | 2018 | |
f3ca80fc CH |
2019 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
2020 | { | |
2021 | return nvme_reset(to_nvme_dev(ctrl)); | |
4cc06521 | 2022 | } |
f3ca80fc | 2023 | |
1c63dc66 | 2024 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
e439bb12 | 2025 | .module = THIS_MODULE, |
1c63dc66 | 2026 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 2027 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2028 | .reg_read64 = nvme_pci_reg_read64, |
5bae7f73 | 2029 | .io_incapable = nvme_pci_io_incapable, |
f3ca80fc | 2030 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 2031 | .free_ctrl = nvme_pci_free_ctrl, |
1c63dc66 | 2032 | }; |
4cc06521 | 2033 | |
8d85fce7 | 2034 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2035 | { |
a4aea562 | 2036 | int node, result = -ENOMEM; |
b60503ba MW |
2037 | struct nvme_dev *dev; |
2038 | ||
a4aea562 MB |
2039 | node = dev_to_node(&pdev->dev); |
2040 | if (node == NUMA_NO_NODE) | |
2041 | set_dev_node(&pdev->dev, 0); | |
2042 | ||
2043 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2044 | if (!dev) |
2045 | return -ENOMEM; | |
a4aea562 MB |
2046 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2047 | GFP_KERNEL, node); | |
b60503ba MW |
2048 | if (!dev->entry) |
2049 | goto free; | |
a4aea562 MB |
2050 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2051 | GFP_KERNEL, node); | |
b60503ba MW |
2052 | if (!dev->queues) |
2053 | goto free; | |
2054 | ||
e75ec752 | 2055 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2056 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2057 | |
f3ca80fc CH |
2058 | INIT_LIST_HEAD(&dev->node); |
2059 | INIT_WORK(&dev->scan_work, nvme_dev_scan); | |
f3ca80fc | 2060 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 2061 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
9396dec9 | 2062 | INIT_WORK(&dev->async_work, nvme_async_event_work); |
77bf25ea | 2063 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2064 | init_completion(&dev->ioq_wait); |
b60503ba | 2065 | |
091b6092 MW |
2066 | result = nvme_setup_prp_pools(dev); |
2067 | if (result) | |
a96d4f5c | 2068 | goto put_pci; |
4cc06521 | 2069 | |
f3ca80fc CH |
2070 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2071 | id->driver_data); | |
4cc06521 | 2072 | if (result) |
2e1d8448 | 2073 | goto release_pools; |
740216fc | 2074 | |
1b3c47c1 SG |
2075 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2076 | ||
92f7a162 | 2077 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
2078 | return 0; |
2079 | ||
0877cb0d | 2080 | release_pools: |
091b6092 | 2081 | nvme_release_prp_pools(dev); |
a96d4f5c | 2082 | put_pci: |
e75ec752 | 2083 | put_device(dev->dev); |
b60503ba MW |
2084 | free: |
2085 | kfree(dev->queues); | |
2086 | kfree(dev->entry); | |
2087 | kfree(dev); | |
2088 | return result; | |
2089 | } | |
2090 | ||
f0d54a54 KB |
2091 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2092 | { | |
a6739479 | 2093 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2094 | |
a6739479 | 2095 | if (prepare) |
a5cdb68c | 2096 | nvme_dev_disable(dev, false); |
a6739479 | 2097 | else |
92f7a162 | 2098 | queue_work(nvme_workq, &dev->reset_work); |
f0d54a54 KB |
2099 | } |
2100 | ||
09ece142 KB |
2101 | static void nvme_shutdown(struct pci_dev *pdev) |
2102 | { | |
2103 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2104 | nvme_dev_disable(dev, true); |
09ece142 KB |
2105 | } |
2106 | ||
8d85fce7 | 2107 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2108 | { |
2109 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
2110 | |
2111 | spin_lock(&dev_list_lock); | |
2112 | list_del_init(&dev->node); | |
2113 | spin_unlock(&dev_list_lock); | |
2114 | ||
2115 | pci_set_drvdata(pdev, NULL); | |
9396dec9 | 2116 | flush_work(&dev->async_work); |
9a6b9458 | 2117 | flush_work(&dev->reset_work); |
a5768aa8 | 2118 | flush_work(&dev->scan_work); |
5bae7f73 | 2119 | nvme_remove_namespaces(&dev->ctrl); |
53029b04 | 2120 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 2121 | nvme_dev_disable(dev, true); |
a4aea562 | 2122 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2123 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2124 | nvme_release_cmb(dev); |
9a6b9458 | 2125 | nvme_release_prp_pools(dev); |
1673f1f0 | 2126 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2127 | } |
2128 | ||
671a6018 | 2129 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2130 | static int nvme_suspend(struct device *dev) |
2131 | { | |
2132 | struct pci_dev *pdev = to_pci_dev(dev); | |
2133 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2134 | ||
a5cdb68c | 2135 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2136 | return 0; |
2137 | } | |
2138 | ||
2139 | static int nvme_resume(struct device *dev) | |
2140 | { | |
2141 | struct pci_dev *pdev = to_pci_dev(dev); | |
2142 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2143 | |
92f7a162 | 2144 | queue_work(nvme_workq, &ndev->reset_work); |
9a6b9458 | 2145 | return 0; |
cd638946 | 2146 | } |
671a6018 | 2147 | #endif |
cd638946 KB |
2148 | |
2149 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2150 | |
a0a3408e KB |
2151 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2152 | pci_channel_state_t state) | |
2153 | { | |
2154 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2155 | ||
2156 | /* | |
2157 | * A frozen channel requires a reset. When detected, this method will | |
2158 | * shutdown the controller to quiesce. The controller will be restarted | |
2159 | * after the slot reset through driver's slot_reset callback. | |
2160 | */ | |
1b3c47c1 | 2161 | dev_warn(dev->ctrl.device, "error detected: state:%d\n", state); |
a0a3408e KB |
2162 | switch (state) { |
2163 | case pci_channel_io_normal: | |
2164 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2165 | case pci_channel_io_frozen: | |
a5cdb68c | 2166 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2167 | return PCI_ERS_RESULT_NEED_RESET; |
2168 | case pci_channel_io_perm_failure: | |
2169 | return PCI_ERS_RESULT_DISCONNECT; | |
2170 | } | |
2171 | return PCI_ERS_RESULT_NEED_RESET; | |
2172 | } | |
2173 | ||
2174 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2175 | { | |
2176 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2177 | ||
1b3c47c1 | 2178 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e KB |
2179 | pci_restore_state(pdev); |
2180 | queue_work(nvme_workq, &dev->reset_work); | |
2181 | return PCI_ERS_RESULT_RECOVERED; | |
2182 | } | |
2183 | ||
2184 | static void nvme_error_resume(struct pci_dev *pdev) | |
2185 | { | |
2186 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2187 | } | |
2188 | ||
1d352035 | 2189 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2190 | .error_detected = nvme_error_detected, |
b60503ba MW |
2191 | .slot_reset = nvme_slot_reset, |
2192 | .resume = nvme_error_resume, | |
f0d54a54 | 2193 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2194 | }; |
2195 | ||
2196 | /* Move to pci_ids.h later */ | |
2197 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2198 | ||
6eb0d698 | 2199 | static const struct pci_device_id nvme_id_table[] = { |
106198ed CH |
2200 | { PCI_VDEVICE(INTEL, 0x0953), |
2201 | .driver_data = NVME_QUIRK_STRIPE_SIZE, }, | |
540c801c KB |
2202 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2203 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
b60503ba | 2204 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2205 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2206 | { 0, } |
2207 | }; | |
2208 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2209 | ||
2210 | static struct pci_driver nvme_driver = { | |
2211 | .name = "nvme", | |
2212 | .id_table = nvme_id_table, | |
2213 | .probe = nvme_probe, | |
8d85fce7 | 2214 | .remove = nvme_remove, |
09ece142 | 2215 | .shutdown = nvme_shutdown, |
cd638946 KB |
2216 | .driver = { |
2217 | .pm = &nvme_dev_pm_ops, | |
2218 | }, | |
b60503ba MW |
2219 | .err_handler = &nvme_err_handler, |
2220 | }; | |
2221 | ||
2222 | static int __init nvme_init(void) | |
2223 | { | |
0ac13140 | 2224 | int result; |
1fa6aead | 2225 | |
b9afca3e | 2226 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 2227 | |
92f7a162 | 2228 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2229 | if (!nvme_workq) |
b9afca3e | 2230 | return -ENOMEM; |
9a6b9458 | 2231 | |
f3db22fe KB |
2232 | result = pci_register_driver(&nvme_driver); |
2233 | if (result) | |
576d55d6 | 2234 | destroy_workqueue(nvme_workq); |
b60503ba MW |
2235 | return result; |
2236 | } | |
2237 | ||
2238 | static void __exit nvme_exit(void) | |
2239 | { | |
2240 | pci_unregister_driver(&nvme_driver); | |
9a6b9458 | 2241 | destroy_workqueue(nvme_workq); |
b9afca3e | 2242 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 2243 | _nvme_check_size(); |
b60503ba MW |
2244 | } |
2245 | ||
2246 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2247 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2248 | MODULE_VERSION("1.0"); |
b60503ba MW |
2249 | module_init(nvme_init); |
2250 | module_exit(nvme_exit); |