#include <Library/UefiBootServicesTableLib.h>\r
#include <Protocol/Cpu.h>\r
\r
-STATIC EFI_CPU_ARCH_PROTOCOL *mCpu;\r
+STATIC EFI_CPU_ARCH_PROTOCOL *mCpu;\r
\r
EFI_STATUS\r
EFIAPI\r
ArmCrashDumpDxeInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);\r
- ASSERT_EFI_ERROR(Status);\r
+ ASSERT_EFI_ERROR (Status);\r
\r
- return mCpu->RegisterInterruptHandler (mCpu,\r
- EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS,\r
- &DefaultExceptionHandler);\r
+ return mCpu->RegisterInterruptHandler (\r
+ mCpu,\r
+ EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS,\r
+ &DefaultExceptionHandler\r
+ );\r
}\r
VOID\r
EFIAPI\r
IrqInterruptHandler (\r
- IN EFI_EXCEPTION_TYPE InterruptType,\r
- IN EFI_SYSTEM_CONTEXT SystemContext\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_SYSTEM_CONTEXT SystemContext\r
);\r
\r
VOID\r
EFI_HANDLE gHardwareInterruptHandle = NULL;\r
\r
// Notifications\r
-EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
\r
// Maximum Number of Interrupts\r
-UINTN mGicNumInterrupts = 0;\r
+UINTN mGicNumInterrupts = 0;\r
\r
HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;\r
\r
-\r
/**\r
Calculate GICD_ICFGRn base address and corresponding bit\r
field Int_config[1] of the GIC distributor register.\r
**/\r
EFI_STATUS\r
GicGetDistributorIcfgBaseAndBit (\r
- IN HARDWARE_INTERRUPT_SOURCE Source,\r
- OUT UINTN *RegAddress,\r
- OUT UINTN *Config1Bit\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ OUT UINTN *RegAddress,\r
+ OUT UINTN *Config1Bit\r
)\r
{\r
- UINTN RegIndex;\r
- UINTN Field;\r
+ UINTN RegIndex;\r
+ UINTN Field;\r
\r
if (Source >= mGicNumInterrupts) {\r
- ASSERT(Source < mGicNumInterrupts);\r
+ ASSERT (Source < mGicNumInterrupts);\r
return EFI_UNSUPPORTED;\r
}\r
\r
- RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE; // NOTE: truncation is significant\r
- Field = Source % ARM_GIC_ICDICFR_F_STRIDE;\r
+ RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE; // NOTE: truncation is significant\r
+ Field = Source % ARM_GIC_ICDICFR_F_STRIDE;\r
*RegAddress = PcdGet64 (PcdGicDistributorBase)\r
+ ARM_GIC_ICDICFR\r
+ (ARM_GIC_ICDICFR_BYTES * RegIndex);\r
return EFI_SUCCESS;\r
}\r
\r
-\r
-\r
/**\r
Register Handler for the specified interrupt source.\r
\r
EFI_STATUS\r
EFIAPI\r
RegisterInterruptSource (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source,\r
- IN HARDWARE_INTERRUPT_HANDLER Handler\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ IN HARDWARE_INTERRUPT_HANDLER Handler\r
)\r
{\r
if (Source >= mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
\r
gRegisteredInterruptHandlers[Source] = Handler;\r
\r
// If the interrupt handler is unregistered then disable the interrupt\r
- if (NULL == Handler){\r
+ if (NULL == Handler) {\r
return This->DisableInterruptSource (This, Source);\r
} else {\r
return This->EnableInterruptSource (This, Source);\r
}\r
}\r
\r
-STATIC VOID *mCpuArchProtocolNotifyEventRegistration;\r
+STATIC VOID *mCpuArchProtocolNotifyEventRegistration;\r
\r
STATIC\r
VOID\r
EFIAPI\r
CpuArchEventProtocolNotify (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
)\r
{\r
- EFI_CPU_ARCH_PROTOCOL *Cpu;\r
- EFI_STATUS Status;\r
+ EFI_CPU_ARCH_PROTOCOL *Cpu;\r
+ EFI_STATUS Status;\r
\r
// Get the CPU protocol that this driver requires.\r
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
// Unregister the default exception handler.\r
Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",\r
- __FUNCTION__, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: Cpu->RegisterInterruptHandler() - %r\n",\r
+ __FUNCTION__,\r
+ Status\r
+ ));\r
return;\r
}\r
\r
// Register to receive interrupts\r
- Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ,\r
- Context);\r
+ Status = Cpu->RegisterInterruptHandler (\r
+ Cpu,\r
+ ARM_ARCH_EXCEPTION_IRQ,\r
+ Context\r
+ );\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",\r
- __FUNCTION__, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: Cpu->RegisterInterruptHandler() - %r\n",\r
+ __FUNCTION__,\r
+ Status\r
+ ));\r
}\r
\r
gBS->CloseEvent (Event);\r
InstallAndRegisterInterruptService (\r
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,\r
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol,\r
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,\r
- IN EFI_EVENT_NOTIFY ExitBootServicesEvent\r
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,\r
+ IN EFI_EVENT_NOTIFY ExitBootServicesEvent\r
)\r
{\r
- EFI_STATUS Status;\r
- CONST UINTN RihArraySize =\r
- (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);\r
+ EFI_STATUS Status;\r
+ CONST UINTN RihArraySize =\r
+ (sizeof (HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);\r
\r
// Initialize the array for the Interrupt Handlers\r
gRegisteredInterruptHandlers = AllocateZeroPool (RihArraySize);\r
TPL_CALLBACK,\r
CpuArchEventProtocolNotify,\r
InterruptHandler,\r
- &mCpuArchProtocolNotifyEventRegistration);\r
+ &mCpuArchProtocolNotifyEventRegistration\r
+ );\r
\r
// Register for an ExitBootServicesEvent\r
Status = gBS->CreateEvent (\r
**/\r
EFI_STATUS\r
InterruptDxeInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
- ARM_GIC_ARCH_REVISION Revision;\r
+ EFI_STATUS Status;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
\r
#include <Protocol/HardwareInterrupt.h>\r
#include <Protocol/HardwareInterrupt2.h>\r
\r
-extern UINTN mGicNumInterrupts;\r
+extern UINTN mGicNumInterrupts;\r
extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers;\r
\r
// Common API\r
InstallAndRegisterInterruptService (\r
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,\r
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol,\r
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,\r
- IN EFI_EVENT_NOTIFY ExitBootServicesEvent\r
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,\r
+ IN EFI_EVENT_NOTIFY ExitBootServicesEvent\r
);\r
\r
EFI_STATUS\r
EFIAPI\r
RegisterInterruptSource (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source,\r
- IN HARDWARE_INTERRUPT_HANDLER Handler\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ IN HARDWARE_INTERRUPT_HANDLER Handler\r
);\r
\r
// GicV2 API\r
EFI_STATUS\r
GicV2DxeInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
// GicV3 API\r
EFI_STATUS\r
GicV3DxeInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
-\r
// Shared code\r
\r
/**\r
**/\r
EFI_STATUS\r
GicGetDistributorIcfgBaseAndBit (\r
- IN HARDWARE_INTERRUPT_SOURCE Source,\r
- OUT UINTN *RegAddress,\r
- OUT UINTN *Config1Bit\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ OUT UINTN *RegAddress,\r
+ OUT UINTN *Config1Bit\r
);\r
\r
#endif // ARM_GIC_DXE_H_\r
+ ARM_GICR_SGI_VLPI_FRAME_SIZE \\r
+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)\r
\r
-#define ISENABLER_ADDRESS(base,offset) ((base) + \\r
+#define ISENABLER_ADDRESS(base, offset) ((base) +\\r
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset))\r
\r
-#define ICENABLER_ADDRESS(base,offset) ((base) + \\r
+#define ICENABLER_ADDRESS(base, offset) ((base) +\\r
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))\r
\r
-#define IPRIORITY_ADDRESS(base,offset) ((base) + \\r
+#define IPRIORITY_ADDRESS(base, offset) ((base) +\\r
ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))\r
\r
/**\r
STATIC\r
UINTN\r
GicGetCpuRedistributorBase (\r
- IN UINTN GicRedistributorBase,\r
- IN ARM_GIC_ARCH_REVISION Revision\r
+ IN UINTN GicRedistributorBase,\r
+ IN ARM_GIC_ARCH_REVISION Revision\r
)\r
{\r
- UINTN MpId;\r
- UINTN CpuAffinity;\r
- UINTN Affinity;\r
- UINTN GicCpuRedistributorBase;\r
- UINT64 TypeRegister;\r
+ UINTN MpId;\r
+ UINTN CpuAffinity;\r
+ UINTN Affinity;\r
+ UINTN GicCpuRedistributorBase;\r
+ UINT64 TypeRegister;\r
\r
MpId = ArmReadMpidr ();\r
// Define CPU affinity as:\r
\r
do {\r
TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER);\r
- Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);\r
+ Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);\r
if (Affinity == CpuAffinity) {\r
return GicCpuRedistributorBase;\r
}\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
)\r
{\r
// Read the GIC Identification Register\r
UINTN\r
EFIAPI\r
ArmGicGetMaxNumInterrupts (\r
- IN INTN GicDistributorBase\r
+ IN INTN GicDistributorBase\r
)\r
{\r
- UINTN ItLines;\r
+ UINTN ItLines;\r
\r
ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F;\r
\r
VOID\r
EFIAPI\r
ArmGicSendSgiTo (\r
- IN INTN GicDistributorBase,\r
- IN INTN TargetListFilter,\r
- IN INTN CPUTargetList,\r
- IN INTN SgiId\r
+ IN INTN GicDistributorBase,\r
+ IN INTN TargetListFilter,\r
+ IN INTN CPUTargetList,\r
+ IN INTN SgiId\r
)\r
{\r
MmioWrite32 (\r
UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
- IN UINTN GicInterruptInterfaceBase,\r
- OUT UINTN *InterruptId\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ OUT UINTN *InterruptId\r
)\r
{\r
- UINTN Value;\r
- ARM_GIC_ARCH_REVISION Revision;\r
+ UINTN Value;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
VOID\r
EFIAPI\r
ArmGicEndOfInterrupt (\r
- IN UINTN GicInterruptInterfaceBase,\r
- IN UINTN Source\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ IN UINTN Source\r
)\r
{\r
- ARM_GIC_ARCH_REVISION Revision;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
VOID\r
EFIAPI\r
ArmGicSetInterruptPriority (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicRedistributorBase,\r
- IN UINTN Source,\r
- IN UINTN Priority\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source,\r
+ IN UINTN Priority\r
)\r
{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- ARM_GIC_ARCH_REVISION Revision;\r
- UINTN GicCpuRedistributorBase;\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
+ UINTN GicCpuRedistributorBase;\r
\r
// Calculate register offset and bit position\r
RegOffset = Source / 4;\r
- RegShift = (Source % 4) * 8;\r
+ RegShift = (Source % 4) * 8;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
- SourceIsSpi (Source)) {\r
+ SourceIsSpi (Source))\r
+ {\r
MmioAndThenOr32 (\r
GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),\r
~(0xff << RegShift),\r
VOID\r
EFIAPI\r
ArmGicEnableInterrupt (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicRedistributorBase,\r
- IN UINTN Source\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source\r
)\r
{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- ARM_GIC_ARCH_REVISION Revision;\r
- UINTN GicCpuRedistributorBase;\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
+ UINTN GicCpuRedistributorBase;\r
\r
// Calculate enable register offset and bit position\r
RegOffset = Source / 32;\r
- RegShift = Source % 32;\r
+ RegShift = Source % 32;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
- SourceIsSpi (Source)) {\r
+ SourceIsSpi (Source))\r
+ {\r
// Write set-enable register\r
MmioWrite32 (\r
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),\r
\r
// Write set-enable register\r
MmioWrite32 (\r
- ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),\r
+ ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),\r
1 << RegShift\r
);\r
}\r
VOID\r
EFIAPI\r
ArmGicDisableInterrupt (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicRedistributorBase,\r
- IN UINTN Source\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source\r
)\r
{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- ARM_GIC_ARCH_REVISION Revision;\r
- UINTN GicCpuRedistributorBase;\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
+ UINTN GicCpuRedistributorBase;\r
\r
// Calculate enable register offset and bit position\r
RegOffset = Source / 32;\r
- RegShift = Source % 32;\r
+ RegShift = Source % 32;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
- SourceIsSpi (Source)) {\r
+ SourceIsSpi (Source))\r
+ {\r
// Write clear-enable register\r
MmioWrite32 (\r
GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),\r
);\r
} else {\r
GicCpuRedistributorBase = GicGetCpuRedistributorBase (\r
- GicRedistributorBase,\r
- Revision\r
- );\r
+ GicRedistributorBase,\r
+ Revision\r
+ );\r
if (GicCpuRedistributorBase == 0) {\r
return;\r
}\r
\r
// Write clear-enable register\r
MmioWrite32 (\r
- ICENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),\r
+ ICENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),\r
1 << RegShift\r
);\r
}\r
BOOLEAN\r
EFIAPI\r
ArmGicIsInterruptEnabled (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicRedistributorBase,\r
- IN UINTN Source\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source\r
)\r
{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- ARM_GIC_ARCH_REVISION Revision;\r
- UINTN GicCpuRedistributorBase;\r
- UINT32 Interrupts;\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
+ UINTN GicCpuRedistributorBase;\r
+ UINT32 Interrupts;\r
\r
// Calculate enable register offset and bit position\r
RegOffset = Source / 32;\r
- RegShift = Source % 32;\r
+ RegShift = Source % 32;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||\r
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||\r
- SourceIsSpi (Source)) {\r
+ SourceIsSpi (Source))\r
+ {\r
Interrupts = ((MmioRead32 (\r
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)\r
)\r
- & (1 << RegShift)) != 0);\r
+ & (1 << RegShift)) != 0);\r
} else {\r
GicCpuRedistributorBase = GicGetCpuRedistributorBase (\r
GicRedistributorBase,\r
\r
// Read set-enable register\r
Interrupts = MmioRead32 (\r
- ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset)\r
+ ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset)\r
);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicDisableDistributor (\r
- IN INTN GicDistributorBase\r
+ IN INTN GicDistributorBase\r
)\r
{\r
// Disable Gic Distributor\r
VOID\r
EFIAPI\r
ArmGicEnableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
)\r
{\r
- ARM_GIC_ARCH_REVISION Revision;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
VOID\r
EFIAPI\r
ArmGicDisableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
)\r
{\r
- ARM_GIC_ARCH_REVISION Revision;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
\r
Revision = ArmGicGetSupportedArchRevision ();\r
if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
VOID\r
EFIAPI\r
ArmGicEnableDistributor (\r
- IN INTN GicDistributorBase\r
+ IN INTN GicDistributorBase\r
)\r
{\r
- ARM_GIC_ARCH_REVISION Revision;\r
+ ARM_GIC_ARCH_REVISION Revision;\r
\r
/*\r
* Enable GIC distributor in Non-Secure world.\r
\r
#define ARM_GIC_DEFAULT_PRIORITY 0x80\r
\r
-extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;\r
-extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;\r
+extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;\r
+extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;\r
\r
-STATIC UINT32 mGicInterruptInterfaceBase;\r
-STATIC UINT32 mGicDistributorBase;\r
+STATIC UINT32 mGicInterruptInterfaceBase;\r
+STATIC UINT32 mGicDistributorBase;\r
\r
/**\r
Enable interrupt source Source.\r
EFI_STATUS\r
EFIAPI\r
GicV2EnableInterruptSource (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
{\r
if (Source >= mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
GicV2DisableInterruptSource (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
{\r
if (Source >= mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
GicV2GetInterruptSourceState (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source,\r
- IN BOOLEAN *InterruptState\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ IN BOOLEAN *InterruptState\r
)\r
{\r
if (Source >= mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
GicV2EndOfInterrupt (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
{\r
if (Source >= mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
\r
VOID\r
EFIAPI\r
GicV2IrqInterruptHandler (\r
- IN EFI_EXCEPTION_TYPE InterruptType,\r
- IN EFI_SYSTEM_CONTEXT SystemContext\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_SYSTEM_CONTEXT SystemContext\r
)\r
{\r
UINT32 GicInterrupt;\r
}\r
\r
// The protocol instance produced by this driver\r
-EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {\r
+EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {\r
RegisterInterruptSource,\r
GicV2EnableInterruptSource,\r
GicV2DisableInterruptSource,\r
EFIAPI\r
GicV2GetTriggerType (\r
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType\r
)\r
{\r
- UINTN RegAddress;\r
- UINTN Config1Bit;\r
- EFI_STATUS Status;\r
+ UINTN RegAddress;\r
+ UINTN Config1Bit;\r
+ EFI_STATUS Status;\r
\r
Status = GicGetDistributorIcfgBaseAndBit (\r
- Source,\r
- &RegAddress,\r
- &Config1Bit\r
- );\r
+ Source,\r
+ &RegAddress,\r
+ &Config1Bit\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {\r
- *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;\r
+ *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;\r
} else {\r
- *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;\r
+ *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;\r
}\r
\r
return EFI_SUCCESS;\r
IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType\r
)\r
{\r
- UINTN RegAddress;\r
- UINTN Config1Bit;\r
- UINT32 Value;\r
- EFI_STATUS Status;\r
- BOOLEAN SourceEnabled;\r
-\r
- if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)\r
- && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {\r
- DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \\r
- TriggerType));\r
- ASSERT (FALSE);\r
- return EFI_UNSUPPORTED;\r
+ UINTN RegAddress;\r
+ UINTN Config1Bit;\r
+ UINT32 Value;\r
+ EFI_STATUS Status;\r
+ BOOLEAN SourceEnabled;\r
+\r
+ if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)\r
+ && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH))\r
+ {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "Invalid interrupt trigger type: %d\n", \\r
+ TriggerType\r
+ ));\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
}\r
\r
Status = GicGetDistributorIcfgBaseAndBit (\r
}\r
\r
Status = GicV2GetInterruptSourceState (\r
- (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,\r
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,\r
Source,\r
&SourceEnabled\r
);\r
// otherwise GIC behavior is UNPREDICTABLE.\r
if (SourceEnabled) {\r
GicV2DisableInterruptSource (\r
- (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,\r
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,\r
Source\r
);\r
}\r
// Restore interrupt state\r
if (SourceEnabled) {\r
GicV2EnableInterruptSource (\r
- (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,\r
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,\r
Source\r
);\r
}\r
return EFI_SUCCESS;\r
}\r
\r
-EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {\r
+EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {\r
(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,\r
(HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource,\r
(HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource,\r
IN VOID *Context\r
)\r
{\r
- UINTN Index;\r
- UINT32 GicInterrupt;\r
+ UINTN Index;\r
+ UINT32 GicInterrupt;\r
\r
// Disable all the interrupts\r
for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
**/\r
EFI_STATUS\r
GicV2DxeInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- UINT32 CpuTarget;\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ UINT32 CpuTarget;\r
\r
// Make sure the Interrupt Controller Protocol is not already installed in\r
// the system.\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
\r
mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase);\r
- mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);\r
- mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);\r
+ mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);\r
+ mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);\r
\r
for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);\r
\r
// Set Priority\r
RegOffset = Index / 4;\r
- RegShift = (Index % 4) * 8;\r
+ RegShift = (Index % 4) * 8;\r
MmioAndThenOr32 (\r
mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),\r
~(0xff << RegShift),\r
UINTN\r
EFIAPI\r
ArmGicV2AcknowledgeInterrupt (\r
- IN UINTN GicInterruptInterfaceBase\r
+ IN UINTN GicInterruptInterfaceBase\r
)\r
{\r
// Read the Interrupt Acknowledge Register\r
VOID\r
EFIAPI\r
ArmGicV2EndOfInterrupt (\r
- IN UINTN GicInterruptInterfaceBase,\r
- IN UINTN Source\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ IN UINTN Source\r
)\r
{\r
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);\r
#include <Library/IoLib.h>\r
#include <Library/ArmGicLib.h>\r
\r
-\r
VOID\r
EFIAPI\r
ArmGicV2EnableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
)\r
{\r
/*\r
VOID\r
EFIAPI\r
ArmGicV2DisableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
)\r
{\r
// Disable Gic Interface\r
\r
#define ARM_GIC_DEFAULT_PRIORITY 0x80\r
\r
-extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;\r
-extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;\r
+extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;\r
+extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;\r
\r
-STATIC UINTN mGicDistributorBase;\r
-STATIC UINTN mGicRedistributorsBase;\r
+STATIC UINTN mGicDistributorBase;\r
+STATIC UINTN mGicRedistributorsBase;\r
\r
/**\r
Enable interrupt source Source.\r
EFI_STATUS\r
EFIAPI\r
GicV3EnableInterruptSource (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
{\r
if (Source >= mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
GicV3DisableInterruptSource (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
{\r
if (Source >= mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
GicV3GetInterruptSourceState (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source,\r
- IN BOOLEAN *InterruptState\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ IN BOOLEAN *InterruptState\r
)\r
{\r
if (Source >= mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
GicV3EndOfInterrupt (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
{\r
if (Source >= mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
\r
VOID\r
EFIAPI\r
GicV3IrqInterruptHandler (\r
- IN EFI_EXCEPTION_TYPE InterruptType,\r
- IN EFI_SYSTEM_CONTEXT SystemContext\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_SYSTEM_CONTEXT SystemContext\r
)\r
{\r
UINT32 GicInterrupt;\r
}\r
\r
// The protocol instance produced by this driver\r
-EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {\r
+EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {\r
RegisterInterruptSource,\r
GicV3EnableInterruptSource,\r
GicV3DisableInterruptSource,\r
OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType\r
)\r
{\r
- UINTN RegAddress;\r
- UINTN Config1Bit;\r
- EFI_STATUS Status;\r
+ UINTN RegAddress;\r
+ UINTN Config1Bit;\r
+ EFI_STATUS Status;\r
\r
Status = GicGetDistributorIcfgBaseAndBit (\r
Source,\r
}\r
\r
if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {\r
- *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;\r
+ *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;\r
} else {\r
- *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;\r
+ *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;\r
}\r
\r
return EFI_SUCCESS;\r
IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType\r
)\r
{\r
- UINTN RegAddress;\r
- UINTN Config1Bit;\r
- UINT32 Value;\r
- EFI_STATUS Status;\r
- BOOLEAN SourceEnabled;\r
-\r
- if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)\r
- && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {\r
- DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \\r
- TriggerType));\r
- ASSERT (FALSE);\r
- return EFI_UNSUPPORTED;\r
+ UINTN RegAddress;\r
+ UINTN Config1Bit;\r
+ UINT32 Value;\r
+ EFI_STATUS Status;\r
+ BOOLEAN SourceEnabled;\r
+\r
+ if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)\r
+ && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH))\r
+ {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "Invalid interrupt trigger type: %d\n", \\r
+ TriggerType\r
+ ));\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
}\r
\r
Status = GicGetDistributorIcfgBaseAndBit (\r
}\r
\r
Status = GicV3GetInterruptSourceState (\r
- (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,\r
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,\r
Source,\r
&SourceEnabled\r
);\r
// otherwise GIC behavior is UNPREDICTABLE.\r
if (SourceEnabled) {\r
GicV3DisableInterruptSource (\r
- (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,\r
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,\r
Source\r
);\r
}\r
// Restore interrupt state\r
if (SourceEnabled) {\r
GicV3EnableInterruptSource (\r
- (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,\r
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,\r
Source\r
);\r
}\r
return EFI_SUCCESS;\r
}\r
\r
-EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {\r
+EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {\r
(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,\r
(HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource,\r
(HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource,\r
IN VOID *Context\r
)\r
{\r
- UINTN Index;\r
+ UINTN Index;\r
\r
// Acknowledge all pending interrupts\r
for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
**/\r
EFI_STATUS\r
GicV3DxeInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
- UINT64 CpuTarget;\r
- UINT64 MpId;\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ UINT64 CpuTarget;\r
+ UINT64 MpId;\r
\r
// Make sure the Interrupt Controller Protocol is not already installed in\r
// the system.\r
}\r
}\r
} else {\r
- MpId = ArmReadMpidr ();\r
+ MpId = ArmReadMpidr ();\r
CpuTarget = MpId &\r
- (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);\r
+ (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);\r
\r
if ((MmioRead32 (\r
mGicDistributorBase + ARM_GIC_ICDDCR\r
- ) & ARM_GIC_ICDDCR_DS) != 0) {\r
-\r
+ ) & ARM_GIC_ICDDCR_DS) != 0)\r
+ {\r
// If the Disable Security (DS) control bit is set, we are dealing with a\r
// GIC that has only one security state. In this case, let's assume we are\r
// executing in non-secure state (which is appropriate for DXE modules)\r
#include <Library/PcdLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
\r
-#define MAX_IO_PORT_ADDRESS 0xFFFF\r
+#define MAX_IO_PORT_ADDRESS 0xFFFF\r
\r
//\r
// Handle for the CPU I/O 2 Protocol\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
-STATIC CONST UINT8 mInStride[] = {\r
+STATIC CONST UINT8 mInStride[] = {\r
1, // EfiCpuIoWidthUint8\r
2, // EfiCpuIoWidthUint16\r
4, // EfiCpuIoWidthUint32\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
-STATIC CONST UINT8 mOutStride[] = {\r
+STATIC CONST UINT8 mOutStride[] = {\r
1, // EfiCpuIoWidthUint8\r
2, // EfiCpuIoWidthUint16\r
4, // EfiCpuIoWidthUint32\r
// For FIFO type, the target address won't increase during the access,\r
// so treat Count as 1\r
//\r
- if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {\r
+ if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {\r
Count = 1;\r
}\r
\r
//\r
// Check to see if Width is in the valid range for I/O Port operations\r
//\r
- Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
if (MaxCount < (Count - 1)) {\r
return EFI_UNSUPPORTED;\r
}\r
+\r
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {\r
return EFI_UNSUPPORTED;\r
}\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
*Uint8Buffer = MmioRead8 ((UINTN)Address);\r
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
\r
for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
//\r
// CPU I/O 2 Protocol instance\r
//\r
-STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {\r
+STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {\r
{\r
CpuMemoryServiceRead,\r
CpuMemoryServiceWrite\r
}\r
};\r
\r
-\r
/**\r
The user Entry Point for module CpuIo2Dxe. The user code starts with this function.\r
\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&mHandle,\r
- &gEfiCpuIo2ProtocolGuid, &mCpuIo2,\r
+ &gEfiCpuIo2ProtocolGuid,\r
+ &mCpuIo2,\r
NULL\r
);\r
ASSERT_EFI_ERROR (Status);\r
\r
// Return values of BASE_DISCOVER_LIST_PROTOCOLS command.\r
typedef struct {\r
- UINT32 NumProtocols;\r
+ UINT32 NumProtocols;\r
\r
// Array of four protocols in each element\r
// Total elements = 1 + (NumProtocols-1)/4\r
// NOTE: Since EDK2 does not allow flexible array member [] we declare\r
// here array of 1 element length. However below is used as a variable\r
// length array.\r
- UINT8 Protocols[1];\r
+ UINT8 Protocols[1];\r
} BASE_DISCOVER_LIST;\r
\r
/** Initialize Base protocol and install protocol on a given handle.\r
**/\r
EFI_STATUS\r
ScmiBaseProtocolInit (\r
- IN OUT EFI_HANDLE* Handle\r
+ IN OUT EFI_HANDLE *Handle\r
);\r
\r
#endif /* ARM_SCMI_BASE_PROTOCOL_PRIVATE_H_ */\r
\r
// Clock rate in two 32bit words.\r
typedef struct {\r
- UINT32 Low;\r
- UINT32 High;\r
+ UINT32 Low;\r
+ UINT32 High;\r
} CLOCK_RATE_DWORD;\r
\r
// Format of the returned rate array. Linear or Non-linear,.RatesFlag Bit[12]\r
-#define RATE_FORMAT_SHIFT 12\r
-#define RATE_FORMAT_MASK 0x0001\r
-#define RATE_FORMAT(RatesFlags) ((RatesFlags >> RATE_FORMAT_SHIFT) \\r
+#define RATE_FORMAT_SHIFT 12\r
+#define RATE_FORMAT_MASK 0x0001\r
+#define RATE_FORMAT(RatesFlags) ((RatesFlags >> RATE_FORMAT_SHIFT) \\r
& RATE_FORMAT_MASK)\r
\r
// Number of remaining rates after a call to the SCP, RatesFlag Bits[31:16]\r
-#define NUM_REMAIN_RATES_SHIFT 16\r
+#define NUM_REMAIN_RATES_SHIFT 16\r
#define NUM_REMAIN_RATES(RatesFlags) ((RatesFlags >> NUM_REMAIN_RATES_SHIFT))\r
\r
// Number of rates that are returned by a call.to the SCP, RatesFlag Bits[11:0]\r
-#define NUM_RATES_MASK 0x0FFF\r
-#define NUM_RATES(RatesFlags) (RatesFlags & NUM_RATES_MASK)\r
+#define NUM_RATES_MASK 0x0FFF\r
+#define NUM_RATES(RatesFlags) (RatesFlags & NUM_RATES_MASK)\r
\r
// Return values for the CLOCK_DESCRIBER_RATE command.\r
typedef struct {\r
- UINT32 NumRatesFlags;\r
+ UINT32 NumRatesFlags;\r
\r
// NOTE: Since EDK2 does not allow flexible array member [] we declare\r
// here array of 1 element length. However below is used as a variable\r
// length array.\r
- CLOCK_RATE_DWORD Rates[1];\r
+ CLOCK_RATE_DWORD Rates[1];\r
} CLOCK_DESCRIBE_RATES;\r
\r
-#define CLOCK_SET_DEFAULT_FLAGS 0\r
+#define CLOCK_SET_DEFAULT_FLAGS 0\r
\r
// Message parameters for CLOCK_RATE_SET command.\r
typedef struct {\r
- UINT32 Flags;\r
- UINT32 ClockId;\r
- CLOCK_RATE_DWORD Rate;\r
+ UINT32 Flags;\r
+ UINT32 ClockId;\r
+ CLOCK_RATE_DWORD Rate;\r
} CLOCK_RATE_SET_ATTRIBUTES;\r
\r
-\r
// Message parameters for CLOCK_CONFIG_SET command.\r
typedef struct {\r
- UINT32 ClockId;\r
- UINT32 Attributes;\r
+ UINT32 ClockId;\r
+ UINT32 Attributes;\r
} CLOCK_CONFIG_SET_ATTRIBUTES;\r
\r
// if ClockAttr Bit[0] is set then clock device is enabled.\r
-#define CLOCK_ENABLE_MASK 0x1\r
+#define CLOCK_ENABLE_MASK 0x1\r
#define CLOCK_ENABLED(ClockAttr) ((ClockAttr & CLOCK_ENABLE_MASK) == 1)\r
\r
typedef struct {\r
- UINT32 Attributes;\r
- UINT8 ClockName[SCMI_MAX_STR_LEN];\r
+ UINT32 Attributes;\r
+ UINT8 ClockName[SCMI_MAX_STR_LEN];\r
} CLOCK_ATTRIBUTES;\r
\r
#pragma pack()\r
**/\r
EFI_STATUS\r
ScmiClockProtocolInit (\r
- IN EFI_HANDLE *Handle\r
+ IN EFI_HANDLE *Handle\r
);\r
\r
#endif /* ARM_SCMI_CLOCK_PROTOCOL_PRIVATE_H_ */\r
#include <Protocol/ArmScmiPerformanceProtocol.h>\r
\r
// Number of performance levels returned by a call to the SCP, Lvls Bits[11:0]\r
-#define NUM_PERF_LEVELS_MASK 0x0FFF\r
-#define NUM_PERF_LEVELS(Lvls) (Lvls & NUM_PERF_LEVELS_MASK)\r
+#define NUM_PERF_LEVELS_MASK 0x0FFF\r
+#define NUM_PERF_LEVELS(Lvls) (Lvls & NUM_PERF_LEVELS_MASK)\r
\r
// Number of performance levels remaining after a call to the SCP, Lvls Bits[31:16]\r
#define NUM_REMAIN_PERF_LEVELS_SHIFT 16\r
-#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)\r
+#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)\r
\r
/** Return values for ScmiMessageIdPerformanceDescribeLevels command.\r
SCMI Spec section 4.5.2.5\r
**/\r
typedef struct {\r
- UINT32 NumLevels;\r
+ UINT32 NumLevels;\r
\r
// NOTE: Since EDK2 does not allow flexible array member [] we declare\r
// here array of 1 element length. However below is used as a variable\r
// length array.\r
- SCMI_PERFORMANCE_LEVEL PerfLevel[1]; // Offset to array of performance levels\r
+ SCMI_PERFORMANCE_LEVEL PerfLevel[1]; // Offset to array of performance levels\r
} PERF_DESCRIBE_LEVELS;\r
\r
/** Initialize performance management protocol and install on a given Handle.\r
**/\r
EFI_STATUS\r
ScmiPerformanceProtocolInit (\r
- IN EFI_HANDLE* Handle\r
+ IN EFI_HANDLE *Handle\r
);\r
\r
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_PRIVATE_H_ */\r
**/\r
EFI_STATUS\r
ScmiCommandGetPayload (\r
- OUT UINT32** Payload\r
+ OUT UINT32 **Payload\r
)\r
{\r
EFI_STATUS Status;\r
ScmiCommandExecute (\r
IN SCMI_COMMAND *Command,\r
IN OUT UINT32 *PayloadLength,\r
- OUT UINT32 **ReturnValues OPTIONAL\r
+ OUT UINT32 **ReturnValues OPTIONAL\r
)\r
{\r
EFI_STATUS Status;\r
return EFI_DEVICE_ERROR;\r
}\r
\r
- Response = (SCMI_MESSAGE_RESPONSE*)MtlGetChannelPayload (Channel);\r
+ Response = (SCMI_MESSAGE_RESPONSE *)MtlGetChannelPayload (Channel);\r
\r
if (Response->Status != ScmiSuccess) {\r
- DEBUG ((DEBUG_ERROR, "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",\r
Command->ProtocolId,\r
Command->MessageId,\r
Response->Status\r
SCMI_COMMAND Command;\r
UINT32 PayloadLength;\r
\r
- PayloadLength = 0;\r
+ PayloadLength = 0;\r
Command.ProtocolId = ProtocolId;\r
Command.MessageId = MessageId;\r
\r
OUT UINT32 *Version\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 *ProtocolVersion;\r
+ EFI_STATUS Status;\r
+ UINT32 *ProtocolVersion;\r
\r
Status = ScmiProtocolDiscoveryCommon (\r
ProtocolId,\r
ScmiMessageIdProtocolVersion,\r
- (UINT32**)&ProtocolVersion\r
+ (UINT32 **)&ProtocolVersion\r
);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
AsciiStrCpyS (\r
- (CHAR8*)VendorIdentifier,\r
+ (CHAR8 *)VendorIdentifier,\r
SCMI_MAX_STR_LEN,\r
- (CONST CHAR8*)ReturnValues\r
+ (CONST CHAR8 *)ReturnValues\r
);\r
\r
return EFI_SUCCESS;\r
Skip = 0;\r
\r
while (Skip < TotalProtocols) {\r
-\r
*MessageParams = Skip;\r
\r
// Note PayloadLength is a IN/OUT parameter.\r
Status = ScmiCommandExecute (\r
&Cmd,\r
&PayloadLength,\r
- (UINT32**)&DiscoverList\r
+ (UINT32 **)&DiscoverList\r
);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
// Instance of the SCMI Base protocol.\r
-STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol = {\r
+STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol = {\r
BaseGetVersion,\r
BaseGetTotalProtocols,\r
BaseDiscoverVendor,\r
**/\r
EFI_STATUS\r
ScmiBaseProtocolInit (\r
- IN OUT EFI_HANDLE* Handle\r
+ IN OUT EFI_HANDLE *Handle\r
)\r
{\r
return gBS->InstallMultipleProtocolInterfaces (\r
STATIC\r
UINT64\r
ConvertTo64Bit (\r
- IN UINT32 Low,\r
- IN UINT32 High\r
+ IN UINT32 Low,\r
+ IN UINT32 High\r
)\r
{\r
- return (Low | ((UINT64)High << 32));\r
+ return (Low | ((UINT64)High << 32));\r
}\r
\r
/** Return version of the clock management protocol supported by SCP firmware.\r
)\r
{\r
EFI_STATUS Status;\r
- UINT32 *ReturnValues;\r
+ UINT32 *ReturnValues;\r
\r
Status = ScmiGetProtocolAttributes (ScmiProtocolIdClock, &ReturnValues);\r
if (EFI_ERROR (Status)) {\r
OUT CHAR8 *ClockAsciiName\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- UINT32 *MessageParams;\r
- CLOCK_ATTRIBUTES *ClockAttributes;\r
- SCMI_COMMAND Cmd;\r
- UINT32 PayloadLength;\r
+ UINT32 *MessageParams;\r
+ CLOCK_ATTRIBUTES *ClockAttributes;\r
+ SCMI_COMMAND Cmd;\r
+ UINT32 PayloadLength;\r
\r
Status = ScmiCommandGetPayload (&MessageParams);\r
if (EFI_ERROR (Status)) {\r
Status = ScmiCommandExecute (\r
&Cmd,\r
&PayloadLength,\r
- (UINT32**)&ClockAttributes\r
+ (UINT32 **)&ClockAttributes\r
);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
- // TRUE if bit 0 of ClockAttributes->Attributes is set.\r
+\r
+ // TRUE if bit 0 of ClockAttributes->Attributes is set.\r
*Enabled = CLOCK_ENABLED (ClockAttributes->Attributes);\r
\r
AsciiStrCpyS (\r
ClockAsciiName,\r
SCMI_MAX_STR_LEN,\r
- (CONST CHAR8*)ClockAttributes->ClockName\r
+ (CONST CHAR8 *)ClockAttributes->ClockName\r
);\r
\r
return EFI_SUCCESS;\r
EFI_STATUS\r
ClockDescribeRates (\r
IN SCMI_CLOCK_PROTOCOL *This,\r
- IN UINT32 ClockId,\r
+ IN UINT32 ClockId,\r
OUT SCMI_CLOCK_RATE_FORMAT *Format,\r
OUT UINT32 *TotalRates,\r
IN OUT UINT32 *RateArraySize,\r
OUT SCMI_CLOCK_RATE *RateArray\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- UINT32 PayloadLength;\r
- SCMI_COMMAND Cmd;\r
- UINT32 *MessageParams;\r
- CLOCK_DESCRIBE_RATES *DescribeRates;\r
- CLOCK_RATE_DWORD *Rate;\r
+ UINT32 PayloadLength;\r
+ SCMI_COMMAND Cmd;\r
+ UINT32 *MessageParams;\r
+ CLOCK_DESCRIBE_RATES *DescribeRates;\r
+ CLOCK_RATE_DWORD *Rate;\r
\r
- UINT32 RequiredArraySize;\r
- UINT32 RateIndex;\r
- UINT32 RateNo;\r
- UINT32 RateOffset;\r
+ UINT32 RequiredArraySize;\r
+ UINT32 RateIndex;\r
+ UINT32 RateNo;\r
+ UINT32 RateOffset;\r
\r
- *TotalRates = 0;\r
+ *TotalRates = 0;\r
RequiredArraySize = 0;\r
- RateIndex = 0;\r
+ RateIndex = 0;\r
\r
Status = ScmiCommandGetPayload (&MessageParams);\r
if (EFI_ERROR (Status)) {\r
Cmd.ProtocolId = ScmiProtocolIdClock;\r
Cmd.MessageId = ScmiMessageIdClockDescribeRates;\r
\r
- *MessageParams++ = ClockId;\r
+ *MessageParams++ = ClockId;\r
\r
do {\r
-\r
*MessageParams = RateIndex;\r
\r
// Set Payload length, note PayloadLength is a IN/OUT parameter.\r
- PayloadLength = sizeof (ClockId) + sizeof (RateIndex);\r
+ PayloadLength = sizeof (ClockId) + sizeof (RateIndex);\r
\r
// Execute and wait for response on a SCMI channel.\r
Status = ScmiCommandExecute (\r
&Cmd,\r
&PayloadLength,\r
- (UINT32**)&DescribeRates\r
+ (UINT32 **)&DescribeRates\r
);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
+ NUM_REMAIN_RATES (DescribeRates->NumRatesFlags);\r
\r
if (*Format == ScmiClockRateFormatDiscrete) {\r
- RequiredArraySize = (*TotalRates) * sizeof (UINT64);\r
+ RequiredArraySize = (*TotalRates) * sizeof (UINT64);\r
} else {\r
- // We need to return triplet of 64 bit value for each rate\r
- RequiredArraySize = (*TotalRates) * 3 * sizeof (UINT64);\r
+ // We need to return triplet of 64 bit value for each rate\r
+ RequiredArraySize = (*TotalRates) * 3 * sizeof (UINT64);\r
}\r
\r
if (RequiredArraySize > (*RateArraySize)) {\r
for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {\r
// Linear clock rates from minimum to maximum in steps\r
// Minimum clock rate.\r
- Rate = &DescribeRates->Rates[RateOffset++];\r
+ Rate = &DescribeRates->Rates[RateOffset++];\r
RateArray[RateIndex].ContinuousRate.Min =\r
ConvertTo64Bit (Rate->Low, Rate->High);\r
\r
OUT UINT64 *Rate\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
UINT32 *MessageParams;\r
CLOCK_RATE_DWORD *ClockRate;\r
SCMI_COMMAND Cmd;\r
\r
- UINT32 PayloadLength;\r
+ UINT32 PayloadLength;\r
\r
Status = ScmiCommandGetPayload (&MessageParams);\r
if (EFI_ERROR (Status)) {\r
}\r
\r
// Fill arguments for clock protocol command.\r
- *MessageParams = ClockId;\r
+ *MessageParams = ClockId;\r
\r
- Cmd.ProtocolId = ScmiProtocolIdClock;\r
- Cmd.MessageId = ScmiMessageIdClockRateGet;\r
+ Cmd.ProtocolId = ScmiProtocolIdClock;\r
+ Cmd.MessageId = ScmiMessageIdClockRateGet;\r
\r
PayloadLength = sizeof (ClockId);\r
\r
Status = ScmiCommandExecute (\r
&Cmd,\r
&PayloadLength,\r
- (UINT32**)&ClockRate\r
+ (UINT32 **)&ClockRate\r
);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
IN UINT64 Rate\r
)\r
{\r
- EFI_STATUS Status;\r
- CLOCK_RATE_SET_ATTRIBUTES *ClockRateSetAttributes;\r
- SCMI_COMMAND Cmd;\r
- UINT32 PayloadLength;\r
+ EFI_STATUS Status;\r
+ CLOCK_RATE_SET_ATTRIBUTES *ClockRateSetAttributes;\r
+ SCMI_COMMAND Cmd;\r
+ UINT32 PayloadLength;\r
\r
- Status = ScmiCommandGetPayload ((UINT32**)&ClockRateSetAttributes);\r
+ Status = ScmiCommandGetPayload ((UINT32 **)&ClockRateSetAttributes);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
// Fill arguments for clock protocol command.\r
- ClockRateSetAttributes->ClockId = ClockId;\r
- ClockRateSetAttributes->Flags = CLOCK_SET_DEFAULT_FLAGS;\r
- ClockRateSetAttributes->Rate.Low = (UINT32)Rate;\r
- ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32);\r
+ ClockRateSetAttributes->ClockId = ClockId;\r
+ ClockRateSetAttributes->Flags = CLOCK_SET_DEFAULT_FLAGS;\r
+ ClockRateSetAttributes->Rate.Low = (UINT32)Rate;\r
+ ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32);\r
\r
Cmd.ProtocolId = ScmiProtocolIdClock;\r
Cmd.MessageId = ScmiMessageIdClockRateSet;\r
STATIC\r
EFI_STATUS\r
ClockEnable (\r
- IN SCMI_CLOCK2_PROTOCOL *This,\r
- IN UINT32 ClockId,\r
- IN BOOLEAN Enable\r
+ IN SCMI_CLOCK2_PROTOCOL *This,\r
+ IN UINT32 ClockId,\r
+ IN BOOLEAN Enable\r
)\r
{\r
- EFI_STATUS Status;\r
- CLOCK_CONFIG_SET_ATTRIBUTES *ClockConfigSetAttributes;\r
- SCMI_COMMAND Cmd;\r
- UINT32 PayloadLength;\r
+ EFI_STATUS Status;\r
+ CLOCK_CONFIG_SET_ATTRIBUTES *ClockConfigSetAttributes;\r
+ SCMI_COMMAND Cmd;\r
+ UINT32 PayloadLength;\r
\r
- Status = ScmiCommandGetPayload ((UINT32**)&ClockConfigSetAttributes);\r
+ Status = ScmiCommandGetPayload ((UINT32 **)&ClockConfigSetAttributes);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
}\r
\r
// Instance of the SCMI clock management protocol.\r
-STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = {\r
+STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = {\r
ClockGetVersion,\r
ClockGetTotalClocks,\r
ClockGetClockAttributes,\r
ClockDescribeRates,\r
ClockRateGet,\r
ClockRateSet\r
- };\r
+};\r
\r
// Instance of the SCMI clock management protocol.\r
-STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = {\r
+STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = {\r
(SCMI_CLOCK2_GET_VERSION)ClockGetVersion,\r
(SCMI_CLOCK2_GET_TOTAL_CLOCKS)ClockGetTotalClocks,\r
(SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES)ClockGetClockAttributes,\r
(SCMI_CLOCK2_RATE_SET)ClockRateSet,\r
SCMI_CLOCK2_PROTOCOL_VERSION,\r
ClockEnable\r
- };\r
+};\r
\r
/** Initialize clock management protocol and install protocol on a given handle.\r
\r
**/\r
EFI_STATUS\r
ScmiClockProtocolInit (\r
- IN EFI_HANDLE* Handle\r
+ IN EFI_HANDLE *Handle\r
)\r
{\r
return gBS->InstallMultipleProtocolInterfaces (\r
#include "ScmiDxe.h"\r
#include "ScmiPrivate.h"\r
\r
-STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {\r
- { ScmiProtocolIdBase, ScmiBaseProtocolInit },\r
+STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {\r
+ { ScmiProtocolIdBase, ScmiBaseProtocolInit },\r
{ ScmiProtocolIdPerformance, ScmiPerformanceProtocolInit },\r
- { ScmiProtocolIdClock, ScmiClockProtocolInit }\r
+ { ScmiProtocolIdClock, ScmiClockProtocolInit }\r
};\r
\r
/** ARM SCMI driver entry point function.\r
EFI_STATUS\r
EFIAPI\r
ArmScmiDxeEntryPoint (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
EFI_STATUS Status;\r
Status = gBS->LocateProtocol (\r
&gArmScmiBaseProtocolGuid,\r
NULL,\r
- (VOID**)&BaseProtocol\r
+ (VOID **)&BaseProtocol\r
);\r
if (EFI_ERROR (Status)) {\r
ASSERT (FALSE);\r
\r
// Accept any version between SCMI v1.0 and SCMI v2.0\r
if ((Version < BASE_PROTOCOL_VERSION_V1) ||\r
- (Version > BASE_PROTOCOL_VERSION_V2)) {\r
+ (Version > BASE_PROTOCOL_VERSION_V2))\r
+ {\r
ASSERT (FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
// Apart from Base protocol, SCMI may implement various other protocols,\r
// query total protocols implemented by the SCP firmware.\r
NumProtocols = 0;\r
- Status = BaseProtocol->GetTotalProtocols (BaseProtocol, &NumProtocols);\r
+ Status = BaseProtocol->GetTotalProtocols (BaseProtocol, &NumProtocols);\r
if (EFI_ERROR (Status)) {\r
ASSERT (FALSE);\r
return Status;\r
Status = gBS->AllocatePool (\r
EfiBootServicesData,\r
SupportedListSize,\r
- (VOID**)&SupportedList\r
+ (VOID **)&SupportedList\r
);\r
if (EFI_ERROR (Status)) {\r
ASSERT (FALSE);\r
\r
// Install supported protocol on ImageHandle.\r
for (ProtocolIndex = 1; ProtocolIndex < ARRAY_SIZE (Protocols);\r
- ProtocolIndex++) {\r
+ ProtocolIndex++)\r
+ {\r
for (Index = 0; Index < NumProtocols; Index++) {\r
if (Protocols[ProtocolIndex].Id == SupportedList[Index]) {\r
Status = Protocols[ProtocolIndex].InitFn (&ImageHandle);\r
ASSERT_EFI_ERROR (Status);\r
return Status;\r
}\r
+\r
break;\r
}\r
}\r
http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/\r
DEN0056A_System_Control_and_Management_Interface.pdf\r
**/\r
+\r
#ifndef SCMI_DXE_H_\r
#define SCMI_DXE_H_\r
\r
#include "ScmiPrivate.h"\r
\r
-#define MAX_VENDOR_LEN SCMI_MAX_STR_LEN\r
+#define MAX_VENDOR_LEN SCMI_MAX_STR_LEN\r
\r
/** Pointer to protocol initialization function.\r
\r
);\r
\r
typedef struct {\r
- SCMI_PROTOCOL_ID Id; // Protocol Id.\r
- SCMI_PROTOCOL_INIT_FXN InitFn; // Protocol init function.\r
+ SCMI_PROTOCOL_ID Id; // Protocol Id.\r
+ SCMI_PROTOCOL_INIT_FXN InitFn; // Protocol init function.\r
} SCMI_PROTOCOL_ENTRY;\r
\r
#endif /* SCMI_DXE_H_ */\r
STATIC\r
EFI_STATUS\r
PerformanceGetAttributes (\r
- IN SCMI_PERFORMANCE_PROTOCOL *This,\r
- OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes\r
+ IN SCMI_PERFORMANCE_PROTOCOL *This,\r
+ OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes\r
)\r
{\r
EFI_STATUS Status;\r
- UINT32* ReturnValues;\r
+ UINT32 *ReturnValues;\r
\r
Status = ScmiGetProtocolAttributes (\r
ScmiProtocolIdPerformance,\r
EFI_STATUS\r
PerformanceDomainAttributes (\r
IN SCMI_PERFORMANCE_PROTOCOL *This,\r
- IN UINT32 DomainId,\r
+ IN UINT32 DomainId,\r
OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes\r
)\r
{\r
EFI_STATUS Status;\r
UINT32 PayloadLength;\r
SCMI_COMMAND Cmd;\r
- UINT32* MessageParams;\r
+ UINT32 *MessageParams;\r
UINT32 LevelIndex;\r
UINT32 RequiredSize;\r
UINT32 LevelNo;\r
UINT32 ReturnNumLevels;\r
UINT32 ReturnRemainNumLevels;\r
\r
- PERF_DESCRIBE_LEVELS *Levels;\r
+ PERF_DESCRIBE_LEVELS *Levels;\r
\r
Status = ScmiCommandGetPayload (&MessageParams);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- LevelIndex = 0;\r
+ LevelIndex = 0;\r
RequiredSize = 0;\r
\r
*MessageParams++ = DomainId;\r
Cmd.MessageId = ScmiMessageIdPerformanceDescribeLevels;\r
\r
do {\r
-\r
*MessageParams = LevelIndex;\r
\r
// Note, PayloadLength is an IN/OUT parameter.\r
Status = ScmiCommandExecute (\r
&Cmd,\r
&PayloadLength,\r
- (UINT32**)&Levels\r
+ (UINT32 **)&Levels\r
);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- ReturnNumLevels = NUM_PERF_LEVELS (Levels->NumLevels);\r
+ ReturnNumLevels = NUM_PERF_LEVELS (Levels->NumLevels);\r
ReturnRemainNumLevels = NUM_REMAIN_PERF_LEVELS (Levels->NumLevels);\r
\r
if (RequiredSize == 0) {\r
}\r
\r
for (LevelNo = 0; LevelNo < ReturnNumLevels; LevelNo++) {\r
- CopyMem (\r
- &LevelArray[LevelIndex++],\r
- &Levels->PerfLevel[LevelNo],\r
- sizeof (SCMI_PERFORMANCE_LEVEL)\r
- );\r
+ CopyMem (\r
+ &LevelArray[LevelIndex++],\r
+ &Levels->PerfLevel[LevelNo],\r
+ sizeof (SCMI_PERFORMANCE_LEVEL)\r
+ );\r
}\r
-\r
} while (ReturnRemainNumLevels != 0);\r
\r
*LevelArraySize = RequiredSize;\r
**/\r
EFI_STATUS\r
PerformanceLimitsSet (\r
- IN SCMI_PERFORMANCE_PROTOCOL *This,\r
- IN UINT32 DomainId,\r
- IN SCMI_PERFORMANCE_LIMITS *Limits\r
+ IN SCMI_PERFORMANCE_PROTOCOL *This,\r
+ IN UINT32 DomainId,\r
+ IN SCMI_PERFORMANCE_LIMITS *Limits\r
)\r
{\r
EFI_STATUS Status;\r
**/\r
EFI_STATUS\r
PerformanceLimitsGet (\r
- SCMI_PERFORMANCE_PROTOCOL *This,\r
- UINT32 DomainId,\r
- SCMI_PERFORMANCE_LIMITS *Limits\r
+ SCMI_PERFORMANCE_PROTOCOL *This,\r
+ UINT32 DomainId,\r
+ SCMI_PERFORMANCE_LIMITS *Limits\r
)\r
{\r
EFI_STATUS Status;\r
Status = ScmiCommandExecute (\r
&Cmd,\r
&PayloadLength,\r
- (UINT32**)&ReturnValues\r
+ (UINT32 **)&ReturnValues\r
);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
**/\r
EFI_STATUS\r
PerformanceLevelSet (\r
- IN SCMI_PERFORMANCE_PROTOCOL *This,\r
- IN UINT32 DomainId,\r
- IN UINT32 Level\r
+ IN SCMI_PERFORMANCE_PROTOCOL *This,\r
+ IN UINT32 DomainId,\r
+ IN UINT32 Level\r
)\r
{\r
EFI_STATUS Status;\r
**/\r
EFI_STATUS\r
PerformanceLevelGet (\r
- IN SCMI_PERFORMANCE_PROTOCOL *This,\r
- IN UINT32 DomainId,\r
- OUT UINT32 *Level\r
+ IN SCMI_PERFORMANCE_PROTOCOL *This,\r
+ IN UINT32 DomainId,\r
+ OUT UINT32 *Level\r
)\r
{\r
EFI_STATUS Status;\r
}\r
\r
// Instance of the SCMI performance management protocol.\r
-STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol = {\r
+STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol = {\r
PerformanceGetVersion,\r
PerformanceGetAttributes,\r
PerformanceDomainAttributes,\r
**/\r
EFI_STATUS\r
ScmiPerformanceProtocolInit (\r
- IN EFI_HANDLE* Handle\r
+ IN EFI_HANDLE *Handle\r
)\r
{\r
return gBS->InstallMultipleProtocolInterfaces (\r
http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/\r
DEN0056A_System_Control_and_Management_Interface.pdf\r
**/\r
+\r
#ifndef SCMI_PRIVATE_H_\r
#define SCMI_PRIVATE_H_\r
\r
\r
// Not defined in SCMI specification but will help to identify a message.\r
typedef struct {\r
- SCMI_PROTOCOL_ID ProtocolId;\r
- UINT32 MessageId;\r
+ SCMI_PROTOCOL_ID ProtocolId;\r
+ UINT32 MessageId;\r
} SCMI_COMMAND;\r
\r
#pragma pack(1)\r
\r
// Response to a SCMI command.\r
typedef struct {\r
- INT32 Status;\r
- UINT32 ReturnValues[];\r
+ INT32 Status;\r
+ UINT32 ReturnValues[];\r
} SCMI_MESSAGE_RESPONSE;\r
\r
// Message header. MsgId[7:0], MsgType[9:8], ProtocolId[17:10]\r
-#define MESSAGE_TYPE_SHIFT 8\r
-#define PROTOCOL_ID_SHIFT 10\r
+#define MESSAGE_TYPE_SHIFT 8\r
+#define PROTOCOL_ID_SHIFT 10\r
#define SCMI_MESSAGE_HEADER(MsgId, MsgType, ProtocolId) ( \\r
MsgType << MESSAGE_TYPE_SHIFT | \\r
ProtocolId << PROTOCOL_ID_SHIFT | \\r
)\r
// SCMI message header.\r
typedef struct {\r
- UINT32 MessageHeader;\r
+ UINT32 MessageHeader;\r
} SCMI_MESSAGE_HEADER;\r
\r
#pragma pack()\r
**/\r
EFI_STATUS\r
ScmiCommandGetPayload (\r
- OUT UINT32** Payload\r
+ OUT UINT32 **Payload\r
);\r
\r
/** Execute a SCMI command and receive a response.\r
ScmiCommandExecute (\r
IN SCMI_COMMAND *Command,\r
IN OUT UINT32 *PayloadLength,\r
- OUT UINT32 **ReturnValues OPTIONAL\r
+ OUT UINT32 **ReturnValues OPTIONAL\r
);\r
\r
/** Return protocol version from SCP for a given protocol ID.\r
#include <Library/MemoryAllocationLib.h>\r
#include "CpuDxe.h"\r
\r
-#define INVALID_ENTRY ((UINT32)~0)\r
+#define INVALID_ENTRY ((UINT32)~0)\r
\r
#define MIN_T0SZ 16\r
#define BITS_PER_LEVEL 9\r
STATIC\r
VOID\r
GetRootTranslationTableInfo (\r
- IN UINTN T0SZ,\r
- OUT UINTN *RootTableLevel,\r
- OUT UINTN *RootTableEntryCount\r
+ IN UINTN T0SZ,\r
+ OUT UINTN *RootTableLevel,\r
+ OUT UINTN *RootTableEntryCount\r
)\r
{\r
- *RootTableLevel = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;\r
- *RootTableEntryCount = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;\r
+ *RootTableLevel = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;\r
+ *RootTableEntryCount = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;\r
}\r
\r
STATIC\r
UINT64\r
PageAttributeToGcdAttribute (\r
- IN UINT64 PageAttributes\r
+ IN UINT64 PageAttributes\r
)\r
{\r
UINT64 GcdAttributes;\r
\r
switch (PageAttributes & TT_ATTR_INDX_MASK) {\r
- case TT_ATTR_INDX_DEVICE_MEMORY:\r
- GcdAttributes = EFI_MEMORY_UC;\r
- break;\r
- case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:\r
- GcdAttributes = EFI_MEMORY_WC;\r
- break;\r
- case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:\r
- GcdAttributes = EFI_MEMORY_WT;\r
- break;\r
- case TT_ATTR_INDX_MEMORY_WRITE_BACK:\r
- GcdAttributes = EFI_MEMORY_WB;\r
- break;\r
- default:\r
- DEBUG ((DEBUG_ERROR,\r
- "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n",\r
- PageAttributes));\r
- ASSERT (0);\r
- // The Global Coherency Domain (GCD) value is defined as a bit set.\r
- // Returning 0 means no attribute has been set.\r
- GcdAttributes = 0;\r
+ case TT_ATTR_INDX_DEVICE_MEMORY:\r
+ GcdAttributes = EFI_MEMORY_UC;\r
+ break;\r
+ case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:\r
+ GcdAttributes = EFI_MEMORY_WC;\r
+ break;\r
+ case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:\r
+ GcdAttributes = EFI_MEMORY_WT;\r
+ break;\r
+ case TT_ATTR_INDX_MEMORY_WRITE_BACK:\r
+ GcdAttributes = EFI_MEMORY_WB;\r
+ break;\r
+ default:\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n",\r
+ PageAttributes\r
+ ));\r
+ ASSERT (0);\r
+ // The Global Coherency Domain (GCD) value is defined as a bit set.\r
+ // Returning 0 means no attribute has been set.\r
+ GcdAttributes = 0;\r
}\r
\r
// Determine protection attributes\r
if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) ||\r
- ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {\r
+ ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO))\r
+ {\r
// Read only cases map to write-protect\r
GcdAttributes |= EFI_MEMORY_RO;\r
}\r
UINT64\r
GetFirstPageAttribute (\r
IN UINT64 *FirstLevelTableAddress,\r
- IN UINTN TableLevel\r
+ IN UINTN TableLevel\r
)\r
{\r
- UINT64 FirstEntry;\r
+ UINT64 FirstEntry;\r
\r
// Get the first entry of the table\r
FirstEntry = *FirstLevelTableAddress;\r
\r
- if ((TableLevel != 3) && (FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {\r
+ if ((TableLevel != 3) && ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {\r
// Only valid for Levels 0, 1 and 2\r
\r
// Get the attribute of the subsequent table\r
- return GetFirstPageAttribute ((UINT64*)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1);\r
+ return GetFirstPageAttribute ((UINT64 *)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1);\r
} else if (((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) ||\r
((TableLevel == 3) && ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3)))\r
{\r
STATIC\r
UINT64\r
GetNextEntryAttribute (\r
- IN UINT64 *TableAddress,\r
+ IN UINT64 *TableAddress,\r
IN UINTN EntryCount,\r
IN UINTN TableLevel,\r
IN UINT64 BaseAddress,\r
- IN OUT UINT32 *PrevEntryAttribute,\r
- IN OUT UINT64 *StartGcdRegion\r
+ IN OUT UINT32 *PrevEntryAttribute,\r
+ IN OUT UINT64 *StartGcdRegion\r
)\r
{\r
- UINTN Index;\r
- UINT64 Entry;\r
- UINT32 EntryAttribute;\r
- UINT32 EntryType;\r
- EFI_STATUS Status;\r
- UINTN NumberOfDescriptors;\r
+ UINTN Index;\r
+ UINT64 Entry;\r
+ UINT32 EntryAttribute;\r
+ UINT32 EntryType;\r
+ EFI_STATUS Status;\r
+ UINTN NumberOfDescriptors;\r
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
\r
// Get the memory space map from GCD\r
MemorySpaceMap = NULL;\r
- Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
+ Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
ASSERT_EFI_ERROR (Status);\r
\r
// We cannot get more than 3-level page table\r
// While the top level table might not contain TT_ENTRY_COUNT entries;\r
// the subsequent ones should be filled up\r
for (Index = 0; Index < EntryCount; Index++) {\r
- Entry = TableAddress[Index];\r
- EntryType = Entry & TT_TYPE_MASK;\r
+ Entry = TableAddress[Index];\r
+ EntryType = Entry & TT_TYPE_MASK;\r
EntryAttribute = Entry & TT_ATTR_INDX_MASK;\r
\r
// If Entry is a Table Descriptor type entry then go through the sub-level table\r
if ((EntryType == TT_TYPE_BLOCK_ENTRY) ||\r
- ((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3))) {\r
+ ((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3)))\r
+ {\r
if ((*PrevEntryAttribute == INVALID_ENTRY) || (EntryAttribute != *PrevEntryAttribute)) {\r
if (*PrevEntryAttribute != INVALID_ENTRY) {\r
// Update GCD with the last region\r
- SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,\r
- *StartGcdRegion,\r
- (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion,\r
- PageAttributeToGcdAttribute (*PrevEntryAttribute));\r
+ SetGcdMemorySpaceAttributes (\r
+ MemorySpaceMap,\r
+ NumberOfDescriptors,\r
+ *StartGcdRegion,\r
+ (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel))) - *StartGcdRegion,\r
+ PageAttributeToGcdAttribute (*PrevEntryAttribute)\r
+ );\r
}\r
\r
// Start of the new region\r
- *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel));\r
+ *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel));\r
*PrevEntryAttribute = EntryAttribute;\r
} else {\r
continue;\r
ASSERT (TableLevel < 3);\r
\r
// Increase the level number and scan the sub-level table\r
- GetNextEntryAttribute ((UINT64*)(Entry & TT_ADDRESS_MASK_DESCRIPTION_TABLE),\r
- TT_ENTRY_COUNT, TableLevel + 1,\r
- (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))),\r
- PrevEntryAttribute, StartGcdRegion);\r
+ GetNextEntryAttribute (\r
+ (UINT64 *)(Entry & TT_ADDRESS_MASK_DESCRIPTION_TABLE),\r
+ TT_ENTRY_COUNT,\r
+ TableLevel + 1,\r
+ (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel))),\r
+ PrevEntryAttribute,\r
+ StartGcdRegion\r
+ );\r
} else {\r
if (*PrevEntryAttribute != INVALID_ENTRY) {\r
// Update GCD with the last region\r
- SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,\r
- *StartGcdRegion,\r
- (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion,\r
- PageAttributeToGcdAttribute (*PrevEntryAttribute));\r
+ SetGcdMemorySpaceAttributes (\r
+ MemorySpaceMap,\r
+ NumberOfDescriptors,\r
+ *StartGcdRegion,\r
+ (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel))) - *StartGcdRegion,\r
+ PageAttributeToGcdAttribute (*PrevEntryAttribute)\r
+ );\r
\r
// Start of the new region\r
- *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel));\r
+ *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel));\r
*PrevEntryAttribute = INVALID_ENTRY;\r
}\r
}\r
\r
FreePool (MemorySpaceMap);\r
\r
- return BaseAddress + (EntryCount * TT_ADDRESS_AT_LEVEL(TableLevel));\r
+ return BaseAddress + (EntryCount * TT_ADDRESS_AT_LEVEL (TableLevel));\r
}\r
\r
EFI_STATUS\r
SyncCacheConfig (\r
- IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
+ IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 PageAttribute;\r
- UINT64 *FirstLevelTableAddress;\r
- UINTN TableLevel;\r
- UINTN TableCount;\r
- UINTN NumberOfDescriptors;\r
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
- UINTN Tcr;\r
- UINTN T0SZ;\r
- UINT64 BaseAddressGcdRegion;\r
- UINT64 EndAddressGcdRegion;\r
+ EFI_STATUS Status;\r
+ UINT32 PageAttribute;\r
+ UINT64 *FirstLevelTableAddress;\r
+ UINTN TableLevel;\r
+ UINTN TableCount;\r
+ UINTN NumberOfDescriptors;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
+ UINTN Tcr;\r
+ UINTN T0SZ;\r
+ UINT64 BaseAddressGcdRegion;\r
+ UINT64 EndAddressGcdRegion;\r
\r
// This code assumes MMU is enabled and filed with section translations\r
ASSERT (ArmMmuEnabled ());\r
// Get the memory space map from GCD\r
//\r
MemorySpaceMap = NULL;\r
- Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
+ Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
ASSERT_EFI_ERROR (Status);\r
\r
// The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs\r
// with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.\r
\r
// Obtain page table base\r
- FirstLevelTableAddress = (UINT64*)(ArmGetTTBR0BaseAddress ());\r
+ FirstLevelTableAddress = (UINT64 *)(ArmGetTTBR0BaseAddress ());\r
\r
// Get Translation Control Register value\r
Tcr = ArmGetTCR ();\r
\r
// We scan from the start of the memory map (ie: at the address 0x0)\r
BaseAddressGcdRegion = 0x0;\r
- EndAddressGcdRegion = GetNextEntryAttribute (FirstLevelTableAddress,\r
- TableCount, TableLevel,\r
- BaseAddressGcdRegion,\r
- &PageAttribute, &BaseAddressGcdRegion);\r
+ EndAddressGcdRegion = GetNextEntryAttribute (\r
+ FirstLevelTableAddress,\r
+ TableCount,\r
+ TableLevel,\r
+ BaseAddressGcdRegion,\r
+ &PageAttribute,\r
+ &BaseAddressGcdRegion\r
+ );\r
\r
// Update GCD with the last region if valid\r
if (PageAttribute != INVALID_ENTRY) {\r
- SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,\r
- BaseAddressGcdRegion,\r
- EndAddressGcdRegion - BaseAddressGcdRegion,\r
- PageAttributeToGcdAttribute (PageAttribute));\r
+ SetGcdMemorySpaceAttributes (\r
+ MemorySpaceMap,\r
+ NumberOfDescriptors,\r
+ BaseAddressGcdRegion,\r
+ EndAddressGcdRegion - BaseAddressGcdRegion,\r
+ PageAttributeToGcdAttribute (PageAttribute)\r
+ );\r
}\r
\r
FreePool (MemorySpaceMap);\r
\r
UINT64\r
EfiAttributeToArmAttribute (\r
- IN UINT64 EfiAttributes\r
+ IN UINT64 EfiAttributes\r
)\r
{\r
- UINT64 ArmAttributes;\r
+ UINT64 ArmAttributes;\r
\r
switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) {\r
- case EFI_MEMORY_UC:\r
- if (ArmReadCurrentEL () == AARCH64_EL2) {\r
- ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;\r
- } else {\r
- ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;\r
- }\r
- break;\r
- case EFI_MEMORY_WC:\r
- ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r
- break;\r
- case EFI_MEMORY_WT:\r
- ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;\r
- break;\r
- case EFI_MEMORY_WB:\r
- ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r
- break;\r
- default:\r
- ArmAttributes = TT_ATTR_INDX_MASK;\r
+ case EFI_MEMORY_UC:\r
+ if (ArmReadCurrentEL () == AARCH64_EL2) {\r
+ ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;\r
+ } else {\r
+ ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;\r
+ }\r
+\r
+ break;\r
+ case EFI_MEMORY_WC:\r
+ ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r
+ break;\r
+ case EFI_MEMORY_WT:\r
+ ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;\r
+ break;\r
+ case EFI_MEMORY_WB:\r
+ ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r
+ break;\r
+ default:\r
+ ArmAttributes = TT_ATTR_INDX_MASK;\r
}\r
\r
// Set the access flag to match the block attributes\r
// And then the function will identify the size of the region that has the same page table attribute.\r
EFI_STATUS\r
GetMemoryRegionRec (\r
- IN UINT64 *TranslationTable,\r
- IN UINTN TableLevel,\r
- IN UINT64 *LastBlockEntry,\r
- IN OUT UINTN *BaseAddress,\r
- OUT UINTN *RegionLength,\r
- OUT UINTN *RegionAttributes\r
+ IN UINT64 *TranslationTable,\r
+ IN UINTN TableLevel,\r
+ IN UINT64 *LastBlockEntry,\r
+ IN OUT UINTN *BaseAddress,\r
+ OUT UINTN *RegionLength,\r
+ OUT UINTN *RegionAttributes\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT64 *NextTranslationTable;\r
- UINT64 *BlockEntry;\r
- UINT64 BlockEntryType;\r
- UINT64 EntryType;\r
+ EFI_STATUS Status;\r
+ UINT64 *NextTranslationTable;\r
+ UINT64 *BlockEntry;\r
+ UINT64 BlockEntryType;\r
+ UINT64 EntryType;\r
\r
if (TableLevel != 3) {\r
BlockEntryType = TT_TYPE_BLOCK_ENTRY;\r
}\r
\r
// Find the block entry linked to the Base Address\r
- BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, TableLevel, *BaseAddress);\r
- EntryType = *BlockEntry & TT_TYPE_MASK;\r
+ BlockEntry = (UINT64 *)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, TableLevel, *BaseAddress);\r
+ EntryType = *BlockEntry & TT_TYPE_MASK;\r
\r
if ((TableLevel < 3) && (EntryType == TT_TYPE_TABLE_ENTRY)) {\r
- NextTranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);\r
+ NextTranslationTable = (UINT64 *)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);\r
\r
// The entry is a page table, so we go to the next level\r
Status = GetMemoryRegionRec (\r
- NextTranslationTable, // Address of the next level page table\r
- TableLevel + 1, // Next Page Table level\r
- (UINTN*)TT_LAST_BLOCK_ADDRESS(NextTranslationTable, TT_ENTRY_COUNT),\r
- BaseAddress, RegionLength, RegionAttributes);\r
+ NextTranslationTable, // Address of the next level page table\r
+ TableLevel + 1, // Next Page Table level\r
+ (UINTN *)TT_LAST_BLOCK_ADDRESS (NextTranslationTable, TT_ENTRY_COUNT),\r
+ BaseAddress,\r
+ RegionLength,\r
+ RegionAttributes\r
+ );\r
\r
// In case of 'Success', it means the end of the block region has been found into the upper\r
// level translation table\r
- if (!EFI_ERROR(Status)) {\r
+ if (!EFI_ERROR (Status)) {\r
return EFI_SUCCESS;\r
}\r
\r
} else if (EntryType == BlockEntryType) {\r
// We have found the BlockEntry attached to the address. We save its start address (the start\r
// address might be before the 'BaseAddress') and attributes\r
- *BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL(TableLevel) - 1);\r
+ *BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL (TableLevel) - 1);\r
*RegionLength = 0;\r
*RegionAttributes = *BlockEntry & TT_ATTRIBUTES_MASK;\r
} else {\r
\r
while (BlockEntry <= LastBlockEntry) {\r
if ((*BlockEntry & TT_ATTRIBUTES_MASK) == *RegionAttributes) {\r
- *RegionLength = *RegionLength + TT_BLOCK_ENTRY_SIZE_AT_LEVEL(TableLevel);\r
+ *RegionLength = *RegionLength + TT_BLOCK_ENTRY_SIZE_AT_LEVEL (TableLevel);\r
} else {\r
// In case we have found the end of the region we return success\r
return EFI_SUCCESS;\r
}\r
+\r
BlockEntry++;\r
}\r
\r
\r
EFI_STATUS\r
GetMemoryRegion (\r
- IN OUT UINTN *BaseAddress,\r
- OUT UINTN *RegionLength,\r
- OUT UINTN *RegionAttributes\r
+ IN OUT UINTN *BaseAddress,\r
+ OUT UINTN *RegionLength,\r
+ OUT UINTN *RegionAttributes\r
)\r
{\r
EFI_STATUS Status;\r
- UINT64 *TranslationTable;\r
+ UINT64 *TranslationTable;\r
UINTN TableLevel;\r
UINTN EntryCount;\r
UINTN T0SZ;\r
// Get the Table info from T0SZ\r
GetRootTranslationTableInfo (T0SZ, &TableLevel, &EntryCount);\r
\r
- Status = GetMemoryRegionRec (TranslationTable, TableLevel,\r
- (UINTN*)TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount),\r
- BaseAddress, RegionLength, RegionAttributes);\r
+ Status = GetMemoryRegionRec (\r
+ TranslationTable,\r
+ TableLevel,\r
+ (UINTN *)TT_LAST_BLOCK_ADDRESS (TranslationTable, EntryCount),\r
+ BaseAddress,\r
+ RegionLength,\r
+ RegionAttributes\r
+ );\r
\r
// If the region continues up to the end of the root table then GetMemoryRegionRec()\r
// will return EFI_NOT_FOUND\r
*GcdAttributes = 0;\r
\r
// determine cacheability attributes\r
- switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {\r
+ switch (SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {\r
case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:\r
*GcdAttributes |= EFI_MEMORY_UC;\r
break;\r
}\r
\r
// determine protection attributes\r
- switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {\r
+ switch (SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {\r
case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write\r
- //*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;\r
+ // *GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;\r
break;\r
\r
case TT_DESCRIPTOR_SECTION_AP_RW_NO:\r
*GcdAttributes = 0;\r
\r
// determine cacheability attributes\r
- switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {\r
+ switch (PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {\r
case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED:\r
*GcdAttributes |= EFI_MEMORY_UC;\r
break;\r
}\r
\r
// determine protection attributes\r
- switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {\r
+ switch (PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {\r
case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write\r
- //*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;\r
+ // *GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;\r
break;\r
\r
case TT_DESCRIPTOR_PAGE_AP_RW_NO:\r
\r
EFI_STATUS\r
SyncCacheConfigPage (\r
- IN UINT32 SectionIndex,\r
- IN UINT32 FirstLevelDescriptor,\r
- IN UINTN NumberOfDescriptors,\r
- IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
- IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,\r
- IN OUT UINT64 *NextRegionLength,\r
- IN OUT UINT32 *NextSectionAttributes\r
+ IN UINT32 SectionIndex,\r
+ IN UINT32 FirstLevelDescriptor,\r
+ IN UINTN NumberOfDescriptors,\r
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
+ IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,\r
+ IN OUT UINT64 *NextRegionLength,\r
+ IN OUT UINT32 *NextSectionAttributes\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 i;\r
- volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;\r
- UINT32 NextPageAttributes;\r
- UINT32 PageAttributes;\r
- UINT32 BaseAddress;\r
- UINT64 GcdAttributes;\r
+ EFI_STATUS Status;\r
+ UINT32 i;\r
+ volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;\r
+ UINT32 NextPageAttributes;\r
+ UINT32 PageAttributes;\r
+ UINT32 BaseAddress;\r
+ UINT64 GcdAttributes;\r
\r
// Get the Base Address from FirstLevelDescriptor;\r
- BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
+ BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
\r
// Convert SectionAttributes into PageAttributes\r
NextPageAttributes =\r
- TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) |\r
- TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes);\r
+ TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (*NextSectionAttributes, 0) |\r
+ TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (*NextSectionAttributes);\r
\r
// obtain page table base\r
SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);\r
\r
- for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {\r
+ for (i = 0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {\r
if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {\r
// extract attributes (cacheability and permissions)\r
PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);\r
\r
if (NextPageAttributes == 0) {\r
// start on a new region\r
- *NextRegionLength = 0;\r
- *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
+ *NextRegionLength = 0;\r
+ *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
NextPageAttributes = PageAttributes;\r
} else if (PageAttributes != NextPageAttributes) {\r
// Convert Section Attributes into GCD Attributes\r
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);\r
\r
// start on a new region\r
- *NextRegionLength = 0;\r
- *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
+ *NextRegionLength = 0;\r
+ *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
NextPageAttributes = PageAttributes;\r
}\r
} else if (NextPageAttributes != 0) {\r
// update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);\r
\r
- *NextRegionLength = 0;\r
- *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
+ *NextRegionLength = 0;\r
+ *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r
NextPageAttributes = 0;\r
}\r
+\r
*NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE;\r
}\r
\r
// Convert back PageAttributes into SectionAttributes\r
*NextSectionAttributes =\r
- TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) |\r
- TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes);\r
+ TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (NextPageAttributes, 0) |\r
+ TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (NextPageAttributes);\r
\r
return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
SyncCacheConfig (\r
- IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
+ IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 i;\r
- EFI_PHYSICAL_ADDRESS NextRegionBase;\r
- UINT64 NextRegionLength;\r
- UINT32 NextSectionAttributes;\r
- UINT32 SectionAttributes;\r
- UINT64 GcdAttributes;\r
- volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
- UINTN NumberOfDescriptors;\r
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
-\r
+ EFI_STATUS Status;\r
+ UINT32 i;\r
+ EFI_PHYSICAL_ADDRESS NextRegionBase;\r
+ UINT64 NextRegionLength;\r
+ UINT32 NextSectionAttributes;\r
+ UINT32 SectionAttributes;\r
+ UINT64 GcdAttributes;\r
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
+ UINTN NumberOfDescriptors;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
\r
DEBUG ((DEBUG_PAGE, "SyncCacheConfig()\n"));\r
\r
// Get the memory space map from GCD\r
//\r
MemorySpaceMap = NULL;\r
- Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
+ Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
ASSERT_EFI_ERROR (Status);\r
\r
-\r
// The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs\r
// to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a\r
// GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were\r
\r
// iterate through each 1MB descriptor\r
NextRegionBase = NextRegionLength = 0;\r
- for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {\r
+ for (i = 0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {\r
if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {\r
// extract attributes (cacheability and permissions)\r
SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);\r
\r
if (NextSectionAttributes == 0) {\r
// start on a new region\r
- NextRegionLength = 0;\r
- NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
+ NextRegionLength = 0;\r
+ NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
NextSectionAttributes = SectionAttributes;\r
} else if (SectionAttributes != NextSectionAttributes) {\r
// Convert Section Attributes into GCD Attributes\r
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
\r
// start on a new region\r
- NextRegionLength = 0;\r
- NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
+ NextRegionLength = 0;\r
+ NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
NextSectionAttributes = SectionAttributes;\r
}\r
+\r
NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;\r
- } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) {\r
+ } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (FirstLevelTable[i])) {\r
// In this case any bits set in the 'NextSectionAttributes' are garbage and were set from\r
// bits that are actually part of the pagetable address. We clear it out to zero so that\r
// the SyncCacheConfigPage will use the page attributes instead of trying to convert the\r
// section attributes into page attributes\r
NextSectionAttributes = 0;\r
- Status = SyncCacheConfigPage (\r
- i,FirstLevelTable[i],\r
- NumberOfDescriptors, MemorySpaceMap,\r
- &NextRegionBase,&NextRegionLength,&NextSectionAttributes);\r
+ Status = SyncCacheConfigPage (\r
+ i,\r
+ FirstLevelTable[i],\r
+ NumberOfDescriptors,\r
+ MemorySpaceMap,\r
+ &NextRegionBase,\r
+ &NextRegionLength,\r
+ &NextSectionAttributes\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
} else {\r
// We do not support yet 16MB sections\r
// update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
\r
- NextRegionLength = 0;\r
- NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
+ NextRegionLength = 0;\r
+ NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
NextSectionAttributes = 0;\r
}\r
+\r
NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;\r
}\r
} // section entry loop\r
\r
UINT64\r
EfiAttributeToArmAttribute (\r
- IN UINT64 EfiAttributes\r
+ IN UINT64 EfiAttributes\r
)\r
{\r
- UINT64 ArmAttributes;\r
+ UINT64 ArmAttributes;\r
\r
switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) {\r
case EFI_MEMORY_UC:\r
\r
EFI_STATUS\r
GetMemoryRegionPage (\r
- IN UINT32 *PageTable,\r
- IN OUT UINTN *BaseAddress,\r
- OUT UINTN *RegionLength,\r
- OUT UINTN *RegionAttributes\r
+ IN UINT32 *PageTable,\r
+ IN OUT UINTN *BaseAddress,\r
+ OUT UINTN *RegionLength,\r
+ OUT UINTN *RegionAttributes\r
)\r
{\r
- UINT32 PageAttributes;\r
- UINT32 TableIndex;\r
- UINT32 PageDescriptor;\r
+ UINT32 PageAttributes;\r
+ UINT32 TableIndex;\r
+ UINT32 PageDescriptor;\r
\r
// Convert the section attributes into page attributes\r
PageAttributes = ConvertSectionAttributesToPageAttributes (*RegionAttributes, 0);\r
ASSERT (TableIndex < TRANSLATION_TABLE_PAGE_COUNT);\r
\r
// Go through the page table to find the end of the section\r
- for (; TableIndex < TRANSLATION_TABLE_PAGE_COUNT; TableIndex++) {\r
+ for ( ; TableIndex < TRANSLATION_TABLE_PAGE_COUNT; TableIndex++) {\r
// Get the section at the given index\r
PageDescriptor = PageTable[TableIndex];\r
\r
}\r
} else {\r
// We do not support Large Page yet. We return EFI_SUCCESS that means end of the region.\r
- ASSERT(0);\r
+ ASSERT (0);\r
return EFI_SUCCESS;\r
}\r
}\r
\r
EFI_STATUS\r
GetMemoryRegion (\r
- IN OUT UINTN *BaseAddress,\r
- OUT UINTN *RegionLength,\r
- OUT UINTN *RegionAttributes\r
+ IN OUT UINTN *BaseAddress,\r
+ OUT UINTN *RegionLength,\r
+ OUT UINTN *RegionAttributes\r
)\r
{\r
EFI_STATUS Status;\r
UINT32 PageAttributes;\r
UINT32 PageTableIndex;\r
UINT32 SectionDescriptor;\r
- ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
- UINT32 *PageTable;\r
+ ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
+ UINT32 *PageTable;\r
\r
// Initialize the arguments\r
*RegionLength = 0;\r
if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) ||\r
((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION))\r
{\r
- *BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;\r
+ *BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;\r
*RegionAttributes = SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK;\r
} else {\r
// Otherwise, we round it to the page boundary\r
*BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK;\r
\r
// Get the attribute at the page table level (Level 2)\r
- PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);\r
+ PageTable = (UINT32 *)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);\r
\r
// Calculate index into first level translation table for start of modification\r
PageTableIndex = ((*BaseAddress) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);\r
\r
- PageAttributes = PageTable[PageTableIndex] & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK;\r
+ PageAttributes = PageTable[PageTableIndex] & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK;\r
*RegionAttributes = TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (PageAttributes, 0) |\r
TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttributes);\r
}\r
\r
- for (;TableIndex < TRANSLATION_TABLE_SECTION_COUNT; TableIndex++) {\r
+ for ( ; TableIndex < TRANSLATION_TABLE_SECTION_COUNT; TableIndex++) {\r
// Get the section at the given index\r
SectionDescriptor = FirstLevelTable[TableIndex];\r
\r
// If the entry is a level-2 page table then we scan it to find the end of the region\r
if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (SectionDescriptor)) {\r
// Extract the page table location from the descriptor\r
- PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);\r
+ PageTable = (UINT32 *)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);\r
\r
// Scan the page table to find the end of the region.\r
Status = GetMemoryRegionPage (PageTable, BaseAddress, RegionLength, RegionAttributes);\r
break;\r
}\r
} else if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) ||\r
- ((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION)) {\r
+ ((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION))\r
+ {\r
if ((SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK) != *RegionAttributes) {\r
// If the attributes of the section differ from the one targeted then we exit the loop\r
break;\r
\r
#include <Guid/IdleLoopEvent.h>\r
\r
-BOOLEAN mIsFlushingGCD;\r
+BOOLEAN mIsFlushingGCD;\r
\r
/**\r
This function flushes the range of addresses from Start to Start+Length\r
EFI_STATUS\r
EFIAPI\r
CpuFlushCpuDataCache (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- IN EFI_PHYSICAL_ADDRESS Start,\r
- IN UINT64 Length,\r
- IN EFI_CPU_FLUSH_TYPE FlushType\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS Start,\r
+ IN UINT64 Length,\r
+ IN EFI_CPU_FLUSH_TYPE FlushType\r
)\r
{\r
-\r
switch (FlushType) {\r
case EfiCpuFlushTypeWriteBack:\r
WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
This function enables interrupt processing by the processor.\r
\r
EFI_STATUS\r
EFIAPI\r
CpuEnableInterrupt (\r
- IN EFI_CPU_ARCH_PROTOCOL *This\r
+ IN EFI_CPU_ARCH_PROTOCOL *This\r
)\r
{\r
ArmEnableInterrupts ();\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
This function disables interrupt processing by the processor.\r
\r
EFI_STATUS\r
EFIAPI\r
CpuDisableInterrupt (\r
- IN EFI_CPU_ARCH_PROTOCOL *This\r
+ IN EFI_CPU_ARCH_PROTOCOL *This\r
)\r
{\r
ArmDisableInterrupts ();\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
This function retrieves the processor's current interrupt state a returns it in\r
State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r
EFI_STATUS\r
EFIAPI\r
CpuGetInterruptState (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- OUT BOOLEAN *State\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ OUT BOOLEAN *State\r
)\r
{\r
if (State == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- *State = ArmGetInterruptState();\r
+ *State = ArmGetInterruptState ();\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
This function generates an INIT on the processor. If this function succeeds, then the\r
processor will be reset, and control will not be returned to the caller. If InitType is\r
EFI_STATUS\r
EFIAPI\r
CpuInit (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- IN EFI_CPU_INIT_TYPE InitType\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_CPU_INIT_TYPE InitType\r
)\r
{\r
return EFI_UNSUPPORTED;\r
EFI_STATUS\r
EFIAPI\r
CpuRegisterInterruptHandler (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- IN EFI_EXCEPTION_TYPE InterruptType,\r
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
)\r
{\r
return RegisterInterruptHandler (InterruptType, InterruptHandler);\r
EFI_STATUS\r
EFIAPI\r
CpuGetTimerValue (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- IN UINT32 TimerIndex,\r
- OUT UINT64 *TimerValue,\r
- OUT UINT64 *TimerPeriod OPTIONAL\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN UINT32 TimerIndex,\r
+ OUT UINT64 *TimerValue,\r
+ OUT UINT64 *TimerPeriod OPTIONAL\r
)\r
{\r
return EFI_UNSUPPORTED;\r
VOID\r
EFIAPI\r
IdleLoopEventCallback (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
)\r
{\r
CpuSleep ();\r
//\r
// Globals used to initialize the protocol\r
//\r
-EFI_HANDLE mCpuHandle = NULL;\r
-EFI_CPU_ARCH_PROTOCOL mCpu = {\r
+EFI_HANDLE mCpuHandle = NULL;\r
+EFI_CPU_ARCH_PROTOCOL mCpu = {\r
CpuFlushCpuDataCache,\r
CpuEnableInterrupt,\r
CpuDisableInterrupt,\r
STATIC\r
VOID\r
InitializeDma (\r
- IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol\r
+ IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol\r
)\r
{\r
CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();\r
\r
EFI_STATUS\r
CpuDxeInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
EFI_STATUS Status;\r
- EFI_EVENT IdleLoopEvent;\r
+ EFI_EVENT IdleLoopEvent;\r
\r
InitializeExceptions (&mCpu);\r
\r
InitializeDma (&mCpu);\r
\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
- &mCpuHandle,\r
- &gEfiCpuArchProtocolGuid, &mCpu,\r
- NULL\r
- );\r
+ &mCpuHandle,\r
+ &gEfiCpuArchProtocolGuid,\r
+ &mCpu,\r
+ NULL\r
+ );\r
\r
//\r
// Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()\r
\r
// If the platform is a MPCore system then install the Configuration Table describing the\r
// secondary core states\r
- if (ArmIsMpCore()) {\r
- PublishArmProcessorTable();\r
+ if (ArmIsMpCore ()) {\r
+ PublishArmProcessorTable ();\r
}\r
\r
//\r
#include <Protocol/DebugSupport.h>\r
#include <Protocol/LoadedImage.h>\r
\r
-extern BOOLEAN mIsFlushingGCD;\r
+extern BOOLEAN mIsFlushingGCD;\r
\r
/**\r
This function registers and enables the handler specified by InterruptHandler for a processor\r
**/\r
EFI_STATUS\r
RegisterInterruptHandler (\r
- IN EFI_EXCEPTION_TYPE InterruptType,\r
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
);\r
\r
-\r
/**\r
This function registers and enables the handler specified by InterruptHandler for a processor\r
interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the\r
**/\r
EFI_STATUS\r
RegisterDebuggerInterruptHandler (\r
- IN EFI_EXCEPTION_TYPE InterruptType,\r
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
);\r
\r
-\r
EFI_STATUS\r
EFIAPI\r
CpuSetMemoryAttributes (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
);\r
\r
EFI_STATUS\r
InitializeExceptions (\r
- IN EFI_CPU_ARCH_PROTOCOL *Cpu\r
+ IN EFI_CPU_ARCH_PROTOCOL *Cpu\r
);\r
\r
EFI_STATUS\r
SyncCacheConfig (\r
- IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
+ IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
);\r
\r
/**\r
**/\r
VOID\r
EFIAPI\r
-PublishArmProcessorTable(\r
+PublishArmProcessorTable (\r
VOID\r
);\r
\r
// The ARM Attributes might be defined on 64-bit (case of the long format description table)\r
UINT64\r
EfiAttributeToArmAttribute (\r
- IN UINT64 EfiAttributes\r
+ IN UINT64 EfiAttributes\r
);\r
\r
EFI_STATUS\r
GetMemoryRegion (\r
- IN OUT UINTN *BaseAddress,\r
- OUT UINTN *RegionLength,\r
- OUT UINTN *RegionAttributes\r
+ IN OUT UINTN *BaseAddress,\r
+ OUT UINTN *RegionLength,\r
+ OUT UINTN *RegionAttributes\r
);\r
\r
EFI_STATUS\r
SetGcdMemorySpaceAttributes (\r
- IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
- IN UINTN NumberOfDescriptors,\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes\r
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
+ IN UINTN NumberOfDescriptors,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
);\r
\r
#endif // CPU_DXE_H_\r
**/\r
EFI_STATUS\r
SearchGcdMemorySpaces (\r
- IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
- IN UINTN NumberOfDescriptors,\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- OUT UINTN *StartIndex,\r
- OUT UINTN *EndIndex\r
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
+ IN UINTN NumberOfDescriptors,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ OUT UINTN *StartIndex,\r
+ OUT UINTN *EndIndex\r
)\r
{\r
- UINTN Index;\r
+ UINTN Index;\r
\r
*StartIndex = 0;\r
*EndIndex = 0;\r
for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) &&\r
- (BaseAddress < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) {\r
+ (BaseAddress < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)))\r
+ {\r
*StartIndex = Index;\r
}\r
+\r
if (((BaseAddress + Length - 1) >= MemorySpaceMap[Index].BaseAddress) &&\r
- ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) {\r
+ ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)))\r
+ {\r
*EndIndex = Index;\r
return EFI_SUCCESS;\r
}\r
}\r
+\r
return EFI_NOT_FOUND;\r
}\r
\r
-\r
/**\r
Sets the attributes for a specified range in Gcd Memory Space Map.\r
\r
**/\r
EFI_STATUS\r
SetGcdMemorySpaceAttributes (\r
- IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
- IN UINTN NumberOfDescriptors,\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes\r
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
+ IN UINTN NumberOfDescriptors,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
)\r
{\r
EFI_STATUS Status;\r
EFI_PHYSICAL_ADDRESS RegionStart;\r
UINT64 RegionLength;\r
\r
- DEBUG ((DEBUG_GCD, "SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n",\r
- BaseAddress, BaseAddress + Length, Attributes));\r
+ DEBUG ((\r
+ DEBUG_GCD,\r
+ "SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n",\r
+ BaseAddress,\r
+ BaseAddress + Length,\r
+ Attributes\r
+ ));\r
\r
// We do not support a smaller granularity than 4KB on ARM Architecture\r
if ((Length & EFI_PAGE_MASK) != 0) {\r
- DEBUG ((DEBUG_WARN,\r
- "Warning: We do not support smaller granularity than 4KB on ARM Architecture (passed length: 0x%lX).\n",\r
- Length));\r
+ DEBUG ((\r
+ DEBUG_WARN,\r
+ "Warning: We do not support smaller granularity than 4KB on ARM Architecture (passed length: 0x%lX).\n",\r
+ Length\r
+ ));\r
}\r
\r
//\r
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
continue;\r
}\r
+\r
//\r
// Calculate the start and end address of the overlapping range\r
//\r
} else {\r
RegionStart = MemorySpaceMap[Index].BaseAddress;\r
}\r
+\r
if ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)) {\r
RegionLength = BaseAddress + Length - RegionStart;\r
} else {\r
RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r
}\r
+\r
//\r
// Set memory attributes according to MTRR attribute and the original attribute of descriptor\r
//\r
EFI_STATUS\r
EFIAPI\r
CpuSetMemoryAttributes (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 EfiAttributes\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 EfiAttributes\r
)\r
{\r
EFI_STATUS Status;\r
\r
// Get the region starting from 'BaseAddress' and its 'Attribute'\r
RegionBaseAddress = BaseAddress;\r
- Status = GetMemoryRegion (&RegionBaseAddress, &RegionLength, &RegionArmAttributes);\r
+ Status = GetMemoryRegion (&RegionBaseAddress, &RegionLength, &RegionArmAttributes);\r
\r
// Data & Instruction Caches are flushed when we set new memory attributes.\r
// So, we only set the attributes if the new region is different.\r
\r
#include <Guid/ArmMpCoreInfo.h>\r
\r
-ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {\r
+ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {\r
{\r
EFI_ARM_PROCESSOR_TABLE_SIGNATURE,\r
0,\r
EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION,\r
{ 0 },\r
0\r
- }, //ARM Processor table header\r
+ }, // ARM Processor table header\r
0, // Number of entries in ARM processor Table\r
NULL // ARM Processor Table\r
};\r
VOID\r
)\r
{\r
- EFI_PEI_HOB_POINTERS Hob;\r
+ EFI_PEI_HOB_POINTERS Hob;\r
\r
Hob.Raw = GetHobList ();\r
\r
// Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB\r
- for (; !END_OF_HOB_LIST(Hob); Hob.Raw = GET_NEXT_HOB(Hob)) {\r
+ for ( ; !END_OF_HOB_LIST (Hob); Hob.Raw = GET_NEXT_HOB (Hob)) {\r
// Check for Correct HOB type\r
if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) {\r
// Check for correct GUID type\r
- if (CompareGuid(&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) {\r
- ARM_PROCESSOR_TABLE *ArmProcessorTable;\r
- EFI_STATUS Status;\r
+ if (CompareGuid (&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) {\r
+ ARM_PROCESSOR_TABLE *ArmProcessorTable;\r
+ EFI_STATUS Status;\r
\r
// Allocate Runtime memory for ARM processor table\r
- ArmProcessorTable = (ARM_PROCESSOR_TABLE*)AllocateRuntimePool(sizeof(ARM_PROCESSOR_TABLE));\r
+ ArmProcessorTable = (ARM_PROCESSOR_TABLE *)AllocateRuntimePool (sizeof (ARM_PROCESSOR_TABLE));\r
\r
// Check if the memory allocation is successful or not\r
- ASSERT(NULL != ArmProcessorTable);\r
+ ASSERT (NULL != ArmProcessorTable);\r
\r
// Set ARM processor table to default values\r
- CopyMem(ArmProcessorTable,&mArmProcessorTableTemplate,sizeof(ARM_PROCESSOR_TABLE));\r
+ CopyMem (ArmProcessorTable, &mArmProcessorTableTemplate, sizeof (ARM_PROCESSOR_TABLE));\r
\r
// Fill in Length fields of ARM processor table\r
- ArmProcessorTable->Header.Length = sizeof(ARM_PROCESSOR_TABLE);\r
- ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE(Hob);\r
+ ArmProcessorTable->Header.Length = sizeof (ARM_PROCESSOR_TABLE);\r
+ ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE (Hob);\r
\r
// Fill in Identifier(ARM processor table GUID)\r
ArmProcessorTable->Header.Identifier = gArmMpCoreInfoGuid;\r
\r
// Set Number of ARM core entries in the Table\r
- ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE(Hob)/sizeof(ARM_CORE_INFO);\r
+ ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE (Hob)/sizeof (ARM_CORE_INFO);\r
\r
// Allocate runtime memory for ARM processor Table entries\r
- ArmProcessorTable->ArmCpus = (ARM_CORE_INFO*)AllocateRuntimePool (\r
- ArmProcessorTable->NumberOfEntries * sizeof(ARM_CORE_INFO));\r
+ ArmProcessorTable->ArmCpus = (ARM_CORE_INFO *)AllocateRuntimePool (\r
+ ArmProcessorTable->NumberOfEntries * sizeof (ARM_CORE_INFO)\r
+ );\r
\r
// Check if the memory allocation is successful or not\r
- ASSERT(NULL != ArmProcessorTable->ArmCpus);\r
+ ASSERT (NULL != ArmProcessorTable->ArmCpus);\r
\r
// Copy ARM Processor Table data from HOB list to newly allocated memory\r
- CopyMem(ArmProcessorTable->ArmCpus,GET_GUID_HOB_DATA(Hob), ArmProcessorTable->Header.DataLen);\r
+ CopyMem (ArmProcessorTable->ArmCpus, GET_GUID_HOB_DATA (Hob), ArmProcessorTable->Header.DataLen);\r
\r
// Install the ARM Processor table into EFI system configuration table\r
Status = gBS->InstallConfigurationTable (&gArmMpCoreInfoGuid, ArmProcessorTable);\r
\r
EFI_STATUS\r
InitializeExceptions (\r
- IN EFI_CPU_ARCH_PROTOCOL *Cpu\r
+ IN EFI_CPU_ARCH_PROTOCOL *Cpu\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_VECTOR_HANDOFF_INFO *VectorInfoList;\r
- EFI_VECTOR_HANDOFF_INFO *VectorInfo;\r
- BOOLEAN IrqEnabled;\r
- BOOLEAN FiqEnabled;\r
+ EFI_STATUS Status;\r
+ EFI_VECTOR_HANDOFF_INFO *VectorInfoList;\r
+ EFI_VECTOR_HANDOFF_INFO *VectorInfo;\r
+ BOOLEAN IrqEnabled;\r
+ BOOLEAN FiqEnabled;\r
\r
VectorInfo = (EFI_VECTOR_HANDOFF_INFO *)NULL;\r
- Status = EfiGetSystemConfigurationTable(&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);\r
- if (Status == EFI_SUCCESS && VectorInfoList != NULL) {\r
+ Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);\r
+ if ((Status == EFI_SUCCESS) && (VectorInfoList != NULL)) {\r
VectorInfo = VectorInfoList;\r
}\r
\r
// initialize the CpuExceptionHandlerLib so we take over the exception vector table from the DXE Core\r
- InitializeCpuExceptionHandlers(VectorInfo);\r
+ InitializeCpuExceptionHandlers (VectorInfo);\r
\r
Status = EFI_SUCCESS;\r
\r
//\r
DEBUG_CODE (\r
ArmEnableAsynchronousAbort ();\r
- );\r
+ );\r
\r
return Status;\r
}\r
\r
**/\r
EFI_STATUS\r
-RegisterInterruptHandler(\r
- IN EFI_EXCEPTION_TYPE InterruptType,\r
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
+RegisterInterruptHandler (\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
)\r
{\r
// pass down to CpuExceptionHandlerLib\r
- return (EFI_STATUS)RegisterCpuInterruptHandler(InterruptType, InterruptHandler);\r
+ return (EFI_STATUS)RegisterCpuInterruptHandler (InterruptType, InterruptHandler);\r
}\r
\r
**/\r
\r
-\r
-\r
//\r
// The package level header files this module uses\r
//\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- EFI_STATUS Status;\r
- ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r
- UINTN ArmCoreCount;\r
- ARM_CORE_INFO *ArmCoreInfoTable;\r
+ EFI_STATUS Status;\r
+ ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r
+ UINTN ArmCoreCount;\r
+ ARM_CORE_INFO *ArmCoreInfoTable;\r
\r
// Enable program flow prediction, if supported.\r
ArmEnableBranchPrediction ();\r
BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));\r
\r
// Only MP Core platform need to produce gArmMpCoreInfoPpiGuid\r
- Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID**)&ArmMpCoreInfoPpi);\r
- if (!EFI_ERROR(Status)) {\r
+ Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID **)&ArmMpCoreInfoPpi);\r
+ if (!EFI_ERROR (Status)) {\r
// Build the MP Core Info Table\r
ArmCoreCount = 0;\r
- Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
- if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {\r
+ Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
+ if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) {\r
// Build MPCore Info HOB\r
BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);\r
}\r
* SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
+\r
#ifndef GENERIC_WATCHDOG_H_\r
#define GENERIC_WATCHDOG_H_\r
\r
// Refresh Frame:\r
-#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)\r
+#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)\r
\r
// Control Frame:\r
-#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000)\r
-#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008)\r
-#define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)\r
-#define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014)\r
+#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000)\r
+#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008)\r
+#define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)\r
+#define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014)\r
\r
// Values of bit 0 of the Control/Status Register\r
-#define GENERIC_WDOG_ENABLED 1\r
-#define GENERIC_WDOG_DISABLED 0\r
+#define GENERIC_WDOG_ENABLED 1\r
+#define GENERIC_WDOG_DISABLED 0\r
\r
-#endif // GENERIC_WATCHDOG_H_\r
+#endif // GENERIC_WATCHDOG_H_\r
\r
/* The number of 100ns periods (the unit of time passed to these functions)\r
in a second */\r
-#define TIME_UNITS_PER_SECOND 10000000\r
+#define TIME_UNITS_PER_SECOND 10000000\r
\r
// Tick frequency of the generic timer basis of the generic watchdog.\r
-STATIC UINTN mTimerFrequencyHz = 0;\r
+STATIC UINTN mTimerFrequencyHz = 0;\r
\r
/* In cases where the compare register was set manually, information about\r
how long the watchdog was asked to wait cannot be retrieved from hardware.\r
It is therefore stored here. 0 means the timer is not running. */\r
-STATIC UINT64 mNumTimerTicks = 0;\r
+STATIC UINT64 mNumTimerTicks = 0;\r
\r
-STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol;\r
-STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;\r
+STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol;\r
+STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;\r
\r
STATIC\r
VOID\r
VOID\r
EFIAPI\r
WatchdogInterruptHandler (\r
- IN HARDWARE_INTERRUPT_SOURCE Source,\r
- IN EFI_SYSTEM_CONTEXT SystemContext\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ IN EFI_SYSTEM_CONTEXT SystemContext\r
)\r
{\r
- STATIC CONST CHAR16 ResetString[]= L"The generic watchdog timer ran out.";\r
- UINT64 TimerPeriod;\r
+ STATIC CONST CHAR16 ResetString[] = L"The generic watchdog timer ran out.";\r
+ UINT64 TimerPeriod;\r
\r
WatchdogDisable ();\r
\r
mWatchdogNotify (TimerPeriod + 1);\r
}\r
\r
- gRT->ResetSystem (EfiResetCold, EFI_TIMEOUT, StrSize (ResetString),\r
- (CHAR16 *)ResetString);\r
+ gRT->ResetSystem (\r
+ EfiResetCold,\r
+ EFI_TIMEOUT,\r
+ StrSize (ResetString),\r
+ (CHAR16 *)ResetString\r
+ );\r
\r
// If we got here then the reset didn't work\r
ASSERT (FALSE);\r
EFI_STATUS\r
EFIAPI\r
WatchdogRegisterHandler (\r
- IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,\r
- IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction\r
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,\r
+ IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction\r
)\r
{\r
- if (mWatchdogNotify == NULL && NotifyFunction == NULL) {\r
+ if ((mWatchdogNotify == NULL) && (NotifyFunction == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- if (mWatchdogNotify != NULL && NotifyFunction != NULL) {\r
+ if ((mWatchdogNotify != NULL) && (NotifyFunction != NULL)) {\r
return EFI_ALREADY_STARTED;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
WatchdogSetTimerPeriod (\r
- IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,\r
- IN UINT64 TimerPeriod // In 100ns units\r
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,\r
+ IN UINT64 TimerPeriod // In 100ns units\r
)\r
{\r
- UINTN SystemCount;\r
+ UINTN SystemCount;\r
\r
// if TimerPeriod is 0, this is a request to stop the watchdog.\r
if (TimerPeriod == 0) {\r
EFI_STATUS\r
EFIAPI\r
WatchdogGetTimerPeriod (\r
- IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,\r
- OUT UINT64 *TimerPeriod\r
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,\r
+ OUT UINT64 *TimerPeriod\r
)\r
{\r
if (TimerPeriod == NULL) {\r
Retrieves the period of the timer interrupt in 100ns units.\r
\r
**/\r
-STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = {\r
+STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = {\r
WatchdogRegisterHandler,\r
WatchdogSetTimerPeriod,\r
WatchdogGetTimerPeriod\r
};\r
\r
-STATIC EFI_EVENT mEfiExitBootServicesEvent;\r
+STATIC EFI_EVENT mEfiExitBootServicesEvent;\r
\r
EFI_STATUS\r
EFIAPI\r
GenericWatchdogEntry (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_HANDLE Handle;\r
-\r
- Status = gBS->LocateProtocol (&gHardwareInterrupt2ProtocolGuid, NULL,\r
- (VOID **)&mInterruptProtocol);\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE Handle;\r
+\r
+ Status = gBS->LocateProtocol (\r
+ &gHardwareInterrupt2ProtocolGuid,\r
+ NULL,\r
+ (VOID **)&mInterruptProtocol\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
\r
/* Make sure the Watchdog Timer Architectural Protocol has not been installed\r
ASSERT (mTimerFrequencyHz != 0);\r
\r
// Install interrupt handler\r
- Status = mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol,\r
+ Status = mInterruptProtocol->RegisterInterruptSource (\r
+ mInterruptProtocol,\r
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),\r
- WatchdogInterruptHandler);\r
+ WatchdogInterruptHandler\r
+ );\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- Status = mInterruptProtocol->SetTriggerType (mInterruptProtocol,\r
+ Status = mInterruptProtocol->SetTriggerType (\r
+ mInterruptProtocol,\r
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),\r
- EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING);\r
+ EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING\r
+ );\r
if (EFI_ERROR (Status)) {\r
goto UnregisterHandler;\r
}\r
\r
// Install the Timer Architectural Protocol onto a new handle\r
Handle = NULL;\r
- Status = gBS->InstallMultipleProtocolInterfaces (&Handle,\r
- &gEfiWatchdogTimerArchProtocolGuid, &mWatchdogTimer,\r
- NULL);\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &Handle,\r
+ &gEfiWatchdogTimerArchProtocolGuid,\r
+ &mWatchdogTimer,\r
+ NULL\r
+ );\r
if (EFI_ERROR (Status)) {\r
goto UnregisterHandler;\r
}\r
\r
// Register for an ExitBootServicesEvent\r
- Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,\r
- WatchdogExitBootServicesEvent, NULL,\r
- &mEfiExitBootServicesEvent);\r
+ Status = gBS->CreateEvent (\r
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,\r
+ TPL_NOTIFY,\r
+ WatchdogExitBootServicesEvent,\r
+ NULL,\r
+ &mEfiExitBootServicesEvent\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
\r
mNumTimerTicks = 0;\r
\r
UnregisterHandler:\r
// Unregister the handler\r
- mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol,\r
+ mInterruptProtocol->RegisterInterruptSource (\r
+ mInterruptProtocol,\r
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),\r
- NULL);\r
+ NULL\r
+ );\r
return Status;\r
}\r
#ifndef MM_COMMUNICATE_H_\r
#define MM_COMMUNICATE_H_\r
\r
-#define MM_MAJOR_VER_MASK 0xEFFF0000\r
-#define MM_MINOR_VER_MASK 0x0000FFFF\r
-#define MM_MAJOR_VER_SHIFT 16\r
+#define MM_MAJOR_VER_MASK 0xEFFF0000\r
+#define MM_MINOR_VER_MASK 0x0000FFFF\r
+#define MM_MAJOR_VER_SHIFT 16\r
\r
-#define MM_MAJOR_VER(x) (((x) & MM_MAJOR_VER_MASK) >> MM_MAJOR_VER_SHIFT)\r
-#define MM_MINOR_VER(x) ((x) & MM_MINOR_VER_MASK)\r
+#define MM_MAJOR_VER(x) (((x) & MM_MAJOR_VER_MASK) >> MM_MAJOR_VER_SHIFT)\r
+#define MM_MINOR_VER(x) ((x) & MM_MINOR_VER_MASK)\r
\r
-#define MM_CALLER_MAJOR_VER 0x1UL\r
-#define MM_CALLER_MINOR_VER 0x0\r
+#define MM_CALLER_MAJOR_VER 0x1UL\r
+#define MM_CALLER_MINOR_VER 0x0\r
\r
#endif /* MM_COMMUNICATE_H_ */\r
EFI_STATUS\r
EFIAPI\r
MmCommunication2Communicate (\r
- IN CONST EFI_MM_COMMUNICATION2_PROTOCOL *This,\r
- IN OUT VOID *CommBufferPhysical,\r
- IN OUT VOID *CommBufferVirtual,\r
- IN OUT UINTN *CommSize OPTIONAL\r
+ IN CONST EFI_MM_COMMUNICATION2_PROTOCOL *This,\r
+ IN OUT VOID *CommBufferPhysical,\r
+ IN OUT VOID *CommBufferVirtual,\r
+ IN OUT UINTN *CommSize OPTIONAL\r
)\r
{\r
- EFI_MM_COMMUNICATE_HEADER *CommunicateHeader;\r
- ARM_SMC_ARGS CommunicateSmcArgs;\r
- EFI_STATUS Status;\r
- UINTN BufferSize;\r
+ EFI_MM_COMMUNICATE_HEADER *CommunicateHeader;\r
+ ARM_SMC_ARGS CommunicateSmcArgs;\r
+ EFI_STATUS Status;\r
+ UINTN BufferSize;\r
\r
- Status = EFI_ACCESS_DENIED;\r
+ Status = EFI_ACCESS_DENIED;\r
BufferSize = 0;\r
\r
ZeroMem (&CommunicateSmcArgs, sizeof (ARM_SMC_ARGS));\r
// This case can be used by the consumer of this driver to find out the\r
// max size that can be used for allocating CommBuffer.\r
if ((*CommSize == 0) ||\r
- (*CommSize > mNsCommBuffMemRegion.Length)) {\r
+ (*CommSize > mNsCommBuffMemRegion.Length))\r
+ {\r
*CommSize = mNsCommBuffMemRegion.Length;\r
return EFI_BAD_BUFFER_SIZE;\r
}\r
+\r
//\r
// CommSize must match MessageLength + sizeof (EFI_MM_COMMUNICATE_HEADER);\r
//\r
if (*CommSize != BufferSize) {\r
- return EFI_INVALID_PARAMETER;\r
+ return EFI_INVALID_PARAMETER;\r
}\r
}\r
\r
// environment then return the expected size.\r
//\r
if ((BufferSize == 0) ||\r
- (BufferSize > mNsCommBuffMemRegion.Length)) {\r
+ (BufferSize > mNsCommBuffMemRegion.Length))\r
+ {\r
CommunicateHeader->MessageLength = mNsCommBuffMemRegion.Length -\r
sizeof (CommunicateHeader->HeaderGuid) -\r
sizeof (CommunicateHeader->MessageLength);\r
ArmCallSmc (&CommunicateSmcArgs);\r
\r
switch (CommunicateSmcArgs.Arg0) {\r
- case ARM_SMC_MM_RET_SUCCESS:\r
- ZeroMem (CommBufferVirtual, BufferSize);\r
- // On successful return, the size of data being returned is inferred from\r
- // MessageLength + Header.\r
- CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase;\r
- BufferSize = CommunicateHeader->MessageLength +\r
- sizeof (CommunicateHeader->HeaderGuid) +\r
- sizeof (CommunicateHeader->MessageLength);\r
-\r
- CopyMem (\r
- CommBufferVirtual,\r
- (VOID *)mNsCommBuffMemRegion.VirtualBase,\r
- BufferSize\r
- );\r
- Status = EFI_SUCCESS;\r
- break;\r
-\r
- case ARM_SMC_MM_RET_INVALID_PARAMS:\r
- Status = EFI_INVALID_PARAMETER;\r
- break;\r
-\r
- case ARM_SMC_MM_RET_DENIED:\r
- Status = EFI_ACCESS_DENIED;\r
- break;\r
-\r
- case ARM_SMC_MM_RET_NO_MEMORY:\r
- // Unexpected error since the CommSize was checked for zero length\r
- // prior to issuing the SMC\r
- Status = EFI_OUT_OF_RESOURCES;\r
- ASSERT (0);\r
- break;\r
-\r
- default:\r
- Status = EFI_ACCESS_DENIED;\r
- ASSERT (0);\r
+ case ARM_SMC_MM_RET_SUCCESS:\r
+ ZeroMem (CommBufferVirtual, BufferSize);\r
+ // On successful return, the size of data being returned is inferred from\r
+ // MessageLength + Header.\r
+ CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase;\r
+ BufferSize = CommunicateHeader->MessageLength +\r
+ sizeof (CommunicateHeader->HeaderGuid) +\r
+ sizeof (CommunicateHeader->MessageLength);\r
+\r
+ CopyMem (\r
+ CommBufferVirtual,\r
+ (VOID *)mNsCommBuffMemRegion.VirtualBase,\r
+ BufferSize\r
+ );\r
+ Status = EFI_SUCCESS;\r
+ break;\r
+\r
+ case ARM_SMC_MM_RET_INVALID_PARAMS:\r
+ Status = EFI_INVALID_PARAMETER;\r
+ break;\r
+\r
+ case ARM_SMC_MM_RET_DENIED:\r
+ Status = EFI_ACCESS_DENIED;\r
+ break;\r
+\r
+ case ARM_SMC_MM_RET_NO_MEMORY:\r
+ // Unexpected error since the CommSize was checked for zero length\r
+ // prior to issuing the SMC\r
+ Status = EFI_OUT_OF_RESOURCES;\r
+ ASSERT (0);\r
+ break;\r
+\r
+ default:\r
+ Status = EFI_ACCESS_DENIED;\r
+ ASSERT (0);\r
}\r
\r
return Status;\r
EFIAPI\r
NotifySetVirtualAddressMap (\r
IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN VOID *Context\r
)\r
{\r
EFI_STATUS Status;\r
(VOID **)&mNsCommBuffMemRegion.VirtualBase\r
);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "NotifySetVirtualAddressMap():"\r
- " Unable to convert MM runtime pointer. Status:0x%r\n", Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "NotifySetVirtualAddressMap():"\r
+ " Unable to convert MM runtime pointer. Status:0x%r\n",\r
+ Status\r
+ ));\r
}\r
-\r
}\r
\r
STATIC\r
EFI_STATUS\r
-GetMmCompatibility ()\r
+GetMmCompatibility (\r
+ )\r
{\r
- EFI_STATUS Status;\r
- UINT32 MmVersion;\r
- ARM_SMC_ARGS MmVersionArgs;\r
+ EFI_STATUS Status;\r
+ UINT32 MmVersion;\r
+ ARM_SMC_ARGS MmVersionArgs;\r
\r
// MM_VERSION uses SMC32 calling conventions\r
MmVersionArgs.Arg0 = ARM_SMC_ID_MM_VERSION_AARCH32;\r
\r
MmVersion = MmVersionArgs.Arg0;\r
\r
- if ((MM_MAJOR_VER(MmVersion) == MM_CALLER_MAJOR_VER) &&\r
- (MM_MINOR_VER(MmVersion) >= MM_CALLER_MINOR_VER)) {\r
- DEBUG ((DEBUG_INFO, "MM Version: Major=0x%x, Minor=0x%x\n",\r
- MM_MAJOR_VER(MmVersion), MM_MINOR_VER(MmVersion)));\r
+ if ((MM_MAJOR_VER (MmVersion) == MM_CALLER_MAJOR_VER) &&\r
+ (MM_MINOR_VER (MmVersion) >= MM_CALLER_MINOR_VER))\r
+ {\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "MM Version: Major=0x%x, Minor=0x%x\n",\r
+ MM_MAJOR_VER (MmVersion),\r
+ MM_MINOR_VER (MmVersion)\r
+ ));\r
Status = EFI_SUCCESS;\r
} else {\r
- DEBUG ((DEBUG_ERROR, "Incompatible MM Versions.\n Current Version: Major=0x%x, Minor=0x%x.\n Expected: Major=0x%x, Minor>=0x%x.\n",\r
- MM_MAJOR_VER(MmVersion), MM_MINOR_VER(MmVersion), MM_CALLER_MAJOR_VER, MM_CALLER_MINOR_VER));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "Incompatible MM Versions.\n Current Version: Major=0x%x, Minor=0x%x.\n Expected: Major=0x%x, Minor>=0x%x.\n",\r
+ MM_MAJOR_VER (MmVersion),\r
+ MM_MINOR_VER (MmVersion),\r
+ MM_CALLER_MAJOR_VER,\r
+ MM_CALLER_MINOR_VER\r
+ ));\r
Status = EFI_UNSUPPORTED;\r
}\r
\r
return Status;\r
}\r
\r
-STATIC EFI_GUID* CONST mGuidedEventGuid[] = {\r
+STATIC EFI_GUID *CONST mGuidedEventGuid[] = {\r
&gEfiEndOfDxeEventGroupGuid,\r
&gEfiEventExitBootServicesGuid,\r
&gEfiEventReadyToBootGuid,\r
};\r
\r
-STATIC EFI_EVENT mGuidedEvent[ARRAY_SIZE (mGuidedEventGuid)];\r
+STATIC EFI_EVENT mGuidedEvent[ARRAY_SIZE (mGuidedEventGuid)];\r
\r
/**\r
Event notification that is fired when GUIDed Event Group is signaled.\r
IN VOID *Context\r
)\r
{\r
- EFI_MM_COMMUNICATE_HEADER Header;\r
- UINTN Size;\r
+ EFI_MM_COMMUNICATE_HEADER Header;\r
+ UINTN Size;\r
\r
//\r
// Use Guid to initialize EFI_SMM_COMMUNICATE_HEADER structure\r
//\r
CopyGuid (&Header.HeaderGuid, Context);\r
Header.MessageLength = 1;\r
- Header.Data[0] = 0;\r
+ Header.Data[0] = 0;\r
\r
Size = sizeof (Header);\r
MmCommunication2Communicate (&mMmCommunication2, &Header, &Header, &Size);\r
EFI_STATUS\r
EFIAPI\r
MmCommunication2Initialize (\r
- IN EFI_HANDLE ImageHandle,\r
+ IN EFI_HANDLE ImageHandle,\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
\r
// Check if we can make the MM call\r
Status = GetMmCompatibility ();\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
goto ReturnErrorStatus;\r
}\r
\r
mNsCommBuffMemRegion.PhysicalBase = PcdGet64 (PcdMmBufferBase);\r
// During boot , Virtual and Physical are same\r
mNsCommBuffMemRegion.VirtualBase = mNsCommBuffMemRegion.PhysicalBase;\r
- mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize);\r
+ mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize);\r
\r
ASSERT (mNsCommBuffMemRegion.PhysicalBase != 0);\r
\r
EFI_MEMORY_RUNTIME\r
);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "MmCommunicateInitialize: "\r
- "Failed to add MM-NS Buffer Memory Space\n"));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "MmCommunicateInitialize: "\r
+ "Failed to add MM-NS Buffer Memory Space\n"\r
+ ));\r
goto ReturnErrorStatus;\r
}\r
\r
EFI_MEMORY_WB | EFI_MEMORY_XP | EFI_MEMORY_RUNTIME\r
);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "MmCommunicateInitialize: "\r
- "Failed to set MM-NS Buffer Memory attributes\n"));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "MmCommunicateInitialize: "\r
+ "Failed to set MM-NS Buffer Memory attributes\n"\r
+ ));\r
goto CleanAddedMemorySpace;\r
}\r
\r
EFI_NATIVE_INTERFACE,\r
&mMmCommunication2\r
);\r
- if (EFI_ERROR(Status)) {\r
- DEBUG ((DEBUG_ERROR, "MmCommunicationInitialize: "\r
- "Failed to install MM communication protocol\n"));\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "MmCommunicationInitialize: "\r
+ "Failed to install MM communication protocol\n"\r
+ ));\r
goto CleanAddedMemorySpace;\r
}\r
\r
ASSERT_EFI_ERROR (Status);\r
\r
for (Index = 0; Index < ARRAY_SIZE (mGuidedEventGuid); Index++) {\r
- Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,\r
- MmGuidedEventNotify, mGuidedEventGuid[Index],\r
- mGuidedEventGuid[Index], &mGuidedEvent[Index]);\r
+ Status = gBS->CreateEventEx (\r
+ EVT_NOTIFY_SIGNAL,\r
+ TPL_CALLBACK,\r
+ MmGuidedEventNotify,\r
+ mGuidedEventGuid[Index],\r
+ mGuidedEventGuid[Index],\r
+ &mGuidedEvent[Index]\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
if (EFI_ERROR (Status)) {\r
while (Index-- > 0) {\r
gBS->CloseEvent (mGuidedEvent[Index]);\r
}\r
+\r
goto UninstallProtocol;\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
\r
UninstallProtocol:\r
\r
**/\r
\r
-\r
#include <PiDxe.h>\r
\r
#include <Library/ArmLib.h>\r
#include <Protocol/HardwareInterrupt.h>\r
\r
// The notification function to call on every timer interrupt.\r
-EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;\r
-EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
+EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;\r
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
\r
// The current period of the timer interrupt\r
-UINT64 mTimerPeriod = 0;\r
+UINT64 mTimerPeriod = 0;\r
// The latest Timer Tick calculated for mTimerPeriod\r
-UINT64 mTimerTicks = 0;\r
+UINT64 mTimerTicks = 0;\r
// Number of elapsed period since the last Timer interrupt\r
-UINT64 mElapsedPeriod = 1;\r
+UINT64 mElapsedPeriod = 1;\r
\r
// Cached copy of the Hardware Interrupt protocol instance\r
-EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;\r
+EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;\r
\r
/**\r
This function registers the handler NotifyFunction so it is called every time\r
IN UINT64 TimerPeriod\r
)\r
{\r
- UINT64 CounterValue;\r
- UINT64 TimerTicks;\r
- EFI_TPL OriginalTPL;\r
+ UINT64 CounterValue;\r
+ UINT64 TimerTicks;\r
+ EFI_TPL OriginalTPL;\r
\r
// Always disable the timer\r
ArmGenericTimerDisableTimer ();\r
ArmGenericTimerEnableTimer ();\r
} else {\r
// Save the new timer period\r
- mTimerPeriod = TimerPeriod;\r
+ mTimerPeriod = TimerPeriod;\r
// Reset the elapsed period\r
mElapsedPeriod = 1;\r
}\r
EFI_STATUS\r
EFIAPI\r
TimerDriverGetTimerPeriod (\r
- IN EFI_TIMER_ARCH_PROTOCOL *This,\r
- OUT UINT64 *TimerPeriod\r
+ IN EFI_TIMER_ARCH_PROTOCOL *This,\r
+ OUT UINT64 *TimerPeriod\r
)\r
{\r
if (TimerPeriod == NULL) {\r
a period of time.\r
\r
**/\r
-EFI_TIMER_ARCH_PROTOCOL gTimer = {\r
+EFI_TIMER_ARCH_PROTOCOL gTimer = {\r
TimerDriverRegisterHandler,\r
TimerDriverSetTimerPeriod,\r
TimerDriverGetTimerPeriod,\r
VOID\r
EFIAPI\r
TimerInterruptHandler (\r
- IN HARDWARE_INTERRUPT_SOURCE Source,\r
- IN EFI_SYSTEM_CONTEXT SystemContext\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ IN EFI_SYSTEM_CONTEXT SystemContext\r
)\r
{\r
- EFI_TPL OriginalTPL;\r
- UINT64 CurrentValue;\r
- UINT64 CompareValue;\r
+ EFI_TPL OriginalTPL;\r
+ UINT64 CurrentValue;\r
+ UINT64 CompareValue;\r
\r
//\r
// DXE core uses this callback for the EFI timer tick. The DXE core uses locks\r
gInterrupt->EndOfInterrupt (gInterrupt, Source);\r
\r
// Check if the timer interrupt is active\r
- if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {\r
-\r
+ if ((ArmGenericTimerGetTimerCtrlReg ()) & ARM_ARCH_TIMER_ISTATUS) {\r
if (mTimerNotifyFunction != 0) {\r
mTimerNotifyFunction (mTimerPeriod * mElapsedPeriod);\r
}\r
gBS->RestoreTPL (OriginalTPL);\r
}\r
\r
-\r
/**\r
Initialize the state information for the Timer Architectural Protocol and\r
the Timer Debug support protocol that allows the debugger to break into a\r
EFI_STATUS\r
EFIAPI\r
TimerInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
EFI_HANDLE Handle;\r
ASSERT_EFI_ERROR (Status);\r
\r
// Disable the timer\r
- TimerCtrlReg = ArmGenericTimerGetTimerCtrlReg ();\r
+ TimerCtrlReg = ArmGenericTimerGetTimerCtrlReg ();\r
TimerCtrlReg |= ARM_ARCH_TIMER_IMASK;\r
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;\r
ArmGenericTimerSetTimerCtrlReg (TimerCtrlReg);\r
ASSERT_EFI_ERROR (Status);\r
\r
// Set up default timer\r
- Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD\r
+ Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32 (PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD\r
ASSERT_EFI_ERROR (Status);\r
\r
Handle = NULL;\r
// Install the Timer Architectural Protocol onto a new handle\r
- Status = gBS->InstallMultipleProtocolInterfaces(\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
&Handle,\r
- &gEfiTimerArchProtocolGuid, &gTimer,\r
+ &gEfiTimerArchProtocolGuid,\r
+ &gTimer,\r
NULL\r
);\r
- ASSERT_EFI_ERROR(Status);\r
+ ASSERT_EFI_ERROR (Status);\r
\r
// Everything is ready, unmask and enable timer interrupts\r
TimerCtrlReg = ARM_ARCH_TIMER_ENABLE;\r
\r
#include "SemihostFs.h"\r
\r
-#define DEFAULT_SEMIHOST_FS_LABEL L"SemihostFs"\r
+#define DEFAULT_SEMIHOST_FS_LABEL L"SemihostFs"\r
\r
-STATIC CHAR16 *mSemihostFsLabel;\r
+STATIC CHAR16 *mSemihostFsLabel;\r
\r
-EFI_SIMPLE_FILE_SYSTEM_PROTOCOL gSemihostFs = {\r
+EFI_SIMPLE_FILE_SYSTEM_PROTOCOL gSemihostFs = {\r
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION,\r
VolumeOpen\r
};\r
\r
-EFI_FILE gSemihostFsFile = {\r
+EFI_FILE gSemihostFsFile = {\r
EFI_FILE_PROTOCOL_REVISION,\r
FileOpen,\r
FileClose,\r
// Device path for semi-hosting. It contains our auto-generated Caller ID GUID.\r
//\r
typedef struct {\r
- VENDOR_DEVICE_PATH Guid;\r
- EFI_DEVICE_PATH_PROTOCOL End;\r
+ VENDOR_DEVICE_PATH Guid;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
} SEMIHOST_DEVICE_PATH;\r
\r
-SEMIHOST_DEVICE_PATH gDevicePath = {\r
+SEMIHOST_DEVICE_PATH gDevicePath = {\r
{\r
- { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 } },\r
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 }\r
+ },\r
EFI_CALLER_ID_GUID\r
},\r
- { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } }\r
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }\r
+ }\r
};\r
\r
typedef struct {\r
- LIST_ENTRY Link;\r
- UINT64 Signature;\r
- EFI_FILE File;\r
- CHAR8 *FileName;\r
- UINT64 OpenMode;\r
- UINT32 Position;\r
- UINTN SemihostHandle;\r
- BOOLEAN IsRoot;\r
- EFI_FILE_INFO Info;\r
+ LIST_ENTRY Link;\r
+ UINT64 Signature;\r
+ EFI_FILE File;\r
+ CHAR8 *FileName;\r
+ UINT64 OpenMode;\r
+ UINT32 Position;\r
+ UINTN SemihostHandle;\r
+ BOOLEAN IsRoot;\r
+ EFI_FILE_INFO Info;\r
} SEMIHOST_FCB;\r
\r
-#define SEMIHOST_FCB_SIGNATURE SIGNATURE_32( 'S', 'H', 'F', 'C' )\r
-#define SEMIHOST_FCB_FROM_THIS(a) CR(a, SEMIHOST_FCB, File, SEMIHOST_FCB_SIGNATURE)\r
-#define SEMIHOST_FCB_FROM_LINK(a) CR(a, SEMIHOST_FCB, Link, SEMIHOST_FCB_SIGNATURE);\r
+#define SEMIHOST_FCB_SIGNATURE SIGNATURE_32( 'S', 'H', 'F', 'C' )\r
+#define SEMIHOST_FCB_FROM_THIS(a) CR(a, SEMIHOST_FCB, File, SEMIHOST_FCB_SIGNATURE)\r
+#define SEMIHOST_FCB_FROM_LINK(a) CR(a, SEMIHOST_FCB, Link, SEMIHOST_FCB_SIGNATURE);\r
\r
EFI_HANDLE gInstallHandle = NULL;\r
-LIST_ENTRY gFileList = INITIALIZE_LIST_HEAD_VARIABLE (gFileList);\r
+LIST_ENTRY gFileList = INITIALIZE_LIST_HEAD_VARIABLE (gFileList);\r
\r
SEMIHOST_FCB *\r
AllocateFCB (\r
VOID\r
)\r
{\r
- SEMIHOST_FCB *Fcb;\r
+ SEMIHOST_FCB *Fcb;\r
\r
Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB));\r
if (Fcb != NULL) {\r
\r
VOID\r
FreeFCB (\r
- IN SEMIHOST_FCB *Fcb\r
+ IN SEMIHOST_FCB *Fcb\r
)\r
{\r
// Remove Fcb from gFileList.\r
FreePool (Fcb);\r
}\r
\r
-\r
-\r
EFI_STATUS\r
VolumeOpen (\r
- IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,\r
- OUT EFI_FILE **Root\r
+ IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,\r
+ OUT EFI_FILE **Root\r
)\r
{\r
- SEMIHOST_FCB *RootFcb;\r
+ SEMIHOST_FCB *RootFcb;\r
\r
if (Root == NULL) {\r
return EFI_INVALID_PARAMETER;\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- RootFcb->IsRoot = TRUE;\r
+ RootFcb->IsRoot = TRUE;\r
RootFcb->Info.Attribute = EFI_FILE_READ_ONLY | EFI_FILE_DIRECTORY;\r
\r
InsertTailList (&gFileList, &RootFcb->Link);\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- if ( (OpenMode != EFI_FILE_MODE_READ) &&\r
- (OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE)) &&\r
- (OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE)) ) {\r
+ if ((OpenMode != EFI_FILE_MODE_READ) &&\r
+ (OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE)) &&\r
+ (OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE)))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
if (((OpenMode & EFI_FILE_MODE_CREATE) != 0) &&\r
- ((Attributes & EFI_FILE_DIRECTORY) != 0)) {\r
+ ((Attributes & EFI_FILE_DIRECTORY) != 0))\r
+ {\r
return EFI_WRITE_PROTECTED;\r
}\r
\r
- Length = StrLen (FileName) + 1;\r
+ Length = StrLen (FileName) + 1;\r
AsciiFileName = AllocatePool (Length);\r
if (AsciiFileName == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
UnicodeStrToAsciiStrS (FileName, AsciiFileName, Length);\r
\r
// Opening '/', '\', '.', or the NULL pathname is trying to open the root directory\r
if ((AsciiStrCmp (AsciiFileName, "\\") == 0) ||\r
(AsciiStrCmp (AsciiFileName, "/") == 0) ||\r
(AsciiStrCmp (AsciiFileName, "") == 0) ||\r
- (AsciiStrCmp (AsciiFileName, ".") == 0) ) {\r
+ (AsciiStrCmp (AsciiFileName, ".") == 0))\r
+ {\r
FreePool (AsciiFileName);\r
return (VolumeOpen (&gSemihostFs, NewHandle));\r
}\r
} else {\r
SemihostMode = SEMIHOST_FILE_MODE_READ | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE;\r
}\r
+\r
Return = SemihostFileOpen (AsciiFileName, SemihostMode, &SemihostHandle);\r
\r
if (RETURN_ERROR (Return)) {\r
FileFcb->Info.FileSize = Length;\r
FileFcb->Info.PhysicalSize = Length;\r
FileFcb->Info.Attribute = ((OpenMode & EFI_FILE_MODE_CREATE) != 0) ?\r
- Attributes : 0;\r
+ Attributes : 0;\r
\r
InsertTailList (&gFileList, &FileFcb->Link);\r
\r
EFI_STATUS\r
TruncateFile (\r
IN CHAR8 *FileName,\r
- IN UINTN Size\r
+ IN UINTN Size\r
)\r
{\r
EFI_STATUS Status;\r
goto Error;\r
}\r
\r
- Read = 0;\r
+ Read = 0;\r
Remaining = Size;\r
while (Remaining > 0) {\r
ToRead = Remaining;\r
if (RETURN_ERROR (Return)) {\r
goto Error;\r
}\r
+\r
Remaining -= ToRead;\r
Read += ToRead;\r
}\r
\r
- Return = SemihostFileClose (FileHandle);\r
+ Return = SemihostFileClose (FileHandle);\r
FileHandle = 0;\r
if (RETURN_ERROR (Return)) {\r
goto Error;\r
if (FileHandle != 0) {\r
SemihostFileClose (FileHandle);\r
}\r
+\r
if (Buffer != NULL) {\r
FreePool (Buffer);\r
}\r
\r
return (Status);\r
-\r
}\r
\r
/**\r
IN EFI_FILE *This\r
)\r
{\r
- SEMIHOST_FCB *Fcb;\r
+ SEMIHOST_FCB *Fcb;\r
\r
if (This == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- Fcb = SEMIHOST_FCB_FROM_THIS(This);\r
+ Fcb = SEMIHOST_FCB_FROM_THIS (This);\r
\r
if (!Fcb->IsRoot) {\r
SemihostFileClose (Fcb->SemihostHandle);\r
if (Fcb->Info.FileSize < Fcb->Info.PhysicalSize) {\r
TruncateFile (Fcb->FileName, Fcb->Info.FileSize);\r
}\r
+\r
FreePool (Fcb->FileName);\r
}\r
\r
**/\r
EFI_STATUS\r
FileDelete (\r
- IN EFI_FILE *This\r
+ IN EFI_FILE *This\r
)\r
{\r
SEMIHOST_FCB *Fcb;\r
if (RETURN_ERROR (Return)) {\r
return EFI_WARN_DELETE_FAILURE;\r
}\r
+\r
return EFI_SUCCESS;\r
} else {\r
return EFI_WARN_DELETE_FAILURE;\r
}\r
\r
Remaining = Size;\r
- SetMem (WriteBuffer, 0, sizeof(WriteBuffer));\r
+ SetMem (WriteBuffer, 0, sizeof (WriteBuffer));\r
while (Remaining > 0) {\r
- WriteNb = MIN (Remaining, sizeof(WriteBuffer));\r
+ WriteNb = MIN (Remaining, sizeof (WriteBuffer));\r
WriteSize = WriteNb;\r
- Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, WriteBuffer);\r
+ Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, WriteBuffer);\r
if (RETURN_ERROR (Return)) {\r
return EFI_DEVICE_ERROR;\r
}\r
+\r
Remaining -= WriteNb;\r
}\r
\r
**/\r
EFI_STATUS\r
FileWrite (\r
- IN EFI_FILE *This,\r
- IN OUT UINTN *BufferSize,\r
- IN VOID *Buffer\r
+ IN EFI_FILE *This,\r
+ IN OUT UINTN *BufferSize,\r
+ IN VOID *Buffer\r
)\r
{\r
SEMIHOST_FCB *Fcb;\r
Fcb = SEMIHOST_FCB_FROM_THIS (This);\r
\r
// We cannot write a read-only file\r
- if ((Fcb->Info.Attribute & EFI_FILE_READ_ONLY)\r
- || !(Fcb->OpenMode & EFI_FILE_MODE_WRITE)) {\r
+ if ( (Fcb->Info.Attribute & EFI_FILE_READ_ONLY)\r
+ || !(Fcb->OpenMode & EFI_FILE_MODE_WRITE))\r
+ {\r
return EFI_ACCESS_DENIED;\r
}\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
Fcb->Info.FileSize = Fcb->Position;\r
}\r
\r
WriteSize = *BufferSize;\r
- Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, Buffer);\r
+ Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, Buffer);\r
if (RETURN_ERROR (Return)) {\r
return EFI_DEVICE_ERROR;\r
}\r
if (RETURN_ERROR (Return)) {\r
return EFI_DEVICE_ERROR;\r
}\r
+\r
Fcb->Info.PhysicalSize = Length;\r
\r
return EFI_SUCCESS;\r
**/\r
EFI_STATUS\r
FileGetPosition (\r
- IN EFI_FILE *This,\r
- OUT UINT64 *Position\r
+ IN EFI_FILE *This,\r
+ OUT UINT64 *Position\r
)\r
{\r
- SEMIHOST_FCB *Fcb;\r
+ SEMIHOST_FCB *Fcb;\r
\r
if ((This == NULL) || (Position == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- Fcb = SEMIHOST_FCB_FROM_THIS(This);\r
+ Fcb = SEMIHOST_FCB_FROM_THIS (This);\r
\r
*Position = Fcb->Position;\r
\r
**/\r
EFI_STATUS\r
FileSetPosition (\r
- IN EFI_FILE *This,\r
- IN UINT64 Position\r
+ IN EFI_FILE *This,\r
+ IN UINT64 Position\r
)\r
{\r
SEMIHOST_FCB *Fcb;\r
if (Position != 0) {\r
return EFI_UNSUPPORTED;\r
}\r
- }\r
- else {\r
+ } else {\r
//\r
// UEFI Spec section 12.5:\r
// "Seeking to position 0xFFFFFFFFFFFFFFFF causes the current position to\r
if (Position == 0xFFFFFFFFFFFFFFFF) {\r
Position = Fcb->Info.FileSize;\r
}\r
+\r
Return = SemihostFileSeek (Fcb->SemihostHandle, MIN (Position, Fcb->Info.FileSize));\r
if (RETURN_ERROR (Return)) {\r
return EFI_DEVICE_ERROR;\r
OUT VOID *Buffer\r
)\r
{\r
- EFI_FILE_INFO *Info;\r
- UINTN NameSize;\r
- UINTN ResultSize;\r
- UINTN Index;\r
+ EFI_FILE_INFO *Info;\r
+ UINTN NameSize;\r
+ UINTN ResultSize;\r
+ UINTN Index;\r
\r
if (Fcb->IsRoot) {\r
- NameSize = 0;\r
- ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof(CHAR16);\r
+ NameSize = 0;\r
+ ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof (CHAR16);\r
} else {\r
NameSize = AsciiStrLen (Fcb->FileName) + 1;\r
ResultSize = SIZE_OF_EFI_FILE_INFO + NameSize * sizeof (CHAR16);\r
Info->Size = ResultSize;\r
\r
if (Fcb->IsRoot) {\r
- Info->FileName[0] = L'\0';\r
+ Info->FileName[0] = L'\0';\r
} else {\r
for (Index = 0; Index < NameSize; Index++) {\r
Info->FileName[Index] = Fcb->FileName[Index];\r
STATIC\r
EFI_STATUS\r
GetFilesystemInfo (\r
- IN SEMIHOST_FCB *Fcb,\r
- IN OUT UINTN *BufferSize,\r
- OUT VOID *Buffer\r
+ IN SEMIHOST_FCB *Fcb,\r
+ IN OUT UINTN *BufferSize,\r
+ OUT VOID *Buffer\r
)\r
{\r
EFI_FILE_SYSTEM_INFO *Info;\r
OUT VOID *Buffer\r
)\r
{\r
- SEMIHOST_FCB *Fcb;\r
- EFI_STATUS Status;\r
- UINTN ResultSize;\r
+ SEMIHOST_FCB *Fcb;\r
+ EFI_STATUS Status;\r
+ UINTN ResultSize;\r
\r
if ((This == NULL) ||\r
(InformationType == NULL) ||\r
(BufferSize == NULL) ||\r
- ((Buffer == NULL) && (*BufferSize > 0)) ) {\r
+ ((Buffer == NULL) && (*BufferSize > 0)))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- Fcb = SEMIHOST_FCB_FROM_THIS(This);\r
+ Fcb = SEMIHOST_FCB_FROM_THIS (This);\r
\r
if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) {\r
Status = GetFilesystemInfo (Fcb, BufferSize, Buffer);\r
return EFI_ACCESS_DENIED;\r
}\r
\r
- Length = StrLen (Info->FileName) + 1;\r
+ Length = StrLen (Info->FileName) + 1;\r
AsciiFileName = AllocatePool (Length);\r
if (AsciiFileName == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
UnicodeStrToAsciiStrS (Info->FileName, AsciiFileName, Length);\r
\r
FileSizeIsDifferent = (Info->FileSize != Fcb->Info.FileSize);\r
// description.\r
//\r
if ((Fcb->OpenMode == EFI_FILE_MODE_READ) ||\r
- (Fcb->Info.Attribute & EFI_FILE_READ_ONLY) ) {\r
+ (Fcb->Info.Attribute & EFI_FILE_READ_ONLY))\r
+ {\r
if (FileSizeIsDifferent || FileNameIsDifferent || ReadOnlyIsDifferent) {\r
Status = EFI_ACCESS_DENIED;\r
goto Error;\r
if (EFI_ERROR (Status)) {\r
goto Error;\r
}\r
+\r
//\r
// The read/write position from the host file system point of view\r
// is at the end of the file. If the position from this module\r
FileSetPosition (&Fcb->File, Fcb->Position);\r
}\r
}\r
+\r
Fcb->Info.FileSize = FileSize;\r
\r
Return = SemihostFileLength (Fcb->SemihostHandle, &Length);\r
if (RETURN_ERROR (Return)) {\r
goto Error;\r
}\r
+\r
Fcb->Info.PhysicalSize = Length;\r
}\r
\r
if (RETURN_ERROR (Return)) {\r
goto Error;\r
}\r
+\r
FreePool (Fcb->FileName);\r
Fcb->FileName = AsciiFileName;\r
AsciiFileName = NULL;\r
if (Info->Size < (SIZE_OF_EFI_FILE_INFO + StrSize (Info->FileName))) {\r
return EFI_INVALID_PARAMETER;\r
}\r
+\r
if (BufferSize < Info->Size) {\r
return EFI_BAD_BUFFER_SIZE;\r
}\r
+\r
return SetFileInfo (Fcb, Info);\r
} else if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) {\r
SystemInfo = Buffer;\r
if (SystemInfo->Size <\r
- (SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize (SystemInfo->VolumeLabel))) {\r
+ (SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize (SystemInfo->VolumeLabel)))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
+\r
if (BufferSize < SystemInfo->Size) {\r
return EFI_BAD_BUFFER_SIZE;\r
}\r
+\r
Buffer = SystemInfo->VolumeLabel;\r
\r
if (StrSize (Buffer) > 0) {\r
\r
EFI_STATUS\r
FileFlush (\r
- IN EFI_FILE *File\r
+ IN EFI_FILE *File\r
)\r
{\r
- SEMIHOST_FCB *Fcb;\r
+ SEMIHOST_FCB *Fcb;\r
\r
- Fcb = SEMIHOST_FCB_FROM_THIS(File);\r
+ Fcb = SEMIHOST_FCB_FROM_THIS (File);\r
\r
if (Fcb->IsRoot) {\r
return EFI_SUCCESS;\r
} else {\r
- if ((Fcb->Info.Attribute & EFI_FILE_READ_ONLY)\r
- || !(Fcb->OpenMode & EFI_FILE_MODE_WRITE)) {\r
+ if ( (Fcb->Info.Attribute & EFI_FILE_READ_ONLY)\r
+ || !(Fcb->OpenMode & EFI_FILE_MODE_WRITE))\r
+ {\r
return EFI_ACCESS_DENIED;\r
} else {\r
return EFI_SUCCESS;\r
\r
EFI_STATUS\r
SemihostFsEntryPoint (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
Status = EFI_NOT_FOUND;\r
\r
\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&gInstallHandle,\r
- &gEfiSimpleFileSystemProtocolGuid, &gSemihostFs,\r
- &gEfiDevicePathProtocolGuid, &gDevicePath,\r
+ &gEfiSimpleFileSystemProtocolGuid,\r
+ &gSemihostFs,\r
+ &gEfiDevicePathProtocolGuid,\r
+ &gDevicePath,\r
NULL\r
);\r
\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
FreePool (mSemihostFsLabel);\r
}\r
}\r
\r
EFI_STATUS\r
VolumeOpen (\r
- IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,\r
- OUT EFI_FILE **Root\r
+ IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,\r
+ OUT EFI_FILE **Root\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
FileDelete (\r
- IN EFI_FILE *This\r
+ IN EFI_FILE *This\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
FileWrite (\r
- IN EFI_FILE *This,\r
- IN OUT UINTN *BufferSize,\r
- IN VOID *Buffer\r
+ IN EFI_FILE *This,\r
+ IN OUT UINTN *BufferSize,\r
+ IN VOID *Buffer\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
FileGetPosition (\r
- IN EFI_FILE *File,\r
- OUT UINT64 *Position\r
+ IN EFI_FILE *File,\r
+ OUT UINT64 *Position\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
FileSetPosition (\r
- IN EFI_FILE *File,\r
- IN UINT64 Position\r
+ IN EFI_FILE *File,\r
+ IN UINT64 Position\r
);\r
\r
/**\r
\r
EFI_STATUS\r
FileFlush (\r
- IN EFI_FILE *File\r
+ IN EFI_FILE *File\r
);\r
\r
#endif // SEMIHOST_FS_H_\r
-\r
\r
**/\r
\r
-\r
#ifndef ASM_MACRO_IO_LIB_H_\r
#define ASM_MACRO_IO_LIB_H_\r
\r
.p2align 2 ; \\r
Name:\r
\r
-#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)\r
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)\r
\r
#define MOV32(Reg, Val) \\r
movw Reg, #(Val) & 0xffff ; \\r
\r
**/\r
\r
-\r
#ifndef ASM_MACRO_IO_LIBV8_H_\r
#define ASM_MACRO_IO_LIBV8_H_\r
\r
cbnz SAFE_XREG, 1f ;\\r
b . ;// We should never get here\r
\r
-\r
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1\r
// This only selects between EL1 and EL2 and EL3, else we die.\r
// Provide the Macro with a safe temp xreg to use.\r
.type Name, %function ; \\r
Name:\r
\r
-#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)\r
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)\r
\r
#define MOV32(Reg, Val) \\r
movz Reg, (Val) >> 16, lsl #16 ; \\r
#include <Chipset/AArch64Mmu.h>\r
\r
// ARM Interrupt ID in Exception Table\r
-#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ\r
+#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ\r
\r
// CPACR - Coprocessor Access Control Register definitions\r
-#define CPACR_TTA_EN (1UL << 28)\r
-#define CPACR_FPEN_EL1 (1UL << 20)\r
-#define CPACR_FPEN_FULL (3UL << 20)\r
-#define CPACR_CP_FULL_ACCESS 0x300000\r
+#define CPACR_TTA_EN (1UL << 28)\r
+#define CPACR_FPEN_EL1 (1UL << 20)\r
+#define CPACR_FPEN_FULL (3UL << 20)\r
+#define CPACR_CP_FULL_ACCESS 0x300000\r
\r
// Coprocessor Trap Register (CPTR)\r
-#define AARCH64_CPTR_TFP (1 << 10)\r
+#define AARCH64_CPTR_TFP (1 << 10)\r
\r
// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions\r
-#define AARCH64_PFR0_FP (0xF << 16)\r
-#define AARCH64_PFR0_GIC (0xF << 24)\r
+#define AARCH64_PFR0_FP (0xF << 16)\r
+#define AARCH64_PFR0_GIC (0xF << 24)\r
\r
// SCR - Secure Configuration Register definitions\r
-#define SCR_NS (1 << 0)\r
-#define SCR_IRQ (1 << 1)\r
-#define SCR_FIQ (1 << 2)\r
-#define SCR_EA (1 << 3)\r
-#define SCR_FW (1 << 4)\r
-#define SCR_AW (1 << 5)\r
+#define SCR_NS (1 << 0)\r
+#define SCR_IRQ (1 << 1)\r
+#define SCR_FIQ (1 << 2)\r
+#define SCR_EA (1 << 3)\r
+#define SCR_FW (1 << 4)\r
+#define SCR_AW (1 << 5)\r
\r
// MIDR - Main ID Register definitions\r
-#define ARM_CPU_TYPE_SHIFT 4\r
-#define ARM_CPU_TYPE_MASK 0xFFF\r
-#define ARM_CPU_TYPE_AEMV8 0xD0F\r
-#define ARM_CPU_TYPE_A53 0xD03\r
-#define ARM_CPU_TYPE_A57 0xD07\r
-#define ARM_CPU_TYPE_A72 0xD08\r
-#define ARM_CPU_TYPE_A15 0xC0F\r
-#define ARM_CPU_TYPE_A9 0xC09\r
-#define ARM_CPU_TYPE_A7 0xC07\r
-#define ARM_CPU_TYPE_A5 0xC05\r
-\r
-#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r
-#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
+#define ARM_CPU_TYPE_SHIFT 4\r
+#define ARM_CPU_TYPE_MASK 0xFFF\r
+#define ARM_CPU_TYPE_AEMV8 0xD0F\r
+#define ARM_CPU_TYPE_A53 0xD03\r
+#define ARM_CPU_TYPE_A57 0xD07\r
+#define ARM_CPU_TYPE_A72 0xD08\r
+#define ARM_CPU_TYPE_A15 0xC0F\r
+#define ARM_CPU_TYPE_A9 0xC09\r
+#define ARM_CPU_TYPE_A7 0xC07\r
+#define ARM_CPU_TYPE_A5 0xC05\r
+\r
+#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r
+#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
\r
// Hypervisor Configuration Register\r
-#define ARM_HCR_FMO BIT3\r
-#define ARM_HCR_IMO BIT4\r
-#define ARM_HCR_AMO BIT5\r
-#define ARM_HCR_TSC BIT19\r
-#define ARM_HCR_TGE BIT27\r
+#define ARM_HCR_FMO BIT3\r
+#define ARM_HCR_IMO BIT4\r
+#define ARM_HCR_AMO BIT5\r
+#define ARM_HCR_TSC BIT19\r
+#define ARM_HCR_TGE BIT27\r
\r
// Exception Syndrome Register\r
-#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))\r
-#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))\r
+#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))\r
+#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))\r
\r
-#define AARCH64_ESR_EC_SMC32 (0x13 << 26)\r
-#define AARCH64_ESR_EC_SMC64 (0x17 << 26)\r
+#define AARCH64_ESR_EC_SMC32 (0x13 << 26)\r
+#define AARCH64_ESR_EC_SMC64 (0x17 << 26)\r
\r
// AArch64 Exception Level\r
-#define AARCH64_EL3 0xC\r
-#define AARCH64_EL2 0x8\r
-#define AARCH64_EL1 0x4\r
+#define AARCH64_EL3 0xC\r
+#define AARCH64_EL2 0x8\r
+#define AARCH64_EL1 0x4\r
\r
// Saved Program Status Register definitions\r
-#define SPSR_A BIT8\r
-#define SPSR_I BIT7\r
-#define SPSR_F BIT6\r
+#define SPSR_A BIT8\r
+#define SPSR_I BIT7\r
+#define SPSR_F BIT6\r
\r
-#define SPSR_AARCH32 BIT4\r
+#define SPSR_AARCH32 BIT4\r
\r
-#define SPSR_AARCH32_MODE_USER 0x0\r
-#define SPSR_AARCH32_MODE_FIQ 0x1\r
-#define SPSR_AARCH32_MODE_IRQ 0x2\r
-#define SPSR_AARCH32_MODE_SVC 0x3\r
-#define SPSR_AARCH32_MODE_ABORT 0x7\r
-#define SPSR_AARCH32_MODE_UNDEF 0xB\r
-#define SPSR_AARCH32_MODE_SYS 0xF\r
+#define SPSR_AARCH32_MODE_USER 0x0\r
+#define SPSR_AARCH32_MODE_FIQ 0x1\r
+#define SPSR_AARCH32_MODE_IRQ 0x2\r
+#define SPSR_AARCH32_MODE_SVC 0x3\r
+#define SPSR_AARCH32_MODE_ABORT 0x7\r
+#define SPSR_AARCH32_MODE_UNDEF 0xB\r
+#define SPSR_AARCH32_MODE_SYS 0xF\r
\r
// Counter-timer Hypervisor Control register definitions\r
-#define CNTHCTL_EL2_EL1PCTEN BIT0\r
-#define CNTHCTL_EL2_EL1PCEN BIT1\r
+#define CNTHCTL_EL2_EL1PCTEN BIT0\r
+#define CNTHCTL_EL2_EL1PCEN BIT1\r
\r
-#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)\r
+#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)\r
\r
// Vector table offset definitions\r
-#define ARM_VECTOR_CUR_SP0_SYNC 0x000\r
-#define ARM_VECTOR_CUR_SP0_IRQ 0x080\r
-#define ARM_VECTOR_CUR_SP0_FIQ 0x100\r
-#define ARM_VECTOR_CUR_SP0_SERR 0x180\r
-\r
-#define ARM_VECTOR_CUR_SPX_SYNC 0x200\r
-#define ARM_VECTOR_CUR_SPX_IRQ 0x280\r
-#define ARM_VECTOR_CUR_SPX_FIQ 0x300\r
-#define ARM_VECTOR_CUR_SPX_SERR 0x380\r
-\r
-#define ARM_VECTOR_LOW_A64_SYNC 0x400\r
-#define ARM_VECTOR_LOW_A64_IRQ 0x480\r
-#define ARM_VECTOR_LOW_A64_FIQ 0x500\r
-#define ARM_VECTOR_LOW_A64_SERR 0x580\r
-\r
-#define ARM_VECTOR_LOW_A32_SYNC 0x600\r
-#define ARM_VECTOR_LOW_A32_IRQ 0x680\r
-#define ARM_VECTOR_LOW_A32_FIQ 0x700\r
-#define ARM_VECTOR_LOW_A32_SERR 0x780\r
+#define ARM_VECTOR_CUR_SP0_SYNC 0x000\r
+#define ARM_VECTOR_CUR_SP0_IRQ 0x080\r
+#define ARM_VECTOR_CUR_SP0_FIQ 0x100\r
+#define ARM_VECTOR_CUR_SP0_SERR 0x180\r
+\r
+#define ARM_VECTOR_CUR_SPX_SYNC 0x200\r
+#define ARM_VECTOR_CUR_SPX_IRQ 0x280\r
+#define ARM_VECTOR_CUR_SPX_FIQ 0x300\r
+#define ARM_VECTOR_CUR_SPX_SERR 0x380\r
+\r
+#define ARM_VECTOR_LOW_A64_SYNC 0x400\r
+#define ARM_VECTOR_LOW_A64_IRQ 0x480\r
+#define ARM_VECTOR_LOW_A64_FIQ 0x500\r
+#define ARM_VECTOR_LOW_A64_SERR 0x580\r
+\r
+#define ARM_VECTOR_LOW_A32_SYNC 0x600\r
+#define ARM_VECTOR_LOW_A32_IRQ 0x680\r
+#define ARM_VECTOR_LOW_A32_FIQ 0x700\r
+#define ARM_VECTOR_LOW_A32_SERR 0x780\r
\r
// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we\r
// build for ARMv8.0, we need to define the register here.\r
-#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2\r
+#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2\r
\r
#define VECTOR_BASE(tbl) \\r
.section .text.##tbl##,"ax"; \\r
VOID\r
EFIAPI\r
ArmWriteTpidrurw (\r
- UINTN Value\r
+ UINTN Value\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmSetTCR (\r
- UINTN Value\r
+ UINTN Value\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmSetMAIR (\r
- UINTN Value\r
+ UINTN Value\r
);\r
\r
VOID\r
\r
VOID\r
ArmWriteHcr (\r
- IN UINTN Hcr\r
+ IN UINTN Hcr\r
);\r
\r
UINTN\r
\r
UINTN\r
ArmWriteCptr (\r
- IN UINT64 Cptr\r
+ IN UINT64 Cptr\r
);\r
\r
UINT32\r
\r
VOID\r
ArmWriteCntHctl (\r
- IN UINT32 CntHctl\r
+ IN UINT32 CntHctl\r
);\r
\r
#endif // AARCH64_H_\r
//\r
// Memory Attribute Indirection register Definitions\r
//\r
-#define MAIR_ATTR_DEVICE_MEMORY 0x0ULL\r
-#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL\r
-#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL\r
-#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL\r
+#define MAIR_ATTR_DEVICE_MEMORY 0x0ULL\r
+#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL\r
+#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL\r
+#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL\r
\r
-#define MAIR_ATTR(n,value) ((value) << (((n) >> 2)*8))\r
+#define MAIR_ATTR(n, value) ((value) << (((n) >> 2)*8))\r
\r
//\r
// Long-descriptor Translation Table format\r
// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0\r
#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9))\r
\r
-#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))\r
+#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))\r
\r
// Get the associated entry in the given Translation Table\r
#define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \\r
\r
// Return the smallest address granularity from the table level.\r
// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0\r
-#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))\r
+#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))\r
\r
#define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \\r
((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))\r
\r
// There are 512 entries per table when 4K Granularity\r
-#define TT_ENTRY_COUNT 512\r
-#define TT_ALIGNMENT_BLOCK_ENTRY BIT12\r
-#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12\r
-\r
-#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)\r
-#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)\r
-\r
-#define TT_TYPE_MASK 0x3\r
-#define TT_TYPE_TABLE_ENTRY 0x3\r
-#define TT_TYPE_BLOCK_ENTRY 0x1\r
-#define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3\r
-\r
-#define TT_ATTR_INDX_MASK (0x7 << 2)\r
-#define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)\r
-#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)\r
-#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)\r
-#define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)\r
-\r
-#define TT_AP_MASK (0x3UL << 6)\r
-#define TT_AP_NO_RW (0x0UL << 6)\r
-#define TT_AP_RW_RW (0x1UL << 6)\r
-#define TT_AP_NO_RO (0x2UL << 6)\r
-#define TT_AP_RO_RO (0x3UL << 6)\r
-\r
-#define TT_NS BIT5\r
-#define TT_AF BIT10\r
-\r
-#define TT_SH_NON_SHAREABLE (0x0 << 8)\r
-#define TT_SH_OUTER_SHAREABLE (0x2 << 8)\r
-#define TT_SH_INNER_SHAREABLE (0x3 << 8)\r
-#define TT_SH_MASK (0x3 << 8)\r
-\r
-#define TT_PXN_MASK BIT53\r
-#define TT_UXN_MASK BIT54 // EL1&0\r
-#define TT_XN_MASK BIT54 // EL2 / EL3\r
-\r
-#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))\r
-\r
-#define TT_TABLE_PXN BIT59\r
-#define TT_TABLE_UXN BIT60 // EL1&0\r
-#define TT_TABLE_XN BIT60 // EL2 / EL3\r
-#define TT_TABLE_NS BIT63\r
-\r
-#define TT_TABLE_AP_MASK (BIT62 | BIT61)\r
-#define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)\r
-#define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)\r
-#define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)\r
+#define TT_ENTRY_COUNT 512\r
+#define TT_ALIGNMENT_BLOCK_ENTRY BIT12\r
+#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12\r
+\r
+#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)\r
+#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)\r
+\r
+#define TT_TYPE_MASK 0x3\r
+#define TT_TYPE_TABLE_ENTRY 0x3\r
+#define TT_TYPE_BLOCK_ENTRY 0x1\r
+#define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3\r
+\r
+#define TT_ATTR_INDX_MASK (0x7 << 2)\r
+#define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)\r
+#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)\r
+#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)\r
+#define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)\r
+\r
+#define TT_AP_MASK (0x3UL << 6)\r
+#define TT_AP_NO_RW (0x0UL << 6)\r
+#define TT_AP_RW_RW (0x1UL << 6)\r
+#define TT_AP_NO_RO (0x2UL << 6)\r
+#define TT_AP_RO_RO (0x3UL << 6)\r
+\r
+#define TT_NS BIT5\r
+#define TT_AF BIT10\r
+\r
+#define TT_SH_NON_SHAREABLE (0x0 << 8)\r
+#define TT_SH_OUTER_SHAREABLE (0x2 << 8)\r
+#define TT_SH_INNER_SHAREABLE (0x3 << 8)\r
+#define TT_SH_MASK (0x3 << 8)\r
+\r
+#define TT_PXN_MASK BIT53\r
+#define TT_UXN_MASK BIT54 // EL1&0\r
+#define TT_XN_MASK BIT54 // EL2 / EL3\r
+\r
+#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))\r
+\r
+#define TT_TABLE_PXN BIT59\r
+#define TT_TABLE_UXN BIT60 // EL1&0\r
+#define TT_TABLE_XN BIT60 // EL2 / EL3\r
+#define TT_TABLE_NS BIT63\r
+\r
+#define TT_TABLE_AP_MASK (BIT62 | BIT61)\r
+#define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)\r
+#define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)\r
+#define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)\r
\r
//\r
// Translation Control Register\r
//\r
-#define TCR_T0SZ_MASK 0x3FUL\r
-\r
-#define TCR_PS_4GB (0UL << 16)\r
-#define TCR_PS_64GB (1UL << 16)\r
-#define TCR_PS_1TB (2UL << 16)\r
-#define TCR_PS_4TB (3UL << 16)\r
-#define TCR_PS_16TB (4UL << 16)\r
-#define TCR_PS_256TB (5UL << 16)\r
-\r
-#define TCR_TG0_4KB (0UL << 14)\r
-#define TCR_TG1_4KB (2UL << 30)\r
-\r
-#define TCR_IPS_4GB (0ULL << 32)\r
-#define TCR_IPS_64GB (1ULL << 32)\r
-#define TCR_IPS_1TB (2ULL << 32)\r
-#define TCR_IPS_4TB (3ULL << 32)\r
-#define TCR_IPS_16TB (4ULL << 32)\r
-#define TCR_IPS_256TB (5ULL << 32)\r
-\r
-#define TCR_EPD1 (1UL << 23)\r
-\r
-#define TTBR_ASID_FIELD (48)\r
-#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)\r
-#define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits\r
-\r
-#define TCR_EL1_T0SZ_FIELD (0)\r
-#define TCR_EL1_EPD0_FIELD (7)\r
-#define TCR_EL1_IRGN0_FIELD (8)\r
-#define TCR_EL1_ORGN0_FIELD (10)\r
-#define TCR_EL1_SH0_FIELD (12)\r
-#define TCR_EL1_TG0_FIELD (14)\r
-#define TCR_EL1_T1SZ_FIELD (16)\r
-#define TCR_EL1_A1_FIELD (22)\r
-#define TCR_EL1_EPD1_FIELD (23)\r
-#define TCR_EL1_IRGN1_FIELD (24)\r
-#define TCR_EL1_ORGN1_FIELD (26)\r
-#define TCR_EL1_SH1_FIELD (28)\r
-#define TCR_EL1_TG1_FIELD (30)\r
-#define TCR_EL1_IPS_FIELD (32)\r
-#define TCR_EL1_AS_FIELD (36)\r
-#define TCR_EL1_TBI0_FIELD (37)\r
-#define TCR_EL1_TBI1_FIELD (38)\r
-#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)\r
-#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)\r
-#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)\r
-#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)\r
-#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)\r
-#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)\r
-#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)\r
-#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)\r
-#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)\r
-#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)\r
-#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)\r
-#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)\r
-#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)\r
-#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)\r
-#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)\r
-#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)\r
-#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)\r
-\r
-\r
-#define TCR_EL23_T0SZ_FIELD (0)\r
-#define TCR_EL23_IRGN0_FIELD (8)\r
-#define TCR_EL23_ORGN0_FIELD (10)\r
-#define TCR_EL23_SH0_FIELD (12)\r
-#define TCR_EL23_TG0_FIELD (14)\r
-#define TCR_EL23_PS_FIELD (16)\r
-#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)\r
-#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)\r
-#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)\r
-#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)\r
-#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)\r
-#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)\r
-\r
-\r
-#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)\r
-#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)\r
-#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)\r
-#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)\r
-\r
-#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)\r
-#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)\r
-#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)\r
-#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)\r
-\r
-#define TCR_SH_NON_SHAREABLE (0x0UL << 12)\r
-#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)\r
-#define TCR_SH_INNER_SHAREABLE (0x3UL << 12)\r
-\r
-#define TCR_PASZ_32BITS_4GB (0x0UL)\r
-#define TCR_PASZ_36BITS_64GB (0x1UL)\r
-#define TCR_PASZ_40BITS_1TB (0x2UL)\r
-#define TCR_PASZ_42BITS_4TB (0x3UL)\r
-#define TCR_PASZ_44BITS_16TB (0x4UL)\r
-#define TCR_PASZ_48BITS_256TB (0x5UL)\r
+#define TCR_T0SZ_MASK 0x3FUL\r
+\r
+#define TCR_PS_4GB (0UL << 16)\r
+#define TCR_PS_64GB (1UL << 16)\r
+#define TCR_PS_1TB (2UL << 16)\r
+#define TCR_PS_4TB (3UL << 16)\r
+#define TCR_PS_16TB (4UL << 16)\r
+#define TCR_PS_256TB (5UL << 16)\r
+\r
+#define TCR_TG0_4KB (0UL << 14)\r
+#define TCR_TG1_4KB (2UL << 30)\r
+\r
+#define TCR_IPS_4GB (0ULL << 32)\r
+#define TCR_IPS_64GB (1ULL << 32)\r
+#define TCR_IPS_1TB (2ULL << 32)\r
+#define TCR_IPS_4TB (3ULL << 32)\r
+#define TCR_IPS_16TB (4ULL << 32)\r
+#define TCR_IPS_256TB (5ULL << 32)\r
+\r
+#define TCR_EPD1 (1UL << 23)\r
+\r
+#define TTBR_ASID_FIELD (48)\r
+#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)\r
+#define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits\r
+\r
+#define TCR_EL1_T0SZ_FIELD (0)\r
+#define TCR_EL1_EPD0_FIELD (7)\r
+#define TCR_EL1_IRGN0_FIELD (8)\r
+#define TCR_EL1_ORGN0_FIELD (10)\r
+#define TCR_EL1_SH0_FIELD (12)\r
+#define TCR_EL1_TG0_FIELD (14)\r
+#define TCR_EL1_T1SZ_FIELD (16)\r
+#define TCR_EL1_A1_FIELD (22)\r
+#define TCR_EL1_EPD1_FIELD (23)\r
+#define TCR_EL1_IRGN1_FIELD (24)\r
+#define TCR_EL1_ORGN1_FIELD (26)\r
+#define TCR_EL1_SH1_FIELD (28)\r
+#define TCR_EL1_TG1_FIELD (30)\r
+#define TCR_EL1_IPS_FIELD (32)\r
+#define TCR_EL1_AS_FIELD (36)\r
+#define TCR_EL1_TBI0_FIELD (37)\r
+#define TCR_EL1_TBI1_FIELD (38)\r
+#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)\r
+#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)\r
+#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)\r
+#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)\r
+#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)\r
+#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)\r
+#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)\r
+#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)\r
+#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)\r
+#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)\r
+#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)\r
+#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)\r
+#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)\r
+#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)\r
+#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)\r
+#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)\r
+#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)\r
+\r
+#define TCR_EL23_T0SZ_FIELD (0)\r
+#define TCR_EL23_IRGN0_FIELD (8)\r
+#define TCR_EL23_ORGN0_FIELD (10)\r
+#define TCR_EL23_SH0_FIELD (12)\r
+#define TCR_EL23_TG0_FIELD (14)\r
+#define TCR_EL23_PS_FIELD (16)\r
+#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)\r
+#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)\r
+#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)\r
+#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)\r
+#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)\r
+#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)\r
+\r
+#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)\r
+#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)\r
+#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)\r
+#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)\r
+\r
+#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)\r
+#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)\r
+#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)\r
+#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)\r
+\r
+#define TCR_SH_NON_SHAREABLE (0x0UL << 12)\r
+#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)\r
+#define TCR_SH_INNER_SHAREABLE (0x3UL << 12)\r
+\r
+#define TCR_PASZ_32BITS_4GB (0x0UL)\r
+#define TCR_PASZ_36BITS_64GB (0x1UL)\r
+#define TCR_PASZ_40BITS_1TB (0x2UL)\r
+#define TCR_PASZ_42BITS_4TB (0x3UL)\r
+#define TCR_PASZ_44BITS_16TB (0x4UL)\r
+#define TCR_PASZ_48BITS_256TB (0x5UL)\r
\r
// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit\r
// Virtual address range for 512GB of virtual space sets T*SZ to 25\r
-#define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)\r
+#define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)\r
\r
// Uses LPAE Page Table format\r
\r
#endif // AARCH64_MMU_H_\r
-\r
//\r
// Cortex A5x feature bit definitions\r
//\r
-#define A5X_FEATURE_SMP (1 << 6)\r
+#define A5X_FEATURE_SMP (1 << 6)\r
\r
//\r
// Helper functions to access CPU Extended Control Register\r
VOID\r
EFIAPI\r
ArmWriteCpuExCr (\r
- IN UINT64 Val\r
+ IN UINT64 Val\r
);\r
\r
VOID\r
EFIAPI\r
ArmSetCpuExCrBit (\r
- IN UINT64 Bits\r
+ IN UINT64 Bits\r
);\r
\r
VOID\r
EFIAPI\r
ArmUnsetCpuExCrBit (\r
- IN UINT64 Bits\r
+ IN UINT64 Bits\r
);\r
\r
#endif // ARM_CORTEX_A5X_H_\r
//\r
// Cortex A9 Watchdog\r
//\r
-#define ARM_A9_WATCHDOG_REGION 0x600\r
+#define ARM_A9_WATCHDOG_REGION 0x600\r
\r
-#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20\r
-#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28\r
+#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20\r
+#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28\r
\r
-#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)\r
-#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)\r
-#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)\r
-#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)\r
-#define ARM_A9_WATCHDOG_ENABLE 1\r
+#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)\r
+#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)\r
+#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)\r
+#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)\r
+#define ARM_A9_WATCHDOG_ENABLE 1\r
\r
//\r
// SCU register offsets & masks\r
//\r
-#define A9_SCU_CONTROL_OFFSET 0x0\r
-#define A9_SCU_CONFIG_OFFSET 0x4\r
-#define A9_SCU_INVALL_OFFSET 0xC\r
-#define A9_SCU_FILT_START_OFFSET 0x40\r
-#define A9_SCU_FILT_END_OFFSET 0x44\r
-#define A9_SCU_SACR_OFFSET 0x50\r
-#define A9_SCU_SSACR_OFFSET 0x54\r
-\r
+#define A9_SCU_CONTROL_OFFSET 0x0\r
+#define A9_SCU_CONFIG_OFFSET 0x4\r
+#define A9_SCU_INVALL_OFFSET 0xC\r
+#define A9_SCU_FILT_START_OFFSET 0x40\r
+#define A9_SCU_FILT_END_OFFSET 0x44\r
+#define A9_SCU_SACR_OFFSET 0x50\r
+#define A9_SCU_SSACR_OFFSET 0x54\r
\r
UINTN\r
EFIAPI\r
);\r
\r
#endif // ARM_CORTEX_A9_H_\r
-\r
#include <Chipset/ArmV7Mmu.h>\r
\r
// ARM Interrupt ID in Exception Table\r
-#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ\r
+#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ\r
\r
// ID_PFR1 - ARM Processor Feature Register 1 definitions\r
-#define ARM_PFR1_SEC (0xFUL << 4)\r
-#define ARM_PFR1_TIMER (0xFUL << 16)\r
-#define ARM_PFR1_GIC (0xFUL << 28)\r
+#define ARM_PFR1_SEC (0xFUL << 4)\r
+#define ARM_PFR1_TIMER (0xFUL << 16)\r
+#define ARM_PFR1_GIC (0xFUL << 28)\r
\r
// Domain Access Control Register\r
-#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r
\r
// CPSR - Coprocessor Status Register definitions\r
#define CPSR_MODE_USER 0x10\r
#define CPSR_IRQ (1 << 7)\r
#define CPSR_FIQ (1 << 6)\r
\r
-\r
// CPACR - Coprocessor Access Control Register definitions\r
-#define CPACR_CP_DENIED(cp) 0x00\r
-#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r
-#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)\r
-#define CPACR_ASEDIS (1 << 31)\r
-#define CPACR_D32DIS (1 << 30)\r
-#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF\r
+#define CPACR_CP_DENIED(cp) 0x00\r
+#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r
+#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)\r
+#define CPACR_ASEDIS (1 << 31)\r
+#define CPACR_D32DIS (1 << 30)\r
+#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF\r
\r
// NSACR - Non-Secure Access Control Register definitions\r
-#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)\r
-#define NSACR_NSD32DIS (1 << 14)\r
-#define NSACR_NSASEDIS (1 << 15)\r
-#define NSACR_PLE (1 << 16)\r
-#define NSACR_TL (1 << 17)\r
-#define NSACR_NS_SMP (1 << 18)\r
-#define NSACR_RFR (1 << 19)\r
+#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)\r
+#define NSACR_NSD32DIS (1 << 14)\r
+#define NSACR_NSASEDIS (1 << 15)\r
+#define NSACR_PLE (1 << 16)\r
+#define NSACR_TL (1 << 17)\r
+#define NSACR_NS_SMP (1 << 18)\r
+#define NSACR_RFR (1 << 19)\r
\r
// SCR - Secure Configuration Register definitions\r
-#define SCR_NS (1 << 0)\r
-#define SCR_IRQ (1 << 1)\r
-#define SCR_FIQ (1 << 2)\r
-#define SCR_EA (1 << 3)\r
-#define SCR_FW (1 << 4)\r
-#define SCR_AW (1 << 5)\r
+#define SCR_NS (1 << 0)\r
+#define SCR_IRQ (1 << 1)\r
+#define SCR_FIQ (1 << 2)\r
+#define SCR_EA (1 << 3)\r
+#define SCR_FW (1 << 4)\r
+#define SCR_AW (1 << 5)\r
\r
// MIDR - Main ID Register definitions\r
-#define ARM_CPU_TYPE_SHIFT 4\r
-#define ARM_CPU_TYPE_MASK 0xFFF\r
-#define ARM_CPU_TYPE_AEMV8 0xD0F\r
-#define ARM_CPU_TYPE_A53 0xD03\r
-#define ARM_CPU_TYPE_A57 0xD07\r
-#define ARM_CPU_TYPE_A15 0xC0F\r
-#define ARM_CPU_TYPE_A12 0xC0D\r
-#define ARM_CPU_TYPE_A9 0xC09\r
-#define ARM_CPU_TYPE_A7 0xC07\r
-#define ARM_CPU_TYPE_A5 0xC05\r
-\r
-#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r
-#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
-\r
-#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)\r
+#define ARM_CPU_TYPE_SHIFT 4\r
+#define ARM_CPU_TYPE_MASK 0xFFF\r
+#define ARM_CPU_TYPE_AEMV8 0xD0F\r
+#define ARM_CPU_TYPE_A53 0xD03\r
+#define ARM_CPU_TYPE_A57 0xD07\r
+#define ARM_CPU_TYPE_A15 0xC0F\r
+#define ARM_CPU_TYPE_A12 0xC0D\r
+#define ARM_CPU_TYPE_A9 0xC09\r
+#define ARM_CPU_TYPE_A7 0xC07\r
+#define ARM_CPU_TYPE_A5 0xC05\r
+\r
+#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r
+#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
+\r
+#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)\r
\r
VOID\r
EFIAPI\r
VOID\r
EFIAPI\r
ArmWriteTpidrurw (\r
- UINTN Value\r
+ UINTN Value\r
);\r
\r
UINT32\r
VOID\r
EFIAPI\r
ArmWriteNsacr (\r
- IN UINT32 Nsacr\r
+ IN UINT32 Nsacr\r
);\r
\r
#endif // ARM_V7_H_\r
#ifndef ARMV7_MMU_H_\r
#define ARMV7_MMU_H_\r
\r
-#define TTBR_NOT_OUTER_SHAREABLE BIT5\r
-#define TTBR_RGN_OUTER_NON_CACHEABLE 0\r
-#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3\r
-#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4\r
-#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)\r
-#define TTBR_SHAREABLE BIT1\r
-#define TTBR_NON_SHAREABLE 0\r
-#define TTBR_INNER_CACHEABLE BIT0\r
-#define TTBR_INNER_NON_CACHEABLE 0\r
-#define TTBR_RGN_INNER_NON_CACHEABLE 0\r
-#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6\r
-#define TTBR_RGN_INNER_WRITE_THROUGH BIT0\r
-#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)\r
-\r
-#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)\r
-#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)\r
-#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE )\r
-#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)\r
-\r
-#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)\r
-#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)\r
-#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )\r
-#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)\r
-\r
-\r
-#define TRANSLATION_TABLE_SECTION_COUNT 4096\r
-#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)\r
-#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)\r
-#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)\r
-\r
-#define TRANSLATION_TABLE_PAGE_COUNT 256\r
-#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)\r
-#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)\r
-#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)\r
-\r
-#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))\r
+#define TTBR_NOT_OUTER_SHAREABLE BIT5\r
+#define TTBR_RGN_OUTER_NON_CACHEABLE 0\r
+#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3\r
+#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4\r
+#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)\r
+#define TTBR_SHAREABLE BIT1\r
+#define TTBR_NON_SHAREABLE 0\r
+#define TTBR_INNER_CACHEABLE BIT0\r
+#define TTBR_INNER_NON_CACHEABLE 0\r
+#define TTBR_RGN_INNER_NON_CACHEABLE 0\r
+#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6\r
+#define TTBR_RGN_INNER_WRITE_THROUGH BIT0\r
+#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)\r
+\r
+#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)\r
+#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)\r
+#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE )\r
+#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)\r
+\r
+#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)\r
+#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)\r
+#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )\r
+#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)\r
+\r
+#define TRANSLATION_TABLE_SECTION_COUNT 4096\r
+#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)\r
+#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)\r
+#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)\r
+\r
+#define TRANSLATION_TABLE_PAGE_COUNT 256\r
+#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)\r
+#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)\r
+#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)\r
+\r
+#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))\r
\r
// Translation table descriptor types\r
-#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))\r
-#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)\r
-#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)\r
-#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))\r
-#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))\r
-#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)\r
+#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))\r
+#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)\r
+#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)\r
+#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))\r
+#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))\r
+#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)\r
\r
// Translation table descriptor types\r
-#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)\r
-#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)\r
-#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)\r
-#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)\r
-#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)\r
+#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)\r
+#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)\r
+#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)\r
+#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)\r
+#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)\r
\r
// Section descriptor definitions\r
-#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)\r
-\r
-#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)\r
-#define TT_DESCRIPTOR_SECTION_NS (1UL << 19)\r
-\r
-#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)\r
-#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)\r
-#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)\r
-\r
-#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)\r
-#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)\r
-#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)\r
-\r
-#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)\r
-#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)\r
-#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)\r
-\r
-#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)\r
-#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)\r
-#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)\r
-\r
-#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))\r
-\r
-#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))\r
-#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))\r
-#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))\r
-#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))\r
-#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))\r
-#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))\r
-#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))\r
-\r
-#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)\r
-#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)\r
-#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)\r
-\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))\r
-\r
-#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)\r
-\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)\r
+\r
+#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)\r
+#define TT_DESCRIPTOR_SECTION_NS (1UL << 19)\r
+\r
+#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)\r
+#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)\r
+#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)\r
+\r
+#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)\r
+#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)\r
+#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)\r
+\r
+#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)\r
+#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)\r
+#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)\r
+\r
+#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)\r
+#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)\r
+#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)\r
+\r
+#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))\r
+\r
+#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))\r
+#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))\r
+#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))\r
+#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))\r
+#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))\r
+#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))\r
+#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))\r
+\r
+#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)\r
+#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)\r
+#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)\r
+\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))\r
+\r
+#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)\r
+\r
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))\r
#define TT_DESCRIPTOR_PAGE_CACHEABLE_MASK (1UL << 3)\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))\r
-\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))\r
-\r
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)\r
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)\r
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)\r
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc,IsLargePage) ((IsLargePage)? \\r
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))\r
+\r
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))\r
+\r
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)\r
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)\r
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)\r
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc, IsLargePage) ((IsLargePage)?\\r
((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) << 11) & TT_DESCRIPTOR_LARGEPAGE_XN_MASK): \\r
((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK))\r
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \\r
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc, IsLargePage) (IsLargePage? \\r
(((Desc) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK): \\r
(((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))))\r
\r
-#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)\r
+#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)\r
\r
-#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \\r
+#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc, IsLargePage) (IsLargePage? \\r
(((Desc) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK): \\r
(((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2)))))\r
\r
-#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \\r
+#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \\r
TT_DESCRIPTOR_SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \\r
TT_DESCRIPTOR_SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK)\r
\r
-#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \\r
+#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \\r
TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \\r
TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK)\r
\r
-#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)\r
-#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)\r
+#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)\r
+#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)\r
\r
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)\r
-#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)\r
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)\r
-#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20\r
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)\r
+#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)\r
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)\r
+#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20\r
\r
-#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)\r
-#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)\r
-#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)\r
-#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12\r
+#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)\r
+#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)\r
+#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)\r
+#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12\r
\r
-#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \\r
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
TT_DESCRIPTOR_SECTION_S_SHARED | \\r
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)\r
-#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \\r
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
TT_DESCRIPTOR_SECTION_S_SHARED | \\r
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
-#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
+#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \\r
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
TT_DESCRIPTOR_SECTION_XN_MASK | \\r
TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)\r
-#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
+#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \\r
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \\r
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)\r
\r
-#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
+#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
TT_DESCRIPTOR_PAGE_S_SHARED | \\r
TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC)\r
-#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
+#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
TT_DESCRIPTOR_PAGE_S_SHARED | \\r
TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
-#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
+#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
TT_DESCRIPTOR_PAGE_XN_MASK | \\r
TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE)\r
-#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
+#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \\r
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \\r
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \\r
TT_DESCRIPTOR_PAGE_AP_RW_RW | \\r
TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE)\r
\r
// First Level Descriptors\r
-typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;\r
+typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;\r
\r
// Second Level Descriptors\r
-typedef UINT32 ARM_PAGE_TABLE_ENTRY;\r
+typedef UINT32 ARM_PAGE_TABLE_ENTRY;\r
\r
UINT32\r
ConvertSectionAttributesToPageAttributes (\r
#ifndef ARM_MP_CORE_INFO_GUID_H_\r
#define ARM_MP_CORE_INFO_GUID_H_\r
\r
-#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04\r
-#define SCU_CONFIG_REG_OFFSET 0x04\r
-#define MPIDR_U_BIT_MASK 0x40000000\r
+#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04\r
+#define SCU_CONFIG_REG_OFFSET 0x04\r
+#define MPIDR_U_BIT_MASK 0x40000000\r
\r
typedef struct {\r
- UINT32 ClusterId;\r
- UINT32 CoreId;\r
+ UINT32 ClusterId;\r
+ UINT32 CoreId;\r
\r
// MP Core Mailbox\r
- EFI_PHYSICAL_ADDRESS MailboxSetAddress;\r
- EFI_PHYSICAL_ADDRESS MailboxGetAddress;\r
- EFI_PHYSICAL_ADDRESS MailboxClearAddress;\r
- UINT64 MailboxClearValue;\r
+ EFI_PHYSICAL_ADDRESS MailboxSetAddress;\r
+ EFI_PHYSICAL_ADDRESS MailboxGetAddress;\r
+ EFI_PHYSICAL_ADDRESS MailboxClearAddress;\r
+ UINT64 MailboxClearValue;\r
} ARM_CORE_INFO;\r
\r
-typedef struct{\r
- UINT64 Signature;\r
- UINT32 Length;\r
- UINT32 Revision;\r
- UINT64 OemId;\r
- UINT64 OemTableId;\r
- UINTN OemRevision;\r
- UINTN CreatorId;\r
- UINTN CreatorRevision;\r
- EFI_GUID Identifier;\r
- UINTN DataLen;\r
+typedef struct {\r
+ UINT64 Signature;\r
+ UINT32 Length;\r
+ UINT32 Revision;\r
+ UINT64 OemId;\r
+ UINT64 OemTableId;\r
+ UINTN OemRevision;\r
+ UINTN CreatorId;\r
+ UINTN CreatorRevision;\r
+ EFI_GUID Identifier;\r
+ UINTN DataLen;\r
} ARM_PROCESSOR_TABLE_HEADER;\r
\r
typedef struct {\r
- ARM_PROCESSOR_TABLE_HEADER Header;\r
- UINTN NumberOfEntries;\r
- ARM_CORE_INFO *ArmCpus;\r
+ ARM_PROCESSOR_TABLE_HEADER Header;\r
+ UINTN NumberOfEntries;\r
+ ARM_CORE_INFO *ArmCpus;\r
} ARM_PROCESSOR_TABLE;\r
\r
-\r
#define ARM_MP_CORE_INFO_GUID \\r
{ 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
\r
-#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')\r
-#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000 //1.0\r
-#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')\r
-#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')\r
-#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001\r
-#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5\r
-#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001\r
+#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')\r
+#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000// 1.0\r
+#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')\r
+#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')\r
+#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001\r
+#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5\r
+#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001\r
\r
-extern EFI_GUID gArmMpCoreInfoGuid;\r
+extern EFI_GUID gArmMpCoreInfoGuid;\r
\r
#endif /* ARM_MP_CORE_INFO_GUID_H_ */\r
\r
// The ARM Architecture Reference Manual for ARMv8-A defines up\r
// to 7 levels of cache, L1 through L7.\r
-#define MAX_ARM_CACHE_LEVEL 7\r
+#define MAX_ARM_CACHE_LEVEL 7\r
\r
/// Defines the structure of the CSSELR (Cache Size Selection) register\r
typedef union {\r
struct {\r
- UINT32 InD :1; ///< Instruction not Data bit\r
- UINT32 Level :3; ///< Cache level (zero based)\r
- UINT32 TnD :1; ///< Allocation not Data bit\r
- UINT32 Reserved :27; ///< Reserved, RES0\r
- } Bits; ///< Bitfield definition of the register\r
- UINT32 Data; ///< The entire 32-bit value\r
+ UINT32 InD : 1; ///< Instruction not Data bit\r
+ UINT32 Level : 3; ///< Cache level (zero based)\r
+ UINT32 TnD : 1; ///< Allocation not Data bit\r
+ UINT32 Reserved : 27; ///< Reserved, RES0\r
+ } Bits; ///< Bitfield definition of the register\r
+ UINT32 Data; ///< The entire 32-bit value\r
} CSSELR_DATA;\r
\r
/// The cache type values for the InD field of the CSSELR register\r
-typedef enum\r
-{\r
+typedef enum {\r
/// Select the data or unified cache\r
CsselrCacheTypeDataOrUnified = 0,\r
/// Select the instruction cache\r
/// Defines the structure of the CCSIDR (Current Cache Size ID) register\r
typedef union {\r
struct {\r
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)\r
- UINT64 Associativity :10; ///< Associativity - 1\r
- UINT64 NumSets :15; ///< Number of sets in the cache -1\r
- UINT64 Unknown :4; ///< Reserved, UNKNOWN\r
- UINT64 Reserved :32; ///< Reserved, RES0\r
+ UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)\r
+ UINT64 Associativity : 10; ///< Associativity - 1\r
+ UINT64 NumSets : 15; ///< Number of sets in the cache -1\r
+ UINT64 Unknown : 4; ///< Reserved, UNKNOWN\r
+ UINT64 Reserved : 32; ///< Reserved, RES0\r
} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.\r
struct {\r
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)\r
- UINT64 Associativity :21; ///< Associativity - 1\r
- UINT64 Reserved1 :8; ///< Reserved, RES0\r
- UINT64 NumSets :24; ///< Number of sets in the cache -1\r
- UINT64 Reserved2 :8; ///< Reserved, RES0\r
+ UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)\r
+ UINT64 Associativity : 21; ///< Associativity - 1\r
+ UINT64 Reserved1 : 8; ///< Reserved, RES0\r
+ UINT64 NumSets : 24; ///< Number of sets in the cache -1\r
+ UINT64 Reserved2 : 8; ///< Reserved, RES0\r
} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.\r
struct {\r
- UINT64 LineSize : 3;\r
- UINT64 Associativity : 21;\r
- UINT64 Reserved : 8;\r
- UINT64 Unallocated : 32;\r
+ UINT64 LineSize : 3;\r
+ UINT64 Associativity : 21;\r
+ UINT64 Reserved : 8;\r
+ UINT64 Unallocated : 32;\r
} BitsCcidxAA32;\r
- UINT64 Data; ///< The entire 64-bit value\r
+ UINT64 Data; ///< The entire 64-bit value\r
} CCSIDR_DATA;\r
\r
/// Defines the structure of the AARCH32 CCSIDR2 register.\r
typedef union {\r
struct {\r
- UINT32 NumSets :24; ///< Number of sets in the cache - 1\r
- UINT32 Reserved :8; ///< Reserved, RES0\r
- } Bits; ///< Bitfield definition of the register\r
- UINT32 Data; ///< The entire 32-bit value\r
+ UINT32 NumSets : 24; ///< Number of sets in the cache - 1\r
+ UINT32 Reserved : 8; ///< Reserved, RES0\r
+ } Bits; ///< Bitfield definition of the register\r
+ UINT32 Data; ///< The entire 32-bit value\r
} CCSIDR2_DATA;\r
\r
/** Defines the structure of the CLIDR (Cache Level ID) register.\r
**/\r
typedef union {\r
struct {\r
- UINT32 Ctype1 : 3; ///< Level 1 cache type\r
- UINT32 Ctype2 : 3; ///< Level 2 cache type\r
- UINT32 Ctype3 : 3; ///< Level 3 cache type\r
- UINT32 Ctype4 : 3; ///< Level 4 cache type\r
- UINT32 Ctype5 : 3; ///< Level 5 cache type\r
- UINT32 Ctype6 : 3; ///< Level 6 cache type\r
- UINT32 Ctype7 : 3; ///< Level 7 cache type\r
- UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable\r
- UINT32 LoC : 3; ///< Level of Coherency\r
- UINT32 LoUU : 3; ///< Level of Unification Uniprocessor\r
- UINT32 Icb : 3; ///< Inner Cache Boundary\r
- } Bits; ///< Bitfield definition of the register\r
- UINT32 Data; ///< The entire 32-bit value\r
+ UINT32 Ctype1 : 3; ///< Level 1 cache type\r
+ UINT32 Ctype2 : 3; ///< Level 2 cache type\r
+ UINT32 Ctype3 : 3; ///< Level 3 cache type\r
+ UINT32 Ctype4 : 3; ///< Level 4 cache type\r
+ UINT32 Ctype5 : 3; ///< Level 5 cache type\r
+ UINT32 Ctype6 : 3; ///< Level 6 cache type\r
+ UINT32 Ctype7 : 3; ///< Level 7 cache type\r
+ UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable\r
+ UINT32 LoC : 3; ///< Level of Coherency\r
+ UINT32 LoUU : 3; ///< Level of Unification Uniprocessor\r
+ UINT32 Icb : 3; ///< Inner Cache Boundary\r
+ } Bits; ///< Bitfield definition of the register\r
+ UINT32 Data; ///< The entire 32-bit value\r
} CLIDR_DATA;\r
\r
/// The cache types reported in the CLIDR register.\r
ClidrCacheTypeMax\r
} CLIDR_CACHE_TYPE;\r
\r
-#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)\r
+#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)\r
\r
#endif /* ARM_CACHE_H_ */\r
#ifndef ARM_FFA_SVC_H_\r
#define ARM_FFA_SVC_H_\r
\r
-#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063\r
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F\r
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070\r
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F\r
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070\r
+#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070\r
\r
/* Generic IDs when using AArch32 or AArch64 execution state */\r
#ifdef MDE_CPU_AARCH64\r
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64\r
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64\r
#endif\r
#ifdef MDE_CPU_ARM\r
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32\r
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32\r
#endif\r
\r
-#define SPM_MAJOR_VERSION_FFA 1\r
-#define SPM_MINOR_VERSION_FFA 0\r
+#define SPM_MAJOR_VERSION_FFA 1\r
+#define SPM_MINOR_VERSION_FFA 0\r
\r
-#define ARM_FFA_SPM_RET_SUCCESS 0\r
-#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1\r
-#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2\r
-#define ARM_FFA_SPM_RET_NO_MEMORY -3\r
-#define ARM_FFA_SPM_RET_BUSY -4\r
-#define ARM_FFA_SPM_RET_INTERRUPTED -5\r
-#define ARM_FFA_SPM_RET_DENIED -6\r
-#define ARM_FFA_SPM_RET_RETRY -7\r
-#define ARM_FFA_SPM_RET_ABORTED -8\r
+#define ARM_FFA_SPM_RET_SUCCESS 0\r
+#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1\r
+#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2\r
+#define ARM_FFA_SPM_RET_NO_MEMORY -3\r
+#define ARM_FFA_SPM_RET_BUSY -4\r
+#define ARM_FFA_SPM_RET_INTERRUPTED -5\r
+#define ARM_FFA_SPM_RET_DENIED -6\r
+#define ARM_FFA_SPM_RET_RETRY -7\r
+#define ARM_FFA_SPM_RET_ABORTED -8\r
\r
// For now, the destination id to be used in the FF-A calls\r
// is being hard-coded. Subsequently, support will be added\r
// This is the endpoint id used by the optee os's implementation\r
// of the spmc.\r
// https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/kernel/stmm_sp.c#L66\r
-#define ARM_FFA_DESTINATION_ENDPOINT_ID 3\r
+#define ARM_FFA_DESTINATION_ENDPOINT_ID 3\r
\r
#endif // ARM_FFA_SVC_H_\r
* delegated events and request the Secure partition manager to perform\r
* privileged operations on its behalf.\r
*/\r
-#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060\r
-#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061\r
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064\r
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065\r
-#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061\r
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064\r
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065\r
+#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060\r
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061\r
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064\r
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065\r
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061\r
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064\r
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065\r
\r
/* Generic IDs when using AArch32 or AArch64 execution state */\r
#ifdef MDE_CPU_AARCH64\r
-#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64\r
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64\r
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64\r
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64\r
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64\r
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64\r
#endif\r
#ifdef MDE_CPU_ARM\r
-#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32\r
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32\r
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32\r
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32\r
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32\r
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32\r
#endif\r
\r
#define SET_MEM_ATTR_DATA_PERM_MASK 0x3\r
-#define SET_MEM_ATTR_DATA_PERM_SHIFT 0\r
-#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0\r
-#define SET_MEM_ATTR_DATA_PERM_RW 1\r
-#define SET_MEM_ATTR_DATA_PERM_RO 3\r
+#define SET_MEM_ATTR_DATA_PERM_SHIFT 0\r
+#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0\r
+#define SET_MEM_ATTR_DATA_PERM_RW 1\r
+#define SET_MEM_ATTR_DATA_PERM_RO 3\r
\r
#define SET_MEM_ATTR_CODE_PERM_MASK 0x1\r
-#define SET_MEM_ATTR_CODE_PERM_SHIFT 2\r
-#define SET_MEM_ATTR_CODE_PERM_X 0\r
-#define SET_MEM_ATTR_CODE_PERM_XN 1\r
+#define SET_MEM_ATTR_CODE_PERM_SHIFT 2\r
+#define SET_MEM_ATTR_CODE_PERM_X 0\r
+#define SET_MEM_ATTR_CODE_PERM_XN 1\r
\r
#define SET_MEM_ATTR_MAKE_PERM_REQUEST(d_perm, c_perm) \\r
((((c_perm) & SET_MEM_ATTR_CODE_PERM_MASK) << SET_MEM_ATTR_CODE_PERM_SHIFT) | \\r
(( (d_perm) & SET_MEM_ATTR_DATA_PERM_MASK) << SET_MEM_ATTR_DATA_PERM_SHIFT))\r
\r
/* MM SVC Return error codes */\r
-#define ARM_SVC_SPM_RET_SUCCESS 0\r
-#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1\r
-#define ARM_SVC_SPM_RET_INVALID_PARAMS -2\r
-#define ARM_SVC_SPM_RET_DENIED -3\r
-#define ARM_SVC_SPM_RET_NO_MEMORY -5\r
-\r
-#define SPM_MAJOR_VERSION 0\r
-#define SPM_MINOR_VERSION 1\r
+#define ARM_SVC_SPM_RET_SUCCESS 0\r
+#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1\r
+#define ARM_SVC_SPM_RET_INVALID_PARAMS -2\r
+#define ARM_SVC_SPM_RET_DENIED -3\r
+#define ARM_SVC_SPM_RET_NO_MEMORY -5\r
+\r
+#define SPM_MAJOR_VERSION 0\r
+#define SPM_MINOR_VERSION 1\r
\r
#endif // ARM_MM_SVC_H_\r
* SMC function IDs for Standard Service queries\r
*/\r
\r
-#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00\r
-#define ARM_SMC_ID_STD_UID 0x8400ff01\r
+#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00\r
+#define ARM_SMC_ID_STD_UID 0x8400ff01\r
/* 0x8400ff02 is reserved */\r
-#define ARM_SMC_ID_STD_REVISION 0x8400ff03\r
+#define ARM_SMC_ID_STD_REVISION 0x8400ff03\r
\r
/*\r
* The 'Standard Service Call UID' is supposed to return the Standard\r
* Service UUID. This is a 128-bit value.\r
*/\r
-#define ARM_SMC_STD_UUID0 0x108d905b\r
-#define ARM_SMC_STD_UUID1 0x47e8f863\r
-#define ARM_SMC_STD_UUID2 0xfbc02dae\r
-#define ARM_SMC_STD_UUID3 0xe2f64156\r
+#define ARM_SMC_STD_UUID0 0x108d905b\r
+#define ARM_SMC_STD_UUID1 0x47e8f863\r
+#define ARM_SMC_STD_UUID2 0xfbc02dae\r
+#define ARM_SMC_STD_UUID3 0xe2f64156\r
\r
/*\r
* ARM Standard Service Calls revision numbers\r
* The current revision is: 0.1\r
*/\r
-#define ARM_SMC_STD_REVISION_MAJOR 0x0\r
-#define ARM_SMC_STD_REVISION_MINOR 0x1\r
+#define ARM_SMC_STD_REVISION_MAJOR 0x0\r
+#define ARM_SMC_STD_REVISION_MINOR 0x1\r
\r
/*\r
* Management Mode (MM) calls cover a subset of the Standard Service Call range.\r
* The list below is not exhaustive.\r
*/\r
-#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040\r
-#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040\r
+#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040\r
+#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040\r
\r
// Request service from secure standalone MM environment\r
-#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041\r
-#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041\r
+#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041\r
+#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041\r
\r
/* Generic ID when using AArch32 or AArch64 execution state */\r
#ifdef MDE_CPU_AARCH64\r
-#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64\r
+#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64\r
#endif\r
#ifdef MDE_CPU_ARM\r
-#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32\r
+#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32\r
#endif\r
\r
/* MM return error codes */\r
-#define ARM_SMC_MM_RET_SUCCESS 0\r
-#define ARM_SMC_MM_RET_NOT_SUPPORTED -1\r
-#define ARM_SMC_MM_RET_INVALID_PARAMS -2\r
-#define ARM_SMC_MM_RET_DENIED -3\r
-#define ARM_SMC_MM_RET_NO_MEMORY -4\r
+#define ARM_SMC_MM_RET_SUCCESS 0\r
+#define ARM_SMC_MM_RET_NOT_SUPPORTED -1\r
+#define ARM_SMC_MM_RET_INVALID_PARAMS -2\r
+#define ARM_SMC_MM_RET_DENIED -3\r
+#define ARM_SMC_MM_RET_NO_MEMORY -4\r
\r
// ARM Architecture Calls\r
-#define SMCCC_VERSION 0x80000000\r
-#define SMCCC_ARCH_FEATURES 0x80000001\r
-#define SMCCC_ARCH_SOC_ID 0x80000002\r
-#define SMCCC_ARCH_WORKAROUND_1 0x80008000\r
-#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF\r
+#define SMCCC_VERSION 0x80000000\r
+#define SMCCC_ARCH_FEATURES 0x80000001\r
+#define SMCCC_ARCH_SOC_ID 0x80000002\r
+#define SMCCC_ARCH_WORKAROUND_1 0x80008000\r
+#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF\r
\r
#define SMC_ARCH_CALL_SUCCESS 0\r
-#define SMC_ARCH_CALL_NOT_SUPPORTED -1\r
-#define SMC_ARCH_CALL_NOT_REQUIRED -2\r
-#define SMC_ARCH_CALL_INVALID_PARAMETER -3\r
+#define SMC_ARCH_CALL_NOT_SUPPORTED -1\r
+#define SMC_ARCH_CALL_NOT_REQUIRED -2\r
+#define SMC_ARCH_CALL_INVALID_PARAMETER -3\r
\r
/*\r
* Power State Coordination Interface (PSCI) calls cover a subset of the\r
((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)\r
\r
/* PSCI return error codes */\r
-#define ARM_SMC_PSCI_RET_SUCCESS 0\r
-#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1\r
-#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2\r
-#define ARM_SMC_PSCI_RET_DENIED -3\r
-#define ARM_SMC_PSCI_RET_ALREADY_ON -4\r
-#define ARM_SMC_PSCI_RET_ON_PENDING -5\r
-#define ARM_SMC_PSCI_RET_INTERN_FAIL -6\r
-#define ARM_SMC_PSCI_RET_NOT_PRESENT -7\r
-#define ARM_SMC_PSCI_RET_DISABLED -8\r
+#define ARM_SMC_PSCI_RET_SUCCESS 0\r
+#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1\r
+#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2\r
+#define ARM_SMC_PSCI_RET_DENIED -3\r
+#define ARM_SMC_PSCI_RET_ALREADY_ON -4\r
+#define ARM_SMC_PSCI_RET_ON_PENDING -5\r
+#define ARM_SMC_PSCI_RET_INTERN_FAIL -6\r
+#define ARM_SMC_PSCI_RET_NOT_PRESENT -7\r
+#define ARM_SMC_PSCI_RET_DISABLED -8\r
\r
#define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \\r
((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))\r
#define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF)\r
#define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF)\r
\r
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0\r
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1\r
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2\r
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3\r
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0\r
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1\r
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2\r
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3\r
\r
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0\r
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1\r
/*\r
* SMC function IDs for Trusted OS Service queries\r
*/\r
-#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00\r
-#define ARM_SMC_ID_TOS_UID 0xbf00ff01\r
+#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00\r
+#define ARM_SMC_ID_TOS_UID 0xbf00ff01\r
/* 0xbf00ff02 is reserved */\r
-#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03\r
+#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03\r
\r
#endif // ARM_STD_SMC_H_\r
**/\r
VOID\r
DisassembleInstruction (\r
- IN UINT8 **OpCodePtr,\r
- IN BOOLEAN Thumb,\r
- IN BOOLEAN Extended,\r
- IN OUT UINT32 *ItBlock,\r
- OUT CHAR8 *Buf,\r
- OUT UINTN Size\r
+ IN UINT8 **OpCodePtr,\r
+ IN BOOLEAN Thumb,\r
+ IN BOOLEAN Extended,\r
+ IN OUT UINT32 *ItBlock,\r
+ OUT CHAR8 *Buf,\r
+ OUT UINTN Size\r
);\r
\r
#endif // ARM_DISASSEMBLER_LIB_H_\r
VOID\r
EFIAPI\r
ArmGenericTimerSetTimerVal (\r
- IN UINTN Value\r
+ IN UINTN Value\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmGenericTimerSetTimerCtrlReg (\r
- UINTN Value\r
+ UINTN Value\r
);\r
\r
UINT64\r
VOID\r
EFIAPI\r
ArmGenericTimerSetCompareVal (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
);\r
\r
#endif // ARM_GENERIC_TIMER_COUNTER_LIB_H_\r
ARM_GIC_ARCH_REVISION_3\r
} ARM_GIC_ARCH_REVISION;\r
\r
-\r
ARM_GIC_ARCH_REVISION\r
EFIAPI\r
ArmGicGetSupportedArchRevision (\r
#include <Library/ArmGicArchLib.h>\r
\r
// GIC Distributor\r
-#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r
-#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
-#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r
+#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r
+#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
+#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r
\r
// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r
-#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r
-#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
-#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
-#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r
-#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
-#define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r
+#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r
+#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
+#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
+#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r
+#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
+#define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r
\r
// Each reg base below repeats for Number of interrupts / 4\r
-#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
+#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
\r
// Each reg base below repeats for Number of interrupts\r
-#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
-#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
+#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
+#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
\r
-#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r
+#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r
\r
// just one of these\r
-#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
+#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
\r
// GICv3 specific registers\r
-#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers\r
+#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers\r
\r
// GICD_CTLR bits\r
-#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)\r
-#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)\r
+#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)\r
+#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)\r
\r
// GICD_ICDICFR bits\r
#define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register\r
#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt\r
#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt\r
\r
-\r
// GIC Redistributor\r
-#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB\r
-#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
-#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB\r
-#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB\r
+#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB\r
+#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
+#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB\r
+#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB\r
\r
// GIC Redistributor Control frame\r
-#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register\r
+#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register\r
\r
// GIC Redistributor TYPER bit assignments\r
-#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs\r
-#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs\r
-#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs\r
-#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series\r
-#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group\r
+#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs\r
+#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs\r
+#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs\r
+#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series\r
+#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group\r
// Selection Support\r
-#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number\r
-#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity\r
-#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity\r
+#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number\r
+#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity\r
+#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity\r
\r
#define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \\r
ARM_GICR_TYPER_AFFINITY) >> 32)\r
\r
// GIC SGI & PPI Redistributor frame\r
-#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers\r
-#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers\r
+#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers\r
+#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers\r
\r
// GIC Cpu interface\r
-#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r
-#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
-#define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r
-#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r
-#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r
-#define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r
-#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
-#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
-#define ARM_GIC_ICCIIDR 0xFC // Identification Register\r
-\r
-#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r
-#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r
-#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2\r
+#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r
+#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
+#define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r
+#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r
+#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r
+#define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r
+#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
+#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
+#define ARM_GIC_ICCIIDR 0xFC // Identification Register\r
+\r
+#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r
+#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r
+#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2\r
\r
// Bit-masks to configure the CPU Interface Control register\r
-#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01\r
-#define ARM_GIC_ICCICR_ENABLE_NS 0x02\r
-#define ARM_GIC_ICCICR_ACK_CTL 0x04\r
-#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r
-#define ARM_GIC_ICCICR_USE_SBPR 0x10\r
+#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01\r
+#define ARM_GIC_ICCICR_ENABLE_NS 0x02\r
+#define ARM_GIC_ICCICR_ACK_CTL 0x04\r
+#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r
+#define ARM_GIC_ICCICR_USE_SBPR 0x10\r
\r
// Bit Mask for GICC_IIDR\r
-#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)\r
-#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r
-#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r
-#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r
+#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)\r
+#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r
+#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r
+#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r
\r
// Bit Mask for\r
-#define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r
+#define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r
\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
);\r
\r
// GIC Secure interfaces\r
VOID\r
EFIAPI\r
ArmGicSetupNonSecure (\r
- IN UINTN MpId,\r
- IN INTN GicDistributorBase,\r
- IN INTN GicInterruptInterfaceBase\r
+ IN UINTN MpId,\r
+ IN INTN GicDistributorBase,\r
+ IN INTN GicInterruptInterfaceBase\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicSetSecureInterrupts (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN* GicSecureInterruptMask,\r
- IN UINTN GicSecureInterruptMaskSize\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN *GicSecureInterruptMask,\r
+ IN UINTN GicSecureInterruptMaskSize\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicDisableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicEnableDistributor (\r
- IN INTN GicDistributorBase\r
+ IN INTN GicDistributorBase\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicDisableDistributor (\r
- IN INTN GicDistributorBase\r
+ IN INTN GicDistributorBase\r
);\r
\r
UINTN\r
EFIAPI\r
ArmGicGetMaxNumInterrupts (\r
- IN INTN GicDistributorBase\r
+ IN INTN GicDistributorBase\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicSendSgiTo (\r
- IN INTN GicDistributorBase,\r
- IN INTN TargetListFilter,\r
- IN INTN CPUTargetList,\r
- IN INTN SgiId\r
+ IN INTN GicDistributorBase,\r
+ IN INTN TargetListFilter,\r
+ IN INTN CPUTargetList,\r
+ IN INTN SgiId\r
);\r
\r
/*\r
UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
- IN UINTN GicInterruptInterfaceBase,\r
- OUT UINTN *InterruptId\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ OUT UINTN *InterruptId\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicEndOfInterrupt (\r
- IN UINTN GicInterruptInterfaceBase,\r
- IN UINTN Source\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ IN UINTN Source\r
);\r
\r
UINTN\r
EFIAPI\r
ArmGicSetPriorityMask (\r
- IN INTN GicInterruptInterfaceBase,\r
- IN INTN PriorityMask\r
+ IN INTN GicInterruptInterfaceBase,\r
+ IN INTN PriorityMask\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicSetInterruptPriority (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicRedistributorBase,\r
- IN UINTN Source,\r
- IN UINTN Priority\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source,\r
+ IN UINTN Priority\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterrupt (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicRedistributorBase,\r
- IN UINTN Source\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicDisableInterrupt (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicRedistributorBase,\r
- IN UINTN Source\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source\r
);\r
\r
BOOLEAN\r
EFIAPI\r
ArmGicIsInterruptEnabled (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicRedistributorBase,\r
- IN UINTN Source\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicRedistributorBase,\r
+ IN UINTN Source\r
);\r
\r
// GIC revision 2 specific declarations\r
VOID\r
EFIAPI\r
ArmGicV2SetupNonSecure (\r
- IN UINTN MpId,\r
- IN INTN GicDistributorBase,\r
- IN INTN GicInterruptInterfaceBase\r
+ IN UINTN MpId,\r
+ IN INTN GicDistributorBase,\r
+ IN INTN GicInterruptInterfaceBase\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicV2EnableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicV2DisableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
+ IN INTN GicInterruptInterfaceBase\r
);\r
\r
UINTN\r
EFIAPI\r
ArmGicV2AcknowledgeInterrupt (\r
- IN UINTN GicInterruptInterfaceBase\r
+ IN UINTN GicInterruptInterfaceBase\r
);\r
\r
VOID\r
EFIAPI\r
ArmGicV2EndOfInterrupt (\r
- IN UINTN GicInterruptInterfaceBase,\r
- IN UINTN Source\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ IN UINTN Source\r
);\r
\r
// GIC revision 3 specific declarations\r
\r
-#define ICC_SRE_EL2_SRE (1 << 0)\r
+#define ICC_SRE_EL2_SRE (1 << 0)\r
\r
-#define ARM_GICD_IROUTER_IRM BIT31\r
+#define ARM_GICD_IROUTER_IRM BIT31\r
\r
UINT32\r
EFIAPI\r
VOID\r
EFIAPI\r
ArmGicV3SetControlSystemRegisterEnable (\r
- IN UINT32 ControlSystemRegisterEnable\r
+ IN UINT32 ControlSystemRegisterEnable\r
);\r
\r
VOID\r
VOID\r
EFIAPI\r
ArmGicV3EndOfInterrupt (\r
- IN UINTN Source\r
+ IN UINTN Source\r
);\r
\r
VOID\r
ArmGicV3SetBinaryPointer (\r
- IN UINTN BinaryPoint\r
+ IN UINTN BinaryPoint\r
);\r
\r
VOID\r
ArmGicV3SetPriorityMask (\r
- IN UINTN Priority\r
+ IN UINTN Priority\r
);\r
\r
#endif // ARMGIC_H_\r
* The native size is used for the arguments.\r
*/\r
typedef struct {\r
- UINTN Arg0;\r
- UINTN Arg1;\r
- UINTN Arg2;\r
- UINTN Arg3;\r
- UINTN Arg4;\r
- UINTN Arg5;\r
- UINTN Arg6;\r
- UINTN Arg7;\r
+ UINTN Arg0;\r
+ UINTN Arg1;\r
+ UINTN Arg2;\r
+ UINTN Arg3;\r
+ UINTN Arg4;\r
+ UINTN Arg5;\r
+ UINTN Arg6;\r
+ UINTN Arg7;\r
} ARM_HVC_ARGS;\r
\r
/**\r
**/\r
VOID\r
ArmCallHvc (\r
- IN OUT ARM_HVC_ARGS *Args\r
+ IN OUT ARM_HVC_ARGS *Args\r
);\r
\r
#endif // ARM_HVC_LIB_H_\r
\r
#ifdef MDE_CPU_ARM\r
#include <Chipset/ArmV7.h>\r
-#elif defined(MDE_CPU_AARCH64)\r
+#elif defined (MDE_CPU_AARCH64)\r
#include <Chipset/AArch64.h>\r
#else\r
- #error "Unknown chipset."\r
+ #error "Unknown chipset."\r
#endif\r
\r
-#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
+#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
EFI_MEMORY_UCE)\r
\r
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
} ARM_MEMORY_REGION_ATTRIBUTES;\r
\r
-#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
+#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
\r
typedef struct {\r
- EFI_PHYSICAL_ADDRESS PhysicalBase;\r
- EFI_VIRTUAL_ADDRESS VirtualBase;\r
- UINT64 Length;\r
- ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
+ EFI_PHYSICAL_ADDRESS PhysicalBase;\r
+ EFI_VIRTUAL_ADDRESS VirtualBase;\r
+ UINT64 Length;\r
+ ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
-typedef VOID (*CACHE_OPERATION)(VOID);\r
-typedef VOID (*LINE_OPERATION)(UINTN);\r
+typedef VOID (*CACHE_OPERATION)(\r
+ VOID\r
+ );\r
+typedef VOID (*LINE_OPERATION)(\r
+ UINTN\r
+ );\r
\r
//\r
// ARM Processor Mode\r
//\r
// ARM Cpu IDs\r
//\r
-#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
-#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
-#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
-#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
-#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
-#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
-\r
-#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
-#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
+#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
+#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
+#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
+#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
+#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
+#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
+\r
+#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
\r
//\r
// ARM MP Core IDs\r
//\r
-#define ARM_CORE_AFF0 0xFF\r
-#define ARM_CORE_AFF1 (0xFF << 8)\r
-#define ARM_CORE_AFF2 (0xFF << 16)\r
-#define ARM_CORE_AFF3 (0xFFULL << 32)\r
-\r
-#define ARM_CORE_MASK ARM_CORE_AFF0\r
-#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
-#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
-#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
-#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
-#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
+#define ARM_CORE_AFF0 0xFF\r
+#define ARM_CORE_AFF1 (0xFF << 8)\r
+#define ARM_CORE_AFF2 (0xFF << 16)\r
+#define ARM_CORE_AFF3 (0xFFULL << 32)\r
+\r
+#define ARM_CORE_MASK ARM_CORE_AFF0\r
+#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
+#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
+#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
+#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
+#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
/** Reads the CCSIDR register for the specified cache.\r
\r
**/\r
UINTN\r
ReadCCSIDR (\r
- IN UINT32 CSSELR\r
+ IN UINT32 CSSELR\r
);\r
\r
/** Reads the CCSIDR2 for the specified cache.\r
**/\r
UINT32\r
ReadCCSIDR2 (\r
- IN UINT32 CSSELR\r
+ IN UINT32 CSSELR\r
);\r
\r
/** Reads the Cache Level ID (CLIDR) register.\r
VOID\r
);\r
\r
-\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCache (\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryByMVA (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryToPoUByMVA (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryByMVA (\r
-IN UINTN Address\r
-);\r
+ IN UINTN Address\r
+ );\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryByMVA (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
VOID\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
- IN VOID *TranslationTableEntry,\r
- IN VOID *Mva\r
+ IN VOID *TranslationTableEntry,\r
+ IN VOID *Mva\r
);\r
\r
VOID\r
VOID\r
EFIAPI\r
ArmSetTTBCR (\r
- IN UINT32 Bits\r
+ IN UINT32 Bits\r
);\r
\r
VOID *\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
- IN UINTN VectorBase\r
+ IN UINTN VectorBase\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmWriteAuxCr (\r
- IN UINT32 Bit\r
+ IN UINT32 Bit\r
);\r
\r
UINT32\r
VOID\r
EFIAPI\r
ArmSetAuxCrBit (\r
- IN UINT32 Bits\r
+ IN UINT32 Bits\r
);\r
\r
VOID\r
EFIAPI\r
ArmUnsetAuxCrBit (\r
- IN UINT32 Bits\r
+ IN UINT32 Bits\r
);\r
\r
VOID\r
VOID\r
EFIAPI\r
ArmWriteCpacr (\r
- IN UINT32 Access\r
+ IN UINT32 Access\r
);\r
\r
VOID\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
- IN UINT32 Value\r
+ IN UINT32 Value\r
);\r
\r
UINT32\r
VOID\r
EFIAPI\r
ArmWriteMVBar (\r
- IN UINT32 VectorMonitorBase\r
+ IN UINT32 VectorMonitorBase\r
);\r
\r
UINT32\r
VOID\r
EFIAPI\r
ArmWriteSctlr (\r
- IN UINT32 Value\r
+ IN UINT32 Value\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmWriteHVBar (\r
- IN UINTN HypModeVectorBase\r
+ IN UINTN HypModeVectorBase\r
);\r
\r
-\r
//\r
// Helper functions for accessing CPU ACTLR\r
//\r
VOID\r
EFIAPI\r
ArmWriteCpuActlr (\r
- IN UINTN Val\r
+ IN UINTN Val\r
);\r
\r
VOID\r
EFIAPI\r
ArmSetCpuActlrBit (\r
- IN UINTN Bits\r
+ IN UINTN Bits\r
);\r
\r
VOID\r
EFIAPI\r
ArmUnsetCpuActlrBit (\r
- IN UINTN Bits\r
+ IN UINTN Bits\r
);\r
\r
//\r
// Accessors for the architected generic timer registers\r
//\r
\r
-#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
-#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
-#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
+#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
+#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
+#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
\r
UINTN\r
EFIAPI\r
VOID\r
EFIAPI\r
ArmWriteCntFrq (\r
- UINTN FreqInHz\r
+ UINTN FreqInHz\r
);\r
\r
UINT64\r
VOID\r
EFIAPI\r
ArmWriteCntkCtl (\r
- UINTN Val\r
+ UINTN Val\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmWriteCntpTval (\r
- UINTN Val\r
+ UINTN Val\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmWriteCntpCtl (\r
- UINTN Val\r
+ UINTN Val\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmWriteCntvTval (\r
- UINTN Val\r
+ UINTN Val\r
);\r
\r
UINTN\r
VOID\r
EFIAPI\r
ArmWriteCntvCtl (\r
- UINTN Val\r
+ UINTN Val\r
);\r
\r
UINT64\r
VOID\r
EFIAPI\r
ArmWriteCntpCval (\r
- UINT64 Val\r
+ UINT64 Val\r
);\r
\r
UINT64\r
VOID\r
EFIAPI\r
ArmWriteCntvCval (\r
- UINT64 Val\r
+ UINT64 Val\r
);\r
\r
UINT64\r
VOID\r
EFIAPI\r
ArmWriteCntvOff (\r
- UINT64 Val\r
+ UINT64 Val\r
);\r
\r
UINTN\r
VOID\r
);\r
\r
-\r
///\r
/// ID Register Helper functions\r
///\r
///\r
/// AArch32-only ID Register Helper functions\r
///\r
+\r
/**\r
Check whether the CPU supports the Security extensions\r
\r
ArmHasSecurityExtensions (\r
VOID\r
);\r
+\r
#endif // MDE_CPU_ARM\r
\r
#endif // ARM_LIB_H_\r
EFI_STATUS\r
EFIAPI\r
ArmSetMemoryRegionNoExec (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
EFI_STATUS\r
EFIAPI\r
ArmClearMemoryRegionNoExec (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
EFI_STATUS\r
EFIAPI\r
ArmSetMemoryRegionReadOnly (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
EFI_STATUS\r
EFIAPI\r
ArmClearMemoryRegionReadOnly (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
VOID\r
\r
EFI_STATUS\r
ArmSetMemoryAttributes (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
);\r
\r
#endif // ARM_MMU_LIB_H_\r
#pragma pack(1)\r
\r
typedef struct {\r
- UINT32 Reserved1;\r
- UINT32 ChannelStatus;\r
- UINT64 Reserved2;\r
- UINT32 Flags;\r
- UINT32 Length;\r
- UINT32 MessageHeader;\r
+ UINT32 Reserved1;\r
+ UINT32 ChannelStatus;\r
+ UINT64 Reserved2;\r
+ UINT32 Flags;\r
+ UINT32 Length;\r
+ UINT32 MessageHeader;\r
\r
// NOTE: Since EDK2 does not allow flexible array member [] we declare\r
// here array of 1 element length. However below is used as a variable\r
// length array.\r
- UINT32 Payload[1]; // size less object gives offset to payload.\r
+ UINT32 Payload[1]; // size less object gives offset to payload.\r
} MTL_MAILBOX;\r
\r
#pragma pack()\r
\r
// Channel Type, Low-priority, and High-priority\r
typedef enum {\r
- MTL_CHANNEL_TYPE_LOW = 0,\r
+ MTL_CHANNEL_TYPE_LOW = 0,\r
MTL_CHANNEL_TYPE_HIGH = 1\r
} MTL_CHANNEL_TYPE;\r
\r
typedef struct {\r
- UINT64 PhysicalAddress;\r
- UINT32 ModifyMask;\r
- UINT32 PreserveMask;\r
+ UINT64 PhysicalAddress;\r
+ UINT32 ModifyMask;\r
+ UINT32 PreserveMask;\r
} MTL_DOORBELL;\r
\r
typedef struct {\r
- MTL_CHANNEL_TYPE ChannelType;\r
- MTL_MAILBOX * CONST MailBox;\r
- MTL_DOORBELL DoorBell;\r
+ MTL_CHANNEL_TYPE ChannelType;\r
+ MTL_MAILBOX *CONST MailBox;\r
+ MTL_DOORBELL DoorBell;\r
} MTL_CHANNEL;\r
\r
/** Wait until channel is free.\r
\r
@retval UINT32* Pointer to the payload.\r
**/\r
-UINT32*\r
+UINT32 *\r
MtlGetChannelPayload (\r
IN MTL_CHANNEL *Channel\r
);\r
OUT UINT32 *PayloadLength\r
);\r
\r
-#endif /* ARM_MTL_LIB_H_ */\r
-\r
+#endif /* ARM_MTL_LIB_H_ */\r
* The native size is used for the arguments.\r
*/\r
typedef struct {\r
- UINTN Arg0;\r
- UINTN Arg1;\r
- UINTN Arg2;\r
- UINTN Arg3;\r
- UINTN Arg4;\r
- UINTN Arg5;\r
- UINTN Arg6;\r
- UINTN Arg7;\r
+ UINTN Arg0;\r
+ UINTN Arg1;\r
+ UINTN Arg2;\r
+ UINTN Arg3;\r
+ UINTN Arg4;\r
+ UINTN Arg5;\r
+ UINTN Arg6;\r
+ UINTN Arg7;\r
} ARM_SMC_ARGS;\r
\r
/**\r
**/\r
VOID\r
ArmCallSmc (\r
- IN OUT ARM_SMC_ARGS *Args\r
+ IN OUT ARM_SMC_ARGS *Args\r
);\r
\r
#endif // ARM_SMC_LIB_H_\r
* The native size is used for the arguments.\r
*/\r
typedef struct {\r
- UINTN Arg0;\r
- UINTN Arg1;\r
- UINTN Arg2;\r
- UINTN Arg3;\r
- UINTN Arg4;\r
- UINTN Arg5;\r
- UINTN Arg6;\r
- UINTN Arg7;\r
+ UINTN Arg0;\r
+ UINTN Arg1;\r
+ UINTN Arg2;\r
+ UINTN Arg3;\r
+ UINTN Arg4;\r
+ UINTN Arg5;\r
+ UINTN Arg6;\r
+ UINTN Arg7;\r
} ARM_SVC_ARGS;\r
\r
/**\r
**/\r
VOID\r
ArmCallSvc (\r
- IN OUT ARM_SVC_ARGS *Args\r
+ IN OUT ARM_SVC_ARGS *Args\r
);\r
\r
#endif // ARM_SVC_LIB_H_\r
**/\r
VOID\r
DefaultExceptionHandler (\r
- IN EFI_EXCEPTION_TYPE ExceptionType,\r
- IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
+ IN EFI_EXCEPTION_TYPE ExceptionType,\r
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
);\r
\r
#endif // DEFAULT_EXCEPTION_HANDLER_LIB_H_\r
*\r
**/\r
\r
-\r
#ifndef OEM_MISC_LIB_H_\r
#define OEM_MISC_LIB_H_\r
\r
#include <Uefi.h>\r
#include <IndustryStandard/SmBios.h>\r
\r
-typedef enum\r
-{\r
+typedef enum {\r
CpuCacheL1 = 1,\r
CpuCacheL2,\r
CpuCacheL3,\r
CpuCacheLevelMax\r
} OEM_MISC_CPU_CACHE_LEVEL;\r
\r
-typedef struct\r
-{\r
- UINT8 Voltage; ///< Processor voltage\r
- UINT16 CurrentSpeed; ///< Current clock speed in MHz\r
- UINT16 MaxSpeed; ///< Maximum clock speed in MHz\r
- UINT16 ExternalClock; ///< External clock speed in MHz\r
- UINT16 CoreCount; ///< Number of cores available\r
- UINT16 CoresEnabled; ///< Number of cores enabled\r
- UINT16 ThreadCount; ///< Number of threads per processor\r
+typedef struct {\r
+ UINT8 Voltage; ///< Processor voltage\r
+ UINT16 CurrentSpeed; ///< Current clock speed in MHz\r
+ UINT16 MaxSpeed; ///< Maximum clock speed in MHz\r
+ UINT16 ExternalClock; ///< External clock speed in MHz\r
+ UINT16 CoreCount; ///< Number of cores available\r
+ UINT16 CoresEnabled; ///< Number of cores enabled\r
+ UINT16 ThreadCount; ///< Number of threads per processor\r
} OEM_MISC_PROCESSOR_DATA;\r
\r
-typedef enum\r
-{\r
- ProductNameType01,\r
- SerialNumType01,\r
- UuidType01,\r
- SystemManufacturerType01,\r
- SkuNumberType01,\r
- FamilyType01,\r
- AssertTagType02,\r
- SerialNumberType02,\r
- BoardManufacturerType02,\r
- SkuNumberType02,\r
- ChassisLocationType02,\r
- AssetTagType03,\r
- SerialNumberType03,\r
- VersionType03,\r
- ChassisTypeType03,\r
- ManufacturerType03,\r
- SkuNumberType03,\r
- SmbiosHiiStringFieldMax\r
+typedef enum {\r
+ ProductNameType01,\r
+ SerialNumType01,\r
+ UuidType01,\r
+ SystemManufacturerType01,\r
+ SkuNumberType01,\r
+ FamilyType01,\r
+ AssertTagType02,\r
+ SerialNumberType02,\r
+ BoardManufacturerType02,\r
+ SkuNumberType02,\r
+ ChassisLocationType02,\r
+ AssetTagType03,\r
+ SerialNumberType03,\r
+ VersionType03,\r
+ ChassisTypeType03,\r
+ ManufacturerType03,\r
+ SkuNumberType03,\r
+ SmbiosHiiStringFieldMax\r
} OEM_MISC_SMBIOS_HII_STRING_FIELD;\r
\r
/*\r
UINTN\r
EFIAPI\r
OemGetCpuFreq (\r
- IN UINT8 ProcessorIndex\r
+ IN UINT8 ProcessorIndex\r
);\r
\r
/** Gets information about the specified processor and stores it in\r
BOOLEAN\r
EFIAPI\r
OemGetProcessorInformation (\r
- IN UINTN ProcessorIndex,\r
- IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,\r
- IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,\r
- IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData\r
+ IN UINTN ProcessorIndex,\r
+ IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,\r
+ IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,\r
+ IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData\r
);\r
\r
/** Gets information about the cache at the specified cache level.\r
BOOLEAN\r
EFIAPI\r
OemGetCacheInformation (\r
- IN UINT8 ProcessorIndex,\r
- IN UINT8 CacheLevel,\r
- IN BOOLEAN DataCache,\r
- IN BOOLEAN UnifiedCache,\r
- IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable\r
+ IN UINT8 ProcessorIndex,\r
+ IN UINT8 CacheLevel,\r
+ IN BOOLEAN DataCache,\r
+ IN BOOLEAN UnifiedCache,\r
+ IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable\r
);\r
\r
/** Gets the maximum number of processors supported by the platform.\r
BOOLEAN\r
EFIAPI\r
OemIsProcessorPresent (\r
- IN UINTN ProcessorIndex\r
+ IN UINTN ProcessorIndex\r
);\r
\r
/** Updates the HII string for the specified field.\r
VOID\r
EFIAPI\r
OemUpdateSmbiosInfo (\r
- IN EFI_HII_HANDLE HiiHandle,\r
- IN EFI_STRING_ID TokenToUpdate,\r
- IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field\r
+ IN EFI_HII_HANDLE HiiHandle,\r
+ IN EFI_STRING_ID TokenToUpdate,\r
+ IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field\r
);\r
\r
/** Fetches the Type 32 boot information status.\r
* The 'Trusted OS Call UID' is supposed to return the following UUID for\r
* OP-TEE OS. This is a 128-bit value.\r
*/\r
-#define OPTEE_OS_UID0 0x384fb3e0\r
-#define OPTEE_OS_UID1 0xe7f811e3\r
-#define OPTEE_OS_UID2 0xaf630002\r
-#define OPTEE_OS_UID3 0xa5d5c51b\r
+#define OPTEE_OS_UID0 0x384fb3e0\r
+#define OPTEE_OS_UID1 0xe7f811e3\r
+#define OPTEE_OS_UID2 0xaf630002\r
+#define OPTEE_OS_UID3 0xa5d5c51b\r
\r
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE 0x0\r
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT 0x1\r
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT 0x2\r
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT 0x3\r
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT 0x9\r
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT 0xa\r
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT 0xb\r
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE 0x0\r
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT 0x1\r
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT 0x2\r
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT 0x3\r
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT 0x9\r
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT 0xa\r
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT 0xb\r
\r
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK 0xff\r
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK 0xff\r
\r
-#define OPTEE_SUCCESS 0x00000000\r
-#define OPTEE_ORIGIN_COMMUNICATION 0x00000002\r
-#define OPTEE_ERROR_COMMUNICATION 0xFFFF000E\r
+#define OPTEE_SUCCESS 0x00000000\r
+#define OPTEE_ORIGIN_COMMUNICATION 0x00000002\r
+#define OPTEE_ERROR_COMMUNICATION 0xFFFF000E\r
\r
typedef struct {\r
UINT64 BufferAddress;\r
} OPTEE_MESSAGE_PARAM_VALUE;\r
\r
typedef union {\r
- OPTEE_MESSAGE_PARAM_MEMORY Memory;\r
- OPTEE_MESSAGE_PARAM_VALUE Value;\r
+ OPTEE_MESSAGE_PARAM_MEMORY Memory;\r
+ OPTEE_MESSAGE_PARAM_VALUE Value;\r
} OPTEE_MESSAGE_PARAM_UNION;\r
\r
typedef struct {\r
- UINT64 Attribute;\r
- OPTEE_MESSAGE_PARAM_UNION Union;\r
+ UINT64 Attribute;\r
+ OPTEE_MESSAGE_PARAM_UNION Union;\r
} OPTEE_MESSAGE_PARAM;\r
\r
-#define OPTEE_MAX_CALL_PARAMS 4\r
+#define OPTEE_MAX_CALL_PARAMS 4\r
\r
typedef struct {\r
- UINT32 Command;\r
- UINT32 Function;\r
- UINT32 Session;\r
- UINT32 CancelId;\r
- UINT32 Pad;\r
- UINT32 Return;\r
- UINT32 ReturnOrigin;\r
- UINT32 NumParams;\r
+ UINT32 Command;\r
+ UINT32 Function;\r
+ UINT32 Session;\r
+ UINT32 CancelId;\r
+ UINT32 Pad;\r
+ UINT32 Return;\r
+ UINT32 ReturnOrigin;\r
+ UINT32 NumParams;\r
\r
// NumParams tells the actual number of element in Params\r
- OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS];\r
+ OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS];\r
} OPTEE_MESSAGE_ARG;\r
\r
typedef struct {\r
- EFI_GUID Uuid; // [in] GUID/UUID of the Trusted Application\r
- UINT32 Session; // [out] Session id\r
- UINT32 Return; // [out] Return value\r
- UINT32 ReturnOrigin; // [out] Origin of the return value\r
+ EFI_GUID Uuid; // [in] GUID/UUID of the Trusted Application\r
+ UINT32 Session; // [out] Session id\r
+ UINT32 Return; // [out] Return value\r
+ UINT32 ReturnOrigin; // [out] Origin of the return value\r
} OPTEE_OPEN_SESSION_ARG;\r
\r
typedef struct {\r
- UINT32 Function; // [in] Trusted Application function, specific to the TA\r
- UINT32 Session; // [in] Session id\r
- UINT32 Return; // [out] Return value\r
- UINT32 ReturnOrigin; // [out] Origin of the return value\r
- OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS]; // Params for function to be invoked\r
+ UINT32 Function; // [in] Trusted Application function, specific to the TA\r
+ UINT32 Session; // [in] Session id\r
+ UINT32 Return; // [out] Return value\r
+ UINT32 ReturnOrigin; // [out] Origin of the return value\r
+ OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS]; // Params for function to be invoked\r
} OPTEE_INVOKE_FUNCTION_ARG;\r
\r
BOOLEAN\r
EFI_STATUS\r
EFIAPI\r
OpteeOpenSession (\r
- IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg\r
+ IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg\r
);\r
\r
EFI_STATUS\r
EFIAPI\r
OpteeCloseSession (\r
- IN UINT32 Session\r
+ IN UINT32 Session\r
);\r
\r
EFI_STATUS\r
EFIAPI\r
OpteeInvokeFunction (\r
- IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg\r
+ IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg\r
);\r
\r
#endif // OPTEE_LIB_H_\r
*\r
*/\r
\r
-#define SEMIHOST_FILE_MODE_READ (0 << 2)\r
-#define SEMIHOST_FILE_MODE_WRITE (1 << 2)\r
-#define SEMIHOST_FILE_MODE_APPEND (2 << 2)\r
-#define SEMIHOST_FILE_MODE_UPDATE (1 << 1)\r
-#define SEMIHOST_FILE_MODE_BINARY (1 << 0)\r
-#define SEMIHOST_FILE_MODE_ASCII (0 << 0)\r
+#define SEMIHOST_FILE_MODE_READ (0 << 2)\r
+#define SEMIHOST_FILE_MODE_WRITE (1 << 2)\r
+#define SEMIHOST_FILE_MODE_APPEND (2 << 2)\r
+#define SEMIHOST_FILE_MODE_UPDATE (1 << 1)\r
+#define SEMIHOST_FILE_MODE_BINARY (1 << 0)\r
+#define SEMIHOST_FILE_MODE_ASCII (0 << 0)\r
\r
BOOLEAN\r
SemihostConnectionSupported (\r
\r
RETURN_STATUS\r
SemihostFileOpen (\r
- IN CHAR8 *FileName,\r
- IN UINT32 Mode,\r
- OUT UINTN *FileHandle\r
+ IN CHAR8 *FileName,\r
+ IN UINT32 Mode,\r
+ OUT UINTN *FileHandle\r
);\r
\r
RETURN_STATUS\r
\r
**/\r
RETURN_STATUS\r
-SemihostFileTmpName(\r
+SemihostFileTmpName (\r
OUT VOID *Buffer,\r
IN UINT8 Identifier,\r
IN UINTN Length\r
\r
RETURN_STATUS\r
SemihostFileRemove (\r
- IN CHAR8 *FileName\r
+ IN CHAR8 *FileName\r
);\r
\r
/**\r
\r
**/\r
RETURN_STATUS\r
-SemihostFileRename(\r
+SemihostFileRename (\r
IN CHAR8 *FileName,\r
IN CHAR8 *NewFileName\r
);\r
\r
VOID\r
SemihostWriteCharacter (\r
- IN CHAR8 Character\r
+ IN CHAR8 Character\r
);\r
\r
VOID\r
SemihostWriteString (\r
- IN CHAR8 *String\r
+ IN CHAR8 *String\r
);\r
\r
UINT32\r
SemihostSystem (\r
- IN CHAR8 *CommandLine\r
+ IN CHAR8 *CommandLine\r
);\r
\r
#endif // SEMIHOSTING_LIB_H_\r
\r
EFI_STATUS\r
ArmSetMemoryRegionNoExec (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
EFI_STATUS\r
ArmClearMemoryRegionNoExec (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
EFI_STATUS\r
ArmSetMemoryRegionReadOnly (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
EFI_STATUS\r
ArmClearMemoryRegionReadOnly (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
#endif /* STANDALONE_MM_MMU_LIB_ */\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * ARM_MP_CORE_INFO_GET) (\r
+(EFIAPI *ARM_MP_CORE_INFO_GET)(\r
OUT UINTN *ArmCoreCount,\r
OUT ARM_CORE_INFO **ArmCoreTable\r
-);\r
+ );\r
\r
///\r
/// This service abstracts the ability to migrate contents of the platform early memory store.\r
/// This PPI was optional.\r
///\r
typedef struct {\r
- ARM_MP_CORE_INFO_GET GetMpCoreInfo;\r
+ ARM_MP_CORE_INFO_GET GetMpCoreInfo;\r
} ARM_MP_CORE_INFO_PPI;\r
\r
-extern EFI_GUID gArmMpCoreInfoPpiGuid;\r
-extern EFI_GUID gArmMpCoreInfoGuid;\r
+extern EFI_GUID gArmMpCoreInfoPpiGuid;\r
+extern EFI_GUID gArmMpCoreInfoGuid;\r
\r
#endif // ARM_MP_CORE_INFO_PPI_H_\r
/* As per SCMI specification, maximum allowed ASCII string length\r
for various return values/parameters of a SCMI message.\r
*/\r
-#define SCMI_MAX_STR_LEN 16\r
+#define SCMI_MAX_STR_LEN 16\r
\r
#endif /* ARM_SCMI_H_ */\r
-\r
#define BASE_PROTOCOL_VERSION_V1 0x10000\r
#define BASE_PROTOCOL_VERSION_V2 0x20000\r
\r
-#define NUM_PROTOCOL_MASK 0xFFU\r
-#define NUM_AGENT_MASK 0xFFU\r
+#define NUM_PROTOCOL_MASK 0xFFU\r
+#define NUM_AGENT_MASK 0xFFU\r
\r
-#define NUM_AGENT_SHIFT 0x8\r
+#define NUM_AGENT_SHIFT 0x8\r
\r
/** Returns total number of protocols that are\r
implemented (excluding the Base protocol)\r
*/\r
-#define SCMI_TOTAL_PROTOCOLS(Attr) (Attr & NUM_PROTOCOL_MASK)\r
+#define SCMI_TOTAL_PROTOCOLS(Attr) (Attr & NUM_PROTOCOL_MASK)\r
\r
// Returns total number of agents in the system.\r
-#define SCMI_TOTAL_AGENTS(Attr) ((Attr >> NUM_AGENT_SHIFT) & NUM_AGENT_MASK)\r
+#define SCMI_TOTAL_AGENTS(Attr) ((Attr >> NUM_AGENT_SHIFT) & NUM_AGENT_MASK)\r
\r
#define ARM_SCMI_BASE_PROTOCOL_GUID { \\r
0xd7e5abe9, 0x33ab, 0x418e, {0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f} \\r
}\r
\r
-extern EFI_GUID gArmScmiBaseProtocolGuid;\r
+extern EFI_GUID gArmScmiBaseProtocolGuid;\r
\r
typedef struct _SCMI_BASE_PROTOCOL SCMI_BASE_PROTOCOL;\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_BASE_GET_VERSION) (\r
+(EFIAPI *SCMI_BASE_GET_VERSION)(\r
IN SCMI_BASE_PROTOCOL *This,\r
OUT UINT32 *Version\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_BASE_GET_TOTAL_PROTOCOLS) (\r
+(EFIAPI *SCMI_BASE_GET_TOTAL_PROTOCOLS)(\r
IN SCMI_BASE_PROTOCOL *This,\r
OUT UINT32 *TotalProtocols\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_BASE_DISCOVER_VENDOR) (\r
+(EFIAPI *SCMI_BASE_DISCOVER_VENDOR)(\r
IN SCMI_BASE_PROTOCOL *This,\r
OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_BASE_DISCOVER_SUB_VENDOR) (\r
+(EFIAPI *SCMI_BASE_DISCOVER_SUB_VENDOR)(\r
IN SCMI_BASE_PROTOCOL *This,\r
OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION) (\r
+(EFIAPI *SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION)(\r
IN SCMI_BASE_PROTOCOL *This,\r
OUT UINT32 *ImplementationVersion\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_BASE_DISCOVER_LIST_PROTOCOLS) (\r
+(EFIAPI *SCMI_BASE_DISCOVER_LIST_PROTOCOLS)(\r
IN SCMI_BASE_PROTOCOL *This,\r
IN OUT UINT32 *ProtocolListSize,\r
OUT UINT8 *ProtocolList\r
\r
// Base protocol.\r
typedef struct _SCMI_BASE_PROTOCOL {\r
- SCMI_BASE_GET_VERSION GetVersion;\r
- SCMI_BASE_GET_TOTAL_PROTOCOLS GetTotalProtocols;\r
- SCMI_BASE_DISCOVER_VENDOR DiscoverVendor;\r
- SCMI_BASE_DISCOVER_SUB_VENDOR DiscoverSubVendor;\r
- SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION DiscoverImplementationVersion;\r
- SCMI_BASE_DISCOVER_LIST_PROTOCOLS DiscoverListProtocols;\r
+ SCMI_BASE_GET_VERSION GetVersion;\r
+ SCMI_BASE_GET_TOTAL_PROTOCOLS GetTotalProtocols;\r
+ SCMI_BASE_DISCOVER_VENDOR DiscoverVendor;\r
+ SCMI_BASE_DISCOVER_SUB_VENDOR DiscoverSubVendor;\r
+ SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION DiscoverImplementationVersion;\r
+ SCMI_BASE_DISCOVER_LIST_PROTOCOLS DiscoverListProtocols;\r
} SCMI_BASE_PROTOCOL;\r
\r
// SCMI Message IDs for Base protocol.\r
typedef enum {\r
- ScmiMessageIdBaseDiscoverVendor = 0x3,\r
- ScmiMessageIdBaseDiscoverSubVendor = 0x4,\r
- ScmiMessageIdBaseDiscoverImplementationVersion = 0x5,\r
- ScmiMessageIdBaseDiscoverListProtocols = 0x6\r
+ ScmiMessageIdBaseDiscoverVendor = 0x3,\r
+ ScmiMessageIdBaseDiscoverSubVendor = 0x4,\r
+ ScmiMessageIdBaseDiscoverImplementationVersion = 0x5,\r
+ ScmiMessageIdBaseDiscoverListProtocols = 0x6\r
} SCMI_MESSAGE_ID_BASE;\r
\r
#endif /* ARM_SCMI_BASE_PROTOCOL_H_ */\r
#include <Protocol/ArmScmi.h>\r
#include <Protocol/ArmScmiClockProtocol.h>\r
\r
-#define ARM_SCMI_CLOCK2_PROTOCOL_GUID { \\r
+#define ARM_SCMI_CLOCK2_PROTOCOL_GUID {\\r
0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } \\r
}\r
\r
-extern EFI_GUID gArmScmiClock2ProtocolGuid;\r
+extern EFI_GUID gArmScmiClock2ProtocolGuid;\r
\r
-#define SCMI_CLOCK2_PROTOCOL_VERSION 1\r
+#define SCMI_CLOCK2_PROTOCOL_VERSION 1\r
\r
typedef struct _SCMI_CLOCK2_PROTOCOL SCMI_CLOCK2_PROTOCOL;\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK2_GET_VERSION) (\r
+(EFIAPI *SCMI_CLOCK2_GET_VERSION)(\r
IN SCMI_CLOCK2_PROTOCOL *This,\r
OUT UINT32 *Version\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK2_GET_TOTAL_CLOCKS) (\r
+(EFIAPI *SCMI_CLOCK2_GET_TOTAL_CLOCKS)(\r
IN SCMI_CLOCK2_PROTOCOL *This,\r
OUT UINT32 *TotalClocks\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES) (\r
+(EFIAPI *SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES)(\r
IN SCMI_CLOCK2_PROTOCOL *This,\r
IN UINT32 ClockId,\r
OUT BOOLEAN *Enabled,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK2_DESCRIBE_RATES) (\r
+(EFIAPI *SCMI_CLOCK2_DESCRIBE_RATES)(\r
IN SCMI_CLOCK2_PROTOCOL *This,\r
IN UINT32 ClockId,\r
OUT SCMI_CLOCK_RATE_FORMAT *Format,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK2_RATE_GET) (\r
+(EFIAPI *SCMI_CLOCK2_RATE_GET)(\r
IN SCMI_CLOCK2_PROTOCOL *This,\r
IN UINT32 ClockId,\r
OUT UINT64 *Rate\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK2_RATE_SET) (\r
+(EFIAPI *SCMI_CLOCK2_RATE_SET)(\r
IN SCMI_CLOCK2_PROTOCOL *This,\r
IN UINT32 ClockId,\r
IN UINT64 Rate\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK2_ENABLE) (\r
+(EFIAPI *SCMI_CLOCK2_ENABLE)(\r
IN SCMI_CLOCK2_PROTOCOL *This,\r
IN UINT32 ClockId,\r
IN BOOLEAN Enable\r
);\r
\r
typedef struct _SCMI_CLOCK2_PROTOCOL {\r
- SCMI_CLOCK2_GET_VERSION GetVersion;\r
- SCMI_CLOCK2_GET_TOTAL_CLOCKS GetTotalClocks;\r
- SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES GetClockAttributes;\r
- SCMI_CLOCK2_DESCRIBE_RATES DescribeRates;\r
- SCMI_CLOCK2_RATE_GET RateGet;\r
- SCMI_CLOCK2_RATE_SET RateSet;\r
+ SCMI_CLOCK2_GET_VERSION GetVersion;\r
+ SCMI_CLOCK2_GET_TOTAL_CLOCKS GetTotalClocks;\r
+ SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES GetClockAttributes;\r
+ SCMI_CLOCK2_DESCRIBE_RATES DescribeRates;\r
+ SCMI_CLOCK2_RATE_GET RateGet;\r
+ SCMI_CLOCK2_RATE_SET RateSet;\r
\r
// Extension to original ClockProtocol, added here so SCMI_CLOCK2_PROTOCOL\r
// can be cast to SCMI_CLOCK_PROTOCOL\r
- UINTN Version; // For future expandability\r
- SCMI_CLOCK2_ENABLE Enable;\r
+ UINTN Version; // For future expandability\r
+ SCMI_CLOCK2_ENABLE Enable;\r
} SCMI_CLOCK2_PROTOCOL;\r
\r
#endif /* ARM_SCMI_CLOCK2_PROTOCOL_H_ */\r
\r
#include <Protocol/ArmScmi.h>\r
\r
-#define ARM_SCMI_CLOCK_PROTOCOL_GUID { \\r
+#define ARM_SCMI_CLOCK_PROTOCOL_GUID {\\r
0x91ce67a8, 0xe0aa, 0x4012, {0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa} \\r
}\r
\r
-extern EFI_GUID gArmScmiClockProtocolGuid;\r
+extern EFI_GUID gArmScmiClockProtocolGuid;\r
\r
// Message Type for clock management protocol.\r
typedef enum {\r
} SCMI_CLOCK_RATE_FORMAT;\r
\r
// Clock management protocol version.\r
-#define SCMI_CLOCK_PROTOCOL_VERSION 0x10000\r
+#define SCMI_CLOCK_PROTOCOL_VERSION 0x10000\r
\r
-#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK 0xFFU\r
-#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT 16\r
-#define SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK 0xFFFFU\r
+#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK 0xFFU\r
+#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT 16\r
+#define SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK 0xFFFFU\r
\r
/** Total number of pending asynchronous clock rates changes\r
supported by the SCP, Attr Bits[23:16]\r
*/\r
-#define SCMI_CLOCK_PROTOCOL_MAX_ASYNC_CLK_RATES(Attr) ( \\r
+#define SCMI_CLOCK_PROTOCOL_MAX_ASYNC_CLK_RATES(Attr) ( \\r
(Attr >> SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT) && \\r
SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK)\r
\r
// Total of clock devices supported by the SCP, Attr Bits[15:0]\r
-#define SCMI_CLOCK_PROTOCOL_TOTAL_CLKS(Attr) (Attr & SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK)\r
+#define SCMI_CLOCK_PROTOCOL_TOTAL_CLKS(Attr) (Attr & SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK)\r
\r
#pragma pack(1)\r
\r
either Rate or Min/Max/Step triplet is valid.\r
*/\r
typedef struct {\r
- UINT64 Min;\r
- UINT64 Max;\r
- UINT64 Step;\r
+ UINT64 Min;\r
+ UINT64 Max;\r
+ UINT64 Step;\r
} SCMI_CLOCK_RATE_CONTINUOUS;\r
\r
typedef struct {\r
- UINT64 Rate;\r
+ UINT64 Rate;\r
} SCMI_CLOCK_RATE_DISCRETE;\r
\r
typedef union {\r
- SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;\r
- SCMI_CLOCK_RATE_DISCRETE DiscreteRate;\r
+ SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;\r
+ SCMI_CLOCK_RATE_DISCRETE DiscreteRate;\r
} SCMI_CLOCK_RATE;\r
\r
#pragma pack()\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK_GET_VERSION) (\r
+(EFIAPI *SCMI_CLOCK_GET_VERSION)(\r
IN SCMI_CLOCK_PROTOCOL *This,\r
OUT UINT32 *Version\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK_GET_TOTAL_CLOCKS) (\r
+(EFIAPI *SCMI_CLOCK_GET_TOTAL_CLOCKS)(\r
IN SCMI_CLOCK_PROTOCOL *This,\r
OUT UINT32 *TotalClocks\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK_GET_CLOCK_ATTRIBUTES) (\r
+(EFIAPI *SCMI_CLOCK_GET_CLOCK_ATTRIBUTES)(\r
IN SCMI_CLOCK_PROTOCOL *This,\r
IN UINT32 ClockId,\r
OUT BOOLEAN *Enabled,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK_DESCRIBE_RATES) (\r
+(EFIAPI *SCMI_CLOCK_DESCRIBE_RATES)(\r
IN SCMI_CLOCK_PROTOCOL *This,\r
IN UINT32 ClockId,\r
OUT SCMI_CLOCK_RATE_FORMAT *Format,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK_RATE_GET) (\r
+(EFIAPI *SCMI_CLOCK_RATE_GET)(\r
IN SCMI_CLOCK_PROTOCOL *This,\r
IN UINT32 ClockId,\r
OUT UINT64 *Rate\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_CLOCK_RATE_SET) (\r
+(EFIAPI *SCMI_CLOCK_RATE_SET)(\r
IN SCMI_CLOCK_PROTOCOL *This,\r
IN UINT32 ClockId,\r
IN UINT64 Rate\r
);\r
\r
typedef struct _SCMI_CLOCK_PROTOCOL {\r
- SCMI_CLOCK_GET_VERSION GetVersion;\r
- SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks;\r
- SCMI_CLOCK_GET_CLOCK_ATTRIBUTES GetClockAttributes;\r
- SCMI_CLOCK_DESCRIBE_RATES DescribeRates;\r
- SCMI_CLOCK_RATE_GET RateGet;\r
- SCMI_CLOCK_RATE_SET RateSet;\r
+ SCMI_CLOCK_GET_VERSION GetVersion;\r
+ SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks;\r
+ SCMI_CLOCK_GET_CLOCK_ATTRIBUTES GetClockAttributes;\r
+ SCMI_CLOCK_DESCRIBE_RATES DescribeRates;\r
+ SCMI_CLOCK_RATE_GET RateGet;\r
+ SCMI_CLOCK_RATE_SET RateSet;\r
} SCMI_CLOCK_PROTOCOL;\r
\r
#endif /* ARM_SCMI_CLOCK_PROTOCOL_H_ */\r
-\r
0x9b8ba84, 0x3dd3, 0x49a6, {0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad} \\r
}\r
\r
-extern EFI_GUID gArmScmiPerformanceProtocolGuid;\r
+extern EFI_GUID gArmScmiPerformanceProtocolGuid;\r
\r
typedef struct _SCMI_PERFORMANCE_PROTOCOL SCMI_PERFORMANCE_PROTOCOL;\r
\r
#pragma pack(1)\r
\r
-#define POWER_IN_MW_SHIFT 16\r
-#define POWER_IN_MW_MASK 0x1\r
-#define NUM_PERF_DOMAINS_MASK 0xFFFF\r
+#define POWER_IN_MW_SHIFT 16\r
+#define POWER_IN_MW_MASK 0x1\r
+#define NUM_PERF_DOMAINS_MASK 0xFFFF\r
\r
// Total number of performance domains, Attr Bits [15:0]\r
#define SCMI_PERF_TOTAL_DOMAINS(Attr) (Attr & NUM_PERF_DOMAINS_MASK)\r
\r
// Performance protocol attributes return values.\r
typedef struct {\r
- UINT32 Attributes;\r
- UINT64 StatisticsAddress;\r
- UINT32 StatisticsLen;\r
+ UINT32 Attributes;\r
+ UINT64 StatisticsAddress;\r
+ UINT32 StatisticsLen;\r
} SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES;\r
\r
-#define SCMI_PERF_SUPPORT_LVL_CHANGE_NOTIFY(Attr) ((Attr >> 28) & 0x1)\r
-#define SCMI_PERF_SUPPORT_LIM_CHANGE_NOTIFY(Attr) ((Attr >> 29) & 0x1)\r
-#define SCMI_PERF_SUPPORT_SET_LVL(Attr) ((Attr >> 30) & 0x1)\r
-#define SCMI_PERF_SUPPORT_SET_LIM(Attr) ((Attr >> 31) & 0x1)\r
-#define SCMI_PERF_RATE_LIMIT(RateLimit) (RateLimit & 0xFFF)\r
+#define SCMI_PERF_SUPPORT_LVL_CHANGE_NOTIFY(Attr) ((Attr >> 28) & 0x1)\r
+#define SCMI_PERF_SUPPORT_LIM_CHANGE_NOTIFY(Attr) ((Attr >> 29) & 0x1)\r
+#define SCMI_PERF_SUPPORT_SET_LVL(Attr) ((Attr >> 30) & 0x1)\r
+#define SCMI_PERF_SUPPORT_SET_LIM(Attr) ((Attr >> 31) & 0x1)\r
+#define SCMI_PERF_RATE_LIMIT(RateLimit) (RateLimit & 0xFFF)\r
\r
// Performance protocol domain attributes.\r
typedef struct {\r
- UINT32 Attributes;\r
- UINT32 RateLimit;\r
- UINT32 SustainedFreq;\r
- UINT32 SustainedPerfLevel;\r
- UINT8 Name[SCMI_MAX_STR_LEN];\r
+ UINT32 Attributes;\r
+ UINT32 RateLimit;\r
+ UINT32 SustainedFreq;\r
+ UINT32 SustainedPerfLevel;\r
+ UINT8 Name[SCMI_MAX_STR_LEN];\r
} SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES;\r
\r
// Worst case latency in microseconds, Bits[15:0]\r
-#define PERF_LATENCY_MASK 0xFFFF\r
-#define SCMI_PERFORMANCE_PROTOCOL_LATENCY(Latency) (Latency & PERF_LATENCY_MASK)\r
+#define PERF_LATENCY_MASK 0xFFFF\r
+#define SCMI_PERFORMANCE_PROTOCOL_LATENCY(Latency) (Latency & PERF_LATENCY_MASK)\r
\r
// Performance protocol performance level.\r
typedef struct {\r
- UINT32 Level;\r
- UINT32 PowerCost;\r
- UINT32 Latency;\r
+ UINT32 Level;\r
+ UINT32 PowerCost;\r
+ UINT32 Latency;\r
} SCMI_PERFORMANCE_LEVEL;\r
\r
// Performance protocol performance limit.\r
typedef struct {\r
- UINT32 RangeMax;\r
- UINT32 RangeMin;\r
+ UINT32 RangeMax;\r
+ UINT32 RangeMin;\r
} SCMI_PERFORMANCE_LIMITS;\r
\r
#pragma pack()\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_PERFORMANCE_GET_VERSION) (\r
+(EFIAPI *SCMI_PERFORMANCE_GET_VERSION)(\r
IN SCMI_PERFORMANCE_PROTOCOL *This,\r
OUT UINT32 *Version\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_PERFORMANCE_GET_ATTRIBUTES) (\r
+(EFIAPI *SCMI_PERFORMANCE_GET_ATTRIBUTES)(\r
IN SCMI_PERFORMANCE_PROTOCOL *This,\r
OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES) (\r
+(EFIAPI *SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES)(\r
IN SCMI_PERFORMANCE_PROTOCOL *This,\r
IN UINT32 DomainId,\r
OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_PERFORMANCE_DESCRIBE_LEVELS) (\r
+(EFIAPI *SCMI_PERFORMANCE_DESCRIBE_LEVELS)(\r
IN SCMI_PERFORMANCE_PROTOCOL *This,\r
IN UINT32 DomainId,\r
OUT UINT32 *NumLevels,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_PERFORMANCE_LIMITS_SET) (\r
+(EFIAPI *SCMI_PERFORMANCE_LIMITS_SET)(\r
IN SCMI_PERFORMANCE_PROTOCOL *This,\r
IN UINT32 DomainId,\r
IN SCMI_PERFORMANCE_LIMITS *Limits\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_PERFORMANCE_LIMITS_GET) (\r
+(EFIAPI *SCMI_PERFORMANCE_LIMITS_GET)(\r
SCMI_PERFORMANCE_PROTOCOL *This,\r
UINT32 DomainId,\r
SCMI_PERFORMANCE_LIMITS *Limits\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_PERFORMANCE_LEVEL_SET) (\r
+(EFIAPI *SCMI_PERFORMANCE_LEVEL_SET)(\r
IN SCMI_PERFORMANCE_PROTOCOL *This,\r
IN UINT32 DomainId,\r
IN UINT32 Level\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *SCMI_PERFORMANCE_LEVEL_GET) (\r
+(EFIAPI *SCMI_PERFORMANCE_LEVEL_GET)(\r
IN SCMI_PERFORMANCE_PROTOCOL *This,\r
IN UINT32 DomainId,\r
OUT UINT32 *Level\r
);\r
\r
typedef struct _SCMI_PERFORMANCE_PROTOCOL {\r
- SCMI_PERFORMANCE_GET_VERSION GetVersion;\r
- SCMI_PERFORMANCE_GET_ATTRIBUTES GetProtocolAttributes;\r
- SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES GetDomainAttributes;\r
- SCMI_PERFORMANCE_DESCRIBE_LEVELS DescribeLevels;\r
- SCMI_PERFORMANCE_LIMITS_SET LimitsSet;\r
- SCMI_PERFORMANCE_LIMITS_GET LimitsGet;\r
- SCMI_PERFORMANCE_LEVEL_SET LevelSet;\r
- SCMI_PERFORMANCE_LEVEL_GET LevelGet;\r
+ SCMI_PERFORMANCE_GET_VERSION GetVersion;\r
+ SCMI_PERFORMANCE_GET_ATTRIBUTES GetProtocolAttributes;\r
+ SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES GetDomainAttributes;\r
+ SCMI_PERFORMANCE_DESCRIBE_LEVELS DescribeLevels;\r
+ SCMI_PERFORMANCE_LIMITS_SET LimitsSet;\r
+ SCMI_PERFORMANCE_LIMITS_GET LimitsGet;\r
+ SCMI_PERFORMANCE_LEVEL_SET LevelSet;\r
+ SCMI_PERFORMANCE_LEVEL_GET LevelGet;\r
} SCMI_PERFORMANCE_PROTOCOL;\r
\r
typedef enum {\r
} SCMI_MESSAGE_ID_PERFORMANCE;\r
\r
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */\r
-\r
\r
**/\r
\r
-\r
#include <Base.h>\r
#include <Library/ArmLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/ArmGenericTimerCounterLib.h>\r
\r
-#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U)\r
+#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U)\r
\r
// Select appropriate multiply function for platform architecture.\r
#ifdef MDE_CPU_ARM\r
-#define MULT_U64_X_N MultU64x32\r
+#define MULT_U64_X_N MultU64x32\r
#else\r
-#define MULT_U64_X_N MultU64x64\r
+#define MULT_U64_X_N MultU64x64\r
#endif\r
\r
-\r
RETURN_STATUS\r
EFIAPI\r
TimerConstructor (\r
// Check if the ARM Generic Timer Extension is implemented.\r
//\r
if (ArmIsArchTimerImplemented ()) {\r
-\r
//\r
// Check if Architectural Timer frequency is pre-determined by the platform\r
// (ie. nonzero).\r
//\r
ASSERT (TICKS_PER_MICRO_SEC);\r
\r
-#ifdef MDE_CPU_ARM\r
+ #ifdef MDE_CPU_ARM\r
//\r
// Only set the frequency for ARMv7. We expect the secure firmware to\r
// have already done it.\r
if (ArmHasSecurityExtensions ()) {\r
ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));\r
}\r
-#endif\r
+\r
+ #endif\r
}\r
\r
//\r
// If the reset value (0) is returned, just ASSERT.\r
//\r
ASSERT (ArmGenericTimerGetTimerFreq () != 0);\r
-\r
} else {\r
DEBUG ((DEBUG_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library cannot be used.\n"));\r
ASSERT (0);\r
GetPlatformTimerFreq (\r
)\r
{\r
- UINTN TimerFreq;\r
+ UINTN TimerFreq;\r
\r
TimerFreq = PcdGet32 (PcdArmArchTimerFreqInHz);\r
if (TimerFreq == 0) {\r
TimerFreq = ArmGenericTimerGetTimerFreq ();\r
}\r
+\r
return TimerFreq;\r
}\r
\r
-\r
/**\r
Stalls the CPU for the number of microseconds specified by MicroSeconds.\r
\r
UINTN\r
EFIAPI\r
MicroSecondDelay (\r
- IN UINTN MicroSeconds\r
+ IN UINTN MicroSeconds\r
)\r
{\r
- UINT64 TimerTicks64;\r
- UINT64 SystemCounterVal;\r
+ UINT64 TimerTicks64;\r
+ UINT64 SystemCounterVal;\r
\r
// Calculate counter ticks that represent requested delay:\r
// = MicroSeconds x TICKS_PER_MICRO_SEC\r
return MicroSeconds;\r
}\r
\r
-\r
/**\r
Stalls the CPU for at least the given number of nanoseconds.\r
\r
UINTN\r
EFIAPI\r
NanoSecondDelay (\r
- IN UINTN NanoSeconds\r
+ IN UINTN NanoSeconds\r
)\r
{\r
UINTN MicroSeconds;\r
\r
// Round up to 1us Tick Number\r
- MicroSeconds = NanoSeconds / 1000;\r
+ MicroSeconds = NanoSeconds / 1000;\r
MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1;\r
\r
MicroSecondDelay (MicroSeconds);\r
UINT64\r
EFIAPI\r
GetPerformanceCounterProperties (\r
- OUT UINT64 *StartValue OPTIONAL,\r
- OUT UINT64 *EndValue OPTIONAL\r
+ OUT UINT64 *StartValue OPTIONAL,\r
+ OUT UINT64 *EndValue OPTIONAL\r
)\r
{\r
if (StartValue != NULL) {\r
// Timer starts at 0\r
- *StartValue = (UINT64)0ULL ;\r
+ *StartValue = (UINT64)0ULL;\r
}\r
\r
if (EndValue != NULL) {\r
UINT64\r
EFIAPI\r
GetTimeInNanoSecond (\r
- IN UINT64 Ticks\r
+ IN UINT64 Ticks\r
)\r
{\r
UINT64 NanoSeconds;\r
DivU64x32Remainder (\r
Ticks,\r
TimerFreq,\r
- &Remainder),\r
+ &Remainder\r
+ ),\r
1000000000U\r
);\r
\r
//\r
NanoSeconds += DivU64x32 (\r
MULT_U64_X_N (\r
- (UINT64) Remainder,\r
- 1000000000U),\r
+ (UINT64)Remainder,\r
+ 1000000000U\r
+ ),\r
TimerFreq\r
);\r
\r
IN UINTN LineLength\r
)\r
{\r
- UINTN ArmCacheLineAlignmentMask;\r
+ UINTN ArmCacheLineAlignmentMask;\r
// Align address (rounding down)\r
- UINTN AlignedAddress;\r
- UINTN EndAddress;\r
+ UINTN AlignedAddress;\r
+ UINTN EndAddress;\r
\r
ArmCacheLineAlignmentMask = LineLength - 1;\r
- AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);\r
- EndAddress = (UINTN)Start + Length;\r
+ AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);\r
+ EndAddress = (UINTN)Start + Length;\r
\r
// Perform the line operation on an address in each cache line\r
while (AlignedAddress < EndAddress) {\r
- LineOperation(AlignedAddress);\r
+ LineOperation (AlignedAddress);\r
AlignedAddress += LineLength;\r
}\r
+\r
ArmDataSynchronizationBarrier ();\r
}\r
\r
VOID *\r
EFIAPI\r
InvalidateInstructionCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
- CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA,\r
- ArmDataCacheLineLength ());\r
- CacheRangeOperation (Address, Length,\r
+ CacheRangeOperation (\r
+ Address,\r
+ Length,\r
+ ArmCleanDataCacheEntryToPoUByMVA,\r
+ ArmDataCacheLineLength ()\r
+ );\r
+ CacheRangeOperation (\r
+ Address,\r
+ Length,\r
ArmInvalidateInstructionCacheEntryToPoUByMVA,\r
- ArmInstructionCacheLineLength ());\r
+ ArmInstructionCacheLineLength ()\r
+ );\r
\r
ArmInstructionSynchronizationBarrier ();\r
\r
VOID *\r
EFIAPI\r
WriteBackInvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
- CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA,\r
- ArmDataCacheLineLength ());\r
+ CacheRangeOperation (\r
+ Address,\r
+ Length,\r
+ ArmCleanInvalidateDataCacheEntryByMVA,\r
+ ArmDataCacheLineLength ()\r
+ );\r
return Address;\r
}\r
\r
VOID *\r
EFIAPI\r
WriteBackDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
- CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA,\r
- ArmDataCacheLineLength ());\r
+ CacheRangeOperation (\r
+ Address,\r
+ Length,\r
+ ArmCleanDataCacheEntryByMVA,\r
+ ArmDataCacheLineLength ()\r
+ );\r
return Address;\r
}\r
\r
VOID *\r
EFIAPI\r
InvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
- CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA,\r
- ArmDataCacheLineLength ());\r
+ CacheRangeOperation (\r
+ Address,\r
+ Length,\r
+ ArmInvalidateDataCacheEntryByMVA,\r
+ ArmDataCacheLineLength ()\r
+ );\r
return Address;\r
}\r
**/\r
VOID\r
DisassembleInstruction (\r
- IN UINT8 **OpCodePtr,\r
- IN BOOLEAN Thumb,\r
- IN BOOLEAN Extended,\r
- IN OUT UINT32 *ItBlock,\r
- OUT CHAR8 *Buf,\r
- OUT UINTN Size\r
+ IN UINT8 **OpCodePtr,\r
+ IN BOOLEAN Thumb,\r
+ IN BOOLEAN Extended,\r
+ IN OUT UINT32 *ItBlock,\r
+ OUT CHAR8 *Buf,\r
+ OUT UINTN Size\r
)\r
{\r
// Not yet supported for AArch64.\r
#include <Library/PrintLib.h>\r
#include <Library/ArmDisassemblerLib.h>\r
\r
-CHAR8 *gCondition[] = {\r
+CHAR8 *gCondition[] = {\r
"EQ",\r
"NE",\r
"CS",\r
\r
#define COND(_a) gCondition[((_a) >> 28)]\r
\r
-CHAR8 *gReg[] = {\r
+CHAR8 *gReg[] = {\r
"r0",\r
"r1",\r
"r2",\r
"pc"\r
};\r
\r
-CHAR8 *gLdmAdr[] = {\r
+CHAR8 *gLdmAdr[] = {\r
"DA",\r
"IA",\r
"DB",\r
"IB"\r
};\r
\r
-CHAR8 *gLdmStack[] = {\r
+CHAR8 *gLdmStack[] = {\r
"FA",\r
"FD",\r
"EA",\r
"ED"\r
};\r
\r
-#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])\r
+#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])\r
\r
+#define SIGN(_U) ((_U) ? "" : "-")\r
+#define WRITE(_Write) ((_Write) ? "!" : "")\r
+#define BYTE(_B) ((_B) ? "B":"")\r
+#define USER(_B) ((_B) ? "^" : "")\r
\r
-#define SIGN(_U) ((_U) ? "" : "-")\r
-#define WRITE(_Write) ((_Write) ? "!" : "")\r
-#define BYTE(_B) ((_B) ? "B":"")\r
-#define USER(_B) ((_B) ? "^" : "")\r
-\r
-CHAR8 mMregListStr[4*15 + 1];\r
+CHAR8 mMregListStr[4*15 + 1];\r
\r
CHAR8 *\r
MRegList (\r
UINT32 OpCode\r
)\r
{\r
- UINTN Index, Start, End;\r
- BOOLEAN First;\r
+ UINTN Index, Start, End;\r
+ BOOLEAN First;\r
\r
mMregListStr[0] = '\0';\r
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "{");\r
}\r
}\r
}\r
+\r
if (First) {\r
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "ERROR");\r
}\r
+\r
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "}");\r
\r
// BugBug: Make caller pass in buffer it is cleaner\r
\r
UINT32\r
RotateRight (\r
- IN UINT32 Op,\r
- IN UINT32 Shift\r
+ IN UINT32 Op,\r
+ IN UINT32 Shift\r
)\r
{\r
return (Op >> Shift) | (Op << (32 - Shift));\r
}\r
\r
-\r
/**\r
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to\r
point to next instruction.\r
**/\r
VOID\r
DisassembleArmInstruction (\r
- IN UINT32 **OpCodePtr,\r
- OUT CHAR8 *Buf,\r
- OUT UINTN Size,\r
- IN BOOLEAN Extended\r
+ IN UINT32 **OpCodePtr,\r
+ OUT CHAR8 *Buf,\r
+ OUT UINTN Size,\r
+ IN BOOLEAN Extended\r
)\r
{\r
- UINT32 OpCode;\r
- CHAR8 *Type;\r
- CHAR8 *Root;\r
- BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;\r
- UINT32 Rn, Rd, Rm;\r
- UINT32 IMod, Offset8, Offset12;\r
- UINT32 Index;\r
- UINT32 ShiftImm, Shift;\r
+ UINT32 OpCode;\r
+ CHAR8 *Type;\r
+ CHAR8 *Root;\r
+ BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;\r
+ UINT32 Rn, Rd, Rm;\r
+ UINT32 IMod, Offset8, Offset12;\r
+ UINT32 Index;\r
+ UINT32 ShiftImm, Shift;\r
\r
OpCode = **OpCodePtr;\r
\r
- Imm = (OpCode & BIT25) == BIT25; // I\r
- Pre = (OpCode & BIT24) == BIT24; // P\r
- Up = (OpCode & BIT23) == BIT23; // U\r
+ Imm = (OpCode & BIT25) == BIT25; // I\r
+ Pre = (OpCode & BIT24) == BIT24; // P\r
+ Up = (OpCode & BIT23) == BIT23; // U\r
WriteBack = (OpCode & BIT22) == BIT22; // B, also called S\r
- Write = (OpCode & BIT21) == BIT21; // W\r
- Load = (OpCode & BIT20) == BIT20; // L\r
- Sign = (OpCode & BIT6) == BIT6; // S\r
- Half = (OpCode & BIT5) == BIT5; // H\r
- Rn = (OpCode >> 16) & 0xf;\r
- Rd = (OpCode >> 12) & 0xf;\r
- Rm = (OpCode & 0xf);\r
-\r
+ Write = (OpCode & BIT21) == BIT21; // W\r
+ Load = (OpCode & BIT20) == BIT20; // L\r
+ Sign = (OpCode & BIT6) == BIT6; // S\r
+ Half = (OpCode & BIT5) == BIT5; // H\r
+ Rn = (OpCode >> 16) & 0xf;\r
+ Rd = (OpCode >> 12) & 0xf;\r
+ Rm = (OpCode & 0xf);\r
\r
if (Extended) {\r
Index = AsciiSPrint (Buf, Size, "0x%08x ", OpCode);\r
- Buf += Index;\r
+ Buf += Index;\r
Size -= Index;\r
}\r
\r
// A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]\r
AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);\r
} else {\r
- // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]\r
+ // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]\r
AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);\r
}\r
+\r
return;\r
}\r
\r
// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>\r
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^\r
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^\r
- AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));\r
+ AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));\r
} else {\r
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>\r
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^\r
- AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));\r
+ AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));\r
}\r
+\r
return;\r
}\r
\r
// LDR/STR Address Mode 2\r
- if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {\r
+ if (((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000) == 0xf550f000)) {\r
Offset12 = OpCode & 0xfff;\r
- if ((OpCode & 0xfd70f000 ) == 0xf550f000) {\r
+ if ((OpCode & 0xfd70f000) == 0xf550f000) {\r
Index = AsciiSPrint (Buf, Size, "PLD");\r
} else {\r
- Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]);\r
+ Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T" : "", gReg[Rd]);\r
}\r
+\r
if (Pre) {\r
if (!Imm) {\r
// A5.2.2 [<Rn>, #+/-<offset_12>]\r
// A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]\r
// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!\r
ShiftImm = (OpCode >> 7) & 0x1f;\r
- Shift = (OpCode >> 5) & 0x3;\r
+ Shift = (OpCode >> 5) & 0x3;\r
if (Shift == 0x0) {\r
Type = "LSL";\r
} else if (Shift == 0x1) {\r
\r
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));\r
}\r
- } else { // !Pre\r
+ } else {\r
+ // !Pre\r
if (!Imm) {\r
// A5.2.8 [<Rn>], #+/-<offset_12>\r
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);\r
} else {\r
// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>\r
ShiftImm = (OpCode >> 7) & 0x1f;\r
- Shift = (OpCode >> 5) & 0x3;\r
+ Shift = (OpCode >> 5) & 0x3;\r
\r
if (Shift == 0x0) {\r
Type = "LSL";\r
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);\r
}\r
}\r
+\r
return;\r
}\r
\r
\r
Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);\r
\r
- Sign = (OpCode & BIT6) == BIT6;\r
- Half = (OpCode & BIT5) == BIT5;\r
+ Sign = (OpCode & BIT6) == BIT6;\r
+ Half = (OpCode & BIT5) == BIT5;\r
Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;\r
if (Pre & !Write) {\r
// Immediate offset/index\r
if (WriteBack) {\r
// A5.3.2 [<Rn>, #+/-<offset_8>]\r
// A5.3.4 [<Rn>, #+/-<offset_8>]!\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));\r
} else {\r
// A5.3.3 [<Rn>, +/-<Rm>]\r
// A5.3.5 [<Rn>, +/-<Rm>]!\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));\r
}\r
} else {\r
// Register offset/index\r
if (WriteBack) {\r
// A5.3.6 [<Rn>], #+/-<offset_8>\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);\r
} else {\r
// A5.3.7 [<Rn>], +/-<Rm>\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);\r
}\r
}\r
+\r
return;\r
}\r
\r
if (((OpCode >> 6) & 0x7) == 0) {\r
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));\r
} else {\r
- IMod = (OpCode >> 18) & 0x3;\r
- Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a",\r
- (IMod == 3) ? "ID":"IE",\r
- ((OpCode & BIT8) != 0) ? "A":"",\r
- ((OpCode & BIT7) != 0) ? "I":"",\r
- ((OpCode & BIT6) != 0) ? "F":"");\r
+ IMod = (OpCode >> 18) & 0x3;\r
+ Index = AsciiSPrint (\r
+ Buf,\r
+ Size,\r
+ "CPS%a %a%a%a",\r
+ (IMod == 3) ? "ID" : "IE",\r
+ ((OpCode & BIT8) != 0) ? "A" : "",\r
+ ((OpCode & BIT7) != 0) ? "I" : "",\r
+ ((OpCode & BIT6) != 0) ? "F" : ""\r
+ );\r
if ((OpCode & BIT17) != 0) {\r
AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);\r
}\r
}\r
+\r
return;\r
}\r
\r
return;\r
}\r
\r
-\r
if ((OpCode & 0x0db00000) == 0x01200000) {\r
// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>\r
if (Imm) {\r
// MSR{<cond>} CPSR_<fields>, #<immediate>\r
- AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));\r
+ AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));\r
} else {\r
// MSR{<cond>} CPSR_<fields>, <Rm>\r
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);\r
}\r
+\r
return;\r
}\r
\r
if ((OpCode & 0x0e000000) == 0x0c000000) {\r
// A4.1.19 LDC and A4.1.96 SDC\r
if ((OpCode & 0xf0000000) == 0xf0000000) {\r
- Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);\r
+ Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC" : "SDC", (OpCode >> 8) & 0xf, Rd);\r
} else {\r
- Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);\r
+ Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC" : "SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);\r
}\r
\r
if (!Pre) {\r
if (!Write) {\r
// A5.5.5.5 [<Rn>], <option>\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);\r
} else {\r
// A.5.5.4 [<Rn>], #+/-<offset_8>*4\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);\r
}\r
} else {\r
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!\r
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));\r
}\r
-\r
}\r
\r
if ((OpCode & 0x0f000010) == 0x0e000010) {\r
// A4.1.32 MRC2, MCR2\r
- AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);\r
+ AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC" : "MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);\r
return;\r
}\r
\r
if ((OpCode & 0x0ff00000) == 0x0c400000) {\r
// A4.1.33 MRRC2, MCRR2\r
- AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);\r
+ AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC" : "MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);\r
return;\r
}\r
\r
*OpCodePtr += 1;\r
return;\r
}\r
-\r
#include <Library/DebugLib.h>\r
#include <Library/PrintLib.h>\r
\r
-extern CHAR8 *gCondition[];\r
+extern CHAR8 *gCondition[];\r
\r
-extern CHAR8 *gReg[];\r
+extern CHAR8 *gReg[];\r
\r
// Thumb address modes\r
-#define LOAD_STORE_FORMAT1 1\r
-#define LOAD_STORE_FORMAT1_H 101\r
-#define LOAD_STORE_FORMAT1_B 111\r
-#define LOAD_STORE_FORMAT2 2\r
-#define LOAD_STORE_FORMAT3 3\r
-#define LOAD_STORE_FORMAT4 4\r
-#define LOAD_STORE_MULTIPLE_FORMAT1 5\r
-#define PUSH_FORMAT 6\r
-#define POP_FORMAT 106\r
-#define IMMED_8 7\r
-#define CONDITIONAL_BRANCH 8\r
-#define UNCONDITIONAL_BRANCH 9\r
-#define UNCONDITIONAL_BRANCH_SHORT 109\r
+#define LOAD_STORE_FORMAT1 1\r
+#define LOAD_STORE_FORMAT1_H 101\r
+#define LOAD_STORE_FORMAT1_B 111\r
+#define LOAD_STORE_FORMAT2 2\r
+#define LOAD_STORE_FORMAT3 3\r
+#define LOAD_STORE_FORMAT4 4\r
+#define LOAD_STORE_MULTIPLE_FORMAT1 5\r
+#define PUSH_FORMAT 6\r
+#define POP_FORMAT 106\r
+#define IMMED_8 7\r
+#define CONDITIONAL_BRANCH 8\r
+#define UNCONDITIONAL_BRANCH 9\r
+#define UNCONDITIONAL_BRANCH_SHORT 109\r
#define BRANCH_EXCHANGE 10\r
#define DATA_FORMAT1 11\r
#define DATA_FORMAT2 12\r
#define DATA_FORMAT4 14\r
#define DATA_FORMAT5 15\r
#define DATA_FORMAT6_SP 16\r
-#define DATA_FORMAT6_PC 116\r
+#define DATA_FORMAT6_PC 116\r
#define DATA_FORMAT7 17\r
#define DATA_FORMAT8 19\r
#define CPS_FORMAT 20\r
#define IT_BLOCK 24\r
\r
// Thumb2 address modes\r
-#define B_T3 200\r
-#define B_T4 201\r
-#define BL_T2 202\r
-#define POP_T2 203\r
-#define POP_T3 204\r
-#define STM_FORMAT 205\r
-#define LDM_REG_IMM12_SIGNED 206\r
-#define LDM_REG_IMM12_LSL 207\r
-#define LDM_REG_IMM8 208\r
-#define LDM_REG_IMM12 209\r
-#define LDM_REG_INDIRECT_LSL 210\r
-#define LDM_REG_IMM8_SIGNED 211\r
-#define LDRD_REG_IMM8 212\r
-#define LDREXB 213\r
-#define LDREXD 214\r
-#define SRS_FORMAT 215\r
-#define RFE_FORMAT 216\r
-#define LDRD_REG_IMM8_SIGNED 217\r
-#define ADD_IMM12 218\r
-#define ADD_IMM5 219\r
-#define ADR_THUMB2 220\r
-#define CMN_THUMB2 221\r
-#define ASR_IMM5 222\r
-#define ASR_3REG 223\r
-#define BFC_THUMB2 224\r
-#define CDP_THUMB2 225\r
-#define THUMB2_NO_ARGS 226\r
-#define THUMB2_2REGS 227\r
-#define ADD_IMM5_2REG 228\r
-#define CPD_THUMB2 229\r
-#define THUMB2_4REGS 230\r
-#define ADD_IMM12_1REG 231\r
-#define THUMB2_IMM16 232\r
-#define MRC_THUMB2 233\r
-#define MRRC_THUMB2 234\r
-#define THUMB2_MRS 235\r
-#define THUMB2_MSR 236\r
-\r
-\r
-\r
+#define B_T3 200\r
+#define B_T4 201\r
+#define BL_T2 202\r
+#define POP_T2 203\r
+#define POP_T3 204\r
+#define STM_FORMAT 205\r
+#define LDM_REG_IMM12_SIGNED 206\r
+#define LDM_REG_IMM12_LSL 207\r
+#define LDM_REG_IMM8 208\r
+#define LDM_REG_IMM12 209\r
+#define LDM_REG_INDIRECT_LSL 210\r
+#define LDM_REG_IMM8_SIGNED 211\r
+#define LDRD_REG_IMM8 212\r
+#define LDREXB 213\r
+#define LDREXD 214\r
+#define SRS_FORMAT 215\r
+#define RFE_FORMAT 216\r
+#define LDRD_REG_IMM8_SIGNED 217\r
+#define ADD_IMM12 218\r
+#define ADD_IMM5 219\r
+#define ADR_THUMB2 220\r
+#define CMN_THUMB2 221\r
+#define ASR_IMM5 222\r
+#define ASR_3REG 223\r
+#define BFC_THUMB2 224\r
+#define CDP_THUMB2 225\r
+#define THUMB2_NO_ARGS 226\r
+#define THUMB2_2REGS 227\r
+#define ADD_IMM5_2REG 228\r
+#define CPD_THUMB2 229\r
+#define THUMB2_4REGS 230\r
+#define ADD_IMM12_1REG 231\r
+#define THUMB2_IMM16 232\r
+#define MRC_THUMB2 233\r
+#define MRRC_THUMB2 234\r
+#define THUMB2_MRS 235\r
+#define THUMB2_MSR 236\r
\r
typedef struct {\r
- CHAR8 *Start;\r
- UINT32 OpCode;\r
- UINT32 Mask;\r
- UINT32 AddressMode;\r
+ CHAR8 *Start;\r
+ UINT32 OpCode;\r
+ UINT32 Mask;\r
+ UINT32 AddressMode;\r
} THUMB_INSTRUCTIONS;\r
\r
-THUMB_INSTRUCTIONS gOpThumb[] = {\r
-// Thumb 16-bit instructions\r
-// Op Mask Format\r
- { "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 }, // ADC <Rndn>, <Rm>\r
- { "ADR", 0xa000, 0xf800, ADR_FORMAT }, // ADR <Rd>, <label>\r
- { "ADD" , 0x1c00, 0xfe00, DATA_FORMAT2 },\r
- { "ADD" , 0x3000, 0xf800, DATA_FORMAT3 },\r
- { "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },\r
- { "ADD" , 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9\r
- { "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },\r
- { "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP },\r
- { "ADD" , 0xb000, 0xff80, DATA_FORMAT7 },\r
-\r
- { "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },\r
-\r
- { "ASR" , 0x1000, 0xf800, DATA_FORMAT4 },\r
- { "ASR" , 0x4100, 0xffc0, DATA_FORMAT5 },\r
-\r
- { "B" , 0xd000, 0xf000, CONDITIONAL_BRANCH },\r
- { "B" , 0xe000, 0xf800, UNCONDITIONAL_BRANCH_SHORT },\r
- { "BLX" , 0x4780, 0xff80, BRANCH_EXCHANGE },\r
- { "BX" , 0x4700, 0xff87, BRANCH_EXCHANGE },\r
-\r
- { "BIC" , 0x4380, 0xffc0, DATA_FORMAT5 },\r
- { "BKPT", 0xdf00, 0xff00, IMMED_8 },\r
- { "CBZ", 0xb100, 0xfd00, DATA_CBZ },\r
- { "CBNZ", 0xb900, 0xfd00, DATA_CBZ },\r
- { "CMN" , 0x42c0, 0xffc0, DATA_FORMAT5 },\r
-\r
- { "CMP" , 0x2800, 0xf800, DATA_FORMAT3 },\r
- { "CMP" , 0x4280, 0xffc0, DATA_FORMAT5 },\r
- { "CMP" , 0x4500, 0xff00, DATA_FORMAT8 },\r
-\r
- { "CPS" , 0xb660, 0xffe8, CPS_FORMAT },\r
- { "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },\r
- { "EOR" , 0x4040, 0xffc0, DATA_FORMAT5 },\r
-\r
- { "LDMIA" , 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },\r
- { "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 }, // LDR <Rt>, [<Rn> {,#<imm>}]\r
- { "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]\r
- { "LDR" , 0x4800, 0xf800, LOAD_STORE_FORMAT3 },\r
- { "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 }, // LDR <Rt>, [SP, #<imm>]\r
- { "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1_B },\r
- { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]\r
- { "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1_H },\r
- { "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },\r
- { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]\r
- { "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },\r
-\r
- { "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 }, // LSL with imm5 == 0 is a MOVS, so this must go before LSL\r
- { "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },\r
- { "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },\r
- { "LSR" , 0x0001, 0xf800, DATA_FORMAT4 },\r
- { "LSR" , 0x40c0, 0xffc0, DATA_FORMAT5 },\r
- { "LSRS", 0x0800, 0xf800, DATA_FORMAT4 }, // LSRS <Rd>, <Rm>, #<imm5>\r
-\r
- { "MOVS", 0x2000, 0xf800, DATA_FORMAT3 },\r
- { "MOV" , 0x1c00, 0xffc0, DATA_FORMAT3 },\r
- { "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },\r
-\r
- { "MUL" , 0x4340, 0xffc0, DATA_FORMAT5 },\r
- { "MVN" , 0x41c0, 0xffc0, DATA_FORMAT5 },\r
- { "NEG" , 0x4240, 0xffc0, DATA_FORMAT5 },\r
- { "ORR" , 0x4300, 0xffc0, DATA_FORMAT5 },\r
- { "POP" , 0xbc00, 0xfe00, POP_FORMAT },\r
- { "PUSH", 0xb400, 0xfe00, PUSH_FORMAT },\r
-\r
- { "REV" , 0xba00, 0xffc0, DATA_FORMAT5 },\r
- { "REV16" , 0xba40, 0xffc0, DATA_FORMAT5 },\r
- { "REVSH" , 0xbac0, 0xffc0, DATA_FORMAT5 },\r
-\r
- { "ROR" , 0x41c0, 0xffc0, DATA_FORMAT5 },\r
- { "SBC" , 0x4180, 0xffc0, DATA_FORMAT5 },\r
- { "SETEND" , 0xb650, 0xfff0, ENDIAN_FORMAT },\r
-\r
- { "STMIA" , 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },\r
- { "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 }, // STR <Rt>, [<Rn> {,#<imm>}]\r
- { "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]\r
- { "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 }, // STR <Rt>, [SP, #<imm>]\r
- { "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1_B }, // STRB <Rt>, [<Rn>, #<imm5>]\r
- { "STRB" , 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>]\r
- { "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1_H }, // STRH <Rt>, [<Rn>{,#<imm>}]\r
- { "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 }, // STRH <Rt>, [<Rn>, <Rm>]\r
-\r
- { "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2 },\r
- { "SUB" , 0x3800, 0xf800, DATA_FORMAT3 },\r
- { "SUB" , 0x1a00, 0xfe00, DATA_FORMAT1 },\r
- { "SUB" , 0xb080, 0xff80, DATA_FORMAT7 },\r
-\r
- { "SBC" , 0x4180, 0xffc0, DATA_FORMAT5 },\r
-\r
- { "SWI" , 0xdf00, 0xff00, IMMED_8 },\r
- { "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },\r
- { "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },\r
- { "TST" , 0x4200, 0xffc0, DATA_FORMAT5 },\r
- { "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },\r
- { "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 },\r
-\r
- { "IT", 0xbf00, 0xff00, IT_BLOCK }\r
-\r
+THUMB_INSTRUCTIONS gOpThumb[] = {\r
+ // Thumb 16-bit instructions\r
+ // Op Mask Format\r
+ { "ADC", 0x4140, 0xffc0, DATA_FORMAT5 }, // ADC <Rndn>, <Rm>\r
+ { "ADR", 0xa000, 0xf800, ADR_FORMAT }, // ADR <Rd>, <label>\r
+ { "ADD", 0x1c00, 0xfe00, DATA_FORMAT2 },\r
+ { "ADD", 0x3000, 0xf800, DATA_FORMAT3 },\r
+ { "ADD", 0x1800, 0xfe00, DATA_FORMAT1 },\r
+ { "ADD", 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9\r
+ { "ADD", 0xa000, 0xf100, DATA_FORMAT6_PC },\r
+ { "ADD", 0xa800, 0xf800, DATA_FORMAT6_SP },\r
+ { "ADD", 0xb000, 0xff80, DATA_FORMAT7 },\r
+\r
+ { "AND", 0x4000, 0xffc0, DATA_FORMAT5 },\r
+\r
+ { "ASR", 0x1000, 0xf800, DATA_FORMAT4 },\r
+ { "ASR", 0x4100, 0xffc0, DATA_FORMAT5 },\r
+\r
+ { "B", 0xd000, 0xf000, CONDITIONAL_BRANCH },\r
+ { "B", 0xe000, 0xf800, UNCONDITIONAL_BRANCH_SHORT },\r
+ { "BLX", 0x4780, 0xff80, BRANCH_EXCHANGE },\r
+ { "BX", 0x4700, 0xff87, BRANCH_EXCHANGE },\r
+\r
+ { "BIC", 0x4380, 0xffc0, DATA_FORMAT5 },\r
+ { "BKPT", 0xdf00, 0xff00, IMMED_8 },\r
+ { "CBZ", 0xb100, 0xfd00, DATA_CBZ },\r
+ { "CBNZ", 0xb900, 0xfd00, DATA_CBZ },\r
+ { "CMN", 0x42c0, 0xffc0, DATA_FORMAT5 },\r
+\r
+ { "CMP", 0x2800, 0xf800, DATA_FORMAT3 },\r
+ { "CMP", 0x4280, 0xffc0, DATA_FORMAT5 },\r
+ { "CMP", 0x4500, 0xff00, DATA_FORMAT8 },\r
+\r
+ { "CPS", 0xb660, 0xffe8, CPS_FORMAT },\r
+ { "MOV", 0x4600, 0xff00, DATA_FORMAT8 },\r
+ { "EOR", 0x4040, 0xffc0, DATA_FORMAT5 },\r
+\r
+ { "LDMIA", 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },\r
+ { "LDR", 0x6800, 0xf800, LOAD_STORE_FORMAT1 }, // LDR <Rt>, [<Rn> {,#<imm>}]\r
+ { "LDR", 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]\r
+ { "LDR", 0x4800, 0xf800, LOAD_STORE_FORMAT3 },\r
+ { "LDR", 0x9800, 0xf800, LOAD_STORE_FORMAT4 }, // LDR <Rt>, [SP, #<imm>]\r
+ { "LDRB", 0x7800, 0xf800, LOAD_STORE_FORMAT1_B },\r
+ { "LDRB", 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]\r
+ { "LDRH", 0x8800, 0xf800, LOAD_STORE_FORMAT1_H },\r
+ { "LDRH", 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },\r
+ { "LDRSB", 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]\r
+ { "LDRSH", 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },\r
+\r
+ { "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 }, // LSL with imm5 == 0 is a MOVS, so this must go before LSL\r
+ { "LSL", 0x0000, 0xf800, DATA_FORMAT4 },\r
+ { "LSL", 0x4080, 0xffc0, DATA_FORMAT5 },\r
+ { "LSR", 0x0001, 0xf800, DATA_FORMAT4 },\r
+ { "LSR", 0x40c0, 0xffc0, DATA_FORMAT5 },\r
+ { "LSRS", 0x0800, 0xf800, DATA_FORMAT4 }, // LSRS <Rd>, <Rm>, #<imm5>\r
+\r
+ { "MOVS", 0x2000, 0xf800, DATA_FORMAT3 },\r
+ { "MOV", 0x1c00, 0xffc0, DATA_FORMAT3 },\r
+ { "MOV", 0x4600, 0xff00, DATA_FORMAT8 },\r
+\r
+ { "MUL", 0x4340, 0xffc0, DATA_FORMAT5 },\r
+ { "MVN", 0x41c0, 0xffc0, DATA_FORMAT5 },\r
+ { "NEG", 0x4240, 0xffc0, DATA_FORMAT5 },\r
+ { "ORR", 0x4300, 0xffc0, DATA_FORMAT5 },\r
+ { "POP", 0xbc00, 0xfe00, POP_FORMAT },\r
+ { "PUSH", 0xb400, 0xfe00, PUSH_FORMAT },\r
+\r
+ { "REV", 0xba00, 0xffc0, DATA_FORMAT5 },\r
+ { "REV16", 0xba40, 0xffc0, DATA_FORMAT5 },\r
+ { "REVSH", 0xbac0, 0xffc0, DATA_FORMAT5 },\r
+\r
+ { "ROR", 0x41c0, 0xffc0, DATA_FORMAT5 },\r
+ { "SBC", 0x4180, 0xffc0, DATA_FORMAT5 },\r
+ { "SETEND", 0xb650, 0xfff0, ENDIAN_FORMAT },\r
+\r
+ { "STMIA", 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },\r
+ { "STR", 0x6000, 0xf800, LOAD_STORE_FORMAT1 }, // STR <Rt>, [<Rn> {,#<imm>}]\r
+ { "STR", 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]\r
+ { "STR", 0x9000, 0xf800, LOAD_STORE_FORMAT4 }, // STR <Rt>, [SP, #<imm>]\r
+ { "STRB", 0x7000, 0xf800, LOAD_STORE_FORMAT1_B }, // STRB <Rt>, [<Rn>, #<imm5>]\r
+ { "STRB", 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>]\r
+ { "STRH", 0x8000, 0xf800, LOAD_STORE_FORMAT1_H }, // STRH <Rt>, [<Rn>{,#<imm>}]\r
+ { "STRH", 0x5200, 0xfe00, LOAD_STORE_FORMAT2 }, // STRH <Rt>, [<Rn>, <Rm>]\r
+\r
+ { "SUB", 0x1e00, 0xfe00, DATA_FORMAT2 },\r
+ { "SUB", 0x3800, 0xf800, DATA_FORMAT3 },\r
+ { "SUB", 0x1a00, 0xfe00, DATA_FORMAT1 },\r
+ { "SUB", 0xb080, 0xff80, DATA_FORMAT7 },\r
+\r
+ { "SBC", 0x4180, 0xffc0, DATA_FORMAT5 },\r
+\r
+ { "SWI", 0xdf00, 0xff00, IMMED_8 },\r
+ { "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },\r
+ { "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },\r
+ { "TST", 0x4200, 0xffc0, DATA_FORMAT5 },\r
+ { "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },\r
+ { "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 },\r
+\r
+ { "IT", 0xbf00, 0xff00, IT_BLOCK }\r
};\r
\r
-THUMB_INSTRUCTIONS gOpThumb2[] = {\r
-//Instruct OpCode OpCode Mask Addressig Mode\r
-\r
- { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW\r
- { "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, #<const> ;Needs to go before ADD\r
- { "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}\r
- { "CMP", 0xf1a00f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>\r
- { "TEQ", 0xf0900f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>\r
- { "TEQ", 0xea900f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}\r
- { "TST", 0xf0100f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>\r
- { "TST", 0xea100f00, 0xfff08f00, ADD_IMM5_2REG }, // TST <Rn>, <Rm> {,<shift> #<const>}\r
-\r
- { "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV <Rd>, #<const>\r
- { "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW <Rd>, #<const>\r
- { "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT <Rd>, #<const>\r
-\r
- { "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>\r
- { "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
- { "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>\r
- { "ADD", 0xeb000000, 0xffe08000, ADD_IMM5 }, // ADD{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
- { "ADDW", 0xf2000000, 0xfbe08000, ADD_IMM12 }, // ADDW{S} <Rd>, <Rn>, #<const>\r
- { "AND", 0xf0000000, 0xfbe08000, ADD_IMM12 }, // AND{S} <Rd>, <Rn>, #<const>\r
- { "AND", 0xea000000, 0xffe08000, ADD_IMM5 }, // AND{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
- { "BIC", 0xf0200000, 0xfbe08000, ADD_IMM12 }, // BIC{S} <Rd>, <Rn>, #<const>\r
- { "BIC", 0xea200000, 0xffe08000, ADD_IMM5 }, // BIC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
- { "EOR", 0xf0800000, 0xfbe08000, ADD_IMM12 }, // EOR{S} <Rd>, <Rn>, #<const>\r
- { "EOR", 0xea800000, 0xffe08000, ADD_IMM5 }, // EOR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
- { "ORN", 0xf0600000, 0xfbe08000, ADD_IMM12 }, // ORN{S} <Rd>, <Rn>, #<const>\r
- { "ORN", 0xea600000, 0xffe08000, ADD_IMM5 }, // ORN{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
- { "ORR", 0xf0400000, 0xfbe08000, ADD_IMM12 }, // ORR{S} <Rd>, <Rn>, #<const>\r
- { "ORR", 0xea400000, 0xffe08000, ADD_IMM5 }, // ORR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
- { "RSB", 0xf1c00000, 0xfbe08000, ADD_IMM12 }, // RSB{S} <Rd>, <Rn>, #<const>\r
- { "RSB", 0xebc00000, 0xffe08000, ADD_IMM5 }, // RSB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
- { "SBC", 0xf1600000, 0xfbe08000, ADD_IMM12 }, // SBC{S} <Rd>, <Rn>, #<const>\r
- { "SBC", 0xeb600000, 0xffe08000, ADD_IMM5 }, // SBC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
- { "SUB", 0xf1a00000, 0xfbe08000, ADD_IMM12 }, // SUB{S} <Rd>, <Rn>, #<const>\r
- { "SUB", 0xeba00000, 0xffe08000, ADD_IMM5 }, // SUB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
-\r
- { "ASR", 0xea4f0020, 0xffef8030, ASR_IMM5 }, // ARS <Rd>, <Rm> #<const>} imm3:imm2\r
- { "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm>\r
- { "LSR", 0xea4f0010, 0xffef8030, ASR_IMM5 }, // LSR <Rd>, <Rm> #<const>} imm3:imm2\r
- { "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm>\r
- { "ROR", 0xea4f0030, 0xffef8030, ASR_IMM5 }, // ROR <Rd>, <Rm> #<const>} imm3:imm2\r
- { "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm>\r
-\r
- { "BFC", 0xf36f0000, 0xffff8010, BFC_THUMB2 }, // BFC <Rd>, #<lsb>, #<width>\r
- { "BIC", 0xf3600000, 0xfff08010, BFC_THUMB2 }, // BIC <Rn>, <Rd>, #<lsb>, #<width>\r
- { "SBFX", 0xf3400000, 0xfff08010, BFC_THUMB2 }, // SBFX <Rn>, <Rd>, #<lsb>, #<width>\r
- { "UBFX", 0xf3c00000, 0xfff08010, BFC_THUMB2 }, // UBFX <Rn>, <Rd>, #<lsb>, #<width>\r
-\r
- { "CPD", 0xee000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>\r
- { "CPD2", 0xfe000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>\r
-\r
- { "MRC", 0xee100000, 0xff100000, MRC_THUMB2 }, // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>\r
- { "MRC2", 0xfe100000, 0xff100000, MRC_THUMB2 }, // MRC2 <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>\r
- { "MRRC", 0xec500000, 0xfff00000, MRRC_THUMB2 }, // MRRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>\r
- { "MRRC2", 0xfc500000, 0xfff00000, MRRC_THUMB2 }, // MRR2 <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>\r
-\r
- { "MRS", 0xf3ef8000, 0xfffff0ff, THUMB2_MRS }, // MRS <Rd>, CPSR\r
- { "MSR", 0xf3808000, 0xfff0fcff, THUMB2_MSR }, // MSR CPSR_fs, <Rn>\r
-\r
- { "CLREX", 0xf3bf8f2f, 0xfffffff, THUMB2_NO_ARGS }, // CLREX\r
-\r
- { "CLZ", 0xfab0f080, 0xfff0f0f0, THUMB2_2REGS }, // CLZ <Rd>,<Rm>\r
- { "MOV", 0xec4f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOV <Rd>,<Rm>\r
- { "MOVS", 0xec5f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOVS <Rd>,<Rm>\r
- { "RBIT", 0xfb90f0a0, 0xfff0f0f0, THUMB2_2REGS }, // RBIT <Rd>,<Rm>\r
- { "REV", 0xfb90f080, 0xfff0f0f0, THUMB2_2REGS }, // REV <Rd>,<Rm>\r
- { "REV16", 0xfa90f090, 0xfff0f0f0, THUMB2_2REGS }, // REV16 <Rd>,<Rm>\r
- { "REVSH", 0xfa90f0b0, 0xfff0f0f0, THUMB2_2REGS }, // REVSH <Rd>,<Rm>\r
- { "RRX", 0xea4f0030, 0xfffff0f0, THUMB2_2REGS }, // RRX <Rd>,<Rm>\r
- { "RRXS", 0xea5f0030, 0xfffff0f0, THUMB2_2REGS }, // RRXS <Rd>,<Rm>\r
-\r
- { "MLA", 0xfb000000, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>\r
- { "MLS", 0xfb000010, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>\r
-\r
-\r
- { "SMLABB", 0xfb100000, 0xfff000f0, THUMB2_4REGS }, // SMLABB <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLABT", 0xfb100010, 0xfff000f0, THUMB2_4REGS }, // SMLABT <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLABB", 0xfb100020, 0xfff000f0, THUMB2_4REGS }, // SMLATB <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLATT", 0xfb100030, 0xfff000f0, THUMB2_4REGS }, // SMLATT <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS }, // SMLAWB <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS }, // SMLAWT <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS }, // SMLSD <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS }, // SMLSDX <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS }, // SMMLA <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS }, // SMMLAR <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS }, // SMMLS <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS }, // SMMLSR <Rd>, <Rn>, <Rm>, <Ra>\r
- { "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS }, // USADA8 <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS }, // SMLAD <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS }, // SMLADX <Rd>, <Rn>, <Rm>, <Ra>\r
-\r
-\r
- { "B", 0xf0008000, 0xf800d000, B_T3 }, // B<c> <label>\r
- { "B", 0xf0009000, 0xf800d000, B_T4 }, // B<c> <label>\r
- { "BL", 0xf000d000, 0xf800d000, B_T4 }, // BL<c> <label>\r
- { "BLX", 0xf000c000, 0xf800d000, BL_T2 }, // BLX<c> <label>\r
-\r
- { "POP", 0xe8bd0000, 0xffff2000, POP_T2 }, // POP <registers>\r
- { "POP", 0xf85d0b04, 0xffff0fff, POP_T3 }, // POP <register>\r
- { "PUSH", 0xe8ad0000, 0xffffa000, POP_T2 }, // PUSH <registers>\r
- { "PUSH", 0xf84d0d04, 0xffff0fff, POP_T3 }, // PUSH <register>\r
- { "STM" , 0xe8800000, 0xffd0a000, STM_FORMAT }, // STM <Rn>{!},<registers>\r
- { "STMDB", 0xe9800000, 0xffd0a000, STM_FORMAT }, // STMDB <Rn>{!},<registers>\r
- { "LDM" , 0xe8900000, 0xffd02000, STM_FORMAT }, // LDM <Rn>{!},<registers>\r
- { "LDMDB", 0xe9100000, 0xffd02000, STM_FORMAT }, // LDMDB <Rn>{!},<registers>\r
-\r
- { "LDR", 0xf8d00000, 0xfff00000, LDM_REG_IMM12 }, // LDR <rt>, [<rn>, {, #<imm12>]}\r
- { "LDRB", 0xf8900000, 0xfff00000, LDM_REG_IMM12 }, // LDRB <rt>, [<rn>, {, #<imm12>]}\r
- { "LDRH", 0xf8b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRH <rt>, [<rn>, {, #<imm12>]}\r
- { "LDRSB", 0xf9900000, 0xfff00000, LDM_REG_IMM12 }, // LDRSB <rt>, [<rn>, {, #<imm12>]}\r
- { "LDRSH", 0xf9b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRSH <rt>, [<rn>, {, #<imm12>]}\r
-\r
- { "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label>\r
- { "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label>\r
- { "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label>\r
- { "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>\r
- { "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>\r
-\r
- { "LDR", 0xf8500000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDR <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
- { "LDRB", 0xf8100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
- { "LDRH", 0xf8300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
- { "LDRSB", 0xf9100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
- { "LDRSH", 0xf9300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
-\r
- { "LDR", 0xf8500800, 0xfff00800, LDM_REG_IMM8 }, // LDR <rt>, [<rn>, {, #<imm8>]}\r
- { "LDRBT", 0xf8100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRBT <rt>, [<rn>, {, #<imm8>]}\r
- { "LDRHT", 0xf8300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]}\r
- { "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form?\r
- { "LDRSBT",0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form?\r
- { "LDRSH" ,0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]}\r
- { "LDRSHT",0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]}\r
- { "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]}\r
-\r
- { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
- { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8 }, // LDRD <rt>, <rt2>, <label>\r
-\r
- { "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]]\r
- { "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>]\r
- { "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>]\r
-\r
- { "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>]\r
-\r
- { "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]}\r
- { "STRB", 0xf8800000, 0xfff00000, LDM_REG_IMM12 }, // STRB <rt>, [<rn>, {, #<imm12>]}\r
- { "STRH", 0xf8a00000, 0xfff00000, LDM_REG_IMM12 }, // STRH <rt>, [<rn>, {, #<imm12>]}\r
-\r
- { "STR", 0xf8400000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STR <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
- { "STRB", 0xf8000000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
- { "STRH", 0xf8200000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
-\r
- { "STR", 0xf8400800, 0xfff00800, LDM_REG_IMM8 }, // STR <rt>, [<rn>, {, #<imm8>]}\r
- { "STRH", 0xf8200800, 0xfff00800, LDM_REG_IMM8 }, // STRH <rt>, [<rn>, {, #<imm8>]}\r
- { "STRBT", 0xf8000e00, 0xfff00f00, LDM_REG_IMM8 }, // STRBT <rt>, [<rn>, {, #<imm8>]}\r
- { "STRHT", 0xf8200e00, 0xfff00f00, LDM_REG_IMM8 }, // STRHT <rt>, [<rn>, {, #<imm8>]}\r
- { "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]}\r
-\r
- { "STRD", 0xe8400000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // STRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
-\r
- { "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]]\r
- { "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>]\r
- { "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>]\r
-\r
- { "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]\r
-\r
- { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>\r
- { "SRS" , 0xe98dc000, 0xffdffff0, SRS_FORMAT }, // SRS{IA}<c> SP{!},#<mode>\r
- { "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}\r
- { "RFE" , 0xe990c000, 0xffd0ffff, RFE_FORMAT } // RFE{IA}<c> <Rn>{!}\r
+THUMB_INSTRUCTIONS gOpThumb2[] = {\r
+ // Instruct OpCode OpCode Mask Addressig Mode\r
+\r
+ { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW\r
+ { "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, #<const> ;Needs to go before ADD\r
+ { "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}\r
+ { "CMP", 0xf1a00f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>\r
+ { "TEQ", 0xf0900f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>\r
+ { "TEQ", 0xea900f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}\r
+ { "TST", 0xf0100f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>\r
+ { "TST", 0xea100f00, 0xfff08f00, ADD_IMM5_2REG }, // TST <Rn>, <Rm> {,<shift> #<const>}\r
+\r
+ { "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV <Rd>, #<const>\r
+ { "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW <Rd>, #<const>\r
+ { "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT <Rd>, #<const>\r
+\r
+ { "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>\r
+ { "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>\r
+ { "ADD", 0xeb000000, 0xffe08000, ADD_IMM5 }, // ADD{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "ADDW", 0xf2000000, 0xfbe08000, ADD_IMM12 }, // ADDW{S} <Rd>, <Rn>, #<const>\r
+ { "AND", 0xf0000000, 0xfbe08000, ADD_IMM12 }, // AND{S} <Rd>, <Rn>, #<const>\r
+ { "AND", 0xea000000, 0xffe08000, ADD_IMM5 }, // AND{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "BIC", 0xf0200000, 0xfbe08000, ADD_IMM12 }, // BIC{S} <Rd>, <Rn>, #<const>\r
+ { "BIC", 0xea200000, 0xffe08000, ADD_IMM5 }, // BIC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "EOR", 0xf0800000, 0xfbe08000, ADD_IMM12 }, // EOR{S} <Rd>, <Rn>, #<const>\r
+ { "EOR", 0xea800000, 0xffe08000, ADD_IMM5 }, // EOR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "ORN", 0xf0600000, 0xfbe08000, ADD_IMM12 }, // ORN{S} <Rd>, <Rn>, #<const>\r
+ { "ORN", 0xea600000, 0xffe08000, ADD_IMM5 }, // ORN{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "ORR", 0xf0400000, 0xfbe08000, ADD_IMM12 }, // ORR{S} <Rd>, <Rn>, #<const>\r
+ { "ORR", 0xea400000, 0xffe08000, ADD_IMM5 }, // ORR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "RSB", 0xf1c00000, 0xfbe08000, ADD_IMM12 }, // RSB{S} <Rd>, <Rn>, #<const>\r
+ { "RSB", 0xebc00000, 0xffe08000, ADD_IMM5 }, // RSB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "SBC", 0xf1600000, 0xfbe08000, ADD_IMM12 }, // SBC{S} <Rd>, <Rn>, #<const>\r
+ { "SBC", 0xeb600000, 0xffe08000, ADD_IMM5 }, // SBC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "SUB", 0xf1a00000, 0xfbe08000, ADD_IMM12 }, // SUB{S} <Rd>, <Rn>, #<const>\r
+ { "SUB", 0xeba00000, 0xffe08000, ADD_IMM5 }, // SUB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+\r
+ { "ASR", 0xea4f0020, 0xffef8030, ASR_IMM5 }, // ARS <Rd>, <Rm> #<const>} imm3:imm2\r
+ { "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm>\r
+ { "LSR", 0xea4f0010, 0xffef8030, ASR_IMM5 }, // LSR <Rd>, <Rm> #<const>} imm3:imm2\r
+ { "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm>\r
+ { "ROR", 0xea4f0030, 0xffef8030, ASR_IMM5 }, // ROR <Rd>, <Rm> #<const>} imm3:imm2\r
+ { "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm>\r
+\r
+ { "BFC", 0xf36f0000, 0xffff8010, BFC_THUMB2 }, // BFC <Rd>, #<lsb>, #<width>\r
+ { "BIC", 0xf3600000, 0xfff08010, BFC_THUMB2 }, // BIC <Rn>, <Rd>, #<lsb>, #<width>\r
+ { "SBFX", 0xf3400000, 0xfff08010, BFC_THUMB2 }, // SBFX <Rn>, <Rd>, #<lsb>, #<width>\r
+ { "UBFX", 0xf3c00000, 0xfff08010, BFC_THUMB2 }, // UBFX <Rn>, <Rd>, #<lsb>, #<width>\r
+\r
+ { "CPD", 0xee000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>\r
+ { "CPD2", 0xfe000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>\r
+\r
+ { "MRC", 0xee100000, 0xff100000, MRC_THUMB2 }, // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>\r
+ { "MRC2", 0xfe100000, 0xff100000, MRC_THUMB2 }, // MRC2 <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>\r
+ { "MRRC", 0xec500000, 0xfff00000, MRRC_THUMB2 }, // MRRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>\r
+ { "MRRC2", 0xfc500000, 0xfff00000, MRRC_THUMB2 }, // MRR2 <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>\r
+\r
+ { "MRS", 0xf3ef8000, 0xfffff0ff, THUMB2_MRS }, // MRS <Rd>, CPSR\r
+ { "MSR", 0xf3808000, 0xfff0fcff, THUMB2_MSR }, // MSR CPSR_fs, <Rn>\r
+\r
+ { "CLREX", 0xf3bf8f2f, 0xfffffff, THUMB2_NO_ARGS }, // CLREX\r
+\r
+ { "CLZ", 0xfab0f080, 0xfff0f0f0, THUMB2_2REGS }, // CLZ <Rd>,<Rm>\r
+ { "MOV", 0xec4f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOV <Rd>,<Rm>\r
+ { "MOVS", 0xec5f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOVS <Rd>,<Rm>\r
+ { "RBIT", 0xfb90f0a0, 0xfff0f0f0, THUMB2_2REGS }, // RBIT <Rd>,<Rm>\r
+ { "REV", 0xfb90f080, 0xfff0f0f0, THUMB2_2REGS }, // REV <Rd>,<Rm>\r
+ { "REV16", 0xfa90f090, 0xfff0f0f0, THUMB2_2REGS }, // REV16 <Rd>,<Rm>\r
+ { "REVSH", 0xfa90f0b0, 0xfff0f0f0, THUMB2_2REGS }, // REVSH <Rd>,<Rm>\r
+ { "RRX", 0xea4f0030, 0xfffff0f0, THUMB2_2REGS }, // RRX <Rd>,<Rm>\r
+ { "RRXS", 0xea5f0030, 0xfffff0f0, THUMB2_2REGS }, // RRXS <Rd>,<Rm>\r
+\r
+ { "MLA", 0xfb000000, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "MLS", 0xfb000010, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>\r
+\r
+ { "SMLABB", 0xfb100000, 0xfff000f0, THUMB2_4REGS }, // SMLABB <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLABT", 0xfb100010, 0xfff000f0, THUMB2_4REGS }, // SMLABT <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLABB", 0xfb100020, 0xfff000f0, THUMB2_4REGS }, // SMLATB <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLATT", 0xfb100030, 0xfff000f0, THUMB2_4REGS }, // SMLATT <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS }, // SMLAWB <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS }, // SMLAWT <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS }, // SMLSD <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS }, // SMLSDX <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS }, // SMMLA <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS }, // SMMLAR <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS }, // SMMLS <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS }, // SMMLSR <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS }, // USADA8 <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS }, // SMLAD <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS }, // SMLADX <Rd>, <Rn>, <Rm>, <Ra>\r
+\r
+ { "B", 0xf0008000, 0xf800d000, B_T3 }, // B<c> <label>\r
+ { "B", 0xf0009000, 0xf800d000, B_T4 }, // B<c> <label>\r
+ { "BL", 0xf000d000, 0xf800d000, B_T4 }, // BL<c> <label>\r
+ { "BLX", 0xf000c000, 0xf800d000, BL_T2 }, // BLX<c> <label>\r
+\r
+ { "POP", 0xe8bd0000, 0xffff2000, POP_T2 }, // POP <registers>\r
+ { "POP", 0xf85d0b04, 0xffff0fff, POP_T3 }, // POP <register>\r
+ { "PUSH", 0xe8ad0000, 0xffffa000, POP_T2 }, // PUSH <registers>\r
+ { "PUSH", 0xf84d0d04, 0xffff0fff, POP_T3 }, // PUSH <register>\r
+ { "STM", 0xe8800000, 0xffd0a000, STM_FORMAT }, // STM <Rn>{!},<registers>\r
+ { "STMDB", 0xe9800000, 0xffd0a000, STM_FORMAT }, // STMDB <Rn>{!},<registers>\r
+ { "LDM", 0xe8900000, 0xffd02000, STM_FORMAT }, // LDM <Rn>{!},<registers>\r
+ { "LDMDB", 0xe9100000, 0xffd02000, STM_FORMAT }, // LDMDB <Rn>{!},<registers>\r
+\r
+ { "LDR", 0xf8d00000, 0xfff00000, LDM_REG_IMM12 }, // LDR <rt>, [<rn>, {, #<imm12>]}\r
+ { "LDRB", 0xf8900000, 0xfff00000, LDM_REG_IMM12 }, // LDRB <rt>, [<rn>, {, #<imm12>]}\r
+ { "LDRH", 0xf8b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRH <rt>, [<rn>, {, #<imm12>]}\r
+ { "LDRSB", 0xf9900000, 0xfff00000, LDM_REG_IMM12 }, // LDRSB <rt>, [<rn>, {, #<imm12>]}\r
+ { "LDRSH", 0xf9b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRSH <rt>, [<rn>, {, #<imm12>]}\r
+\r
+ { "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label>\r
+ { "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label>\r
+ { "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label>\r
+ { "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>\r
+ { "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>\r
+\r
+ { "LDR", 0xf8500000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDR <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ { "LDRB", 0xf8100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ { "LDRH", 0xf8300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ { "LDRSB", 0xf9100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ { "LDRSH", 0xf9300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+\r
+ { "LDR", 0xf8500800, 0xfff00800, LDM_REG_IMM8 }, // LDR <rt>, [<rn>, {, #<imm8>]}\r
+ { "LDRBT", 0xf8100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRBT <rt>, [<rn>, {, #<imm8>]}\r
+ { "LDRHT", 0xf8300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]}\r
+ { "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form?\r
+ { "LDRSBT", 0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form?\r
+ { "LDRSH", 0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]}\r
+ { "LDRSHT", 0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]}\r
+ { "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]}\r
+\r
+ { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
+ { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8 }, // LDRD <rt>, <rt2>, <label>\r
+\r
+ { "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]]\r
+ { "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>]\r
+ { "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>]\r
+\r
+ { "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>]\r
+\r
+ { "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]}\r
+ { "STRB", 0xf8800000, 0xfff00000, LDM_REG_IMM12 }, // STRB <rt>, [<rn>, {, #<imm12>]}\r
+ { "STRH", 0xf8a00000, 0xfff00000, LDM_REG_IMM12 }, // STRH <rt>, [<rn>, {, #<imm12>]}\r
+\r
+ { "STR", 0xf8400000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STR <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ { "STRB", 0xf8000000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ { "STRH", 0xf8200000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+\r
+ { "STR", 0xf8400800, 0xfff00800, LDM_REG_IMM8 }, // STR <rt>, [<rn>, {, #<imm8>]}\r
+ { "STRH", 0xf8200800, 0xfff00800, LDM_REG_IMM8 }, // STRH <rt>, [<rn>, {, #<imm8>]}\r
+ { "STRBT", 0xf8000e00, 0xfff00f00, LDM_REG_IMM8 }, // STRBT <rt>, [<rn>, {, #<imm8>]}\r
+ { "STRHT", 0xf8200e00, 0xfff00f00, LDM_REG_IMM8 }, // STRHT <rt>, [<rn>, {, #<imm8>]}\r
+ { "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]}\r
+\r
+ { "STRD", 0xe8400000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // STRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
+\r
+ { "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]]\r
+ { "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>]\r
+ { "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>]\r
+\r
+ { "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]\r
+\r
+ { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>\r
+ { "SRS", 0xe98dc000, 0xffdffff0, SRS_FORMAT }, // SRS{IA}<c> SP{!},#<mode>\r
+ { "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}\r
+ { "RFE", 0xe990c000, 0xffd0ffff, RFE_FORMAT } // RFE{IA}<c> <Rn>{!}\r
};\r
\r
-CHAR8 *gShiftType[] = {\r
+CHAR8 *gShiftType[] = {\r
"LSL",\r
"LSR",\r
"ASR",\r
"ROR"\r
};\r
\r
-CHAR8 mThumbMregListStr[4*15 + 1];\r
+CHAR8 mThumbMregListStr[4*15 + 1];\r
\r
CHAR8 *\r
ThumbMRegList (\r
UINT32 RegBitMask\r
)\r
{\r
- UINTN Index, Start, End;\r
- BOOLEAN First;\r
+ UINTN Index, Start, End;\r
+ BOOLEAN First;\r
\r
mThumbMregListStr[0] = '\0';\r
AsciiStrCatS (mThumbMregListStr, sizeof mThumbMregListStr, "{");\r
}\r
}\r
}\r
+\r
if (First) {\r
AsciiStrCatS (mThumbMregListStr, sizeof mThumbMregListStr, "ERROR");\r
}\r
+\r
AsciiStrCatS (mThumbMregListStr, sizeof mThumbMregListStr, "}");\r
\r
// BugBug: Make caller pass in buffer it is cleaner\r
\r
do {\r
TopBit <<= 1;\r
- Data |= TopBit;\r
+ Data |= TopBit;\r
} while ((TopBit & BIT31) != BIT31);\r
\r
return Data;\r
**/\r
VOID\r
DisassembleThumbInstruction (\r
- IN UINT16 **OpCodePtrPtr,\r
- OUT CHAR8 *Buf,\r
- OUT UINTN Size,\r
- OUT UINT32 *ItBlock,\r
- IN BOOLEAN Extended\r
+ IN UINT16 **OpCodePtrPtr,\r
+ OUT CHAR8 *Buf,\r
+ OUT UINTN Size,\r
+ OUT UINT32 *ItBlock,\r
+ IN BOOLEAN Extended\r
)\r
{\r
- UINT16 *OpCodePtr;\r
- UINT16 OpCode;\r
- UINT32 OpCode32;\r
- UINT32 Index;\r
- UINT32 Offset;\r
- UINT16 Rd, Rn, Rm, Rt, Rt2;\r
- BOOLEAN H1Bit; // H1\r
- BOOLEAN H2Bit; // H2\r
- BOOLEAN IMod; // imod\r
- //BOOLEAN ItFlag;\r
- UINT32 Pc, Target, MsBit, LsBit;\r
- CHAR8 *Cond;\r
- BOOLEAN Sign; // S\r
- BOOLEAN J1Bit; // J1\r
- BOOLEAN J2Bit; // J2\r
- BOOLEAN Pre; // P\r
- BOOLEAN UAdd; // U\r
- BOOLEAN WriteBack; // W\r
- UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;\r
- UINT32 Mask;\r
+ UINT16 *OpCodePtr;\r
+ UINT16 OpCode;\r
+ UINT32 OpCode32;\r
+ UINT32 Index;\r
+ UINT32 Offset;\r
+ UINT16 Rd, Rn, Rm, Rt, Rt2;\r
+ BOOLEAN H1Bit; // H1\r
+ BOOLEAN H2Bit; // H2\r
+ BOOLEAN IMod; // imod\r
+ // BOOLEAN ItFlag;\r
+ UINT32 Pc, Target, MsBit, LsBit;\r
+ CHAR8 *Cond;\r
+ BOOLEAN Sign; // S\r
+ BOOLEAN J1Bit; // J1\r
+ BOOLEAN J2Bit; // J2\r
+ BOOLEAN Pre; // P\r
+ BOOLEAN UAdd; // U\r
+ BOOLEAN WriteBack; // W\r
+ UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;\r
+ UINT32 Mask;\r
\r
OpCodePtr = *OpCodePtrPtr;\r
- OpCode = **OpCodePtrPtr;\r
+ OpCode = **OpCodePtrPtr;\r
\r
// Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.\r
OpCode32 = (((UINT32)OpCode) << 16) | *(OpCodePtr + 1);\r
\r
// These register names match branch form, but not others\r
- Rd = OpCode & 0x7;\r
- Rn = (OpCode >> 3) & 0x7;\r
- Rm = (OpCode >> 6) & 0x7;\r
+ Rd = OpCode & 0x7;\r
+ Rn = (OpCode >> 3) & 0x7;\r
+ Rm = (OpCode >> 6) & 0x7;\r
H1Bit = (OpCode & BIT7) != 0;\r
H2Bit = (OpCode & BIT6) != 0;\r
- IMod = (OpCode & BIT4) != 0;\r
- Pc = (UINT32)(UINTN)OpCodePtr;\r
+ IMod = (OpCode & BIT4) != 0;\r
+ Pc = (UINT32)(UINTN)OpCodePtr;\r
\r
// Increment by the minimum instruction size, Thumb2 could be bigger\r
*OpCodePtrPtr += 1;\r
\r
// Manage IT Block ItFlag TRUE means we are in an IT block\r
+\r
/*if (*ItBlock != 0) {\r
ItFlag = TRUE;\r
*ItBlock -= 1;\r
} else {\r
Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start);\r
}\r
+\r
switch (gOpThumb[Index].AddressMode) {\r
- case LOAD_STORE_FORMAT1:\r
- // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);\r
- return;\r
- case LOAD_STORE_FORMAT1_H:\r
- // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);\r
- return;\r
- case LOAD_STORE_FORMAT1_B:\r
- // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);\r
- return;\r
-\r
- case LOAD_STORE_FORMAT2:\r
- // A6.5.1 <Rd>, [<Rn>, <Rm>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);\r
- return;\r
- case LOAD_STORE_FORMAT3:\r
- // A6.5.1 <Rd>, [PC, #<8_bit_offset>]\r
- Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);\r
- return;\r
- case LOAD_STORE_FORMAT4:\r
- // Rt, [SP, #imm8]\r
- Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);\r
- return;\r
-\r
- case LOAD_STORE_MULTIPLE_FORMAT1:\r
- // <Rn>!, {r0-r7}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));\r
- return;\r
-\r
- case POP_FORMAT:\r
- // POP {r0-r7,pc}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));\r
- return;\r
-\r
- case PUSH_FORMAT:\r
- // PUSH {r0-r7,lr}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));\r
- return;\r
-\r
-\r
- case IMMED_8:\r
- // A6.7 <immed_8>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);\r
- return;\r
-\r
- case CONDITIONAL_BRANCH:\r
- // A6.3.1 B<cond> <target_address>\r
- // Patch in the condition code. A little hack but based on "%-6a"\r
- Cond = gCondition[(OpCode >> 8) & 0xf];\r
- Buf[Offset-5] = *Cond++;\r
- Buf[Offset-4] = *Cond;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));\r
- return;\r
- case UNCONDITIONAL_BRANCH_SHORT:\r
- // A6.3.2 B <target_address>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));\r
- return;\r
-\r
- case BRANCH_EXCHANGE:\r
- // A6.3.3 BX|BLX <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8:0)]);\r
- return;\r
-\r
- case DATA_FORMAT1:\r
- // A6.4.3 <Rd>, <Rn>, <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);\r
- return;\r
- case DATA_FORMAT2:\r
- // A6.4.3 <Rd>, <Rn>, #3_bit_immed\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);\r
- return;\r
- case DATA_FORMAT3:\r
- // A6.4.3 <Rd>|<Rn>, #imm8\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);\r
- return;\r
- case DATA_FORMAT4:\r
- // A6.4.3 <Rd>|<Rm>, #immed_5\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);\r
- return;\r
- case DATA_FORMAT5:\r
- // A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);\r
- return;\r
- case DATA_FORMAT6_SP:\r
- // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);\r
- return;\r
- case DATA_FORMAT6_PC:\r
- // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);\r
- return;\r
- case DATA_FORMAT7:\r
- // A6.4.3 SP, SP, #<7_Bit_immed>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);\r
- return;\r
- case DATA_FORMAT8:\r
- // A6.4.3 <Rd>|<Rn>, <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8:0)], gReg[Rn | (H2Bit ? 8:0)]);\r
- return;\r
-\r
- case CPS_FORMAT:\r
- // A7.1.24\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");\r
- return;\r
-\r
- case ENDIAN_FORMAT:\r
- // A7.1.24\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");\r
- return;\r
-\r
- case DATA_CBZ:\r
- // CB{N}Z <Rn>, <Lable>\r
- Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);\r
- return;\r
-\r
- case ADR_FORMAT:\r
- // ADR <Rd>, <Label>\r
- Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);\r
- return;\r
-\r
- case IT_BLOCK:\r
- // ITSTATE = cond:mask OpCode[7:4]:OpCode[3:0]\r
- // ITSTATE[7:5] == cond[3:1]\r
- // ITSTATE[4] == 1st Instruction cond[0]\r
- // ITSTATE[3] == 2st Instruction cond[0]\r
- // ITSTATE[2] == 3st Instruction cond[0]\r
- // ITSTATE[1] == 4st Instruction cond[0]\r
- // ITSTATE[0] == 1 4 instruction IT block. 0 means 0,1,2 or 3 instructions\r
- // 1st one in ITSTATE low bits defines the number of instructions\r
- Mask = (OpCode & 0xf);\r
- if ((Mask & 0x1) == 0x1) {\r
- *ItBlock = 4;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a%a", (Mask & BIT3)?"T":"E", (Mask & BIT2)?"T":"E", (Mask & BIT1)?"T":"E");\r
- } else if ((OpCode & 0x3) == 0x2) {\r
- *ItBlock = 3;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a", (Mask & BIT3)?"T":"E", (Mask & BIT2)?"T":"E");\r
- } else if ((OpCode & 0x7) == 0x4) {\r
- *ItBlock = 2;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a", (Mask & BIT3)?"T":"E");\r
- } else if ((OpCode & 0xf) == 0x8) {\r
- *ItBlock = 1;\r
- }\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]);\r
- return;\r
+ case LOAD_STORE_FORMAT1:\r
+ // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);\r
+ return;\r
+ case LOAD_STORE_FORMAT1_H:\r
+ // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);\r
+ return;\r
+ case LOAD_STORE_FORMAT1_B:\r
+ // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);\r
+ return;\r
+\r
+ case LOAD_STORE_FORMAT2:\r
+ // A6.5.1 <Rd>, [<Rn>, <Rm>]\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);\r
+ return;\r
+ case LOAD_STORE_FORMAT3:\r
+ // A6.5.1 <Rd>, [PC, #<8_bit_offset>]\r
+ Target = (OpCode & 0xff) << 2;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);\r
+ return;\r
+ case LOAD_STORE_FORMAT4:\r
+ // Rt, [SP, #imm8]\r
+ Target = (OpCode & 0xff) << 2;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);\r
+ return;\r
+\r
+ case LOAD_STORE_MULTIPLE_FORMAT1:\r
+ // <Rn>!, {r0-r7}\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));\r
+ return;\r
+\r
+ case POP_FORMAT:\r
+ // POP {r0-r7,pc}\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));\r
+ return;\r
+\r
+ case PUSH_FORMAT:\r
+ // PUSH {r0-r7,lr}\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));\r
+ return;\r
+\r
+ case IMMED_8:\r
+ // A6.7 <immed_8>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);\r
+ return;\r
+\r
+ case CONDITIONAL_BRANCH:\r
+ // A6.3.1 B<cond> <target_address>\r
+ // Patch in the condition code. A little hack but based on "%-6a"\r
+ Cond = gCondition[(OpCode >> 8) & 0xf];\r
+ Buf[Offset-5] = *Cond++;\r
+ Buf[Offset-4] = *Cond;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));\r
+ return;\r
+ case UNCONDITIONAL_BRANCH_SHORT:\r
+ // A6.3.2 B <target_address>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));\r
+ return;\r
+\r
+ case BRANCH_EXCHANGE:\r
+ // A6.3.3 BX|BLX <Rm>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8 : 0)]);\r
+ return;\r
+\r
+ case DATA_FORMAT1:\r
+ // A6.4.3 <Rd>, <Rn>, <Rm>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);\r
+ return;\r
+ case DATA_FORMAT2:\r
+ // A6.4.3 <Rd>, <Rn>, #3_bit_immed\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);\r
+ return;\r
+ case DATA_FORMAT3:\r
+ // A6.4.3 <Rd>|<Rn>, #imm8\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);\r
+ return;\r
+ case DATA_FORMAT4:\r
+ // A6.4.3 <Rd>|<Rm>, #immed_5\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);\r
+ return;\r
+ case DATA_FORMAT5:\r
+ // A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);\r
+ return;\r
+ case DATA_FORMAT6_SP:\r
+ // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);\r
+ return;\r
+ case DATA_FORMAT6_PC:\r
+ // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);\r
+ return;\r
+ case DATA_FORMAT7:\r
+ // A6.4.3 SP, SP, #<7_Bit_immed>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);\r
+ return;\r
+ case DATA_FORMAT8:\r
+ // A6.4.3 <Rd>|<Rn>, <Rm>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8 : 0)], gReg[Rn | (H2Bit ? 8 : 0)]);\r
+ return;\r
+\r
+ case CPS_FORMAT:\r
+ // A7.1.24\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID" : "IE", ((OpCode & BIT2) == 0) ? "" : "a", ((OpCode & BIT1) == 0) ? "" : "i", ((OpCode & BIT0) == 0) ? "" : "f");\r
+ return;\r
+\r
+ case ENDIAN_FORMAT:\r
+ // A7.1.24\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE" : "BE");\r
+ return;\r
+\r
+ case DATA_CBZ:\r
+ // CB{N}Z <Rn>, <Lable>\r
+ Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);\r
+ return;\r
+\r
+ case ADR_FORMAT:\r
+ // ADR <Rd>, <Label>\r
+ Target = (OpCode & 0xff) << 2;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);\r
+ return;\r
+\r
+ case IT_BLOCK:\r
+ // ITSTATE = cond:mask OpCode[7:4]:OpCode[3:0]\r
+ // ITSTATE[7:5] == cond[3:1]\r
+ // ITSTATE[4] == 1st Instruction cond[0]\r
+ // ITSTATE[3] == 2st Instruction cond[0]\r
+ // ITSTATE[2] == 3st Instruction cond[0]\r
+ // ITSTATE[1] == 4st Instruction cond[0]\r
+ // ITSTATE[0] == 1 4 instruction IT block. 0 means 0,1,2 or 3 instructions\r
+ // 1st one in ITSTATE low bits defines the number of instructions\r
+ Mask = (OpCode & 0xf);\r
+ if ((Mask & 0x1) == 0x1) {\r
+ *ItBlock = 4;\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a%a", (Mask & BIT3) ? "T" : "E", (Mask & BIT2) ? "T" : "E", (Mask & BIT1) ? "T" : "E");\r
+ } else if ((OpCode & 0x3) == 0x2) {\r
+ *ItBlock = 3;\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a", (Mask & BIT3) ? "T" : "E", (Mask & BIT2) ? "T" : "E");\r
+ } else if ((OpCode & 0x7) == 0x4) {\r
+ *ItBlock = 2;\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a", (Mask & BIT3) ? "T" : "E");\r
+ } else if ((OpCode & 0xf) == 0x8) {\r
+ *ItBlock = 1;\r
+ }\r
+\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]);\r
+ return;\r
}\r
}\r
}\r
\r
-\r
// Thumb2 are 32-bit instructions\r
*OpCodePtrPtr += 1;\r
- Rt = (OpCode32 >> 12) & 0xf;\r
- Rt2 = (OpCode32 >> 8) & 0xf;\r
- Rd = (OpCode32 >> 8) & 0xf;\r
- Rm = (OpCode32 & 0xf);\r
- Rn = (OpCode32 >> 16) & 0xf;\r
+ Rt = (OpCode32 >> 12) & 0xf;\r
+ Rt2 = (OpCode32 >> 8) & 0xf;\r
+ Rd = (OpCode32 >> 8) & 0xf;\r
+ Rm = (OpCode32 & 0xf);\r
+ Rn = (OpCode32 >> 16) & 0xf;\r
for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {\r
if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {\r
if (Extended) {\r
} else {\r
Offset = AsciiSPrint (Buf, Size, " %-6a", gOpThumb2[Index].Start);\r
}\r
+\r
switch (gOpThumb2[Index].AddressMode) {\r
- case B_T3:\r
- Cond = gCondition[(OpCode32 >> 22) & 0xf];\r
- Buf[Offset-5] = *Cond++;\r
- Buf[Offset-4] = *Cond;\r
- // S:J2:J1:imm6:imm11:0\r
- Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3f000);\r
- Target |= ((OpCode32 & BIT11) == BIT11)? BIT19 : 0; // J2\r
- Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1\r
- Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S\r
- Target = SignExtend32 (Target, BIT20);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);\r
- return;\r
- case B_T4:\r
- // S:I1:I2:imm10:imm11:0\r
- Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);\r
- Sign = (OpCode32 & BIT26) == BIT26;\r
- J1Bit = (OpCode32 & BIT13) == BIT13;\r
- J2Bit = (OpCode32 & BIT11) == BIT11;\r
- Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2\r
- Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1\r
- Target |= (Sign ? BIT24 : 0); // S\r
- Target = SignExtend32 (Target, BIT24);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);\r
- return;\r
-\r
- case BL_T2:\r
- // BLX S:I1:I2:imm10:imm11:0\r
- Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);\r
- Sign = (OpCode32 & BIT26) == BIT26;\r
- J1Bit = (OpCode32 & BIT13) == BIT13;\r
- J2Bit = (OpCode32 & BIT11) == BIT11;\r
- Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2\r
- Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1\r
- Target |= (Sign ? BIT25 : 0); // S\r
- Target = SignExtend32 (Target, BIT25);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);\r
- return;\r
-\r
- case POP_T2:\r
- // <reglist> some must be zero, handled in table\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList (OpCode32 & 0xffff));\r
- return;\r
-\r
- case POP_T3:\r
- // <register>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[(OpCode32 >> 12) & 0xf]);\r
- return;\r
-\r
- case STM_FORMAT:\r
- // <Rn>{!}, <registers>\r
- WriteBack = (OpCode32 & BIT21) == BIT21;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!":"", ThumbMRegList (OpCode32 & 0xffff));\r
- return;\r
-\r
- case LDM_REG_IMM12_SIGNED:\r
- // <rt>, <label>\r
- Target = OpCode32 & 0xfff;\r
- if ((OpCode32 & BIT23) == 0) {\r
- // U == 0 means subtrack, U == 1 means add\r
- Target = -Target;\r
- }\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);\r
- return;\r
-\r
- case LDM_REG_INDIRECT_LSL:\r
- // <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a, %a", gReg[Rt], gReg[Rn], gReg[Rm]);\r
- if (((OpCode32 >> 4) & 3) == 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "]");\r
- } else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL #%d]", (OpCode32 >> 4) & 3);\r
- }\r
- return;\r
-\r
- case LDM_REG_IMM12:\r
- // <rt>, [<rn>, {, #<imm12>]}\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);\r
- if ((OpCode32 & 0xfff) == 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "]");\r
- } else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #0x%x]", OpCode32 & 0xfff);\r
- }\r
- return;\r
-\r
- case LDM_REG_IMM8:\r
- // <rt>, [<rn>, {, #<imm8>}]{!}\r
- WriteBack = (OpCode32 & BIT8) == BIT8;\r
- UAdd = (OpCode32 & BIT9) == BIT9;\r
- Pre = (OpCode32 & BIT10) == BIT10;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);\r
- if (Pre) {\r
- if ((OpCode32 & 0xff) == 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack?"!":"");\r
+ case B_T3:\r
+ Cond = gCondition[(OpCode32 >> 22) & 0xf];\r
+ Buf[Offset-5] = *Cond++;\r
+ Buf[Offset-4] = *Cond;\r
+ // S:J2:J1:imm6:imm11:0\r
+ Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3f000);\r
+ Target |= ((OpCode32 & BIT11) == BIT11) ? BIT19 : 0; // J2\r
+ Target |= ((OpCode32 & BIT13) == BIT13) ? BIT18 : 0; // J1\r
+ Target |= ((OpCode32 & BIT26) == BIT26) ? BIT20 : 0; // S\r
+ Target = SignExtend32 (Target, BIT20);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);\r
+ return;\r
+ case B_T4:\r
+ // S:I1:I2:imm10:imm11:0\r
+ Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);\r
+ Sign = (OpCode32 & BIT26) == BIT26;\r
+ J1Bit = (OpCode32 & BIT13) == BIT13;\r
+ J2Bit = (OpCode32 & BIT11) == BIT11;\r
+ Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2\r
+ Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1\r
+ Target |= (Sign ? BIT24 : 0); // S\r
+ Target = SignExtend32 (Target, BIT24);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);\r
+ return;\r
+\r
+ case BL_T2:\r
+ // BLX S:I1:I2:imm10:imm11:0\r
+ Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);\r
+ Sign = (OpCode32 & BIT26) == BIT26;\r
+ J1Bit = (OpCode32 & BIT13) == BIT13;\r
+ J2Bit = (OpCode32 & BIT11) == BIT11;\r
+ Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2\r
+ Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1\r
+ Target |= (Sign ? BIT25 : 0); // S\r
+ Target = SignExtend32 (Target, BIT25);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);\r
+ return;\r
+\r
+ case POP_T2:\r
+ // <reglist> some must be zero, handled in table\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList (OpCode32 & 0xffff));\r
+ return;\r
+\r
+ case POP_T3:\r
+ // <register>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[(OpCode32 >> 12) & 0xf]);\r
+ return;\r
+\r
+ case STM_FORMAT:\r
+ // <Rn>{!}, <registers>\r
+ WriteBack = (OpCode32 & BIT21) == BIT21;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!" : "", ThumbMRegList (OpCode32 & 0xffff));\r
+ return;\r
+\r
+ case LDM_REG_IMM12_SIGNED:\r
+ // <rt>, <label>\r
+ Target = OpCode32 & 0xfff;\r
+ if ((OpCode32 & BIT23) == 0) {\r
+ // U == 0 means subtrack, U == 1 means add\r
+ Target = -Target;\r
+ }\r
+\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);\r
+ return;\r
+\r
+ case LDM_REG_INDIRECT_LSL:\r
+ // <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a, %a", gReg[Rt], gReg[Rn], gReg[Rm]);\r
+ if (((OpCode32 >> 4) & 3) == 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]");\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-" , OpCode32 & 0xff, WriteBack?"!":"");\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL #%d]", (OpCode32 >> 4) & 3);\r
}\r
- } else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd?"":"-", OpCode32 & 0xff);\r
- }\r
- return;\r
-\r
- case LDRD_REG_IMM8_SIGNED:\r
- // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
- Pre = (OpCode32 & BIT24) == BIT24; // index = P\r
- UAdd = (OpCode32 & BIT23) == BIT23;\r
- WriteBack = (OpCode32 & BIT21) == BIT21;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);\r
- if (Pre) {\r
- if ((OpCode32 & 0xff) == 0) {\r
+\r
+ return;\r
+\r
+ case LDM_REG_IMM12:\r
+ // <rt>, [<rn>, {, #<imm12>]}\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);\r
+ if ((OpCode32 & 0xfff) == 0) {\r
AsciiSPrint (&Buf[Offset], Size - Offset, "]");\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-", (OpCode32 & 0xff) << 2, WriteBack?"!":"");\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #0x%x]", OpCode32 & 0xfff);\r
+ }\r
+\r
+ return;\r
+\r
+ case LDM_REG_IMM8:\r
+ // <rt>, [<rn>, {, #<imm8>}]{!}\r
+ WriteBack = (OpCode32 & BIT8) == BIT8;\r
+ UAdd = (OpCode32 & BIT9) == BIT9;\r
+ Pre = (OpCode32 & BIT10) == BIT10;\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);\r
+ if (Pre) {\r
+ if ((OpCode32 & 0xff) == 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack ? "!" : "");\r
+ } else {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd ? "" : "-", OpCode32 & 0xff, WriteBack ? "!" : "");\r
+ }\r
+ } else {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd ? "" : "-", OpCode32 & 0xff);\r
}\r
- } else {\r
- if ((OpCode32 & 0xff) != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd?"":"-", (OpCode32 & 0xff) << 2);\r
+\r
+ return;\r
+\r
+ case LDRD_REG_IMM8_SIGNED:\r
+ // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
+ Pre = (OpCode32 & BIT24) == BIT24; // index = P\r
+ UAdd = (OpCode32 & BIT23) == BIT23;\r
+ WriteBack = (OpCode32 & BIT21) == BIT21;\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);\r
+ if (Pre) {\r
+ if ((OpCode32 & 0xff) == 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]");\r
+ } else {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd ? "" : "-", (OpCode32 & 0xff) << 2, WriteBack ? "!" : "");\r
+ }\r
+ } else {\r
+ if ((OpCode32 & 0xff) != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd ? "" : "-", (OpCode32 & 0xff) << 2);\r
+ }\r
}\r
- }\r
- return;\r
-\r
- case LDRD_REG_IMM8:\r
- // LDRD <rt>, <rt2>, <label>\r
- Target = (OpCode32 & 0xff) << 2;\r
- if ((OpCode32 & BIT23) == 0) {\r
- // U == 0 means subtrack, U == 1 means add\r
- Target = -Target;\r
- }\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);\r
- return;\r
-\r
- case LDREXB:\r
- // LDREXB <Rt>, [Rn]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a]", gReg[Rt], gReg[Rn]);\r
- return;\r
-\r
- case LDREXD:\r
- // LDREXD <Rt>, <Rt2>, [<Rn>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, [%a]", gReg[Rt], gReg[Rt2], gReg[Rn]);\r
- return;\r
-\r
- case SRS_FORMAT:\r
- // SP{!}, #<mode>\r
- WriteBack = (OpCode32 & BIT21) == BIT21;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack?"!":"", OpCode32 & 0x1f);\r
- return;\r
-\r
- case RFE_FORMAT:\r
- // <Rn>{!}\r
- WriteBack = (OpCode32 & BIT21) == BIT21;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack?"!":"");\r
- return;\r
-\r
- case ADD_IMM12:\r
- // ADD{S} <Rd>, <Rn>, #<const> i:imm3:imm8\r
- if ((OpCode32 & BIT20) == BIT20) {\r
- Buf[Offset - 3] = 'S'; // assume %-6a\r
- }\r
- Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target);\r
- return;\r
-\r
- case ADD_IMM12_1REG:\r
- // MOV{S} <Rd>, #<const> i:imm3:imm8\r
- if ((OpCode32 & BIT20) == BIT20) {\r
- Buf[Offset - 3] = 'S'; // assume %-6a\r
- }\r
- Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);\r
- return;\r
-\r
- case THUMB2_IMM16:\r
- // MOVW <Rd>, #<const> i:imm3:imm8\r
- Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
- Target |= ((OpCode32 >> 4) & 0xf0000);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);\r
- return;\r
-\r
- case ADD_IMM5:\r
- // ADC{S} <Rd>, <Rn>, <Rm> {,LSL #<const>} imm3:imm2\r
- if ((OpCode32 & BIT20) == BIT20) {\r
- Buf[Offset - 3] = 'S'; // assume %-6a\r
- }\r
- Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);\r
- if (Target != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);\r
- }\r
- return;\r
-\r
- case ADD_IMM5_2REG:\r
- // CMP <Rn>, <Rm> {,LSL #<const>} imm3:imm2\r
- Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]);\r
- if (Target != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);\r
- }\r
-\r
-\r
- case ASR_IMM5:\r
- // ARS <Rd>, <Rm> #<const>} imm3:imm2\r
- if ((OpCode32 & BIT20) == BIT20) {\r
- Buf[Offset - 3] = 'S'; // assume %-6a\r
- }\r
- Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target);\r
- return;\r
-\r
- case ASR_3REG:\r
- // ARS <Rd>, <Rn>, <Rm>\r
- if ((OpCode32 & BIT20) == BIT20) {\r
- Buf[Offset - 3] = 'S'; // assume %-6a\r
- }\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]);\r
- return;\r
-\r
- case ADR_THUMB2:\r
- // ADDR <Rd>, <label>\r
- Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
- if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {\r
- Target = PcAlign4 (Pc) - Target;\r
- } else {\r
- Target = PcAlign4 (Pc) + Target;\r
- }\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);\r
- return;\r
-\r
- case CMN_THUMB2:\r
- // CMN <Rn>, #<const>}\r
- Target = (OpCode32 & 0xff) | ((OpCode >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target);\r
- return;\r
-\r
- case BFC_THUMB2:\r
- // BFI <Rd>, <Rn>, #<lsb>, #<width>\r
- MsBit = OpCode32 & 0x1f;\r
- LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);\r
- if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){\r
- // BFC <Rd>, #<lsb>, #<width>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);\r
- } else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);\r
- } else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);\r
- }\r
- return;\r
-\r
- case CPD_THUMB2:\r
- // <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>\r
- Coproc = (OpCode32 >> 8) & 0xf;\r
- Opc1 = (OpCode32 >> 20) & 0xf;\r
- Opc2 = (OpCode32 >> 5) & 0x7;\r
- CRd = (OpCode32 >> 12) & 0xf;\r
- CRn = (OpCode32 >> 16) & 0xf;\r
- CRm = OpCode32 & 0xf;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);\r
- if (Opc2 != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);\r
- }\r
- return;\r
-\r
- case MRC_THUMB2:\r
- // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>\r
- Coproc = (OpCode32 >> 8) & 0xf;\r
- Opc1 = (OpCode32 >> 20) & 0xf;\r
- Opc2 = (OpCode32 >> 5) & 0x7;\r
- CRn = (OpCode32 >> 16) & 0xf;\r
- CRm = OpCode32 & 0xf;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);\r
- if (Opc2 != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);\r
- }\r
- return;\r
-\r
- case MRRC_THUMB2:\r
- // MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>\r
- Coproc = (OpCode32 >> 8) & 0xf;\r
- Opc1 = (OpCode32 >> 20) & 0xf;\r
- CRn = (OpCode32 >> 16) & 0xf;\r
- CRm = OpCode32 & 0xf;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);\r
- return;\r
-\r
- case THUMB2_2REGS:\r
- // <Rd>, <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd], gReg[Rm]);\r
- return;\r
-\r
- case THUMB2_4REGS:\r
- // <Rd>, <Rn>, <Rm>, <Ra>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm], gReg[Rt]);\r
- return;\r
-\r
- case THUMB2_MRS:\r
- // MRS <Rd>, CPSR\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, CPSR", gReg[Rd]);\r
- return;\r
-\r
- case THUMB2_MSR:\r
- // MRS CPSR_<fields>, <Rd>\r
- Target = (OpCode32 >> 10) & 3;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " CPSR_%a%a, %a", (Target & 2) == 0 ? "":"f", (Target & 1) == 0 ? "":"s", gReg[Rd]);\r
- return;\r
-\r
- case THUMB2_NO_ARGS:\r
- default:\r
- break;\r
+\r
+ return;\r
+\r
+ case LDRD_REG_IMM8:\r
+ // LDRD <rt>, <rt2>, <label>\r
+ Target = (OpCode32 & 0xff) << 2;\r
+ if ((OpCode32 & BIT23) == 0) {\r
+ // U == 0 means subtrack, U == 1 means add\r
+ Target = -Target;\r
+ }\r
+\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);\r
+ return;\r
+\r
+ case LDREXB:\r
+ // LDREXB <Rt>, [Rn]\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a]", gReg[Rt], gReg[Rn]);\r
+ return;\r
+\r
+ case LDREXD:\r
+ // LDREXD <Rt>, <Rt2>, [<Rn>]\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, [%a]", gReg[Rt], gReg[Rt2], gReg[Rn]);\r
+ return;\r
+\r
+ case SRS_FORMAT:\r
+ // SP{!}, #<mode>\r
+ WriteBack = (OpCode32 & BIT21) == BIT21;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack ? "!" : "", OpCode32 & 0x1f);\r
+ return;\r
+\r
+ case RFE_FORMAT:\r
+ // <Rn>{!}\r
+ WriteBack = (OpCode32 & BIT21) == BIT21;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack ? "!" : "");\r
+ return;\r
+\r
+ case ADD_IMM12:\r
+ // ADD{S} <Rd>, <Rn>, #<const> i:imm3:imm8\r
+ if ((OpCode32 & BIT20) == BIT20) {\r
+ Buf[Offset - 3] = 'S'; // assume %-6a\r
+ }\r
+\r
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target);\r
+ return;\r
+\r
+ case ADD_IMM12_1REG:\r
+ // MOV{S} <Rd>, #<const> i:imm3:imm8\r
+ if ((OpCode32 & BIT20) == BIT20) {\r
+ Buf[Offset - 3] = 'S'; // assume %-6a\r
+ }\r
+\r
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);\r
+ return;\r
+\r
+ case THUMB2_IMM16:\r
+ // MOVW <Rd>, #<const> i:imm3:imm8\r
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
+ Target |= ((OpCode32 >> 4) & 0xf0000);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);\r
+ return;\r
+\r
+ case ADD_IMM5:\r
+ // ADC{S} <Rd>, <Rn>, <Rm> {,LSL #<const>} imm3:imm2\r
+ if ((OpCode32 & BIT20) == BIT20) {\r
+ Buf[Offset - 3] = 'S'; // assume %-6a\r
+ }\r
+\r
+ Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);\r
+ if (Target != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);\r
+ }\r
+\r
+ return;\r
+\r
+ case ADD_IMM5_2REG:\r
+ // CMP <Rn>, <Rm> {,LSL #<const>} imm3:imm2\r
+ Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]);\r
+ if (Target != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);\r
+ }\r
+\r
+ case ASR_IMM5:\r
+ // ARS <Rd>, <Rm> #<const>} imm3:imm2\r
+ if ((OpCode32 & BIT20) == BIT20) {\r
+ Buf[Offset - 3] = 'S'; // assume %-6a\r
+ }\r
+\r
+ Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target);\r
+ return;\r
+\r
+ case ASR_3REG:\r
+ // ARS <Rd>, <Rn>, <Rm>\r
+ if ((OpCode32 & BIT20) == BIT20) {\r
+ Buf[Offset - 3] = 'S'; // assume %-6a\r
+ }\r
+\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]);\r
+ return;\r
+\r
+ case ADR_THUMB2:\r
+ // ADDR <Rd>, <label>\r
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
+ if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {\r
+ Target = PcAlign4 (Pc) - Target;\r
+ } else {\r
+ Target = PcAlign4 (Pc) + Target;\r
+ }\r
+\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);\r
+ return;\r
+\r
+ case CMN_THUMB2:\r
+ // CMN <Rn>, #<const>}\r
+ Target = (OpCode32 & 0xff) | ((OpCode >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target);\r
+ return;\r
+\r
+ case BFC_THUMB2:\r
+ // BFI <Rd>, <Rn>, #<lsb>, #<width>\r
+ MsBit = OpCode32 & 0x1f;\r
+ LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);\r
+ if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)) {\r
+ // BFC <Rd>, #<lsb>, #<width>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);\r
+ } else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);\r
+ } else {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);\r
+ }\r
+\r
+ return;\r
+\r
+ case CPD_THUMB2:\r
+ // <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>\r
+ Coproc = (OpCode32 >> 8) & 0xf;\r
+ Opc1 = (OpCode32 >> 20) & 0xf;\r
+ Opc2 = (OpCode32 >> 5) & 0x7;\r
+ CRd = (OpCode32 >> 12) & 0xf;\r
+ CRn = (OpCode32 >> 16) & 0xf;\r
+ CRm = OpCode32 & 0xf;\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);\r
+ if (Opc2 != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);\r
+ }\r
+\r
+ return;\r
+\r
+ case MRC_THUMB2:\r
+ // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>\r
+ Coproc = (OpCode32 >> 8) & 0xf;\r
+ Opc1 = (OpCode32 >> 20) & 0xf;\r
+ Opc2 = (OpCode32 >> 5) & 0x7;\r
+ CRn = (OpCode32 >> 16) & 0xf;\r
+ CRm = OpCode32 & 0xf;\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);\r
+ if (Opc2 != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);\r
+ }\r
+\r
+ return;\r
+\r
+ case MRRC_THUMB2:\r
+ // MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>\r
+ Coproc = (OpCode32 >> 8) & 0xf;\r
+ Opc1 = (OpCode32 >> 20) & 0xf;\r
+ CRn = (OpCode32 >> 16) & 0xf;\r
+ CRm = OpCode32 & 0xf;\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);\r
+ return;\r
+\r
+ case THUMB2_2REGS:\r
+ // <Rd>, <Rm>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd], gReg[Rm]);\r
+ return;\r
+\r
+ case THUMB2_4REGS:\r
+ // <Rd>, <Rn>, <Rm>, <Ra>\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm], gReg[Rt]);\r
+ return;\r
+\r
+ case THUMB2_MRS:\r
+ // MRS <Rd>, CPSR\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, CPSR", gReg[Rd]);\r
+ return;\r
+\r
+ case THUMB2_MSR:\r
+ // MRS CPSR_<fields>, <Rd>\r
+ Target = (OpCode32 >> 10) & 3;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " CPSR_%a%a, %a", (Target & 2) == 0 ? "" : "f", (Target & 1) == 0 ? "" : "s", gReg[Rd]);\r
+ return;\r
+\r
+ case THUMB2_NO_ARGS:\r
+ default:\r
+ break;\r
}\r
}\r
}\r
AsciiSPrint (Buf, Size, "0x%08x", OpCode32);\r
}\r
\r
-\r
-\r
VOID\r
DisassembleArmInstruction (\r
- IN UINT32 **OpCodePtr,\r
- OUT CHAR8 *Buf,\r
- OUT UINTN Size,\r
- IN BOOLEAN Extended\r
+ IN UINT32 **OpCodePtr,\r
+ OUT CHAR8 *Buf,\r
+ OUT UINTN Size,\r
+ IN BOOLEAN Extended\r
);\r
\r
-\r
/**\r
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to\r
point to next instruction.\r
**/\r
VOID\r
DisassembleInstruction (\r
- IN UINT8 **OpCodePtr,\r
- IN BOOLEAN Thumb,\r
- IN BOOLEAN Extended,\r
- IN OUT UINT32 *ItBlock,\r
- OUT CHAR8 *Buf,\r
- OUT UINTN Size\r
+ IN UINT8 **OpCodePtr,\r
+ IN BOOLEAN Thumb,\r
+ IN BOOLEAN Extended,\r
+ IN OUT UINT32 *ItBlock,\r
+ OUT CHAR8 *Buf,\r
+ OUT UINTN Size\r
)\r
{\r
if (Thumb) {\r
DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size, Extended);\r
}\r
}\r
-\r
#include <Library/MemoryAllocationLib.h>\r
#include <Protocol/DebugSupport.h> // for MAX_AARCH64_EXCEPTION\r
\r
-UINTN gMaxExceptionNumber = MAX_AARCH64_EXCEPTION;\r
-EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };\r
+UINTN gMaxExceptionNumber = MAX_AARCH64_EXCEPTION;\r
+EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };\r
EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };\r
-PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;\r
-UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64\r
+PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;\r
+UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64\r
\r
#define EL0_STACK_SIZE EFI_PAGES_TO_SIZE(2)\r
-STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];\r
+STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];\r
\r
VOID\r
RegisterEl0Stack (\r
- IN VOID *Stack\r
+ IN VOID *Stack\r
);\r
\r
RETURN_STATUS\r
ArchVectorConfig (\r
- IN UINTN VectorBaseAddress\r
+ IN UINTN VectorBaseAddress\r
)\r
{\r
- UINTN HcrReg;\r
+ UINTN HcrReg;\r
\r
// Round down sp by 16 bytes alignment\r
RegisterEl0Stack (\r
(VOID *)(((UINTN)mNewStackBase + EL0_STACK_SIZE) & ~0xFUL)\r
);\r
\r
- if (ArmReadCurrentEL() == AARCH64_EL2) {\r
- HcrReg = ArmReadHcr();\r
+ if (ArmReadCurrentEL () == AARCH64_EL2) {\r
+ HcrReg = ArmReadHcr ();\r
\r
// Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2\r
HcrReg |= ARM_HCR_TGE;\r
\r
- ArmWriteHcr(HcrReg);\r
+ ArmWriteHcr (HcrReg);\r
}\r
\r
return RETURN_SUCCESS;\r
\r
#include <Protocol/DebugSupport.h> // for MAX_ARM_EXCEPTION\r
\r
-UINTN gMaxExceptionNumber = MAX_ARM_EXCEPTION;\r
-EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };\r
+UINTN gMaxExceptionNumber = MAX_ARM_EXCEPTION;\r
+EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };\r
EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };\r
-PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;\r
+PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;\r
\r
// Exception handler contains branch to vector location (jmp $) so no handler\r
// NOTE: This code assumes vectors are ARM and not Thumb code\r
-UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;\r
+UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;\r
\r
RETURN_STATUS\r
ArchVectorConfig (\r
- IN UINTN VectorBaseAddress\r
+ IN UINTN VectorBaseAddress\r
)\r
{\r
// if the vector address corresponds to high vectors\r
if (VectorBaseAddress == 0xFFFF0000) {\r
// set SCTLR.V to enable high vectors\r
- ArmSetHighVectors();\r
- }\r
- else {\r
+ ArmSetHighVectors ();\r
+ } else {\r
// Set SCTLR.V to 0 to enable VBAR to be used\r
- ArmSetLowVectors();\r
+ ArmSetLowVectors ();\r
}\r
\r
return RETURN_SUCCESS;\r
\r
STATIC\r
RETURN_STATUS\r
-CopyExceptionHandlers(\r
- IN PHYSICAL_ADDRESS BaseAddress\r
+CopyExceptionHandlers (\r
+ IN PHYSICAL_ADDRESS BaseAddress\r
);\r
\r
EFI_STATUS\r
EFIAPI\r
-RegisterExceptionHandler(\r
- IN EFI_EXCEPTION_TYPE ExceptionType,\r
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
+RegisterExceptionHandler (\r
+ IN EFI_EXCEPTION_TYPE ExceptionType,\r
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
);\r
\r
VOID\r
-ExceptionHandlersStart(\r
+ExceptionHandlersStart (\r
VOID\r
);\r
\r
VOID\r
-ExceptionHandlersEnd(\r
+ExceptionHandlersEnd (\r
VOID\r
);\r
\r
-RETURN_STATUS ArchVectorConfig(\r
- IN UINTN VectorBaseAddress\r
+RETURN_STATUS\r
+ArchVectorConfig (\r
+ IN UINTN VectorBaseAddress\r
);\r
\r
// these globals are provided by the architecture specific source (Arm or AArch64)\r
-extern UINTN gMaxExceptionNumber;\r
-extern EFI_EXCEPTION_CALLBACK gExceptionHandlers[];\r
-extern EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[];\r
-extern PHYSICAL_ADDRESS gExceptionVectorAlignmentMask;\r
-extern UINTN gDebuggerNoHandlerValue;\r
+extern UINTN gMaxExceptionNumber;\r
+extern EFI_EXCEPTION_CALLBACK gExceptionHandlers[];\r
+extern EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[];\r
+extern PHYSICAL_ADDRESS gExceptionVectorAlignmentMask;\r
+extern UINTN gDebuggerNoHandlerValue;\r
\r
// A compiler flag adjusts the compilation of this library to a variant where\r
// the vectors are relocated (copied) to another location versus using the\r
// address this at library build time. Since this affects the build of the\r
// library we cannot represent this in a PCD since PCDs are evaluated on\r
// a per-module basis.\r
-#if defined(ARM_RELOCATE_VECTORS)\r
-STATIC CONST BOOLEAN gArmRelocateVectorTable = TRUE;\r
+#if defined (ARM_RELOCATE_VECTORS)\r
+STATIC CONST BOOLEAN gArmRelocateVectorTable = TRUE;\r
#else\r
-STATIC CONST BOOLEAN gArmRelocateVectorTable = FALSE;\r
+STATIC CONST BOOLEAN gArmRelocateVectorTable = FALSE;\r
#endif\r
\r
-\r
/**\r
Initializes all CPU exceptions entries and provides the default exception handlers.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
-InitializeCpuExceptionHandlers(\r
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL\r
+InitializeCpuExceptionHandlers (\r
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL\r
)\r
{\r
- RETURN_STATUS Status;\r
- UINTN VectorBase;\r
+ RETURN_STATUS Status;\r
+ UINTN VectorBase;\r
\r
Status = EFI_SUCCESS;\r
\r
// if we are requested to copy exception handlers to another location\r
if (gArmRelocateVectorTable) {\r
-\r
- VectorBase = PcdGet64(PcdCpuVectorBaseAddress);\r
- Status = CopyExceptionHandlers(VectorBase);\r
-\r
- }\r
- else { // use VBAR to point to where our exception handlers are\r
+ VectorBase = PcdGet64 (PcdCpuVectorBaseAddress);\r
+ Status = CopyExceptionHandlers (VectorBase);\r
+ } else {\r
+ // use VBAR to point to where our exception handlers are\r
\r
// The vector table must be aligned for the architecture. If this\r
// assertion fails ensure the appropriate FFS alignment is in effect,\r
// for AArch64 Align=4K is required. Align=Auto can be used but this\r
// is known to cause an issue with populating the reset vector area\r
// for encapsulated FVs.\r
- ASSERT(((UINTN)ExceptionHandlersStart & gExceptionVectorAlignmentMask) == 0);\r
+ ASSERT (((UINTN)ExceptionHandlersStart & gExceptionVectorAlignmentMask) == 0);\r
\r
// We do not copy the Exception Table at PcdGet64(PcdCpuVectorBaseAddress). We just set Vector\r
// Base Address to point into CpuDxe code.\r
Status = RETURN_SUCCESS;\r
}\r
\r
- if (!RETURN_ERROR(Status)) {\r
+ if (!RETURN_ERROR (Status)) {\r
// call the architecture-specific routine to prepare for the new vector\r
// configuration to take effect\r
- ArchVectorConfig(VectorBase);\r
+ ArchVectorConfig (VectorBase);\r
\r
- ArmWriteVBar(VectorBase);\r
+ ArmWriteVBar (VectorBase);\r
}\r
\r
return RETURN_SUCCESS;\r
**/\r
STATIC\r
RETURN_STATUS\r
-CopyExceptionHandlers(\r
- IN PHYSICAL_ADDRESS BaseAddress\r
+CopyExceptionHandlers (\r
+ IN PHYSICAL_ADDRESS BaseAddress\r
)\r
{\r
- RETURN_STATUS Status;\r
- UINTN Length;\r
- UINTN Index;\r
- UINT32 *VectorBase;\r
+ RETURN_STATUS Status;\r
+ UINTN Length;\r
+ UINTN Index;\r
+ UINT32 *VectorBase;\r
\r
// ensure that the destination value specifies an address meeting the vector alignment requirements\r
ASSERT ((BaseAddress & gExceptionVectorAlignmentMask) == 0);\r
\r
VectorBase = (UINT32 *)(UINTN)BaseAddress;\r
\r
- if (FeaturePcdGet(PcdDebuggerExceptionSupport) == TRUE) {\r
+ if (FeaturePcdGet (PcdDebuggerExceptionSupport) == TRUE) {\r
// Save existing vector table, in case debugger is already hooked in\r
- CopyMem((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (EFI_EXCEPTION_CALLBACK)* (gMaxExceptionNumber+1));\r
+ CopyMem ((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (EFI_EXCEPTION_CALLBACK)* (gMaxExceptionNumber+1));\r
}\r
\r
// Copy our assembly code into the page that contains the exception vectors.\r
- CopyMem((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);\r
+ CopyMem ((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);\r
\r
//\r
// Initialize the C entry points for interrupts\r
//\r
for (Index = 0; Index <= gMaxExceptionNumber; Index++) {\r
- if (!FeaturePcdGet(PcdDebuggerExceptionSupport) ||\r
- (gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)gDebuggerNoHandlerValue)) {\r
-\r
- Status = RegisterExceptionHandler(Index, NULL);\r
- ASSERT_EFI_ERROR(Status);\r
- }\r
- else {\r
+ if (!FeaturePcdGet (PcdDebuggerExceptionSupport) ||\r
+ (gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)gDebuggerNoHandlerValue))\r
+ {\r
+ Status = RegisterExceptionHandler (Index, NULL);\r
+ ASSERT_EFI_ERROR (Status);\r
+ } else {\r
// If the debugger has already hooked put its vector back\r
VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index];\r
}\r
}\r
\r
// Flush Caches since we updated executable stuff\r
- InvalidateInstructionCacheRange((VOID *)(UINTN)BaseAddress, Length);\r
+ InvalidateInstructionCacheRange ((VOID *)(UINTN)BaseAddress, Length);\r
\r
return RETURN_SUCCESS;\r
}\r
\r
-\r
/**\r
Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
-InitializeCpuInterruptHandlers(\r
-IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL\r
-)\r
+InitializeCpuInterruptHandlers (\r
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL\r
+ )\r
{\r
// not needed, this is what the CPU driver is for\r
return EFI_UNSUPPORTED;\r
or this function is not supported.\r
**/\r
RETURN_STATUS\r
-RegisterCpuInterruptHandler(\r
- IN EFI_EXCEPTION_TYPE ExceptionType,\r
- IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler\r
+RegisterCpuInterruptHandler (\r
+ IN EFI_EXCEPTION_TYPE ExceptionType,\r
+ IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler\r
)\r
{\r
if (ExceptionType > gMaxExceptionNumber) {\r
**/\r
EFI_STATUS\r
EFIAPI\r
-RegisterExceptionHandler(\r
- IN EFI_EXCEPTION_TYPE ExceptionType,\r
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
+RegisterExceptionHandler (\r
+ IN EFI_EXCEPTION_TYPE ExceptionType,\r
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
)\r
{\r
- return RegisterCpuInterruptHandler(ExceptionType, InterruptHandler);\r
+ return RegisterCpuInterruptHandler (ExceptionType, InterruptHandler);\r
}\r
\r
VOID\r
EFIAPI\r
-CommonCExceptionHandler(\r
- IN EFI_EXCEPTION_TYPE ExceptionType,\r
- IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
+CommonCExceptionHandler (\r
+ IN EFI_EXCEPTION_TYPE ExceptionType,\r
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
)\r
{\r
if (ExceptionType <= gMaxExceptionNumber) {\r
gExceptionHandlers[ExceptionType](ExceptionType, SystemContext);\r
return;\r
}\r
- }\r
- else {\r
- DEBUG((DEBUG_ERROR, "Unknown exception type %d\n", ExceptionType));\r
- ASSERT(FALSE);\r
+ } else {\r
+ DEBUG ((DEBUG_ERROR, "Unknown exception type %d\n", ExceptionType));\r
+ ASSERT (FALSE);\r
}\r
\r
- DefaultExceptionHandler(ExceptionType, SystemContext);\r
+ DefaultExceptionHandler (ExceptionType, SystemContext);\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
InitializeCpuExceptionHandlersEx (\r
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,\r
- IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL\r
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,\r
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL\r
)\r
{\r
return InitializeCpuExceptionHandlers (VectorInfo);\r
VOID\r
)\r
{\r
- UINTN TimerCtrlReg;\r
+ UINTN TimerCtrlReg;\r
\r
- TimerCtrlReg = ArmReadCntpCtl ();\r
+ TimerCtrlReg = ArmReadCntpCtl ();\r
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;\r
ArmWriteCntpCtl (TimerCtrlReg);\r
}\r
VOID\r
)\r
{\r
- UINTN TimerCtrlReg;\r
+ UINTN TimerCtrlReg;\r
\r
- TimerCtrlReg = ArmReadCntpCtl ();\r
+ TimerCtrlReg = ArmReadCntpCtl ();\r
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;\r
ArmWriteCntpCtl (TimerCtrlReg);\r
}\r
return ArmReadCntpTval ();\r
}\r
\r
-\r
VOID\r
EFIAPI\r
ArmGenericTimerSetTimerVal (\r
- IN UINTN Value\r
+ IN UINTN Value\r
)\r
{\r
ArmWriteCntpTval (Value);\r
VOID\r
EFIAPI\r
ArmGenericTimerSetTimerCtrlReg (\r
- UINTN Value\r
+ UINTN Value\r
)\r
{\r
ArmWriteCntpCtl (Value);\r
VOID\r
EFIAPI\r
ArmGenericTimerSetCompareVal (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
ArmWriteCntpCval (Value);\r
VOID\r
)\r
{\r
- UINTN TimerCtrlReg;\r
+ UINTN TimerCtrlReg;\r
\r
- TimerCtrlReg = ArmReadCntvCtl ();\r
+ TimerCtrlReg = ArmReadCntvCtl ();\r
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;\r
ArmWriteCntvCtl (TimerCtrlReg);\r
}\r
VOID\r
)\r
{\r
- UINTN TimerCtrlReg;\r
+ UINTN TimerCtrlReg;\r
\r
- TimerCtrlReg = ArmReadCntvCtl ();\r
+ TimerCtrlReg = ArmReadCntvCtl ();\r
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;\r
ArmWriteCntvCtl (TimerCtrlReg);\r
}\r
return ArmReadCntvTval ();\r
}\r
\r
-\r
VOID\r
EFIAPI\r
ArmGenericTimerSetTimerVal (\r
- IN UINTN Value\r
+ IN UINTN Value\r
)\r
{\r
ArmWriteCntvTval (Value);\r
VOID\r
EFIAPI\r
ArmGenericTimerSetTimerCtrlReg (\r
- UINTN Value\r
+ UINTN Value\r
)\r
{\r
ArmWriteCntvCtl (Value);\r
VOID\r
EFIAPI\r
ArmGenericTimerSetCompareVal (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
ArmWriteCntvCval (Value);\r
#include <Library/ArmLib.h>\r
#include <Library/ArmGicLib.h>\r
\r
-STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;\r
+STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;\r
\r
RETURN_STATUS\r
EFIAPI\r
VOID\r
)\r
{\r
- UINT32 IccSre;\r
+ UINT32 IccSre;\r
\r
// Ideally we would like to use the GICC IIDR Architecture version here, but\r
// this does not seem to be very reliable as the implementation could easily\r
ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);\r
IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
}\r
+\r
if (IccSre & ICC_SRE_EL2_SRE) {\r
mGicArchRevision = ARM_GIC_ARCH_REVISION_3;\r
goto Done;\r
VOID\r
)\r
{\r
- UINT32 IccSre;\r
+ UINT32 IccSre;\r
\r
// Ideally we would like to use the GICC IIDR Architecture version here, but\r
// this does not seem to be very reliable as the implementation could easily\r
ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);\r
IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
}\r
+\r
if (IccSre & ICC_SRE_EL2_SRE) {\r
return ARM_GIC_ARCH_REVISION_3;\r
}\r
IN AARCH64_CACHE_OPERATION DataCacheOperation\r
)\r
{\r
- UINTN SavedInterruptState;\r
+ UINTN SavedInterruptState;\r
\r
SavedInterruptState = ArmGetInterruptState ();\r
- ArmDisableInterrupts();\r
+ ArmDisableInterrupts ();\r
\r
AArch64AllDataCachesOperation (DataCacheOperation);\r
\r
VOID\r
)\r
{\r
- UINTN Mmfr2;\r
+ UINTN Mmfr2;\r
\r
Mmfr2 = ArmReadIdAA64Mmfr2 ();\r
return (((Mmfr2 >> 20) & 0xF) == 1) ? TRUE : FALSE;\r
#ifndef AARCH64_LIB_H_\r
#define AARCH64_LIB_H_\r
\r
-typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);\r
+typedef VOID (*AARCH64_CACHE_OPERATION)(\r
+ UINTN\r
+ );\r
\r
VOID\r
AArch64AllDataCachesOperation (\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryBySetWay (\r
- IN UINTN SetWayFormat\r
+ IN UINTN SetWayFormat\r
);\r
\r
UINTN\r
);\r
\r
#endif // AARCH64_LIB_H_\r
-\r
IN ARM_V7_CACHE_OPERATION DataCacheOperation\r
)\r
{\r
- UINTN SavedInterruptState;\r
+ UINTN SavedInterruptState;\r
\r
SavedInterruptState = ArmGetInterruptState ();\r
ArmDisableInterrupts ();\r
VOID\r
)\r
{\r
- UINTN Mmfr4;\r
+ UINTN Mmfr4;\r
\r
Mmfr4 = ArmReadIdMmfr4 ();\r
return (((Mmfr4 >> 24) & 0xF) == 1) ? TRUE : FALSE;\r
#ifndef ARM_V7_LIB_H_\r
#define ARM_V7_LIB_H_\r
\r
-#define ID_MMFR0_SHARELVL_SHIFT 12\r
-#define ID_MMFR0_SHARELVL_MASK 0xf\r
-#define ID_MMFR0_SHARELVL_ONE 0\r
-#define ID_MMFR0_SHARELVL_TWO 1\r
-\r
-#define ID_MMFR0_INNERSHR_SHIFT 28\r
-#define ID_MMFR0_INNERSHR_MASK 0xf\r
-#define ID_MMFR0_OUTERSHR_SHIFT 8\r
-#define ID_MMFR0_OUTERSHR_MASK 0xf\r
-\r
-#define ID_MMFR0_SHR_IMP_UNCACHED 0\r
-#define ID_MMFR0_SHR_IMP_HW_COHERENT 1\r
-#define ID_MMFR0_SHR_IGNORED 0xf\r
-\r
-typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32);\r
+#define ID_MMFR0_SHARELVL_SHIFT 12\r
+#define ID_MMFR0_SHARELVL_MASK 0xf\r
+#define ID_MMFR0_SHARELVL_ONE 0\r
+#define ID_MMFR0_SHARELVL_TWO 1\r
+\r
+#define ID_MMFR0_INNERSHR_SHIFT 28\r
+#define ID_MMFR0_INNERSHR_MASK 0xf\r
+#define ID_MMFR0_OUTERSHR_SHIFT 8\r
+#define ID_MMFR0_OUTERSHR_MASK 0xf\r
+\r
+#define ID_MMFR0_SHR_IMP_UNCACHED 0\r
+#define ID_MMFR0_SHR_IMP_HW_COHERENT 1\r
+#define ID_MMFR0_SHR_IGNORED 0xf\r
+\r
+typedef VOID (*ARM_V7_CACHE_OPERATION)(\r
+ UINT32\r
+ );\r
\r
VOID\r
ArmV7AllDataCachesOperation (\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryBySetWay (\r
- IN UINTN SetWayFormat\r
+ IN UINTN SetWayFormat\r
);\r
\r
/** Reads the ID_MMFR4 register.\r
);\r
\r
#endif // ARM_V7_LIB_H_\r
-\r
VOID\r
EFIAPI\r
ArmSetAuxCrBit (\r
- IN UINT32 Bits\r
+ IN UINT32 Bits\r
)\r
{\r
- ArmWriteAuxCr(ArmReadAuxCr() | Bits);\r
+ ArmWriteAuxCr (ArmReadAuxCr () | Bits);\r
}\r
\r
VOID\r
EFIAPI\r
ArmUnsetAuxCrBit (\r
- IN UINT32 Bits\r
+ IN UINT32 Bits\r
)\r
{\r
- ArmWriteAuxCr(ArmReadAuxCr() & ~Bits);\r
+ ArmWriteAuxCr (ArmReadAuxCr () & ~Bits);\r
}\r
\r
//\r
VOID\r
EFIAPI\r
ArmSetCpuActlrBit (\r
- IN UINTN Bits\r
+ IN UINTN Bits\r
)\r
{\r
ArmWriteCpuActlr (ArmReadCpuActlr () | Bits);\r
VOID\r
EFIAPI\r
ArmUnsetCpuActlrBit (\r
- IN UINTN Bits\r
+ IN UINTN Bits\r
)\r
{\r
ArmWriteCpuActlr (ArmReadCpuActlr () & ~Bits);\r
VOID\r
)\r
{\r
- UINTN CWG;\r
+ UINTN CWG;\r
\r
CWG = (ArmCacheInfo () >> 24) & 0xf; // CTR_EL0.CWG\r
\r
#ifndef ARM_LIB_PRIVATE_H_\r
#define ARM_LIB_PRIVATE_H_\r
\r
-#define CACHE_SIZE_4_KB (3UL)\r
-#define CACHE_SIZE_8_KB (4UL)\r
-#define CACHE_SIZE_16_KB (5UL)\r
-#define CACHE_SIZE_32_KB (6UL)\r
-#define CACHE_SIZE_64_KB (7UL)\r
-#define CACHE_SIZE_128_KB (8UL)\r
+#define CACHE_SIZE_4_KB (3UL)\r
+#define CACHE_SIZE_8_KB (4UL)\r
+#define CACHE_SIZE_16_KB (5UL)\r
+#define CACHE_SIZE_32_KB (6UL)\r
+#define CACHE_SIZE_64_KB (7UL)\r
+#define CACHE_SIZE_128_KB (8UL)\r
\r
#define CACHE_ASSOCIATIVITY_DIRECT (0UL)\r
#define CACHE_ASSOCIATIVITY_4_WAY (2UL)\r
#define CACHE_ASSOCIATIVITY_8_WAY (3UL)\r
\r
-#define CACHE_PRESENT (0UL)\r
-#define CACHE_NOT_PRESENT (1UL)\r
+#define CACHE_PRESENT (0UL)\r
+#define CACHE_NOT_PRESENT (1UL)\r
\r
#define CACHE_LINE_LENGTH_32_BYTES (2UL)\r
\r
#define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)\r
#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)\r
\r
-#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)\r
-#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)\r
+#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)\r
+#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)\r
\r
-#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))\r
-#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))\r
-#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))\r
-#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))\r
\r
-#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
\r
-#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)\r
-#define CACHE_TYPE_WRITE_BACK (0x0EUL)\r
+#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)\r
+#define CACHE_TYPE_WRITE_BACK (0x0EUL)\r
\r
-#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)\r
-#define CACHE_ARCHITECTURE_UNIFIED (0UL)\r
-#define CACHE_ARCHITECTURE_SEPARATE (1UL)\r
+#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)\r
+#define CACHE_ARCHITECTURE_UNIFIED (0UL)\r
+#define CACHE_ARCHITECTURE_SEPARATE (1UL)\r
\r
VOID\r
CPSRMaskInsert (\r
)\r
{\r
switch (Attributes) {\r
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
- return TT_ATTR_INDX_MEMORY_WRITE_BACK;\r
-\r
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
- return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r
-\r
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
- return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;\r
-\r
- // Uncached and device mappings are treated as outer shareable by default,\r
- case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
- return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r
-\r
- default:\r
- ASSERT (0);\r
- case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
- if (ArmReadCurrentEL () == AARCH64_EL2)\r
- return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;\r
- else\r
- return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
+ return TT_ATTR_INDX_MEMORY_WRITE_BACK;\r
+\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
+ return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r
+\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
+ return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;\r
+\r
+ // Uncached and device mappings are treated as outer shareable by default,\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
+ return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r
+\r
+ default:\r
+ ASSERT (0);\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
+ if (ArmReadCurrentEL () == AARCH64_EL2) {\r
+ return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;\r
+ } else {\r
+ return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;\r
+ }\r
}\r
}\r
\r
STATIC\r
UINTN\r
GetRootTableEntryCount (\r
- IN UINTN T0SZ\r
+ IN UINTN T0SZ\r
)\r
{\r
return TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;\r
STATIC\r
UINTN\r
GetRootTableLevel (\r
- IN UINTN T0SZ\r
+ IN UINTN T0SZ\r
)\r
{\r
return (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;\r
STATIC\r
VOID\r
ReplaceTableEntry (\r
- IN UINT64 *Entry,\r
- IN UINT64 Value,\r
- IN UINT64 RegionStart,\r
- IN BOOLEAN IsLiveBlockMapping\r
+ IN UINT64 *Entry,\r
+ IN UINT64 Value,\r
+ IN UINT64 RegionStart,\r
+ IN BOOLEAN IsLiveBlockMapping\r
)\r
{\r
if (!ArmMmuEnabled () || !IsLiveBlockMapping) {\r
IN UINTN Level\r
)\r
{\r
- UINTN Index;\r
+ UINTN Index;\r
\r
ASSERT (Level <= 3);\r
\r
if (Level < 3) {\r
for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {\r
if ((TranslationTable[Index] & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {\r
- FreePageTablesRecursive ((VOID *)(UINTN)(TranslationTable[Index] &\r
- TT_ADDRESS_MASK_BLOCK_ENTRY),\r
- Level + 1);\r
+ FreePageTablesRecursive (\r
+ (VOID *)(UINTN)(TranslationTable[Index] &\r
+ TT_ADDRESS_MASK_BLOCK_ENTRY),\r
+ Level + 1\r
+ );\r
}\r
}\r
}\r
+\r
FreePages (TranslationTable, 1);\r
}\r
\r
if (Level == 3) {\r
return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3;\r
}\r
+\r
return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY;\r
}\r
\r
//\r
return FALSE;\r
}\r
+\r
return (Entry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY;\r
}\r
\r
STATIC\r
EFI_STATUS\r
UpdateRegionMappingRecursive (\r
- IN UINT64 RegionStart,\r
- IN UINT64 RegionEnd,\r
- IN UINT64 AttributeSetMask,\r
- IN UINT64 AttributeClearMask,\r
- IN UINT64 *PageTable,\r
- IN UINTN Level\r
+ IN UINT64 RegionStart,\r
+ IN UINT64 RegionEnd,\r
+ IN UINT64 AttributeSetMask,\r
+ IN UINT64 AttributeClearMask,\r
+ IN UINT64 *PageTable,\r
+ IN UINTN Level\r
)\r
{\r
- UINTN BlockShift;\r
- UINT64 BlockMask;\r
- UINT64 BlockEnd;\r
- UINT64 *Entry;\r
- UINT64 EntryValue;\r
- VOID *TranslationTable;\r
- EFI_STATUS Status;\r
+ UINTN BlockShift;\r
+ UINT64 BlockMask;\r
+ UINT64 BlockEnd;\r
+ UINT64 *Entry;\r
+ UINT64 EntryValue;\r
+ VOID *TranslationTable;\r
+ EFI_STATUS Status;\r
\r
ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0);\r
\r
BlockShift = (Level + 1) * BITS_PER_LEVEL + MIN_T0SZ;\r
- BlockMask = MAX_UINT64 >> BlockShift;\r
-\r
- DEBUG ((DEBUG_VERBOSE, "%a(%d): %llx - %llx set %lx clr %lx\n", __FUNCTION__,\r
- Level, RegionStart, RegionEnd, AttributeSetMask, AttributeClearMask));\r
-\r
- for (; RegionStart < RegionEnd; RegionStart = BlockEnd) {\r
+ BlockMask = MAX_UINT64 >> BlockShift;\r
+\r
+ DEBUG ((\r
+ DEBUG_VERBOSE,\r
+ "%a(%d): %llx - %llx set %lx clr %lx\n",\r
+ __FUNCTION__,\r
+ Level,\r
+ RegionStart,\r
+ RegionEnd,\r
+ AttributeSetMask,\r
+ AttributeClearMask\r
+ ));\r
+\r
+ for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) {\r
BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);\r
- Entry = &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_COUNT - 1)];\r
+ Entry = &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_COUNT - 1)];\r
\r
//\r
// If RegionStart or BlockEnd is not aligned to the block size at this\r
// we cannot replace it with a block entry without potentially losing\r
// attribute information, so keep the table entry in that case.\r
//\r
- if (Level == 0 || ((RegionStart | BlockEnd) & BlockMask) != 0 ||\r
- (IsTableEntry (*Entry, Level) && AttributeClearMask != 0)) {\r
+ if ((Level == 0) || (((RegionStart | BlockEnd) & BlockMask) != 0) ||\r
+ (IsTableEntry (*Entry, Level) && (AttributeClearMask != 0)))\r
+ {\r
ASSERT (Level < 3);\r
\r
if (!IsTableEntry (*Entry, Level)) {\r
// We are splitting an existing block entry, so we have to populate\r
// the new table with the attributes of the block entry it replaces.\r
//\r
- Status = UpdateRegionMappingRecursive (RegionStart & ~BlockMask,\r
- (RegionStart | BlockMask) + 1, *Entry & TT_ATTRIBUTES_MASK,\r
- 0, TranslationTable, Level + 1);\r
+ Status = UpdateRegionMappingRecursive (\r
+ RegionStart & ~BlockMask,\r
+ (RegionStart | BlockMask) + 1,\r
+ *Entry & TT_ATTRIBUTES_MASK,\r
+ 0,\r
+ TranslationTable,\r
+ Level + 1\r
+ );\r
if (EFI_ERROR (Status)) {\r
//\r
// The range we passed to UpdateRegionMappingRecursive () is block\r
//\r
// Recurse to the next level\r
//\r
- Status = UpdateRegionMappingRecursive (RegionStart, BlockEnd,\r
- AttributeSetMask, AttributeClearMask, TranslationTable,\r
- Level + 1);\r
+ Status = UpdateRegionMappingRecursive (\r
+ RegionStart,\r
+ BlockEnd,\r
+ AttributeSetMask,\r
+ AttributeClearMask,\r
+ TranslationTable,\r
+ Level + 1\r
+ );\r
if (EFI_ERROR (Status)) {\r
if (!IsTableEntry (*Entry, Level)) {\r
//\r
//\r
FreePageTablesRecursive (TranslationTable, Level + 1);\r
}\r
+\r
return Status;\r
}\r
\r
if (!IsTableEntry (*Entry, Level)) {\r
EntryValue = (UINTN)TranslationTable | TT_TYPE_TABLE_ENTRY;\r
- ReplaceTableEntry (Entry, EntryValue, RegionStart,\r
- IsBlockEntry (*Entry, Level));\r
+ ReplaceTableEntry (\r
+ Entry,\r
+ EntryValue,\r
+ RegionStart,\r
+ IsBlockEntry (*Entry, Level)\r
+ );\r
}\r
} else {\r
- EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;\r
+ EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;\r
EntryValue |= RegionStart;\r
EntryValue |= (Level == 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3\r
: TT_TYPE_BLOCK_ENTRY;\r
}\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
IN UINT64 AttributeClearMask\r
)\r
{\r
- UINTN T0SZ;\r
+ UINTN T0SZ;\r
\r
if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) {\r
return EFI_INVALID_PARAMETER;\r
\r
T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;\r
\r
- return UpdateRegionMappingRecursive (RegionStart, RegionStart + RegionLength,\r
- AttributeSetMask, AttributeClearMask, ArmGetTTBR0BaseAddress (),\r
- GetRootTableLevel (T0SZ));\r
+ return UpdateRegionMappingRecursive (\r
+ RegionStart,\r
+ RegionStart + RegionLength,\r
+ AttributeSetMask,\r
+ AttributeClearMask,\r
+ ArmGetTTBR0BaseAddress (),\r
+ GetRootTableLevel (T0SZ)\r
+ );\r
}\r
\r
STATIC\r
STATIC\r
UINT64\r
GcdAttributeToPageAttribute (\r
- IN UINT64 GcdAttributes\r
+ IN UINT64 GcdAttributes\r
)\r
{\r
- UINT64 PageAttributes;\r
+ UINT64 PageAttributes;\r
\r
switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {\r
- case EFI_MEMORY_UC:\r
- PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;\r
- break;\r
- case EFI_MEMORY_WC:\r
- PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r
- break;\r
- case EFI_MEMORY_WT:\r
- PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;\r
- break;\r
- case EFI_MEMORY_WB:\r
- PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r
- break;\r
- default:\r
- PageAttributes = TT_ATTR_INDX_MASK;\r
- break;\r
+ case EFI_MEMORY_UC:\r
+ PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;\r
+ break;\r
+ case EFI_MEMORY_WC:\r
+ PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r
+ break;\r
+ case EFI_MEMORY_WT:\r
+ PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;\r
+ break;\r
+ case EFI_MEMORY_WB:\r
+ PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r
+ break;\r
+ default:\r
+ PageAttributes = TT_ATTR_INDX_MASK;\r
+ break;\r
}\r
\r
- if ((GcdAttributes & EFI_MEMORY_XP) != 0 ||\r
- (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) {\r
+ if (((GcdAttributes & EFI_MEMORY_XP) != 0) ||\r
+ ((GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC))\r
+ {\r
if (ArmReadCurrentEL () == AARCH64_EL2) {\r
PageAttributes |= TT_XN_MASK;\r
} else {\r
\r
EFI_STATUS\r
ArmSetMemoryAttributes (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
)\r
{\r
- UINT64 PageAttributes;\r
- UINT64 PageAttributeMask;\r
+ UINT64 PageAttributes;\r
+ UINT64 PageAttributeMask;\r
\r
- PageAttributes = GcdAttributeToPageAttribute (Attributes);\r
+ PageAttributes = GcdAttributeToPageAttribute (Attributes);\r
PageAttributeMask = 0;\r
\r
if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) {\r
// No memory type was set in Attributes, so we are going to update the\r
// permissions only.\r
//\r
- PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;\r
+ PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;\r
PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK |\r
TT_PXN_MASK | TT_XN_MASK);\r
}\r
\r
- return UpdateRegionMapping (BaseAddress, Length, PageAttributes,\r
- PageAttributeMask);\r
+ return UpdateRegionMapping (\r
+ BaseAddress,\r
+ Length,\r
+ PageAttributes,\r
+ PageAttributeMask\r
+ );\r
}\r
\r
STATIC\r
EFI_STATUS\r
SetMemoryRegionAttribute (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes,\r
- IN UINT64 BlockEntryMask\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes,\r
+ IN UINT64 BlockEntryMask\r
)\r
{\r
return UpdateRegionMapping (BaseAddress, Length, Attributes, BlockEntryMask);\r
\r
EFI_STATUS\r
ArmSetMemoryRegionNoExec (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
- UINT64 Val;\r
+ UINT64 Val;\r
\r
if (ArmReadCurrentEL () == AARCH64_EL1) {\r
Val = TT_PXN_MASK | TT_UXN_MASK;\r
BaseAddress,\r
Length,\r
Val,\r
- ~TT_ADDRESS_MASK_BLOCK_ENTRY);\r
+ ~TT_ADDRESS_MASK_BLOCK_ENTRY\r
+ );\r
}\r
\r
EFI_STATUS\r
ArmClearMemoryRegionNoExec (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
- UINT64 Mask;\r
+ UINT64 Mask;\r
\r
// XN maps to UXN in the EL1&0 translation regime\r
Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK);\r
BaseAddress,\r
Length,\r
0,\r
- Mask);\r
+ Mask\r
+ );\r
}\r
\r
EFI_STATUS\r
ArmSetMemoryRegionReadOnly (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
return SetMemoryRegionAttribute (\r
BaseAddress,\r
Length,\r
TT_AP_RO_RO,\r
- ~TT_ADDRESS_MASK_BLOCK_ENTRY);\r
+ ~TT_ADDRESS_MASK_BLOCK_ENTRY\r
+ );\r
}\r
\r
EFI_STATUS\r
ArmClearMemoryRegionReadOnly (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
return SetMemoryRegionAttribute (\r
BaseAddress,\r
Length,\r
TT_AP_RW_RW,\r
- ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));\r
+ ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK)\r
+ );\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
ArmConfigureMmu (\r
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
- OUT VOID **TranslationTableBase OPTIONAL,\r
+ OUT VOID **TranslationTableBase OPTIONAL,\r
OUT UINTN *TranslationTableSize OPTIONAL\r
)\r
{\r
- VOID* TranslationTable;\r
- UINTN MaxAddressBits;\r
- UINT64 MaxAddress;\r
- UINTN T0SZ;\r
- UINTN RootTableEntryCount;\r
- UINT64 TCR;\r
- EFI_STATUS Status;\r
+ VOID *TranslationTable;\r
+ UINTN MaxAddressBits;\r
+ UINT64 MaxAddress;\r
+ UINTN T0SZ;\r
+ UINTN RootTableEntryCount;\r
+ UINT64 TCR;\r
+ EFI_STATUS Status;\r
\r
if (MemoryTable == NULL) {\r
ASSERT (MemoryTable != NULL);\r
// use of 4 KB pages.\r
//\r
MaxAddressBits = MIN (ArmGetPhysicalAddressBits (), MAX_VA_BITS);\r
- MaxAddress = LShiftU64 (1ULL, MaxAddressBits) - 1;\r
+ MaxAddress = LShiftU64 (1ULL, MaxAddressBits) - 1;\r
\r
- T0SZ = 64 - MaxAddressBits;\r
+ T0SZ = 64 - MaxAddressBits;\r
RootTableEntryCount = GetRootTableEntryCount (T0SZ);\r
\r
//\r
// Ideally we will be running at EL2, but should support EL1 as well.\r
// UEFI should not run at EL3.\r
if (ArmReadCurrentEL () == AARCH64_EL2) {\r
- //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2\r
+ // Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2\r
TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;\r
\r
// Set the Physical Address Size using MaxAddress\r
} else if (MaxAddress < SIZE_256TB) {\r
TCR |= TCR_PS_256TB;\r
} else {\r
- DEBUG ((DEBUG_ERROR,\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",\r
- MaxAddress));\r
+ MaxAddress\r
+ ));\r
ASSERT (0); // Bigger than 48-bit memory space are not supported\r
return EFI_UNSUPPORTED;\r
}\r
} else if (MaxAddress < SIZE_256TB) {\r
TCR |= TCR_IPS_256TB;\r
} else {\r
- DEBUG ((DEBUG_ERROR,\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",\r
- MaxAddress));\r
+ MaxAddress\r
+ ));\r
ASSERT (0); // Bigger than 48-bit memory space are not supported\r
return EFI_UNSUPPORTED;\r
}\r
if (TranslationTable == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
//\r
// We set TTBR0 just after allocating the table to retrieve its location from\r
// the subsequent functions without needing to pass this value across the\r
// Make sure we are not inadvertently hitting in the caches\r
// when populating the page tables.\r
//\r
- InvalidateDataCacheRange (TranslationTable,\r
- RootTableEntryCount * sizeof (UINT64));\r
+ InvalidateDataCacheRange (\r
+ TranslationTable,\r
+ RootTableEntryCount * sizeof (UINT64)\r
+ );\r
ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));\r
\r
while (MemoryTable->Length != 0) {\r
if (EFI_ERROR (Status)) {\r
goto FreeTranslationTable;\r
}\r
+\r
MemoryTable++;\r
}\r
\r
// EFI_MEMORY_WB ==> MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK\r
//\r
ArmSetMAIR (\r
- MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |\r
+ MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |\r
MAIR_ATTR (TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) |\r
MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) |\r
- MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)\r
+ MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)\r
);\r
\r
ArmDisableAlignmentCheck ();\r
VOID\r
)\r
{\r
- extern UINT32 ArmReplaceLiveTranslationEntrySize;\r
+ extern UINT32 ArmReplaceLiveTranslationEntrySize;\r
\r
//\r
// The ArmReplaceLiveTranslationEntry () helper function may be invoked\r
// with the MMU off so we have to ensure that it gets cleaned to the PoC\r
//\r
- WriteBackDataCacheRange ((VOID *)(UINTN)ArmReplaceLiveTranslationEntry,\r
- ArmReplaceLiveTranslationEntrySize);\r
+ WriteBackDataCacheRange (\r
+ (VOID *)(UINTN)ArmReplaceLiveTranslationEntry,\r
+ ArmReplaceLiveTranslationEntrySize\r
+ );\r
\r
return RETURN_SUCCESS;\r
}\r
EFI_STATUS\r
EFIAPI\r
ArmMmuPeiLibConstructor (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- extern UINT32 ArmReplaceLiveTranslationEntrySize;\r
+ extern UINT32 ArmReplaceLiveTranslationEntrySize;\r
\r
- EFI_FV_FILE_INFO FileInfo;\r
- EFI_STATUS Status;\r
+ EFI_FV_FILE_INFO FileInfo;\r
+ EFI_STATUS Status;\r
\r
ASSERT (FileHandle != NULL);\r
\r
// is executing from DRAM, we only need to perform the cache maintenance\r
// when not executing in place.\r
//\r
- if ((UINTN)FileInfo.Buffer <= (UINTN)ArmReplaceLiveTranslationEntry &&\r
+ if (((UINTN)FileInfo.Buffer <= (UINTN)ArmReplaceLiveTranslationEntry) &&\r
((UINTN)FileInfo.Buffer + FileInfo.BufferSize >=\r
- (UINTN)ArmReplaceLiveTranslationEntry + ArmReplaceLiveTranslationEntrySize)) {\r
+ (UINTN)ArmReplaceLiveTranslationEntry + ArmReplaceLiveTranslationEntrySize))\r
+ {\r
DEBUG ((DEBUG_INFO, "ArmMmuLib: skipping cache maintenance on XIP PEIM\n"));\r
} else {\r
DEBUG ((DEBUG_INFO, "ArmMmuLib: performing cache maintenance on shadowed PEIM\n"));\r
// The ArmReplaceLiveTranslationEntry () helper function may be invoked\r
// with the MMU off so we have to ensure that it gets cleaned to the PoC\r
//\r
- WriteBackDataCacheRange ((VOID *)(UINTN)ArmReplaceLiveTranslationEntry,\r
- ArmReplaceLiveTranslationEntrySize);\r
+ WriteBackDataCacheRange (\r
+ (VOID *)(UINTN)ArmReplaceLiveTranslationEntry,\r
+ ArmReplaceLiveTranslationEntrySize\r
+ );\r
}\r
\r
return RETURN_SUCCESS;\r
IN BOOLEAN IsLargePage\r
)\r
{\r
- UINT32 PageAttributes;\r
+ UINT32 PageAttributes;\r
\r
- PageAttributes = 0;\r
+ PageAttributes = 0;\r
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes, IsLargePage);\r
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);\r
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes, IsLargePage);\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
\r
-#define ID_MMFR0_SHARELVL_SHIFT 12\r
-#define ID_MMFR0_SHARELVL_MASK 0xf\r
-#define ID_MMFR0_SHARELVL_ONE 0\r
-#define ID_MMFR0_SHARELVL_TWO 1\r
+#define ID_MMFR0_SHARELVL_SHIFT 12\r
+#define ID_MMFR0_SHARELVL_MASK 0xf\r
+#define ID_MMFR0_SHARELVL_ONE 0\r
+#define ID_MMFR0_SHARELVL_TWO 1\r
\r
-#define ID_MMFR0_INNERSHR_SHIFT 28\r
-#define ID_MMFR0_INNERSHR_MASK 0xf\r
-#define ID_MMFR0_OUTERSHR_SHIFT 8\r
-#define ID_MMFR0_OUTERSHR_MASK 0xf\r
+#define ID_MMFR0_INNERSHR_SHIFT 28\r
+#define ID_MMFR0_INNERSHR_MASK 0xf\r
+#define ID_MMFR0_OUTERSHR_SHIFT 8\r
+#define ID_MMFR0_OUTERSHR_MASK 0xf\r
\r
-#define ID_MMFR0_SHR_IMP_UNCACHED 0\r
-#define ID_MMFR0_SHR_IMP_HW_COHERENT 1\r
-#define ID_MMFR0_SHR_IGNORED 0xf\r
+#define ID_MMFR0_SHR_IMP_UNCACHED 0\r
+#define ID_MMFR0_SHR_IMP_HW_COHERENT 1\r
+#define ID_MMFR0_SHR_IGNORED 0xf\r
\r
UINTN\r
EFIAPI\r
VOID\r
)\r
{\r
- UINTN Mmfr;\r
- UINTN Val;\r
+ UINTN Mmfr;\r
+ UINTN Val;\r
\r
if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride)) {\r
return TRUE;\r
//\r
Mmfr = ArmReadIdMmfr0 ();\r
switch ((Mmfr >> ID_MMFR0_SHARELVL_SHIFT) & ID_MMFR0_SHARELVL_MASK) {\r
- case ID_MMFR0_SHARELVL_ONE:\r
- // one level of shareability\r
- Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;\r
- break;\r
- case ID_MMFR0_SHARELVL_TWO:\r
- // two levels of shareability\r
- Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;\r
- break;\r
- default:\r
- // unexpected value -> shareable is the safe option\r
- ASSERT (FALSE);\r
- return FALSE;\r
+ case ID_MMFR0_SHARELVL_ONE:\r
+ // one level of shareability\r
+ Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;\r
+ break;\r
+ case ID_MMFR0_SHARELVL_TWO:\r
+ // two levels of shareability\r
+ Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;\r
+ break;\r
+ default:\r
+ // unexpected value -> shareable is the safe option\r
+ ASSERT (FALSE);\r
+ return FALSE;\r
}\r
+\r
return Val != ID_MMFR0_SHR_IMP_HW_COHERENT;\r
}\r
\r
STATIC\r
VOID\r
PopulateLevel2PageTable (\r
- IN UINT32 *SectionEntry,\r
- IN UINT32 PhysicalBase,\r
- IN UINT32 RemainLength,\r
- IN ARM_MEMORY_REGION_ATTRIBUTES Attributes\r
+ IN UINT32 *SectionEntry,\r
+ IN UINT32 PhysicalBase,\r
+ IN UINT32 RemainLength,\r
+ IN ARM_MEMORY_REGION_ATTRIBUTES Attributes\r
)\r
{\r
- UINT32* PageEntry;\r
+ UINT32 *PageEntry;\r
UINT32 Pages;\r
UINT32 Index;\r
UINT32 PageAttributes;\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
- PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
+ PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
// Level 2 Translation Table to it\r
if (*SectionEntry != 0) {\r
// The entry must be a page table. Otherwise it exists an overlapping in the memory map\r
- if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {\r
+ if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (*SectionEntry)) {\r
TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;\r
} else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {\r
// Case where a virtual memory map descriptor overlapped a section entry\r
// Allocate a Level2 Page Table for this Section\r
TranslationTable = (UINTN)AllocateAlignedPages (\r
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE),\r
- TRANSLATION_TABLE_PAGE_ALIGNMENT);\r
+ TRANSLATION_TABLE_PAGE_ALIGNMENT\r
+ );\r
\r
// Translate the Section Descriptor into Page Descriptor\r
SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);\r
\r
- BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);\r
+ BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (*SectionEntry);\r
\r
//\r
// Make sure we are not inadvertently hitting in the caches\r
// when populating the page tables\r
//\r
- InvalidateDataCacheRange ((VOID *)TranslationTable,\r
- TRANSLATION_TABLE_PAGE_SIZE);\r
+ InvalidateDataCacheRange (\r
+ (VOID *)TranslationTable,\r
+ TRANSLATION_TABLE_PAGE_SIZE\r
+ );\r
\r
// Populate the new Level2 Page Table for the section\r
- PageEntry = (UINT32*)TranslationTable;\r
+ PageEntry = (UINT32 *)TranslationTable;\r
for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r
- PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;\r
+ PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (BaseSectionAddress + (Index << 12)) | SectionDescriptor;\r
}\r
\r
// Overwrite the section entry to point to the new Level2 Translation Table\r
*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |\r
- (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |\r
- TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
+ (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE (Attributes) ? (1 << 3) : 0) |\r
+ TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
} else {\r
// We do not support the other section type (16MB Section)\r
- ASSERT(0);\r
+ ASSERT (0);\r
return;\r
}\r
} else {\r
TranslationTable = (UINTN)AllocateAlignedPages (\r
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE),\r
- TRANSLATION_TABLE_PAGE_ALIGNMENT);\r
+ TRANSLATION_TABLE_PAGE_ALIGNMENT\r
+ );\r
//\r
// Make sure we are not inadvertently hitting in the caches\r
// when populating the page tables\r
//\r
- InvalidateDataCacheRange ((VOID *)TranslationTable,\r
- TRANSLATION_TABLE_PAGE_SIZE);\r
+ InvalidateDataCacheRange (\r
+ (VOID *)TranslationTable,\r
+ TRANSLATION_TABLE_PAGE_SIZE\r
+ );\r
ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);\r
\r
*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |\r
- (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |\r
- TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
+ (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE (Attributes) ? (1 << 3) : 0) |\r
+ TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
}\r
\r
FirstPageOffset = (PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
- PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;\r
- Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;\r
+ PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;\r
+ Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;\r
\r
ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT);\r
\r
for (Index = 0; Index < Pages; Index++) {\r
- *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;\r
+ *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (PhysicalBase) | PageAttributes;\r
PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;\r
}\r
\r
// [speculatively] since the previous invalidate are evicted again.\r
//\r
ArmDataMemoryBarrier ();\r
- InvalidateDataCacheRange ((UINT32 *)TranslationTable + FirstPageOffset,\r
- RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry));\r
+ InvalidateDataCacheRange (\r
+ (UINT32 *)TranslationTable + FirstPageOffset,\r
+ RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry)\r
+ );\r
}\r
\r
STATIC\r
UINT64 RemainLength;\r
UINT32 PageMapLength;\r
\r
- ASSERT(MemoryRegion->Length > 0);\r
+ ASSERT (MemoryRegion->Length > 0);\r
\r
if (MemoryRegion->PhysicalBase >= SIZE_4GB) {\r
return;\r
}\r
\r
PhysicalBase = (UINT32)MemoryRegion->PhysicalBase;\r
- RemainLength = MIN(MemoryRegion->Length, SIZE_4GB - PhysicalBase);\r
+ RemainLength = MIN (MemoryRegion->Length, SIZE_4GB - PhysicalBase);\r
\r
switch (MemoryRegion->Attributes) {\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (0);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (0);\r
Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH (0);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
- Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);\r
+ Attributes = TT_DESCRIPTOR_SECTION_DEVICE (0);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (0);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (1);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (1);\r
Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH (1);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
- Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);\r
+ Attributes = TT_DESCRIPTOR_SECTION_DEVICE (1);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);\r
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (1);\r
break;\r
default:\r
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (0);\r
break;\r
}\r
\r
}\r
\r
// Get the first section entry for this mapping\r
- SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r
+ SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS (TranslationTable, MemoryRegion->VirtualBase);\r
\r
while (RemainLength != 0) {\r
- if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 &&\r
- RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {\r
+ if ((PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0) &&\r
+ (RemainLength >= TT_DESCRIPTOR_SECTION_SIZE))\r
+ {\r
// Case: Physical address aligned on the Section Size (1MB) && the length\r
// is greater than the Section Size\r
- *SectionEntry = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r
+ *SectionEntry = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (PhysicalBase) | Attributes;\r
\r
//\r
// Issue a DMB to ensure that the page table entry update made it to\r
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;\r
} else {\r
- PageMapLength = MIN ((UINT32)RemainLength, TT_DESCRIPTOR_SECTION_SIZE -\r
- (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE));\r
+ PageMapLength = MIN (\r
+ (UINT32)RemainLength,\r
+ TT_DESCRIPTOR_SECTION_SIZE -\r
+ (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE)\r
+ );\r
\r
// Case: Physical address aligned on the Section Size (1MB) && the length\r
// does not fill a section\r
// Case: Physical address NOT aligned on the Section Size (1MB)\r
- PopulateLevel2PageTable (SectionEntry, PhysicalBase, PageMapLength,\r
- MemoryRegion->Attributes);\r
+ PopulateLevel2PageTable (\r
+ SectionEntry,\r
+ PhysicalBase,\r
+ PageMapLength,\r
+ MemoryRegion->Attributes\r
+ );\r
\r
//\r
// Issue a DMB to ensure that the page table entry update made it to\r
EFIAPI\r
ArmConfigureMmu (\r
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
- OUT VOID **TranslationTableBase OPTIONAL,\r
+ OUT VOID **TranslationTableBase OPTIONAL,\r
OUT UINTN *TranslationTableSize OPTIONAL\r
)\r
{\r
- VOID *TranslationTable;\r
- UINT32 TTBRAttributes;\r
+ VOID *TranslationTable;\r
+ UINT32 TTBRAttributes;\r
\r
TranslationTable = AllocateAlignedPages (\r
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE),\r
- TRANSLATION_TABLE_SECTION_ALIGNMENT);\r
+ TRANSLATION_TABLE_SECTION_ALIGNMENT\r
+ );\r
if (TranslationTable == NULL) {\r
return RETURN_OUT_OF_RESOURCES;\r
}\r
//\r
ArmSetTTBCR (0);\r
\r
- ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |\r
- DOMAIN_ACCESS_CONTROL_NONE(14) |\r
- DOMAIN_ACCESS_CONTROL_NONE(13) |\r
- DOMAIN_ACCESS_CONTROL_NONE(12) |\r
- DOMAIN_ACCESS_CONTROL_NONE(11) |\r
- DOMAIN_ACCESS_CONTROL_NONE(10) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 9) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 8) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 7) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 6) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 5) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 4) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 3) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 2) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 1) |\r
- DOMAIN_ACCESS_CONTROL_CLIENT(0));\r
-\r
- ArmEnableInstructionCache();\r
- ArmEnableDataCache();\r
- ArmEnableMmu();\r
+ ArmSetDomainAccessControl (\r
+ DOMAIN_ACCESS_CONTROL_NONE (15) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (14) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (13) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (12) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (11) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (10) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (9) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (8) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (7) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (6) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (5) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (4) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (3) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (2) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (1) |\r
+ DOMAIN_ACCESS_CONTROL_CLIENT (0)\r
+ );\r
+\r
+ ArmEnableInstructionCache ();\r
+ ArmEnableDataCache ();\r
+ ArmEnableMmu ();\r
return RETURN_SUCCESS;\r
}\r
\r
#include <Chipset/ArmV7.h>\r
\r
-#define __EFI_MEMORY_RWX 0 // no restrictions\r
+#define __EFI_MEMORY_RWX 0 // no restrictions\r
\r
-#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \\r
+#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \\r
EFI_MEMORY_WC | \\r
EFI_MEMORY_WT | \\r
EFI_MEMORY_WB | \\r
IN EFI_PHYSICAL_ADDRESS BaseAddress\r
)\r
{\r
- UINT32 FirstLevelIdx;\r
- UINT32 SectionDescriptor;\r
- UINT32 PageTableDescriptor;\r
- UINT32 PageDescriptor;\r
- UINT32 Index;\r
+ UINT32 FirstLevelIdx;\r
+ UINT32 SectionDescriptor;\r
+ UINT32 PageTableDescriptor;\r
+ UINT32 PageDescriptor;\r
+ UINT32 Index;\r
\r
- volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
- volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
+ volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
\r
DEBUG ((DEBUG_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r
\r
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
\r
// Calculate index into first level translation table for start of modification\r
- FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
+ FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
\r
// Get section attributes and convert to page attributes\r
SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r
- PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE);\r
+ PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE);\r
\r
// Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r
PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1);\r
\r
// Write the page table entries out\r
for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r
- PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;\r
+ PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (BaseAddress + (Index << 12)) | PageDescriptor;\r
}\r
\r
// Formulate page table entry, Domain=0, NS=0\r
STATIC\r
EFI_STATUS\r
UpdatePageEntries (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes,\r
- OUT BOOLEAN *FlushTlbs OPTIONAL\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes,\r
+ OUT BOOLEAN *FlushTlbs OPTIONAL\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 EntryValue;\r
- UINT32 EntryMask;\r
- UINT32 FirstLevelIdx;\r
- UINT32 Offset;\r
- UINT32 NumPageEntries;\r
- UINT32 Descriptor;\r
- UINT32 p;\r
- UINT32 PageTableIndex;\r
- UINT32 PageTableEntry;\r
- UINT32 CurrentPageTableEntry;\r
- VOID *Mva;\r
-\r
- volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
- volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
+ EFI_STATUS Status;\r
+ UINT32 EntryValue;\r
+ UINT32 EntryMask;\r
+ UINT32 FirstLevelIdx;\r
+ UINT32 Offset;\r
+ UINT32 NumPageEntries;\r
+ UINT32 Descriptor;\r
+ UINT32 p;\r
+ UINT32 PageTableIndex;\r
+ UINT32 PageTableEntry;\r
+ UINT32 CurrentPageTableEntry;\r
+ VOID *Mva;\r
+\r
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
+ volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
\r
Status = EFI_SUCCESS;\r
\r
\r
// Iterate for the number of 4KB pages to change\r
Offset = 0;\r
- for(p = 0; p < NumPageEntries; p++) {\r
+ for (p = 0; p < NumPageEntries; p++) {\r
// Calculate index into first level translation table for page table value\r
\r
- FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
+ FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
\r
// Read the descriptor from the first level page table\r
Descriptor = FirstLevelTable[FirstLevelIdx];\r
\r
// Does this descriptor need to be converted from section entry to 4K pages?\r
- if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {\r
+ if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (Descriptor)) {\r
Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
// Exit for loop\r
break;\r
}\r
}\r
\r
// Obtain page table base address\r
- PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);\r
+ PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS (Descriptor);\r
\r
// Calculate index into the page table\r
PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r
}\r
\r
- Status = EFI_SUCCESS;\r
+ Status = EFI_SUCCESS;\r
Offset += TT_DESCRIPTOR_PAGE_SIZE;\r
-\r
} // End first level translation table loop\r
\r
return Status;\r
STATIC\r
EFI_STATUS\r
UpdateSectionEntries (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 EntryMask;\r
- UINT32 EntryValue;\r
- UINT32 FirstLevelIdx;\r
- UINT32 NumSections;\r
- UINT32 i;\r
- UINT32 CurrentDescriptor;\r
- UINT32 Descriptor;\r
- VOID *Mva;\r
- volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
+ EFI_STATUS Status;\r
+ UINT32 EntryMask;\r
+ UINT32 EntryValue;\r
+ UINT32 FirstLevelIdx;\r
+ UINT32 NumSections;\r
+ UINT32 i;\r
+ UINT32 CurrentDescriptor;\r
+ UINT32 Descriptor;\r
+ VOID *Mva;\r
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
\r
Status = EFI_SUCCESS;\r
\r
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r
\r
// calculate index into first level translation table for start of modification\r
- FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
+ FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r
\r
// calculate number of 1MB first level entries this applies to\r
NumSections = (UINT32)(Length / TT_DESCRIPTOR_SECTION_SIZE);\r
\r
// iterate through each descriptor\r
- for(i=0; i<NumSections; i++) {\r
+ for (i = 0; i < NumSections; i++) {\r
CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r
\r
// has this descriptor already been converted to pages?\r
- if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {\r
+ if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (CurrentDescriptor)) {\r
// forward this 1MB range to page table function instead\r
Status = UpdatePageEntries (\r
(FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT,\r
TT_DESCRIPTOR_SECTION_SIZE,\r
Attributes,\r
- NULL);\r
+ NULL\r
+ );\r
} else {\r
// still a section entry\r
\r
\r
EFI_STATUS\r
ArmSetMemoryAttributes (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT64 ChunkLength;\r
- BOOLEAN FlushTlbs;\r
+ EFI_STATUS Status;\r
+ UINT64 ChunkLength;\r
+ BOOLEAN FlushTlbs;\r
\r
if (BaseAddress > (UINT64)MAX_ADDRESS) {\r
return EFI_UNSUPPORTED;\r
FlushTlbs = FALSE;\r
while (Length > 0) {\r
if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) &&\r
- Length >= TT_DESCRIPTOR_SECTION_SIZE) {\r
-\r
+ (Length >= TT_DESCRIPTOR_SECTION_SIZE))\r
+ {\r
ChunkLength = Length - Length % TT_DESCRIPTOR_SECTION_SIZE;\r
\r
- DEBUG ((DEBUG_PAGE,\r
+ DEBUG ((\r
+ DEBUG_PAGE,\r
"SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n",\r
- BaseAddress, ChunkLength, Attributes));\r
+ BaseAddress,\r
+ ChunkLength,\r
+ Attributes\r
+ ));\r
\r
Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes);\r
\r
FlushTlbs = TRUE;\r
} else {\r
-\r
//\r
// Process page by page until the next section boundary, but only if\r
// we have more than a section's worth of area to deal with after that.\r
ChunkLength = Length;\r
}\r
\r
- DEBUG ((DEBUG_PAGE,\r
+ DEBUG ((\r
+ DEBUG_PAGE,\r
"SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n",\r
- BaseAddress, ChunkLength, Attributes));\r
+ BaseAddress,\r
+ ChunkLength,\r
+ Attributes\r
+ ));\r
\r
- Status = UpdatePageEntries (BaseAddress, ChunkLength, Attributes,\r
- &FlushTlbs);\r
+ Status = UpdatePageEntries (\r
+ BaseAddress,\r
+ ChunkLength,\r
+ Attributes,\r
+ &FlushTlbs\r
+ );\r
}\r
\r
if (EFI_ERROR (Status)) {\r
}\r
\r
BaseAddress += ChunkLength;\r
- Length -= ChunkLength;\r
+ Length -= ChunkLength;\r
}\r
\r
if (FlushTlbs) {\r
ArmInvalidateTlb ();\r
}\r
+\r
return Status;\r
}\r
\r
EFI_STATUS\r
ArmSetMemoryRegionNoExec (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP);\r
\r
EFI_STATUS\r
ArmClearMemoryRegionNoExec (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);\r
\r
EFI_STATUS\r
ArmSetMemoryRegionReadOnly (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);\r
\r
EFI_STATUS\r
ArmClearMemoryRegionReadOnly (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);\r
\r
@retval UINT32* Pointer to the payload.\r
**/\r
-UINT32*\r
+UINT32 *\r
MtlGetChannelPayload (\r
IN MTL_CHANNEL *Channel\r
)\r
EFI_STATUS\r
EFIAPI\r
LibResetSystem (\r
- IN EFI_RESET_TYPE ResetType,\r
- IN EFI_STATUS ResetStatus,\r
- IN UINTN DataSize,\r
- IN CHAR16 *ResetData OPTIONAL\r
+ IN EFI_RESET_TYPE ResetType,\r
+ IN EFI_STATUS ResetStatus,\r
+ IN UINTN DataSize,\r
+ IN CHAR16 *ResetData OPTIONAL\r
)\r
{\r
- ARM_SMC_ARGS ArmSmcArgs;\r
+ ARM_SMC_ARGS ArmSmcArgs;\r
\r
switch (ResetType) {\r
- case EfiResetPlatformSpecific:\r
+ case EfiResetPlatformSpecific:\r
// Map the platform specific reset as reboot\r
- case EfiResetWarm:\r
+ case EfiResetWarm:\r
// Map a warm reset into a cold reset\r
- case EfiResetCold:\r
- // Send a PSCI 0.2 SYSTEM_RESET command\r
- ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;\r
- break;\r
- case EfiResetShutdown:\r
- // Send a PSCI 0.2 SYSTEM_OFF command\r
- ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;\r
- break;\r
- default:\r
- ASSERT (FALSE);\r
- return EFI_UNSUPPORTED;\r
+ case EfiResetCold:\r
+ // Send a PSCI 0.2 SYSTEM_RESET command\r
+ ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;\r
+ break;\r
+ case EfiResetShutdown:\r
+ // Send a PSCI 0.2 SYSTEM_OFF command\r
+ ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;\r
+ break;\r
+ default:\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
}\r
\r
ArmCallSmc (&ArmSmcArgs);\r
\r
VOID\r
ArmCallSmc (\r
- IN OUT ARM_SMC_ARGS *Args\r
+ IN OUT ARM_SMC_ARGS *Args\r
)\r
{\r
}\r
VOID\r
)\r
{\r
- ARM_SMC_ARGS ArmSmcArgs;\r
+ ARM_SMC_ARGS ArmSmcArgs;\r
\r
// Send a PSCI 0.2 SYSTEM_RESET command\r
ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;\r
VOID\r
)\r
{\r
- ARM_SMC_ARGS ArmSmcArgs;\r
+ ARM_SMC_ARGS ArmSmcArgs;\r
\r
// Send a PSCI 0.2 SYSTEM_OFF command\r
ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;\r
VOID\r
EFIAPI\r
ResetPlatformSpecific (\r
- IN UINTN DataSize,\r
- IN VOID *ResetData\r
+ IN UINTN DataSize,\r
+ IN VOID *ResetData\r
)\r
{\r
// Map the platform specific reset as reboot\r
VOID\r
EFIAPI\r
ResetSystem (\r
- IN EFI_RESET_TYPE ResetType,\r
- IN EFI_STATUS ResetStatus,\r
- IN UINTN DataSize,\r
- IN VOID *ResetData OPTIONAL\r
+ IN EFI_RESET_TYPE ResetType,\r
+ IN EFI_STATUS ResetStatus,\r
+ IN UINTN DataSize,\r
+ IN VOID *ResetData OPTIONAL\r
)\r
{\r
switch (ResetType) {\r
- case EfiResetWarm:\r
- ResetWarm ();\r
- break;\r
+ case EfiResetWarm:\r
+ ResetWarm ();\r
+ break;\r
\r
- case EfiResetCold:\r
- ResetCold ();\r
- break;\r
+ case EfiResetCold:\r
+ ResetCold ();\r
+ break;\r
\r
- case EfiResetShutdown:\r
- ResetShutdown ();\r
- return;\r
+ case EfiResetShutdown:\r
+ ResetShutdown ();\r
+ return;\r
\r
- case EfiResetPlatformSpecific:\r
- ResetPlatformSpecific (DataSize, ResetData);\r
- return;\r
+ case EfiResetPlatformSpecific:\r
+ ResetPlatformSpecific (DataSize, ResetData);\r
+ return;\r
\r
- default:\r
- return;\r
+ default:\r
+ return;\r
}\r
}\r
* have been expected we use aeabi_float_t and aeabi_double_t respectively\r
* instead.\r
*/\r
-typedef uint32_t aeabi_float_t;\r
-typedef uint64_t aeabi_double_t;\r
+typedef uint32_t aeabi_float_t;\r
+typedef uint64_t aeabi_double_t;\r
\r
/*\r
* Helpers to convert between float32 and aeabi_float_t, and float64 and\r
* aeabi_double_t used by the AEABI functions below.\r
*/\r
-static aeabi_float_t f32_to_f(float32_t val)\r
+static aeabi_float_t\r
+f32_to_f (\r
+ float32_t val\r
+ )\r
{\r
return val.v;\r
}\r
\r
-static float32_t f32_from_f(aeabi_float_t val)\r
+static float32_t\r
+f32_from_f (\r
+ aeabi_float_t val\r
+ )\r
{\r
- float32_t res;\r
+ float32_t res;\r
\r
res.v = val;\r
\r
return res;\r
}\r
\r
-static aeabi_double_t f64_to_d(float64_t val)\r
+static aeabi_double_t\r
+f64_to_d (\r
+ float64_t val\r
+ )\r
{\r
return val.v;\r
}\r
\r
-static float64_t f64_from_d(aeabi_double_t val)\r
+static float64_t\r
+f64_from_d (\r
+ aeabi_double_t val\r
+ )\r
{\r
- float64_t res;\r
+ float64_t res;\r
\r
res.v = val;\r
\r
* Table 2, Standard aeabi_double_t precision floating-point arithmetic helper\r
* functions\r
*/\r
-\r
-aeabi_double_t __aeabi_dadd(aeabi_double_t a, aeabi_double_t b)\r
+aeabi_double_t\r
+__aeabi_dadd (\r
+ aeabi_double_t a,\r
+ aeabi_double_t b\r
+ )\r
{\r
- return f64_to_d(f64_add(f64_from_d(a), f64_from_d(b)));\r
+ return f64_to_d (f64_add (f64_from_d (a), f64_from_d (b)));\r
}\r
\r
-aeabi_double_t __aeabi_ddiv(aeabi_double_t a, aeabi_double_t b)\r
+aeabi_double_t\r
+__aeabi_ddiv (\r
+ aeabi_double_t a,\r
+ aeabi_double_t b\r
+ )\r
{\r
- return f64_to_d(f64_div(f64_from_d(a), f64_from_d(b)));\r
+ return f64_to_d (f64_div (f64_from_d (a), f64_from_d (b)));\r
}\r
\r
-aeabi_double_t __aeabi_dmul(aeabi_double_t a, aeabi_double_t b)\r
+aeabi_double_t\r
+__aeabi_dmul (\r
+ aeabi_double_t a,\r
+ aeabi_double_t b\r
+ )\r
{\r
- return f64_to_d(f64_mul(f64_from_d(a), f64_from_d(b)));\r
+ return f64_to_d (f64_mul (f64_from_d (a), f64_from_d (b)));\r
}\r
\r
-\r
-aeabi_double_t __aeabi_drsub(aeabi_double_t a, aeabi_double_t b)\r
+aeabi_double_t\r
+__aeabi_drsub (\r
+ aeabi_double_t a,\r
+ aeabi_double_t b\r
+ )\r
{\r
- return f64_to_d(f64_sub(f64_from_d(b), f64_from_d(a)));\r
+ return f64_to_d (f64_sub (f64_from_d (b), f64_from_d (a)));\r
}\r
\r
-aeabi_double_t __aeabi_dsub(aeabi_double_t a, aeabi_double_t b)\r
+aeabi_double_t\r
+__aeabi_dsub (\r
+ aeabi_double_t a,\r
+ aeabi_double_t b\r
+ )\r
{\r
- return f64_to_d(f64_sub(f64_from_d(a), f64_from_d(b)));\r
+ return f64_to_d (f64_sub (f64_from_d (a), f64_from_d (b)));\r
}\r
\r
/*\r
* Table 3, double precision floating-point comparison helper functions\r
*/\r
-\r
-int __aeabi_dcmpeq(aeabi_double_t a, aeabi_double_t b)\r
+int\r
+__aeabi_dcmpeq (\r
+ aeabi_double_t a,\r
+ aeabi_double_t b\r
+ )\r
{\r
- return f64_eq(f64_from_d(a), f64_from_d(b));\r
+ return f64_eq (f64_from_d (a), f64_from_d (b));\r
}\r
\r
-int __aeabi_dcmplt(aeabi_double_t a, aeabi_double_t b)\r
+int\r
+__aeabi_dcmplt (\r
+ aeabi_double_t a,\r
+ aeabi_double_t b\r
+ )\r
{\r
- return f64_lt(f64_from_d(a), f64_from_d(b));\r
+ return f64_lt (f64_from_d (a), f64_from_d (b));\r
}\r
\r
-int __aeabi_dcmple(aeabi_double_t a, aeabi_double_t b)\r
+int\r
+__aeabi_dcmple (\r
+ aeabi_double_t a,\r
+ aeabi_double_t b\r
+ )\r
{\r
- return f64_le(f64_from_d(a), f64_from_d(b));\r
+ return f64_le (f64_from_d (a), f64_from_d (b));\r
}\r
\r
-int __aeabi_dcmpge(aeabi_double_t a, aeabi_double_t b)\r
+int\r
+__aeabi_dcmpge (\r
+ aeabi_double_t a,\r
+ aeabi_double_t b\r
+ )\r
{\r
- return f64_le(f64_from_d(b), f64_from_d(a));\r
+ return f64_le (f64_from_d (b), f64_from_d (a));\r
}\r
\r
-int __aeabi_dcmpgt(aeabi_double_t a, aeabi_double_t b)\r
+int\r
+__aeabi_dcmpgt (\r
+ aeabi_double_t a,\r
+ aeabi_double_t b\r
+ )\r
{\r
- return f64_lt(f64_from_d(b), f64_from_d(a));\r
+ return f64_lt (f64_from_d (b), f64_from_d (a));\r
}\r
\r
/*\r
* Table 4, Standard single precision floating-point arithmetic helper\r
* functions\r
*/\r
-\r
-aeabi_float_t __aeabi_fadd(aeabi_float_t a, aeabi_float_t b)\r
+aeabi_float_t\r
+__aeabi_fadd (\r
+ aeabi_float_t a,\r
+ aeabi_float_t b\r
+ )\r
{\r
- return f32_to_f(f32_add(f32_from_f(a), f32_from_f(b)));\r
+ return f32_to_f (f32_add (f32_from_f (a), f32_from_f (b)));\r
}\r
\r
-aeabi_float_t __aeabi_fdiv(aeabi_float_t a, aeabi_float_t b)\r
+aeabi_float_t\r
+__aeabi_fdiv (\r
+ aeabi_float_t a,\r
+ aeabi_float_t b\r
+ )\r
{\r
- return f32_to_f(f32_div(f32_from_f(a), f32_from_f(b)));\r
+ return f32_to_f (f32_div (f32_from_f (a), f32_from_f (b)));\r
}\r
\r
-aeabi_float_t __aeabi_fmul(aeabi_float_t a, aeabi_float_t b)\r
+aeabi_float_t\r
+__aeabi_fmul (\r
+ aeabi_float_t a,\r
+ aeabi_float_t b\r
+ )\r
{\r
- return f32_to_f(f32_mul(f32_from_f(a), f32_from_f(b)));\r
+ return f32_to_f (f32_mul (f32_from_f (a), f32_from_f (b)));\r
}\r
\r
-aeabi_float_t __aeabi_frsub(aeabi_float_t a, aeabi_float_t b)\r
+aeabi_float_t\r
+__aeabi_frsub (\r
+ aeabi_float_t a,\r
+ aeabi_float_t b\r
+ )\r
{\r
- return f32_to_f(f32_sub(f32_from_f(b), f32_from_f(a)));\r
+ return f32_to_f (f32_sub (f32_from_f (b), f32_from_f (a)));\r
}\r
\r
-aeabi_float_t __aeabi_fsub(aeabi_float_t a, aeabi_float_t b)\r
+aeabi_float_t\r
+__aeabi_fsub (\r
+ aeabi_float_t a,\r
+ aeabi_float_t b\r
+ )\r
{\r
- return f32_to_f(f32_sub(f32_from_f(a), f32_from_f(b)));\r
+ return f32_to_f (f32_sub (f32_from_f (a), f32_from_f (b)));\r
}\r
\r
/*\r
* Table 5, Standard single precision floating-point comparison helper\r
* functions\r
*/\r
-\r
-int __aeabi_fcmpeq(aeabi_float_t a, aeabi_float_t b)\r
+int\r
+__aeabi_fcmpeq (\r
+ aeabi_float_t a,\r
+ aeabi_float_t b\r
+ )\r
{\r
- return f32_eq(f32_from_f(a), f32_from_f(b));\r
+ return f32_eq (f32_from_f (a), f32_from_f (b));\r
}\r
\r
-int __aeabi_fcmplt(aeabi_float_t a, aeabi_float_t b)\r
+int\r
+__aeabi_fcmplt (\r
+ aeabi_float_t a,\r
+ aeabi_float_t b\r
+ )\r
{\r
- return f32_lt(f32_from_f(a), f32_from_f(b));\r
+ return f32_lt (f32_from_f (a), f32_from_f (b));\r
}\r
\r
-int __aeabi_fcmple(aeabi_float_t a, aeabi_float_t b)\r
+int\r
+__aeabi_fcmple (\r
+ aeabi_float_t a,\r
+ aeabi_float_t b\r
+ )\r
{\r
- return f32_le(f32_from_f(a), f32_from_f(b));\r
+ return f32_le (f32_from_f (a), f32_from_f (b));\r
}\r
\r
-int __aeabi_fcmpge(aeabi_float_t a, aeabi_float_t b)\r
+int\r
+__aeabi_fcmpge (\r
+ aeabi_float_t a,\r
+ aeabi_float_t b\r
+ )\r
{\r
- return f32_le(f32_from_f(b), f32_from_f(a));\r
+ return f32_le (f32_from_f (b), f32_from_f (a));\r
}\r
\r
-int __aeabi_fcmpgt(aeabi_float_t a, aeabi_float_t b)\r
+int\r
+__aeabi_fcmpgt (\r
+ aeabi_float_t a,\r
+ aeabi_float_t b\r
+ )\r
{\r
- return f32_lt(f32_from_f(b), f32_from_f(a));\r
+ return f32_lt (f32_from_f (b), f32_from_f (a));\r
}\r
\r
/*\r
* Table 6, Standard floating-point to integer conversions\r
*/\r
-\r
-int __aeabi_d2iz(aeabi_double_t a)\r
+int\r
+__aeabi_d2iz (\r
+ aeabi_double_t a\r
+ )\r
{\r
- return f64_to_i32_r_minMag(f64_from_d(a), false);\r
+ return f64_to_i32_r_minMag (f64_from_d (a), false);\r
}\r
\r
-unsigned __aeabi_d2uiz(aeabi_double_t a)\r
+unsigned\r
+__aeabi_d2uiz (\r
+ aeabi_double_t a\r
+ )\r
{\r
- return f64_to_ui32_r_minMag(f64_from_d(a), false);\r
+ return f64_to_ui32_r_minMag (f64_from_d (a), false);\r
}\r
\r
-long long __aeabi_d2lz(aeabi_double_t a)\r
+long long\r
+__aeabi_d2lz (\r
+ aeabi_double_t a\r
+ )\r
{\r
- return f64_to_i64_r_minMag(f64_from_d(a), false);\r
+ return f64_to_i64_r_minMag (f64_from_d (a), false);\r
}\r
\r
-unsigned long long __aeabi_d2ulz(aeabi_double_t a)\r
+unsigned long long\r
+__aeabi_d2ulz (\r
+ aeabi_double_t a\r
+ )\r
{\r
- return f64_to_ui64_r_minMag(f64_from_d(a), false);\r
+ return f64_to_ui64_r_minMag (f64_from_d (a), false);\r
}\r
\r
-int __aeabi_f2iz(aeabi_float_t a)\r
+int\r
+__aeabi_f2iz (\r
+ aeabi_float_t a\r
+ )\r
{\r
- return f32_to_i32_r_minMag(f32_from_f(a), false);\r
+ return f32_to_i32_r_minMag (f32_from_f (a), false);\r
}\r
\r
-unsigned __aeabi_f2uiz(aeabi_float_t a)\r
+unsigned\r
+__aeabi_f2uiz (\r
+ aeabi_float_t a\r
+ )\r
{\r
- return f32_to_ui32_r_minMag(f32_from_f(a), false);\r
+ return f32_to_ui32_r_minMag (f32_from_f (a), false);\r
}\r
\r
-long long __aeabi_f2lz(aeabi_float_t a)\r
+long long\r
+__aeabi_f2lz (\r
+ aeabi_float_t a\r
+ )\r
{\r
- return f32_to_i64_r_minMag(f32_from_f(a), false);\r
+ return f32_to_i64_r_minMag (f32_from_f (a), false);\r
}\r
\r
-unsigned long long __aeabi_f2ulz(aeabi_float_t a)\r
+unsigned long long\r
+__aeabi_f2ulz (\r
+ aeabi_float_t a\r
+ )\r
{\r
- return f32_to_ui64_r_minMag(f32_from_f(a), false);\r
+ return f32_to_ui64_r_minMag (f32_from_f (a), false);\r
}\r
\r
/*\r
* Table 7, Standard conversions between floating types\r
*/\r
-\r
-aeabi_float_t __aeabi_d2f(aeabi_double_t a)\r
+aeabi_float_t\r
+__aeabi_d2f (\r
+ aeabi_double_t a\r
+ )\r
{\r
- return f32_to_f(f64_to_f32(f64_from_d(a)));\r
+ return f32_to_f (f64_to_f32 (f64_from_d (a)));\r
}\r
\r
-aeabi_double_t __aeabi_f2d(aeabi_float_t a)\r
+aeabi_double_t\r
+__aeabi_f2d (\r
+ aeabi_float_t a\r
+ )\r
{\r
- return f64_to_d(f32_to_f64(f32_from_f(a)));\r
+ return f64_to_d (f32_to_f64 (f32_from_f (a)));\r
}\r
\r
/*\r
* Table 8, Standard integer to floating-point conversions\r
*/\r
-\r
-aeabi_double_t __aeabi_i2d(int a)\r
+aeabi_double_t\r
+__aeabi_i2d (\r
+ int a\r
+ )\r
{\r
- return f64_to_d(i32_to_f64(a));\r
+ return f64_to_d (i32_to_f64 (a));\r
}\r
\r
-aeabi_double_t __aeabi_ui2d(unsigned a)\r
+aeabi_double_t\r
+__aeabi_ui2d (\r
+ unsigned a\r
+ )\r
{\r
- return f64_to_d(ui32_to_f64(a));\r
+ return f64_to_d (ui32_to_f64 (a));\r
}\r
\r
-aeabi_double_t __aeabi_l2d(long long a)\r
+aeabi_double_t\r
+__aeabi_l2d (\r
+ long long a\r
+ )\r
{\r
- return f64_to_d(i64_to_f64(a));\r
+ return f64_to_d (i64_to_f64 (a));\r
}\r
\r
-aeabi_double_t __aeabi_ul2d(unsigned long long a)\r
+aeabi_double_t\r
+__aeabi_ul2d (\r
+ unsigned long long a\r
+ )\r
{\r
- return f64_to_d(ui64_to_f64(a));\r
+ return f64_to_d (ui64_to_f64 (a));\r
}\r
\r
-aeabi_float_t __aeabi_i2f(int a)\r
+aeabi_float_t\r
+__aeabi_i2f (\r
+ int a\r
+ )\r
{\r
- return f32_to_f(i32_to_f32(a));\r
+ return f32_to_f (i32_to_f32 (a));\r
}\r
\r
-aeabi_float_t __aeabi_ui2f(unsigned a)\r
+aeabi_float_t\r
+__aeabi_ui2f (\r
+ unsigned a\r
+ )\r
{\r
- return f32_to_f(ui32_to_f32(a));\r
+ return f32_to_f (ui32_to_f32 (a));\r
}\r
\r
-aeabi_float_t __aeabi_l2f(long long a)\r
+aeabi_float_t\r
+__aeabi_l2f (\r
+ long long a\r
+ )\r
{\r
- return f32_to_f(i64_to_f32(a));\r
+ return f32_to_f (i64_to_f32 (a));\r
}\r
\r
-aeabi_float_t __aeabi_ul2f(unsigned long long a)\r
+aeabi_float_t\r
+__aeabi_ul2f (\r
+ unsigned long long a\r
+ )\r
{\r
- return f32_to_f(ui64_to_f32(a));\r
+ return f32_to_f (ui64_to_f32 (a));\r
}\r
#ifndef ARM_SOFT_FLOAT_LIB_H_\r
#define ARM_SOFT_FLOAT_LIB_H_\r
\r
-#define LITTLEENDIAN 1\r
-#define INLINE static inline\r
-#define SOFTFLOAT_BUILTIN_CLZ 1\r
+#define LITTLEENDIAN 1\r
+#define INLINE static inline\r
+#define SOFTFLOAT_BUILTIN_CLZ 1\r
#define SOFTFLOAT_FAST_INT64\r
#include "opts-GCC.h"\r
\r
-//------------------------------------------------------------------------------\r
+// ------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2019, Pete Batard. All rights reserved.\r
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>\r
//\r
// SPDX-License-Identifier: BSD-2-Clause-Patent\r
//\r
-//------------------------------------------------------------------------------\r
+// ------------------------------------------------------------------------------\r
\r
-#if defined(_M_ARM64)\r
-typedef unsigned __int64 size_t;\r
+#if defined (_M_ARM64)\r
+typedef unsigned __int64 size_t;\r
#else\r
-typedef unsigned __int32 size_t;\r
+typedef unsigned __int32 size_t;\r
#endif\r
\r
-int memcmp(void *, void *, size_t);\r
+int\r
+memcmp (\r
+ void *,\r
+ void *,\r
+ size_t\r
+ );\r
+\r
#pragma intrinsic(memcmp)\r
#pragma function(memcmp)\r
-int memcmp(const void *s1, const void *s2, size_t n)\r
+int\r
+memcmp (\r
+ const void *s1,\r
+ const void *s2,\r
+ size_t n\r
+ )\r
{\r
- unsigned char const *t1;\r
- unsigned char const *t2;\r
+ unsigned char const *t1;\r
+ unsigned char const *t2;\r
\r
t1 = s1;\r
t2 = s2;\r
\r
while (n-- != 0) {\r
- if (*t1 != *t2)\r
+ if (*t1 != *t2) {\r
return (int)*t1 - (int)*t2;\r
+ }\r
+\r
t1++;\r
t2++;\r
}\r
-//------------------------------------------------------------------------------\r
+// ------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>\r
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>\r
//\r
// SPDX-License-Identifier: BSD-2-Clause-Patent\r
//\r
-//------------------------------------------------------------------------------\r
+// ------------------------------------------------------------------------------\r
\r
typedef __SIZE_TYPE__ size_t;\r
\r
-static void __memcpy(void *dest, const void *src, size_t n)\r
+static void\r
+__memcpy (\r
+ void *dest,\r
+ const void *src,\r
+ size_t n\r
+ )\r
{\r
- unsigned char *d;\r
- unsigned char const *s;\r
+ unsigned char *d;\r
+ unsigned char const *s;\r
\r
d = dest;\r
s = src;\r
}\r
}\r
\r
-void *memcpy(void *dest, const void *src, size_t n)\r
+void *\r
+memcpy (\r
+ void *dest,\r
+ const void *src,\r
+ size_t n\r
+ )\r
{\r
- __memcpy(dest, src, n);\r
+ __memcpy (dest, src, n);\r
return dest;\r
}\r
\r
#ifdef __arm__\r
\r
-__attribute__((__alias__("__memcpy")))\r
-void __aeabi_memcpy(void *dest, const void *src, size_t n);\r
+__attribute__ ((__alias__ ("__memcpy")))\r
+void\r
+__aeabi_memcpy (\r
+ void *dest,\r
+ const void *src,\r
+ size_t n\r
+ );\r
\r
-__attribute__((__alias__("__memcpy")))\r
-void __aeabi_memcpy4(void *dest, const void *src, size_t n);\r
+__attribute__ ((__alias__ ("__memcpy")))\r
+void\r
+__aeabi_memcpy4 (\r
+ void *dest,\r
+ const void *src,\r
+ size_t n\r
+ );\r
\r
-__attribute__((__alias__("__memcpy")))\r
-void __aeabi_memcpy8(void *dest, const void *src, size_t n);\r
+__attribute__ ((__alias__ ("__memcpy")))\r
+void\r
+__aeabi_memcpy8 (\r
+ void *dest,\r
+ const void *src,\r
+ size_t n\r
+ );\r
\r
#endif\r
-//------------------------------------------------------------------------------\r
+// ------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2017, Pete Batard. All rights reserved.<BR>\r
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>\r
//\r
// SPDX-License-Identifier: BSD-2-Clause-Patent\r
//\r
-//------------------------------------------------------------------------------\r
+// ------------------------------------------------------------------------------\r
\r
-#if defined(_M_ARM64)\r
-typedef unsigned __int64 size_t;\r
+#if defined (_M_ARM64)\r
+typedef unsigned __int64 size_t;\r
#else\r
-typedef unsigned __int32 size_t;\r
+typedef unsigned __int32 size_t;\r
#endif\r
\r
-void* memcpy(void *, const void *, size_t);\r
+void *\r
+memcpy (\r
+ void *,\r
+ const void *,\r
+ size_t\r
+ );\r
+\r
#pragma intrinsic(memcpy)\r
#pragma function(memcpy)\r
-void* memcpy(void *dest, const void *src, size_t n)\r
+void *\r
+memcpy (\r
+ void *dest,\r
+ const void *src,\r
+ size_t n\r
+ )\r
{\r
- unsigned char *d;\r
- unsigned char const *s;\r
+ unsigned char *d;\r
+ unsigned char const *s;\r
\r
d = dest;\r
s = src;\r
-//------------------------------------------------------------------------------\r
+// ------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2019, Pete Batard. All rights reserved.\r
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>\r
//\r
// SPDX-License-Identifier: BSD-2-Clause-Patent\r
//\r
-//------------------------------------------------------------------------------\r
+// ------------------------------------------------------------------------------\r
\r
-#if defined(_M_ARM64)\r
-typedef unsigned __int64 size_t;\r
+#if defined (_M_ARM64)\r
+typedef unsigned __int64 size_t;\r
#else\r
-typedef unsigned __int32 size_t;\r
+typedef unsigned __int32 size_t;\r
#endif\r
\r
-void* memmove(void *, const void *, size_t);\r
+void *\r
+memmove (\r
+ void *,\r
+ const void *,\r
+ size_t\r
+ );\r
+\r
#pragma intrinsic(memmove)\r
#pragma function(memmove)\r
-void* memmove(void *dest, const void *src, size_t n)\r
+void *\r
+memmove (\r
+ void *dest,\r
+ const void *src,\r
+ size_t n\r
+ )\r
{\r
- unsigned char *d;\r
- unsigned char const *s;\r
+ unsigned char *d;\r
+ unsigned char const *s;\r
\r
d = dest;\r
s = src;\r
-//------------------------------------------------------------------------------\r
+// ------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>\r
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>\r
//\r
// SPDX-License-Identifier: BSD-2-Clause-Patent\r
//\r
-//------------------------------------------------------------------------------\r
+// ------------------------------------------------------------------------------\r
\r
typedef __SIZE_TYPE__ size_t;\r
\r
-static __attribute__((__used__))\r
-void *__memset(void *s, int c, size_t n)\r
+static __attribute__ ((__used__))\r
+void *\r
+__memset (\r
+ void *s,\r
+ int c,\r
+ size_t n\r
+ )\r
{\r
- unsigned char *d;\r
+ unsigned char *d;\r
\r
d = s;\r
\r
// object was pulled into the link due to the definitions below. So make\r
// our memset() 'weak' to let the other implementation take precedence.\r
//\r
-__attribute__((__weak__, __alias__("__memset")))\r
-void *memset(void *dest, int c, size_t n);\r
+__attribute__ ((__weak__, __alias__ ("__memset")))\r
+void *\r
+memset (\r
+ void *dest,\r
+ int c,\r
+ size_t n\r
+ );\r
\r
#ifdef __arm__\r
\r
-void __aeabi_memset(void *dest, size_t n, int c)\r
+void\r
+__aeabi_memset (\r
+ void *dest,\r
+ size_t n,\r
+ int c\r
+ )\r
{\r
- __memset(dest, c, n);\r
+ __memset (dest, c, n);\r
}\r
\r
-__attribute__((__alias__("__aeabi_memset")))\r
-void __aeabi_memset4(void *dest, size_t n, int c);\r
+__attribute__ ((__alias__ ("__aeabi_memset")))\r
+void\r
+__aeabi_memset4 (\r
+ void *dest,\r
+ size_t n,\r
+ int c\r
+ );\r
\r
-__attribute__((__alias__("__aeabi_memset")))\r
-void __aeabi_memset8(void *dest, size_t n, int c);\r
+__attribute__ ((__alias__ ("__aeabi_memset")))\r
+void\r
+__aeabi_memset8 (\r
+ void *dest,\r
+ size_t n,\r
+ int c\r
+ );\r
\r
-void __aeabi_memclr(void *dest, size_t n)\r
+void\r
+__aeabi_memclr (\r
+ void *dest,\r
+ size_t n\r
+ )\r
{\r
- __memset(dest, 0, n);\r
+ __memset (dest, 0, n);\r
}\r
\r
-__attribute__((__alias__("__aeabi_memclr")))\r
-void __aeabi_memclr4(void *dest, size_t n);\r
+__attribute__ ((__alias__ ("__aeabi_memclr")))\r
+void\r
+__aeabi_memclr4 (\r
+ void *dest,\r
+ size_t n\r
+ );\r
\r
-__attribute__((__alias__("__aeabi_memclr")))\r
-void __aeabi_memclr8(void *dest, size_t n);\r
+__attribute__ ((__alias__ ("__aeabi_memclr")))\r
+void\r
+__aeabi_memclr8 (\r
+ void *dest,\r
+ size_t n\r
+ );\r
\r
#endif\r
-//------------------------------------------------------------------------------\r
+// ------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2017, Pete Batard. All rights reserved.<BR>\r
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>\r
//\r
// SPDX-License-Identifier: BSD-2-Clause-Patent\r
//\r
-//------------------------------------------------------------------------------\r
+// ------------------------------------------------------------------------------\r
\r
-#if defined(_M_ARM64)\r
-typedef unsigned __int64 size_t;\r
+#if defined (_M_ARM64)\r
+typedef unsigned __int64 size_t;\r
#else\r
-typedef unsigned __int32 size_t;\r
+typedef unsigned __int32 size_t;\r
#endif\r
\r
-void* memset(void *, int, size_t);\r
+void *\r
+memset (\r
+ void *,\r
+ int,\r
+ size_t\r
+ );\r
+\r
#pragma intrinsic(memset)\r
#pragma function(memset)\r
-void *memset(void *s, int c, size_t n)\r
+void *\r
+memset (\r
+ void *s,\r
+ int c,\r
+ size_t n\r
+ )\r
{\r
- unsigned char *d;\r
+ unsigned char *d;\r
\r
d = s;\r
\r
#define GET_OCCUPIED_SIZE(ActualSize, Alignment) \\r
(ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((Alignment) - 1))\r
\r
-\r
// Vector Table for Sec Phase\r
VOID\r
DebugAgentVectorTable (\r
FileState = FfsHeader->State;\r
\r
if (ErasePolarity != 0) {\r
- FileState = (EFI_FFS_FILE_STATE)~FileState;\r
+ FileState = (EFI_FFS_FILE_STATE) ~FileState;\r
}\r
\r
HighestBit = 0x80;\r
IN EFI_FFS_FILE_HEADER *FileHeader\r
)\r
{\r
- UINT8 Sum;\r
+ UINT8 Sum;\r
\r
// Calculate the sum of the header\r
- Sum = CalculateSum8 ((CONST VOID*)FileHeader,sizeof(EFI_FFS_FILE_HEADER));\r
+ Sum = CalculateSum8 ((CONST VOID *)FileHeader, sizeof (EFI_FFS_FILE_HEADER));\r
\r
// State field (since this indicates the different state of file).\r
Sum = (UINT8)(Sum - FileHeader->State);\r
\r
EFI_STATUS\r
GetFfsFile (\r
- IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader,\r
- IN EFI_FV_FILETYPE FileType,\r
- OUT EFI_FFS_FILE_HEADER **FileHeader\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader,\r
+ IN EFI_FV_FILETYPE FileType,\r
+ OUT EFI_FFS_FILE_HEADER **FileHeader\r
)\r
{\r
- UINT64 FvLength;\r
- UINTN FileOffset;\r
- EFI_FFS_FILE_HEADER *FfsFileHeader;\r
- UINT8 ErasePolarity;\r
- UINT8 FileState;\r
- UINT32 FileLength;\r
- UINT32 FileOccupiedSize;\r
+ UINT64 FvLength;\r
+ UINTN FileOffset;\r
+ EFI_FFS_FILE_HEADER *FfsFileHeader;\r
+ UINT8 ErasePolarity;\r
+ UINT8 FileState;\r
+ UINT32 FileLength;\r
+ UINT32 FileOccupiedSize;\r
\r
ASSERT (FwVolHeader->Signature == EFI_FVH_SIGNATURE);\r
\r
- FvLength = FwVolHeader->FvLength;\r
+ FvLength = FwVolHeader->FvLength;\r
FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FwVolHeader + FwVolHeader->HeaderLength);\r
- FileOffset = FwVolHeader->HeaderLength;\r
+ FileOffset = FwVolHeader->HeaderLength;\r
\r
if (FwVolHeader->Attributes & EFI_FVB2_ERASE_POLARITY) {\r
ErasePolarity = 1;\r
FileState = GetFileState (ErasePolarity, FfsFileHeader);\r
\r
switch (FileState) {\r
+ case EFI_FILE_HEADER_INVALID:\r
+ FileOffset += sizeof (EFI_FFS_FILE_HEADER);\r
+ FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + sizeof (EFI_FFS_FILE_HEADER));\r
+ break;\r
\r
- case EFI_FILE_HEADER_INVALID:\r
- FileOffset += sizeof(EFI_FFS_FILE_HEADER);\r
- FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + sizeof(EFI_FFS_FILE_HEADER));\r
- break;\r
-\r
- case EFI_FILE_DATA_VALID:\r
- case EFI_FILE_MARKED_FOR_UPDATE:\r
- if (CalculateHeaderChecksum (FfsFileHeader) != 0) {\r
- ASSERT (FALSE);\r
- return EFI_NOT_FOUND;\r
- }\r
+ case EFI_FILE_DATA_VALID:\r
+ case EFI_FILE_MARKED_FOR_UPDATE:\r
+ if (CalculateHeaderChecksum (FfsFileHeader) != 0) {\r
+ ASSERT (FALSE);\r
+ return EFI_NOT_FOUND;\r
+ }\r
\r
- if (FfsFileHeader->Type == FileType) {\r
- *FileHeader = FfsFileHeader;\r
- return EFI_SUCCESS;\r
- }\r
+ if (FfsFileHeader->Type == FileType) {\r
+ *FileHeader = FfsFileHeader;\r
+ return EFI_SUCCESS;\r
+ }\r
\r
- FileLength = *(UINT32 *)(FfsFileHeader->Size) & 0x00FFFFFF;\r
- FileOccupiedSize = GET_OCCUPIED_SIZE(FileLength, 8);\r
+ FileLength = *(UINT32 *)(FfsFileHeader->Size) & 0x00FFFFFF;\r
+ FileOccupiedSize = GET_OCCUPIED_SIZE (FileLength, 8);\r
\r
- FileOffset += FileOccupiedSize;\r
- FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + FileOccupiedSize);\r
- break;\r
+ FileOffset += FileOccupiedSize;\r
+ FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + FileOccupiedSize);\r
+ break;\r
\r
- case EFI_FILE_DELETED:\r
- FileLength = *(UINT32 *)(FfsFileHeader->Size) & 0x00FFFFFF;\r
- FileOccupiedSize = GET_OCCUPIED_SIZE(FileLength, 8);\r
- FileOffset += FileOccupiedSize;\r
- FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + FileOccupiedSize);\r
- break;\r
+ case EFI_FILE_DELETED:\r
+ FileLength = *(UINT32 *)(FfsFileHeader->Size) & 0x00FFFFFF;\r
+ FileOccupiedSize = GET_OCCUPIED_SIZE (FileLength, 8);\r
+ FileOffset += FileOccupiedSize;\r
+ FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + FileOccupiedSize);\r
+ break;\r
\r
- default:\r
- return EFI_NOT_FOUND;\r
+ default:\r
+ return EFI_NOT_FOUND;\r
}\r
}\r
+\r
return EFI_NOT_FOUND;\r
}\r
\r
OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN ParsedLength;\r
- UINTN SectionSize;\r
- UINTN SectionLength;\r
- EFI_COMMON_SECTION_HEADER *Section;\r
- VOID *EfiImage;\r
- UINTN ImageAddress;\r
- EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *DebugEntry;\r
- VOID *CodeViewEntryPointer;\r
-\r
- Section = (EFI_COMMON_SECTION_HEADER *)(FfsHeader + 1);\r
- SectionSize = *(UINT32 *)(FfsHeader->Size) & 0x00FFFFFF;\r
+ EFI_STATUS Status;\r
+ UINTN ParsedLength;\r
+ UINTN SectionSize;\r
+ UINTN SectionLength;\r
+ EFI_COMMON_SECTION_HEADER *Section;\r
+ VOID *EfiImage;\r
+ UINTN ImageAddress;\r
+ EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *DebugEntry;\r
+ VOID *CodeViewEntryPointer;\r
+\r
+ Section = (EFI_COMMON_SECTION_HEADER *)(FfsHeader + 1);\r
+ SectionSize = *(UINT32 *)(FfsHeader->Size) & 0x00FFFFFF;\r
SectionSize -= sizeof (EFI_FFS_FILE_HEADER);\r
ParsedLength = 0;\r
- EfiImage = NULL;\r
+ EfiImage = NULL;\r
\r
while (ParsedLength < SectionSize) {\r
if ((Section->Type == EFI_SECTION_PE32) || (Section->Type == EFI_SECTION_TE)) {\r
- EfiImage = (EFI_IMAGE_OPTIONAL_HEADER_UNION*)(Section + 1);\r
+ EfiImage = (EFI_IMAGE_OPTIONAL_HEADER_UNION *)(Section + 1);\r
break;\r
}\r
\r
SectionLength = GET_OCCUPIED_SIZE (SectionLength, 4);\r
ASSERT (SectionLength != 0);\r
ParsedLength += SectionLength;\r
- Section = (EFI_COMMON_SECTION_HEADER *)((UINT8 *)Section + SectionLength);\r
+ Section = (EFI_COMMON_SECTION_HEADER *)((UINT8 *)Section + SectionLength);\r
}\r
\r
if (EfiImage == NULL) {\r
ImageContext->ImageRead = PeCoffLoaderImageReadFromMemory;\r
\r
Status = PeCoffLoaderGetImageInfo (ImageContext);\r
- if (!EFI_ERROR(Status) && ((VOID*)(UINTN)ImageContext->DebugDirectoryEntryRva != NULL)) {\r
+ if (!EFI_ERROR (Status) && ((VOID *)(UINTN)ImageContext->DebugDirectoryEntryRva != NULL)) {\r
ImageAddress = ImageContext->ImageAddress;\r
if (ImageContext->IsTeImage) {\r
- ImageAddress += sizeof (EFI_TE_IMAGE_HEADER) - ((EFI_TE_IMAGE_HEADER*)EfiImage)->StrippedSize;\r
+ ImageAddress += sizeof (EFI_TE_IMAGE_HEADER) - ((EFI_TE_IMAGE_HEADER *)EfiImage)->StrippedSize;\r
}\r
\r
- DebugEntry = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY*)(ImageAddress + ImageContext->DebugDirectoryEntryRva);\r
+ DebugEntry = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *)(ImageAddress + ImageContext->DebugDirectoryEntryRva);\r
if (DebugEntry->Type == EFI_IMAGE_DEBUG_TYPE_CODEVIEW) {\r
- CodeViewEntryPointer = (VOID *) (ImageAddress + (UINTN) DebugEntry->RVA);\r
- switch (* (UINT32 *) CodeViewEntryPointer) {\r
- case CODEVIEW_SIGNATURE_NB10:\r
- ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY);\r
- break;\r
- case CODEVIEW_SIGNATURE_RSDS:\r
- ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY);\r
- break;\r
- case CODEVIEW_SIGNATURE_MTOC:\r
- ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY);\r
- break;\r
- default:\r
- break;\r
+ CodeViewEntryPointer = (VOID *)(ImageAddress + (UINTN)DebugEntry->RVA);\r
+ switch (*(UINT32 *)CodeViewEntryPointer) {\r
+ case CODEVIEW_SIGNATURE_NB10:\r
+ ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY);\r
+ break;\r
+ case CODEVIEW_SIGNATURE_RSDS:\r
+ ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY);\r
+ break;\r
+ case CODEVIEW_SIGNATURE_MTOC:\r
+ ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY);\r
+ break;\r
+ default:\r
+ break;\r
}\r
}\r
}\r
IN DEBUG_AGENT_CONTINUE Function OPTIONAL\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_FFS_FILE_HEADER *FfsHeader;\r
+ EFI_STATUS Status;\r
+ EFI_FFS_FILE_HEADER *FfsHeader;\r
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;\r
\r
// We use InitFlag to know if DebugAgent has been initialized from\r
//\r
// Get the Sec or PrePeiCore module (defined as SEC type module)\r
//\r
- Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet64 (PcdSecureFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);\r
- if (!EFI_ERROR(Status)) {\r
- Status = GetImageContext (FfsHeader,&ImageContext);\r
- if (!EFI_ERROR(Status)) {\r
+ Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdSecureFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = GetImageContext (FfsHeader, &ImageContext);\r
+ if (!EFI_ERROR (Status)) {\r
PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
}\r
}\r
//\r
// Get the PrePi or PrePeiCore module (defined as SEC type module)\r
//\r
- Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);\r
- if (!EFI_ERROR(Status)) {\r
- Status = GetImageContext (FfsHeader,&ImageContext);\r
- if (!EFI_ERROR(Status)) {\r
+ Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = GetImageContext (FfsHeader, &ImageContext);\r
+ if (!EFI_ERROR (Status)) {\r
PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
}\r
}\r
//\r
// Get the PeiCore module (defined as PEI_CORE type module)\r
//\r
- Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_PEI_CORE, &FfsHeader);\r
- if (!EFI_ERROR(Status)) {\r
- Status = GetImageContext (FfsHeader,&ImageContext);\r
- if (!EFI_ERROR(Status)) {\r
+ Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_PEI_CORE, &FfsHeader);\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = GetImageContext (FfsHeader, &ImageContext);\r
+ if (!EFI_ERROR (Status)) {\r
PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
}\r
}\r
BOOLEAN\r
EFIAPI\r
SaveAndSetDebugTimerInterrupt (\r
- IN BOOLEAN EnableStatus\r
+ IN BOOLEAN EnableStatus\r
)\r
{\r
return FALSE;\r
#include <Library/PeCoffExtraActionLib.h>\r
#include <Library/PrintLib.h>\r
\r
-\r
/**\r
If the build is done on cygwin the paths are cygpaths.\r
/cygdrive/c/tmp.txt vs c:\tmp.txt so we need to convert\r
**/\r
CHAR8 *\r
DeCygwinPathIfNeeded (\r
- IN CHAR8 *Name,\r
- IN CHAR8 *Temp,\r
- IN UINTN Size\r
+ IN CHAR8 *Name,\r
+ IN CHAR8 *Temp,\r
+ IN UINTN Size\r
)\r
{\r
- CHAR8 *Ptr;\r
- UINTN Index;\r
- UINTN Index2;\r
+ CHAR8 *Ptr;\r
+ UINTN Index;\r
+ UINTN Index2;\r
\r
Ptr = AsciiStrStr (Name, "/cygdrive/");\r
if (Ptr == NULL) {\r
for (Index = 9, Index2 = 0; (Index < (Size + 9)) && (Ptr[Index] != '\0'); Index++, Index2++) {\r
Temp[Index2] = Ptr[Index];\r
if (Temp[Index2] == '/') {\r
- Temp[Index2] = '\\' ;\r
- }\r
+ Temp[Index2] = '\\';\r
+ }\r
\r
if (Index2 == 1) {\r
Temp[Index2 - 1] = Ptr[Index];\r
- Temp[Index2] = ':';\r
+ Temp[Index2] = ':';\r
}\r
}\r
\r
return Temp;\r
}\r
\r
-\r
/**\r
Performs additional actions after a PE/COFF image has been loaded and relocated.\r
\r
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
)\r
{\r
-#if !defined(MDEPKG_NDEBUG)\r
- CHAR8 Temp[512];\r
-#endif\r
+ #if !defined (MDEPKG_NDEBUG)\r
+ CHAR8 Temp[512];\r
+ #endif\r
\r
if (ImageContext->PdbPointer) {\r
-#ifdef __CC_ARM\r
-#if (__ARMCC_VERSION < 500000)\r
+ #ifdef __CC_ARM\r
+ #if (__ARMCC_VERSION < 500000)\r
// Print out the command for the RVD debugger to load symbols for this image\r
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "load /a /ni /np %a &0x%p\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));\r
-#else\r
+ #else\r
// Print out the command for the DS-5 to load symbols for this image\r
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "add-symbol-file %a 0x%p\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));\r
-#endif\r
-#elif __GNUC__\r
+ #endif\r
+ #elif __GNUC__\r
// This may not work correctly if you generate PE/COFF directly as then the Offset would not be required\r
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "add-symbol-file %a 0x%p\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));\r
-#else\r
- DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Loading driver at 0x%11p EntryPoint=0x%11p\n", (VOID *)(UINTN) ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));\r
-#endif\r
+ #else\r
+ DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Loading driver at 0x%11p EntryPoint=0x%11p\n", (VOID *)(UINTN)ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));\r
+ #endif\r
} else {\r
- DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Loading driver at 0x%11p EntryPoint=0x%11p\n", (VOID *)(UINTN) ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));\r
+ DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Loading driver at 0x%11p EntryPoint=0x%11p\n", (VOID *)(UINTN)ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));\r
}\r
}\r
\r
-\r
-\r
/**\r
Performs additional actions just before a PE/COFF image is unloaded. Any resources\r
that were allocated by PeCoffLoaderRelocateImageExtraAction() must be freed.\r
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
)\r
{\r
-#if !defined(MDEPKG_NDEBUG)\r
- CHAR8 Temp[512];\r
-#endif\r
+ #if !defined (MDEPKG_NDEBUG)\r
+ CHAR8 Temp[512];\r
+ #endif\r
\r
if (ImageContext->PdbPointer) {\r
-#ifdef __CC_ARM\r
+ #ifdef __CC_ARM\r
// Print out the command for the RVD debugger to load symbols for this image\r
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "unload symbols_only %a\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp))));\r
-#elif __GNUC__\r
+ #elif __GNUC__\r
// This may not work correctly if you generate PE/COFF directly as then the Offset would not be required\r
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "remove-symbol-file %a 0x%08x\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));\r
-#else\r
+ #else\r
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Unloading %a\n", ImageContext->PdbPointer));\r
-#endif\r
+ #endif\r
} else {\r
- DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Unloading driver at 0x%11p\n", (VOID *)(UINTN) ImageContext->ImageAddress));\r
+ DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Unloading driver at 0x%11p\n", (VOID *)(UINTN)ImageContext->ImageAddress));\r
}\r
}\r
#include <Protocol/DebugSupport.h>\r
#include <Protocol/LoadedImage.h>\r
\r
-STATIC CHAR8 *gExceptionTypeString[] = {\r
+STATIC CHAR8 *gExceptionTypeString[] = {\r
"Synchronous",\r
"IRQ",\r
"FIQ",\r
"SError"\r
};\r
\r
-STATIC BOOLEAN mRecursiveException;\r
+STATIC BOOLEAN mRecursiveException;\r
\r
CHAR8 *\r
GetImageName (\r
STATIC\r
VOID\r
DescribeInstructionOrDataAbort (\r
- IN CHAR8 *AbortType,\r
- IN UINTN Iss\r
+ IN CHAR8 *AbortType,\r
+ IN UINTN Iss\r
)\r
{\r
- CHAR8 *AbortCause;\r
+ CHAR8 *AbortCause;\r
\r
switch (Iss & 0x3f) {\r
- case 0x0: AbortCause = "Address size fault, zeroth level of translation or translation table base register"; break;\r
- case 0x1: AbortCause = "Address size fault, first level"; break;\r
- case 0x2: AbortCause = "Address size fault, second level"; break;\r
- case 0x3: AbortCause = "Address size fault, third level"; break;\r
- case 0x4: AbortCause = "Translation fault, zeroth level"; break;\r
- case 0x5: AbortCause = "Translation fault, first level"; break;\r
- case 0x6: AbortCause = "Translation fault, second level"; break;\r
- case 0x7: AbortCause = "Translation fault, third level"; break;\r
- case 0x9: AbortCause = "Access flag fault, first level"; break;\r
- case 0xa: AbortCause = "Access flag fault, second level"; break;\r
- case 0xb: AbortCause = "Access flag fault, third level"; break;\r
- case 0xd: AbortCause = "Permission fault, first level"; break;\r
- case 0xe: AbortCause = "Permission fault, second level"; break;\r
- case 0xf: AbortCause = "Permission fault, third level"; break;\r
- case 0x10: AbortCause = "Synchronous external abort"; break;\r
- case 0x18: AbortCause = "Synchronous parity error on memory access"; break;\r
- case 0x11: AbortCause = "Asynchronous external abort"; break;\r
- case 0x19: AbortCause = "Asynchronous parity error on memory access"; break;\r
- case 0x14: AbortCause = "Synchronous external abort on translation table walk, zeroth level"; break;\r
- case 0x15: AbortCause = "Synchronous external abort on translation table walk, first level"; break;\r
- case 0x16: AbortCause = "Synchronous external abort on translation table walk, second level"; break;\r
- case 0x17: AbortCause = "Synchronous external abort on translation table walk, third level"; break;\r
- case 0x1c: AbortCause = "Synchronous parity error on memory access on translation table walk, zeroth level"; break;\r
- case 0x1d: AbortCause = "Synchronous parity error on memory access on translation table walk, first level"; break;\r
- case 0x1e: AbortCause = "Synchronous parity error on memory access on translation table walk, second level"; break;\r
- case 0x1f: AbortCause = "Synchronous parity error on memory access on translation table walk, third level"; break;\r
- case 0x21: AbortCause = "Alignment fault"; break;\r
- case 0x22: AbortCause = "Debug event"; break;\r
- case 0x30: AbortCause = "TLB conflict abort"; break;\r
+ case 0x0: AbortCause = "Address size fault, zeroth level of translation or translation table base register";\r
+ break;\r
+ case 0x1: AbortCause = "Address size fault, first level";\r
+ break;\r
+ case 0x2: AbortCause = "Address size fault, second level";\r
+ break;\r
+ case 0x3: AbortCause = "Address size fault, third level";\r
+ break;\r
+ case 0x4: AbortCause = "Translation fault, zeroth level";\r
+ break;\r
+ case 0x5: AbortCause = "Translation fault, first level";\r
+ break;\r
+ case 0x6: AbortCause = "Translation fault, second level";\r
+ break;\r
+ case 0x7: AbortCause = "Translation fault, third level";\r
+ break;\r
+ case 0x9: AbortCause = "Access flag fault, first level";\r
+ break;\r
+ case 0xa: AbortCause = "Access flag fault, second level";\r
+ break;\r
+ case 0xb: AbortCause = "Access flag fault, third level";\r
+ break;\r
+ case 0xd: AbortCause = "Permission fault, first level";\r
+ break;\r
+ case 0xe: AbortCause = "Permission fault, second level";\r
+ break;\r
+ case 0xf: AbortCause = "Permission fault, third level";\r
+ break;\r
+ case 0x10: AbortCause = "Synchronous external abort";\r
+ break;\r
+ case 0x18: AbortCause = "Synchronous parity error on memory access";\r
+ break;\r
+ case 0x11: AbortCause = "Asynchronous external abort";\r
+ break;\r
+ case 0x19: AbortCause = "Asynchronous parity error on memory access";\r
+ break;\r
+ case 0x14: AbortCause = "Synchronous external abort on translation table walk, zeroth level";\r
+ break;\r
+ case 0x15: AbortCause = "Synchronous external abort on translation table walk, first level";\r
+ break;\r
+ case 0x16: AbortCause = "Synchronous external abort on translation table walk, second level";\r
+ break;\r
+ case 0x17: AbortCause = "Synchronous external abort on translation table walk, third level";\r
+ break;\r
+ case 0x1c: AbortCause = "Synchronous parity error on memory access on translation table walk, zeroth level";\r
+ break;\r
+ case 0x1d: AbortCause = "Synchronous parity error on memory access on translation table walk, first level";\r
+ break;\r
+ case 0x1e: AbortCause = "Synchronous parity error on memory access on translation table walk, second level";\r
+ break;\r
+ case 0x1f: AbortCause = "Synchronous parity error on memory access on translation table walk, third level";\r
+ break;\r
+ case 0x21: AbortCause = "Alignment fault";\r
+ break;\r
+ case 0x22: AbortCause = "Debug event";\r
+ break;\r
+ case 0x30: AbortCause = "TLB conflict abort";\r
+ break;\r
case 0x33:\r
- case 0x34: AbortCause = "IMPLEMENTATION DEFINED"; break;\r
+ case 0x34: AbortCause = "IMPLEMENTATION DEFINED";\r
+ break;\r
case 0x35:\r
- case 0x36: AbortCause = "Domain fault"; break;\r
- default: AbortCause = ""; break;\r
+ case 0x36: AbortCause = "Domain fault";\r
+ break;\r
+ default: AbortCause = "";\r
+ break;\r
}\r
\r
DEBUG ((DEBUG_ERROR, "\n%a: %a\n", AbortType, AbortCause));\r
STATIC\r
VOID\r
DescribeExceptionSyndrome (\r
- IN UINT32 Esr\r
+ IN UINT32 Esr\r
)\r
{\r
- CHAR8 *Message;\r
- UINTN Ec;\r
- UINTN Iss;\r
+ CHAR8 *Message;\r
+ UINTN Ec;\r
+ UINTN Iss;\r
\r
- Ec = Esr >> 26;\r
+ Ec = Esr >> 26;\r
Iss = Esr & 0x00ffffff;\r
\r
switch (Ec) {\r
- case 0x15: Message = "SVC executed in AArch64"; break;\r
+ case 0x15: Message = "SVC executed in AArch64";\r
+ break;\r
case 0x20:\r
- case 0x21: DescribeInstructionOrDataAbort ("Instruction abort", Iss); return;\r
- case 0x22: Message = "PC alignment fault"; break;\r
- case 0x23: Message = "SP alignment fault"; break;\r
+ case 0x21: DescribeInstructionOrDataAbort ("Instruction abort", Iss);\r
+ return;\r
+ case 0x22: Message = "PC alignment fault";\r
+ break;\r
+ case 0x23: Message = "SP alignment fault";\r
+ break;\r
case 0x24:\r
- case 0x25: DescribeInstructionOrDataAbort ("Data abort", Iss); return;\r
+ case 0x25: DescribeInstructionOrDataAbort ("Data abort", Iss);\r
+ return;\r
default: return;\r
}\r
\r
STATIC\r
CONST CHAR8 *\r
BaseName (\r
- IN CONST CHAR8 *FullName\r
+ IN CONST CHAR8 *FullName\r
)\r
{\r
- CONST CHAR8 *Str;\r
+ CONST CHAR8 *Str;\r
\r
Str = FullName + AsciiStrLen (FullName);\r
\r
while (--Str > FullName) {\r
- if (*Str == '/' || *Str == '\\') {\r
+ if ((*Str == '/') || (*Str == '\\')) {\r
return Str + 1;\r
}\r
}\r
+\r
return Str;\r
}\r
+\r
#endif\r
\r
/**\r
**/\r
VOID\r
DefaultExceptionHandler (\r
- IN EFI_EXCEPTION_TYPE ExceptionType,\r
- IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
+ IN EFI_EXCEPTION_TYPE ExceptionType,\r
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
)\r
{\r
CHAR8 Buffer[100];\r
INT32 Offset;\r
\r
if (mRecursiveException) {\r
- STATIC CHAR8 CONST Message[] = "\nRecursive exception occurred while dumping the CPU state\n";\r
+ STATIC CHAR8 CONST Message[] = "\nRecursive exception occurred while dumping the CPU state\n";\r
\r
SerialPortWrite ((UINT8 *)Message, sizeof Message - 1);\r
if (gST->ConOut != NULL) {\r
AsciiPrint (Message);\r
}\r
+\r
CpuDeadLoop ();\r
}\r
+\r
mRecursiveException = TRUE;\r
\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"\n\n%a Exception at 0x%016lx\n", gExceptionTypeString[ExceptionType], SystemContext.SystemContextAArch64->ELR);\r
- SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n\n%a Exception at 0x%016lx\n", gExceptionTypeString[ExceptionType], SystemContext.SystemContextAArch64->ELR);\r
+ SerialPortWrite ((UINT8 *)Buffer, CharCount);\r
if (gST->ConOut != NULL) {\r
AsciiPrint (Buffer);\r
}\r
\r
DEBUG_CODE_BEGIN ();\r
- CHAR8 *Pdb, *PrevPdb;\r
- UINTN ImageBase;\r
- UINTN PeCoffSizeOfHeader;\r
- UINT64 *Fp;\r
- UINT64 RootFp[2];\r
- UINTN Idx;\r
+ CHAR8 *Pdb, *PrevPdb;\r
+ UINTN ImageBase;\r
+ UINTN PeCoffSizeOfHeader;\r
+ UINT64 *Fp;\r
+ UINT64 RootFp[2];\r
+ UINTN Idx;\r
+\r
+ PrevPdb = Pdb = GetImageName (SystemContext.SystemContextAArch64->ELR, &ImageBase, &PeCoffSizeOfHeader);\r
+ if (Pdb != NULL) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "PC 0x%012lx (0x%012lx+0x%08x) [ 0] %a\n",\r
+ SystemContext.SystemContextAArch64->ELR,\r
+ ImageBase,\r
+ SystemContext.SystemContextAArch64->ELR - ImageBase,\r
+ BaseName (Pdb)\r
+ ));\r
+ } else {\r
+ DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", SystemContext.SystemContextAArch64->ELR));\r
+ }\r
\r
- PrevPdb = Pdb = GetImageName (SystemContext.SystemContextAArch64->ELR, &ImageBase, &PeCoffSizeOfHeader);\r
- if (Pdb != NULL) {\r
- DEBUG ((DEBUG_ERROR, "PC 0x%012lx (0x%012lx+0x%08x) [ 0] %a\n",\r
- SystemContext.SystemContextAArch64->ELR, ImageBase,\r
- SystemContext.SystemContextAArch64->ELR - ImageBase, BaseName (Pdb)));\r
- } else {\r
- DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", SystemContext.SystemContextAArch64->ELR));\r
- }\r
+ if ((UINT64 *)SystemContext.SystemContextAArch64->FP != 0) {\r
+ Idx = 0;\r
\r
- if ((UINT64 *)SystemContext.SystemContextAArch64->FP != 0) {\r
- Idx = 0;\r
+ RootFp[0] = ((UINT64 *)SystemContext.SystemContextAArch64->FP)[0];\r
+ RootFp[1] = ((UINT64 *)SystemContext.SystemContextAArch64->FP)[1];\r
+ if (RootFp[1] != SystemContext.SystemContextAArch64->LR) {\r
+ RootFp[0] = SystemContext.SystemContextAArch64->FP;\r
+ RootFp[1] = SystemContext.SystemContextAArch64->LR;\r
+ }\r
\r
- RootFp[0] = ((UINT64 *)SystemContext.SystemContextAArch64->FP)[0];\r
- RootFp[1] = ((UINT64 *)SystemContext.SystemContextAArch64->FP)[1];\r
- if (RootFp[1] != SystemContext.SystemContextAArch64->LR) {\r
- RootFp[0] = SystemContext.SystemContextAArch64->FP;\r
- RootFp[1] = SystemContext.SystemContextAArch64->LR;\r
- }\r
- for (Fp = RootFp; Fp[0] != 0; Fp = (UINT64 *)Fp[0]) {\r
- Pdb = GetImageName (Fp[1], &ImageBase, &PeCoffSizeOfHeader);\r
- if (Pdb != NULL) {\r
- if (Pdb != PrevPdb) {\r
- Idx++;\r
- PrevPdb = Pdb;\r
- }\r
- DEBUG ((DEBUG_ERROR, "PC 0x%012lx (0x%012lx+0x%08x) [% 2d] %a\n",\r
- Fp[1], ImageBase, Fp[1] - ImageBase, Idx, BaseName (Pdb)));\r
- } else {\r
- DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", Fp[1]));\r
- }\r
- }\r
- PrevPdb = Pdb = GetImageName (SystemContext.SystemContextAArch64->ELR, &ImageBase, &PeCoffSizeOfHeader);\r
+ for (Fp = RootFp; Fp[0] != 0; Fp = (UINT64 *)Fp[0]) {\r
+ Pdb = GetImageName (Fp[1], &ImageBase, &PeCoffSizeOfHeader);\r
if (Pdb != NULL) {\r
- DEBUG ((DEBUG_ERROR, "\n[ 0] %a\n", Pdb));\r
- }\r
-\r
- Idx = 0;\r
- for (Fp = RootFp; Fp[0] != 0; Fp = (UINT64 *)Fp[0]) {\r
- Pdb = GetImageName (Fp[1], &ImageBase, &PeCoffSizeOfHeader);\r
- if (Pdb != NULL && Pdb != PrevPdb) {\r
- DEBUG ((DEBUG_ERROR, "[% 2d] %a\n", ++Idx, Pdb));\r
+ if (Pdb != PrevPdb) {\r
+ Idx++;\r
PrevPdb = Pdb;\r
}\r
+\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "PC 0x%012lx (0x%012lx+0x%08x) [% 2d] %a\n",\r
+ Fp[1],\r
+ ImageBase,\r
+ Fp[1] - ImageBase,\r
+ Idx,\r
+ BaseName (Pdb)\r
+ ));\r
+ } else {\r
+ DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", Fp[1]));\r
+ }\r
+ }\r
+\r
+ PrevPdb = Pdb = GetImageName (SystemContext.SystemContextAArch64->ELR, &ImageBase, &PeCoffSizeOfHeader);\r
+ if (Pdb != NULL) {\r
+ DEBUG ((DEBUG_ERROR, "\n[ 0] %a\n", Pdb));\r
+ }\r
+\r
+ Idx = 0;\r
+ for (Fp = RootFp; Fp[0] != 0; Fp = (UINT64 *)Fp[0]) {\r
+ Pdb = GetImageName (Fp[1], &ImageBase, &PeCoffSizeOfHeader);\r
+ if ((Pdb != NULL) && (Pdb != PrevPdb)) {\r
+ DEBUG ((DEBUG_ERROR, "[% 2d] %a\n", ++Idx, Pdb));\r
+ PrevPdb = Pdb;\r
}\r
}\r
+ }\r
+\r
DEBUG_CODE_END ();\r
\r
DEBUG ((DEBUG_ERROR, "\n X0 0x%016lx X1 0x%016lx X2 0x%016lx X3 0x%016lx\n", SystemContext.SystemContextAArch64->X0, SystemContext.SystemContextAArch64->X1, SystemContext.SystemContextAArch64->X2, SystemContext.SystemContextAArch64->X3));\r
\r
DEBUG ((DEBUG_ERROR, "\n SP 0x%016lx ELR 0x%016lx SPSR 0x%08lx FPSR 0x%08lx\n ESR 0x%08lx FAR 0x%016lx\n", SystemContext.SystemContextAArch64->SP, SystemContext.SystemContextAArch64->ELR, SystemContext.SystemContextAArch64->SPSR, SystemContext.SystemContextAArch64->FPSR, SystemContext.SystemContextAArch64->ESR, SystemContext.SystemContextAArch64->FAR));\r
\r
- DEBUG ((DEBUG_ERROR, "\n ESR : EC 0x%02x IL 0x%x ISS 0x%08x\n", (SystemContext.SystemContextAArch64->ESR & 0xFC000000) >> 26, (SystemContext.SystemContextAArch64->ESR >> 25) & 0x1, SystemContext.SystemContextAArch64->ESR & 0x1FFFFFF ));\r
+ DEBUG ((DEBUG_ERROR, "\n ESR : EC 0x%02x IL 0x%x ISS 0x%08x\n", (SystemContext.SystemContextAArch64->ESR & 0xFC000000) >> 26, (SystemContext.SystemContextAArch64->ESR >> 25) & 0x1, SystemContext.SystemContextAArch64->ESR & 0x1FFFFFF));\r
\r
DescribeExceptionSyndrome (SystemContext.SystemContextAArch64->ESR);\r
\r
DEBUG ((DEBUG_ERROR, "\nStack dump:\n"));\r
for (Offset = -256; Offset < 256; Offset += 32) {\r
- DEBUG ((DEBUG_ERROR, "%c %013lx: %016lx %016lx %016lx %016lx\n",\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%c %013lx: %016lx %016lx %016lx %016lx\n",\r
Offset == 0 ? '>' : ' ',\r
SystemContext.SystemContextAArch64->SP + Offset,\r
*(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset),\r
*(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset + 8),\r
*(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset + 16),\r
- *(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset + 24)));\r
+ *(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset + 24)\r
+ ));\r
}\r
\r
ASSERT (FALSE);\r
// The number of elements in a CHAR8 array, including the terminating NUL, that\r
// is meant to hold the string rendering of the CPSR.\r
//\r
-#define CPSR_STRING_SIZE 32\r
+#define CPSR_STRING_SIZE 32\r
\r
typedef struct {\r
- UINT32 BIT;\r
- CHAR8 Char;\r
+ UINT32 BIT;\r
+ CHAR8 Char;\r
} CPSR_CHAR;\r
\r
-STATIC CONST CPSR_CHAR mCpsrChar[] = {\r
+STATIC CONST CPSR_CHAR mCpsrChar[] = {\r
{ 31, 'n' },\r
{ 30, 'z' },\r
{ 29, 'c' },\r
OUT CHAR8 *ReturnStr\r
)\r
{\r
- UINTN Index;\r
- CHAR8* Str;\r
- CHAR8* ModeStr;\r
+ UINTN Index;\r
+ CHAR8 *Str;\r
+ CHAR8 *ModeStr;\r
\r
Str = ReturnStr;\r
\r
}\r
\r
*Str++ = '_';\r
- *Str = '\0';\r
+ *Str = '\0';\r
\r
switch (Cpsr & 0x1f) {\r
- case 0x10:\r
- ModeStr = "usr";\r
- break;\r
- case 0x011:\r
- ModeStr = "fiq";\r
- break;\r
- case 0x12:\r
- ModeStr = "irq";\r
- break;\r
- case 0x13:\r
- ModeStr = "svc";\r
- break;\r
- case 0x16:\r
- ModeStr = "mon";\r
- break;\r
- case 0x17:\r
- ModeStr = "abt";\r
- break;\r
- case 0x1b:\r
- ModeStr = "und";\r
- break;\r
- case 0x1f:\r
- ModeStr = "sys";\r
- break;\r
-\r
- default:\r
- ModeStr = "???";\r
- break;\r
+ case 0x10:\r
+ ModeStr = "usr";\r
+ break;\r
+ case 0x011:\r
+ ModeStr = "fiq";\r
+ break;\r
+ case 0x12:\r
+ ModeStr = "irq";\r
+ break;\r
+ case 0x13:\r
+ ModeStr = "svc";\r
+ break;\r
+ case 0x16:\r
+ ModeStr = "mon";\r
+ break;\r
+ case 0x17:\r
+ ModeStr = "abt";\r
+ break;\r
+ case 0x1b:\r
+ ModeStr = "und";\r
+ break;\r
+ case 0x1f:\r
+ ModeStr = "sys";\r
+ break;\r
+\r
+ default:\r
+ ModeStr = "???";\r
+ break;\r
}\r
\r
//\r
IN UINT32 Status\r
)\r
{\r
- CHAR8 *FaultSource;\r
+ CHAR8 *FaultSource;\r
\r
switch (Status) {\r
- case 0x01: FaultSource = "Alignment fault"; break;\r
- case 0x02: FaultSource = "Debug event fault"; break;\r
- case 0x03: FaultSource = "Access Flag fault on Section"; break;\r
- case 0x04: FaultSource = "Cache maintenance operation fault[2]"; break;\r
- case 0x05: FaultSource = "Translation fault on Section"; break;\r
- case 0x06: FaultSource = "Access Flag fault on Page"; break;\r
- case 0x07: FaultSource = "Translation fault on Page"; break;\r
- case 0x08: FaultSource = "Precise External Abort"; break;\r
- case 0x09: FaultSource = "Domain fault on Section"; break;\r
- case 0x0b: FaultSource = "Domain fault on Page"; break;\r
- case 0x0c: FaultSource = "External abort on translation, first level"; break;\r
- case 0x0d: FaultSource = "Permission fault on Section"; break;\r
- case 0x0e: FaultSource = "External abort on translation, second level"; break;\r
- case 0x0f: FaultSource = "Permission fault on Page"; break;\r
- case 0x16: FaultSource = "Imprecise External Abort"; break;\r
- default: FaultSource = "No function"; break;\r
- }\r
+ case 0x01: FaultSource = "Alignment fault";\r
+ break;\r
+ case 0x02: FaultSource = "Debug event fault";\r
+ break;\r
+ case 0x03: FaultSource = "Access Flag fault on Section";\r
+ break;\r
+ case 0x04: FaultSource = "Cache maintenance operation fault[2]";\r
+ break;\r
+ case 0x05: FaultSource = "Translation fault on Section";\r
+ break;\r
+ case 0x06: FaultSource = "Access Flag fault on Page";\r
+ break;\r
+ case 0x07: FaultSource = "Translation fault on Page";\r
+ break;\r
+ case 0x08: FaultSource = "Precise External Abort";\r
+ break;\r
+ case 0x09: FaultSource = "Domain fault on Section";\r
+ break;\r
+ case 0x0b: FaultSource = "Domain fault on Page";\r
+ break;\r
+ case 0x0c: FaultSource = "External abort on translation, first level";\r
+ break;\r
+ case 0x0d: FaultSource = "Permission fault on Section";\r
+ break;\r
+ case 0x0e: FaultSource = "External abort on translation, second level";\r
+ break;\r
+ case 0x0f: FaultSource = "Permission fault on Page";\r
+ break;\r
+ case 0x16: FaultSource = "Imprecise External Abort";\r
+ break;\r
+ default: FaultSource = "No function";\r
+ break;\r
+ }\r
\r
return FaultSource;\r
}\r
\r
-STATIC CHAR8 *gExceptionTypeString[] = {\r
+STATIC CHAR8 *gExceptionTypeString[] = {\r
"Reset",\r
"Undefined OpCode",\r
"SVC",\r
**/\r
VOID\r
DefaultExceptionHandler (\r
- IN EFI_EXCEPTION_TYPE ExceptionType,\r
- IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
+ IN EFI_EXCEPTION_TYPE ExceptionType,\r
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
)\r
{\r
- CHAR8 Buffer[100];\r
- UINTN CharCount;\r
- UINT32 DfsrStatus;\r
- UINT32 IfsrStatus;\r
- BOOLEAN DfsrWrite;\r
- UINT32 PcAdjust;\r
+ CHAR8 Buffer[100];\r
+ UINTN CharCount;\r
+ UINT32 DfsrStatus;\r
+ UINT32 IfsrStatus;\r
+ BOOLEAN DfsrWrite;\r
+ UINT32 PcAdjust;\r
\r
PcAdjust = 0;\r
\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"\n%a Exception PC at 0x%08x CPSR 0x%08x ",\r
- gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC, SystemContext.SystemContextArm->CPSR);\r
+ CharCount = AsciiSPrint (\r
+ Buffer,\r
+ sizeof (Buffer),\r
+ "\n%a Exception PC at 0x%08x CPSR 0x%08x ",\r
+ gExceptionTypeString[ExceptionType],\r
+ SystemContext.SystemContextArm->PC,\r
+ SystemContext.SystemContextArm->CPSR\r
+ );\r
SerialPortWrite ((UINT8 *)Buffer, CharCount);\r
if (gST->ConOut != NULL) {\r
AsciiPrint (Buffer);\r
}\r
\r
DEBUG_CODE_BEGIN ();\r
- CHAR8 *Pdb;\r
- UINT32 ImageBase;\r
- UINT32 PeCoffSizeOfHeader;\r
- UINT32 Offset;\r
- CHAR8 CpsrStr[CPSR_STRING_SIZE]; // char per bit. Lower 5-bits are mode\r
+ CHAR8 *Pdb;\r
+ UINT32 ImageBase;\r
+ UINT32 PeCoffSizeOfHeader;\r
+ UINT32 Offset;\r
+ CHAR8 CpsrStr[CPSR_STRING_SIZE]; // char per bit. Lower 5-bits are mode\r
// that is a 3 char string\r
- CHAR8 Buffer[80];\r
- UINT8 *DisAsm;\r
- UINT32 ItBlock;\r
-\r
- CpsrString (SystemContext.SystemContextArm->CPSR, CpsrStr);\r
- DEBUG ((DEBUG_ERROR, "%a\n", CpsrStr));\r
-\r
- Pdb = GetImageName (SystemContext.SystemContextArm->PC, &ImageBase, &PeCoffSizeOfHeader);\r
- Offset = SystemContext.SystemContextArm->PC - ImageBase;\r
- if (Pdb != NULL) {\r
- DEBUG ((DEBUG_ERROR, "%a\n", Pdb));\r
-\r
- //\r
- // A PE/COFF image loads its headers into memory so the headers are\r
- // included in the linked addresses. ELF and Mach-O images do not\r
- // include the headers so the first byte of the image is usually\r
- // text (code). If you look at link maps from ELF or Mach-O images\r
- // you need to subtract out the size of the PE/COFF header to get\r
- // get the offset that matches the link map.\r
- //\r
- DEBUG ((DEBUG_ERROR, "loaded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));\r
-\r
- // If we come from an image it is safe to show the instruction. We know it should not fault\r
- DisAsm = (UINT8 *)(UINTN)SystemContext.SystemContextArm->PC;\r
- ItBlock = 0;\r
- DisassembleInstruction (&DisAsm, (SystemContext.SystemContextArm->CPSR & BIT5) == BIT5, TRUE, &ItBlock, Buffer, sizeof (Buffer));\r
- DEBUG ((DEBUG_ERROR, "\n%a", Buffer));\r
-\r
- switch (ExceptionType) {\r
+ CHAR8 Buffer[80];\r
+ UINT8 *DisAsm;\r
+ UINT32 ItBlock;\r
+\r
+ CpsrString (SystemContext.SystemContextArm->CPSR, CpsrStr);\r
+ DEBUG ((DEBUG_ERROR, "%a\n", CpsrStr));\r
+\r
+ Pdb = GetImageName (SystemContext.SystemContextArm->PC, &ImageBase, &PeCoffSizeOfHeader);\r
+ Offset = SystemContext.SystemContextArm->PC - ImageBase;\r
+ if (Pdb != NULL) {\r
+ DEBUG ((DEBUG_ERROR, "%a\n", Pdb));\r
+\r
+ //\r
+ // A PE/COFF image loads its headers into memory so the headers are\r
+ // included in the linked addresses. ELF and Mach-O images do not\r
+ // include the headers so the first byte of the image is usually\r
+ // text (code). If you look at link maps from ELF or Mach-O images\r
+ // you need to subtract out the size of the PE/COFF header to get\r
+ // get the offset that matches the link map.\r
+ //\r
+ DEBUG ((DEBUG_ERROR, "loaded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));\r
+\r
+ // If we come from an image it is safe to show the instruction. We know it should not fault\r
+ DisAsm = (UINT8 *)(UINTN)SystemContext.SystemContextArm->PC;\r
+ ItBlock = 0;\r
+ DisassembleInstruction (&DisAsm, (SystemContext.SystemContextArm->CPSR & BIT5) == BIT5, TRUE, &ItBlock, Buffer, sizeof (Buffer));\r
+ DEBUG ((DEBUG_ERROR, "\n%a", Buffer));\r
+\r
+ switch (ExceptionType) {\r
case EXCEPT_ARM_UNDEFINED_INSTRUCTION:\r
case EXCEPT_ARM_SOFTWARE_INTERRUPT:\r
case EXCEPT_ARM_PREFETCH_ABORT:\r
\r
default:\r
break;\r
- }\r
-\r
}\r
+ }\r
+\r
DEBUG_CODE_END ();\r
DEBUG ((DEBUG_ERROR, "\n R0 0x%08x R1 0x%08x R2 0x%08x R3 0x%08x\n", SystemContext.SystemContextArm->R0, SystemContext.SystemContextArm->R1, SystemContext.SystemContextArm->R2, SystemContext.SystemContextArm->R3));\r
DEBUG ((DEBUG_ERROR, " R4 0x%08x R5 0x%08x R6 0x%08x R7 0x%08x\n", SystemContext.SystemContextArm->R4, SystemContext.SystemContextArm->R5, SystemContext.SystemContextArm->R6, SystemContext.SystemContextArm->R7));\r
\r
// Bit10 is Status[4] Bit3:0 is Status[3:0]\r
DfsrStatus = (SystemContext.SystemContextArm->DFSR & 0xf) | ((SystemContext.SystemContextArm->DFSR >> 6) & 0x10);\r
- DfsrWrite = (SystemContext.SystemContextArm->DFSR & BIT11) != 0;\r
+ DfsrWrite = (SystemContext.SystemContextArm->DFSR & BIT11) != 0;\r
if (DfsrStatus != 0x00) {\r
DEBUG ((DEBUG_ERROR, " %a: %a 0x%08x\n", FaultStatusToString (DfsrStatus), DfsrWrite ? "write to" : "read from", SystemContext.SystemContextArm->DFAR));\r
}\r
OUT UINTN *PeCoffSizeOfHeaders\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *DebugTableHeader;\r
- EFI_DEBUG_IMAGE_INFO *DebugTable;\r
- UINTN Entry;\r
- CHAR8 *Address;\r
+ EFI_STATUS Status;\r
+ EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *DebugTableHeader;\r
+ EFI_DEBUG_IMAGE_INFO *DebugTable;\r
+ UINTN Entry;\r
+ CHAR8 *Address;\r
\r
Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&DebugTableHeader);\r
if (EFI_ERROR (Status)) {\r
for (Entry = 0; Entry < DebugTableHeader->TableSize; Entry++, DebugTable++) {\r
if (DebugTable->NormalImage != NULL) {\r
if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) &&\r
- (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL)) {\r
+ (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL))\r
+ {\r
if ((Address >= (CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase) &&\r
- (Address <= ((CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase + DebugTable->NormalImage->LoadedImageProtocolInstance->ImageSize))) {\r
- *ImageBase = (UINTN)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;\r
+ (Address <= ((CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase + DebugTable->NormalImage->LoadedImageProtocolInstance->ImageSize)))\r
+ {\r
+ *ImageBase = (UINTN)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;\r
*PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)*ImageBase);\r
return PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase);\r
}\r
\r
return NULL;\r
}\r
-\r
STATIC\r
VOID\r
PlatformRegisterFvBootOption (\r
- CONST EFI_GUID *FileGuid,\r
- CHAR16 *Description,\r
- UINT32 Attributes\r
+ CONST EFI_GUID *FileGuid,\r
+ CHAR16 *Description,\r
+ UINT32 Attributes\r
)\r
{\r
- EFI_STATUS Status;\r
- INTN OptionIndex;\r
- EFI_BOOT_MANAGER_LOAD_OPTION NewOption;\r
- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;\r
- UINTN BootOptionCount;\r
- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;\r
- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_STATUS Status;\r
+ INTN OptionIndex;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;\r
+ UINTN BootOptionCount;\r
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;\r
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
\r
Status = gBS->HandleProtocol (\r
gImageHandle,\r
Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN);\r
ASSERT_EFI_ERROR (Status);\r
}\r
+\r
EfiBootManagerFreeLoadOption (&NewOption);\r
EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);\r
}\r
VOID\r
)\r
{\r
- EFI_GUID LinuxBootFileGuid;\r
+ EFI_GUID LinuxBootFileGuid;\r
\r
CopyGuid (&LinuxBootFileGuid, PcdGetPtr (PcdLinuxBootFileGuid));\r
\r
VOID\r
EFIAPI\r
PlatformBootManagerWaitCallback (\r
- UINT16 TimeoutRemain\r
+ UINT16 TimeoutRemain\r
)\r
{\r
return;\r
#include <OpteeSmc.h>\r
#include <Uefi.h>\r
\r
-STATIC OPTEE_SHARED_MEMORY_INFORMATION OpteeSharedMemoryInformation = { 0 };\r
+STATIC OPTEE_SHARED_MEMORY_INFORMATION OpteeSharedMemoryInformation = { 0 };\r
\r
/**\r
Check for OP-TEE presence.\r
VOID\r
)\r
{\r
- ARM_SMC_ARGS ArmSmcArgs;\r
+ ARM_SMC_ARGS ArmSmcArgs;\r
\r
ZeroMem (&ArmSmcArgs, sizeof (ARM_SMC_ARGS));\r
// Send a Trusted OS Calls UID command\r
if ((ArmSmcArgs.Arg0 == OPTEE_OS_UID0) &&\r
(ArmSmcArgs.Arg1 == OPTEE_OS_UID1) &&\r
(ArmSmcArgs.Arg2 == OPTEE_OS_UID2) &&\r
- (ArmSmcArgs.Arg3 == OPTEE_OS_UID3)) {\r
+ (ArmSmcArgs.Arg3 == OPTEE_OS_UID3))\r
+ {\r
return TRUE;\r
} else {\r
return FALSE;\r
VOID\r
)\r
{\r
- ARM_SMC_ARGS ArmSmcArgs;\r
- EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
- EFI_PHYSICAL_ADDRESS Start;\r
- EFI_PHYSICAL_ADDRESS End;\r
- EFI_STATUS Status;\r
- UINTN Size;\r
+ ARM_SMC_ARGS ArmSmcArgs;\r
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
+ EFI_PHYSICAL_ADDRESS Start;\r
+ EFI_PHYSICAL_ADDRESS End;\r
+ EFI_STATUS Status;\r
+ UINTN Size;\r
\r
ZeroMem (&ArmSmcArgs, sizeof (ARM_SMC_ARGS));\r
ArmSmcArgs.Arg0 = OPTEE_SMC_GET_SHARED_MEMORY_CONFIG;\r
return EFI_UNSUPPORTED;\r
}\r
\r
- Start = (ArmSmcArgs.Arg1 + SIZE_4KB - 1) & ~(SIZE_4KB - 1);\r
- End = (ArmSmcArgs.Arg1 + ArmSmcArgs.Arg2) & ~(SIZE_4KB - 1);\r
+ Start = (ArmSmcArgs.Arg1 + SIZE_4KB - 1) & ~(SIZE_4KB - 1);\r
+ End = (ArmSmcArgs.Arg1 + ArmSmcArgs.Arg2) & ~(SIZE_4KB - 1);\r
PhysicalAddress = Start;\r
- Size = End - Start;\r
+ Size = End - Start;\r
\r
if (Size < SIZE_4KB) {\r
DEBUG ((DEBUG_WARN, "OP-TEE shared memory too small\n"));\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if (!IsOpteePresent ()) {\r
DEBUG ((DEBUG_WARN, "OP-TEE not present\n"));\r
STATIC\r
BOOLEAN\r
IsOpteeSmcReturnRpc (\r
- UINT32 Return\r
+ UINT32 Return\r
)\r
{\r
return (Return != OPTEE_SMC_RETURN_UNKNOWN_FUNCTION) &&\r
STATIC\r
UINT32\r
OpteeCallWithArg (\r
- IN UINT64 PhysicalArg\r
+ IN UINT64 PhysicalArg\r
)\r
{\r
- ARM_SMC_ARGS ArmSmcArgs;\r
+ ARM_SMC_ARGS ArmSmcArgs;\r
\r
ZeroMem (&ArmSmcArgs, sizeof (ARM_SMC_ARGS));\r
ArmSmcArgs.Arg0 = OPTEE_SMC_CALL_WITH_ARG;\r
\r
if (IsOpteeSmcReturnRpc (ArmSmcArgs.Arg0)) {\r
switch (ArmSmcArgs.Arg0) {\r
- case OPTEE_SMC_RETURN_RPC_FOREIGN_INTERRUPT:\r
- //\r
- // A foreign interrupt was raised while secure world was\r
- // executing, since they are handled in UEFI a dummy RPC is\r
- // performed to let UEFI take the interrupt through the normal\r
- // vector.\r
- //\r
- break;\r
-\r
- default:\r
- // Do nothing in case RPC is not implemented.\r
- break;\r
+ case OPTEE_SMC_RETURN_RPC_FOREIGN_INTERRUPT:\r
+ //\r
+ // A foreign interrupt was raised while secure world was\r
+ // executing, since they are handled in UEFI a dummy RPC is\r
+ // performed to let UEFI take the interrupt through the normal\r
+ // vector.\r
+ //\r
+ break;\r
+\r
+ default:\r
+ // Do nothing in case RPC is not implemented.\r
+ break;\r
}\r
\r
ArmSmcArgs.Arg0 = OPTEE_SMC_RETURN_FROM_RPC;\r
STATIC\r
VOID\r
EfiGuidToRfc4122Uuid (\r
- OUT RFC4122_UUID *Rfc4122Uuid,\r
- IN EFI_GUID *Guid\r
+ OUT RFC4122_UUID *Rfc4122Uuid,\r
+ IN EFI_GUID *Guid\r
)\r
{\r
Rfc4122Uuid->Data1 = SwapBytes32 (Guid->Data1);\r
EFI_STATUS\r
EFIAPI\r
OpteeOpenSession (\r
- IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg\r
+ IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg\r
)\r
{\r
- OPTEE_MESSAGE_ARG *MessageArg;\r
+ OPTEE_MESSAGE_ARG *MessageArg;\r
\r
MessageArg = NULL;\r
\r
MessageArg->NumParams = 2;\r
\r
if (OpteeCallWithArg ((UINTN)MessageArg) != 0) {\r
- MessageArg->Return = OPTEE_ERROR_COMMUNICATION;\r
+ MessageArg->Return = OPTEE_ERROR_COMMUNICATION;\r
MessageArg->ReturnOrigin = OPTEE_ORIGIN_COMMUNICATION;\r
}\r
\r
- OpenSessionArg->Session = MessageArg->Session;\r
- OpenSessionArg->Return = MessageArg->Return;\r
+ OpenSessionArg->Session = MessageArg->Session;\r
+ OpenSessionArg->Return = MessageArg->Return;\r
OpenSessionArg->ReturnOrigin = MessageArg->ReturnOrigin;\r
\r
return EFI_SUCCESS;\r
EFI_STATUS\r
EFIAPI\r
OpteeCloseSession (\r
- IN UINT32 Session\r
+ IN UINT32 Session\r
)\r
{\r
- OPTEE_MESSAGE_ARG *MessageArg;\r
+ OPTEE_MESSAGE_ARG *MessageArg;\r
\r
MessageArg = NULL;\r
\r
STATIC\r
EFI_STATUS\r
OpteeToMessageParam (\r
- OUT OPTEE_MESSAGE_PARAM *MessageParams,\r
- IN UINT32 NumParams,\r
- IN OPTEE_MESSAGE_PARAM *InParams\r
+ OUT OPTEE_MESSAGE_PARAM *MessageParams,\r
+ IN UINT32 NumParams,\r
+ IN OPTEE_MESSAGE_PARAM *InParams\r
)\r
{\r
- UINT32 Idx;\r
- UINTN ParamSharedMemoryAddress;\r
- UINTN SharedMemorySize;\r
- UINTN Size;\r
+ UINT32 Idx;\r
+ UINTN ParamSharedMemoryAddress;\r
+ UINTN SharedMemorySize;\r
+ UINTN Size;\r
\r
Size = (sizeof (OPTEE_MESSAGE_ARG) + sizeof (UINT64) - 1) &\r
- ~(sizeof (UINT64) - 1);\r
+ ~(sizeof (UINT64) - 1);\r
ParamSharedMemoryAddress = OpteeSharedMemoryInformation.Base + Size;\r
- SharedMemorySize = OpteeSharedMemoryInformation.Size - Size;\r
+ SharedMemorySize = OpteeSharedMemoryInformation.Size - Size;\r
\r
for (Idx = 0; Idx < NumParams; Idx++) {\r
- CONST OPTEE_MESSAGE_PARAM *InParam;\r
- OPTEE_MESSAGE_PARAM *MessageParam;\r
- UINT32 Attribute;\r
+ CONST OPTEE_MESSAGE_PARAM *InParam;\r
+ OPTEE_MESSAGE_PARAM *MessageParam;\r
+ UINT32 Attribute;\r
\r
- InParam = InParams + Idx;\r
+ InParam = InParams + Idx;\r
MessageParam = MessageParams + Idx;\r
- Attribute = InParam->Attribute & OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK;\r
+ Attribute = InParam->Attribute & OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK;\r
\r
switch (Attribute) {\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE:\r
- MessageParam->Attribute = OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE;\r
- ZeroMem (&MessageParam->Union, sizeof (MessageParam->Union));\r
- break;\r
-\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT:\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT:\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT:\r
- MessageParam->Attribute = Attribute;\r
- MessageParam->Union.Value.A = InParam->Union.Value.A;\r
- MessageParam->Union.Value.B = InParam->Union.Value.B;\r
- MessageParam->Union.Value.C = InParam->Union.Value.C;\r
- break;\r
-\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT:\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT:\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT:\r
- MessageParam->Attribute = Attribute;\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE:\r
+ MessageParam->Attribute = OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE;\r
+ ZeroMem (&MessageParam->Union, sizeof (MessageParam->Union));\r
+ break;\r
\r
- if (InParam->Union.Memory.Size > SharedMemorySize) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT:\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT:\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT:\r
+ MessageParam->Attribute = Attribute;\r
+ MessageParam->Union.Value.A = InParam->Union.Value.A;\r
+ MessageParam->Union.Value.B = InParam->Union.Value.B;\r
+ MessageParam->Union.Value.C = InParam->Union.Value.C;\r
+ break;\r
\r
- CopyMem (\r
- (VOID *)ParamSharedMemoryAddress,\r
- (VOID *)(UINTN)InParam->Union.Memory.BufferAddress,\r
- InParam->Union.Memory.Size\r
- );\r
- MessageParam->Union.Memory.BufferAddress = (UINT64)ParamSharedMemoryAddress;\r
- MessageParam->Union.Memory.Size = InParam->Union.Memory.Size;\r
-\r
- Size = (InParam->Union.Memory.Size + sizeof (UINT64) - 1) &\r
- ~(sizeof (UINT64) - 1);\r
- ParamSharedMemoryAddress += Size;\r
- SharedMemorySize -= Size;\r
- break;\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT:\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT:\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT:\r
+ MessageParam->Attribute = Attribute;\r
+\r
+ if (InParam->Union.Memory.Size > SharedMemorySize) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ CopyMem (\r
+ (VOID *)ParamSharedMemoryAddress,\r
+ (VOID *)(UINTN)InParam->Union.Memory.BufferAddress,\r
+ InParam->Union.Memory.Size\r
+ );\r
+ MessageParam->Union.Memory.BufferAddress = (UINT64)ParamSharedMemoryAddress;\r
+ MessageParam->Union.Memory.Size = InParam->Union.Memory.Size;\r
+\r
+ Size = (InParam->Union.Memory.Size + sizeof (UINT64) - 1) &\r
+ ~(sizeof (UINT64) - 1);\r
+ ParamSharedMemoryAddress += Size;\r
+ SharedMemorySize -= Size;\r
+ break;\r
\r
- default:\r
- return EFI_INVALID_PARAMETER;\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
}\r
}\r
\r
STATIC\r
EFI_STATUS\r
OpteeFromMessageParam (\r
- OUT OPTEE_MESSAGE_PARAM *OutParams,\r
- IN UINT32 NumParams,\r
- IN OPTEE_MESSAGE_PARAM *MessageParams\r
+ OUT OPTEE_MESSAGE_PARAM *OutParams,\r
+ IN UINT32 NumParams,\r
+ IN OPTEE_MESSAGE_PARAM *MessageParams\r
)\r
{\r
- UINT32 Idx;\r
+ UINT32 Idx;\r
\r
for (Idx = 0; Idx < NumParams; Idx++) {\r
- OPTEE_MESSAGE_PARAM *OutParam;\r
- CONST OPTEE_MESSAGE_PARAM *MessageParam;\r
- UINT32 Attribute;\r
+ OPTEE_MESSAGE_PARAM *OutParam;\r
+ CONST OPTEE_MESSAGE_PARAM *MessageParam;\r
+ UINT32 Attribute;\r
\r
- OutParam = OutParams + Idx;\r
+ OutParam = OutParams + Idx;\r
MessageParam = MessageParams + Idx;\r
- Attribute = MessageParam->Attribute & OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK;\r
+ Attribute = MessageParam->Attribute & OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK;\r
\r
switch (Attribute) {\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE:\r
- OutParam->Attribute = OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE;\r
- ZeroMem (&OutParam->Union, sizeof (OutParam->Union));\r
- break;\r
-\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT:\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT:\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT:\r
- OutParam->Attribute = Attribute;\r
- OutParam->Union.Value.A = MessageParam->Union.Value.A;\r
- OutParam->Union.Value.B = MessageParam->Union.Value.B;\r
- OutParam->Union.Value.C = MessageParam->Union.Value.C;\r
- break;\r
-\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT:\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT:\r
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT:\r
- OutParam->Attribute = Attribute;\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE:\r
+ OutParam->Attribute = OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE;\r
+ ZeroMem (&OutParam->Union, sizeof (OutParam->Union));\r
+ break;\r
\r
- if (MessageParam->Union.Memory.Size > OutParam->Union.Memory.Size) {\r
- return EFI_BAD_BUFFER_SIZE;\r
- }\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT:\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT:\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT:\r
+ OutParam->Attribute = Attribute;\r
+ OutParam->Union.Value.A = MessageParam->Union.Value.A;\r
+ OutParam->Union.Value.B = MessageParam->Union.Value.B;\r
+ OutParam->Union.Value.C = MessageParam->Union.Value.C;\r
+ break;\r
\r
- CopyMem (\r
- (VOID *)(UINTN)OutParam->Union.Memory.BufferAddress,\r
- (VOID *)(UINTN)MessageParam->Union.Memory.BufferAddress,\r
- MessageParam->Union.Memory.Size\r
- );\r
- OutParam->Union.Memory.Size = MessageParam->Union.Memory.Size;\r
- break;\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT:\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT:\r
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT:\r
+ OutParam->Attribute = Attribute;\r
+\r
+ if (MessageParam->Union.Memory.Size > OutParam->Union.Memory.Size) {\r
+ return EFI_BAD_BUFFER_SIZE;\r
+ }\r
+\r
+ CopyMem (\r
+ (VOID *)(UINTN)OutParam->Union.Memory.BufferAddress,\r
+ (VOID *)(UINTN)MessageParam->Union.Memory.BufferAddress,\r
+ MessageParam->Union.Memory.Size\r
+ );\r
+ OutParam->Union.Memory.Size = MessageParam->Union.Memory.Size;\r
+ break;\r
\r
- default:\r
- return EFI_INVALID_PARAMETER;\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
}\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
OpteeInvokeFunction (\r
- IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg\r
+ IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg\r
)\r
{\r
- EFI_STATUS Status;\r
- OPTEE_MESSAGE_ARG *MessageArg;\r
+ EFI_STATUS Status;\r
+ OPTEE_MESSAGE_ARG *MessageArg;\r
\r
MessageArg = NULL;\r
\r
MessageArg = (OPTEE_MESSAGE_ARG *)OpteeSharedMemoryInformation.Base;\r
ZeroMem (MessageArg, sizeof (OPTEE_MESSAGE_ARG));\r
\r
- MessageArg->Command = OPTEE_MESSAGE_COMMAND_INVOKE_FUNCTION;\r
+ MessageArg->Command = OPTEE_MESSAGE_COMMAND_INVOKE_FUNCTION;\r
MessageArg->Function = InvokeFunctionArg->Function;\r
- MessageArg->Session = InvokeFunctionArg->Session;\r
+ MessageArg->Session = InvokeFunctionArg->Session;\r
\r
Status = OpteeToMessageParam (\r
MessageArg->Params,\r
MessageArg->NumParams = OPTEE_MAX_CALL_PARAMS;\r
\r
if (OpteeCallWithArg ((UINTN)MessageArg) != 0) {\r
- MessageArg->Return = OPTEE_ERROR_COMMUNICATION;\r
+ MessageArg->Return = OPTEE_ERROR_COMMUNICATION;\r
MessageArg->ReturnOrigin = OPTEE_ORIGIN_COMMUNICATION;\r
}\r
\r
InvokeFunctionArg->Params,\r
OPTEE_MAX_CALL_PARAMS,\r
MessageArg->Params\r
- ) != 0) {\r
- MessageArg->Return = OPTEE_ERROR_COMMUNICATION;\r
+ ) != 0)\r
+ {\r
+ MessageArg->Return = OPTEE_ERROR_COMMUNICATION;\r
MessageArg->ReturnOrigin = OPTEE_ORIGIN_COMMUNICATION;\r
}\r
\r
- InvokeFunctionArg->Return = MessageArg->Return;\r
+ InvokeFunctionArg->Return = MessageArg->Return;\r
InvokeFunctionArg->ReturnOrigin = MessageArg->ReturnOrigin;\r
\r
return EFI_SUCCESS;\r
#define OPTEE_SMC_H_\r
\r
/* Returned in Arg0 only from Trusted OS functions */\r
-#define OPTEE_SMC_RETURN_OK 0x0\r
+#define OPTEE_SMC_RETURN_OK 0x0\r
\r
-#define OPTEE_SMC_RETURN_FROM_RPC 0x32000003\r
-#define OPTEE_SMC_CALL_WITH_ARG 0x32000004\r
-#define OPTEE_SMC_GET_SHARED_MEMORY_CONFIG 0xb2000007\r
+#define OPTEE_SMC_RETURN_FROM_RPC 0x32000003\r
+#define OPTEE_SMC_CALL_WITH_ARG 0x32000004\r
+#define OPTEE_SMC_GET_SHARED_MEMORY_CONFIG 0xb2000007\r
\r
-#define OPTEE_SMC_SHARED_MEMORY_CACHED 1\r
+#define OPTEE_SMC_SHARED_MEMORY_CACHED 1\r
\r
#define OPTEE_SMC_RETURN_UNKNOWN_FUNCTION 0xffffffff\r
#define OPTEE_SMC_RETURN_RPC_PREFIX_MASK 0xffff0000\r
#define OPTEE_SMC_RETURN_RPC_PREFIX 0xffff0000\r
#define OPTEE_SMC_RETURN_RPC_FOREIGN_INTERRUPT 0xffff0004\r
\r
-#define OPTEE_MESSAGE_COMMAND_OPEN_SESSION 0\r
-#define OPTEE_MESSAGE_COMMAND_INVOKE_FUNCTION 1\r
-#define OPTEE_MESSAGE_COMMAND_CLOSE_SESSION 2\r
+#define OPTEE_MESSAGE_COMMAND_OPEN_SESSION 0\r
+#define OPTEE_MESSAGE_COMMAND_INVOKE_FUNCTION 1\r
+#define OPTEE_MESSAGE_COMMAND_CLOSE_SESSION 2\r
\r
-#define OPTEE_MESSAGE_ATTRIBUTE_META 0x100\r
+#define OPTEE_MESSAGE_ATTRIBUTE_META 0x100\r
\r
-#define OPTEE_LOGIN_PUBLIC 0x0\r
+#define OPTEE_LOGIN_PUBLIC 0x0\r
\r
typedef struct {\r
UINTN Base;\r
// UUID struct compliant with RFC4122 (network byte order).\r
//\r
typedef struct {\r
- UINT32 Data1;\r
- UINT16 Data2;\r
- UINT16 Data3;\r
- UINT8 Data4[8];\r
+ UINT32 Data1;\r
+ UINT16 Data2;\r
+ UINT16 Data3;\r
+ UINT8 Data4[8];\r
} RFC4122_UUID;\r
\r
#endif // OPTEE_SMC_H_\r
VOID\r
EFIAPI\r
SetPeiServicesTablePointer (\r
- IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer\r
+ IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer\r
)\r
{\r
- ArmWriteTpidrurw((UINTN)PeiServicesTablePointer);\r
+ ArmWriteTpidrurw ((UINTN)PeiServicesTablePointer);\r
}\r
\r
/**\r
VOID\r
)\r
{\r
- return (CONST EFI_PEI_SERVICES **)ArmReadTpidrurw();\r
+ return (CONST EFI_PEI_SERVICES **)ArmReadTpidrurw ();\r
}\r
\r
/**\r
**/\r
VOID\r
EFIAPI\r
-MigratePeiServicesTablePointer(\r
-VOID\r
-)\r
+MigratePeiServicesTablePointer (\r
+ VOID\r
+ )\r
{\r
return;\r
}\r
\r
#include "PlatformBm.h"\r
\r
-#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }\r
+#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }\r
\r
#pragma pack (1)\r
typedef struct {\r
- VENDOR_DEVICE_PATH SerialDxe;\r
- UART_DEVICE_PATH Uart;\r
- VENDOR_DEFINED_DEVICE_PATH TermType;\r
- EFI_DEVICE_PATH_PROTOCOL End;\r
+ VENDOR_DEVICE_PATH SerialDxe;\r
+ UART_DEVICE_PATH Uart;\r
+ VENDOR_DEFINED_DEVICE_PATH TermType;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
} PLATFORM_SERIAL_CONSOLE;\r
#pragma pack ()\r
\r
-STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {\r
+STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {\r
//\r
// VENDOR_DEVICE_PATH SerialDxe\r
//\r
{\r
- { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },\r
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },\r
EDKII_SERIAL_PORT_LIB_VENDOR_GUID\r
},\r
\r
// UART_DEVICE_PATH Uart\r
//\r
{\r
- { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },\r
+ { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },\r
0, // Reserved\r
FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate\r
FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits\r
}\r
};\r
\r
-\r
#pragma pack (1)\r
typedef struct {\r
- USB_CLASS_DEVICE_PATH Keyboard;\r
- EFI_DEVICE_PATH_PROTOCOL End;\r
+ USB_CLASS_DEVICE_PATH Keyboard;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
} PLATFORM_USB_KEYBOARD;\r
#pragma pack ()\r
\r
-STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {\r
+STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {\r
//\r
// USB_CLASS_DEVICE_PATH Keyboard\r
//\r
}\r
};\r
\r
-\r
/**\r
Check if the handle satisfies a particular condition.\r
\r
**/\r
typedef\r
BOOLEAN\r
-(EFIAPI *FILTER_FUNCTION) (\r
+(EFIAPI *FILTER_FUNCTION)(\r
IN EFI_HANDLE Handle,\r
IN CONST CHAR16 *ReportText\r
);\r
\r
-\r
/**\r
Process a handle.\r
\r
**/\r
typedef\r
VOID\r
-(EFIAPI *CALLBACK_FUNCTION) (\r
+(EFIAPI *CALLBACK_FUNCTION)(\r
IN EFI_HANDLE Handle,\r
IN CONST CHAR16 *ReportText\r
);\r
STATIC\r
VOID\r
FilterAndProcess (\r
- IN EFI_GUID *ProtocolGuid,\r
- IN FILTER_FUNCTION Filter OPTIONAL,\r
- IN CALLBACK_FUNCTION Process\r
+ IN EFI_GUID *ProtocolGuid,\r
+ IN FILTER_FUNCTION Filter OPTIONAL,\r
+ IN CALLBACK_FUNCTION Process\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_HANDLE *Handles;\r
- UINTN NoHandles;\r
- UINTN Idx;\r
-\r
- Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid,\r
- NULL /* SearchKey */, &NoHandles, &Handles);\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE *Handles;\r
+ UINTN NoHandles;\r
+ UINTN Idx;\r
+\r
+ Status = gBS->LocateHandleBuffer (\r
+ ByProtocol,\r
+ ProtocolGuid,\r
+ NULL /* SearchKey */,\r
+ &NoHandles,\r
+ &Handles\r
+ );\r
if (EFI_ERROR (Status)) {\r
//\r
// This is not an error, just an informative condition.\r
//\r
- DEBUG ((DEBUG_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid,\r
- Status));\r
+ DEBUG ((\r
+ DEBUG_VERBOSE,\r
+ "%a: %g: %r\n",\r
+ __FUNCTION__,\r
+ ProtocolGuid,\r
+ Status\r
+ ));\r
return;\r
}\r
\r
ASSERT (NoHandles > 0);\r
for (Idx = 0; Idx < NoHandles; ++Idx) {\r
- CHAR16 *DevicePathText;\r
- STATIC CHAR16 Fallback[] = L"<device path unavailable>";\r
+ CHAR16 *DevicePathText;\r
+ STATIC CHAR16 Fallback[] = L"<device path unavailable>";\r
\r
//\r
// The ConvertDevicePathToText() function handles NULL input transparently.\r
DevicePathText = Fallback;\r
}\r
\r
- if (Filter == NULL || Filter (Handles[Idx], DevicePathText)) {\r
+ if ((Filter == NULL) || Filter (Handles[Idx], DevicePathText)) {\r
Process (Handles[Idx], DevicePathText);\r
}\r
\r
FreePool (DevicePathText);\r
}\r
}\r
+\r
gBS->FreePool (Handles);\r
}\r
\r
-\r
/**\r
This FILTER_FUNCTION checks if a handle corresponds to a PCI display device.\r
**/\r
BOOLEAN\r
EFIAPI\r
IsPciDisplay (\r
- IN EFI_HANDLE Handle,\r
- IN CONST CHAR16 *ReportText\r
+ IN EFI_HANDLE Handle,\r
+ IN CONST CHAR16 *ReportText\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- PCI_TYPE00 Pci;\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ PCI_TYPE00 Pci;\r
\r
- Status = gBS->HandleProtocol (Handle, &gEfiPciIoProtocolGuid,\r
- (VOID**)&PciIo);\r
+ Status = gBS->HandleProtocol (\r
+ Handle,\r
+ &gEfiPciIoProtocolGuid,\r
+ (VOID **)&PciIo\r
+ );\r
if (EFI_ERROR (Status)) {\r
//\r
// This is not an error worth reporting.\r
return FALSE;\r
}\r
\r
- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0 /* Offset */,\r
- sizeof Pci / sizeof (UINT32), &Pci);\r
+ Status = PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ 0 /* Offset */,\r
+ sizeof Pci / sizeof (UINT32),\r
+ &Pci\r
+ );\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status));\r
return FALSE;\r
return IS_PCI_DISPLAY (&Pci);\r
}\r
\r
-\r
/**\r
This FILTER_FUNCTION checks if a handle corresponds to a non-discoverable\r
USB host controller.\r
BOOLEAN\r
EFIAPI\r
IsUsbHost (\r
- IN EFI_HANDLE Handle,\r
- IN CONST CHAR16 *ReportText\r
+ IN EFI_HANDLE Handle,\r
+ IN CONST CHAR16 *ReportText\r
)\r
{\r
- NON_DISCOVERABLE_DEVICE *Device;\r
- EFI_STATUS Status;\r
+ NON_DISCOVERABLE_DEVICE *Device;\r
+ EFI_STATUS Status;\r
\r
- Status = gBS->HandleProtocol (Handle,\r
+ Status = gBS->HandleProtocol (\r
+ Handle,\r
&gEdkiiNonDiscoverableDeviceProtocolGuid,\r
- (VOID **)&Device);\r
+ (VOID **)&Device\r
+ );\r
if (EFI_ERROR (Status)) {\r
return FALSE;\r
}\r
\r
if (CompareGuid (Device->Type, &gEdkiiNonDiscoverableUhciDeviceGuid) ||\r
CompareGuid (Device->Type, &gEdkiiNonDiscoverableEhciDeviceGuid) ||\r
- CompareGuid (Device->Type, &gEdkiiNonDiscoverableXhciDeviceGuid)) {\r
+ CompareGuid (Device->Type, &gEdkiiNonDiscoverableXhciDeviceGuid))\r
+ {\r
return TRUE;\r
}\r
+\r
return FALSE;\r
}\r
\r
-\r
/**\r
This CALLBACK_FUNCTION attempts to connect a handle non-recursively, asking\r
the matching driver to produce all first-level child handles.\r
VOID\r
EFIAPI\r
Connect (\r
- IN EFI_HANDLE Handle,\r
- IN CONST CHAR16 *ReportText\r
+ IN EFI_HANDLE Handle,\r
+ IN CONST CHAR16 *ReportText\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
Status = gBS->ConnectController (\r
Handle, // ControllerHandle\r
NULL, // RemainingDevicePath -- produce all children\r
FALSE // Recursive\r
);\r
- DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, "%a: %s: %r\n",\r
- __FUNCTION__, ReportText, Status));\r
+ DEBUG ((\r
+ EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,\r
+ "%a: %s: %r\n",\r
+ __FUNCTION__,\r
+ ReportText,\r
+ Status\r
+ ));\r
}\r
\r
-\r
/**\r
This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the\r
handle, and adds it to ConOut and ErrOut.\r
VOID\r
EFIAPI\r
AddOutput (\r
- IN EFI_HANDLE Handle,\r
- IN CONST CHAR16 *ReportText\r
+ IN EFI_HANDLE Handle,\r
+ IN CONST CHAR16 *ReportText\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
\r
DevicePath = DevicePathFromHandle (Handle);\r
if (DevicePath == NULL) {\r
- DEBUG ((DEBUG_ERROR, "%a: %s: handle %p: device path not found\n",\r
- __FUNCTION__, ReportText, Handle));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: %s: handle %p: device path not found\n",\r
+ __FUNCTION__,\r
+ ReportText,\r
+ Handle\r
+ ));\r
return;\r
}\r
\r
Status = EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: %s: adding to ConOut: %r\n", __FUNCTION__,\r
- ReportText, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: %s: adding to ConOut: %r\n",\r
+ __FUNCTION__,\r
+ ReportText,\r
+ Status\r
+ ));\r
return;\r
}\r
\r
Status = EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: %s: adding to ErrOut: %r\n", __FUNCTION__,\r
- ReportText, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: %s: adding to ErrOut: %r\n",\r
+ __FUNCTION__,\r
+ ReportText,\r
+ Status\r
+ ));\r
return;\r
}\r
\r
- DEBUG ((DEBUG_VERBOSE, "%a: %s: added to ConOut and ErrOut\n", __FUNCTION__,\r
- ReportText));\r
+ DEBUG ((\r
+ DEBUG_VERBOSE,\r
+ "%a: %s: added to ConOut and ErrOut\n",\r
+ __FUNCTION__,\r
+ ReportText\r
+ ));\r
}\r
\r
STATIC\r
VOID\r
PlatformRegisterFvBootOption (\r
- CONST EFI_GUID *FileGuid,\r
- CHAR16 *Description,\r
- UINT32 Attributes,\r
- EFI_INPUT_KEY *Key\r
+ CONST EFI_GUID *FileGuid,\r
+ CHAR16 *Description,\r
+ UINT32 Attributes,\r
+ EFI_INPUT_KEY *Key\r
)\r
{\r
- EFI_STATUS Status;\r
- INTN OptionIndex;\r
- EFI_BOOT_MANAGER_LOAD_OPTION NewOption;\r
- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;\r
- UINTN BootOptionCount;\r
- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;\r
- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_STATUS Status;\r
+ INTN OptionIndex;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;\r
+ UINTN BootOptionCount;\r
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;\r
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
\r
Status = gBS->HandleProtocol (\r
gImageHandle,\r
&gEfiLoadedImageProtocolGuid,\r
- (VOID **) &LoadedImage\r
+ (VOID **)&LoadedImage\r
);\r
ASSERT_EFI_ERROR (Status);\r
\r
ASSERT (DevicePath != NULL);\r
DevicePath = AppendDevicePathNode (\r
DevicePath,\r
- (EFI_DEVICE_PATH_PROTOCOL *) &FileNode\r
+ (EFI_DEVICE_PATH_PROTOCOL *)&FileNode\r
);\r
ASSERT (DevicePath != NULL);\r
\r
FreePool (DevicePath);\r
\r
BootOptions = EfiBootManagerGetLoadOptions (\r
- &BootOptionCount, LoadOptionTypeBoot\r
+ &BootOptionCount,\r
+ LoadOptionTypeBoot\r
);\r
\r
OptionIndex = EfiBootManagerFindLoadOption (\r
- &NewOption, BootOptions, BootOptionCount\r
+ &NewOption,\r
+ BootOptions,\r
+ BootOptionCount\r
);\r
\r
if (OptionIndex == -1) {\r
Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN);\r
ASSERT_EFI_ERROR (Status);\r
- Status = EfiBootManagerAddKeyOptionVariable (NULL,\r
- (UINT16)NewOption.OptionNumber, 0, Key, NULL);\r
+ Status = EfiBootManagerAddKeyOptionVariable (\r
+ NULL,\r
+ (UINT16)NewOption.OptionNumber,\r
+ 0,\r
+ Key,\r
+ NULL\r
+ );\r
ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);\r
}\r
+\r
EfiBootManagerFreeLoadOption (&NewOption);\r
EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);\r
}\r
\r
-\r
STATIC\r
VOID\r
GetPlatformOptions (\r
UINTN Index;\r
UINTN BootCount;\r
\r
- Status = gBS->LocateProtocol (&gPlatformBootManagerProtocolGuid, NULL,\r
- (VOID **)&PlatformBootManager);\r
+ Status = gBS->LocateProtocol (\r
+ &gPlatformBootManagerProtocolGuid,\r
+ NULL,\r
+ (VOID **)&PlatformBootManager\r
+ );\r
if (EFI_ERROR (Status)) {\r
return;\r
}\r
+\r
Status = PlatformBootManager->GetPlatformBootOptionsAndKeys (\r
&BootCount,\r
&BootOptions,\r
if (EFI_ERROR (Status)) {\r
return;\r
}\r
+\r
//\r
// Fetch the existent boot options. If there are none, CurrentBootCount\r
// will be zeroed.\r
// Process the platform boot options.\r
//\r
for (Index = 0; Index < BootCount; Index++) {\r
- INTN Match;\r
- UINTN BootOptionNumber;\r
+ INTN Match;\r
+ UINTN BootOptionNumber;\r
\r
//\r
// If there are any preexistent boot options, and the subject platform boot\r
MAX_UINTN\r
);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: failed to register \"%s\": %r\n",\r
- __FUNCTION__, BootOptions[Index].Description, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: failed to register \"%s\": %r\n",\r
+ __FUNCTION__,\r
+ BootOptions[Index].Description,\r
+ Status\r
+ ));\r
continue;\r
}\r
+\r
BootOptionNumber = BootOptions[Index].OptionNumber;\r
}\r
\r
NULL\r
);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: failed to register hotkey for \"%s\": %r\n",\r
- __FUNCTION__, BootOptions[Index].Description, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: failed to register hotkey for \"%s\": %r\n",\r
+ __FUNCTION__,\r
+ BootOptions[Index].Description,\r
+ Status\r
+ ));\r
}\r
}\r
+\r
EfiBootManagerFreeLoadOptions (CurrentBootOptions, CurrentBootOptionCount);\r
EfiBootManagerFreeLoadOptions (BootOptions, BootCount);\r
FreePool (BootKeys);\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_INPUT_KEY Enter;\r
- EFI_INPUT_KEY F2;\r
- EFI_INPUT_KEY Esc;\r
- EFI_BOOT_MANAGER_LOAD_OPTION BootOption;\r
+ EFI_STATUS Status;\r
+ EFI_INPUT_KEY Enter;\r
+ EFI_INPUT_KEY F2;\r
+ EFI_INPUT_KEY Esc;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION BootOption;\r
\r
GetPlatformOptions ();\r
\r
//\r
Enter.ScanCode = SCAN_NULL;\r
Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;\r
- Status = EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);\r
+ Status = EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);\r
ASSERT_EFI_ERROR (Status);\r
\r
//\r
F2.UnicodeChar = CHAR_NULL;\r
Esc.ScanCode = SCAN_ESC;\r
Esc.UnicodeChar = CHAR_NULL;\r
- Status = EfiBootManagerGetBootManagerMenu (&BootOption);\r
+ Status = EfiBootManagerGetBootManagerMenu (&BootOption);\r
ASSERT_EFI_ERROR (Status);\r
Status = EfiBootManagerAddKeyOptionVariable (\r
- NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL\r
+ NULL,\r
+ (UINT16)BootOption.OptionNumber,\r
+ 0,\r
+ &F2,\r
+ NULL\r
);\r
ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);\r
Status = EfiBootManagerAddKeyOptionVariable (\r
- NULL, (UINT16) BootOption.OptionNumber, 0, &Esc, NULL\r
+ NULL,\r
+ (UINT16)BootOption.OptionNumber,\r
+ 0,\r
+ &Esc,\r
+ NULL\r
);\r
ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);\r
}\r
\r
-\r
//\r
// BDS Platform Functions\r
//\r
+\r
/**\r
Do the platform init, can be customized by OEM/IBV\r
Possible things that can be done in PlatformBootManagerBeforeConsole:\r
//\r
// Add the hardcoded short-form USB keyboard device path to ConIn.\r
//\r
- EfiBootManagerUpdateConsoleVariable (ConIn,\r
- (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, NULL);\r
+ EfiBootManagerUpdateConsoleVariable (\r
+ ConIn,\r
+ (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard,\r
+ NULL\r
+ );\r
\r
//\r
// Add the hardcoded serial console device path to ConIn, ConOut, ErrOut.\r
//\r
- STATIC_ASSERT (FixedPcdGet8 (PcdDefaultTerminalType) == 4,\r
- "PcdDefaultTerminalType must be TTYTERM");\r
- STATIC_ASSERT (FixedPcdGet8 (PcdUartDefaultParity) != 0,\r
- "PcdUartDefaultParity must be set to an actual value, not 'default'");\r
- STATIC_ASSERT (FixedPcdGet8 (PcdUartDefaultStopBits) != 0,\r
- "PcdUartDefaultStopBits must be set to an actual value, not 'default'");\r
+ STATIC_ASSERT (\r
+ FixedPcdGet8 (PcdDefaultTerminalType) == 4,\r
+ "PcdDefaultTerminalType must be TTYTERM"\r
+ );\r
+ STATIC_ASSERT (\r
+ FixedPcdGet8 (PcdUartDefaultParity) != 0,\r
+ "PcdUartDefaultParity must be set to an actual value, not 'default'"\r
+ );\r
+ STATIC_ASSERT (\r
+ FixedPcdGet8 (PcdUartDefaultStopBits) != 0,\r
+ "PcdUartDefaultStopBits must be set to an actual value, not 'default'"\r
+ );\r
\r
CopyGuid (&mSerialConsole.TermType.Guid, &gEfiTtyTermGuid);\r
\r
- EfiBootManagerUpdateConsoleVariable (ConIn,\r
- (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);\r
- EfiBootManagerUpdateConsoleVariable (ConOut,\r
- (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);\r
- EfiBootManagerUpdateConsoleVariable (ErrOut,\r
- (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);\r
+ EfiBootManagerUpdateConsoleVariable (\r
+ ConIn,\r
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole,\r
+ NULL\r
+ );\r
+ EfiBootManagerUpdateConsoleVariable (\r
+ ConOut,\r
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole,\r
+ NULL\r
+ );\r
+ EfiBootManagerUpdateConsoleVariable (\r
+ ErrOut,\r
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole,\r
+ NULL\r
+ );\r
\r
//\r
// Register platform-specific boot options and keyboard shortcuts.\r
VOID\r
)\r
{\r
- ESRT_MANAGEMENT_PROTOCOL *EsrtManagement;\r
- EFI_PEI_HOB_POINTERS HobPointer;\r
- EFI_CAPSULE_HEADER *CapsuleHeader;\r
- BOOLEAN NeedReset;\r
- EFI_STATUS Status;\r
+ ESRT_MANAGEMENT_PROTOCOL *EsrtManagement;\r
+ EFI_PEI_HOB_POINTERS HobPointer;\r
+ EFI_CAPSULE_HEADER *CapsuleHeader;\r
+ BOOLEAN NeedReset;\r
+ EFI_STATUS Status;\r
\r
DEBUG ((DEBUG_INFO, "%a: processing capsules ...\n", __FUNCTION__));\r
\r
- Status = gBS->LocateProtocol (&gEsrtManagementProtocolGuid, NULL,\r
- (VOID **)&EsrtManagement);\r
+ Status = gBS->LocateProtocol (\r
+ &gEsrtManagementProtocolGuid,\r
+ NULL,\r
+ (VOID **)&EsrtManagement\r
+ );\r
if (!EFI_ERROR (Status)) {\r
EsrtManagement->SyncEsrtFmp ();\r
}\r
// Find all capsule images from hob\r
//\r
HobPointer.Raw = GetHobList ();\r
- NeedReset = FALSE;\r
- while ((HobPointer.Raw = GetNextHob (EFI_HOB_TYPE_UEFI_CAPSULE,\r
- HobPointer.Raw)) != NULL) {\r
+ NeedReset = FALSE;\r
+ while ((HobPointer.Raw = GetNextHob (\r
+ EFI_HOB_TYPE_UEFI_CAPSULE,\r
+ HobPointer.Raw\r
+ )) != NULL)\r
+ {\r
CapsuleHeader = (VOID *)(UINTN)HobPointer.Capsule->BaseAddress;\r
\r
Status = ProcessCapsuleImage (CapsuleHeader);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: failed to process capsule %p - %r\n",\r
- __FUNCTION__, CapsuleHeader, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: failed to process capsule %p - %r\n",\r
+ __FUNCTION__,\r
+ CapsuleHeader,\r
+ Status\r
+ ));\r
return;\r
}\r
\r
- NeedReset = TRUE;\r
+ NeedReset = TRUE;\r
HobPointer.Raw = GET_NEXT_HOB (HobPointer);\r
}\r
\r
if (NeedReset) {\r
- DEBUG ((DEBUG_WARN, "%a: capsule update successful, resetting ...\n",\r
- __FUNCTION__));\r
-\r
- gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);\r
- CpuDeadLoop();\r
+ DEBUG ((\r
+ DEBUG_WARN,\r
+ "%a: capsule update successful, resetting ...\n",\r
+ __FUNCTION__\r
+ ));\r
+\r
+ gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);\r
+ CpuDeadLoop ();\r
}\r
}\r
\r
-\r
-#define VERSION_STRING_PREFIX L"Tianocore/EDK2 firmware version "\r
+#define VERSION_STRING_PREFIX L"Tianocore/EDK2 firmware version "\r
\r
/**\r
This functions checks the value of BootDiscoverPolicy variable and\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 DiscoveryPolicy;\r
- UINT32 DiscoveryPolicyOld;\r
- UINTN Size;\r
- EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy;\r
- EFI_GUID *Class;\r
-\r
- Size = sizeof (DiscoveryPolicy);\r
+ EFI_STATUS Status;\r
+ UINT32 DiscoveryPolicy;\r
+ UINT32 DiscoveryPolicyOld;\r
+ UINTN Size;\r
+ EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy;\r
+ EFI_GUID *Class;\r
+\r
+ Size = sizeof (DiscoveryPolicy);\r
Status = gRT->GetVariable (\r
BOOT_DISCOVERY_POLICY_VAR,\r
&gBootDiscoveryPolicyMgrFormsetGuid,\r
);\r
if (Status == EFI_NOT_FOUND) {\r
DiscoveryPolicy = PcdGet32 (PcdBootDiscoveryPolicy);\r
- Status = PcdSet32S (PcdBootDiscoveryPolicy, DiscoveryPolicy);\r
+ Status = PcdSet32S (PcdBootDiscoveryPolicy, DiscoveryPolicy);\r
if (Status == EFI_NOT_FOUND) {\r
return EFI_SUCCESS;\r
} else if (EFI_ERROR (Status)) {\r
(VOID **)&BMPolicy\r
);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_INFO, "%a - Failed to locate gEfiBootManagerPolicyProtocolGuid."\r
- "Driver connect will be skipped.\n", __FUNCTION__));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a - Failed to locate gEfiBootManagerPolicyProtocolGuid."\r
+ "Driver connect will be skipped.\n",\r
+ __FUNCTION__\r
+ ));\r
return Status;\r
}\r
\r
Status = BMPolicy->ConnectDeviceClass (BMPolicy, Class);\r
- if (EFI_ERROR (Status)){\r
+ if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "%a - ConnectDeviceClass returns - %r\n", __FUNCTION__, Status));\r
return Status;\r
}\r
//\r
// Refresh Boot Options if Boot Discovery Policy has been changed\r
//\r
- Size = sizeof (DiscoveryPolicyOld);\r
+ Size = sizeof (DiscoveryPolicyOld);\r
Status = gRT->GetVariable (\r
BOOT_DISCOVERY_POLICY_OLD_VAR,\r
&gBootDiscoveryPolicyMgrFormsetGuid,\r
Status = BootLogoEnableLogo ();\r
if (EFI_ERROR (Status)) {\r
if (FirmwareVerLength > 0) {\r
- Print (VERSION_STRING_PREFIX L"%s\n",\r
- PcdGetPtr (PcdFirmwareVersionString));\r
+ Print (\r
+ VERSION_STRING_PREFIX L"%s\n",\r
+ PcdGetPtr (PcdFirmwareVersionString)\r
+ );\r
}\r
+\r
Print (L"Press ESCAPE for boot options ");\r
} else if (FirmwareVerLength > 0) {\r
- Status = gBS->HandleProtocol (gST->ConsoleOutHandle,\r
- &gEfiGraphicsOutputProtocolGuid, (VOID **)&GraphicsOutput);\r
+ Status = gBS->HandleProtocol (\r
+ gST->ConsoleOutHandle,\r
+ &gEfiGraphicsOutputProtocolGuid,\r
+ (VOID **)&GraphicsOutput\r
+ );\r
if (!EFI_ERROR (Status)) {\r
PosX = (GraphicsOutput->Mode->Info->HorizontalResolution -\r
(StrLen (VERSION_STRING_PREFIX) + FirmwareVerLength) *\r
EFI_GLYPH_WIDTH) / 2;\r
PosY = 0;\r
\r
- PrintXY (PosX, PosY, NULL, NULL, VERSION_STRING_PREFIX L"%s",\r
- PcdGetPtr (PcdFirmwareVersionString));\r
+ PrintXY (\r
+ PosX,\r
+ PosY,\r
+ NULL,\r
+ NULL,\r
+ VERSION_STRING_PREFIX L"%s",\r
+ PcdGetPtr (PcdFirmwareVersionString)\r
+ );\r
}\r
}\r
\r
//\r
// Register UEFI Shell\r
//\r
- Key.ScanCode = SCAN_NULL;\r
- Key.UnicodeChar = L's';\r
+ Key.ScanCode = SCAN_NULL;\r
+ Key.UnicodeChar = L's';\r
PlatformRegisterFvBootOption (&gUefiShellFileGuid, L"UEFI Shell", 0, &Key);\r
}\r
\r
VOID\r
EFIAPI\r
PlatformBootManagerWaitCallback (\r
- UINT16 TimeoutRemain\r
+ UINT16 TimeoutRemain\r
)\r
{\r
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black;\r
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White;\r
- UINT16 Timeout;\r
- EFI_STATUS Status;\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black;\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White;\r
+ UINT16 Timeout;\r
+ EFI_STATUS Status;\r
\r
Timeout = PcdGet16 (PcdPlatformBootTimeOut);\r
\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_BOOT_MANAGER_LOAD_OPTION BootManagerMenu;\r
- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;\r
- UINTN OldBootOptionCount;\r
- UINTN NewBootOptionCount;\r
+ EFI_STATUS Status;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION BootManagerMenu;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;\r
+ UINTN OldBootOptionCount;\r
+ UINTN NewBootOptionCount;\r
\r
//\r
// Record the total number of boot configured boot options\r
//\r
- BootOptions = EfiBootManagerGetLoadOptions (&OldBootOptionCount,\r
- LoadOptionTypeBoot);\r
+ BootOptions = EfiBootManagerGetLoadOptions (\r
+ &OldBootOptionCount,\r
+ LoadOptionTypeBoot\r
+ );\r
EfiBootManagerFreeLoadOptions (BootOptions, OldBootOptionCount);\r
\r
//\r
//\r
// Record the updated number of boot configured boot options\r
//\r
- BootOptions = EfiBootManagerGetLoadOptions (&NewBootOptionCount,\r
- LoadOptionTypeBoot);\r
+ BootOptions = EfiBootManagerGetLoadOptions (\r
+ &NewBootOptionCount,\r
+ LoadOptionTypeBoot\r
+ );\r
EfiBootManagerFreeLoadOptions (BootOptions, NewBootOptionCount);\r
\r
//\r
//\r
if (!PcdGetBool (PcdEmuVariableNvModeEnable)) {\r
if (NewBootOptionCount != OldBootOptionCount) {\r
- DEBUG ((DEBUG_WARN, "%a: rebooting after refreshing all boot options\n",\r
- __FUNCTION__));\r
+ DEBUG ((\r
+ DEBUG_WARN,\r
+ "%a: rebooting after refreshing all boot options\n",\r
+ __FUNCTION__\r
+ ));\r
gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);\r
}\r
}\r
return;\r
}\r
\r
- for (;;) {\r
+ for ( ; ;) {\r
EfiBootManagerBoot (&BootManagerMenu);\r
}\r
}\r
// This gets you all the symbols except for SEC. To get SEC symbols you need to copy the\r
// debug print in the SEC into the debugger manually\r
SemihostWriteString (Buffer);\r
-/*\r
- I'm currently having issues with this code crashing the debugger. Seems like it should work.\r
\r
- UINT32 SemihostHandle;\r
- UINT32 SemihostMode = SEMIHOST_FILE_MODE_WRITE | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE;\r
+ /*\r
+ I'm currently having issues with this code crashing the debugger. Seems like it should work.\r
\r
- SemihostFileOpen ("c:\rvi_symbols.inc", SemihostMode, &SemihostHandle);\r
- SemihostFileWrite (SemihostHandle, &Length, Buffer);\r
- SemihostFileClose (SemihostHandle);\r
- */\r
-}\r
+ UINT32 SemihostHandle;\r
+ UINT32 SemihostMode = SEMIHOST_FILE_MODE_WRITE | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE;\r
\r
+ SemihostFileOpen ("c:\rvi_symbols.inc", SemihostMode, &SemihostHandle);\r
+ SemihostFileWrite (SemihostHandle, &Length, Buffer);\r
+ SemihostFileClose (SemihostHandle);\r
+ */\r
+}\r
\r
/**\r
If the build is done on cygwin the paths are cygpaths.\r
**/\r
CHAR8 *\r
DeCygwinPathIfNeeded (\r
- IN CHAR8 *Name\r
+ IN CHAR8 *Name\r
)\r
{\r
- CHAR8 *Ptr;\r
- UINTN Index;\r
- UINTN Len;\r
+ CHAR8 *Ptr;\r
+ UINTN Index;\r
+ UINTN Len;\r
\r
Ptr = AsciiStrStr (Name, "/cygdrive/");\r
if (Ptr == NULL) {\r
// switch path separators\r
for (Index = 11; Index < Len; Index++) {\r
if (Ptr[Index] == '/') {\r
- Ptr[Index] = '\\' ;\r
+ Ptr[Index] = '\\';\r
}\r
}\r
\r
return Name;\r
}\r
\r
-\r
/**\r
Performs additional actions after a PE/COFF image has been loaded and relocated.\r
\r
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
)\r
{\r
- CHAR8 Buffer[256];\r
+ CHAR8 Buffer[256];\r
\r
-#if (__ARMCC_VERSION < 500000)\r
- AsciiSPrint (Buffer, sizeof(Buffer), "load /a /ni /np \"%a\" &0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));\r
-#else\r
- AsciiSPrint (Buffer, sizeof(Buffer), "add-symbol-file %a 0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));\r
-#endif\r
+ #if (__ARMCC_VERSION < 500000)\r
+ AsciiSPrint (Buffer, sizeof (Buffer), "load /a /ni /np \"%a\" &0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));\r
+ #else\r
+ AsciiSPrint (Buffer, sizeof (Buffer), "add-symbol-file %a 0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));\r
+ #endif\r
DeCygwinPathIfNeeded (&Buffer[16]);\r
\r
WriteStringToFile (Buffer, AsciiStrSize (Buffer));\r
}\r
\r
-\r
-\r
/**\r
Performs additional actions just before a PE/COFF image is unloaded. Any resources\r
that were allocated by PeCoffLoaderRelocateImageExtraAction() must be freed.\r
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
)\r
{\r
- CHAR8 Buffer[256];\r
+ CHAR8 Buffer[256];\r
\r
- AsciiSPrint (Buffer, sizeof(Buffer), "unload symbols_only \"%a\"\n", ImageContext->PdbPointer);\r
+ AsciiSPrint (Buffer, sizeof (Buffer), "unload symbols_only \"%a\"\n", ImageContext->PdbPointer);\r
DeCygwinPathIfNeeded (Buffer);\r
\r
WriteStringToFile (Buffer, AsciiStrSize (Buffer));\r
\r
**/\r
\r
-\r
#include <Uefi.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PrintLib.h>\r
// VA_LIST can not initialize to NULL for all compiler, so we use this to\r
// indicate a null VA_LIST\r
//\r
-VA_LIST mVaListNull;\r
+VA_LIST mVaListNull;\r
\r
/**\r
\r
...\r
)\r
{\r
- VA_LIST Marker;\r
+ VA_LIST Marker;\r
\r
VA_START (Marker, Format);\r
DebugVPrint (ErrorLevel, Format, Marker);\r
VA_END (Marker);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled base on Null-terminated format string and a\r
**/\r
VOID\r
DebugPrintMarker (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
- CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];\r
+ CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];\r
\r
//\r
// If Format is NULL, then ASSERT().\r
//\r
// Check driver debug mask value and global mask\r
//\r
- if ((ErrorLevel & PcdGet32(PcdDebugPrintErrorLevel)) == 0) {\r
+ if ((ErrorLevel & PcdGet32 (PcdDebugPrintErrorLevel)) == 0) {\r
return;\r
}\r
\r
SemihostWriteString (AsciiBuffer);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugVPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugBPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);\r
}\r
\r
-\r
/**\r
\r
Prints an assert message containing a filename, line number, and description.\r
IN CONST CHAR8 *Description\r
)\r
{\r
- CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];\r
+ CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];\r
\r
//\r
// Generate the ASSERT() message in Unicode format\r
//\r
// Generate a Breakpoint, DeadLoop, or NOP based on PCD settings\r
//\r
- if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
+ if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
CpuBreakpoint ();\r
- } else if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
+ } else if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
CpuDeadLoop ();\r
}\r
}\r
\r
-\r
/**\r
\r
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.\r
//\r
// SetMem() checks for the ASSERT() condition on Length and returns Buffer\r
//\r
- return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));\r
+ return SetMem (Buffer, Length, PcdGet8 (PcdDebugClearMemoryValue));\r
}\r
\r
-\r
/**\r
\r
Returns TRUE if ASSERT() macros are enabled.\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
\r
Returns TRUE if DEBUG()macros are enabled.\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
\r
Returns TRUE if DEBUG_CODE()macros are enabled.\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
\r
Returns TRUE if DEBUG_CLEAR_MEMORY()macro is enabled.\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
}\r
#include <Library/SemihostLib.h>\r
#include <Library/SerialPortLib.h>\r
\r
-\r
/*\r
\r
Programmed hardware of Serial port.\r
UINTN\r
EFIAPI\r
SerialPortWrite (\r
- IN UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
-)\r
+ IN UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+ )\r
{\r
- UINT8 PrintBuffer[PRINT_BUFFER_SIZE];\r
- UINTN SourceIndex;\r
- UINTN DestinationIndex;\r
- UINT8 CurrentCharacter;\r
+ UINT8 PrintBuffer[PRINT_BUFFER_SIZE];\r
+ UINTN SourceIndex;\r
+ UINTN DestinationIndex;\r
+ UINT8 CurrentCharacter;\r
\r
SourceIndex = 0;\r
DestinationIndex = 0;\r
\r
- while (SourceIndex < NumberOfBytes)\r
- {\r
- CurrentCharacter = Buffer[SourceIndex++];\r
+ while (SourceIndex < NumberOfBytes) {\r
+ CurrentCharacter = Buffer[SourceIndex++];\r
\r
- switch (CurrentCharacter)\r
- {\r
+ switch (CurrentCharacter) {\r
case '\r':\r
- continue;\r
+ continue;\r
\r
case '\n':\r
- PrintBuffer[DestinationIndex++] = ' ';\r
- // fall through\r
+ PrintBuffer[DestinationIndex++] = ' ';\r
+ // fall through\r
\r
default:\r
- PrintBuffer[DestinationIndex++] = CurrentCharacter;\r
- break;\r
- }\r
+ PrintBuffer[DestinationIndex++] = CurrentCharacter;\r
+ break;\r
+ }\r
\r
- if (DestinationIndex > PRINT_BUFFER_THRESHOLD)\r
- {\r
- PrintBuffer[DestinationIndex] = '\0';\r
- SemihostWriteString ((CHAR8 *) PrintBuffer);\r
+ if (DestinationIndex > PRINT_BUFFER_THRESHOLD) {\r
+ PrintBuffer[DestinationIndex] = '\0';\r
+ SemihostWriteString ((CHAR8 *)PrintBuffer);\r
\r
- DestinationIndex = 0;\r
- }\r
+ DestinationIndex = 0;\r
+ }\r
}\r
\r
- if (DestinationIndex > 0)\r
- {\r
- PrintBuffer[DestinationIndex] = '\0';\r
- SemihostWriteString ((CHAR8 *) PrintBuffer);\r
+ if (DestinationIndex > 0) {\r
+ PrintBuffer[DestinationIndex] = '\0';\r
+ SemihostWriteString ((CHAR8 *)PrintBuffer);\r
}\r
\r
return NumberOfBytes;\r
}\r
\r
-\r
/**\r
Read data from serial device and save the datas in buffer.\r
\r
UINTN\r
EFIAPI\r
SerialPortRead (\r
- OUT UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
-)\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+ )\r
{\r
*Buffer = SemihostReadCharacter ();\r
return 1;\r
}\r
\r
-\r
-\r
/**\r
Check to see if any data is available to be read from the debug device.\r
\r
// Since SemiHosting read character is blocking always say we have a char ready?\r
return SemihostConnectionSupported ();\r
}\r
-\r
\r
RETURN_STATUS\r
SemihostFileOpen (\r
- IN CHAR8 *FileName,\r
- IN UINT32 Mode,\r
- OUT UINTN *FileHandle\r
+ IN CHAR8 *FileName,\r
+ IN UINT32 Mode,\r
+ OUT UINTN *FileHandle\r
)\r
{\r
SEMIHOST_FILE_OPEN_BLOCK OpenBlock;\r
FileName++;\r
}\r
\r
- OpenBlock.FileName = FileName;\r
- OpenBlock.Mode = Mode;\r
- OpenBlock.NameLength = AsciiStrLen(FileName);\r
+ OpenBlock.FileName = FileName;\r
+ OpenBlock.Mode = Mode;\r
+ OpenBlock.NameLength = AsciiStrLen (FileName);\r
\r
Result = SEMIHOST_SYS_OPEN (&OpenBlock);\r
\r
\r
*Length = SEMIHOST_SYS_WRITE (&WriteBlock);\r
\r
- if (*Length != 0)\r
+ if (*Length != 0) {\r
return RETURN_ABORTED;\r
- else\r
+ } else {\r
return RETURN_SUCCESS;\r
+ }\r
}\r
\r
RETURN_STATUS\r
OUT UINTN *Length\r
)\r
{\r
- INT32 Result;\r
+ INT32 Result;\r
\r
if (Length == NULL) {\r
return RETURN_INVALID_PARAMETER;\r
\r
**/\r
RETURN_STATUS\r
-SemihostFileTmpName(\r
+SemihostFileTmpName (\r
OUT VOID *Buffer,\r
IN UINT8 Identifier,\r
IN UINTN Length\r
Result = SEMIHOST_SYS_TMPNAME (&TmpNameBlock);\r
\r
if (Result != 0) {\r
- return RETURN_ABORTED;\r
+ return RETURN_ABORTED;\r
} else {\r
- return RETURN_SUCCESS;\r
+ return RETURN_SUCCESS;\r
}\r
}\r
\r
RETURN_STATUS\r
SemihostFileRemove (\r
- IN CHAR8 *FileName\r
+ IN CHAR8 *FileName\r
)\r
{\r
SEMIHOST_FILE_REMOVE_BLOCK RemoveBlock;\r
FileName++;\r
}\r
\r
- RemoveBlock.FileName = FileName;\r
- RemoveBlock.NameLength = AsciiStrLen(FileName);\r
+ RemoveBlock.FileName = FileName;\r
+ RemoveBlock.NameLength = AsciiStrLen (FileName);\r
\r
Result = SEMIHOST_SYS_REMOVE (&RemoveBlock);\r
\r
\r
**/\r
RETURN_STATUS\r
-SemihostFileRename(\r
+SemihostFileRename (\r
IN CHAR8 *FileName,\r
IN CHAR8 *NewFileName\r
)\r
Result = SEMIHOST_SYS_RENAME (&RenameBlock);\r
\r
if (Result != 0) {\r
- return RETURN_ABORTED;\r
+ return RETURN_ABORTED;\r
} else {\r
- return RETURN_SUCCESS;\r
+ return RETURN_SUCCESS;\r
}\r
}\r
\r
\r
VOID\r
SemihostWriteCharacter (\r
- IN CHAR8 Character\r
+ IN CHAR8 Character\r
)\r
{\r
SEMIHOST_SYS_WRITEC (&Character);\r
\r
VOID\r
SemihostWriteString (\r
- IN CHAR8 *String\r
+ IN CHAR8 *String\r
)\r
{\r
SEMIHOST_SYS_WRITE0 (String);\r
\r
UINT32\r
SemihostSystem (\r
- IN CHAR8 *CommandLine\r
+ IN CHAR8 *CommandLine\r
)\r
{\r
- SEMIHOST_SYSTEM_BLOCK SystemBlock;\r
+ SEMIHOST_SYSTEM_BLOCK SystemBlock;\r
\r
SystemBlock.CommandLine = CommandLine;\r
- SystemBlock.CommandLength = AsciiStrLen(CommandLine);\r
+ SystemBlock.CommandLength = AsciiStrLen (CommandLine);\r
\r
return SEMIHOST_SYS_SYSTEM (&SystemBlock);\r
}\r
#define SEMIHOST_PRIVATE_H_\r
\r
typedef struct {\r
- CHAR8 *FileName;\r
+ CHAR8 *FileName;\r
UINTN Mode;\r
UINTN NameLength;\r
} SEMIHOST_FILE_OPEN_BLOCK;\r
\r
typedef struct {\r
UINTN Handle;\r
- VOID *Buffer;\r
+ VOID *Buffer;\r
UINTN Length;\r
} SEMIHOST_FILE_READ_WRITE_BLOCK;\r
\r
} SEMIHOST_FILE_SEEK_BLOCK;\r
\r
typedef struct {\r
- VOID *Buffer;\r
+ VOID *Buffer;\r
UINTN Identifier;\r
UINTN Length;\r
} SEMIHOST_FILE_TMPNAME_BLOCK;\r
\r
typedef struct {\r
- CHAR8 *FileName;\r
+ CHAR8 *FileName;\r
UINTN NameLength;\r
} SEMIHOST_FILE_REMOVE_BLOCK;\r
\r
typedef struct {\r
- CHAR8 *FileName;\r
+ CHAR8 *FileName;\r
UINTN FileNameLength;\r
- CHAR8 *NewFileName;\r
+ CHAR8 *NewFileName;\r
UINTN NewFileNameLength;\r
} SEMIHOST_FILE_RENAME_BLOCK;\r
\r
typedef struct {\r
- CHAR8 *CommandLine;\r
+ CHAR8 *CommandLine;\r
UINTN CommandLength;\r
} SEMIHOST_SYSTEM_BLOCK;\r
\r
-#if defined(__CC_ARM)\r
+#if defined (__CC_ARM)\r
\r
-#if defined(__thumb__)\r
-#define SWI 0xAB\r
-#else\r
-#define SWI 0x123456\r
-#endif\r
+ #if defined (__thumb__)\r
+#define SWI 0xAB\r
+ #else\r
+#define SWI 0x123456\r
+ #endif\r
\r
#define SEMIHOST_SUPPORTED TRUE\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
INT32\r
-_Semihost_SYS_OPEN(\r
- IN UINTN SWI_0x01,\r
- IN SEMIHOST_FILE_OPEN_BLOCK *OpenBlock\r
+_Semihost_SYS_OPEN (\r
+ IN UINTN SWI_0x01,\r
+ IN SEMIHOST_FILE_OPEN_BLOCK *OpenBlock\r
);\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
INT32\r
-_Semihost_SYS_CLOSE(\r
- IN UINTN SWI_0x02,\r
- IN UINT32 *Handle\r
+_Semihost_SYS_CLOSE (\r
+ IN UINTN SWI_0x02,\r
+ IN UINT32 *Handle\r
);\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
VOID\r
-_Semihost_SYS_WRITEC(\r
- IN UINTN SWI_0x03,\r
- IN CHAR8 *Character\r
+_Semihost_SYS_WRITEC (\r
+ IN UINTN SWI_0x03,\r
+ IN CHAR8 *Character\r
);\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
VOID\r
-_Semihost_SYS_WRITE0(\r
- IN UINTN SWI_0x04,\r
- IN CHAR8 *String\r
+_Semihost_SYS_WRITE0 (\r
+ IN UINTN SWI_0x04,\r
+ IN CHAR8 *String\r
);\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
UINT32\r
-_Semihost_SYS_WRITE(\r
- IN UINTN SWI_0x05,\r
- IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *WriteBlock\r
+_Semihost_SYS_WRITE (\r
+ IN UINTN SWI_0x05,\r
+ IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *WriteBlock\r
);\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
UINT32\r
-_Semihost_SYS_READ(\r
- IN UINTN SWI_0x06,\r
- IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *ReadBlock\r
+_Semihost_SYS_READ (\r
+ IN UINTN SWI_0x06,\r
+ IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *ReadBlock\r
);\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
CHAR8\r
-_Semihost_SYS_READC(\r
- IN UINTN SWI_0x07,\r
- IN UINTN Zero\r
+_Semihost_SYS_READC (\r
+ IN UINTN SWI_0x07,\r
+ IN UINTN Zero\r
);\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
INT32\r
-_Semihost_SYS_SEEK(\r
- IN UINTN SWI_0x0A,\r
- IN SEMIHOST_FILE_SEEK_BLOCK *SeekBlock\r
+_Semihost_SYS_SEEK (\r
+ IN UINTN SWI_0x0A,\r
+ IN SEMIHOST_FILE_SEEK_BLOCK *SeekBlock\r
);\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
INT32\r
-_Semihost_SYS_FLEN(\r
- IN UINTN SWI_0x0C,\r
- IN UINT32 *Handle\r
+_Semihost_SYS_FLEN (\r
+ IN UINTN SWI_0x0C,\r
+ IN UINT32 *Handle\r
);\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
UINT32\r
-_Semihost_SYS_TMPNAME(\r
- IN UINTN SWI_0x0D,\r
- IN SEMIHOST_FILE_TMPNAME_BLOCK *TmpNameBlock\r
+_Semihost_SYS_TMPNAME (\r
+ IN UINTN SWI_0x0D,\r
+ IN SEMIHOST_FILE_TMPNAME_BLOCK *TmpNameBlock\r
);\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
UINT32\r
-_Semihost_SYS_REMOVE(\r
- IN UINTN SWI_0x0E,\r
- IN SEMIHOST_FILE_REMOVE_BLOCK *RemoveBlock\r
+_Semihost_SYS_REMOVE (\r
+ IN UINTN SWI_0x0E,\r
+ IN SEMIHOST_FILE_REMOVE_BLOCK *RemoveBlock\r
);\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
UINT32\r
-_Semihost_SYS_RENAME(\r
- IN UINTN SWI_0x0F,\r
- IN SEMIHOST_FILE_RENAME_BLOCK *RenameBlock\r
+_Semihost_SYS_RENAME (\r
+ IN UINTN SWI_0x0F,\r
+ IN SEMIHOST_FILE_RENAME_BLOCK *RenameBlock\r
);\r
\r
-__swi(SWI)\r
+__swi (SWI)\r
UINT32\r
-_Semihost_SYS_SYSTEM(\r
- IN UINTN SWI_0x12,\r
- IN SEMIHOST_SYSTEM_BLOCK *SystemBlock\r
+_Semihost_SYS_SYSTEM (\r
+ IN UINTN SWI_0x12,\r
+ IN SEMIHOST_SYSTEM_BLOCK *SystemBlock\r
);\r
\r
#define SEMIHOST_SYS_OPEN(OpenBlock) _Semihost_SYS_OPEN(0x01, OpenBlock)\r
#define SEMIHOST_SYS_RENAME(RenameBlock) _Semihost_SYS_RENAME(0x0F, RenameBlock)\r
#define SEMIHOST_SYS_SYSTEM(SystemBlock) _Semihost_SYS_SYSTEM(0x12, SystemBlock)\r
\r
-#elif defined(__GNUC__) // __CC_ARM\r
+#elif defined (__GNUC__) // __CC_ARM\r
\r
#define SEMIHOST_SUPPORTED TRUE\r
\r
UINT32\r
GccSemihostCall (\r
- IN UINT32 Operation,\r
- IN UINTN SystemBlockAddress\r
+ IN UINT32 Operation,\r
+ IN UINTN SystemBlockAddress\r
); // __attribute__ ((interrupt ("SVC")));\r
\r
#define SEMIHOST_SYS_OPEN(OpenBlock) GccSemihostCall(0x01, (UINTN)(OpenBlock))\r
\r
#define SEMIHOST_SUPPORTED FALSE\r
\r
-#define SEMIHOST_SYS_OPEN(OpenBlock) (-1)\r
-#define SEMIHOST_SYS_CLOSE(Handle) (-1)\r
+#define SEMIHOST_SYS_OPEN(OpenBlock) (-1)\r
+#define SEMIHOST_SYS_CLOSE(Handle) (-1)\r
#define SEMIHOST_SYS_WRITE0(String)\r
#define SEMIHOST_SYS_WRITEC(Character)\r
#define SEMIHOST_SYS_WRITE(WriteBlock) (0)\r
STATIC\r
EFI_STATUS\r
SendMemoryPermissionRequest (\r
- IN OUT ARM_SVC_ARGS *SvcArgs,\r
- OUT INT32 *RetVal\r
+ IN OUT ARM_SVC_ARGS *SvcArgs,\r
+ OUT INT32 *RetVal\r
)\r
{\r
if ((SvcArgs == NULL) || (RetVal == NULL)) {\r
STATIC\r
EFI_STATUS\r
GetMemoryPermissions (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- OUT UINT32 *MemoryAttributes\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ OUT UINT32 *MemoryAttributes\r
)\r
{\r
EFI_STATUS Status;\r
STATIC\r
EFI_STATUS\r
RequestMemoryPermissionChange (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT32 Permissions\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT32 Permissions\r
)\r
{\r
INT32 Ret;\r
\r
EFI_STATUS\r
ArmSetMemoryRegionNoExec (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 MemoryAttributes;\r
- UINT32 CodePermission;\r
+ EFI_STATUS Status;\r
+ UINT32 MemoryAttributes;\r
+ UINT32 CodePermission;\r
\r
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);\r
if (!EFI_ERROR (Status)) {\r
MemoryAttributes | CodePermission\r
);\r
}\r
+\r
return Status;\r
}\r
\r
EFI_STATUS\r
ArmClearMemoryRegionNoExec (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 MemoryAttributes;\r
- UINT32 CodePermission;\r
+ EFI_STATUS Status;\r
+ UINT32 MemoryAttributes;\r
+ UINT32 CodePermission;\r
\r
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);\r
if (!EFI_ERROR (Status)) {\r
MemoryAttributes & ~CodePermission\r
);\r
}\r
+\r
return Status;\r
}\r
\r
EFI_STATUS\r
ArmSetMemoryRegionReadOnly (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 MemoryAttributes;\r
- UINT32 DataPermission;\r
+ EFI_STATUS Status;\r
+ UINT32 MemoryAttributes;\r
+ UINT32 DataPermission;\r
\r
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);\r
if (!EFI_ERROR (Status)) {\r
MemoryAttributes | DataPermission\r
);\r
}\r
+\r
return Status;\r
}\r
\r
EFI_STATUS\r
ArmClearMemoryRegionReadOnly (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 MemoryAttributes;\r
- UINT32 PermissionRequest;\r
+ EFI_STATUS Status;\r
+ UINT32 MemoryAttributes;\r
+ UINT32 PermissionRequest;\r
\r
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);\r
if (!EFI_ERROR (Status)) {\r
- PermissionRequest = SET_MEM_ATTR_MAKE_PERM_REQUEST (SET_MEM_ATTR_DATA_PERM_RW,\r
- MemoryAttributes);\r
+ PermissionRequest = SET_MEM_ATTR_MAKE_PERM_REQUEST (\r
+ SET_MEM_ATTR_DATA_PERM_RW,\r
+ MemoryAttributes\r
+ );\r
return RequestMemoryPermissionChange (\r
BaseAddress,\r
Length,\r
PermissionRequest\r
);\r
}\r
+\r
return Status;\r
}\r
#include <Library/HiiLib.h>\r
#include <Library/OemMiscLib.h>\r
\r
-\r
/** Gets the CPU frequency of the specified processor.\r
\r
@param ProcessorIndex Index of the processor to get the frequency for.\r
UINTN\r
EFIAPI\r
OemGetCpuFreq (\r
- IN UINT8 ProcessorIndex\r
+ IN UINT8 ProcessorIndex\r
)\r
{\r
ASSERT (FALSE);\r
BOOLEAN\r
EFIAPI\r
OemGetProcessorInformation (\r
- IN UINTN ProcessorIndex,\r
- IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,\r
- IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,\r
- IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData\r
+ IN UINTN ProcessorIndex,\r
+ IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,\r
+ IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,\r
+ IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData\r
)\r
{\r
ASSERT (FALSE);\r
BOOLEAN\r
EFIAPI\r
OemGetCacheInformation (\r
- IN UINT8 ProcessorIndex,\r
- IN UINT8 CacheLevel,\r
- IN BOOLEAN DataCache,\r
- IN BOOLEAN UnifiedCache,\r
- IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable\r
+ IN UINT8 ProcessorIndex,\r
+ IN UINT8 CacheLevel,\r
+ IN BOOLEAN DataCache,\r
+ IN BOOLEAN UnifiedCache,\r
+ IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable\r
)\r
{\r
ASSERT (FALSE);\r
BOOLEAN\r
EFIAPI\r
OemIsProcessorPresent (\r
- IN UINTN ProcessorIndex\r
+ IN UINTN ProcessorIndex\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
OemUpdateSmbiosInfo (\r
- IN EFI_HII_HANDLE HiiHandle,\r
- IN EFI_STRING_ID TokenToUpdate,\r
- IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field\r
+ IN EFI_HII_HANDLE HiiHandle,\r
+ IN EFI_STRING_ID TokenToUpdate,\r
+ IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field\r
)\r
{\r
ASSERT (FALSE);\r
\r
#include "SmbiosProcessor.h"\r
\r
-extern UINT8 ProcessorSubClassStrings[];\r
+extern UINT8 ProcessorSubClassStrings[];\r
\r
-#define CACHE_SOCKETED_SHIFT 3\r
-#define CACHE_LOCATION_SHIFT 5\r
-#define CACHE_ENABLED_SHIFT 7\r
-#define CACHE_OPERATION_MODE_SHIFT 8\r
+#define CACHE_SOCKETED_SHIFT 3\r
+#define CACHE_LOCATION_SHIFT 5\r
+#define CACHE_ENABLED_SHIFT 7\r
+#define CACHE_OPERATION_MODE_SHIFT 8\r
\r
typedef enum {\r
CacheModeWriteThrough = 0, ///< Cache is write-through\r
CacheLocationMax\r
} CACHE_LOCATION;\r
\r
-EFI_HII_HANDLE mHiiHandle;\r
+EFI_HII_HANDLE mHiiHandle;\r
\r
EFI_SMBIOS_PROTOCOL *mSmbios;\r
\r
-SMBIOS_TABLE_TYPE4 mSmbiosProcessorTableTemplate = {\r
- { // Hdr\r
- EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // Type\r
- sizeof (SMBIOS_TABLE_TYPE4), // Length\r
- 0 // Handle\r
- },\r
- 1, // Socket\r
- CentralProcessor, // ProcessorType\r
- ProcessorFamilyIndicatorFamily2, // ProcessorFamily\r
- 2, // ProcessorManufacture\r
- { // ProcessorId\r
- { // Signature\r
- 0\r
- },\r
- { // FeatureFlags\r
- 0\r
- }\r
- },\r
- 3, // ProcessorVersion\r
- { // Voltage\r
+SMBIOS_TABLE_TYPE4 mSmbiosProcessorTableTemplate = {\r
+ { // Hdr\r
+ EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // Type\r
+ sizeof (SMBIOS_TABLE_TYPE4), // Length\r
+ 0 // Handle\r
+ },\r
+ 1, // Socket\r
+ CentralProcessor, // ProcessorType\r
+ ProcessorFamilyIndicatorFamily2, // ProcessorFamily\r
+ 2, // ProcessorManufacture\r
+ { // ProcessorId\r
+ { // Signature\r
0\r
},\r
- 0, // ExternalClock\r
- 0, // MaxSpeed\r
- 0, // CurrentSpeed\r
- 0, // Status\r
- ProcessorUpgradeUnknown, // ProcessorUpgrade\r
- 0xFFFF, // L1CacheHandle\r
- 0xFFFF, // L2CacheHandle\r
- 0xFFFF, // L3CacheHandle\r
- 4, // SerialNumber\r
- 5, // AssetTag\r
- 6, // PartNumber\r
- 0, // CoreCount\r
- 0, //EnabledCoreCount\r
- 0, // ThreadCount\r
- 0, // ProcessorCharacteristics\r
- ProcessorFamilyARM, // ProcessorFamily2\r
- 0, // CoreCount2\r
- 0, // EnabledCoreCount2\r
- 0 // ThreadCount2\r
+ { // FeatureFlags\r
+ 0\r
+ }\r
+ },\r
+ 3, // ProcessorVersion\r
+ { // Voltage\r
+ 0\r
+ },\r
+ 0, // ExternalClock\r
+ 0, // MaxSpeed\r
+ 0, // CurrentSpeed\r
+ 0, // Status\r
+ ProcessorUpgradeUnknown, // ProcessorUpgrade\r
+ 0xFFFF, // L1CacheHandle\r
+ 0xFFFF, // L2CacheHandle\r
+ 0xFFFF, // L3CacheHandle\r
+ 4, // SerialNumber\r
+ 5, // AssetTag\r
+ 6, // PartNumber\r
+ 0, // CoreCount\r
+ 0, // EnabledCoreCount\r
+ 0, // ThreadCount\r
+ 0, // ProcessorCharacteristics\r
+ ProcessorFamilyARM, // ProcessorFamily2\r
+ 0, // CoreCount2\r
+ 0, // EnabledCoreCount2\r
+ 0 // ThreadCount2\r
};\r
\r
/** Sets the HII variable `StringId` is `Pcd` isn't empty.\r
**/\r
UINT16\r
GetCpuFrequency (\r
- IN UINT8 ProcessorNumber\r
+ IN UINT8 ProcessorNumber\r
)\r
{\r
return (UINT16)(OemGetCpuFreq (ProcessorNumber) / 1000 / 1000);\r
**/\r
UINTN\r
GetCacheSocketStr (\r
- IN UINT8 CacheLevel,\r
- IN BOOLEAN DataCache,\r
- IN BOOLEAN UnifiedCache,\r
- OUT CHAR16 *CacheSocketStr\r
+ IN UINT8 CacheLevel,\r
+ IN BOOLEAN DataCache,\r
+ IN BOOLEAN UnifiedCache,\r
+ OUT CHAR16 *CacheSocketStr\r
)\r
{\r
- UINTN CacheSocketStrLen;\r
+ UINTN CacheSocketStrLen;\r
\r
- if (CacheLevel == CpuCacheL1 && !DataCache && !UnifiedCache) {\r
+ if ((CacheLevel == CpuCacheL1) && !DataCache && !UnifiedCache) {\r
CacheSocketStrLen = UnicodeSPrint (\r
CacheSocketStr,\r
SMBIOS_STRING_MAX_LENGTH - 1,\r
L"L%x Instruction Cache",\r
- CacheLevel);\r
- } else if (CacheLevel == CpuCacheL1 && DataCache) {\r
- CacheSocketStrLen = UnicodeSPrint (CacheSocketStr,\r
+ CacheLevel\r
+ );\r
+ } else if ((CacheLevel == CpuCacheL1) && DataCache) {\r
+ CacheSocketStrLen = UnicodeSPrint (\r
+ CacheSocketStr,\r
SMBIOS_STRING_MAX_LENGTH - 1,\r
L"L%x Data Cache",\r
- CacheLevel);\r
+ CacheLevel\r
+ );\r
} else {\r
- CacheSocketStrLen = UnicodeSPrint (CacheSocketStr,\r
+ CacheSocketStrLen = UnicodeSPrint (\r
+ CacheSocketStr,\r
SMBIOS_STRING_MAX_LENGTH - 1,\r
L"L%x Cache",\r
- CacheLevel);\r
+ CacheLevel\r
+ );\r
}\r
\r
return CacheSocketStrLen;\r
**/\r
VOID\r
ConfigureCacheArchitectureInformation (\r
- IN UINT8 CacheLevel,\r
- IN BOOLEAN DataCache,\r
- IN BOOLEAN UnifiedCache,\r
- OUT SMBIOS_TABLE_TYPE7 *Type7Record\r
+ IN UINT8 CacheLevel,\r
+ IN BOOLEAN DataCache,\r
+ IN BOOLEAN UnifiedCache,\r
+ OUT SMBIOS_TABLE_TYPE7 *Type7Record\r
)\r
{\r
- UINT8 Associativity;\r
- UINT32 CacheSize32;\r
- UINT16 CacheSize16;\r
- UINT64 CacheSize64;\r
+ UINT8 Associativity;\r
+ UINT32 CacheSize32;\r
+ UINT16 CacheSize16;\r
+ UINT64 CacheSize64;\r
\r
if (!DataCache && !UnifiedCache) {\r
Type7Record->SystemCacheType = CacheTypeInstruction;\r
} else if (UnifiedCache) {\r
Type7Record->SystemCacheType = CacheTypeUnified;\r
} else {\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
}\r
\r
- CacheSize64 = SmbiosProcessorGetCacheSize (CacheLevel,\r
- DataCache,\r
- UnifiedCache\r
- );\r
+ CacheSize64 = SmbiosProcessorGetCacheSize (\r
+ CacheLevel,\r
+ DataCache,\r
+ UnifiedCache\r
+ );\r
\r
- Associativity = SmbiosProcessorGetCacheAssociativity (CacheLevel,\r
- DataCache,\r
- UnifiedCache\r
- );\r
+ Associativity = SmbiosProcessorGetCacheAssociativity (\r
+ CacheLevel,\r
+ DataCache,\r
+ UnifiedCache\r
+ );\r
\r
CacheSize64 /= 1024; // Minimum granularity is 1K\r
\r
CacheSize16 = -1;\r
}\r
\r
- Type7Record->MaximumCacheSize = CacheSize16;\r
- Type7Record->InstalledSize = CacheSize16;\r
+ Type7Record->MaximumCacheSize = CacheSize16;\r
+ Type7Record->InstalledSize = CacheSize16;\r
Type7Record->MaximumCacheSize2 = CacheSize32;\r
- Type7Record->InstalledSize2 = CacheSize32;\r
+ Type7Record->InstalledSize2 = CacheSize32;\r
\r
switch (Associativity) {\r
case 2:\r
(CacheLevel - 1);\r
}\r
\r
-\r
/** Allocates and initializes an SMBIOS_TABLE_TYPE7 structure.\r
\r
@param[in] CacheLevel The cache level (L1-L7).\r
**/\r
SMBIOS_TABLE_TYPE7 *\r
AllocateAndInitCacheInformation (\r
- IN UINT8 CacheLevel,\r
- IN BOOLEAN DataCache,\r
- IN BOOLEAN UnifiedCache\r
+ IN UINT8 CacheLevel,\r
+ IN BOOLEAN DataCache,\r
+ IN BOOLEAN UnifiedCache\r
)\r
{\r
SMBIOS_TABLE_TYPE7 *Type7Record;\r
\r
// Allocate and fetch the cache description\r
StringBufferSize = sizeof (CHAR16) * SMBIOS_STRING_MAX_LENGTH;\r
- CacheSocketStr = AllocateZeroPool (StringBufferSize);\r
+ CacheSocketStr = AllocateZeroPool (StringBufferSize);\r
if (CacheSocketStr == NULL) {\r
return NULL;\r
}\r
\r
- CacheSocketStrLen = GetCacheSocketStr (CacheLevel,\r
- DataCache,\r
- UnifiedCache,\r
- CacheSocketStr);\r
+ CacheSocketStrLen = GetCacheSocketStr (\r
+ CacheLevel,\r
+ DataCache,\r
+ UnifiedCache,\r
+ CacheSocketStr\r
+ );\r
\r
- TableSize = sizeof (SMBIOS_TABLE_TYPE7) + CacheSocketStrLen + 1 + 1;\r
+ TableSize = sizeof (SMBIOS_TABLE_TYPE7) + CacheSocketStrLen + 1 + 1;\r
Type7Record = AllocateZeroPool (TableSize);\r
if (Type7Record == NULL) {\r
- FreePool(CacheSocketStr);\r
+ FreePool (CacheSocketStr);\r
return NULL;\r
}\r
\r
- Type7Record->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;\r
+ Type7Record->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;\r
Type7Record->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE7);\r
Type7Record->Hdr.Handle = SMBIOS_HANDLE_PI_RESERVED;\r
\r
Type7Record->SocketDesignation = 1;\r
\r
Type7Record->SupportedSRAMType.Unknown = 1;\r
- Type7Record->CurrentSRAMType.Unknown = 1;\r
- Type7Record->CacheSpeed = 0;\r
- Type7Record->ErrorCorrectionType = CacheErrorUnknown;\r
+ Type7Record->CurrentSRAMType.Unknown = 1;\r
+ Type7Record->CacheSpeed = 0;\r
+ Type7Record->ErrorCorrectionType = CacheErrorUnknown;\r
\r
OptionalStrStart = (CHAR8 *)(Type7Record + 1);\r
UnicodeStrToAsciiStrS (CacheSocketStr, OptionalStrStart, CacheSocketStrLen + 1);\r
**/\r
VOID\r
AddSmbiosCacheTypeTable (\r
- IN UINTN ProcessorIndex,\r
- OUT EFI_SMBIOS_HANDLE *L1CacheHandle,\r
- OUT EFI_SMBIOS_HANDLE *L2CacheHandle,\r
- OUT EFI_SMBIOS_HANDLE *L3CacheHandle\r
+ IN UINTN ProcessorIndex,\r
+ OUT EFI_SMBIOS_HANDLE *L1CacheHandle,\r
+ OUT EFI_SMBIOS_HANDLE *L2CacheHandle,\r
+ OUT EFI_SMBIOS_HANDLE *L3CacheHandle\r
)\r
{\r
- EFI_STATUS Status;\r
- SMBIOS_TABLE_TYPE7 *Type7Record;\r
- EFI_SMBIOS_HANDLE SmbiosHandle;\r
- UINT8 CacheLevel;\r
- UINT8 MaxCacheLevel;\r
- BOOLEAN DataCacheType;\r
- BOOLEAN SeparateCaches;\r
+ EFI_STATUS Status;\r
+ SMBIOS_TABLE_TYPE7 *Type7Record;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ UINT8 CacheLevel;\r
+ UINT8 MaxCacheLevel;\r
+ BOOLEAN DataCacheType;\r
+ BOOLEAN SeparateCaches;\r
\r
Status = EFI_SUCCESS;\r
\r
// process the instruction cache.\r
for (DataCacheType = 0; DataCacheType <= 1; DataCacheType++) {\r
// If there's no separate data/instruction cache, skip the second iteration\r
- if (DataCacheType == 1 && !SeparateCaches) {\r
+ if ((DataCacheType == 1) && !SeparateCaches) {\r
continue;\r
}\r
\r
- Type7Record = AllocateAndInitCacheInformation (CacheLevel,\r
- DataCacheType,\r
- !SeparateCaches\r
- );\r
+ Type7Record = AllocateAndInitCacheInformation (\r
+ CacheLevel,\r
+ DataCacheType,\r
+ !SeparateCaches\r
+ );\r
if (Type7Record == NULL) {\r
continue;\r
}\r
\r
- ConfigureCacheArchitectureInformation(CacheLevel,\r
- DataCacheType,\r
- !SeparateCaches,\r
- Type7Record\r
- );\r
+ ConfigureCacheArchitectureInformation (\r
+ CacheLevel,\r
+ DataCacheType,\r
+ !SeparateCaches,\r
+ Type7Record\r
+ );\r
\r
// Allow the platform to fill in other information such as speed, SRAM type etc.\r
- if (!OemGetCacheInformation (ProcessorIndex, CacheLevel,\r
- DataCacheType, !SeparateCaches, Type7Record)) {\r
+ if (!OemGetCacheInformation (\r
+ ProcessorIndex,\r
+ CacheLevel,\r
+ DataCacheType,\r
+ !SeparateCaches,\r
+ Type7Record\r
+ ))\r
+ {\r
continue;\r
}\r
\r
SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
// Finally, install the table\r
- Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle,\r
- (EFI_SMBIOS_TABLE_HEADER *)Type7Record);\r
+ Status = mSmbios->Add (\r
+ mSmbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *)Type7Record\r
+ );\r
if (EFI_ERROR (Status)) {\r
continue;\r
}\r
**/\r
EFI_STATUS\r
AllocateType4AndSetProcessorInformationStrings (\r
- SMBIOS_TABLE_TYPE4 **Type4Record,\r
- UINT8 ProcessorIndex,\r
- BOOLEAN Populated\r
+ SMBIOS_TABLE_TYPE4 **Type4Record,\r
+ UINT8 ProcessorIndex,\r
+ BOOLEAN Populated\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_STRING_ID ProcessorManu;\r
- EFI_STRING_ID ProcessorVersion;\r
- EFI_STRING_ID SerialNumber;\r
- EFI_STRING_ID AssetTag;\r
- EFI_STRING_ID PartNumber;\r
- EFI_STRING ProcessorStr;\r
- EFI_STRING ProcessorManuStr;\r
- EFI_STRING ProcessorVersionStr;\r
- EFI_STRING SerialNumberStr;\r
- EFI_STRING AssetTagStr;\r
- EFI_STRING PartNumberStr;\r
- CHAR8 *OptionalStrStart;\r
- CHAR8 *StrStart;\r
- UINTN ProcessorStrLen;\r
- UINTN ProcessorManuStrLen;\r
- UINTN ProcessorVersionStrLen;\r
- UINTN SerialNumberStrLen;\r
- UINTN AssetTagStrLen;\r
- UINTN PartNumberStrLen;\r
- UINTN TotalSize;\r
- UINTN StringBufferSize;\r
+ EFI_STATUS Status;\r
+ EFI_STRING_ID ProcessorManu;\r
+ EFI_STRING_ID ProcessorVersion;\r
+ EFI_STRING_ID SerialNumber;\r
+ EFI_STRING_ID AssetTag;\r
+ EFI_STRING_ID PartNumber;\r
+ EFI_STRING ProcessorStr;\r
+ EFI_STRING ProcessorManuStr;\r
+ EFI_STRING ProcessorVersionStr;\r
+ EFI_STRING SerialNumberStr;\r
+ EFI_STRING AssetTagStr;\r
+ EFI_STRING PartNumberStr;\r
+ CHAR8 *OptionalStrStart;\r
+ CHAR8 *StrStart;\r
+ UINTN ProcessorStrLen;\r
+ UINTN ProcessorManuStrLen;\r
+ UINTN ProcessorVersionStrLen;\r
+ UINTN SerialNumberStrLen;\r
+ UINTN AssetTagStrLen;\r
+ UINTN PartNumberStrLen;\r
+ UINTN TotalSize;\r
+ UINTN StringBufferSize;\r
\r
Status = EFI_SUCCESS;\r
\r
AssetTagStr = NULL;\r
PartNumberStr = NULL;\r
\r
- ProcessorManu = STRING_TOKEN (STR_PROCESSOR_MANUFACTURE);\r
- ProcessorVersion = STRING_TOKEN (STR_PROCESSOR_VERSION);\r
- SerialNumber = STRING_TOKEN (STR_PROCESSOR_SERIAL_NUMBER);\r
- AssetTag = STRING_TOKEN (STR_PROCESSOR_ASSET_TAG);\r
- PartNumber = STRING_TOKEN (STR_PROCESSOR_PART_NUMBER);\r
+ ProcessorManu = STRING_TOKEN (STR_PROCESSOR_MANUFACTURE);\r
+ ProcessorVersion = STRING_TOKEN (STR_PROCESSOR_VERSION);\r
+ SerialNumber = STRING_TOKEN (STR_PROCESSOR_SERIAL_NUMBER);\r
+ AssetTag = STRING_TOKEN (STR_PROCESSOR_ASSET_TAG);\r
+ PartNumber = STRING_TOKEN (STR_PROCESSOR_PART_NUMBER);\r
\r
SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorManufacturer, ProcessorManu);\r
SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorVersion, ProcessorVersion);\r
\r
// Processor Designation\r
StringBufferSize = sizeof (CHAR16) * SMBIOS_STRING_MAX_LENGTH;\r
- ProcessorStr = AllocateZeroPool (StringBufferSize);\r
+ ProcessorStr = AllocateZeroPool (StringBufferSize);\r
if (ProcessorStr == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- ProcessorStrLen = UnicodeSPrint (ProcessorStr, StringBufferSize,\r
- L"CPU%02d", ProcessorIndex + 1);\r
+ ProcessorStrLen = UnicodeSPrint (\r
+ ProcessorStr,\r
+ StringBufferSize,\r
+ L"CPU%02d",\r
+ ProcessorIndex + 1\r
+ );\r
\r
// Processor Manufacture\r
- ProcessorManuStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorManu, NULL);\r
+ ProcessorManuStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorManu, NULL);\r
ProcessorManuStrLen = StrLen (ProcessorManuStr);\r
\r
// Processor Version\r
- ProcessorVersionStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorVersion, NULL);\r
+ ProcessorVersionStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorVersion, NULL);\r
ProcessorVersionStrLen = StrLen (ProcessorVersionStr);\r
\r
// Serial Number\r
- SerialNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, SerialNumber, NULL);\r
+ SerialNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, SerialNumber, NULL);\r
SerialNumberStrLen = StrLen (SerialNumberStr);\r
\r
// Asset Tag\r
- AssetTagStr = HiiGetPackageString (&gEfiCallerIdGuid, AssetTag, NULL);\r
+ AssetTagStr = HiiGetPackageString (&gEfiCallerIdGuid, AssetTag, NULL);\r
AssetTagStrLen = StrLen (AssetTagStr);\r
\r
// Part Number\r
- PartNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, PartNumber, NULL);\r
+ PartNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, PartNumber, NULL);\r
PartNumberStrLen = StrLen (PartNumberStr);\r
\r
TotalSize = sizeof (SMBIOS_TABLE_TYPE4) +\r
**/\r
EFI_STATUS\r
AddSmbiosProcessorTypeTable (\r
- IN UINTN ProcessorIndex\r
+ IN UINTN ProcessorIndex\r
)\r
{\r
- EFI_STATUS Status;\r
- SMBIOS_TABLE_TYPE4 *Type4Record;\r
- EFI_SMBIOS_HANDLE SmbiosHandle;\r
- EFI_SMBIOS_HANDLE L1CacheHandle;\r
- EFI_SMBIOS_HANDLE L2CacheHandle;\r
- EFI_SMBIOS_HANDLE L3CacheHandle;\r
- UINT8 *LegacyVoltage;\r
- PROCESSOR_STATUS_DATA ProcessorStatus;\r
- UINT64 *ProcessorId;\r
- PROCESSOR_CHARACTERISTIC_FLAGS ProcessorCharacteristics;\r
- OEM_MISC_PROCESSOR_DATA MiscProcessorData;\r
- BOOLEAN ProcessorPopulated;\r
-\r
- Type4Record = NULL;\r
-\r
- MiscProcessorData.Voltage = 0;\r
- MiscProcessorData.CurrentSpeed = 0;\r
- MiscProcessorData.CoreCount = 0;\r
- MiscProcessorData.CoresEnabled = 0;\r
- MiscProcessorData.ThreadCount = 0;\r
- MiscProcessorData.MaxSpeed = 0;\r
- L1CacheHandle = 0xFFFF;\r
- L2CacheHandle = 0xFFFF;\r
- L3CacheHandle = 0xFFFF;\r
+ EFI_STATUS Status;\r
+ SMBIOS_TABLE_TYPE4 *Type4Record;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ EFI_SMBIOS_HANDLE L1CacheHandle;\r
+ EFI_SMBIOS_HANDLE L2CacheHandle;\r
+ EFI_SMBIOS_HANDLE L3CacheHandle;\r
+ UINT8 *LegacyVoltage;\r
+ PROCESSOR_STATUS_DATA ProcessorStatus;\r
+ UINT64 *ProcessorId;\r
+ PROCESSOR_CHARACTERISTIC_FLAGS ProcessorCharacteristics;\r
+ OEM_MISC_PROCESSOR_DATA MiscProcessorData;\r
+ BOOLEAN ProcessorPopulated;\r
+\r
+ Type4Record = NULL;\r
+\r
+ MiscProcessorData.Voltage = 0;\r
+ MiscProcessorData.CurrentSpeed = 0;\r
+ MiscProcessorData.CoreCount = 0;\r
+ MiscProcessorData.CoresEnabled = 0;\r
+ MiscProcessorData.ThreadCount = 0;\r
+ MiscProcessorData.MaxSpeed = 0;\r
+ L1CacheHandle = 0xFFFF;\r
+ L2CacheHandle = 0xFFFF;\r
+ L3CacheHandle = 0xFFFF;\r
\r
ProcessorPopulated = OemIsProcessorPresent (ProcessorIndex);\r
\r
return Status;\r
}\r
\r
- OemGetProcessorInformation (ProcessorIndex,\r
- &ProcessorStatus,\r
- (PROCESSOR_CHARACTERISTIC_FLAGS*)\r
- &Type4Record->ProcessorCharacteristics,\r
- &MiscProcessorData);\r
+ OemGetProcessorInformation (\r
+ ProcessorIndex,\r
+ &ProcessorStatus,\r
+ (PROCESSOR_CHARACTERISTIC_FLAGS *)\r
+ &Type4Record->ProcessorCharacteristics,\r
+ &MiscProcessorData\r
+ );\r
\r
if (ProcessorPopulated) {\r
- AddSmbiosCacheTypeTable (ProcessorIndex, &L1CacheHandle,\r
- &L2CacheHandle, &L3CacheHandle);\r
+ AddSmbiosCacheTypeTable (\r
+ ProcessorIndex,\r
+ &L1CacheHandle,\r
+ &L2CacheHandle,\r
+ &L3CacheHandle\r
+ );\r
}\r
\r
- LegacyVoltage = (UINT8*)&Type4Record->Voltage;\r
-\r
- *LegacyVoltage = MiscProcessorData.Voltage;\r
- Type4Record->CurrentSpeed = MiscProcessorData.CurrentSpeed;\r
- Type4Record->MaxSpeed = MiscProcessorData.MaxSpeed;\r
- Type4Record->Status = ProcessorStatus.Data;\r
- Type4Record->L1CacheHandle = L1CacheHandle;\r
- Type4Record->L2CacheHandle = L2CacheHandle;\r
- Type4Record->L3CacheHandle = L3CacheHandle;\r
- Type4Record->CoreCount = MiscProcessorData.CoreCount;\r
- Type4Record->CoreCount2 = MiscProcessorData.CoreCount;\r
- Type4Record->EnabledCoreCount = MiscProcessorData.CoresEnabled;\r
- Type4Record->EnabledCoreCount2 = MiscProcessorData.CoresEnabled;\r
- Type4Record->ThreadCount = MiscProcessorData.ThreadCount;\r
- Type4Record->ThreadCount2 = MiscProcessorData.ThreadCount;\r
-\r
- Type4Record->CurrentSpeed = GetCpuFrequency (ProcessorIndex);\r
+ LegacyVoltage = (UINT8 *)&Type4Record->Voltage;\r
+\r
+ *LegacyVoltage = MiscProcessorData.Voltage;\r
+ Type4Record->CurrentSpeed = MiscProcessorData.CurrentSpeed;\r
+ Type4Record->MaxSpeed = MiscProcessorData.MaxSpeed;\r
+ Type4Record->Status = ProcessorStatus.Data;\r
+ Type4Record->L1CacheHandle = L1CacheHandle;\r
+ Type4Record->L2CacheHandle = L2CacheHandle;\r
+ Type4Record->L3CacheHandle = L3CacheHandle;\r
+ Type4Record->CoreCount = MiscProcessorData.CoreCount;\r
+ Type4Record->CoreCount2 = MiscProcessorData.CoreCount;\r
+ Type4Record->EnabledCoreCount = MiscProcessorData.CoresEnabled;\r
+ Type4Record->EnabledCoreCount2 = MiscProcessorData.CoresEnabled;\r
+ Type4Record->ThreadCount = MiscProcessorData.ThreadCount;\r
+ Type4Record->ThreadCount2 = MiscProcessorData.ThreadCount;\r
+\r
+ Type4Record->CurrentSpeed = GetCpuFrequency (ProcessorIndex);\r
Type4Record->ExternalClock =\r
(UINT16)(SmbiosGetExternalClockFrequency () / 1000 / 1000);\r
\r
- ProcessorId = (UINT64*)&Type4Record->ProcessorId;\r
+ ProcessorId = (UINT64 *)&Type4Record->ProcessorId;\r
*ProcessorId = SmbiosGetProcessorId ();\r
\r
- ProcessorCharacteristics = SmbiosGetProcessorCharacteristics ();\r
- Type4Record->ProcessorCharacteristics |= *((UINT64*)&ProcessorCharacteristics);\r
+ ProcessorCharacteristics = SmbiosGetProcessorCharacteristics ();\r
+ Type4Record->ProcessorCharacteristics |= *((UINT64 *)&ProcessorCharacteristics);\r
\r
- Type4Record->ProcessorFamily = SmbiosGetProcessorFamily ();\r
+ Type4Record->ProcessorFamily = SmbiosGetProcessorFamily ();\r
Type4Record->ProcessorFamily2 = SmbiosGetProcessorFamily2 ();\r
\r
SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
- Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle,\r
- (EFI_SMBIOS_TABLE_HEADER *)Type4Record);\r
+ Status = mSmbios->Add (\r
+ mSmbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *)Type4Record\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type04 Table Log Failed! %r \n",\r
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "[%a]:[%dL] Smbios Type04 Table Log Failed! %r \n",\r
+ __FUNCTION__,\r
+ DEBUG_LINE_NUMBER,\r
+ Status\r
+ ));\r
}\r
+\r
FreePool (Type4Record);\r
\r
return Status;\r
**/\r
EFI_STATUS\r
EFIAPI\r
-ProcessorSubClassEntryPoint(\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ProcessorSubClassEntryPoint (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 ProcessorIndex;\r
+ EFI_STATUS Status;\r
+ UINT32 ProcessorIndex;\r
\r
//\r
// Locate dependent protocols\r
//\r
- Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID**)&mSmbios);\r
+ Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID **)&mSmbios);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", Status));\r
return Status;\r
//\r
// Add our default strings to the HII database. They will be modified later.\r
//\r
- mHiiHandle = HiiAddPackages (&gEfiCallerIdGuid,\r
- NULL,\r
- ProcessorSubClassStrings,\r
- NULL,\r
- NULL\r
- );\r
+ mHiiHandle = HiiAddPackages (\r
+ &gEfiCallerIdGuid,\r
+ NULL,\r
+ ProcessorSubClassStrings,\r
+ NULL,\r
+ NULL\r
+ );\r
if (mHiiHandle == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
**/\r
BOOLEAN\r
SmbiosProcessorHasSeparateCaches (\r
- UINT8 CacheLevel\r
+ UINT8 CacheLevel\r
);\r
\r
/** Gets the size of the specified cache.\r
**/\r
UINT64\r
SmbiosProcessorGetCacheSize (\r
- IN UINT8 CacheLevel,\r
- IN BOOLEAN DataCache,\r
- IN BOOLEAN UnifiedCache\r
+ IN UINT8 CacheLevel,\r
+ IN BOOLEAN DataCache,\r
+ IN BOOLEAN UnifiedCache\r
);\r
\r
/** Gets the associativity of the specified cache.\r
**/\r
UINT32\r
SmbiosProcessorGetCacheAssociativity (\r
- IN UINT8 CacheLevel,\r
- IN BOOLEAN DataCache,\r
- IN BOOLEAN UnifiedCache\r
+ IN UINT8 CacheLevel,\r
+ IN BOOLEAN DataCache,\r
+ IN BOOLEAN UnifiedCache\r
);\r
\r
/** Returns a value for the Processor ID field that conforms to SMBIOS\r
@return Processor ID.\r
**/\r
UINT64\r
-SmbiosGetProcessorId (VOID);\r
+SmbiosGetProcessorId (\r
+ VOID\r
+ );\r
\r
/** Returns the external clock frequency.\r
\r
@return The external CPU clock frequency.\r
**/\r
UINTN\r
-SmbiosGetExternalClockFrequency (VOID);\r
+SmbiosGetExternalClockFrequency (\r
+ VOID\r
+ );\r
\r
/** Returns the SMBIOS ProcessorFamily field value.\r
\r
@return The value for the ProcessorFamily field.\r
**/\r
UINT8\r
-SmbiosGetProcessorFamily (VOID);\r
+SmbiosGetProcessorFamily (\r
+ VOID\r
+ );\r
\r
/** Returns the ProcessorFamily2 field value.\r
\r
@return The value for the ProcessorFamily2 field.\r
**/\r
UINT16\r
-SmbiosGetProcessorFamily2 (VOID);\r
+SmbiosGetProcessorFamily2 (\r
+ VOID\r
+ );\r
\r
/** Returns the SMBIOS Processor Characteristics.\r
\r
@return Processor Characteristics bitfield.\r
**/\r
PROCESSOR_CHARACTERISTIC_FLAGS\r
-SmbiosGetProcessorCharacteristics (VOID);\r
+SmbiosGetProcessorCharacteristics (\r
+ VOID\r
+ );\r
\r
#endif // SMBIOS_PROCESSOR_H_\r
**/\r
UINT64\r
SmbiosProcessorGetCacheSize (\r
- IN UINT8 CacheLevel,\r
- IN BOOLEAN DataCache,\r
- IN BOOLEAN UnifiedCache\r
-)\r
+ IN UINT8 CacheLevel,\r
+ IN BOOLEAN DataCache,\r
+ IN BOOLEAN UnifiedCache\r
+ )\r
{\r
- CCSIDR_DATA Ccsidr;\r
- CSSELR_DATA Csselr;\r
- BOOLEAN CcidxSupported;\r
- UINT64 CacheSize;\r
+ CCSIDR_DATA Ccsidr;\r
+ CSSELR_DATA Csselr;\r
+ BOOLEAN CcidxSupported;\r
+ UINT64 CacheSize;\r
\r
- Csselr.Data = 0;\r
+ Csselr.Data = 0;\r
Csselr.Bits.Level = CacheLevel - 1;\r
- Csselr.Bits.InD = (!DataCache && !UnifiedCache);\r
+ Csselr.Bits.InD = (!DataCache && !UnifiedCache);\r
\r
Ccsidr.Data = ReadCCSIDR (Csselr.Data);\r
\r
\r
if (CcidxSupported) {\r
CacheSize = (1 << (Ccsidr.BitsCcidxAA64.LineSize + 4)) *\r
- (Ccsidr.BitsCcidxAA64.Associativity + 1) *\r
- (Ccsidr.BitsCcidxAA64.NumSets + 1);\r
+ (Ccsidr.BitsCcidxAA64.Associativity + 1) *\r
+ (Ccsidr.BitsCcidxAA64.NumSets + 1);\r
} else {\r
CacheSize = (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) *\r
- (Ccsidr.BitsNonCcidx.Associativity + 1) *\r
- (Ccsidr.BitsNonCcidx.NumSets + 1);\r
+ (Ccsidr.BitsNonCcidx.Associativity + 1) *\r
+ (Ccsidr.BitsNonCcidx.NumSets + 1);\r
}\r
\r
return CacheSize;\r
**/\r
UINT32\r
SmbiosProcessorGetCacheAssociativity (\r
- IN UINT8 CacheLevel,\r
- IN BOOLEAN DataCache,\r
- IN BOOLEAN UnifiedCache\r
+ IN UINT8 CacheLevel,\r
+ IN BOOLEAN DataCache,\r
+ IN BOOLEAN UnifiedCache\r
)\r
{\r
- CCSIDR_DATA Ccsidr;\r
- CSSELR_DATA Csselr;\r
- BOOLEAN CcidxSupported;\r
- UINT32 Associativity;\r
+ CCSIDR_DATA Ccsidr;\r
+ CSSELR_DATA Csselr;\r
+ BOOLEAN CcidxSupported;\r
+ UINT32 Associativity;\r
\r
- Csselr.Data = 0;\r
+ Csselr.Data = 0;\r
Csselr.Bits.Level = CacheLevel - 1;\r
- Csselr.Bits.InD = (!DataCache && !UnifiedCache);\r
+ Csselr.Bits.InD = (!DataCache && !UnifiedCache);\r
\r
Ccsidr.Data = ReadCCSIDR (Csselr.Data);\r
\r
\r
return Associativity;\r
}\r
-\r
**/\r
UINT64\r
SmbiosProcessorGetCacheSize (\r
- IN UINT8 CacheLevel,\r
- IN BOOLEAN DataCache,\r
- IN BOOLEAN UnifiedCache\r
+ IN UINT8 CacheLevel,\r
+ IN BOOLEAN DataCache,\r
+ IN BOOLEAN UnifiedCache\r
)\r
{\r
- CCSIDR_DATA Ccsidr;\r
- CCSIDR2_DATA Ccsidr2;\r
- CSSELR_DATA Csselr;\r
- BOOLEAN CcidxSupported;\r
- UINT64 CacheSize;\r
+ CCSIDR_DATA Ccsidr;\r
+ CCSIDR2_DATA Ccsidr2;\r
+ CSSELR_DATA Csselr;\r
+ BOOLEAN CcidxSupported;\r
+ UINT64 CacheSize;\r
\r
// Read the CCSIDR register to get the cache architecture\r
- Csselr.Data = 0;\r
+ Csselr.Data = 0;\r
Csselr.Bits.Level = CacheLevel - 1;\r
- Csselr.Bits.InD = (!DataCache && !UnifiedCache);\r
+ Csselr.Bits.InD = (!DataCache && !UnifiedCache);\r
\r
Ccsidr.Data = ReadCCSIDR (Csselr.Data);\r
\r
\r
if (CcidxSupported) {\r
Ccsidr2.Data = ReadCCSIDR2 (Csselr.Data);\r
- CacheSize = (1 << (Ccsidr.BitsCcidxAA32.LineSize + 4)) *\r
- (Ccsidr.BitsCcidxAA32.Associativity + 1) *\r
- (Ccsidr2.Bits.NumSets + 1);\r
+ CacheSize = (1 << (Ccsidr.BitsCcidxAA32.LineSize + 4)) *\r
+ (Ccsidr.BitsCcidxAA32.Associativity + 1) *\r
+ (Ccsidr2.Bits.NumSets + 1);\r
} else {\r
CacheSize = (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) *\r
- (Ccsidr.BitsNonCcidx.Associativity + 1) *\r
- (Ccsidr.BitsNonCcidx.NumSets + 1);\r
+ (Ccsidr.BitsNonCcidx.Associativity + 1) *\r
+ (Ccsidr.BitsNonCcidx.NumSets + 1);\r
}\r
\r
return CacheSize;\r
**/\r
UINT32\r
SmbiosProcessorGetCacheAssociativity (\r
- IN UINT8 CacheLevel,\r
- IN BOOLEAN DataCache,\r
- IN BOOLEAN UnifiedCache\r
+ IN UINT8 CacheLevel,\r
+ IN BOOLEAN DataCache,\r
+ IN BOOLEAN UnifiedCache\r
)\r
{\r
CCSIDR_DATA Ccsidr;\r
UINT32 Associativity;\r
\r
// Read the CCSIDR register to get the cache architecture\r
- Csselr.Data = 0;\r
+ Csselr.Data = 0;\r
Csselr.Bits.Level = CacheLevel - 1;\r
- Csselr.Bits.InD = (!DataCache && !UnifiedCache);\r
+ Csselr.Bits.InD = (!DataCache && !UnifiedCache);\r
\r
Ccsidr.Data = ReadCCSIDR (Csselr.Data);\r
\r
\r
return Associativity;\r
}\r
-\r
VOID\r
)\r
{\r
- CLIDR_DATA Clidr;\r
- UINT8 CacheLevel;\r
- UINT8 MaxCacheLevel;\r
+ CLIDR_DATA Clidr;\r
+ UINT8 CacheLevel;\r
+ UINT8 MaxCacheLevel;\r
\r
MaxCacheLevel = 0;\r
\r
**/\r
BOOLEAN\r
SmbiosProcessorHasSeparateCaches (\r
- UINT8 CacheLevel\r
+ UINT8 CacheLevel\r
)\r
{\r
- CLIDR_CACHE_TYPE CacheType;\r
- CLIDR_DATA Clidr;\r
- BOOLEAN SeparateCaches;\r
+ CLIDR_CACHE_TYPE CacheType;\r
+ CLIDR_DATA Clidr;\r
+ BOOLEAN SeparateCaches;\r
\r
SeparateCaches = FALSE;\r
\r
VOID\r
)\r
{\r
- ARM_SMC_ARGS Args;\r
- INT32 SmcCallStatus;\r
- BOOLEAN Arm64SocIdSupported;\r
+ ARM_SMC_ARGS Args;\r
+ INT32 SmcCallStatus;\r
+ BOOLEAN Arm64SocIdSupported;\r
\r
Arm64SocIdSupported = FALSE;\r
\r
ArmCallSmc (&Args);\r
SmcCallStatus = (INT32)Args.Arg0;\r
\r
- if (SmcCallStatus < 0 || (SmcCallStatus >> 16) >= 1) {\r
+ if ((SmcCallStatus < 0) || ((SmcCallStatus >> 16) >= 1)) {\r
Args.Arg0 = SMCCC_ARCH_FEATURES;\r
Args.Arg1 = SMCCC_ARCH_SOC_ID;\r
ArmCallSmc (&Args);\r
**/\r
EFI_STATUS\r
SmbiosGetSmcArm64SocId (\r
- OUT INT32 *Jep106Code,\r
- OUT INT32 *SocRevision\r
+ OUT INT32 *Jep106Code,\r
+ OUT INT32 *SocRevision\r
)\r
{\r
ARM_SMC_ARGS Args;\r
VOID\r
)\r
{\r
- INT32 Jep106Code;\r
- INT32 SocRevision;\r
- UINT64 ProcessorId;\r
+ INT32 Jep106Code;\r
+ INT32 SocRevision;\r
+ UINT64 ProcessorId;\r
\r
if (HasSmcArm64SocId ()) {\r
SmbiosGetSmcArm64SocId (&Jep106Code, &SocRevision);\r
VOID\r
)\r
{\r
- UINTN MainIdRegister;\r
- UINT16 ProcessorFamily2;\r
+ UINTN MainIdRegister;\r
+ UINT16 ProcessorFamily2;\r
\r
MainIdRegister = ArmReadMidr ();\r
\r
if (((MainIdRegister >> 16) & 0xF) < 8) {\r
ProcessorFamily2 = ProcessorFamilyARM;\r
} else {\r
- if (sizeof (VOID*) == 4) {\r
+ if (sizeof (VOID *) == 4) {\r
ProcessorFamily2 = ProcessorFamilyARMv7;\r
} else {\r
ProcessorFamily2 = ProcessorFamilyARMv8;\r
VOID\r
)\r
{\r
- PROCESSOR_CHARACTERISTIC_FLAGS Characteristics;\r
+ PROCESSOR_CHARACTERISTIC_FLAGS Characteristics;\r
\r
ZeroMem (&Characteristics, sizeof (Characteristics));\r
\r
//\r
// Data table entry update function.\r
//\r
-typedef EFI_STATUS (EFIAPI SMBIOS_MISC_DATA_FUNCTION) (\r
+typedef EFI_STATUS (EFIAPI SMBIOS_MISC_DATA_FUNCTION)(\r
IN VOID *RecordData,\r
IN EFI_SMBIOS_PROTOCOL *Smbios\r
);\r
\r
-\r
//\r
// Data table entry definition.\r
//\r
//\r
// intermediate input data for SMBIOS record\r
//\r
- VOID *RecordData;\r
- SMBIOS_MISC_DATA_FUNCTION *Function;\r
+ VOID *RecordData;\r
+ SMBIOS_MISC_DATA_FUNCTION *Function;\r
} SMBIOS_MISC_DATA_TABLE;\r
\r
-\r
//\r
// SMBIOS table extern definitions\r
//\r
extern NAME1 NAME2 ## Data; \\r
extern SMBIOS_MISC_DATA_FUNCTION NAME3 ## Function;\r
\r
-\r
//\r
// SMBIOS data table entries\r
//\r
//\r
// Data Table Array Entries\r
//\r
-extern EFI_HII_HANDLE mSmbiosMiscHiiHandle;\r
+extern EFI_HII_HANDLE mSmbiosMiscHiiHandle;\r
\r
-typedef struct _SMBIOS_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING{\r
- UINT8 *LanguageSignature;\r
- EFI_STRING_ID InstallableLanguageLongString;\r
- EFI_STRING_ID InstallableLanguageAbbreviateString;\r
+typedef struct _SMBIOS_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING {\r
+ UINT8 *LanguageSignature;\r
+ EFI_STRING_ID InstallableLanguageLongString;\r
+ EFI_STRING_ID InstallableLanguageAbbreviateString;\r
} SMBIOS_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING;\r
\r
-\r
/**\r
Adds an SMBIOS record.\r
\r
**/\r
EFI_STATUS\r
SmbiosMiscAddRecord (\r
- IN UINT8 *Buffer,\r
- IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle OPTIONAL\r
+ IN UINT8 *Buffer,\r
+ IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle OPTIONAL\r
);\r
\r
/**\r
\r
**/\r
VOID\r
-SmbiosMiscGetLinkTypeHandle(\r
- IN UINT8 SmbiosType,\r
- OUT UINT16 **HandleArray,\r
- OUT UINTN *HandleCount\r
+SmbiosMiscGetLinkTypeHandle (\r
+ IN UINT8 SmbiosType,\r
+ OUT UINT16 **HandleArray,\r
+ OUT UINTN *HandleCount\r
);\r
\r
//\r
// Data Table Array\r
//\r
-extern SMBIOS_MISC_DATA_TABLE mSmbiosMiscDataTable[];\r
+extern SMBIOS_MISC_DATA_TABLE mSmbiosMiscDataTable[];\r
\r
//\r
// Data Table Array Entries\r
//\r
-extern UINTN mSmbiosMiscDataTableEntries;\r
-extern UINT8 mSmbiosMiscDxeStrings[];\r
+extern UINTN mSmbiosMiscDataTableEntries;\r
+extern UINT8 mSmbiosMiscDxeStrings[];\r
\r
#endif // SMBIOS_MISC_H_\r
\r
#include "SmbiosMisc.h"\r
\r
-SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE0,\r
- MiscBiosVendor,\r
- MiscBiosVendor)\r
-SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE1,\r
- MiscSystemManufacturer,\r
- MiscSystemManufacturer)\r
-SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE3,\r
- MiscChassisManufacturer,\r
- MiscChassisManufacturer)\r
-SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE2,\r
- MiscBaseBoardManufacturer,\r
- MiscBaseBoardManufacturer)\r
-SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE13,\r
- MiscNumberOfInstallableLanguages,\r
- MiscNumberOfInstallableLanguages)\r
-SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE32,\r
- MiscBootInformation,\r
- MiscBootInformation)\r
-\r
+SMBIOS_MISC_TABLE_EXTERNS (\r
+ SMBIOS_TABLE_TYPE0,\r
+ MiscBiosVendor,\r
+ MiscBiosVendor\r
+ )\r
+SMBIOS_MISC_TABLE_EXTERNS (\r
+ SMBIOS_TABLE_TYPE1,\r
+ MiscSystemManufacturer,\r
+ MiscSystemManufacturer\r
+ )\r
+SMBIOS_MISC_TABLE_EXTERNS (\r
+ SMBIOS_TABLE_TYPE3,\r
+ MiscChassisManufacturer,\r
+ MiscChassisManufacturer\r
+ )\r
+SMBIOS_MISC_TABLE_EXTERNS (\r
+ SMBIOS_TABLE_TYPE2,\r
+ MiscBaseBoardManufacturer,\r
+ MiscBaseBoardManufacturer\r
+ )\r
+SMBIOS_MISC_TABLE_EXTERNS (\r
+ SMBIOS_TABLE_TYPE13,\r
+ MiscNumberOfInstallableLanguages,\r
+ MiscNumberOfInstallableLanguages\r
+ )\r
+SMBIOS_MISC_TABLE_EXTERNS (\r
+ SMBIOS_TABLE_TYPE32,\r
+ MiscBootInformation,\r
+ MiscBootInformation\r
+ )\r
\r
SMBIOS_MISC_DATA_TABLE mSmbiosMiscDataTable[] = {\r
// Type0\r
- SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBiosVendor,\r
- MiscBiosVendor),\r
+ SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (\r
+ MiscBiosVendor,\r
+ MiscBiosVendor\r
+ ),\r
// Type1\r
- SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscSystemManufacturer,\r
- MiscSystemManufacturer),\r
+ SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (\r
+ MiscSystemManufacturer,\r
+ MiscSystemManufacturer\r
+ ),\r
// Type3\r
- SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscChassisManufacturer,\r
- MiscChassisManufacturer),\r
+ SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (\r
+ MiscChassisManufacturer,\r
+ MiscChassisManufacturer\r
+ ),\r
// Type2\r
- SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBaseBoardManufacturer,\r
- MiscBaseBoardManufacturer),\r
+ SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (\r
+ MiscBaseBoardManufacturer,\r
+ MiscBaseBoardManufacturer\r
+ ),\r
// Type13\r
- SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscNumberOfInstallableLanguages,\r
- MiscNumberOfInstallableLanguages),\r
+ SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (\r
+ MiscNumberOfInstallableLanguages,\r
+ MiscNumberOfInstallableLanguages\r
+ ),\r
// Type32\r
- SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBootInformation,\r
- MiscBootInformation),\r
+ SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (\r
+ MiscBootInformation,\r
+ MiscBootInformation\r
+ ),\r
};\r
\r
-\r
//\r
// Number of Data Table entries.\r
//\r
-UINTN mSmbiosMiscDataTableEntries =\r
+UINTN mSmbiosMiscDataTableEntries =\r
(sizeof (mSmbiosMiscDataTable)) / sizeof (SMBIOS_MISC_DATA_TABLE);\r
\r
#include "SmbiosMisc.h"\r
\r
-\r
STATIC EFI_HANDLE mSmbiosMiscImageHandle;\r
STATIC EFI_SMBIOS_PROTOCOL *mSmbiosMiscSmbios = NULL;\r
\r
-EFI_HII_HANDLE mSmbiosMiscHiiHandle;\r
+EFI_HII_HANDLE mSmbiosMiscHiiHandle;\r
\r
/**\r
Standard EFI driver point. This driver parses the mSmbiosMiscDataTable\r
**/\r
EFI_STATUS\r
EFIAPI\r
-SmbiosMiscEntryPoint(\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+SmbiosMiscEntryPoint (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- UINTN Index;\r
- EFI_STATUS EfiStatus;\r
+ UINTN Index;\r
+ EFI_STATUS EfiStatus;\r
\r
mSmbiosMiscImageHandle = ImageHandle;\r
\r
- EfiStatus = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL,\r
- (VOID**)&mSmbiosMiscSmbios);\r
+ EfiStatus = gBS->LocateProtocol (\r
+ &gEfiSmbiosProtocolGuid,\r
+ NULL,\r
+ (VOID **)&mSmbiosMiscSmbios\r
+ );\r
if (EFI_ERROR (EfiStatus)) {\r
DEBUG ((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", EfiStatus));\r
return EfiStatus;\r
}\r
\r
- mSmbiosMiscHiiHandle = HiiAddPackages (&gEfiCallerIdGuid,\r
- mSmbiosMiscImageHandle,\r
- SmbiosMiscDxeStrings,\r
- NULL\r
- );\r
+ mSmbiosMiscHiiHandle = HiiAddPackages (\r
+ &gEfiCallerIdGuid,\r
+ mSmbiosMiscImageHandle,\r
+ SmbiosMiscDxeStrings,\r
+ NULL\r
+ );\r
if (mSmbiosMiscHiiHandle == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
// If the entry have a function pointer, just log the data.\r
//\r
if (mSmbiosMiscDataTable[Index].Function != NULL) {\r
- EfiStatus = (*mSmbiosMiscDataTable[Index].Function)(mSmbiosMiscDataTable[Index].RecordData,\r
- mSmbiosMiscSmbios\r
- );\r
-\r
- if (EFI_ERROR(EfiStatus)) {\r
- DEBUG ((DEBUG_ERROR, "Misc smbios store error. Index=%d,"\r
- "ReturnStatus=%r\n", Index, EfiStatus));\r
+ EfiStatus = (*mSmbiosMiscDataTable[Index].Function)(\r
+ mSmbiosMiscDataTable[Index].RecordData,\r
+ mSmbiosMiscSmbios\r
+ );\r
+\r
+ if (EFI_ERROR (EfiStatus)) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "Misc smbios store error. Index=%d,"\r
+ "ReturnStatus=%r\n",\r
+ Index,\r
+ EfiStatus\r
+ ));\r
return EfiStatus;\r
}\r
}\r
return EfiStatus;\r
}\r
\r
-\r
/**\r
Adds an SMBIOS record.\r
\r
}\r
\r
Status = mSmbiosMiscSmbios->Add (\r
- mSmbiosMiscSmbios,\r
- NULL,\r
- &Handle,\r
- (EFI_SMBIOS_TABLE_HEADER *)Buffer\r
- );\r
+ mSmbiosMiscSmbios,\r
+ NULL,\r
+ &Handle,\r
+ (EFI_SMBIOS_TABLE_HEADER *)Buffer\r
+ );\r
\r
if (SmbiosHandle != NULL) {\r
*SmbiosHandle = Handle;\r
return Status;\r
}\r
\r
-\r
/** Fetches the number of handles of the specified SMBIOS type.\r
*\r
* @param SmbiosType The type of SMBIOS record to look for.\r
STATIC\r
UINTN\r
GetHandleCount (\r
- IN UINT8 SmbiosType\r
+ IN UINT8 SmbiosType\r
)\r
{\r
UINTN HandleCount;\r
\r
// Iterate through entries to get the number\r
do {\r
- Status = mSmbiosMiscSmbios->GetNext (mSmbiosMiscSmbios,\r
- &SmbiosHandle,\r
- &SmbiosType,\r
- &Record,\r
- NULL\r
- );\r
+ Status = mSmbiosMiscSmbios->GetNext (\r
+ mSmbiosMiscSmbios,\r
+ &SmbiosHandle,\r
+ &SmbiosType,\r
+ &Record,\r
+ NULL\r
+ );\r
\r
if (Status == EFI_SUCCESS) {\r
HandleCount++;\r
@param[out] *HandleCount Number of handles in the array\r
**/\r
VOID\r
-SmbiosMiscGetLinkTypeHandle(\r
- IN UINT8 SmbiosType,\r
- OUT SMBIOS_HANDLE **HandleArray,\r
- OUT UINTN *HandleCount\r
+SmbiosMiscGetLinkTypeHandle (\r
+ IN UINT8 SmbiosType,\r
+ OUT SMBIOS_HANDLE **HandleArray,\r
+ OUT UINTN *HandleCount\r
)\r
{\r
UINTN Index;\r
SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
\r
for (Index = 0; Index < (*HandleCount); Index++) {\r
- Status = mSmbiosMiscSmbios->GetNext (mSmbiosMiscSmbios,\r
- &SmbiosHandle,\r
- &SmbiosType,\r
- &Record,\r
- NULL\r
- );\r
+ Status = mSmbiosMiscSmbios->GetNext (\r
+ mSmbiosMiscSmbios,\r
+ &SmbiosHandle,\r
+ &SmbiosType,\r
+ &Record,\r
+ NULL\r
+ );\r
\r
if (!EFI_ERROR (Status)) {\r
(*HandleArray)[Index] = Record->Handle;\r
}\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
#include "SmbiosMisc.h"\r
\r
-\r
//\r
// Static (possibly build generated) Bios Vendor data.\r
//\r
-SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE0, MiscBiosVendor) = {\r
+SMBIOS_MISC_TABLE_DATA (SMBIOS_TABLE_TYPE0, MiscBiosVendor) = {\r
{ // Hdr\r
- EFI_SMBIOS_TYPE_BIOS_INFORMATION, // Type,\r
- 0, // Length,\r
- 0 // Handle\r
+ EFI_SMBIOS_TYPE_BIOS_INFORMATION, // Type,\r
+ 0, // Length,\r
+ 0 // Handle\r
},\r
1, // Vendor\r
2, // BiosVersion\r
3, // BiosReleaseDate\r
0, // BiosSize\r
{ // BiosCharacteristics\r
- 0, // Reserved :2\r
- 0, // Unknown :1\r
- 0, // BiosCharacteristicsNotSupported :1\r
- 0, // IsaIsSupported :1\r
- 0, // McaIsSupported :1\r
- 0, // EisaIsSupported :1\r
- 1, // PciIsSupported :1\r
- 0, // PcmciaIsSupported :1\r
- 1, // PlugAndPlayIsSupported :1\r
- 0, // ApmIsSupported :1\r
- 1, // BiosIsUpgradable :1\r
- 1, // BiosShadowingAllowed :1\r
- 0, // VlVesaIsSupported :1\r
- 0, // EscdSupportIsAvailable :1\r
- 1, // BootFromCdIsSupported :1\r
- 1, // SelectableBootIsSupported :1\r
- 0, // RomBiosIsSocketed :1\r
- 0, // BootFromPcmciaIsSupported :1\r
- 0, // EDDSpecificationIsSupported :1\r
- 0, // JapaneseNecFloppyIsSupported :1\r
- 0, // JapaneseToshibaFloppyIsSupported :1\r
- 0, // Floppy525_360IsSupported :1\r
- 0, // Floppy525_12IsSupported :1\r
- 0, // Floppy35_720IsSupported :1\r
- 0, // Floppy35_288IsSupported :1\r
- 0, // PrintScreenIsSupported :1\r
- 0, // Keyboard8042IsSupported :1\r
- 0, // SerialIsSupported :1\r
- 0, // PrinterIsSupported :1\r
- 0, // CgaMonoIsSupported :1\r
- 0, // NecPc98 :1\r
- 0 // ReservedForVendor :32\r
+ 0, // Reserved :2\r
+ 0, // Unknown :1\r
+ 0, // BiosCharacteristicsNotSupported :1\r
+ 0, // IsaIsSupported :1\r
+ 0, // McaIsSupported :1\r
+ 0, // EisaIsSupported :1\r
+ 1, // PciIsSupported :1\r
+ 0, // PcmciaIsSupported :1\r
+ 1, // PlugAndPlayIsSupported :1\r
+ 0, // ApmIsSupported :1\r
+ 1, // BiosIsUpgradable :1\r
+ 1, // BiosShadowingAllowed :1\r
+ 0, // VlVesaIsSupported :1\r
+ 0, // EscdSupportIsAvailable :1\r
+ 1, // BootFromCdIsSupported :1\r
+ 1, // SelectableBootIsSupported :1\r
+ 0, // RomBiosIsSocketed :1\r
+ 0, // BootFromPcmciaIsSupported :1\r
+ 0, // EDDSpecificationIsSupported :1\r
+ 0, // JapaneseNecFloppyIsSupported :1\r
+ 0, // JapaneseToshibaFloppyIsSupported :1\r
+ 0, // Floppy525_360IsSupported :1\r
+ 0, // Floppy525_12IsSupported :1\r
+ 0, // Floppy35_720IsSupported :1\r
+ 0, // Floppy35_288IsSupported :1\r
+ 0, // PrintScreenIsSupported :1\r
+ 0, // Keyboard8042IsSupported :1\r
+ 0, // SerialIsSupported :1\r
+ 0, // PrinterIsSupported :1\r
+ 0, // CgaMonoIsSupported :1\r
+ 0, // NecPc98 :1\r
+ 0 // ReservedForVendor :32\r
},\r
\r
{\r
// 0, // Boot1394IsSupported :1\r
// 0 // SmartBatteryIsSupported :1\r
// },\r
- 0x0C //BIOSCharacteristicsExtensionBytes[1]\r
+ 0x0C // BIOSCharacteristicsExtensionBytes[1]\r
// { //SystemReserved\r
// 0, //BiosBootSpecIsSupported :1\r
// 0, //FunctionKeyNetworkBootIsSupported :1\r
// 0 //ExtensionByte2Reserved :3\r
// },\r
},\r
- 0xFF, // SystemBiosMajorRelease;\r
- 0xFF, // SystemBiosMinorRelease;\r
+ 0xFF, // SystemBiosMajorRelease;\r
+ 0xFF, // SystemBiosMinorRelease;\r
0xFF, // EmbeddedControllerFirmwareMajorRelease;\r
0xFF // EmbeddedControllerFirmwareMinorRelease;\r
};\r
\r
#include "SmbiosMisc.h"\r
\r
-\r
typedef struct {\r
- CONST CHAR8* MonthStr;\r
- UINT32 MonthInt;\r
+ CONST CHAR8 *MonthStr;\r
+ UINT32 MonthInt;\r
} MONTH_DESCRIPTION;\r
\r
STATIC CONST\r
-MONTH_DESCRIPTION mMonthDescription[] = {\r
- { "Jan", 1 },\r
- { "Feb", 2 },\r
- { "Mar", 3 },\r
- { "Apr", 4 },\r
- { "May", 5 },\r
- { "Jun", 6 },\r
- { "Jul", 7 },\r
- { "Aug", 8 },\r
- { "Sep", 9 },\r
+MONTH_DESCRIPTION mMonthDescription[] = {\r
+ { "Jan", 1 },\r
+ { "Feb", 2 },\r
+ { "Mar", 3 },\r
+ { "Apr", 4 },\r
+ { "May", 5 },\r
+ { "Jun", 6 },\r
+ { "Jul", 7 },\r
+ { "Aug", 8 },\r
+ { "Sep", 9 },\r
{ "Oct", 10 },\r
{ "Nov", 11 },\r
{ "Dec", 12 },\r
- { "???", 1 }, // Use 1 as default month\r
+ { "???", 1 }, // Use 1 as default month\r
};\r
\r
/**\r
IN UINTN Value\r
)\r
{\r
- UINT8 Size;\r
+ UINT8 Size;\r
\r
Size = ((Value + (SIZE_64KB - 1)) >> 16);\r
\r
**/\r
VOID\r
GetReleaseTime (\r
- OUT EFI_TIME *Time\r
+ OUT EFI_TIME *Time\r
)\r
{\r
- CONST CHAR8 *ReleaseDate = __DATE__;\r
- CONST CHAR8 *ReleaseTime = __TIME__;\r
- UINTN i;\r
+ CONST CHAR8 *ReleaseDate = __DATE__;\r
+ CONST CHAR8 *ReleaseTime = __TIME__;\r
+ UINTN i;\r
\r
for (i = 0; i < 12; i++) {\r
if (AsciiStrnCmp (ReleaseDate, mMonthDescription[i].MonthStr, 3) == 0) {\r
}\r
}\r
\r
- Time->Month = mMonthDescription[i].MonthInt;\r
- Time->Day = AsciiStrDecimalToUintn (ReleaseDate + 4);\r
- Time->Year = AsciiStrDecimalToUintn (ReleaseDate + 7);\r
- Time->Hour = AsciiStrDecimalToUintn (ReleaseTime);\r
+ Time->Month = mMonthDescription[i].MonthInt;\r
+ Time->Day = AsciiStrDecimalToUintn (ReleaseDate + 4);\r
+ Time->Year = AsciiStrDecimalToUintn (ReleaseDate + 7);\r
+ Time->Hour = AsciiStrDecimalToUintn (ReleaseTime);\r
Time->Minute = AsciiStrDecimalToUintn (ReleaseTime + 3);\r
Time->Second = AsciiStrDecimalToUintn (ReleaseTime + 6);\r
}\r
VOID\r
)\r
{\r
- CHAR16 *ReleaseDate;\r
- EFI_TIME BuildTime;\r
+ CHAR16 *ReleaseDate;\r
+ EFI_TIME BuildTime;\r
\r
ReleaseDate = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);\r
if (ReleaseDate == NULL) {\r
- return NULL;\r
+ return NULL;\r
}\r
\r
GetReleaseTime (&BuildTime);\r
\r
- (VOID)UnicodeSPrintAsciiFormat (ReleaseDate,\r
- (sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH,\r
- "%02d/%02d/%4d",\r
- BuildTime.Month,\r
- BuildTime.Day,\r
- BuildTime.Year\r
- );\r
+ (VOID)UnicodeSPrintAsciiFormat (\r
+ ReleaseDate,\r
+ (sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH,\r
+ "%02d/%02d/%4d",\r
+ BuildTime.Month,\r
+ BuildTime.Day,\r
+ BuildTime.Year\r
+ );\r
\r
return ReleaseDate;\r
}\r
VOID\r
)\r
{\r
- CHAR16 *ReleaseString;\r
+ CHAR16 *ReleaseString;\r
\r
ReleaseString = (CHAR16 *)FixedPcdGetPtr (PcdFirmwareVersionString);\r
\r
return ReleaseString;\r
}\r
\r
-\r
/**\r
This function makes boot time changes to the contents of the\r
MiscBiosVendor (Type 0) record.\r
@retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.\r
\r
**/\r
-SMBIOS_MISC_TABLE_FUNCTION (MiscBiosVendor)\r
-{\r
- CHAR8 *OptionalStrStart;\r
- CHAR8 *StrStart;\r
- UINTN VendorStrLen;\r
- UINTN VerStrLen;\r
- UINTN DateStrLen;\r
- UINTN BiosPhysicalSize;\r
- CHAR16 *Vendor;\r
- CHAR16 *Version;\r
- CHAR16 *ReleaseDate;\r
- CHAR16 *Char16String;\r
- EFI_STATUS Status;\r
- EFI_STRING_ID TokenToUpdate;\r
- EFI_STRING_ID TokenToGet;\r
- SMBIOS_TABLE_TYPE0 *SmbiosRecord;\r
- SMBIOS_TABLE_TYPE0 *InputData;\r
+SMBIOS_MISC_TABLE_FUNCTION (MiscBiosVendor) {\r
+ CHAR8 *OptionalStrStart;\r
+ CHAR8 *StrStart;\r
+ UINTN VendorStrLen;\r
+ UINTN VerStrLen;\r
+ UINTN DateStrLen;\r
+ UINTN BiosPhysicalSize;\r
+ CHAR16 *Vendor;\r
+ CHAR16 *Version;\r
+ CHAR16 *ReleaseDate;\r
+ CHAR16 *Char16String;\r
+ EFI_STATUS Status;\r
+ EFI_STRING_ID TokenToUpdate;\r
+ EFI_STRING_ID TokenToGet;\r
+ SMBIOS_TABLE_TYPE0 *SmbiosRecord;\r
+ SMBIOS_TABLE_TYPE0 *InputData;\r
\r
//\r
// First check for invalid parameters.\r
\r
InputData = (SMBIOS_TABLE_TYPE0 *)RecordData;\r
\r
- Vendor = (CHAR16 *) PcdGetPtr (PcdFirmwareVendor);\r
+ Vendor = (CHAR16 *)PcdGetPtr (PcdFirmwareVendor);\r
\r
if (StrLen (Vendor) > 0) {\r
TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VENDOR);\r
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Vendor, NULL);\r
}\r
\r
- Version = GetBiosVersion();\r
+ Version = GetBiosVersion ();\r
\r
if (StrLen (Version) > 0) {\r
TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);\r
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Version, NULL);\r
} else {\r
- Version = (CHAR16 *) PcdGetPtr (PcdFirmwareVersionString);\r
+ Version = (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString);\r
if (StrLen (Version) > 0) {\r
TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);\r
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Version, NULL);\r
}\r
\r
Char16String = GetBiosReleaseDate ();\r
- if (StrLen(Char16String) > 0) {\r
+ if (StrLen (Char16String) > 0) {\r
TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);\r
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Char16String, NULL);\r
}\r
\r
- TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR);\r
- Vendor = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR);\r
+ Vendor = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
VendorStrLen = StrLen (Vendor);\r
\r
TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION);\r
- Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
- VerStrLen = StrLen (Version);\r
+ Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ VerStrLen = StrLen (Version);\r
\r
- TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);\r
ReleaseDate = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
- DateStrLen = StrLen (ReleaseDate);\r
+ DateStrLen = StrLen (ReleaseDate);\r
\r
//\r
// Now update the BiosPhysicalSize\r
//\r
// Two zeros following the last string.\r
//\r
- SmbiosRecord = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 +\r
- VerStrLen + 1 +\r
- DateStrLen + 1 + 1);\r
+ SmbiosRecord = AllocateZeroPool (\r
+ sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 +\r
+ VerStrLen + 1 +\r
+ DateStrLen + 1 + 1\r
+ );\r
if (SmbiosRecord == NULL) {\r
Status = EFI_OUT_OF_RESOURCES;\r
goto Exit;\r
\r
(VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE0));\r
\r
- SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0);\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0);\r
SmbiosRecord->BiosSegment = (UINT16)(FixedPcdGet32 (PcdFdBaseAddress) / SIZE_64KB);\r
if (BiosPhysicalSize < SIZE_16MB) {\r
SmbiosRecord->BiosSize = Base2ToByteWith64KUnit (BiosPhysicalSize) - 1;\r
}\r
}\r
\r
- SmbiosRecord->SystemBiosMajorRelease = (UINT8) (PcdGet16 (PcdSystemBiosRelease) >> 8);\r
- SmbiosRecord->SystemBiosMinorRelease = (UINT8) (PcdGet16 (PcdSystemBiosRelease) & 0xFF);\r
+ SmbiosRecord->SystemBiosMajorRelease = (UINT8)(PcdGet16 (PcdSystemBiosRelease) >> 8);\r
+ SmbiosRecord->SystemBiosMinorRelease = (UINT8)(PcdGet16 (PcdSystemBiosRelease) & 0xFF);\r
\r
SmbiosRecord->EmbeddedControllerFirmwareMajorRelease = (UINT16)\r
- (PcdGet16 (PcdEmbeddedControllerFirmwareRelease) >> 8);\r
+ (PcdGet16 (PcdEmbeddedControllerFirmwareRelease) >> 8);\r
SmbiosRecord->EmbeddedControllerFirmwareMinorRelease = (UINT16)\r
- (PcdGet16 (PcdEmbeddedControllerFirmwareRelease) & 0xFF);\r
+ (PcdGet16 (PcdEmbeddedControllerFirmwareRelease) & 0xFF);\r
\r
OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
UnicodeStrToAsciiStrS (Vendor, OptionalStrStart, VendorStrLen + 1);\r
//\r
// Now we have got the full smbios record, call smbios protocol to add this record.\r
//\r
- Status = SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL);\r
+ Status = SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type00 Table Log Failed! %r \n",\r
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "[%a]:[%dL] Smbios Type00 Table Log Failed! %r \n",\r
+ __FUNCTION__,\r
+ DEBUG_LINE_NUMBER,\r
+ Status\r
+ ));\r
}\r
\r
FreePool (SmbiosRecord);\r
\r
#include "SmbiosMisc.h"\r
\r
-\r
//\r
// Static (possibly build generated) System Manufacturer data.\r
//\r
-SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE1, MiscSystemManufacturer) = {\r
+SMBIOS_MISC_TABLE_DATA (SMBIOS_TABLE_TYPE1, MiscSystemManufacturer) = {\r
{ // Hdr\r
- EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type,\r
- 0, // Length,\r
- 0 // Handle\r
+ EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type,\r
+ 0, // Length,\r
+ 0 // Handle\r
},\r
1, // Manufacturer\r
2, // ProductName\r
3, // Version\r
4, // SerialNumber\r
{ // Uuid\r
- 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\r
+ 0x00000000, 0x0000, 0x0000, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\r
},\r
SystemWakeupTypePowerSwitch, // SystemWakeupType\r
5, // SKUNumber,\r
@retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.\r
\r
**/\r
-SMBIOS_MISC_TABLE_FUNCTION(MiscSystemManufacturer)\r
-{\r
- CHAR8 *OptionalStrStart;\r
- CHAR8 *StrStart;\r
- UINTN ManuStrLen;\r
- UINTN VerStrLen;\r
- UINTN PdNameStrLen;\r
- UINTN SerialNumStrLen;\r
- UINTN SKUNumStrLen;\r
- UINTN FamilyStrLen;\r
- UINTN RecordLength;\r
- EFI_STRING Manufacturer;\r
- EFI_STRING ProductName;\r
- EFI_STRING Version;\r
- EFI_STRING SerialNumber;\r
- EFI_STRING SKUNumber;\r
- EFI_STRING Family;\r
- EFI_STRING_ID TokenToGet;\r
- SMBIOS_TABLE_TYPE1 *SmbiosRecord;\r
- SMBIOS_TABLE_TYPE1 *InputData;\r
- EFI_STATUS Status;\r
- EFI_STRING_ID TokenToUpdate;\r
- CHAR16 *Product;\r
- CHAR16 *pVersion;\r
+SMBIOS_MISC_TABLE_FUNCTION (MiscSystemManufacturer) {\r
+ CHAR8 *OptionalStrStart;\r
+ CHAR8 *StrStart;\r
+ UINTN ManuStrLen;\r
+ UINTN VerStrLen;\r
+ UINTN PdNameStrLen;\r
+ UINTN SerialNumStrLen;\r
+ UINTN SKUNumStrLen;\r
+ UINTN FamilyStrLen;\r
+ UINTN RecordLength;\r
+ EFI_STRING Manufacturer;\r
+ EFI_STRING ProductName;\r
+ EFI_STRING Version;\r
+ EFI_STRING SerialNumber;\r
+ EFI_STRING SKUNumber;\r
+ EFI_STRING Family;\r
+ EFI_STRING_ID TokenToGet;\r
+ SMBIOS_TABLE_TYPE1 *SmbiosRecord;\r
+ SMBIOS_TABLE_TYPE1 *InputData;\r
+ EFI_STATUS Status;\r
+ EFI_STRING_ID TokenToUpdate;\r
+ CHAR16 *Product;\r
+ CHAR16 *pVersion;\r
\r
Status = EFI_SUCCESS;\r
\r
\r
InputData = (SMBIOS_TABLE_TYPE1 *)RecordData;\r
\r
- Product = (CHAR16 *) PcdGetPtr (PcdSystemProductName);\r
+ Product = (CHAR16 *)PcdGetPtr (PcdSystemProductName);\r
if (StrLen (Product) > 0) {\r
TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME);\r
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Product, NULL);\r
}\r
\r
- pVersion = (CHAR16 *) PcdGetPtr (PcdSystemVersion);\r
+ pVersion = (CHAR16 *)PcdGetPtr (PcdSystemVersion);\r
if (StrLen (pVersion) > 0) {\r
TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);\r
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, pVersion, NULL);\r
}\r
\r
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,\r
- STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER),\r
- SerialNumType01);\r
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,\r
- STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER),\r
- SystemManufacturerType01);\r
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,\r
- STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER),\r
- SkuNumberType01);\r
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,\r
- STRING_TOKEN (STR_MISC_SYSTEM_FAMILY),\r
- FamilyType01);\r
+ OemUpdateSmbiosInfo (\r
+ mSmbiosMiscHiiHandle,\r
+ STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER),\r
+ SerialNumType01\r
+ );\r
+ OemUpdateSmbiosInfo (\r
+ mSmbiosMiscHiiHandle,\r
+ STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER),\r
+ SystemManufacturerType01\r
+ );\r
+ OemUpdateSmbiosInfo (\r
+ mSmbiosMiscHiiHandle,\r
+ STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER),\r
+ SkuNumberType01\r
+ );\r
+ OemUpdateSmbiosInfo (\r
+ mSmbiosMiscHiiHandle,\r
+ STRING_TOKEN (STR_MISC_SYSTEM_FAMILY),\r
+ FamilyType01\r
+ );\r
\r
TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER);\r
Manufacturer = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
\r
SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE1);\r
\r
- CopyGuid(&SmbiosRecord->Uuid, &InputData->Uuid);\r
+ CopyGuid (&SmbiosRecord->Uuid, &InputData->Uuid);\r
\r
OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
UnicodeStrToAsciiStrS (Manufacturer, OptionalStrStart, ManuStrLen + 1);\r
StrStart = OptionalStrStart + ManuStrLen + 1;\r
- UnicodeStrToAsciiStrS (ProductName, StrStart, PdNameStrLen + 1);\r
+ UnicodeStrToAsciiStrS (ProductName, StrStart, PdNameStrLen + 1);\r
StrStart += PdNameStrLen + 1;\r
UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1);\r
StrStart += VerStrLen + 1;\r
//\r
// Now we have got the full smbios record, call smbios protocol to add this record.\r
//\r
- Status = SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL);\r
+ Status = SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type01 Table Log Failed! %r \n",\r
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "[%a]:[%dL] Smbios Type01 Table Log Failed! %r \n",\r
+ __FUNCTION__,\r
+ DEBUG_LINE_NUMBER,\r
+ Status\r
+ ));\r
}\r
\r
FreePool (SmbiosRecord);\r
//\r
// Static (possibly build generated) Chassis Manufacturer data.\r
//\r
-SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE2, MiscBaseBoardManufacturer) = {\r
+SMBIOS_MISC_TABLE_DATA (SMBIOS_TABLE_TYPE2, MiscBaseBoardManufacturer) = {\r
{ // Hdr\r
EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // Type,\r
0, // Length,\r
\r
#include "SmbiosMisc.h"\r
\r
-\r
/**\r
This function makes boot time changes to the contents of the\r
MiscBaseBoardManufacturer (Type 2) record.\r
@retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.\r
\r
**/\r
-SMBIOS_MISC_TABLE_FUNCTION(MiscBaseBoardManufacturer)\r
-{\r
- CHAR8 *OptionalStrStart;\r
- CHAR8 *StrStart;\r
- UINTN RecordLength;\r
- UINTN ManuStrLen;\r
- UINTN ProductNameStrLen;\r
- UINTN VerStrLen;\r
- UINTN SerialNumStrLen;\r
- UINTN AssetTagStrLen;\r
- UINTN ChassisLocaStrLen;\r
- UINTN HandleCount;\r
- UINT16 *HandleArray;\r
- CHAR16 *BaseBoardManufacturer;\r
- CHAR16 *BaseBoardProductName;\r
- CHAR16 *Version;\r
- EFI_STRING SerialNumber;\r
- EFI_STRING AssetTag;\r
- EFI_STRING ChassisLocation;\r
- EFI_STRING_ID TokenToGet;\r
- SMBIOS_TABLE_TYPE2 *SmbiosRecord;\r
- SMBIOS_TABLE_TYPE2 *InputData;\r
- EFI_STATUS Status;\r
-\r
- EFI_STRING_ID TokenToUpdate;\r
+SMBIOS_MISC_TABLE_FUNCTION (MiscBaseBoardManufacturer) {\r
+ CHAR8 *OptionalStrStart;\r
+ CHAR8 *StrStart;\r
+ UINTN RecordLength;\r
+ UINTN ManuStrLen;\r
+ UINTN ProductNameStrLen;\r
+ UINTN VerStrLen;\r
+ UINTN SerialNumStrLen;\r
+ UINTN AssetTagStrLen;\r
+ UINTN ChassisLocaStrLen;\r
+ UINTN HandleCount;\r
+ UINT16 *HandleArray;\r
+ CHAR16 *BaseBoardManufacturer;\r
+ CHAR16 *BaseBoardProductName;\r
+ CHAR16 *Version;\r
+ EFI_STRING SerialNumber;\r
+ EFI_STRING AssetTag;\r
+ EFI_STRING ChassisLocation;\r
+ EFI_STRING_ID TokenToGet;\r
+ SMBIOS_TABLE_TYPE2 *SmbiosRecord;\r
+ SMBIOS_TABLE_TYPE2 *InputData;\r
+ EFI_STATUS Status;\r
+\r
+ EFI_STRING_ID TokenToUpdate;\r
\r
HandleCount = 0;\r
HandleArray = NULL;\r
- InputData = NULL;\r
+ InputData = NULL;\r
\r
//\r
// First check for invalid parameters.\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- InputData = (SMBIOS_TABLE_TYPE2*)RecordData;\r
+ InputData = (SMBIOS_TABLE_TYPE2 *)RecordData;\r
\r
- BaseBoardManufacturer = (CHAR16 *) PcdGetPtr (PcdBaseBoardManufacturer);\r
+ BaseBoardManufacturer = (CHAR16 *)PcdGetPtr (PcdBaseBoardManufacturer);\r
if (StrLen (BaseBoardManufacturer) > 0) {\r
TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER);\r
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, BaseBoardManufacturer, NULL);\r
}\r
\r
- BaseBoardProductName = (CHAR16 *) PcdGetPtr (PcdBaseBoardProductName);\r
+ BaseBoardProductName = (CHAR16 *)PcdGetPtr (PcdBaseBoardProductName);\r
if (StrLen (BaseBoardProductName) > 0) {\r
TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME);\r
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, BaseBoardProductName, NULL);\r
}\r
\r
- Version = (CHAR16 *) PcdGetPtr (PcdBaseBoardVersion);\r
+ Version = (CHAR16 *)PcdGetPtr (PcdBaseBoardVersion);\r
if (StrLen (Version) > 0) {\r
TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION);\r
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Version, NULL);\r
}\r
\r
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,\r
+ OemUpdateSmbiosInfo (\r
+ mSmbiosMiscHiiHandle,\r
STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG),\r
AssertTagType02\r
);\r
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,\r
+ OemUpdateSmbiosInfo (\r
+ mSmbiosMiscHiiHandle,\r
STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER),\r
SerialNumberType02\r
);\r
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,\r
+ OemUpdateSmbiosInfo (\r
+ mSmbiosMiscHiiHandle,\r
STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER),\r
BoardManufacturerType02\r
);\r
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,\r
+ OemUpdateSmbiosInfo (\r
+ mSmbiosMiscHiiHandle,\r
STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER),\r
SerialNumberType02\r
);\r
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,\r
+ OemUpdateSmbiosInfo (\r
+ mSmbiosMiscHiiHandle,\r
STRING_TOKEN (STR_MISC_BASE_BOARD_SKU_NUMBER),\r
SerialNumberType02\r
);\r
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,\r
+ OemUpdateSmbiosInfo (\r
+ mSmbiosMiscHiiHandle,\r
STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION),\r
ChassisLocationType02\r
);\r
\r
- TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER);\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER);\r
BaseBoardManufacturer = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
- ManuStrLen = StrLen (BaseBoardManufacturer);\r
+ ManuStrLen = StrLen (BaseBoardManufacturer);\r
\r
- TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME);\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME);\r
BaseBoardProductName = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
- ProductNameStrLen = StrLen (BaseBoardProductName);\r
+ ProductNameStrLen = StrLen (BaseBoardProductName);\r
\r
TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION);\r
- Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
- VerStrLen = StrLen (Version);\r
+ Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ VerStrLen = StrLen (Version);\r
\r
- TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER);\r
- SerialNumber = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER);\r
+ SerialNumber = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
SerialNumStrLen = StrLen (SerialNumber);\r
\r
- TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG);\r
- AssetTag = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG);\r
+ AssetTag = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
AssetTagStrLen = StrLen (AssetTag);\r
\r
- TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION);\r
- ChassisLocation = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION);\r
+ ChassisLocation = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
ChassisLocaStrLen = StrLen (ChassisLocation);\r
\r
//\r
}\r
\r
(VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE2));\r
- SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE2);\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE2);\r
\r
//\r
// Update Contained objects Handle\r
//\r
SmbiosRecord->NumberOfContainedObjectHandles = 0;\r
- SmbiosMiscGetLinkTypeHandle (EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, &HandleArray,\r
- &HandleCount);\r
+ SmbiosMiscGetLinkTypeHandle (\r
+ EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE,\r
+ &HandleArray,\r
+ &HandleCount\r
+ );\r
// It's assumed there's at most a single chassis\r
ASSERT (HandleCount < 2);\r
if (HandleCount > 0) {\r
\r
Status = SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type02 Table Log Failed! %r \n",\r
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "[%a]:[%dL] Smbios Type02 Table Log Failed! %r \n",\r
+ __FUNCTION__,\r
+ DEBUG_LINE_NUMBER,\r
+ Status\r
+ ));\r
}\r
\r
FreePool (SmbiosRecord);\r
\r
#include "SmbiosMisc.h"\r
\r
-\r
//\r
// Static (possibly build generated) Chassis Manufacturer data.\r
//\r
-SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE3, MiscChassisManufacturer) = {\r
+SMBIOS_MISC_TABLE_DATA (SMBIOS_TABLE_TYPE3, MiscChassisManufacturer) = {\r
{ // Hdr\r
EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // Type,\r
0, // Length,\r
@retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.\r
\r
**/\r
-SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)\r
-{\r
- CHAR8 *OptionalStrStart;\r
- CHAR8 *StrStart;\r
- UINT8 *SkuNumberField;\r
- UINTN RecordLength;\r
- UINTN ManuStrLen;\r
- UINTN VerStrLen;\r
- UINTN AssertTagStrLen;\r
- UINTN SerialNumStrLen;\r
- UINTN ChaNumStrLen;\r
- EFI_STRING Manufacturer;\r
- EFI_STRING Version;\r
- EFI_STRING SerialNumber;\r
- EFI_STRING AssertTag;\r
- EFI_STRING ChassisSkuNumber;\r
- EFI_STRING_ID TokenToGet;\r
- SMBIOS_TABLE_TYPE3 *SmbiosRecord;\r
- SMBIOS_TABLE_TYPE3 *InputData;\r
- EFI_STATUS Status;\r
-\r
- UINT8 ContainedElementCount;\r
- CONTAINED_ELEMENT ContainedElements;\r
- UINT8 ExtendLength;\r
+SMBIOS_MISC_TABLE_FUNCTION (MiscChassisManufacturer) {\r
+ CHAR8 *OptionalStrStart;\r
+ CHAR8 *StrStart;\r
+ UINT8 *SkuNumberField;\r
+ UINTN RecordLength;\r
+ UINTN ManuStrLen;\r
+ UINTN VerStrLen;\r
+ UINTN AssertTagStrLen;\r
+ UINTN SerialNumStrLen;\r
+ UINTN ChaNumStrLen;\r
+ EFI_STRING Manufacturer;\r
+ EFI_STRING Version;\r
+ EFI_STRING SerialNumber;\r
+ EFI_STRING AssertTag;\r
+ EFI_STRING ChassisSkuNumber;\r
+ EFI_STRING_ID TokenToGet;\r
+ SMBIOS_TABLE_TYPE3 *SmbiosRecord;\r
+ SMBIOS_TABLE_TYPE3 *InputData;\r
+ EFI_STATUS Status;\r
+\r
+ UINT8 ContainedElementCount;\r
+ CONTAINED_ELEMENT ContainedElements;\r
+ UINT8 ExtendLength;\r
\r
ExtendLength = 0;\r
\r
SkuNumberType03\r
);\r
\r
- TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER);\r
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER);\r
Manufacturer = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
- ManuStrLen = StrLen (Manufacturer);\r
+ ManuStrLen = StrLen (Manufacturer);\r
\r
TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_VERSION);\r
- Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
- VerStrLen = StrLen (Version);\r
+ Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ VerStrLen = StrLen (Version);\r
\r
- TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER);\r
- SerialNumber = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER);\r
+ SerialNumber = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
SerialNumStrLen = StrLen (SerialNumber);\r
\r
- TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG);\r
- AssertTag = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG);\r
+ AssertTag = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
AssertTagStrLen = StrLen (AssertTag);\r
\r
- TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SKU_NUMBER);\r
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SKU_NUMBER);\r
ChassisSkuNumber = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);\r
- ChaNumStrLen = StrLen (ChassisSkuNumber);\r
+ ChaNumStrLen = StrLen (ChassisSkuNumber);\r
\r
ContainedElementCount = InputData->ContainedElementCount;\r
- ExtendLength = ContainedElementCount * sizeof (CONTAINED_ELEMENT);\r
+ ExtendLength = ContainedElementCount * sizeof (CONTAINED_ELEMENT);\r
\r
//\r
// Two zeros following the last string.\r
\r
SmbiosRecord->Type = OemGetChassisType ();\r
\r
- //ContainedElements\r
+ // ContainedElements\r
ASSERT (ContainedElementCount < 2);\r
(VOID)CopyMem (SmbiosRecord + 1, &ContainedElements, ExtendLength);\r
\r
- //ChassisSkuNumber\r
+ // ChassisSkuNumber\r
SkuNumberField = (UINT8 *)SmbiosRecord +\r
sizeof (SMBIOS_TABLE_TYPE3) -\r
sizeof (CONTAINED_ELEMENT) + ExtendLength;\r
*SkuNumberField = 5;\r
\r
OptionalStrStart = (CHAR8 *)((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) +\r
- ExtendLength + 1);\r
+ ExtendLength + 1);\r
UnicodeStrToAsciiStrS (Manufacturer, OptionalStrStart, ManuStrLen + 1);\r
StrStart = OptionalStrStart + ManuStrLen + 1;\r
UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1);\r
StrStart += AssertTagStrLen + 1;\r
UnicodeStrToAsciiStrS (ChassisSkuNumber, StrStart, ChaNumStrLen + 1);\r
\r
- SmbiosRecord->BootupState = OemGetChassisBootupState ();\r
- SmbiosRecord->PowerSupplyState = OemGetChassisPowerSupplyState ();\r
- SmbiosRecord->ThermalState = OemGetChassisThermalState ();\r
- SmbiosRecord->SecurityStatus = OemGetChassisSecurityStatus ();\r
- SmbiosRecord->Height = OemGetChassisHeight ();\r
+ SmbiosRecord->BootupState = OemGetChassisBootupState ();\r
+ SmbiosRecord->PowerSupplyState = OemGetChassisPowerSupplyState ();\r
+ SmbiosRecord->ThermalState = OemGetChassisThermalState ();\r
+ SmbiosRecord->SecurityStatus = OemGetChassisSecurityStatus ();\r
+ SmbiosRecord->Height = OemGetChassisHeight ();\r
SmbiosRecord->NumberofPowerCords = OemGetChassisNumPowerCords ();\r
\r
//\r
// Now we have got the full smbios record, call smbios protocol to add this record.\r
//\r
- Status = SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL);\r
+ Status = SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type03 Table Log Failed! %r \n",\r
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "[%a]:[%dL] Smbios Type03 Table Log Failed! %r \n",\r
+ __FUNCTION__,\r
+ DEBUG_LINE_NUMBER,\r
+ Status\r
+ ));\r
}\r
\r
FreePool (SmbiosRecord);\r
// Static (possibly build generated) Bios Vendor data.\r
//\r
\r
-SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE13, MiscNumberOfInstallableLanguages) =\r
+SMBIOS_MISC_TABLE_DATA (SMBIOS_TABLE_TYPE13, MiscNumberOfInstallableLanguages) =\r
{\r
{ // Hdr\r
- EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // Type,\r
- 0, // Length,\r
- 0 // Handle\r
+ EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // Type,\r
+ 0, // Length,\r
+ 0 // Handle\r
},\r
0, // InstallableLanguages\r
0, // Flags\r
VOID\r
EFIAPI\r
GetNextLanguage (\r
- IN OUT CHAR8 **LangCode,\r
- OUT CHAR8 *Lang\r
+ IN OUT CHAR8 **LangCode,\r
+ OUT CHAR8 *Lang\r
)\r
{\r
UINTN Index;\r
CHAR8 *StringPtr;\r
\r
- if (LangCode == NULL || *LangCode == NULL || Lang == NULL) {\r
+ if ((LangCode == NULL) || (*LangCode == NULL) || (Lang == NULL)) {\r
return;\r
}\r
\r
if (StringPtr[Index] == ';') {\r
Index++;\r
}\r
+\r
*LangCode = StringPtr + Index;\r
}\r
\r
UINT16\r
EFIAPI\r
GetSupportedLanguageNumber (\r
- IN EFI_HII_HANDLE HiiHandle\r
+ IN EFI_HII_HANDLE HiiHandle\r
)\r
{\r
CHAR8 *Lang;\r
}\r
\r
LangNumber = 0;\r
- Lang = AllocatePool (AsciiStrSize (Languages));\r
+ Lang = AllocatePool (AsciiStrSize (Languages));\r
if (Lang != NULL) {\r
LanguageString = Languages;\r
while (*LanguageString != 0) {\r
GetNextLanguage (&LanguageString, Lang);\r
LangNumber++;\r
}\r
+\r
FreePool (Lang);\r
}\r
+\r
FreePool (Languages);\r
return LangNumber;\r
}\r
\r
-\r
/**\r
This function makes boot time changes to the contents of the\r
MiscNumberOfInstallableLanguages (Type 13) record.\r
@retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.\r
\r
**/\r
-SMBIOS_MISC_TABLE_FUNCTION(MiscNumberOfInstallableLanguages)\r
-{\r
- UINTN LangStrLen;\r
- CHAR8 CurrentLang[SMBIOS_STRING_MAX_LENGTH + 1];\r
- CHAR8 *OptionalStrStart;\r
- EFI_STATUS Status;\r
- SMBIOS_TABLE_TYPE13 *SmbiosRecord;\r
- SMBIOS_TABLE_TYPE13 *InputData;\r
+SMBIOS_MISC_TABLE_FUNCTION (MiscNumberOfInstallableLanguages) {\r
+ UINTN LangStrLen;\r
+ CHAR8 CurrentLang[SMBIOS_STRING_MAX_LENGTH + 1];\r
+ CHAR8 *OptionalStrStart;\r
+ EFI_STATUS Status;\r
+ SMBIOS_TABLE_TYPE13 *SmbiosRecord;\r
+ SMBIOS_TABLE_TYPE13 *InputData;\r
\r
InputData = NULL;\r
\r
//\r
// Now we have got the full smbios record, call smbios protocol to add this record.\r
//\r
- Status = SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL);\r
+ Status = SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type13 Table Log Failed! %r \n",\r
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "[%a]:[%dL] Smbios Type13 Table Log Failed! %r \n",\r
+ __FUNCTION__,\r
+ DEBUG_LINE_NUMBER,\r
+ Status\r
+ ));\r
}\r
\r
FreePool (SmbiosRecord);\r
//\r
// Static (possibly build generated) Bios Vendor data.\r
//\r
-SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE32, MiscBootInformation) = {\r
+SMBIOS_MISC_TABLE_DATA (SMBIOS_TABLE_TYPE32, MiscBootInformation) = {\r
{ // Hdr\r
- EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type,\r
- 0, // Length,\r
- 0 // Handle\r
+ EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type,\r
+ 0, // Length,\r
+ 0 // Handle\r
},\r
{ // Reserved[6]\r
0,\r
@retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.\r
\r
**/\r
-SMBIOS_MISC_TABLE_FUNCTION(MiscBootInformation)\r
-{\r
- EFI_STATUS Status;\r
- SMBIOS_TABLE_TYPE32 *SmbiosRecord;\r
- SMBIOS_TABLE_TYPE32 *InputData;\r
+SMBIOS_MISC_TABLE_FUNCTION (MiscBootInformation) {\r
+ EFI_STATUS Status;\r
+ SMBIOS_TABLE_TYPE32 *SmbiosRecord;\r
+ SMBIOS_TABLE_TYPE32 *InputData;\r
\r
//\r
// First check for invalid parameters.\r
//\r
// Now we have got the full smbios record, call smbios protocol to add this record.\r
//\r
- Status = SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL);\r
+ Status = SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type32 Table Log Failed! %r \n",\r
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "[%a]:[%dL] Smbios Type32 Table Log Failed! %r \n",\r
+ __FUNCTION__,\r
+ DEBUG_LINE_NUMBER,\r
+ Status\r
+ ));\r
}\r
\r
FreePool (SmbiosRecord);\r
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