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target-i386: Remove vendor_override field from CPUX86State
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf
EH		 26#include "sysemu/cpus.h"
27#include "topology.h"
c6dc6f63 28
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
7b1b5d19 33#include "qapi/visitor.h"
9c17d615 34#include "sysemu/arch_init.h"
71ad61d3 35
28f52cc0
VR		 36#include "hyperv.h"
37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
bdeec802
IM		 44#ifndef CONFIG_USER_ONLY
45#include "hw/xen.h"
46#include "hw/sysbus.h"
449994eb 47#include "hw/apic_internal.h"
bdeec802
IM		 48#endif
49
99b88a17
IM		 50static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
51 uint32_t vendor2, uint32_t vendor3)
52{
53 int i;
54 for (i = 0; i < 4; i++) {
55 dst[i] = vendor1 >> (8 * i);
56 dst[i + 4] = vendor2 >> (8 * i);
57 dst[i + 8] = vendor3 >> (8 * i);
58 }
59 dst[CPUID_VENDOR_SZ] = '\0';
60}
61
c6dc6f63
AP		 62/* feature flags taken from "Intel Processor Identification and the CPUID
63 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
64 * between feature naming conventions, aliases may be added.
65 */
66static const char *feature_name[] = {
67 "fpu", "vme", "de", "pse",
68 "tsc", "msr", "pae", "mce",
69 "cx8", "apic", NULL, "sep",
70 "mtrr", "pge", "mca", "cmov",
71 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
72 NULL, "ds" /* Intel dts */, "acpi", "mmx",
73 "fxsr", "sse", "sse2", "ss",
74 "ht" /* Intel htt */, "tm", "ia64", "pbe",
75};
76static const char *ext_feature_name[] = {
f370be3c 77 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 78 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 79 "tm2", "ssse3", "cid", NULL,
e117f772 80 "fma", "cx16", "xtpr", "pdcm",
434acb81 81 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 82 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 83 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 84 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 85};
3b671a40
EH		 86/* Feature names that are already defined on feature_name[] but are set on
87 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
88 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
89 * if and only if CPU vendor is AMD.
90 */
c6dc6f63 91static const char *ext2_feature_name[] = {
3b671a40
EH		 92 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
93 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
94 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
95 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
96 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
97 "nx|xd", NULL, "mmxext", NULL /* mmx */,
98 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 99 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 100};
101static const char *ext3_feature_name[] = {
102 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
103 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 104 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 105 "skinit", "wdt", NULL, "lwp",
106 "fma4", "tce", NULL, "nodeid_msr",
107 NULL, "tbm", "topoext", "perfctr_core",
108 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 109 NULL, NULL, NULL, NULL,
110};
111
89e49c8b
EH		 112static const char *ext4_feature_name[] = {
113 NULL, NULL, "xstore", "xstore-en",
114 NULL, NULL, "xcrypt", "xcrypt-en",
115 "ace2", "ace2-en", "phe", "phe-en",
116 "pmm", "pmm-en", NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 NULL, NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL,
120 NULL, NULL, NULL, NULL,
121};
122
c6dc6f63 123static const char *kvm_feature_name[] = {
c3d39807
DS		 124 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
125 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
126 NULL, NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 132};
133
296acb64
JR		 134static const char *svm_feature_name[] = {
135 "npt", "lbrv", "svm_lock", "nrip_save",
136 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
137 NULL, NULL, "pause_filter", NULL,
138 "pfthreshold", NULL, NULL, NULL,
139 NULL, NULL, NULL, NULL,
140 NULL, NULL, NULL, NULL,
141 NULL, NULL, NULL, NULL,
142 NULL, NULL, NULL, NULL,
143};
144
a9321a4d 145static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 146 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
147 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 148 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 149 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
150};
151
5ef57876
EH		 152typedef struct FeatureWordInfo {
153 const char **feat_names;
bffd67b0
EH		 154 uint32_t cpuid_eax; /* Input EAX for CPUID */
155 int cpuid_reg; /* R_* register constant */
5ef57876
EH		 156} FeatureWordInfo;
157
158static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 159 [FEAT_1_EDX] = {
160 .feat_names = feature_name,
161 .cpuid_eax = 1, .cpuid_reg = R_EDX,
162 },
163 [FEAT_1_ECX] = {
164 .feat_names = ext_feature_name,
165 .cpuid_eax = 1, .cpuid_reg = R_ECX,
166 },
167 [FEAT_8000_0001_EDX] = {
168 .feat_names = ext2_feature_name,
169 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
170 },
171 [FEAT_8000_0001_ECX] = {
172 .feat_names = ext3_feature_name,
173 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
174 },
89e49c8b
EH		 175 [FEAT_C000_0001_EDX] = {
176 .feat_names = ext4_feature_name,
177 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
178 },
bffd67b0
EH		 179 [FEAT_KVM] = {
180 .feat_names = kvm_feature_name,
181 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
182 },
183 [FEAT_SVM] = {
184 .feat_names = svm_feature_name,
185 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
186 },
187 [FEAT_7_0_EBX] = {
188 .feat_names = cpuid_7_0_ebx_feature_name,
189 .cpuid_eax = 7, .cpuid_reg = R_EBX,
190 },
5ef57876
EH		 191};
192
8b4beddc
EH		 193const char *get_register_name_32(unsigned int reg)
194{
195 static const char *reg_names[CPU_NB_REGS32] = {
196 [R_EAX] = "EAX",
197 [R_ECX] = "ECX",
198 [R_EDX] = "EDX",
199 [R_EBX] = "EBX",
200 [R_ESP] = "ESP",
201 [R_EBP] = "EBP",
202 [R_ESI] = "ESI",
203 [R_EDI] = "EDI",
204 };
205
206 if (reg > CPU_NB_REGS32) {
207 return NULL;
208 }
209 return reg_names[reg];
210}
211
c6dc6f63
AP		 212/* collects per-function cpuid data
213 */
214typedef struct model_features_t {
215 uint32_t *guest_feat;
216 uint32_t *host_feat;
bffd67b0 217 FeatureWord feat_word;
8b4beddc 218} model_features_t;
c6dc6f63
AP		 219
220int check_cpuid = 0;
221int enforce_cpuid = 0;
222
dc59944b
MT		 223static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
224 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 225 (1 << KVM_FEATURE_CLOCKSOURCE2) |
226 (1 << KVM_FEATURE_ASYNC_PF) |
227 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 228 (1 << KVM_FEATURE_PV_EOI) |
dc59944b 229 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
dc59944b 230
29694758 231void disable_kvm_pv_eoi(void)
dc59944b 232{
29694758 233 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
dc59944b
MT		 234}
235
bb44e0d1
JK		 236void host_cpuid(uint32_t function, uint32_t count,
237 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 238{
239#if defined(CONFIG_KVM)
a1fd24af
AL		 240 uint32_t vec[4];
241
242#ifdef __x86_64__
243 asm volatile("cpuid"
244 : "=a"(vec[0]), "=b"(vec[1]),
245 "=c"(vec[2]), "=d"(vec[3])
246 : "0"(function), "c"(count) : "cc");
247#else
248 asm volatile("pusha \n\t"
249 "cpuid \n\t"
250 "mov %%eax, 0(%2) \n\t"
251 "mov %%ebx, 4(%2) \n\t"
252 "mov %%ecx, 8(%2) \n\t"
253 "mov %%edx, 12(%2) \n\t"
254 "popa"
255 : : "a"(function), "c"(count), "S"(vec)
256 : "memory", "cc");
257#endif
258
bdde476a 259 if (eax)
a1fd24af 260 *eax = vec[0];
bdde476a 261 if (ebx)
a1fd24af 262 *ebx = vec[1];
bdde476a 263 if (ecx)
a1fd24af 264 *ecx = vec[2];
bdde476a 265 if (edx)
a1fd24af 266 *edx = vec[3];
bdde476a
AP		 267#endif
268}
c6dc6f63
AP		 269
270#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
271
272/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
273 * a substring. ex if !NULL points to the first char after a substring,
274 * otherwise the string is assumed to sized by a terminating nul.
275 * Return lexical ordering of *s1:*s2.
276 */
277static int sstrcmp(const char *s1, const char *e1, const char *s2,
278 const char *e2)
279{
280 for (;;) {
281 if (!*s1 || !*s2 || *s1 != *s2)
282 return (*s1 - *s2);
283 ++s1, ++s2;
284 if (s1 == e1 && s2 == e2)
285 return (0);
286 else if (s1 == e1)
287 return (*s2);
288 else if (s2 == e2)
289 return (*s1);
290 }
291}
292
293/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
294 * '|' delimited (possibly empty) strings in which case search for a match
295 * within the alternatives proceeds left to right. Return 0 for success,
296 * non-zero otherwise.
297 */
298static int altcmp(const char *s, const char *e, const char *altstr)
299{
300 const char *p, *q;
301
302 for (q = p = altstr; ; ) {
303 while (*p && *p != '|')
304 ++p;
305 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
306 return (0);
307 if (!*p)
308 return (1);
309 else
310 q = ++p;
311 }
312}
313
314/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 315 * *pval and return true, otherwise return false
c6dc6f63 316 */
e41e0fc6
JK		 317static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
318 const char **featureset)
c6dc6f63
AP		 319{
320 uint32_t mask;
321 const char **ppc;
e41e0fc6 322 bool found = false;
c6dc6f63 323
e41e0fc6 324 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 325 if (*ppc && !altcmp(s, e, *ppc)) {
326 *pval |= mask;
e41e0fc6 327 found = true;
c6dc6f63 328 }
e41e0fc6
JK		 329 }
330 return found;
c6dc6f63
AP		 331}
332
5ef57876
EH		 333static void add_flagname_to_bitmaps(const char *flagname,
334 FeatureWordArray words)
c6dc6f63 335{
5ef57876
EH		 336 FeatureWord w;
337 for (w = 0; w < FEATURE_WORDS; w++) {
338 FeatureWordInfo *wi = &feature_word_info[w];
339 if (wi->feat_names &&
340 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
341 break;
342 }
343 }
344 if (w == FEATURE_WORDS) {
345 fprintf(stderr, "CPU feature %s not found\n", flagname);
346 }
c6dc6f63
AP		 347}
348
349typedef struct x86_def_t {
c6dc6f63
AP		 350 const char *name;
351 uint32_t level;
99b88a17
IM		 352 /* vendor is zero-terminated, 12 character ASCII string */
353 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 354 int family;
355 int model;
356 int stepping;
b862d1fe 357 int tsc_khz;
296acb64
JR		 358 uint32_t features, ext_features, ext2_features, ext3_features;
359 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 360 uint32_t xlevel;
361 char model_id[48];
b3baa152
BW		 362 /* Store the results of Centaur's CPUID instructions */
363 uint32_t ext4_features;
364 uint32_t xlevel2;
13526728
EH		 365 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
366 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 367} x86_def_t;
368
369#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
370#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
371 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
372#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
373 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
374 CPUID_PSE36 | CPUID_FXSR)
375#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
376#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
377 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
378 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
379 CPUID_PAE | CPUID_SEP | CPUID_APIC)
380
551a2dec
AP		 381#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
382 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
383 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
384 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
385 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 386 /* partly implemented:
387 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
388 CPUID_PSE36 (needed for Solaris) */
389 /* missing:
390 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 391#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
a0a70681 392 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 393 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 394 /* missing:
395 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 396 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
60032ac0 397#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 398 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
399 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 400 /* missing:
401 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 402#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
403 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 404#define TCG_SVM_FEATURES 0
a9321a4d 405#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
551a2dec 406
7fc9b714 407/* built-in CPU model definitions
c6dc6f63
AP		 408 */
409static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 410 {
411 .name = "qemu64",
412 .level = 4,
99b88a17 413 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 414 .family = 6,
415 .model = 2,
416 .stepping = 3,
417 .features = PPRO_FEATURES |
c6dc6f63 418 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 419 CPUID_PSE36,
420 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
60032ac0 421 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 422 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
423 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
424 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
425 .xlevel = 0x8000000A,
c6dc6f63
AP		 426 },
427 {
428 .name = "phenom",
429 .level = 5,
99b88a17 430 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 431 .family = 16,
432 .model = 2,
433 .stepping = 3,
c6dc6f63
AP		 434 .features = PPRO_FEATURES |
435 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 436 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 437 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
438 CPUID_EXT_POPCNT,
60032ac0 439 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 440 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
441 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 442 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 443 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
444 CPUID_EXT3_CR8LEG,
445 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
446 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
447 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
448 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 449 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 450 .xlevel = 0x8000001A,
451 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
452 },
453 {
454 .name = "core2duo",
455 .level = 10,
99b88a17 456 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 457 .family = 6,
458 .model = 15,
459 .stepping = 11,
c6dc6f63
AP		 460 .features = PPRO_FEATURES |
461 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 462 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
463 CPUID_HT | CPUID_TM | CPUID_PBE,
464 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
465 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
466 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 467 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
468 .ext3_features = CPUID_EXT3_LAHF_LM,
469 .xlevel = 0x80000008,
470 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
471 },
472 {
473 .name = "kvm64",
474 .level = 5,
99b88a17 475 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 476 .family = 15,
477 .model = 6,
478 .stepping = 1,
479 /* Missing: CPUID_VME, CPUID_HT */
480 .features = PPRO_FEATURES |
481 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
482 CPUID_PSE36,
483 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
484 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
485 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
60032ac0 486 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 487 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
488 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
489 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
490 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
491 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
492 .ext3_features = 0,
493 .xlevel = 0x80000008,
494 .model_id = "Common KVM processor"
495 },
c6dc6f63
AP		 496 {
497 .name = "qemu32",
498 .level = 4,
99b88a17 499 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 500 .family = 6,
501 .model = 3,
502 .stepping = 3,
503 .features = PPRO_FEATURES,
504 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 505 .xlevel = 0x80000004,
c6dc6f63 506 },
eafaf1e5
AP		 507 {
508 .name = "kvm32",
509 .level = 5,
99b88a17 510 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 511 .family = 15,
512 .model = 6,
513 .stepping = 1,
514 .features = PPRO_FEATURES |
515 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
516 .ext_features = CPUID_EXT_SSE3,
60032ac0 517 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
eafaf1e5
AP		 518 .ext3_features = 0,
519 .xlevel = 0x80000008,
520 .model_id = "Common 32-bit KVM processor"
521 },
c6dc6f63
AP		 522 {
523 .name = "coreduo",
524 .level = 10,
99b88a17 525 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 526 .family = 6,
527 .model = 14,
528 .stepping = 8,
c6dc6f63 529 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 530 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
531 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
532 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
533 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 534 .ext2_features = CPUID_EXT2_NX,
535 .xlevel = 0x80000008,
536 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
537 },
538 {
539 .name = "486",
58012d66 540 .level = 1,
99b88a17 541 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 542 .family = 4,
543 .model = 0,
544 .stepping = 0,
545 .features = I486_FEATURES,
546 .xlevel = 0,
547 },
548 {
549 .name = "pentium",
550 .level = 1,
99b88a17 551 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 552 .family = 5,
553 .model = 4,
554 .stepping = 3,
555 .features = PENTIUM_FEATURES,
556 .xlevel = 0,
557 },
558 {
559 .name = "pentium2",
560 .level = 2,
99b88a17 561 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 562 .family = 6,
563 .model = 5,
564 .stepping = 2,
565 .features = PENTIUM2_FEATURES,
566 .xlevel = 0,
567 },
568 {
569 .name = "pentium3",
570 .level = 2,
99b88a17 571 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 572 .family = 6,
573 .model = 7,
574 .stepping = 3,
575 .features = PENTIUM3_FEATURES,
576 .xlevel = 0,
577 },
578 {
579 .name = "athlon",
580 .level = 2,
99b88a17 581 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 582 .family = 6,
583 .model = 2,
584 .stepping = 3,
60032ac0
EH		 585 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
586 CPUID_MCA,
587 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
588 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 589 .xlevel = 0x80000008,
c6dc6f63
AP		 590 },
591 {
592 .name = "n270",
593 /* original is on level 10 */
594 .level = 5,
99b88a17 595 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 596 .family = 6,
597 .model = 28,
598 .stepping = 2,
599 .features = PPRO_FEATURES |
8560efed
AJ		 600 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
601 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 602 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 603 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
604 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
60032ac0
EH		 605 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
606 CPUID_EXT2_NX,
8560efed 607 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 608 .xlevel = 0x8000000A,
609 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
610 },
3eca4642
EH		 611 {
612 .name = "Conroe",
613 .level = 2,
99b88a17 614 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 615 .family = 6,
616 .model = 2,
617 .stepping = 3,
618 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
619 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
620 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
621 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
622 CPUID_DE | CPUID_FP87,
623 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
624 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
625 .ext3_features = CPUID_EXT3_LAHF_LM,
626 .xlevel = 0x8000000A,
627 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
628 },
629 {
630 .name = "Penryn",
631 .level = 2,
99b88a17 632 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 633 .family = 6,
634 .model = 2,
635 .stepping = 3,
636 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
637 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
638 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
639 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
640 CPUID_DE | CPUID_FP87,
641 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
642 CPUID_EXT_SSE3,
643 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
644 .ext3_features = CPUID_EXT3_LAHF_LM,
645 .xlevel = 0x8000000A,
646 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
647 },
648 {
649 .name = "Nehalem",
650 .level = 2,
99b88a17 651 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 652 .family = 6,
653 .model = 2,
654 .stepping = 3,
655 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
656 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
657 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
658 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
659 CPUID_DE | CPUID_FP87,
660 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
661 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
662 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
663 .ext3_features = CPUID_EXT3_LAHF_LM,
664 .xlevel = 0x8000000A,
665 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
666 },
667 {
668 .name = "Westmere",
669 .level = 11,
99b88a17 670 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 671 .family = 6,
672 .model = 44,
673 .stepping = 1,
674 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
675 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
676 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
677 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
678 CPUID_DE | CPUID_FP87,
679 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
680 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
681 CPUID_EXT_SSE3,
682 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
683 .ext3_features = CPUID_EXT3_LAHF_LM,
684 .xlevel = 0x8000000A,
685 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
686 },
687 {
688 .name = "SandyBridge",
689 .level = 0xd,
99b88a17 690 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 691 .family = 6,
692 .model = 42,
693 .stepping = 1,
694 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
695 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
696 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
697 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
698 CPUID_DE | CPUID_FP87,
699 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
700 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
701 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
702 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
703 CPUID_EXT_SSE3,
704 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
705 CPUID_EXT2_SYSCALL,
706 .ext3_features = CPUID_EXT3_LAHF_LM,
707 .xlevel = 0x8000000A,
708 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
709 },
37507094
EH		 710 {
711 .name = "Haswell",
712 .level = 0xd,
99b88a17 713 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 714 .family = 6,
715 .model = 60,
716 .stepping = 1,
717 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
718 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 719 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 720 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
721 CPUID_DE | CPUID_FP87,
722 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
723 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
724 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
725 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
726 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
727 CPUID_EXT_PCID,
80ae4160
EH		 728 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
729 CPUID_EXT2_SYSCALL,
37507094
EH		 730 .ext3_features = CPUID_EXT3_LAHF_LM,
731 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
732 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
733 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
734 CPUID_7_0_EBX_RTM,
735 .xlevel = 0x8000000A,
736 .model_id = "Intel Core Processor (Haswell)",
737 },
3eca4642
EH		 738 {
739 .name = "Opteron_G1",
740 .level = 5,
99b88a17 741 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 742 .family = 15,
743 .model = 6,
744 .stepping = 1,
745 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
746 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
747 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
748 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
749 CPUID_DE | CPUID_FP87,
750 .ext_features = CPUID_EXT_SSE3,
751 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
752 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
753 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
754 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
755 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
756 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
757 .xlevel = 0x80000008,
758 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
759 },
760 {
761 .name = "Opteron_G2",
762 .level = 5,
99b88a17 763 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 764 .family = 15,
765 .model = 6,
766 .stepping = 1,
767 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
768 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
769 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
770 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
771 CPUID_DE | CPUID_FP87,
772 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
773 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
774 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
775 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
776 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
777 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
778 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
779 CPUID_EXT2_DE | CPUID_EXT2_FPU,
780 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
781 .xlevel = 0x80000008,
782 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
783 },
784 {
785 .name = "Opteron_G3",
786 .level = 5,
99b88a17 787 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 788 .family = 15,
789 .model = 6,
790 .stepping = 1,
791 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
792 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
793 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
794 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
795 CPUID_DE | CPUID_FP87,
796 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
797 CPUID_EXT_SSE3,
798 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
799 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
800 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
801 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
802 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
803 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
804 CPUID_EXT2_DE | CPUID_EXT2_FPU,
805 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
806 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
807 .xlevel = 0x80000008,
808 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
809 },
810 {
811 .name = "Opteron_G4",
812 .level = 0xd,
99b88a17 813 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 814 .family = 21,
815 .model = 1,
816 .stepping = 2,
817 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
818 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
819 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
820 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
821 CPUID_DE | CPUID_FP87,
822 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
823 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
824 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
825 CPUID_EXT_SSE3,
826 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
827 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
828 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
829 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
830 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
831 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
832 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
833 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
834 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
835 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
836 CPUID_EXT3_LAHF_LM,
837 .xlevel = 0x8000001A,
838 .model_id = "AMD Opteron 62xx class CPU",
839 },
021941b9
AP		 840 {
841 .name = "Opteron_G5",
842 .level = 0xd,
99b88a17 843 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 844 .family = 21,
845 .model = 2,
846 .stepping = 0,
847 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
848 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
849 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
850 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
851 CPUID_DE | CPUID_FP87,
852 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
853 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
854 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
855 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
856 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
857 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
858 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
859 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
860 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
861 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
862 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
863 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
864 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
865 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
866 CPUID_EXT3_LAHF_LM,
867 .xlevel = 0x8000001A,
868 .model_id = "AMD Opteron 63xx class CPU",
869 },
c6dc6f63
AP		 870};
871
e4ab0d6b 872#ifdef CONFIG_KVM
c6dc6f63
AP		 873static int cpu_x86_fill_model_id(char *str)
874{
875 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
876 int i;
877
878 for (i = 0; i < 3; i++) {
879 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
880 memcpy(str + i * 16 + 0, &eax, 4);
881 memcpy(str + i * 16 + 4, &ebx, 4);
882 memcpy(str + i * 16 + 8, &ecx, 4);
883 memcpy(str + i * 16 + 12, &edx, 4);
884 }
885 return 0;
886}
e4ab0d6b 887#endif
c6dc6f63 888
6e746f30
EH		 889/* Fill a x86_def_t struct with information about the host CPU, and
890 * the CPU features supported by the host hardware + host kernel
891 *
892 * This function may be called only if KVM is enabled.
893 */
894static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 895{
e4ab0d6b 896#ifdef CONFIG_KVM
12869995 897 KVMState *s = kvm_state;
c6dc6f63
AP		 898 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
899
6e746f30
EH		 900 assert(kvm_enabled());
901
c6dc6f63
AP		 902 x86_cpu_def->name = "host";
903 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
99b88a17 904 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
c6dc6f63
AP		 905
906 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
907 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
908 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
909 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 910
12869995
EH		 911 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
912 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
913 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 914
6e746f30 915 if (x86_cpu_def->level >= 7) {
12869995
EH		 916 x86_cpu_def->cpuid_7_0_ebx_features =
917 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728
EH		 918 } else {
919 x86_cpu_def->cpuid_7_0_ebx_features = 0;
920 }
921
12869995
EH		 922 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
923 x86_cpu_def->ext2_features =
924 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
925 x86_cpu_def->ext3_features =
926 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 927
c6dc6f63 928 cpu_x86_fill_model_id(x86_cpu_def->model_id);
c6dc6f63 929
b3baa152 930 /* Call Centaur's CPUID instruction. */
99b88a17 931 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
b3baa152 932 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
12869995 933 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
b3baa152
BW		 934 if (eax >= 0xC0000001) {
935 /* Support VIA max extended level */
936 x86_cpu_def->xlevel2 = eax;
937 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
12869995
EH		 938 x86_cpu_def->ext4_features =
939 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
b3baa152
BW		 940 }
941 }
296acb64 942
fcb93c03
EH		 943 /* Other KVM-specific feature fields: */
944 x86_cpu_def->svm_features =
945 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
bd004bef
EH		 946 x86_cpu_def->kvm_features =
947 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 948
e4ab0d6b 949#endif /* CONFIG_KVM */
c6dc6f63
AP		 950}
951
bffd67b0 952static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 953{
954 int i;
955
956 for (i = 0; i < 32; ++i)
957 if (1 << i & mask) {
bffd67b0 958 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 959 assert(reg);
960 fprintf(stderr, "warning: host doesn't support requested feature: "
961 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 962 f->cpuid_eax, reg,
963 f->feat_names[i] ? "." : "",
964 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 965 break;
966 }
967 return 0;
968}
969
07ca5945
EH		 970/* Check if all requested cpu flags are making their way to the guest
971 *
972 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 973 *
974 * This function may be called only if KVM is enabled.
c6dc6f63 975 */
5ec01c2e 976static int kvm_check_features_against_host(X86CPU *cpu)
c6dc6f63 977{
5ec01c2e 978 CPUX86State *env = &cpu->env;
c6dc6f63
AP		 979 x86_def_t host_def;
980 uint32_t mask;
981 int rv, i;
982 struct model_features_t ft[] = {
5ec01c2e 983 {&env->cpuid_features, &host_def.features,
bffd67b0 984 FEAT_1_EDX },
5ec01c2e 985 {&env->cpuid_ext_features, &host_def.ext_features,
bffd67b0 986 FEAT_1_ECX },
5ec01c2e 987 {&env->cpuid_ext2_features, &host_def.ext2_features,
bffd67b0 988 FEAT_8000_0001_EDX },
5ec01c2e 989 {&env->cpuid_ext3_features, &host_def.ext3_features,
bffd67b0 990 FEAT_8000_0001_ECX },
5ec01c2e 991 {&env->cpuid_ext4_features, &host_def.ext4_features,
07ca5945 992 FEAT_C000_0001_EDX },
5ec01c2e 993 {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
07ca5945 994 FEAT_7_0_EBX },
5ec01c2e 995 {&env->cpuid_svm_features, &host_def.svm_features,
07ca5945 996 FEAT_SVM },
5ec01c2e 997 {&env->cpuid_kvm_features, &host_def.kvm_features,
07ca5945 998 FEAT_KVM },
8b4beddc 999 };
c6dc6f63 1000
6e746f30
EH		 1001 assert(kvm_enabled());
1002
1003 kvm_cpu_fill_host(&host_def);
bffd67b0
EH		 1004 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1005 FeatureWord w = ft[i].feat_word;
1006 FeatureWordInfo *wi = &feature_word_info[w];
1007 for (mask = 1; mask; mask <<= 1) {
e8beac00 1008 if (*ft[i].guest_feat & mask &&
c6dc6f63 1009 !(*ft[i].host_feat & mask)) {
bffd67b0
EH		 1010 unavailable_host_feature(wi, mask);
1011 rv = 1;
1012 }
1013 }
1014 }
c6dc6f63
AP		 1015 return rv;
1016}
1017
95b8519d
AF		 1018static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1019 const char *name, Error **errp)
1020{
1021 X86CPU *cpu = X86_CPU(obj);
1022 CPUX86State *env = &cpu->env;
1023 int64_t value;
1024
1025 value = (env->cpuid_version >> 8) & 0xf;
1026 if (value == 0xf) {
1027 value += (env->cpuid_version >> 20) & 0xff;
1028 }
1029 visit_type_int(v, &value, name, errp);
1030}
1031
71ad61d3
AF		 1032static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1033 const char *name, Error **errp)
ed5e1ec3 1034{
71ad61d3
AF		 1035 X86CPU *cpu = X86_CPU(obj);
1036 CPUX86State *env = &cpu->env;
1037 const int64_t min = 0;
1038 const int64_t max = 0xff + 0xf;
1039 int64_t value;
1040
1041 visit_type_int(v, &value, name, errp);
1042 if (error_is_set(errp)) {
1043 return;
1044 }
1045 if (value < min || value > max) {
1046 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1047 name ? name : "null", value, min, max);
1048 return;
1049 }
1050
ed5e1ec3 1051 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1052 if (value > 0x0f) {
1053 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1054 } else {
71ad61d3 1055 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1056 }
1057}
1058
67e30c83
AF		 1059static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1060 const char *name, Error **errp)
1061{
1062 X86CPU *cpu = X86_CPU(obj);
1063 CPUX86State *env = &cpu->env;
1064 int64_t value;
1065
1066 value = (env->cpuid_version >> 4) & 0xf;
1067 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1068 visit_type_int(v, &value, name, errp);
1069}
1070
c5291a4f
AF		 1071static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1072 const char *name, Error **errp)
b0704cbd 1073{
c5291a4f
AF		 1074 X86CPU *cpu = X86_CPU(obj);
1075 CPUX86State *env = &cpu->env;
1076 const int64_t min = 0;
1077 const int64_t max = 0xff;
1078 int64_t value;
1079
1080 visit_type_int(v, &value, name, errp);
1081 if (error_is_set(errp)) {
1082 return;
1083 }
1084 if (value < min || value > max) {
1085 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1086 name ? name : "null", value, min, max);
1087 return;
1088 }
1089
b0704cbd 1090 env->cpuid_version &= ~0xf00f0;
c5291a4f 1091 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1092}
1093
35112e41
AF		 1094static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1095 void *opaque, const char *name,
1096 Error **errp)
1097{
1098 X86CPU *cpu = X86_CPU(obj);
1099 CPUX86State *env = &cpu->env;
1100 int64_t value;
1101
1102 value = env->cpuid_version & 0xf;
1103 visit_type_int(v, &value, name, errp);
1104}
1105
036e2222
AF		 1106static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1107 void *opaque, const char *name,
1108 Error **errp)
38c3dc46 1109{
036e2222
AF		 1110 X86CPU *cpu = X86_CPU(obj);
1111 CPUX86State *env = &cpu->env;
1112 const int64_t min = 0;
1113 const int64_t max = 0xf;
1114 int64_t value;
1115
1116 visit_type_int(v, &value, name, errp);
1117 if (error_is_set(errp)) {
1118 return;
1119 }
1120 if (value < min || value > max) {
1121 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1122 name ? name : "null", value, min, max);
1123 return;
1124 }
1125
38c3dc46 1126 env->cpuid_version &= ~0xf;
036e2222 1127 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1128}
1129
8e1898bf
AF		 1130static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1131 const char *name, Error **errp)
1132{
1133 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1134
fa029887 1135 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1136}
1137
1138static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1139 const char *name, Error **errp)
1140{
1141 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1142
fa029887 1143 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1144}
1145
16b93aa8
AF		 1146static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1147 const char *name, Error **errp)
1148{
1149 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1150
fa029887 1151 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1152}
1153
1154static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1155 const char *name, Error **errp)
1156{
1157 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1158
fa029887 1159 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1160}
1161
d480e1af
AF		 1162static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1163{
1164 X86CPU *cpu = X86_CPU(obj);
1165 CPUX86State *env = &cpu->env;
1166 char *value;
d480e1af 1167
9df694ee 1168 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1169 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1170 env->cpuid_vendor3);
d480e1af
AF		 1171 return value;
1172}
1173
1174static void x86_cpuid_set_vendor(Object *obj, const char *value,
1175 Error **errp)
1176{
1177 X86CPU *cpu = X86_CPU(obj);
1178 CPUX86State *env = &cpu->env;
1179 int i;
1180
9df694ee 1181 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1182 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1183 "vendor", value);
1184 return;
1185 }
1186
1187 env->cpuid_vendor1 = 0;
1188 env->cpuid_vendor2 = 0;
1189 env->cpuid_vendor3 = 0;
1190 for (i = 0; i < 4; i++) {
1191 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1192 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1193 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1194 }
d480e1af
AF		 1195}
1196
63e886eb
AF		 1197static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1198{
1199 X86CPU *cpu = X86_CPU(obj);
1200 CPUX86State *env = &cpu->env;
1201 char *value;
1202 int i;
1203
1204 value = g_malloc(48 + 1);
1205 for (i = 0; i < 48; i++) {
1206 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1207 }
1208 value[48] = '\0';
1209 return value;
1210}
1211
938d4c25
AF		 1212static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1213 Error **errp)
dcce6675 1214{
938d4c25
AF		 1215 X86CPU *cpu = X86_CPU(obj);
1216 CPUX86State *env = &cpu->env;
dcce6675
AF		 1217 int c, len, i;
1218
1219 if (model_id == NULL) {
1220 model_id = "";
1221 }
1222 len = strlen(model_id);
d0a6acf4 1223 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1224 for (i = 0; i < 48; i++) {
1225 if (i >= len) {
1226 c = '\0';
1227 } else {
1228 c = (uint8_t)model_id[i];
1229 }
1230 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1231 }
1232}
1233
89e48965
AF		 1234static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1235 const char *name, Error **errp)
1236{
1237 X86CPU *cpu = X86_CPU(obj);
1238 int64_t value;
1239
1240 value = cpu->env.tsc_khz * 1000;
1241 visit_type_int(v, &value, name, errp);
1242}
1243
1244static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1245 const char *name, Error **errp)
1246{
1247 X86CPU *cpu = X86_CPU(obj);
1248 const int64_t min = 0;
2e84849a 1249 const int64_t max = INT64_MAX;
89e48965
AF		 1250 int64_t value;
1251
1252 visit_type_int(v, &value, name, errp);
1253 if (error_is_set(errp)) {
1254 return;
1255 }
1256 if (value < min || value > max) {
1257 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1258 name ? name : "null", value, min, max);
1259 return;
1260 }
1261
1262 cpu->env.tsc_khz = value / 1000;
1263}
1264
8f961357 1265static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
c6dc6f63 1266{
c6dc6f63 1267 x86_def_t *def;
7fc9b714 1268 int i;
c6dc6f63 1269
4bfe910d
AF		 1270 if (name == NULL) {
1271 return -1;
9f3fb565 1272 }
4bfe910d 1273 if (kvm_enabled() && strcmp(name, "host") == 0) {
6e746f30 1274 kvm_cpu_fill_host(x86_cpu_def);
4bfe910d 1275 return 0;
c6dc6f63
AP		 1276 }
1277
7fc9b714
AF		 1278 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1279 def = &builtin_x86_defs[i];
4bfe910d
AF		 1280 if (strcmp(name, def->name) == 0) {
1281 memcpy(x86_cpu_def, def, sizeof(*def));
11acfdd5
IM		 1282 /* sysenter isn't supported in compatibility mode on AMD,
1283 * syscall isn't supported in compatibility mode on Intel.
1284 * Normally we advertise the actual CPU vendor, but you can
1285 * override this using the 'vendor' property if you want to use
1286 * KVM's sysenter/syscall emulation in compatibility mode and
1287 * when doing cross vendor migration
1288 */
1289 if (kvm_enabled()) {
1290 uint32_t ebx = 0, ecx = 0, edx = 0;
1291 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1292 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1293 }
4bfe910d
AF		 1294 return 0;
1295 }
1296 }
1297
1298 return -1;
8f961357
EH		 1299}
1300
1301/* Parse "+feature,-feature,feature=foo" CPU feature string
1302 */
1303static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1304{
8f961357
EH		 1305 char *featurestr; /* Single 'key=value" string being parsed */
1306 /* Features to be added */
077c68c3 1307 FeatureWordArray plus_features = { 0 };
8f961357 1308 /* Features to be removed */
5ef57876 1309 FeatureWordArray minus_features = { 0 };
8f961357
EH		 1310 uint32_t numvalue;
1311
8f961357 1312 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1313
1314 while (featurestr) {
1315 char *val;
1316 if (featurestr[0] == '+') {
5ef57876 1317 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1318 } else if (featurestr[0] == '-') {
5ef57876 1319 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1320 } else if ((val = strchr(featurestr, '='))) {
1321 *val = 0; val++;
1322 if (!strcmp(featurestr, "family")) {
1323 char *err;
1324 numvalue = strtoul(val, &err, 0);
a88a677f 1325 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 1326 fprintf(stderr, "bad numerical value %s\n", val);
1327 goto error;
1328 }
1329 x86_cpu_def->family = numvalue;
1330 } else if (!strcmp(featurestr, "model")) {
1331 char *err;
1332 numvalue = strtoul(val, &err, 0);
1333 if (!*val || *err || numvalue > 0xff) {
1334 fprintf(stderr, "bad numerical value %s\n", val);
1335 goto error;
1336 }
1337 x86_cpu_def->model = numvalue;
1338 } else if (!strcmp(featurestr, "stepping")) {
1339 char *err;
1340 numvalue = strtoul(val, &err, 0);
1341 if (!*val || *err || numvalue > 0xf) {
1342 fprintf(stderr, "bad numerical value %s\n", val);
1343 goto error;
1344 }
1345 x86_cpu_def->stepping = numvalue ;
1346 } else if (!strcmp(featurestr, "level")) {
1347 char *err;
1348 numvalue = strtoul(val, &err, 0);
1349 if (!*val || *err) {
1350 fprintf(stderr, "bad numerical value %s\n", val);
1351 goto error;
1352 }
1353 x86_cpu_def->level = numvalue;
1354 } else if (!strcmp(featurestr, "xlevel")) {
1355 char *err;
1356 numvalue = strtoul(val, &err, 0);
1357 if (!*val || *err) {
1358 fprintf(stderr, "bad numerical value %s\n", val);
1359 goto error;
1360 }
1361 if (numvalue < 0x80000000) {
8ba8a698
IM		 1362 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1363 ", fixup will be removed in future versions\n");
2f7a21c4 1364 numvalue += 0x80000000;
c6dc6f63
AP		 1365 }
1366 x86_cpu_def->xlevel = numvalue;
1367 } else if (!strcmp(featurestr, "vendor")) {
99b88a17 1368 pstrcpy(x86_cpu_def->vendor, sizeof(x86_cpu_def->vendor), val);
c6dc6f63
AP		 1369 } else if (!strcmp(featurestr, "model_id")) {
1370 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1371 val);
b862d1fe
JR		 1372 } else if (!strcmp(featurestr, "tsc_freq")) {
1373 int64_t tsc_freq;
1374 char *err;
1375
1376 tsc_freq = strtosz_suffix_unit(val, &err,
1377 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1378 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 1379 fprintf(stderr, "bad numerical value %s\n", val);
1380 goto error;
1381 }
1382 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 1383 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1384 char *err;
1385 numvalue = strtoul(val, &err, 0);
1386 if (!*val || *err) {
1387 fprintf(stderr, "bad numerical value %s\n", val);
1388 goto error;
1389 }
1390 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1391 } else {
1392 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1393 goto error;
1394 }
1395 } else if (!strcmp(featurestr, "check")) {
1396 check_cpuid = 1;
1397 } else if (!strcmp(featurestr, "enforce")) {
1398 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1399 } else if (!strcmp(featurestr, "hv_relaxed")) {
1400 hyperv_enable_relaxed_timing(true);
1401 } else if (!strcmp(featurestr, "hv_vapic")) {
1402 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1403 } else {
1404 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1405 goto error;
1406 }
1407 featurestr = strtok(NULL, ",");
1408 }
5ef57876
EH		 1409 x86_cpu_def->features |= plus_features[FEAT_1_EDX];
1410 x86_cpu_def->ext_features |= plus_features[FEAT_1_ECX];
1411 x86_cpu_def->ext2_features |= plus_features[FEAT_8000_0001_EDX];
1412 x86_cpu_def->ext3_features |= plus_features[FEAT_8000_0001_ECX];
89e49c8b 1413 x86_cpu_def->ext4_features |= plus_features[FEAT_C000_0001_EDX];
5ef57876
EH		 1414 x86_cpu_def->kvm_features |= plus_features[FEAT_KVM];
1415 x86_cpu_def->svm_features |= plus_features[FEAT_SVM];
1416 x86_cpu_def->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1417 x86_cpu_def->features &= ~minus_features[FEAT_1_EDX];
1418 x86_cpu_def->ext_features &= ~minus_features[FEAT_1_ECX];
1419 x86_cpu_def->ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1420 x86_cpu_def->ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
89e49c8b 1421 x86_cpu_def->ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
5ef57876
EH		 1422 x86_cpu_def->kvm_features &= ~minus_features[FEAT_KVM];
1423 x86_cpu_def->svm_features &= ~minus_features[FEAT_SVM];
1424 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63
AP		 1425 return 0;
1426
1427error:
c6dc6f63
AP		 1428 return -1;
1429}
1430
1431/* generate a composite string into buf of all cpuid names in featureset
1432 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1433 * if flags, suppress names undefined in featureset.
1434 */
1435static void listflags(char *buf, int bufsize, uint32_t fbits,
1436 const char **featureset, uint32_t flags)
1437{
1438 const char **p = &featureset[31];
1439 char *q, *b, bit;
1440 int nc;
1441
1442 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1443 *buf = '\0';
1444 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1445 if (fbits & 1 << bit && (*p || !flags)) {
1446 if (*p)
1447 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1448 else
1449 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1450 if (bufsize <= nc) {
1451 if (b) {
1452 memcpy(b, "...", sizeof("..."));
1453 }
1454 return;
1455 }
1456 q += nc;
1457 bufsize -= nc;
1458 }
1459}
1460
e916cbf8
PM		 1461/* generate CPU information. */
1462void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1463{
c6dc6f63
AP		 1464 x86_def_t *def;
1465 char buf[256];
7fc9b714 1466 int i;
c6dc6f63 1467
7fc9b714
AF		 1468 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1469 def = &builtin_x86_defs[i];
c04321b3 1470 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1471 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1472 }
ed2c54d4
AP		 1473 if (kvm_enabled()) {
1474 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1475 }
6cdf8854
PM		 1476 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1477 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
4a19e505 1478 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1479 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
4a19e505 1480 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1481 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
4a19e505 1482 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1483 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
4a19e505 1484 (*cpu_fprintf)(f, " %s\n", buf);
c6dc6f63
AP		 1485}
1486
76b64a7a 1487CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1488{
1489 CpuDefinitionInfoList *cpu_list = NULL;
1490 x86_def_t *def;
7fc9b714 1491 int i;
e3966126 1492
7fc9b714 1493 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1494 CpuDefinitionInfoList *entry;
1495 CpuDefinitionInfo *info;
1496
7fc9b714 1497 def = &builtin_x86_defs[i];
e3966126
AL		 1498 info = g_malloc0(sizeof(*info));
1499 info->name = g_strdup(def->name);
1500
1501 entry = g_malloc0(sizeof(*entry));
1502 entry->value = info;
1503 entry->next = cpu_list;
1504 cpu_list = entry;
1505 }
1506
1507 return cpu_list;
1508}
1509
bc74b7db
EH		 1510#ifdef CONFIG_KVM
1511static void filter_features_for_kvm(X86CPU *cpu)
1512{
1513 CPUX86State *env = &cpu->env;
1514 KVMState *s = kvm_state;
1515
b8091f24
EH		 1516 env->cpuid_features &=
1517 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1518 env->cpuid_ext_features &=
1519 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1520 env->cpuid_ext2_features &=
1521 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1522 env->cpuid_ext3_features &=
1523 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1524 env->cpuid_svm_features &=
1525 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
ffa8c11f
EH		 1526 env->cpuid_7_0_ebx_features &=
1527 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
bc74b7db 1528 env->cpuid_kvm_features &=
b8091f24
EH		 1529 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1530 env->cpuid_ext4_features &=
1531 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
bc74b7db
EH		 1532
1533}
1534#endif
1535
61dcd775 1536int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1537{
61dcd775 1538 CPUX86State *env = &cpu->env;
c6dc6f63 1539 x86_def_t def1, *def = &def1;
71ad61d3 1540 Error *error = NULL;
8f961357
EH		 1541 char *name, *features;
1542 gchar **model_pieces;
c6dc6f63 1543
db0ad1ba
JR		 1544 memset(def, 0, sizeof(*def));
1545
8f961357
EH		 1546 model_pieces = g_strsplit(cpu_model, ",", 2);
1547 if (!model_pieces[0]) {
fa2db3c4
IM		 1548 error_setg(&error, "Invalid/empty CPU model name");
1549 goto out;
8f961357
EH		 1550 }
1551 name = model_pieces[0];
1552 features = model_pieces[1];
1553
1554 if (cpu_x86_find_by_name(def, name) < 0) {
fa2db3c4
IM		 1555 error_setg(&error, "Unable to find CPU definition: %s", name);
1556 goto out;
8f961357
EH		 1557 }
1558
aa87d458
EH		 1559 if (kvm_enabled()) {
1560 def->kvm_features |= kvm_default_features;
1561 }
077c68c3
IM		 1562 def->ext_features |= CPUID_EXT_HYPERVISOR;
1563
8f961357 1564 if (cpu_x86_parse_featurestr(def, features) < 0) {
fa2db3c4
IM		 1565 error_setg(&error, "Invalid cpu_model string format: %s", cpu_model);
1566 goto out;
8f961357 1567 }
99b88a17 1568 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", &error);
8e1898bf 1569 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1570 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1571 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1572 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1573 env->cpuid_features = def->features;
c6dc6f63
AP		 1574 env->cpuid_ext_features = def->ext_features;
1575 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1576 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1577 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1578 env->cpuid_kvm_features = def->kvm_features;
296acb64 1579 env->cpuid_svm_features = def->svm_features;
b3baa152 1580 env->cpuid_ext4_features = def->ext4_features;
a9321a4d 1581 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
b3baa152 1582 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1583 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1584 "tsc-frequency", &error);
3b671a40 1585
938d4c25 1586 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
fa2db3c4
IM		 1587
1588out:
1589 g_strfreev(model_pieces);
18eb473f
IM		 1590 if (error) {
1591 fprintf(stderr, "%s\n", error_get_pretty(error));
71ad61d3 1592 error_free(error);
fa2db3c4 1593 return -1;
71ad61d3 1594 }
c6dc6f63
AP		 1595 return 0;
1596}
1597
1598#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1599
0e26b7b8
BS		 1600void cpu_clear_apic_feature(CPUX86State *env)
1601{
1602 env->cpuid_features &= ~CPUID_APIC;
1603}
1604
c6dc6f63
AP		 1605#endif /* !CONFIG_USER_ONLY */
1606
c04321b3 1607/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1608 */
1609void x86_cpudef_setup(void)
1610{
93bfef4c
CV		 1611 int i, j;
1612 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1613
1614 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291 1615 x86_def_t *def = &builtin_x86_defs[i];
93bfef4c
CV		 1616
1617 /* Look for specific "cpudef" models that */
09faecf2 1618 /* have the QEMU version in .model_id */
93bfef4c 1619 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1620 if (strcmp(model_with_versions[j], def->name) == 0) {
1621 pstrcpy(def->model_id, sizeof(def->model_id),
1622 "QEMU Virtual CPU version ");
1623 pstrcat(def->model_id, sizeof(def->model_id),
1624 qemu_get_version());
93bfef4c
CV		 1625 break;
1626 }
1627 }
c6dc6f63 1628 }
c6dc6f63
AP		 1629}
1630
c6dc6f63
AP		 1631static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1632 uint32_t *ecx, uint32_t *edx)
1633{
1634 *ebx = env->cpuid_vendor1;
1635 *edx = env->cpuid_vendor2;
1636 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 1637}
1638
1639void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1640 uint32_t *eax, uint32_t *ebx,
1641 uint32_t *ecx, uint32_t *edx)
1642{
a60f24b5
AF		 1643 X86CPU *cpu = x86_env_get_cpu(env);
1644 CPUState *cs = CPU(cpu);
1645
c6dc6f63
AP		 1646 /* test if maximum index reached */
1647 if (index & 0x80000000) {
b3baa152
BW		 1648 if (index > env->cpuid_xlevel) {
1649 if (env->cpuid_xlevel2 > 0) {
1650 /* Handle the Centaur's CPUID instruction. */
1651 if (index > env->cpuid_xlevel2) {
1652 index = env->cpuid_xlevel2;
1653 } else if (index < 0xC0000000) {
1654 index = env->cpuid_xlevel;
1655 }
1656 } else {
57f26ae7
EH		 1657 /* Intel documentation states that invalid EAX input will
1658 * return the same information as EAX=cpuid_level
1659 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1660 */
1661 index = env->cpuid_level;
b3baa152
BW		 1662 }
1663 }
c6dc6f63
AP		 1664 } else {
1665 if (index > env->cpuid_level)
1666 index = env->cpuid_level;
1667 }
1668
1669 switch(index) {
1670 case 0:
1671 *eax = env->cpuid_level;
1672 get_cpuid_vendor(env, ebx, ecx, edx);
1673 break;
1674 case 1:
1675 *eax = env->cpuid_version;
1676 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1677 *ecx = env->cpuid_ext_features;
1678 *edx = env->cpuid_features;
ce3960eb
AF		 1679 if (cs->nr_cores * cs->nr_threads > 1) {
1680 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 1681 *edx |= 1 << 28; /* HTT bit */
1682 }
1683 break;
1684 case 2:
1685 /* cache info: needed for Pentium Pro compatibility */
1686 *eax = 1;
1687 *ebx = 0;
1688 *ecx = 0;
1689 *edx = 0x2c307d;
1690 break;
1691 case 4:
1692 /* cache info: needed for Core compatibility */
ce3960eb
AF		 1693 if (cs->nr_cores > 1) {
1694 *eax = (cs->nr_cores - 1) << 26;
c6dc6f63 1695 } else {
2f7a21c4 1696 *eax = 0;
c6dc6f63
AP		 1697 }
1698 switch (count) {
1699 case 0: /* L1 dcache info */
1700 *eax |= 0x0000121;
1701 *ebx = 0x1c0003f;
1702 *ecx = 0x000003f;
1703 *edx = 0x0000001;
1704 break;
1705 case 1: /* L1 icache info */
1706 *eax |= 0x0000122;
1707 *ebx = 0x1c0003f;
1708 *ecx = 0x000003f;
1709 *edx = 0x0000001;
1710 break;
1711 case 2: /* L2 cache info */
1712 *eax |= 0x0000143;
ce3960eb
AF		 1713 if (cs->nr_threads > 1) {
1714 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63
AP		 1715 }
1716 *ebx = 0x3c0003f;
1717 *ecx = 0x0000fff;
1718 *edx = 0x0000001;
1719 break;
1720 default: /* end of info */
1721 *eax = 0;
1722 *ebx = 0;
1723 *ecx = 0;
1724 *edx = 0;
1725 break;
1726 }
1727 break;
1728 case 5:
1729 /* mwait info: needed for Core compatibility */
1730 *eax = 0; /* Smallest monitor-line size in bytes */
1731 *ebx = 0; /* Largest monitor-line size in bytes */
1732 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1733 *edx = 0;
1734 break;
1735 case 6:
1736 /* Thermal and Power Leaf */
1737 *eax = 0;
1738 *ebx = 0;
1739 *ecx = 0;
1740 *edx = 0;
1741 break;
f7911686 1742 case 7:
13526728
EH		 1743 /* Structured Extended Feature Flags Enumeration Leaf */
1744 if (count == 0) {
1745 *eax = 0; /* Maximum ECX value for sub-leaves */
a9321a4d 1746 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
13526728
EH		 1747 *ecx = 0; /* Reserved */
1748 *edx = 0; /* Reserved */
f7911686
YW		 1749 } else {
1750 *eax = 0;
1751 *ebx = 0;
1752 *ecx = 0;
1753 *edx = 0;
1754 }
1755 break;
c6dc6f63
AP		 1756 case 9:
1757 /* Direct Cache Access Information Leaf */
1758 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1759 *ebx = 0;
1760 *ecx = 0;
1761 *edx = 0;
1762 break;
1763 case 0xA:
1764 /* Architectural Performance Monitoring Leaf */
a0fa8208 1765 if (kvm_enabled()) {
a60f24b5 1766 KVMState *s = cs->kvm_state;
a0fa8208
GN		 1767
1768 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1769 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1770 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1771 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1772 } else {
1773 *eax = 0;
1774 *ebx = 0;
1775 *ecx = 0;
1776 *edx = 0;
1777 }
c6dc6f63 1778 break;
51e49430
SY		 1779 case 0xD:
1780 /* Processor Extended State */
1781 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1782 *eax = 0;
1783 *ebx = 0;
1784 *ecx = 0;
1785 *edx = 0;
1786 break;
1787 }
1788 if (kvm_enabled()) {
a60f24b5 1789 KVMState *s = cs->kvm_state;
ba9bc59e
JK		 1790
1791 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1792 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1793 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1794 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1795 } else {
1796 *eax = 0;
1797 *ebx = 0;
1798 *ecx = 0;
1799 *edx = 0;
1800 }
1801 break;
c6dc6f63
AP		 1802 case 0x80000000:
1803 *eax = env->cpuid_xlevel;
1804 *ebx = env->cpuid_vendor1;
1805 *edx = env->cpuid_vendor2;
1806 *ecx = env->cpuid_vendor3;
1807 break;
1808 case 0x80000001:
1809 *eax = env->cpuid_version;
1810 *ebx = 0;
1811 *ecx = env->cpuid_ext3_features;
1812 *edx = env->cpuid_ext2_features;
1813
1814 /* The Linux kernel checks for the CMPLegacy bit and
1815 * discards multiple thread information if it is set.
1816 * So dont set it here for Intel to make Linux guests happy.
1817 */
ce3960eb 1818 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 1819 uint32_t tebx, tecx, tedx;
1820 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1821 if (tebx != CPUID_VENDOR_INTEL_1 ||
1822 tedx != CPUID_VENDOR_INTEL_2 ||
1823 tecx != CPUID_VENDOR_INTEL_3) {
1824 *ecx |= 1 << 1; /* CmpLegacy bit */
1825 }
1826 }
c6dc6f63
AP		 1827 break;
1828 case 0x80000002:
1829 case 0x80000003:
1830 case 0x80000004:
1831 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1832 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1833 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1834 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1835 break;
1836 case 0x80000005:
1837 /* cache info (L1 cache) */
1838 *eax = 0x01ff01ff;
1839 *ebx = 0x01ff01ff;
1840 *ecx = 0x40020140;
1841 *edx = 0x40020140;
1842 break;
1843 case 0x80000006:
1844 /* cache info (L2 cache) */
1845 *eax = 0;
1846 *ebx = 0x42004200;
1847 *ecx = 0x02008140;
1848 *edx = 0;
1849 break;
1850 case 0x80000008:
1851 /* virtual & phys address size in low 2 bytes. */
1852/* XXX: This value must match the one used in the MMU code. */
1853 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1854 /* 64 bit processor */
1855/* XXX: The physical address space is limited to 42 bits in exec.c. */
1856 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1857 } else {
1858 if (env->cpuid_features & CPUID_PSE36)
1859 *eax = 0x00000024; /* 36 bits physical */
1860 else
1861 *eax = 0x00000020; /* 32 bits physical */
1862 }
1863 *ebx = 0;
1864 *ecx = 0;
1865 *edx = 0;
ce3960eb
AF		 1866 if (cs->nr_cores * cs->nr_threads > 1) {
1867 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 1868 }
1869 break;
1870 case 0x8000000A:
9f3fb565
EH		 1871 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1872 *eax = 0x00000001; /* SVM Revision */
1873 *ebx = 0x00000010; /* nr of ASIDs */
1874 *ecx = 0;
1875 *edx = env->cpuid_svm_features; /* optional features */
1876 } else {
1877 *eax = 0;
1878 *ebx = 0;
1879 *ecx = 0;
1880 *edx = 0;
1881 }
c6dc6f63 1882 break;
b3baa152
BW		 1883 case 0xC0000000:
1884 *eax = env->cpuid_xlevel2;
1885 *ebx = 0;
1886 *ecx = 0;
1887 *edx = 0;
1888 break;
1889 case 0xC0000001:
1890 /* Support for VIA CPU's CPUID instruction */
1891 *eax = env->cpuid_version;
1892 *ebx = 0;
1893 *ecx = 0;
1894 *edx = env->cpuid_ext4_features;
1895 break;
1896 case 0xC0000002:
1897 case 0xC0000003:
1898 case 0xC0000004:
1899 /* Reserved for the future, and now filled with zero */
1900 *eax = 0;
1901 *ebx = 0;
1902 *ecx = 0;
1903 *edx = 0;
1904 break;
c6dc6f63
AP		 1905 default:
1906 /* reserved values: zero */
1907 *eax = 0;
1908 *ebx = 0;
1909 *ecx = 0;
1910 *edx = 0;
1911 break;
1912 }
1913}
5fd2087a
AF		 1914
1915/* CPUClass::reset() */
1916static void x86_cpu_reset(CPUState *s)
1917{
1918 X86CPU *cpu = X86_CPU(s);
1919 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1920 CPUX86State *env = &cpu->env;
c1958aea
AF		 1921 int i;
1922
1923 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 1924 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
6fd2a026 1925 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
c1958aea 1926 }
5fd2087a
AF		 1927
1928 xcc->parent_reset(s);
1929
c1958aea
AF		 1930
1931 memset(env, 0, offsetof(CPUX86State, breakpoints));
1932
1933 tlb_flush(env, 1);
1934
1935 env->old_exception = -1;
1936
1937 /* init to reset state */
1938
1939#ifdef CONFIG_SOFTMMU
1940 env->hflags |= HF_SOFTMMU_MASK;
1941#endif
1942 env->hflags2 |= HF2_GIF_MASK;
1943
1944 cpu_x86_update_cr0(env, 0x60000010);
1945 env->a20_mask = ~0x0;
1946 env->smbase = 0x30000;
1947
1948 env->idt.limit = 0xffff;
1949 env->gdt.limit = 0xffff;
1950 env->ldt.limit = 0xffff;
1951 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1952 env->tr.limit = 0xffff;
1953 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1954
1955 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1956 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1957 DESC_R_MASK | DESC_A_MASK);
1958 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1959 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1960 DESC_A_MASK);
1961 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1962 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1963 DESC_A_MASK);
1964 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1965 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1966 DESC_A_MASK);
1967 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1968 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1969 DESC_A_MASK);
1970 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1971 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1972 DESC_A_MASK);
1973
1974 env->eip = 0xfff0;
1975 env->regs[R_EDX] = env->cpuid_version;
1976
1977 env->eflags = 0x2;
1978
1979 /* FPU init */
1980 for (i = 0; i < 8; i++) {
1981 env->fptags[i] = 1;
1982 }
1983 env->fpuc = 0x37f;
1984
1985 env->mxcsr = 0x1f80;
1986
1987 env->pat = 0x0007040600070406ULL;
1988 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1989
1990 memset(env->dr, 0, sizeof(env->dr));
1991 env->dr[6] = DR6_FIXED_1;
1992 env->dr[7] = DR7_FIXED_1;
1993 cpu_breakpoint_remove_all(env, BP_CPU);
1994 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 1995
1996#if !defined(CONFIG_USER_ONLY)
1997 /* We hard-wire the BSP to the first CPU. */
55e5c285 1998 if (s->cpu_index == 0) {
dd673288
IM		 1999 apic_designate_bsp(env->apic_state);
2000 }
2001
2002 env->halted = !cpu_is_bsp(cpu);
2003#endif
5fd2087a
AF		 2004}
2005
dd673288
IM		 2006#ifndef CONFIG_USER_ONLY
2007bool cpu_is_bsp(X86CPU *cpu)
2008{
2009 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2010}
65dee380
IM		 2011
2012/* TODO: remove me, when reset over QOM tree is implemented */
2013static void x86_cpu_machine_reset_cb(void *opaque)
2014{
2015 X86CPU *cpu = opaque;
2016 cpu_reset(CPU(cpu));
2017}
dd673288
IM		 2018#endif
2019
de024815
AF		 2020static void mce_init(X86CPU *cpu)
2021{
2022 CPUX86State *cenv = &cpu->env;
2023 unsigned int bank;
2024
2025 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2026 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2027 (CPUID_MCE | CPUID_MCA)) {
2028 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2029 cenv->mcg_ctl = ~(uint64_t)0;
2030 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2031 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2032 }
2033 }
2034}
2035
bdeec802
IM		 2036#define MSI_ADDR_BASE 0xfee00000
2037
2038#ifndef CONFIG_USER_ONLY
2039static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2040{
2041 static int apic_mapped;
2042 CPUX86State *env = &cpu->env;
449994eb 2043 APICCommonState *apic;
bdeec802
IM		 2044 const char *apic_type = "apic";
2045
2046 if (kvm_irqchip_in_kernel()) {
2047 apic_type = "kvm-apic";
2048 } else if (xen_enabled()) {
2049 apic_type = "xen-apic";
2050 }
2051
2052 env->apic_state = qdev_try_create(NULL, apic_type);
2053 if (env->apic_state == NULL) {
2054 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2055 return;
2056 }
2057
2058 object_property_add_child(OBJECT(cpu), "apic",
2059 OBJECT(env->apic_state), NULL);
2060 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2061 /* TODO: convert to link<> */
449994eb 2062 apic = APIC_COMMON(env->apic_state);
60671e58 2063 apic->cpu = cpu;
bdeec802
IM		 2064
2065 if (qdev_init(env->apic_state)) {
2066 error_setg(errp, "APIC device '%s' could not be initialized",
2067 object_get_typename(OBJECT(env->apic_state)));
2068 return;
2069 }
2070
2071 /* XXX: mapping more APICs at the same memory location */
2072 if (apic_mapped == 0) {
2073 /* NOTE: the APIC is directly connected to the CPU - it is not
2074 on the global memory bus. */
2075 /* XXX: what if the base changes? */
1356b98d 2076 sysbus_mmio_map(SYS_BUS_DEVICE(env->apic_state), 0, MSI_ADDR_BASE);
bdeec802
IM		 2077 apic_mapped = 1;
2078 }
2079}
2080#endif
2081
7a059953
AF		 2082void x86_cpu_realize(Object *obj, Error **errp)
2083{
2084 X86CPU *cpu = X86_CPU(obj);
b34d12d1
IM		 2085 CPUX86State *env = &cpu->env;
2086
2087 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2088 env->cpuid_level = 7;
2089 }
7a059953 2090
9b15cd9e
IM		 2091 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2092 * CPUID[1].EDX.
2093 */
2094 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2095 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2096 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2097 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2098 env->cpuid_ext2_features |= (env->cpuid_features
2099 & CPUID_EXT2_AMD_ALIASES);
2100 }
2101
4586f157
IM		 2102 if (!kvm_enabled()) {
2103 env->cpuid_features &= TCG_FEATURES;
2104 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2105 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2106#ifdef TARGET_X86_64
2107 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2108#endif
2109 );
2110 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2111 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2112 } else {
2113#ifdef CONFIG_KVM
2114 filter_features_for_kvm(cpu);
2115#endif
5ec01c2e
IM		 2116 if (check_cpuid && kvm_check_features_against_host(cpu)
2117 && enforce_cpuid) {
2118 error_setg(errp, "Host's CPU doesn't support requested features");
2119 return;
2120 }
4586f157
IM		 2121 }
2122
65dee380
IM		 2123#ifndef CONFIG_USER_ONLY
2124 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802
IM		 2125
2126 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2127 x86_cpu_apic_init(cpu, errp);
2128 if (error_is_set(errp)) {
2129 return;
2130 }
2131 }
65dee380
IM		 2132#endif
2133
7a059953
AF		 2134 mce_init(cpu);
2135 qemu_init_vcpu(&cpu->env);
65dee380 2136 cpu_reset(CPU(cpu));
7a059953
AF		 2137}
2138
8932cfdf
EH		 2139/* Enables contiguous-apic-ID mode, for compatibility */
2140static bool compat_apic_id_mode;
2141
2142void enable_compat_apic_id_mode(void)
2143{
2144 compat_apic_id_mode = true;
2145}
2146
cb41bad3
EH		 2147/* Calculates initial APIC ID for a specific CPU index
2148 *
2149 * Currently we need to be able to calculate the APIC ID from the CPU index
2150 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2151 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2152 * all CPUs up to max_cpus.
2153 */
2154uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2155{
8932cfdf
EH		 2156 uint32_t correct_id;
2157 static bool warned;
2158
2159 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2160 if (compat_apic_id_mode) {
2161 if (cpu_index != correct_id && !warned) {
2162 error_report("APIC IDs set in compatibility mode, "
2163 "CPU topology won't match the configuration");
2164 warned = true;
2165 }
2166 return cpu_index;
2167 } else {
2168 return correct_id;
2169 }
cb41bad3
EH		 2170}
2171
de024815
AF		 2172static void x86_cpu_initfn(Object *obj)
2173{
55e5c285 2174 CPUState *cs = CPU(obj);
de024815
AF		 2175 X86CPU *cpu = X86_CPU(obj);
2176 CPUX86State *env = &cpu->env;
d65e9815 2177 static int inited;
de024815
AF		 2178
2179 cpu_exec_init(env);
71ad61d3
AF		 2180
2181 object_property_add(obj, "family", "int",
95b8519d 2182 x86_cpuid_version_get_family,
71ad61d3 2183 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2184 object_property_add(obj, "model", "int",
67e30c83 2185 x86_cpuid_version_get_model,
c5291a4f 2186 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2187 object_property_add(obj, "stepping", "int",
35112e41 2188 x86_cpuid_version_get_stepping,
036e2222 2189 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2190 object_property_add(obj, "level", "int",
2191 x86_cpuid_get_level,
2192 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2193 object_property_add(obj, "xlevel", "int",
2194 x86_cpuid_get_xlevel,
2195 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2196 object_property_add_str(obj, "vendor",
2197 x86_cpuid_get_vendor,
2198 x86_cpuid_set_vendor, NULL);
938d4c25 2199 object_property_add_str(obj, "model-id",
63e886eb 2200 x86_cpuid_get_model_id,
938d4c25 2201 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2202 object_property_add(obj, "tsc-frequency", "int",
2203 x86_cpuid_get_tsc_freq,
2204 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 2205
cb41bad3 2206 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815
IM		 2207
2208 /* init various static tables used in TCG mode */
2209 if (tcg_enabled() && !inited) {
2210 inited = 1;
2211 optimize_flags_init();
2212#ifndef CONFIG_USER_ONLY
2213 cpu_set_debug_excp_handler(breakpoint_handler);
2214#endif
2215 }
de024815
AF		 2216}
2217
5fd2087a
AF		 2218static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2219{
2220 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2221 CPUClass *cc = CPU_CLASS(oc);
2222
2223 xcc->parent_reset = cc->reset;
2224 cc->reset = x86_cpu_reset;
2225}
2226
2227static const TypeInfo x86_cpu_type_info = {
2228 .name = TYPE_X86_CPU,
2229 .parent = TYPE_CPU,
2230 .instance_size = sizeof(X86CPU),
de024815 2231 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2232 .abstract = false,
2233 .class_size = sizeof(X86CPUClass),
2234 .class_init = x86_cpu_common_class_init,
2235};
2236
2237static void x86_cpu_register_types(void)
2238{
2239 type_register_static(&x86_cpu_type_info);
2240}
2241
2242type_init(x86_cpu_register_types)
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