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KVM: SVM: Add manipulation functions for CRx intercepts
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
9611c187 7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
631bc487 34#include <asm/kvm_para.h>
6aa8b732 35
63d1142f 36#include <asm/virtext.h>
229456fc 37#include "trace.h"
63d1142f 38
4ecac3fd
AK		 39#define __ex(x) __kvm_handle_fault_on_reboot(x)
40
6aa8b732
AK		 41MODULE_AUTHOR("Qumranet");
42MODULE_LICENSE("GPL");
43
44#define IOPM_ALLOC_ORDER 2
45#define MSRPM_ALLOC_ORDER 1
46
6aa8b732
AK		 47#define SEG_TYPE_LDT 2
48#define SEG_TYPE_BUSY_TSS16 3
49
6bc31bdc
AP		 50#define SVM_FEATURE_NPT (1 << 0)
51#define SVM_FEATURE_LBRV (1 << 1)
52#define SVM_FEATURE_SVML (1 << 2)
53#define SVM_FEATURE_NRIP (1 << 3)
54#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 55
410e4d57
JR		 56#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
24e09cbf
JR		 60#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
67ec6607
JR		 62static bool erratum_383_found __read_mostly;
63
6c8166a7
AK		 64static const u32 host_save_user_msrs[] = {
65#ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68#endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70};
71
72#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74struct kvm_vcpu;
75
e6aa9abd
JR		 76struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
4a810181 79 u64 vm_cr_msr;
e6aa9abd
JR		 80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
ce2ac085 87 u64 vmcb_iopm;
aad42c64 88
cd3ff653
JR		 89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
cda00082
JR		 92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
aad42c64 100 /* cache for intercepts of the guest */
4ee546b4 101 u32 intercept_cr;
aad42c64
JR		 102 u16 intercept_dr_read;
103 u16 intercept_dr_write;
104 u32 intercept_exceptions;
105 u64 intercept;
106
5bd2edc3
JR		 107 /* Nested Paging related state */
108 u64 nested_cr3;
e6aa9abd
JR		 109};
110
323c3d80
JR		 111#define MSRPM_OFFSETS 16
112static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
113
6c8166a7
AK		 114struct vcpu_svm {
115 struct kvm_vcpu vcpu;
116 struct vmcb *vmcb;
117 unsigned long vmcb_pa;
118 struct svm_cpu_data *svm_data;
119 uint64_t asid_generation;
120 uint64_t sysenter_esp;
121 uint64_t sysenter_eip;
122
123 u64 next_rip;
124
125 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
afe9e66f 126 struct {
dacccfdd
AK		 127 u16 fs;
128 u16 gs;
129 u16 ldt;
afe9e66f
AK		 130 u64 gs_base;
131 } host;
6c8166a7
AK		 132
133 u32 *msrpm;
6c8166a7 134
e6aa9abd 135 struct nested_state nested;
6be7d306
JK		 136
137 bool nmi_singlestep;
66b7138f
JK		 138
139 unsigned int3_injected;
140 unsigned long int3_rip;
631bc487 141 u32 apf_reason;
6c8166a7
AK		 142};
143
455716fa
JR		 144#define MSR_INVALID 0xffffffffU
145
ac72a9b7
JR		 146static struct svm_direct_access_msrs {
147 u32 index; /* Index of the MSR */
148 bool always; /* True if intercept is always on */
149} direct_access_msrs[] = {
8c06585d 150 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 151 { .index = MSR_IA32_SYSENTER_CS, .always = true },
152#ifdef CONFIG_X86_64
153 { .index = MSR_GS_BASE, .always = true },
154 { .index = MSR_FS_BASE, .always = true },
155 { .index = MSR_KERNEL_GS_BASE, .always = true },
156 { .index = MSR_LSTAR, .always = true },
157 { .index = MSR_CSTAR, .always = true },
158 { .index = MSR_SYSCALL_MASK, .always = true },
159#endif
160 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
161 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
162 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
163 { .index = MSR_IA32_LASTINTTOIP, .always = false },
164 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 165};
166
709ddebf
JR		 167/* enable NPT for AMD64 and X86 with PAE */
168#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
169static bool npt_enabled = true;
170#else
e0231715 171static bool npt_enabled;
709ddebf 172#endif
6c7dac72
JR		 173static int npt = 1;
174
175module_param(npt, int, S_IRUGO);
e3da3acd 176
4b6e4dca 177static int nested = 1;
236de055
AG		 178module_param(nested, int, S_IRUGO);
179
44874f84 180static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 181static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 182
410e4d57 183static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 184static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 185static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 186static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
187 bool has_error_code, u32 error_code);
188
a2fa3e9f
GH		 189static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
190{
fb3f0f51 191 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 192}
193
384c6368
JR		 194static void recalc_intercepts(struct vcpu_svm *svm)
195{
196 struct vmcb_control_area *c, *h;
197 struct nested_state *g;
198
199 if (!is_guest_mode(&svm->vcpu))
200 return;
201
202 c = &svm->vmcb->control;
203 h = &svm->nested.hsave->control;
204 g = &svm->nested;
205
4ee546b4 206 c->intercept_cr = h->intercept_cr | g->intercept_cr;
384c6368
JR		 207 c->intercept_dr_read = h->intercept_dr_read | g->intercept_dr_read;
208 c->intercept_dr_write = h->intercept_dr_write | g->intercept_dr_write;
209 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
210 c->intercept = h->intercept | g->intercept;
211}
212
4ee546b4
RJ		 213static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
214{
215 if (is_guest_mode(&svm->vcpu))
216 return svm->nested.hsave;
217 else
218 return svm->vmcb;
219}
220
221static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
222{
223 struct vmcb *vmcb = get_host_vmcb(svm);
224
225 vmcb->control.intercept_cr |= (1U << bit);
226
227 recalc_intercepts(svm);
228}
229
230static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
231{
232 struct vmcb *vmcb = get_host_vmcb(svm);
233
234 vmcb->control.intercept_cr &= ~(1U << bit);
235
236 recalc_intercepts(svm);
237}
238
239static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
240{
241 struct vmcb *vmcb = get_host_vmcb(svm);
242
243 return vmcb->control.intercept_cr & (1U << bit);
244}
245
2af9194d
JR		 246static inline void enable_gif(struct vcpu_svm *svm)
247{
248 svm->vcpu.arch.hflags |= HF_GIF_MASK;
249}
250
251static inline void disable_gif(struct vcpu_svm *svm)
252{
253 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
254}
255
256static inline bool gif_set(struct vcpu_svm *svm)
257{
258 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
259}
260
4866d5e3 261static unsigned long iopm_base;
6aa8b732
AK		 262
263struct kvm_ldttss_desc {
264 u16 limit0;
265 u16 base0;
e0231715
JR		 266 unsigned base1:8, type:5, dpl:2, p:1;
267 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 268 u32 base3;
269 u32 zero1;
270} __attribute__((packed));
271
272struct svm_cpu_data {
273 int cpu;
274
5008fdf5
AK		 275 u64 asid_generation;
276 u32 max_asid;
277 u32 next_asid;
6aa8b732
AK		 278 struct kvm_ldttss_desc *tss_desc;
279
280 struct page *save_area;
281};
282
283static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 284static uint32_t svm_features;
6aa8b732
AK		 285
286struct svm_init_data {
287 int cpu;
288 int r;
289};
290
291static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
292
9d8f549d 293#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 294#define MSRS_RANGE_SIZE 2048
295#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
296
455716fa
JR		 297static u32 svm_msrpm_offset(u32 msr)
298{
299 u32 offset;
300 int i;
301
302 for (i = 0; i < NUM_MSR_MAPS; i++) {
303 if (msr < msrpm_ranges[i] ||
304 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
305 continue;
306
307 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
308 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
309
310 /* Now we have the u8 offset - but need the u32 offset */
311 return offset / 4;
312 }
313
314 /* MSR not in any range */
315 return MSR_INVALID;
316}
317
6aa8b732
AK		 318#define MAX_INST_SIZE 15
319
6aa8b732
AK		 320static inline void clgi(void)
321{
4ecac3fd 322 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 323}
324
325static inline void stgi(void)
326{
4ecac3fd 327 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 328}
329
330static inline void invlpga(unsigned long addr, u32 asid)
331{
e0231715 332 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 333}
334
6aa8b732
AK		 335static inline void force_new_asid(struct kvm_vcpu *vcpu)
336{
a2fa3e9f 337 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 338}
339
340static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
341{
342 force_new_asid(vcpu);
343}
344
4b16184c
JR		 345static int get_npt_level(void)
346{
347#ifdef CONFIG_X86_64
348 return PT64_ROOT_LEVEL;
349#else
350 return PT32E_ROOT_LEVEL;
351#endif
352}
353
6aa8b732
AK		 354static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
355{
6dc696d4 356 vcpu->arch.efer = efer;
709ddebf 357 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 358 efer &= ~EFER_LME;
6aa8b732 359
9962d032 360 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
6aa8b732
AK		 361}
362
6aa8b732
AK		 363static int is_external_interrupt(u32 info)
364{
365 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
366 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
367}
368
2809f5d2
GC		 369static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
370{
371 struct vcpu_svm *svm = to_svm(vcpu);
372 u32 ret = 0;
373
374 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 375 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 376 return ret & mask;
377}
378
379static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
380{
381 struct vcpu_svm *svm = to_svm(vcpu);
382
383 if (mask == 0)
384 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
385 else
386 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
387
388}
389
6aa8b732
AK		 390static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
391{
a2fa3e9f
GH		 392 struct vcpu_svm *svm = to_svm(vcpu);
393
6bc31bdc
AP		 394 if (svm->vmcb->control.next_rip != 0)
395 svm->next_rip = svm->vmcb->control.next_rip;
396
a2fa3e9f 397 if (!svm->next_rip) {
851ba692 398 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 399 EMULATE_DONE)
400 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 401 return;
402 }
5fdbf976
MT		 403 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
404 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
405 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 406
5fdbf976 407 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 408 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 409}
410
116a4752 411static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 412 bool has_error_code, u32 error_code,
413 bool reinject)
116a4752
JK		 414{
415 struct vcpu_svm *svm = to_svm(vcpu);
416
e0231715
JR		 417 /*
418 * If we are within a nested VM we'd better #VMEXIT and let the guest
419 * handle the exception
420 */
ce7ddec4
JR		 421 if (!reinject &&
422 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 423 return;
424
2a6b20b8 425 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
66b7138f
JK		 426 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
427
428 /*
429 * For guest debugging where we have to reinject #BP if some
430 * INT3 is guest-owned:
431 * Emulate nRIP by moving RIP forward. Will fail if injection
432 * raises a fault that is not intercepted. Still better than
433 * failing in all cases.
434 */
435 skip_emulated_instruction(&svm->vcpu);
436 rip = kvm_rip_read(&svm->vcpu);
437 svm->int3_rip = rip + svm->vmcb->save.cs.base;
438 svm->int3_injected = rip - old_rip;
439 }
440
116a4752
JK		 441 svm->vmcb->control.event_inj = nr
442 | SVM_EVTINJ_VALID
443 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
444 | SVM_EVTINJ_TYPE_EXEPT;
445 svm->vmcb->control.event_inj_err = error_code;
446}
447
67ec6607
JR		 448static void svm_init_erratum_383(void)
449{
450 u32 low, high;
451 int err;
452 u64 val;
453
1be85a6d 454 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 455 return;
456
457 /* Use _safe variants to not break nested virtualization */
458 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
459 if (err)
460 return;
461
462 val |= (1ULL << 47);
463
464 low = lower_32_bits(val);
465 high = upper_32_bits(val);
466
467 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
468
469 erratum_383_found = true;
470}
471
6aa8b732
AK		 472static int has_svm(void)
473{
63d1142f 474 const char *msg;
6aa8b732 475
63d1142f 476 if (!cpu_has_svm(&msg)) {
ff81ff10 477 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 478 return 0;
479 }
480
6aa8b732
AK		 481 return 1;
482}
483
484static void svm_hardware_disable(void *garbage)
485{
2c8dceeb 486 cpu_svm_disable();
6aa8b732
AK		 487}
488
10474ae8 489static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 490{
491
0fe1e009 492 struct svm_cpu_data *sd;
6aa8b732 493 uint64_t efer;
89a27f4d 494 struct desc_ptr gdt_descr;
6aa8b732
AK		 495 struct desc_struct *gdt;
496 int me = raw_smp_processor_id();
497
10474ae8
AG		 498 rdmsrl(MSR_EFER, efer);
499 if (efer & EFER_SVME)
500 return -EBUSY;
501
6aa8b732 502 if (!has_svm()) {
e6732a5a
ZA		 503 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
504 me);
10474ae8 505 return -EINVAL;
6aa8b732 506 }
0fe1e009 507 sd = per_cpu(svm_data, me);
6aa8b732 508
0fe1e009 509 if (!sd) {
e6732a5a 510 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 511 me);
10474ae8 512 return -EINVAL;
6aa8b732
AK		 513 }
514
0fe1e009
TH		 515 sd->asid_generation = 1;
516 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
517 sd->next_asid = sd->max_asid + 1;
6aa8b732 518
d6ab1ed4 519 native_store_gdt(&gdt_descr);
89a27f4d 520 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 521 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 522
9962d032 523 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 524
d0316554 525 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 526
67ec6607
JR		 527 svm_init_erratum_383();
528
10474ae8 529 return 0;
6aa8b732
AK		 530}
531
0da1db75
JR		 532static void svm_cpu_uninit(int cpu)
533{
0fe1e009 534 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 535
0fe1e009 536 if (!sd)
0da1db75
JR		 537 return;
538
539 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 540 __free_page(sd->save_area);
541 kfree(sd);
0da1db75
JR		 542}
543
6aa8b732
AK		 544static int svm_cpu_init(int cpu)
545{
0fe1e009 546 struct svm_cpu_data *sd;
6aa8b732
AK		 547 int r;
548
0fe1e009
TH		 549 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
550 if (!sd)
6aa8b732 551 return -ENOMEM;
0fe1e009
TH		 552 sd->cpu = cpu;
553 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 554 r = -ENOMEM;
0fe1e009 555 if (!sd->save_area)
6aa8b732
AK		 556 goto err_1;
557
0fe1e009 558 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 559
560 return 0;
561
562err_1:
0fe1e009 563 kfree(sd);
6aa8b732
AK		 564 return r;
565
566}
567
ac72a9b7
JR		 568static bool valid_msr_intercept(u32 index)
569{
570 int i;
571
572 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
573 if (direct_access_msrs[i].index == index)
574 return true;
575
576 return false;
577}
578
bfc733a7
RR		 579static void set_msr_interception(u32 *msrpm, unsigned msr,
580 int read, int write)
6aa8b732 581{
455716fa
JR		 582 u8 bit_read, bit_write;
583 unsigned long tmp;
584 u32 offset;
6aa8b732 585
ac72a9b7
JR		 586 /*
587 * If this warning triggers extend the direct_access_msrs list at the
588 * beginning of the file
589 */
590 WARN_ON(!valid_msr_intercept(msr));
591
455716fa
JR		 592 offset = svm_msrpm_offset(msr);
593 bit_read = 2 * (msr & 0x0f);
594 bit_write = 2 * (msr & 0x0f) + 1;
595 tmp = msrpm[offset];
596
597 BUG_ON(offset == MSR_INVALID);
598
599 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
600 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
601
602 msrpm[offset] = tmp;
6aa8b732
AK		 603}
604
f65c229c 605static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 606{
607 int i;
608
f65c229c
JR		 609 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
610
ac72a9b7
JR		 611 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
612 if (!direct_access_msrs[i].always)
613 continue;
614
615 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
616 }
f65c229c
JR		 617}
618
323c3d80
JR		 619static void add_msr_offset(u32 offset)
620{
621 int i;
622
623 for (i = 0; i < MSRPM_OFFSETS; ++i) {
624
625 /* Offset already in list? */
626 if (msrpm_offsets[i] == offset)
bfc733a7 627 return;
323c3d80
JR		 628
629 /* Slot used by another offset? */
630 if (msrpm_offsets[i] != MSR_INVALID)
631 continue;
632
633 /* Add offset to list */
634 msrpm_offsets[i] = offset;
635
636 return;
6aa8b732 637 }
323c3d80
JR		 638
639 /*
640 * If this BUG triggers the msrpm_offsets table has an overflow. Just
641 * increase MSRPM_OFFSETS in this case.
642 */
bfc733a7 643 BUG();
6aa8b732
AK		 644}
645
323c3d80 646static void init_msrpm_offsets(void)
f65c229c 647{
323c3d80 648 int i;
f65c229c 649
323c3d80
JR		 650 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
651
652 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
653 u32 offset;
654
655 offset = svm_msrpm_offset(direct_access_msrs[i].index);
656 BUG_ON(offset == MSR_INVALID);
657
658 add_msr_offset(offset);
659 }
f65c229c
JR		 660}
661
24e09cbf
JR		 662static void svm_enable_lbrv(struct vcpu_svm *svm)
663{
664 u32 *msrpm = svm->msrpm;
665
666 svm->vmcb->control.lbr_ctl = 1;
667 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
668 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
669 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
670 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
671}
672
673static void svm_disable_lbrv(struct vcpu_svm *svm)
674{
675 u32 *msrpm = svm->msrpm;
676
677 svm->vmcb->control.lbr_ctl = 0;
678 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
679 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
680 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
681 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
682}
683
6aa8b732
AK		 684static __init int svm_hardware_setup(void)
685{
686 int cpu;
687 struct page *iopm_pages;
f65c229c 688 void *iopm_va;
6aa8b732
AK		 689 int r;
690
6aa8b732
AK		 691 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
692
693 if (!iopm_pages)
694 return -ENOMEM;
c8681339
AL		 695
696 iopm_va = page_address(iopm_pages);
697 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 698 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
699
323c3d80
JR		 700 init_msrpm_offsets();
701
50a37eb4
JR		 702 if (boot_cpu_has(X86_FEATURE_NX))
703 kvm_enable_efer_bits(EFER_NX);
704
1b2fd70c
AG		 705 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
706 kvm_enable_efer_bits(EFER_FFXSR);
707
236de055
AG		 708 if (nested) {
709 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 710 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 711 }
712
3230bb47 713 for_each_possible_cpu(cpu) {
6aa8b732
AK		 714 r = svm_cpu_init(cpu);
715 if (r)
f65c229c 716 goto err;
6aa8b732 717 }
33bd6a0b
JR		 718
719 svm_features = cpuid_edx(SVM_CPUID_FUNC);
720
2a6b20b8 721 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 722 npt_enabled = false;
723
6c7dac72
JR		 724 if (npt_enabled && !npt) {
725 printk(KERN_INFO "kvm: Nested Paging disabled\n");
726 npt_enabled = false;
727 }
728
18552672 729 if (npt_enabled) {
e3da3acd 730 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 731 kvm_enable_tdp();
5f4cb662
JR		 732 } else
733 kvm_disable_tdp();
e3da3acd 734
6aa8b732
AK		 735 return 0;
736
f65c229c 737err:
6aa8b732
AK		 738 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
739 iopm_base = 0;
740 return r;
741}
742
743static __exit void svm_hardware_unsetup(void)
744{
0da1db75
JR		 745 int cpu;
746
3230bb47 747 for_each_possible_cpu(cpu)
0da1db75
JR		 748 svm_cpu_uninit(cpu);
749
6aa8b732 750 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 751 iopm_base = 0;
6aa8b732
AK		 752}
753
754static void init_seg(struct vmcb_seg *seg)
755{
756 seg->selector = 0;
757 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 758 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 759 seg->limit = 0xffff;
760 seg->base = 0;
761}
762
763static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
764{
765 seg->selector = 0;
766 seg->attrib = SVM_SELECTOR_P_MASK | type;
767 seg->limit = 0xffff;
768 seg->base = 0;
769}
770
f4e1b3c8
ZA		 771static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
772{
773 struct vcpu_svm *svm = to_svm(vcpu);
774 u64 g_tsc_offset = 0;
775
2030753d 776 if (is_guest_mode(vcpu)) {
f4e1b3c8
ZA		 777 g_tsc_offset = svm->vmcb->control.tsc_offset -
778 svm->nested.hsave->control.tsc_offset;
779 svm->nested.hsave->control.tsc_offset = offset;
780 }
781
782 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
783}
784
e48672fa
ZA		 785static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
786{
787 struct vcpu_svm *svm = to_svm(vcpu);
788
789 svm->vmcb->control.tsc_offset += adjustment;
2030753d 790 if (is_guest_mode(vcpu))
e48672fa
ZA		 791 svm->nested.hsave->control.tsc_offset += adjustment;
792}
793
e6101a96 794static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 795{
e6101a96
JR		 796 struct vmcb_control_area *control = &svm->vmcb->control;
797 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 798
bff78274 799 svm->vcpu.fpu_active = 1;
4ee546b4 800 svm->vcpu.arch.hflags = 0;
bff78274 801
4ee546b4
RJ		 802 set_cr_intercept(svm, INTERCEPT_CR0_READ);
803 set_cr_intercept(svm, INTERCEPT_CR3_READ);
804 set_cr_intercept(svm, INTERCEPT_CR4_READ);
805 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
806 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
807 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
808 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
6aa8b732 809
e0231715 810 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 811 INTERCEPT_DR1_MASK |
812 INTERCEPT_DR2_MASK |
727f5a23
JK		 813 INTERCEPT_DR3_MASK |
814 INTERCEPT_DR4_MASK |
815 INTERCEPT_DR5_MASK |
816 INTERCEPT_DR6_MASK |
817 INTERCEPT_DR7_MASK;
6aa8b732 818
e0231715 819 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 820 INTERCEPT_DR1_MASK |
821 INTERCEPT_DR2_MASK |
822 INTERCEPT_DR3_MASK |
727f5a23 823 INTERCEPT_DR4_MASK |
6aa8b732 824 INTERCEPT_DR5_MASK |
727f5a23 825 INTERCEPT_DR6_MASK |
6aa8b732
AK		 826 INTERCEPT_DR7_MASK;
827
7aa81cc0 828 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 829 (1 << UD_VECTOR) |
830 (1 << MC_VECTOR);
6aa8b732
AK		 831
832
e0231715 833 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 834 (1ULL << INTERCEPT_NMI) |
0152527b 835 (1ULL << INTERCEPT_SMI) |
d225157b 836 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 837 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 838 (1ULL << INTERCEPT_INVD) |
6aa8b732 839 (1ULL << INTERCEPT_HLT) |
a7052897 840 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 841 (1ULL << INTERCEPT_INVLPGA) |
842 (1ULL << INTERCEPT_IOIO_PROT) |
843 (1ULL << INTERCEPT_MSR_PROT) |
844 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 845 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 846 (1ULL << INTERCEPT_VMRUN) |
847 (1ULL << INTERCEPT_VMMCALL) |
848 (1ULL << INTERCEPT_VMLOAD) |
849 (1ULL << INTERCEPT_VMSAVE) |
850 (1ULL << INTERCEPT_STGI) |
851 (1ULL << INTERCEPT_CLGI) |
916ce236 852 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 853 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 854 (1ULL << INTERCEPT_MONITOR) |
855 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 856
857 control->iopm_base_pa = iopm_base;
f65c229c 858 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 859 control->int_ctl = V_INTR_MASKING_MASK;
860
861 init_seg(&save->es);
862 init_seg(&save->ss);
863 init_seg(&save->ds);
864 init_seg(&save->fs);
865 init_seg(&save->gs);
866
867 save->cs.selector = 0xf000;
868 /* Executable/Readable Code Segment */
869 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
870 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
871 save->cs.limit = 0xffff;
d92899a0
AK		 872 /*
873 * cs.base should really be 0xffff0000, but vmx can't handle that, so
874 * be consistent with it.
875 *
876 * Replace when we have real mode working for vmx.
877 */
878 save->cs.base = 0xf0000;
6aa8b732
AK		 879
880 save->gdtr.limit = 0xffff;
881 save->idtr.limit = 0xffff;
882
883 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
884 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
885
eaa48512 886 svm_set_efer(&svm->vcpu, 0);
d77c26fc 887 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 888 save->dr7 = 0x400;
889 save->rflags = 2;
890 save->rip = 0x0000fff0;
5fdbf976 891 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 892
e0231715
JR		 893 /*
894 * This is the guest-visible cr0 value.
18fa000a 895 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 896 */
678041ad
MT		 897 svm->vcpu.arch.cr0 = 0;
898 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
18fa000a 899
66aee91a 900 save->cr4 = X86_CR4_PAE;
6aa8b732 901 /* rdx = ?? */
709ddebf
JR		 902
903 if (npt_enabled) {
904 /* Setup VMCB for Nested Paging */
905 control->nested_ctl = 1;
a7052897
MT		 906 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
907 (1ULL << INTERCEPT_INVLPG));
709ddebf 908 control->intercept_exceptions &= ~(1 << PF_VECTOR);
4ee546b4
RJ		 909 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
910 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
709ddebf 911 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 912 save->cr3 = 0;
913 save->cr4 = 0;
914 }
a79d2f18 915 force_new_asid(&svm->vcpu);
1371d904 916
e6aa9abd 917 svm->nested.vmcb = 0;
2af9194d
JR		 918 svm->vcpu.arch.hflags = 0;
919
2a6b20b8 920 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
565d0998
ML		 921 control->pause_filter_count = 3000;
922 control->intercept |= (1ULL << INTERCEPT_PAUSE);
923 }
924
2af9194d 925 enable_gif(svm);
6aa8b732
AK		 926}
927
e00c8cf2 928static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 929{
930 struct vcpu_svm *svm = to_svm(vcpu);
931
e6101a96 932 init_vmcb(svm);
70433389 933
c5af89b6 934 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 935 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 936 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
937 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 938 }
5fdbf976
MT		 939 vcpu->arch.regs_avail = ~0;
940 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 941
942 return 0;
04d2cc77
AK		 943}
944
fb3f0f51 945static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 946{
a2fa3e9f 947 struct vcpu_svm *svm;
6aa8b732 948 struct page *page;
f65c229c 949 struct page *msrpm_pages;
b286d5d8 950 struct page *hsave_page;
3d6368ef 951 struct page *nested_msrpm_pages;
fb3f0f51 952 int err;
6aa8b732 953
c16f862d 954 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 955 if (!svm) {
956 err = -ENOMEM;
957 goto out;
958 }
959
960 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
961 if (err)
962 goto free_svm;
963
b7af4043 964 err = -ENOMEM;
6aa8b732 965 page = alloc_page(GFP_KERNEL);
b7af4043 966 if (!page)
fb3f0f51 967 goto uninit;
6aa8b732 968
f65c229c
JR		 969 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
970 if (!msrpm_pages)
b7af4043 971 goto free_page1;
3d6368ef
AG		 972
973 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
974 if (!nested_msrpm_pages)
b7af4043 975 goto free_page2;
f65c229c 976
b286d5d8
AG		 977 hsave_page = alloc_page(GFP_KERNEL);
978 if (!hsave_page)
b7af4043
TY		 979 goto free_page3;
980
e6aa9abd 981 svm->nested.hsave = page_address(hsave_page);
b286d5d8 982
b7af4043
TY		 983 svm->msrpm = page_address(msrpm_pages);
984 svm_vcpu_init_msrpm(svm->msrpm);
985
e6aa9abd 986 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 987 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 988
a2fa3e9f
GH		 989 svm->vmcb = page_address(page);
990 clear_page(svm->vmcb);
991 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
992 svm->asid_generation = 0;
e6101a96 993 init_vmcb(svm);
99e3e30a 994 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 995
10ab25cd
JK		 996 err = fx_init(&svm->vcpu);
997 if (err)
998 goto free_page4;
999
ad312c7c 1000 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 1001 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 1002 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 1003
fb3f0f51 1004 return &svm->vcpu;
36241b8c 1005
10ab25cd
JK		 1006free_page4:
1007 __free_page(hsave_page);
b7af4043
TY		 1008free_page3:
1009 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1010free_page2:
1011 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1012free_page1:
1013 __free_page(page);
fb3f0f51
RR		 1014uninit:
1015 kvm_vcpu_uninit(&svm->vcpu);
1016free_svm:
a4770347 1017 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 1018out:
1019 return ERR_PTR(err);
6aa8b732
AK		 1020}
1021
1022static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1023{
a2fa3e9f
GH		 1024 struct vcpu_svm *svm = to_svm(vcpu);
1025
fb3f0f51 1026 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 1027 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 1028 __free_page(virt_to_page(svm->nested.hsave));
1029 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 1030 kvm_vcpu_uninit(vcpu);
a4770347 1031 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 1032}
1033
15ad7146 1034static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1035{
a2fa3e9f 1036 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 1037 int i;
0cc5064d 1038
0cc5064d 1039 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1040 svm->asid_generation = 0;
0cc5064d 1041 }
94dfbdb3 1042
82ca2d10
AK		 1043#ifdef CONFIG_X86_64
1044 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1045#endif
dacccfdd
AK		 1046 savesegment(fs, svm->host.fs);
1047 savesegment(gs, svm->host.gs);
1048 svm->host.ldt = kvm_read_ldt();
1049
94dfbdb3 1050 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1051 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1052}
1053
1054static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1055{
a2fa3e9f 1056 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1057 int i;
1058
e1beb1d3 1059 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1060 kvm_load_ldt(svm->host.ldt);
1061#ifdef CONFIG_X86_64
1062 loadsegment(fs, svm->host.fs);
1063 load_gs_index(svm->host.gs);
1064 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1065#else
1066 loadsegment(gs, svm->host.gs);
1067#endif
94dfbdb3 1068 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1069 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1070}
1071
6aa8b732
AK		 1072static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1073{
a2fa3e9f 1074 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 1075}
1076
1077static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1078{
a2fa3e9f 1079 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1080}
1081
6de4f3ad
AK		 1082static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1083{
1084 switch (reg) {
1085 case VCPU_EXREG_PDPTR:
1086 BUG_ON(!npt_enabled);
ff03a073 1087 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
6de4f3ad
AK		 1088 break;
1089 default:
1090 BUG();
1091 }
1092}
1093
f0b85051
AG		 1094static void svm_set_vintr(struct vcpu_svm *svm)
1095{
1096 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1097}
1098
1099static void svm_clear_vintr(struct vcpu_svm *svm)
1100{
1101 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1102}
1103
6aa8b732
AK		 1104static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1105{
a2fa3e9f 1106 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1107
1108 switch (seg) {
1109 case VCPU_SREG_CS: return &save->cs;
1110 case VCPU_SREG_DS: return &save->ds;
1111 case VCPU_SREG_ES: return &save->es;
1112 case VCPU_SREG_FS: return &save->fs;
1113 case VCPU_SREG_GS: return &save->gs;
1114 case VCPU_SREG_SS: return &save->ss;
1115 case VCPU_SREG_TR: return &save->tr;
1116 case VCPU_SREG_LDTR: return &save->ldtr;
1117 }
1118 BUG();
8b6d44c7 1119 return NULL;
6aa8b732
AK		 1120}
1121
1122static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1123{
1124 struct vmcb_seg *s = svm_seg(vcpu, seg);
1125
1126 return s->base;
1127}
1128
1129static void svm_get_segment(struct kvm_vcpu *vcpu,
1130 struct kvm_segment *var, int seg)
1131{
1132 struct vmcb_seg *s = svm_seg(vcpu, seg);
1133
1134 var->base = s->base;
1135 var->limit = s->limit;
1136 var->selector = s->selector;
1137 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1138 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1139 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1140 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1141 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1142 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1143 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1144 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1145
e0231715
JR		 1146 /*
1147 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1148 * for cross vendor migration purposes by "not present"
1149 */
1150 var->unusable = !var->present || (var->type == 0);
1151
1fbdc7a5
AP		 1152 switch (seg) {
1153 case VCPU_SREG_CS:
1154 /*
1155 * SVM always stores 0 for the 'G' bit in the CS selector in
1156 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1157 * Intel's VMENTRY has a check on the 'G' bit.
1158 */
25022acc 1159 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1160 break;
1161 case VCPU_SREG_TR:
1162 /*
1163 * Work around a bug where the busy flag in the tr selector
1164 * isn't exposed
1165 */
c0d09828 1166 var->type |= 0x2;
1fbdc7a5
AP		 1167 break;
1168 case VCPU_SREG_DS:
1169 case VCPU_SREG_ES:
1170 case VCPU_SREG_FS:
1171 case VCPU_SREG_GS:
1172 /*
1173 * The accessed bit must always be set in the segment
1174 * descriptor cache, although it can be cleared in the
1175 * descriptor, the cached bit always remains at 1. Since
1176 * Intel has a check on this, set it here to support
1177 * cross-vendor migration.
1178 */
1179 if (!var->unusable)
1180 var->type |= 0x1;
1181 break;
b586eb02 1182 case VCPU_SREG_SS:
e0231715
JR		 1183 /*
1184 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1185 * descriptor is left as 1, although the whole segment has
1186 * been made unusable. Clear it here to pass an Intel VMX
1187 * entry check when cross vendor migrating.
1188 */
1189 if (var->unusable)
1190 var->db = 0;
1191 break;
1fbdc7a5 1192 }
6aa8b732
AK		 1193}
1194
2e4d2653
IE		 1195static int svm_get_cpl(struct kvm_vcpu *vcpu)
1196{
1197 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1198
1199 return save->cpl;
1200}
1201
89a27f4d 1202static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1203{
a2fa3e9f
GH		 1204 struct vcpu_svm *svm = to_svm(vcpu);
1205
89a27f4d
GN		 1206 dt->size = svm->vmcb->save.idtr.limit;
1207 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1208}
1209
89a27f4d 1210static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1211{
a2fa3e9f
GH		 1212 struct vcpu_svm *svm = to_svm(vcpu);
1213
89a27f4d
GN		 1214 svm->vmcb->save.idtr.limit = dt->size;
1215 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1216}
1217
89a27f4d 1218static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1219{
a2fa3e9f
GH		 1220 struct vcpu_svm *svm = to_svm(vcpu);
1221
89a27f4d
GN		 1222 dt->size = svm->vmcb->save.gdtr.limit;
1223 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1224}
1225
89a27f4d 1226static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1227{
a2fa3e9f
GH		 1228 struct vcpu_svm *svm = to_svm(vcpu);
1229
89a27f4d
GN		 1230 svm->vmcb->save.gdtr.limit = dt->size;
1231 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1232}
1233
e8467fda
AK		 1234static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1235{
1236}
1237
25c4c276 1238static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1239{
1240}
1241
d225157b
AK		 1242static void update_cr0_intercept(struct vcpu_svm *svm)
1243{
1244 ulong gcr0 = svm->vcpu.arch.cr0;
1245 u64 *hcr0 = &svm->vmcb->save.cr0;
1246
1247 if (!svm->vcpu.fpu_active)
1248 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1249 else
1250 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1251 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1252
1253
1254 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
4ee546b4
RJ		 1255 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1256 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b 1257 } else {
4ee546b4
RJ		 1258 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1259 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b
AK		 1260 }
1261}
1262
6aa8b732
AK		 1263static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1264{
a2fa3e9f
GH		 1265 struct vcpu_svm *svm = to_svm(vcpu);
1266
2030753d 1267 if (is_guest_mode(vcpu)) {
7f5d8b56
JR		 1268 /*
1269 * We are here because we run in nested mode, the host kvm
1270 * intercepts cr0 writes but the l1 hypervisor does not.
1271 * But the L1 hypervisor may intercept selective cr0 writes.
1272 * This needs to be checked here.
1273 */
1274 unsigned long old, new;
1275
1276 /* Remove bits that would trigger a real cr0 write intercept */
1277 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1278 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1279
1280 if (old == new) {
1281 /* cr0 write with ts and mp unchanged */
1282 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
cda00082
JR		 1283 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1284 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1285 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1286 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7f5d8b56 1287 return;
cda00082 1288 }
7f5d8b56
JR		 1289 }
1290 }
1291
05b3e0c2 1292#ifdef CONFIG_X86_64
f6801dff 1293 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1294 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1295 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1296 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1297 }
1298
d77c26fc 1299 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1300 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1301 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1302 }
1303 }
1304#endif
ad312c7c 1305 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1306
1307 if (!npt_enabled)
1308 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1309
1310 if (!vcpu->fpu_active)
334df50a 1311 cr0 |= X86_CR0_TS;
709ddebf
JR		 1312 /*
1313 * re-enable caching here because the QEMU bios
1314 * does not do it - this results in some delay at
1315 * reboot
1316 */
1317 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1318 svm->vmcb->save.cr0 = cr0;
d225157b 1319 update_cr0_intercept(svm);
6aa8b732
AK		 1320}
1321
1322static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1323{
6394b649 1324 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1325 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1326
1327 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1328 force_new_asid(vcpu);
6394b649 1329
ec077263
JR		 1330 vcpu->arch.cr4 = cr4;
1331 if (!npt_enabled)
1332 cr4 |= X86_CR4_PAE;
6394b649 1333 cr4 |= host_cr4_mce;
ec077263 1334 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1335}
1336
1337static void svm_set_segment(struct kvm_vcpu *vcpu,
1338 struct kvm_segment *var, int seg)
1339{
a2fa3e9f 1340 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1341 struct vmcb_seg *s = svm_seg(vcpu, seg);
1342
1343 s->base = var->base;
1344 s->limit = var->limit;
1345 s->selector = var->selector;
1346 if (var->unusable)
1347 s->attrib = 0;
1348 else {
1349 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1350 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1351 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1352 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1353 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1354 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1355 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1356 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1357 }
1358 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1359 svm->vmcb->save.cpl
1360 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1361 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1362
1363}
1364
44c11430 1365static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1366{
d0bfb940
JK		 1367 struct vcpu_svm *svm = to_svm(vcpu);
1368
d0bfb940
JK		 1369 svm->vmcb->control.intercept_exceptions &=
1370 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1371
6be7d306 1372 if (svm->nmi_singlestep)
44c11430
GN		 1373 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1374
d0bfb940
JK		 1375 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1376 if (vcpu->guest_debug &
1377 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1378 svm->vmcb->control.intercept_exceptions |=
1379 1 << DB_VECTOR;
1380 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1381 svm->vmcb->control.intercept_exceptions |=
1382 1 << BP_VECTOR;
1383 } else
1384 vcpu->guest_debug = 0;
44c11430
GN		 1385}
1386
355be0b9 1387static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1388{
44c11430
GN		 1389 struct vcpu_svm *svm = to_svm(vcpu);
1390
ae675ef0
JK		 1391 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1392 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1393 else
1394 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1395
355be0b9 1396 update_db_intercept(vcpu);
6aa8b732
AK		 1397}
1398
0fe1e009 1399static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1400{
0fe1e009
TH		 1401 if (sd->next_asid > sd->max_asid) {
1402 ++sd->asid_generation;
1403 sd->next_asid = 1;
a2fa3e9f 1404 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1405 }
1406
0fe1e009
TH		 1407 svm->asid_generation = sd->asid_generation;
1408 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1409}
1410
020df079 1411static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1412{
42dbaa5a 1413 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1414
020df079 1415 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1416}
1417
851ba692 1418static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1419{
631bc487 1420 u64 fault_address = svm->vmcb->control.exit_info_2;
6aa8b732 1421 u32 error_code;
631bc487 1422 int r = 1;
6aa8b732 1423
631bc487
GN		 1424 switch (svm->apf_reason) {
1425 default:
1426 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1427
631bc487
GN		 1428 trace_kvm_page_fault(fault_address, error_code);
1429 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1430 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1431 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1432 break;
1433 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1434 svm->apf_reason = 0;
1435 local_irq_disable();
1436 kvm_async_pf_task_wait(fault_address);
1437 local_irq_enable();
1438 break;
1439 case KVM_PV_REASON_PAGE_READY:
1440 svm->apf_reason = 0;
1441 local_irq_disable();
1442 kvm_async_pf_task_wake(fault_address);
1443 local_irq_enable();
1444 break;
1445 }
1446 return r;
6aa8b732
AK		 1447}
1448
851ba692 1449static int db_interception(struct vcpu_svm *svm)
d0bfb940 1450{
851ba692
AK		 1451 struct kvm_run *kvm_run = svm->vcpu.run;
1452
d0bfb940 1453 if (!(svm->vcpu.guest_debug &
44c11430 1454 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1455 !svm->nmi_singlestep) {
d0bfb940
JK		 1456 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1457 return 1;
1458 }
44c11430 1459
6be7d306
JK		 1460 if (svm->nmi_singlestep) {
1461 svm->nmi_singlestep = false;
44c11430
GN		 1462 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1463 svm->vmcb->save.rflags &=
1464 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1465 update_db_intercept(&svm->vcpu);
1466 }
1467
1468 if (svm->vcpu.guest_debug &
e0231715 1469 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1470 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1471 kvm_run->debug.arch.pc =
1472 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1473 kvm_run->debug.arch.exception = DB_VECTOR;
1474 return 0;
1475 }
1476
1477 return 1;
d0bfb940
JK		 1478}
1479
851ba692 1480static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1481{
851ba692
AK		 1482 struct kvm_run *kvm_run = svm->vcpu.run;
1483
d0bfb940
JK		 1484 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1485 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1486 kvm_run->debug.arch.exception = BP_VECTOR;
1487 return 0;
1488}
1489
851ba692 1490static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1491{
1492 int er;
1493
851ba692 1494 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1495 if (er != EMULATE_DONE)
7ee5d940 1496 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1497 return 1;
1498}
1499
6b52d186 1500static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1501{
6b52d186 1502 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1503 u32 excp;
1504
2030753d 1505 if (is_guest_mode(vcpu)) {
66a562f7
JR		 1506 u32 h_excp, n_excp;
1507
1508 h_excp = svm->nested.hsave->control.intercept_exceptions;
1509 n_excp = svm->nested.intercept_exceptions;
1510 h_excp &= ~(1 << NM_VECTOR);
1511 excp = h_excp | n_excp;
1512 } else {
1513 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1514 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1515 }
1516
1517 svm->vmcb->control.intercept_exceptions = excp;
1518
e756fc62 1519 svm->vcpu.fpu_active = 1;
d225157b 1520 update_cr0_intercept(svm);
6b52d186 1521}
a2fa3e9f 1522
6b52d186
AK		 1523static int nm_interception(struct vcpu_svm *svm)
1524{
1525 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1526 return 1;
7807fa6c
AL		 1527}
1528
67ec6607
JR		 1529static bool is_erratum_383(void)
1530{
1531 int err, i;
1532 u64 value;
1533
1534 if (!erratum_383_found)
1535 return false;
1536
1537 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1538 if (err)
1539 return false;
1540
1541 /* Bit 62 may or may not be set for this mce */
1542 value &= ~(1ULL << 62);
1543
1544 if (value != 0xb600000000010015ULL)
1545 return false;
1546
1547 /* Clear MCi_STATUS registers */
1548 for (i = 0; i < 6; ++i)
1549 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1550
1551 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1552 if (!err) {
1553 u32 low, high;
1554
1555 value &= ~(1ULL << 2);
1556 low = lower_32_bits(value);
1557 high = upper_32_bits(value);
1558
1559 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1560 }
1561
1562 /* Flush tlb to evict multi-match entries */
1563 __flush_tlb_all();
1564
1565 return true;
1566}
1567
fe5913e4 1568static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1569{
67ec6607
JR		 1570 if (is_erratum_383()) {
1571 /*
1572 * Erratum 383 triggered. Guest state is corrupt so kill the
1573 * guest.
1574 */
1575 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1576
a8eeb04a 1577 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1578
1579 return;
1580 }
1581
53371b50
JR		 1582 /*
1583 * On an #MC intercept the MCE handler is not called automatically in
1584 * the host. So do it by hand here.
1585 */
1586 asm volatile (
1587 "int $0x12\n");
1588 /* not sure if we ever come back to this point */
1589
fe5913e4
JR		 1590 return;
1591}
1592
1593static int mc_interception(struct vcpu_svm *svm)
1594{
53371b50
JR		 1595 return 1;
1596}
1597
851ba692 1598static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1599{
851ba692
AK		 1600 struct kvm_run *kvm_run = svm->vcpu.run;
1601
46fe4ddd
JR		 1602 /*
1603 * VMCB is undefined after a SHUTDOWN intercept
1604 * so reinitialize it.
1605 */
a2fa3e9f 1606 clear_page(svm->vmcb);
e6101a96 1607 init_vmcb(svm);
46fe4ddd
JR		 1608
1609 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1610 return 0;
1611}
1612
851ba692 1613static int io_interception(struct vcpu_svm *svm)
6aa8b732 1614{
cf8f70bf 1615 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1616 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1617 int size, in, string;
039576c0 1618 unsigned port;
6aa8b732 1619
e756fc62 1620 ++svm->vcpu.stat.io_exits;
e70669ab 1621 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1622 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1623 if (string || in)
6d77dbfc 1624 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1625
039576c0
AK		 1626 port = io_info >> 16;
1627 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1628 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1629 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1630
1631 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1632}
1633
851ba692 1634static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1635{
1636 return 1;
1637}
1638
851ba692 1639static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1640{
1641 ++svm->vcpu.stat.irq_exits;
1642 return 1;
1643}
1644
851ba692 1645static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1646{
1647 return 1;
1648}
1649
851ba692 1650static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1651{
5fdbf976 1652 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1653 skip_emulated_instruction(&svm->vcpu);
1654 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1655}
1656
851ba692 1657static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1658{
5fdbf976 1659 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1660 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1661 kvm_emulate_hypercall(&svm->vcpu);
1662 return 1;
02e235bc
AK		 1663}
1664
5bd2edc3
JR		 1665static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1666{
1667 struct vcpu_svm *svm = to_svm(vcpu);
1668
1669 return svm->nested.nested_cr3;
1670}
1671
1672static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1673 unsigned long root)
1674{
1675 struct vcpu_svm *svm = to_svm(vcpu);
1676
1677 svm->vmcb->control.nested_cr3 = root;
1678 force_new_asid(vcpu);
1679}
1680
6389ee94
AK		 1681static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1682 struct x86_exception *fault)
5bd2edc3
JR		 1683{
1684 struct vcpu_svm *svm = to_svm(vcpu);
1685
1686 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1687 svm->vmcb->control.exit_code_hi = 0;
6389ee94
AK		 1688 svm->vmcb->control.exit_info_1 = fault->error_code;
1689 svm->vmcb->control.exit_info_2 = fault->address;
5bd2edc3
JR		 1690
1691 nested_svm_vmexit(svm);
1692}
1693
4b16184c
JR		 1694static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1695{
1696 int r;
1697
1698 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1699
1700 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1701 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1702 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1703 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1704 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1705
1706 return r;
1707}
1708
1709static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1710{
1711 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1712}
1713
c0725420
AG		 1714static int nested_svm_check_permissions(struct vcpu_svm *svm)
1715{
f6801dff 1716 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1717 || !is_paging(&svm->vcpu)) {
1718 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1719 return 1;
1720 }
1721
1722 if (svm->vmcb->save.cpl) {
1723 kvm_inject_gp(&svm->vcpu, 0);
1724 return 1;
1725 }
1726
1727 return 0;
1728}
1729
cf74a78b
AG		 1730static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1731 bool has_error_code, u32 error_code)
1732{
b8e88bc8
JR		 1733 int vmexit;
1734
2030753d 1735 if (!is_guest_mode(&svm->vcpu))
0295ad7d 1736 return 0;
cf74a78b 1737
0295ad7d
JR		 1738 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1739 svm->vmcb->control.exit_code_hi = 0;
1740 svm->vmcb->control.exit_info_1 = error_code;
1741 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1742
b8e88bc8
JR		 1743 vmexit = nested_svm_intercept(svm);
1744 if (vmexit == NESTED_EXIT_DONE)
1745 svm->nested.exit_required = true;
1746
1747 return vmexit;
cf74a78b
AG		 1748}
1749
8fe54654
JR		 1750/* This function returns true if it is save to enable the irq window */
1751static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1752{
2030753d 1753 if (!is_guest_mode(&svm->vcpu))
8fe54654 1754 return true;
cf74a78b 1755
26666957 1756 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1757 return true;
cf74a78b 1758
26666957 1759 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1760 return false;
cf74a78b 1761
a0a07cd2
GN		 1762 /*
1763 * if vmexit was already requested (by intercepted exception
1764 * for instance) do not overwrite it with "external interrupt"
1765 * vmexit.
1766 */
1767 if (svm->nested.exit_required)
1768 return false;
1769
197717d5
JR		 1770 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1771 svm->vmcb->control.exit_info_1 = 0;
1772 svm->vmcb->control.exit_info_2 = 0;
26666957 1773
cd3ff653
JR		 1774 if (svm->nested.intercept & 1ULL) {
1775 /*
1776 * The #vmexit can't be emulated here directly because this
1777 * code path runs with irqs and preemtion disabled. A
1778 * #vmexit emulation might sleep. Only signal request for
1779 * the #vmexit here.
1780 */
1781 svm->nested.exit_required = true;
236649de 1782 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1783 return false;
cf74a78b
AG		 1784 }
1785
8fe54654 1786 return true;
cf74a78b
AG		 1787}
1788
887f500c
JR		 1789/* This function returns true if it is save to enable the nmi window */
1790static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1791{
2030753d 1792 if (!is_guest_mode(&svm->vcpu))
887f500c
JR		 1793 return true;
1794
1795 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1796 return true;
1797
1798 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1799 svm->nested.exit_required = true;
1800
1801 return false;
cf74a78b
AG		 1802}
1803
7597f129 1804static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1805{
1806 struct page *page;
1807
6c3bd3d7
JR		 1808 might_sleep();
1809
34f80cfa 1810 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1811 if (is_error_page(page))
1812 goto error;
1813
7597f129
JR		 1814 *_page = page;
1815
1816 return kmap(page);
34f80cfa
JR		 1817
1818error:
1819 kvm_release_page_clean(page);
1820 kvm_inject_gp(&svm->vcpu, 0);
1821
1822 return NULL;
1823}
1824
7597f129 1825static void nested_svm_unmap(struct page *page)
34f80cfa 1826{
7597f129 1827 kunmap(page);
34f80cfa
JR		 1828 kvm_release_page_dirty(page);
1829}
34f80cfa 1830
ce2ac085
JR		 1831static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1832{
1833 unsigned port;
1834 u8 val, bit;
1835 u64 gpa;
34f80cfa 1836
ce2ac085
JR		 1837 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1838 return NESTED_EXIT_HOST;
34f80cfa 1839
ce2ac085
JR		 1840 port = svm->vmcb->control.exit_info_1 >> 16;
1841 gpa = svm->nested.vmcb_iopm + (port / 8);
1842 bit = port % 8;
1843 val = 0;
1844
1845 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1846 val &= (1 << bit);
1847
1848 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1849}
1850
d2477826 1851static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1852{
0d6b3537
JR		 1853 u32 offset, msr, value;
1854 int write, mask;
4c2161ae 1855
3d62d9aa 1856 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1857 return NESTED_EXIT_HOST;
3d62d9aa 1858
0d6b3537
JR		 1859 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1860 offset = svm_msrpm_offset(msr);
1861 write = svm->vmcb->control.exit_info_1 & 1;
1862 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1863
0d6b3537
JR		 1864 if (offset == MSR_INVALID)
1865 return NESTED_EXIT_DONE;
4c2161ae 1866
0d6b3537
JR		 1867 /* Offset is in 32 bit units but need in 8 bit units */
1868 offset *= 4;
4c2161ae 1869
0d6b3537
JR		 1870 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1871 return NESTED_EXIT_DONE;
3d62d9aa 1872
0d6b3537 1873 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1874}
1875
410e4d57 1876static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1877{
cf74a78b 1878 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1879
410e4d57
JR		 1880 switch (exit_code) {
1881 case SVM_EXIT_INTR:
1882 case SVM_EXIT_NMI:
ff47a49b 1883 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1884 return NESTED_EXIT_HOST;
410e4d57 1885 case SVM_EXIT_NPF:
e0231715 1886 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1887 if (npt_enabled)
1888 return NESTED_EXIT_HOST;
1889 break;
410e4d57 1890 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
631bc487
GN		 1891 /* When we're shadowing, trap PFs, but not async PF */
1892 if (!npt_enabled && svm->apf_reason == 0)
410e4d57
JR		 1893 return NESTED_EXIT_HOST;
1894 break;
66a562f7
JR		 1895 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1896 nm_interception(svm);
1897 break;
410e4d57
JR		 1898 default:
1899 break;
cf74a78b
AG		 1900 }
1901
410e4d57
JR		 1902 return NESTED_EXIT_CONTINUE;
1903}
1904
1905/*
1906 * If this function returns true, this #vmexit was already handled
1907 */
b8e88bc8 1908static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1909{
1910 u32 exit_code = svm->vmcb->control.exit_code;
1911 int vmexit = NESTED_EXIT_HOST;
1912
cf74a78b 1913 switch (exit_code) {
9c4e40b9 1914 case SVM_EXIT_MSR:
3d62d9aa 1915 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1916 break;
ce2ac085
JR		 1917 case SVM_EXIT_IOIO:
1918 vmexit = nested_svm_intercept_ioio(svm);
1919 break;
4ee546b4
RJ		 1920 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
1921 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
1922 if (svm->nested.intercept_cr & bit)
410e4d57 1923 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1924 break;
1925 }
1926 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1927 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1928 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1929 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1930 break;
1931 }
1932 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1933 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1934 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1935 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1936 break;
1937 }
1938 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1939 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1940 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1941 vmexit = NESTED_EXIT_DONE;
631bc487
GN		 1942 /* async page fault always cause vmexit */
1943 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
1944 svm->apf_reason != 0)
1945 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1946 break;
1947 }
228070b1
JR		 1948 case SVM_EXIT_ERR: {
1949 vmexit = NESTED_EXIT_DONE;
1950 break;
1951 }
cf74a78b
AG		 1952 default: {
1953 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1954 if (svm->nested.intercept & exit_bits)
410e4d57 1955 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1956 }
1957 }
1958
b8e88bc8
JR		 1959 return vmexit;
1960}
1961
1962static int nested_svm_exit_handled(struct vcpu_svm *svm)
1963{
1964 int vmexit;
1965
1966 vmexit = nested_svm_intercept(svm);
1967
1968 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1969 nested_svm_vmexit(svm);
9c4e40b9
JR		 1970
1971 return vmexit;
cf74a78b
AG		 1972}
1973
0460a979
JR		 1974static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1975{
1976 struct vmcb_control_area *dst = &dst_vmcb->control;
1977 struct vmcb_control_area *from = &from_vmcb->control;
1978
4ee546b4 1979 dst->intercept_cr = from->intercept_cr;
0460a979
JR		 1980 dst->intercept_dr_read = from->intercept_dr_read;
1981 dst->intercept_dr_write = from->intercept_dr_write;
1982 dst->intercept_exceptions = from->intercept_exceptions;
1983 dst->intercept = from->intercept;
1984 dst->iopm_base_pa = from->iopm_base_pa;
1985 dst->msrpm_base_pa = from->msrpm_base_pa;
1986 dst->tsc_offset = from->tsc_offset;
1987 dst->asid = from->asid;
1988 dst->tlb_ctl = from->tlb_ctl;
1989 dst->int_ctl = from->int_ctl;
1990 dst->int_vector = from->int_vector;
1991 dst->int_state = from->int_state;
1992 dst->exit_code = from->exit_code;
1993 dst->exit_code_hi = from->exit_code_hi;
1994 dst->exit_info_1 = from->exit_info_1;
1995 dst->exit_info_2 = from->exit_info_2;
1996 dst->exit_int_info = from->exit_int_info;
1997 dst->exit_int_info_err = from->exit_int_info_err;
1998 dst->nested_ctl = from->nested_ctl;
1999 dst->event_inj = from->event_inj;
2000 dst->event_inj_err = from->event_inj_err;
2001 dst->nested_cr3 = from->nested_cr3;
2002 dst->lbr_ctl = from->lbr_ctl;
2003}
2004
34f80cfa 2005static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 2006{
34f80cfa 2007 struct vmcb *nested_vmcb;
e6aa9abd 2008 struct vmcb *hsave = svm->nested.hsave;
33740e40 2009 struct vmcb *vmcb = svm->vmcb;
7597f129 2010 struct page *page;
cf74a78b 2011
17897f36
JR		 2012 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2013 vmcb->control.exit_info_1,
2014 vmcb->control.exit_info_2,
2015 vmcb->control.exit_int_info,
2016 vmcb->control.exit_int_info_err);
2017
7597f129 2018 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 2019 if (!nested_vmcb)
2020 return 1;
2021
2030753d
JR		 2022 /* Exit Guest-Mode */
2023 leave_guest_mode(&svm->vcpu);
06fc7772
JR		 2024 svm->nested.vmcb = 0;
2025
cf74a78b 2026 /* Give the current vmcb to the guest */
33740e40
JR		 2027 disable_gif(svm);
2028
2029 nested_vmcb->save.es = vmcb->save.es;
2030 nested_vmcb->save.cs = vmcb->save.cs;
2031 nested_vmcb->save.ss = vmcb->save.ss;
2032 nested_vmcb->save.ds = vmcb->save.ds;
2033 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2034 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 2035 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 2036 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 2037 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 2038 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 2039 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 2040 nested_vmcb->save.rflags = vmcb->save.rflags;
2041 nested_vmcb->save.rip = vmcb->save.rip;
2042 nested_vmcb->save.rsp = vmcb->save.rsp;
2043 nested_vmcb->save.rax = vmcb->save.rax;
2044 nested_vmcb->save.dr7 = vmcb->save.dr7;
2045 nested_vmcb->save.dr6 = vmcb->save.dr6;
2046 nested_vmcb->save.cpl = vmcb->save.cpl;
2047
2048 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2049 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2050 nested_vmcb->control.int_state = vmcb->control.int_state;
2051 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2052 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2053 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2054 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2055 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2056 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 2057 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 2058
2059 /*
2060 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2061 * to make sure that we do not lose injected events. So check event_inj
2062 * here and copy it to exit_int_info if it is valid.
2063 * Exit_int_info and event_inj can't be both valid because the case
2064 * below only happens on a VMRUN instruction intercept which has
2065 * no valid exit_int_info set.
2066 */
2067 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2068 struct vmcb_control_area *nc = &nested_vmcb->control;
2069
2070 nc->exit_int_info = vmcb->control.event_inj;
2071 nc->exit_int_info_err = vmcb->control.event_inj_err;
2072 }
2073
33740e40
JR		 2074 nested_vmcb->control.tlb_ctl = 0;
2075 nested_vmcb->control.event_inj = 0;
2076 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 2077
2078 /* We always set V_INTR_MASKING and remember the old value in hflags */
2079 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2080 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2081
cf74a78b 2082 /* Restore the original control entries */
0460a979 2083 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 2084
219b65dc
AG		 2085 kvm_clear_exception_queue(&svm->vcpu);
2086 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b 2087
4b16184c
JR		 2088 svm->nested.nested_cr3 = 0;
2089
cf74a78b
AG		 2090 /* Restore selected save entries */
2091 svm->vmcb->save.es = hsave->save.es;
2092 svm->vmcb->save.cs = hsave->save.cs;
2093 svm->vmcb->save.ss = hsave->save.ss;
2094 svm->vmcb->save.ds = hsave->save.ds;
2095 svm->vmcb->save.gdtr = hsave->save.gdtr;
2096 svm->vmcb->save.idtr = hsave->save.idtr;
2097 svm->vmcb->save.rflags = hsave->save.rflags;
2098 svm_set_efer(&svm->vcpu, hsave->save.efer);
2099 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2100 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2101 if (npt_enabled) {
2102 svm->vmcb->save.cr3 = hsave->save.cr3;
2103 svm->vcpu.arch.cr3 = hsave->save.cr3;
2104 } else {
2390218b 2105 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 2106 }
2107 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2108 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2109 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2110 svm->vmcb->save.dr7 = 0;
2111 svm->vmcb->save.cpl = 0;
2112 svm->vmcb->control.exit_int_info = 0;
2113
7597f129 2114 nested_svm_unmap(page);
cf74a78b 2115
4b16184c 2116 nested_svm_uninit_mmu_context(&svm->vcpu);
cf74a78b
AG		 2117 kvm_mmu_reset_context(&svm->vcpu);
2118 kvm_mmu_load(&svm->vcpu);
2119
2120 return 0;
2121}
3d6368ef 2122
9738b2c9 2123static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 2124{
323c3d80
JR		 2125 /*
2126 * This function merges the msr permission bitmaps of kvm and the
2127 * nested vmcb. It is omptimized in that it only merges the parts where
2128 * the kvm msr permission bitmap may contain zero bits
2129 */
3d6368ef 2130 int i;
9738b2c9 2131
323c3d80
JR		 2132 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2133 return true;
9738b2c9 2134
323c3d80
JR		 2135 for (i = 0; i < MSRPM_OFFSETS; i++) {
2136 u32 value, p;
2137 u64 offset;
9738b2c9 2138
323c3d80
JR		 2139 if (msrpm_offsets[i] == 0xffffffff)
2140 break;
3d6368ef 2141
0d6b3537
JR		 2142 p = msrpm_offsets[i];
2143 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2144
2145 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2146 return false;
2147
2148 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2149 }
3d6368ef 2150
323c3d80 2151 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2152
2153 return true;
3d6368ef
AG		 2154}
2155
52c65a30
JR		 2156static bool nested_vmcb_checks(struct vmcb *vmcb)
2157{
2158 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2159 return false;
2160
dbe77584
JR		 2161 if (vmcb->control.asid == 0)
2162 return false;
2163
4b16184c
JR		 2164 if (vmcb->control.nested_ctl && !npt_enabled)
2165 return false;
2166
52c65a30
JR		 2167 return true;
2168}
2169
9738b2c9 2170static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2171{
9738b2c9 2172 struct vmcb *nested_vmcb;
e6aa9abd 2173 struct vmcb *hsave = svm->nested.hsave;
defbba56 2174 struct vmcb *vmcb = svm->vmcb;
7597f129 2175 struct page *page;
06fc7772 2176 u64 vmcb_gpa;
3d6368ef 2177
06fc7772 2178 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2179
7597f129 2180 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2181 if (!nested_vmcb)
2182 return false;
2183
52c65a30
JR		 2184 if (!nested_vmcb_checks(nested_vmcb)) {
2185 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2186 nested_vmcb->control.exit_code_hi = 0;
2187 nested_vmcb->control.exit_info_1 = 0;
2188 nested_vmcb->control.exit_info_2 = 0;
2189
2190 nested_svm_unmap(page);
2191
2192 return false;
2193 }
2194
b75f4eb3 2195 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
0ac406de
JR		 2196 nested_vmcb->save.rip,
2197 nested_vmcb->control.int_ctl,
2198 nested_vmcb->control.event_inj,
2199 nested_vmcb->control.nested_ctl);
2200
4ee546b4
RJ		 2201 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2202 nested_vmcb->control.intercept_cr >> 16,
2e554e8d
JR		 2203 nested_vmcb->control.intercept_exceptions,
2204 nested_vmcb->control.intercept);
2205
3d6368ef 2206 /* Clear internal status */
219b65dc
AG		 2207 kvm_clear_exception_queue(&svm->vcpu);
2208 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2209
e0231715
JR		 2210 /*
2211 * Save the old vmcb, so we don't need to pick what we save, but can
2212 * restore everything when a VMEXIT occurs
2213 */
defbba56
JR		 2214 hsave->save.es = vmcb->save.es;
2215 hsave->save.cs = vmcb->save.cs;
2216 hsave->save.ss = vmcb->save.ss;
2217 hsave->save.ds = vmcb->save.ds;
2218 hsave->save.gdtr = vmcb->save.gdtr;
2219 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2220 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2221 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2222 hsave->save.cr4 = svm->vcpu.arch.cr4;
2223 hsave->save.rflags = vmcb->save.rflags;
b75f4eb3 2224 hsave->save.rip = kvm_rip_read(&svm->vcpu);
defbba56
JR		 2225 hsave->save.rsp = vmcb->save.rsp;
2226 hsave->save.rax = vmcb->save.rax;
2227 if (npt_enabled)
2228 hsave->save.cr3 = vmcb->save.cr3;
2229 else
2230 hsave->save.cr3 = svm->vcpu.arch.cr3;
2231
0460a979 2232 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2233
2234 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2235 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2236 else
2237 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2238
4b16184c
JR		 2239 if (nested_vmcb->control.nested_ctl) {
2240 kvm_mmu_unload(&svm->vcpu);
2241 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2242 nested_svm_init_mmu_context(&svm->vcpu);
2243 }
2244
3d6368ef
AG		 2245 /* Load the nested guest state */
2246 svm->vmcb->save.es = nested_vmcb->save.es;
2247 svm->vmcb->save.cs = nested_vmcb->save.cs;
2248 svm->vmcb->save.ss = nested_vmcb->save.ss;
2249 svm->vmcb->save.ds = nested_vmcb->save.ds;
2250 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2251 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2252 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2253 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2254 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2255 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2256 if (npt_enabled) {
2257 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2258 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2259 } else
2390218b 2260 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2261
2262 /* Guest paging mode is active - reset mmu */
2263 kvm_mmu_reset_context(&svm->vcpu);
2264
defbba56 2265 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2266 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2267 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2268 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2269
3d6368ef
AG		 2270 /* In case we don't even reach vcpu_run, the fields are not updated */
2271 svm->vmcb->save.rax = nested_vmcb->save.rax;
2272 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2273 svm->vmcb->save.rip = nested_vmcb->save.rip;
2274 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2275 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2276 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2277
f7138538 2278 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2279 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2280
aad42c64 2281 /* cache intercepts */
4ee546b4 2282 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
aad42c64
JR		 2283 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2284 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2285 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2286 svm->nested.intercept = nested_vmcb->control.intercept;
2287
3d6368ef 2288 force_new_asid(&svm->vcpu);
3d6368ef 2289 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2290 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2291 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2292 else
2293 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2294
88ab24ad
JR		 2295 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2296 /* We only want the cr8 intercept bits of the guest */
4ee546b4
RJ		 2297 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2298 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
88ab24ad
JR		 2299 }
2300
0d945bd9
JR		 2301 /* We don't want to see VMMCALLs from a nested guest */
2302 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2303
88ab24ad 2304 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2305 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2306 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2307 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2308 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2309 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2310
7597f129 2311 nested_svm_unmap(page);
9738b2c9 2312
2030753d
JR		 2313 /* Enter Guest-Mode */
2314 enter_guest_mode(&svm->vcpu);
2315
384c6368
JR		 2316 /*
2317 * Merge guest and host intercepts - must be called with vcpu in
2318 * guest-mode to take affect here
2319 */
2320 recalc_intercepts(svm);
2321
06fc7772 2322 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2323
2af9194d 2324 enable_gif(svm);
3d6368ef 2325
9738b2c9 2326 return true;
3d6368ef
AG		 2327}
2328
9966bf68 2329static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2330{
2331 to_vmcb->save.fs = from_vmcb->save.fs;
2332 to_vmcb->save.gs = from_vmcb->save.gs;
2333 to_vmcb->save.tr = from_vmcb->save.tr;
2334 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2335 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2336 to_vmcb->save.star = from_vmcb->save.star;
2337 to_vmcb->save.lstar = from_vmcb->save.lstar;
2338 to_vmcb->save.cstar = from_vmcb->save.cstar;
2339 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2340 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2341 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2342 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2343}
2344
851ba692 2345static int vmload_interception(struct vcpu_svm *svm)
5542675b 2346{
9966bf68 2347 struct vmcb *nested_vmcb;
7597f129 2348 struct page *page;
9966bf68 2349
5542675b
AG		 2350 if (nested_svm_check_permissions(svm))
2351 return 1;
2352
2353 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2354 skip_emulated_instruction(&svm->vcpu);
2355
7597f129 2356 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2357 if (!nested_vmcb)
2358 return 1;
2359
2360 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2361 nested_svm_unmap(page);
5542675b
AG		 2362
2363 return 1;
2364}
2365
851ba692 2366static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2367{
9966bf68 2368 struct vmcb *nested_vmcb;
7597f129 2369 struct page *page;
9966bf68 2370
5542675b
AG		 2371 if (nested_svm_check_permissions(svm))
2372 return 1;
2373
2374 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2375 skip_emulated_instruction(&svm->vcpu);
2376
7597f129 2377 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2378 if (!nested_vmcb)
2379 return 1;
2380
2381 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2382 nested_svm_unmap(page);
5542675b
AG		 2383
2384 return 1;
2385}
2386
851ba692 2387static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2388{
3d6368ef
AG		 2389 if (nested_svm_check_permissions(svm))
2390 return 1;
2391
b75f4eb3
RJ		 2392 /* Save rip after vmrun instruction */
2393 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3d6368ef 2394
9738b2c9 2395 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2396 return 1;
2397
9738b2c9 2398 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2399 goto failed;
2400
2401 return 1;
2402
2403failed:
2404
2405 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2406 svm->vmcb->control.exit_code_hi = 0;
2407 svm->vmcb->control.exit_info_1 = 0;
2408 svm->vmcb->control.exit_info_2 = 0;
2409
2410 nested_svm_vmexit(svm);
3d6368ef
AG		 2411
2412 return 1;
2413}
2414
851ba692 2415static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2416{
2417 if (nested_svm_check_permissions(svm))
2418 return 1;
2419
2420 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2421 skip_emulated_instruction(&svm->vcpu);
3842d135 2422 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
1371d904 2423
2af9194d 2424 enable_gif(svm);
1371d904
AG		 2425
2426 return 1;
2427}
2428
851ba692 2429static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2430{
2431 if (nested_svm_check_permissions(svm))
2432 return 1;
2433
2434 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2435 skip_emulated_instruction(&svm->vcpu);
2436
2af9194d 2437 disable_gif(svm);
1371d904
AG		 2438
2439 /* After a CLGI no interrupts should come */
2440 svm_clear_vintr(svm);
2441 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2442
2443 return 1;
2444}
2445
851ba692 2446static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2447{
2448 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2449
ec1ff790
JR		 2450 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2451 vcpu->arch.regs[VCPU_REGS_RAX]);
2452
ff092385
AG		 2453 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2454 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2455
2456 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2457 skip_emulated_instruction(&svm->vcpu);
2458 return 1;
2459}
2460
532a46b9
JR		 2461static int skinit_interception(struct vcpu_svm *svm)
2462{
2463 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2464
2465 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2466 return 1;
2467}
2468
851ba692 2469static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2470{
7ee5d940 2471 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2472 return 1;
2473}
2474
851ba692 2475static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2476{
37817f29 2477 u16 tss_selector;
64a7ec06
GN		 2478 int reason;
2479 int int_type = svm->vmcb->control.exit_int_info &
2480 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2481 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2482 uint32_t type =
2483 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2484 uint32_t idt_v =
2485 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2486 bool has_error_code = false;
2487 u32 error_code = 0;
37817f29
IE		 2488
2489 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2490
37817f29
IE		 2491 if (svm->vmcb->control.exit_info_2 &
2492 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2493 reason = TASK_SWITCH_IRET;
2494 else if (svm->vmcb->control.exit_info_2 &
2495 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2496 reason = TASK_SWITCH_JMP;
fe8e7f83 2497 else if (idt_v)
64a7ec06
GN		 2498 reason = TASK_SWITCH_GATE;
2499 else
2500 reason = TASK_SWITCH_CALL;
2501
fe8e7f83
GN		 2502 if (reason == TASK_SWITCH_GATE) {
2503 switch (type) {
2504 case SVM_EXITINTINFO_TYPE_NMI:
2505 svm->vcpu.arch.nmi_injected = false;
2506 break;
2507 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2508 if (svm->vmcb->control.exit_info_2 &
2509 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2510 has_error_code = true;
2511 error_code =
2512 (u32)svm->vmcb->control.exit_info_2;
2513 }
fe8e7f83
GN		 2514 kvm_clear_exception_queue(&svm->vcpu);
2515 break;
2516 case SVM_EXITINTINFO_TYPE_INTR:
2517 kvm_clear_interrupt_queue(&svm->vcpu);
2518 break;
2519 default:
2520 break;
2521 }
2522 }
64a7ec06 2523
8317c298
GN		 2524 if (reason != TASK_SWITCH_GATE ||
2525 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2526 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2527 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2528 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2529
acb54517
GN		 2530 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2531 has_error_code, error_code) == EMULATE_FAIL) {
2532 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2533 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2534 svm->vcpu.run->internal.ndata = 0;
2535 return 0;
2536 }
2537 return 1;
6aa8b732
AK		 2538}
2539
851ba692 2540static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2541{
5fdbf976 2542 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2543 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2544 return 1;
6aa8b732
AK		 2545}
2546
851ba692 2547static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2548{
2549 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2550 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2551 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2552 return 1;
2553}
2554
851ba692 2555static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2556{
6d77dbfc 2557 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2558}
2559
851ba692 2560static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2561{
6d77dbfc 2562 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2563}
2564
cda00082
JR		 2565static int cr0_write_interception(struct vcpu_svm *svm)
2566{
2567 struct kvm_vcpu *vcpu = &svm->vcpu;
2568 int r;
2569
2570 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2571
2572 if (svm->nested.vmexit_rip) {
2573 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2574 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2575 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2576 svm->nested.vmexit_rip = 0;
2577 }
2578
2579 return r == EMULATE_DONE;
2580}
2581
851ba692 2582static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2583{
851ba692
AK		 2584 struct kvm_run *kvm_run = svm->vcpu.run;
2585
0a5fff19
GN		 2586 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2587 /* instruction emulation calls kvm_set_cr8() */
851ba692 2588 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273 2589 if (irqchip_in_kernel(svm->vcpu.kvm)) {
4ee546b4 2590 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1d075434 2591 return 1;
95ba8273 2592 }
0a5fff19
GN		 2593 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2594 return 1;
1d075434
JR		 2595 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2596 return 0;
2597}
2598
6aa8b732
AK		 2599static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2600{
a2fa3e9f
GH		 2601 struct vcpu_svm *svm = to_svm(vcpu);
2602
6aa8b732 2603 switch (ecx) {
af24a4e4 2604 case MSR_IA32_TSC: {
20824f30 2605 u64 tsc_offset;
6aa8b732 2606
2030753d 2607 if (is_guest_mode(vcpu))
20824f30
JR		 2608 tsc_offset = svm->nested.hsave->control.tsc_offset;
2609 else
2610 tsc_offset = svm->vmcb->control.tsc_offset;
2611
2612 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2613 break;
2614 }
8c06585d 2615 case MSR_STAR:
a2fa3e9f 2616 *data = svm->vmcb->save.star;
6aa8b732 2617 break;
0e859cac 2618#ifdef CONFIG_X86_64
6aa8b732 2619 case MSR_LSTAR:
a2fa3e9f 2620 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2621 break;
2622 case MSR_CSTAR:
a2fa3e9f 2623 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2624 break;
2625 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2626 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2627 break;
2628 case MSR_SYSCALL_MASK:
a2fa3e9f 2629 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2630 break;
2631#endif
2632 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2633 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2634 break;
2635 case MSR_IA32_SYSENTER_EIP:
017cb99e 2636 *data = svm->sysenter_eip;
6aa8b732
AK		 2637 break;
2638 case MSR_IA32_SYSENTER_ESP:
017cb99e 2639 *data = svm->sysenter_esp;
6aa8b732 2640 break;
e0231715
JR		 2641 /*
2642 * Nobody will change the following 5 values in the VMCB so we can
2643 * safely return them on rdmsr. They will always be 0 until LBRV is
2644 * implemented.
2645 */
a2938c80
JR		 2646 case MSR_IA32_DEBUGCTLMSR:
2647 *data = svm->vmcb->save.dbgctl;
2648 break;
2649 case MSR_IA32_LASTBRANCHFROMIP:
2650 *data = svm->vmcb->save.br_from;
2651 break;
2652 case MSR_IA32_LASTBRANCHTOIP:
2653 *data = svm->vmcb->save.br_to;
2654 break;
2655 case MSR_IA32_LASTINTFROMIP:
2656 *data = svm->vmcb->save.last_excp_from;
2657 break;
2658 case MSR_IA32_LASTINTTOIP:
2659 *data = svm->vmcb->save.last_excp_to;
2660 break;
b286d5d8 2661 case MSR_VM_HSAVE_PA:
e6aa9abd 2662 *data = svm->nested.hsave_msr;
b286d5d8 2663 break;
eb6f302e 2664 case MSR_VM_CR:
4a810181 2665 *data = svm->nested.vm_cr_msr;
eb6f302e 2666 break;
c8a73f18
AG		 2667 case MSR_IA32_UCODE_REV:
2668 *data = 0x01000065;
2669 break;
6aa8b732 2670 default:
3bab1f5d 2671 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2672 }
2673 return 0;
2674}
2675
851ba692 2676static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2677{
ad312c7c 2678 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2679 u64 data;
2680
59200273
AK		 2681 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2682 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2683 kvm_inject_gp(&svm->vcpu, 0);
59200273 2684 } else {
229456fc 2685 trace_kvm_msr_read(ecx, data);
af9ca2d7 2686
5fdbf976 2687 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2688 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2689 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2690 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2691 }
2692 return 1;
2693}
2694
4a810181
JR		 2695static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2696{
2697 struct vcpu_svm *svm = to_svm(vcpu);
2698 int svm_dis, chg_mask;
2699
2700 if (data & ~SVM_VM_CR_VALID_MASK)
2701 return 1;
2702
2703 chg_mask = SVM_VM_CR_VALID_MASK;
2704
2705 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2706 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2707
2708 svm->nested.vm_cr_msr &= ~chg_mask;
2709 svm->nested.vm_cr_msr |= (data & chg_mask);
2710
2711 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2712
2713 /* check for svm_disable while efer.svme is set */
2714 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2715 return 1;
2716
2717 return 0;
2718}
2719
6aa8b732
AK		 2720static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2721{
a2fa3e9f
GH		 2722 struct vcpu_svm *svm = to_svm(vcpu);
2723
6aa8b732 2724 switch (ecx) {
f4e1b3c8 2725 case MSR_IA32_TSC:
99e3e30a 2726 kvm_write_tsc(vcpu, data);
6aa8b732 2727 break;
8c06585d 2728 case MSR_STAR:
a2fa3e9f 2729 svm->vmcb->save.star = data;
6aa8b732 2730 break;
49b14f24 2731#ifdef CONFIG_X86_64
6aa8b732 2732 case MSR_LSTAR:
a2fa3e9f 2733 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2734 break;
2735 case MSR_CSTAR:
a2fa3e9f 2736 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2737 break;
2738 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2739 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2740 break;
2741 case MSR_SYSCALL_MASK:
a2fa3e9f 2742 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2743 break;
2744#endif
2745 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2746 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2747 break;
2748 case MSR_IA32_SYSENTER_EIP:
017cb99e 2749 svm->sysenter_eip = data;
a2fa3e9f 2750 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2751 break;
2752 case MSR_IA32_SYSENTER_ESP:
017cb99e 2753 svm->sysenter_esp = data;
a2fa3e9f 2754 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2755 break;
a2938c80 2756 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 2757 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
24e09cbf 2758 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2759 __func__, data);
24e09cbf
JR		 2760 break;
2761 }
2762 if (data & DEBUGCTL_RESERVED_BITS)
2763 return 1;
2764
2765 svm->vmcb->save.dbgctl = data;
2766 if (data & (1ULL<<0))
2767 svm_enable_lbrv(svm);
2768 else
2769 svm_disable_lbrv(svm);
a2938c80 2770 break;
b286d5d8 2771 case MSR_VM_HSAVE_PA:
e6aa9abd 2772 svm->nested.hsave_msr = data;
62b9abaa 2773 break;
3c5d0a44 2774 case MSR_VM_CR:
4a810181 2775 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2776 case MSR_VM_IGNNE:
3c5d0a44
AG		 2777 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2778 break;
6aa8b732 2779 default:
3bab1f5d 2780 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2781 }
2782 return 0;
2783}
2784
851ba692 2785static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2786{
ad312c7c 2787 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2788 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2789 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2790
af9ca2d7 2791
5fdbf976 2792 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2793 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2794 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2795 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2796 } else {
2797 trace_kvm_msr_write(ecx, data);
e756fc62 2798 skip_emulated_instruction(&svm->vcpu);
59200273 2799 }
6aa8b732
AK		 2800 return 1;
2801}
2802
851ba692 2803static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2804{
e756fc62 2805 if (svm->vmcb->control.exit_info_1)
851ba692 2806 return wrmsr_interception(svm);
6aa8b732 2807 else
851ba692 2808 return rdmsr_interception(svm);
6aa8b732
AK		 2809}
2810
851ba692 2811static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2812{
851ba692
AK		 2813 struct kvm_run *kvm_run = svm->vcpu.run;
2814
3842d135 2815 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2816 svm_clear_vintr(svm);
85f455f7 2817 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2818 /*
2819 * If the user space waits to inject interrupts, exit as soon as
2820 * possible
2821 */
8061823a
GN		 2822 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2823 kvm_run->request_interrupt_window &&
2824 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2825 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2826 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2827 return 0;
2828 }
2829
2830 return 1;
2831}
2832
565d0998
ML		 2833static int pause_interception(struct vcpu_svm *svm)
2834{
2835 kvm_vcpu_on_spin(&(svm->vcpu));
2836 return 1;
2837}
2838
851ba692 2839static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2840 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2841 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2842 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2843 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2844 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
cda00082 2845 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
e0231715
JR		 2846 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2847 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2848 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2849 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2850 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2851 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2852 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2853 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2854 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2855 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2856 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2857 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2858 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2859 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2860 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2861 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2862 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2863 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2864 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2865 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2866 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2867 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2868 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2869 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2870 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2871 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2872 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2873 [SVM_EXIT_SMI] = nop_on_interception,
2874 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2875 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2876 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2877 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2878 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2879 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2880 [SVM_EXIT_HLT] = halt_interception,
a7052897 2881 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2882 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2883 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2884 [SVM_EXIT_MSR] = msr_interception,
2885 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2886 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2887 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2888 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2889 [SVM_EXIT_VMLOAD] = vmload_interception,
2890 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2891 [SVM_EXIT_STGI] = stgi_interception,
2892 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2893 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2894 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2895 [SVM_EXIT_MONITOR] = invalid_op_interception,
2896 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2897 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2898};
2899
3f10c846
JR		 2900void dump_vmcb(struct kvm_vcpu *vcpu)
2901{
2902 struct vcpu_svm *svm = to_svm(vcpu);
2903 struct vmcb_control_area *control = &svm->vmcb->control;
2904 struct vmcb_save_area *save = &svm->vmcb->save;
2905
2906 pr_err("VMCB Control Area:\n");
4ee546b4
RJ		 2907 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2908 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
3f10c846
JR		 2909 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2910 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2911 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2912 pr_err("intercepts: %016llx\n", control->intercept);
2913 pr_err("pause filter count: %d\n", control->pause_filter_count);
2914 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2915 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2916 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2917 pr_err("asid: %d\n", control->asid);
2918 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2919 pr_err("int_ctl: %08x\n", control->int_ctl);
2920 pr_err("int_vector: %08x\n", control->int_vector);
2921 pr_err("int_state: %08x\n", control->int_state);
2922 pr_err("exit_code: %08x\n", control->exit_code);
2923 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2924 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2925 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2926 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2927 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2928 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2929 pr_err("event_inj: %08x\n", control->event_inj);
2930 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2931 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2932 pr_err("next_rip: %016llx\n", control->next_rip);
2933 pr_err("VMCB State Save Area:\n");
2934 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2935 save->es.selector, save->es.attrib,
2936 save->es.limit, save->es.base);
2937 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2938 save->cs.selector, save->cs.attrib,
2939 save->cs.limit, save->cs.base);
2940 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2941 save->ss.selector, save->ss.attrib,
2942 save->ss.limit, save->ss.base);
2943 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2944 save->ds.selector, save->ds.attrib,
2945 save->ds.limit, save->ds.base);
2946 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2947 save->fs.selector, save->fs.attrib,
2948 save->fs.limit, save->fs.base);
2949 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2950 save->gs.selector, save->gs.attrib,
2951 save->gs.limit, save->gs.base);
2952 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2953 save->gdtr.selector, save->gdtr.attrib,
2954 save->gdtr.limit, save->gdtr.base);
2955 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2956 save->ldtr.selector, save->ldtr.attrib,
2957 save->ldtr.limit, save->ldtr.base);
2958 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2959 save->idtr.selector, save->idtr.attrib,
2960 save->idtr.limit, save->idtr.base);
2961 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2962 save->tr.selector, save->tr.attrib,
2963 save->tr.limit, save->tr.base);
2964 pr_err("cpl: %d efer: %016llx\n",
2965 save->cpl, save->efer);
2966 pr_err("cr0: %016llx cr2: %016llx\n",
2967 save->cr0, save->cr2);
2968 pr_err("cr3: %016llx cr4: %016llx\n",
2969 save->cr3, save->cr4);
2970 pr_err("dr6: %016llx dr7: %016llx\n",
2971 save->dr6, save->dr7);
2972 pr_err("rip: %016llx rflags: %016llx\n",
2973 save->rip, save->rflags);
2974 pr_err("rsp: %016llx rax: %016llx\n",
2975 save->rsp, save->rax);
2976 pr_err("star: %016llx lstar: %016llx\n",
2977 save->star, save->lstar);
2978 pr_err("cstar: %016llx sfmask: %016llx\n",
2979 save->cstar, save->sfmask);
2980 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2981 save->kernel_gs_base, save->sysenter_cs);
2982 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2983 save->sysenter_esp, save->sysenter_eip);
2984 pr_err("gpat: %016llx dbgctl: %016llx\n",
2985 save->g_pat, save->dbgctl);
2986 pr_err("br_from: %016llx br_to: %016llx\n",
2987 save->br_from, save->br_to);
2988 pr_err("excp_from: %016llx excp_to: %016llx\n",
2989 save->last_excp_from, save->last_excp_to);
2990
2991}
2992
586f9607
AK		 2993static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2994{
2995 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2996
2997 *info1 = control->exit_info_1;
2998 *info2 = control->exit_info_2;
2999}
3000
851ba692 3001static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3002{
04d2cc77 3003 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 3004 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 3005 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 3006
aa17911e 3007 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
af9ca2d7 3008
4ee546b4 3009 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2be4fc7a
JR		 3010 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3011 if (npt_enabled)
3012 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 3013
cd3ff653
JR		 3014 if (unlikely(svm->nested.exit_required)) {
3015 nested_svm_vmexit(svm);
3016 svm->nested.exit_required = false;
3017
3018 return 1;
3019 }
3020
2030753d 3021 if (is_guest_mode(vcpu)) {
410e4d57
JR		 3022 int vmexit;
3023
d8cabddf
JR		 3024 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3025 svm->vmcb->control.exit_info_1,
3026 svm->vmcb->control.exit_info_2,
3027 svm->vmcb->control.exit_int_info,
3028 svm->vmcb->control.exit_int_info_err);
3029
410e4d57
JR		 3030 vmexit = nested_svm_exit_special(svm);
3031
3032 if (vmexit == NESTED_EXIT_CONTINUE)
3033 vmexit = nested_svm_exit_handled(svm);
3034
3035 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 3036 return 1;
cf74a78b
AG		 3037 }
3038
a5c3832d
JR		 3039 svm_complete_interrupts(svm);
3040
04d2cc77
AK		 3041 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3042 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3043 kvm_run->fail_entry.hardware_entry_failure_reason
3044 = svm->vmcb->control.exit_code;
3f10c846
JR		 3045 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3046 dump_vmcb(vcpu);
04d2cc77
AK		 3047 return 0;
3048 }
3049
a2fa3e9f 3050 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 3051 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 3052 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3053 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6aa8b732
AK		 3054 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3055 "exit_code 0x%x\n",
b8688d51 3056 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 3057 exit_code);
3058
9d8f549d 3059 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 3060 || !svm_exit_handlers[exit_code]) {
6aa8b732 3061 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 3062 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 3063 return 0;
3064 }
3065
851ba692 3066 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3067}
3068
3069static void reload_tss(struct kvm_vcpu *vcpu)
3070{
3071 int cpu = raw_smp_processor_id();
3072
0fe1e009
TH		 3073 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3074 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3075 load_TR_desc();
3076}
3077
e756fc62 3078static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 3079{
3080 int cpu = raw_smp_processor_id();
3081
0fe1e009 3082 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 3083
a2fa3e9f 3084 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 3085 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3086 if (svm->asid_generation != sd->asid_generation)
3087 new_asid(svm, sd);
6aa8b732
AK		 3088}
3089
95ba8273
GN		 3090static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3091{
3092 struct vcpu_svm *svm = to_svm(vcpu);
3093
3094 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3095 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 3096 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 3097 ++vcpu->stat.nmi_injections;
3098}
6aa8b732 3099
85f455f7 3100static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 3101{
3102 struct vmcb_control_area *control;
3103
e756fc62 3104 control = &svm->vmcb->control;
85f455f7 3105 control->int_vector = irq;
6aa8b732
AK		 3106 control->int_ctl &= ~V_INTR_PRIO_MASK;
3107 control->int_ctl |= V_IRQ_MASK |
3108 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3109}
3110
66fd3f7f 3111static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3112{
3113 struct vcpu_svm *svm = to_svm(vcpu);
3114
2af9194d 3115 BUG_ON(!(gif_set(svm)));
cf74a78b 3116
9fb2d2b4
GN		 3117 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3118 ++vcpu->stat.irq_injections;
3119
219b65dc
AG		 3120 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3121 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3122}
3123
95ba8273 3124static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3125{
3126 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3127
2030753d 3128 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3129 return;
3130
95ba8273 3131 if (irr == -1)
aaacfc9a
JR		 3132 return;
3133
95ba8273 3134 if (tpr >= irr)
4ee546b4 3135 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
95ba8273 3136}
aaacfc9a 3137
95ba8273
GN		 3138static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3139{
3140 struct vcpu_svm *svm = to_svm(vcpu);
3141 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 3142 int ret;
3143 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3144 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3145 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3146
3147 return ret;
aaacfc9a
JR		 3148}
3149
3cfc3092
JK		 3150static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3151{
3152 struct vcpu_svm *svm = to_svm(vcpu);
3153
3154 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3155}
3156
3157static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3158{
3159 struct vcpu_svm *svm = to_svm(vcpu);
3160
3161 if (masked) {
3162 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 3163 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3164 } else {
3165 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 3166 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3167 }
3168}
3169
78646121
GN		 3170static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3171{
3172 struct vcpu_svm *svm = to_svm(vcpu);
3173 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3174 int ret;
3175
3176 if (!gif_set(svm) ||
3177 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3178 return 0;
3179
3180 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3181
2030753d 3182 if (is_guest_mode(vcpu))
7fcdb510
JR		 3183 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3184
3185 return ret;
78646121
GN		 3186}
3187
9222be18 3188static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3189{
219b65dc 3190 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3191
e0231715
JR		 3192 /*
3193 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3194 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3195 * get that intercept, this function will be called again though and
3196 * we'll get the vintr intercept.
3197 */
8fe54654 3198 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3199 svm_set_vintr(svm);
3200 svm_inject_irq(svm, 0x0);
3201 }
85f455f7
ED		 3202}
3203
95ba8273 3204static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3205{
04d2cc77 3206 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3207
44c11430
GN		 3208 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3209 == HF_NMI_MASK)
3210 return; /* IRET will cause a vm exit */
3211
e0231715
JR		 3212 /*
3213 * Something prevents NMI from been injected. Single step over possible
3214 * problem (IRET or exception injection or interrupt shadow)
3215 */
6be7d306 3216 svm->nmi_singlestep = true;
44c11430
GN		 3217 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3218 update_db_intercept(vcpu);
c1150d8c
DL		 3219}
3220
cbc94022
IE		 3221static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3222{
3223 return 0;
3224}
3225
d9e368d6
AK		 3226static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3227{
3228 force_new_asid(vcpu);
3229}
3230
04d2cc77
AK		 3231static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3232{
3233}
3234
d7bf8221
JR		 3235static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3236{
3237 struct vcpu_svm *svm = to_svm(vcpu);
3238
2030753d 3239 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3240 return;
3241
4ee546b4 3242 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
d7bf8221 3243 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3244 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3245 }
3246}
3247
649d6864
JR		 3248static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3249{
3250 struct vcpu_svm *svm = to_svm(vcpu);
3251 u64 cr8;
3252
2030753d 3253 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3254 return;
3255
649d6864
JR		 3256 cr8 = kvm_get_cr8(vcpu);
3257 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3258 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3259}
3260
9222be18
GN		 3261static void svm_complete_interrupts(struct vcpu_svm *svm)
3262{
3263 u8 vector;
3264 int type;
3265 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3266 unsigned int3_injected = svm->int3_injected;
3267
3268 svm->int3_injected = 0;
9222be18 3269
3842d135 3270 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
44c11430 3271 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3272 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3273 }
44c11430 3274
9222be18
GN		 3275 svm->vcpu.arch.nmi_injected = false;
3276 kvm_clear_exception_queue(&svm->vcpu);
3277 kvm_clear_interrupt_queue(&svm->vcpu);
3278
3279 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3280 return;
3281
3842d135
AK		 3282 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3283
9222be18
GN		 3284 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3285 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3286
3287 switch (type) {
3288 case SVM_EXITINTINFO_TYPE_NMI:
3289 svm->vcpu.arch.nmi_injected = true;
3290 break;
3291 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3292 /*
3293 * In case of software exceptions, do not reinject the vector,
3294 * but re-execute the instruction instead. Rewind RIP first
3295 * if we emulated INT3 before.
3296 */
3297 if (kvm_exception_is_soft(vector)) {
3298 if (vector == BP_VECTOR && int3_injected &&
3299 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3300 kvm_rip_write(&svm->vcpu,
3301 kvm_rip_read(&svm->vcpu) -
3302 int3_injected);
9222be18 3303 break;
66b7138f 3304 }
9222be18
GN		 3305 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3306 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3307 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3308
3309 } else
ce7ddec4 3310 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3311 break;
3312 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3313 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3314 break;
3315 default:
3316 break;
3317 }
3318}
3319
b463a6f7
AK		 3320static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3321{
3322 struct vcpu_svm *svm = to_svm(vcpu);
3323 struct vmcb_control_area *control = &svm->vmcb->control;
3324
3325 control->exit_int_info = control->event_inj;
3326 control->exit_int_info_err = control->event_inj_err;
3327 control->event_inj = 0;
3328 svm_complete_interrupts(svm);
3329}
3330
80e31d4f
AK		 3331#ifdef CONFIG_X86_64
3332#define R "r"
3333#else
3334#define R "e"
3335#endif
3336
851ba692 3337static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3338{
a2fa3e9f 3339 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3340
2041a06a
JR		 3341 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3342 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3343 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3344
cd3ff653
JR		 3345 /*
3346 * A vmexit emulation is required before the vcpu can be executed
3347 * again.
3348 */
3349 if (unlikely(svm->nested.exit_required))
3350 return;
3351
e756fc62 3352 pre_svm_run(svm);
6aa8b732 3353
649d6864
JR		 3354 sync_lapic_to_cr8(vcpu);
3355
cda0ffdd 3356 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3357
04d2cc77
AK		 3358 clgi();
3359
3360 local_irq_enable();
36241b8c 3361
6aa8b732 3362 asm volatile (
80e31d4f
AK		 3363 "push %%"R"bp; \n\t"
3364 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3365 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3366 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3367 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3368 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3369 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3370#ifdef CONFIG_X86_64
fb3f0f51
RR		 3371 "mov %c[r8](%[svm]), %%r8 \n\t"
3372 "mov %c[r9](%[svm]), %%r9 \n\t"
3373 "mov %c[r10](%[svm]), %%r10 \n\t"
3374 "mov %c[r11](%[svm]), %%r11 \n\t"
3375 "mov %c[r12](%[svm]), %%r12 \n\t"
3376 "mov %c[r13](%[svm]), %%r13 \n\t"
3377 "mov %c[r14](%[svm]), %%r14 \n\t"
3378 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3379#endif
3380
6aa8b732 3381 /* Enter guest mode */
80e31d4f
AK		 3382 "push %%"R"ax \n\t"
3383 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3384 __ex(SVM_VMLOAD) "\n\t"
3385 __ex(SVM_VMRUN) "\n\t"
3386 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3387 "pop %%"R"ax \n\t"
6aa8b732
AK		 3388
3389 /* Save guest registers, load host registers */
80e31d4f
AK		 3390 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3391 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3392 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3393 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3394 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3395 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3396#ifdef CONFIG_X86_64
fb3f0f51
RR		 3397 "mov %%r8, %c[r8](%[svm]) \n\t"
3398 "mov %%r9, %c[r9](%[svm]) \n\t"
3399 "mov %%r10, %c[r10](%[svm]) \n\t"
3400 "mov %%r11, %c[r11](%[svm]) \n\t"
3401 "mov %%r12, %c[r12](%[svm]) \n\t"
3402 "mov %%r13, %c[r13](%[svm]) \n\t"
3403 "mov %%r14, %c[r14](%[svm]) \n\t"
3404 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3405#endif
80e31d4f 3406 "pop %%"R"bp"
6aa8b732 3407 :
fb3f0f51 3408 : [svm]"a"(svm),
6aa8b732 3409 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3410 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3411 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3412 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3413 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3414 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3415 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3416#ifdef CONFIG_X86_64
ad312c7c
ZX		 3417 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3418 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3419 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3420 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3421 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3422 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3423 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3424 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3425#endif
54a08c04 3426 : "cc", "memory"
80e31d4f 3427 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3428#ifdef CONFIG_X86_64
54a08c04
LV		 3429 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3430#endif
3431 );
6aa8b732 3432
82ca2d10
AK		 3433#ifdef CONFIG_X86_64
3434 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3435#else
dacccfdd 3436 loadsegment(fs, svm->host.fs);
9581d442 3437#endif
6aa8b732
AK		 3438
3439 reload_tss(vcpu);
3440
56ba47dd
AK		 3441 local_irq_disable();
3442
3443 stgi();
3444
13c34e07
AK		 3445 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3446 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3447 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3448 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3449
d7bf8221
JR		 3450 sync_cr8_to_lapic(vcpu);
3451
a2fa3e9f 3452 svm->next_rip = 0;
9222be18 3453
631bc487
GN		 3454 /* if exit due to PF check for async PF */
3455 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3456 svm->apf_reason = kvm_read_and_reset_pf_reason();
3457
6de4f3ad
AK		 3458 if (npt_enabled) {
3459 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3460 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3461 }
fe5913e4
JR		 3462
3463 /*
3464 * We need to handle MC intercepts here before the vcpu has a chance to
3465 * change the physical cpu
3466 */
3467 if (unlikely(svm->vmcb->control.exit_code ==
3468 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3469 svm_handle_mce(svm);
6aa8b732
AK		 3470}
3471
80e31d4f
AK		 3472#undef R
3473
6aa8b732
AK		 3474static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3475{
a2fa3e9f
GH		 3476 struct vcpu_svm *svm = to_svm(vcpu);
3477
3478 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3479 force_new_asid(vcpu);
3480}
3481
1c97f0a0
JR		 3482static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3483{
3484 struct vcpu_svm *svm = to_svm(vcpu);
3485
3486 svm->vmcb->control.nested_cr3 = root;
3487
3488 /* Also sync guest cr3 here in case we live migrate */
3489 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3490
3491 force_new_asid(vcpu);
3492}
3493
6aa8b732
AK		 3494static int is_disabled(void)
3495{
6031a61c
JR		 3496 u64 vm_cr;
3497
3498 rdmsrl(MSR_VM_CR, vm_cr);
3499 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3500 return 1;
3501
6aa8b732
AK		 3502 return 0;
3503}
3504
102d8325
IM		 3505static void
3506svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3507{
3508 /*
3509 * Patch in the VMMCALL instruction:
3510 */
3511 hypercall[0] = 0x0f;
3512 hypercall[1] = 0x01;
3513 hypercall[2] = 0xd9;
102d8325
IM		 3514}
3515
002c7f7c
YS		 3516static void svm_check_processor_compat(void *rtn)
3517{
3518 *(int *)rtn = 0;
3519}
3520
774ead3a
AK		 3521static bool svm_cpu_has_accelerated_tpr(void)
3522{
3523 return false;
3524}
3525
4b12f0de 3526static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3527{
3528 return 0;
3529}
3530
0e851880
SY		 3531static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3532{
3533}
3534
d4330ef2
JR		 3535static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3536{
c2c63a49 3537 switch (func) {
24d1b15f
JR		 3538 case 0x00000001:
3539 /* Mask out xsave bit as long as it is not supported by SVM */
3540 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3541 break;
4c62a2dc
JR		 3542 case 0x80000001:
3543 if (nested)
3544 entry->ecx |= (1 << 2); /* Set SVM bit */
3545 break;
c2c63a49
JR		 3546 case 0x8000000A:
3547 entry->eax = 1; /* SVM revision 1 */
3548 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3549 ASID emulation to nested SVM */
3550 entry->ecx = 0; /* Reserved */
7a190667
JR		 3551 entry->edx = 0; /* Per default do not support any
3552 additional features */
3553
3554 /* Support next_rip if host supports it */
2a6b20b8 3555 if (boot_cpu_has(X86_FEATURE_NRIPS))
7a190667 3556 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49 3557
3d4aeaad
JR		 3558 /* Support NPT for the guest if enabled */
3559 if (npt_enabled)
3560 entry->edx |= SVM_FEATURE_NPT;
3561
c2c63a49
JR		 3562 break;
3563 }
d4330ef2
JR		 3564}
3565
229456fc 3566static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3567 { SVM_EXIT_READ_CR0, "read_cr0" },
3568 { SVM_EXIT_READ_CR3, "read_cr3" },
3569 { SVM_EXIT_READ_CR4, "read_cr4" },
3570 { SVM_EXIT_READ_CR8, "read_cr8" },
3571 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3572 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3573 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3574 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3575 { SVM_EXIT_READ_DR0, "read_dr0" },
3576 { SVM_EXIT_READ_DR1, "read_dr1" },
3577 { SVM_EXIT_READ_DR2, "read_dr2" },
3578 { SVM_EXIT_READ_DR3, "read_dr3" },
3579 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3580 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3581 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3582 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3583 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3584 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3585 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3586 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3587 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3588 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3589 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3590 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3591 { SVM_EXIT_INTR, "interrupt" },
3592 { SVM_EXIT_NMI, "nmi" },
3593 { SVM_EXIT_SMI, "smi" },
3594 { SVM_EXIT_INIT, "init" },
3595 { SVM_EXIT_VINTR, "vintr" },
3596 { SVM_EXIT_CPUID, "cpuid" },
3597 { SVM_EXIT_INVD, "invd" },
3598 { SVM_EXIT_HLT, "hlt" },
3599 { SVM_EXIT_INVLPG, "invlpg" },
3600 { SVM_EXIT_INVLPGA, "invlpga" },
3601 { SVM_EXIT_IOIO, "io" },
3602 { SVM_EXIT_MSR, "msr" },
3603 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3604 { SVM_EXIT_SHUTDOWN, "shutdown" },
3605 { SVM_EXIT_VMRUN, "vmrun" },
3606 { SVM_EXIT_VMMCALL, "hypercall" },
3607 { SVM_EXIT_VMLOAD, "vmload" },
3608 { SVM_EXIT_VMSAVE, "vmsave" },
3609 { SVM_EXIT_STGI, "stgi" },
3610 { SVM_EXIT_CLGI, "clgi" },
3611 { SVM_EXIT_SKINIT, "skinit" },
3612 { SVM_EXIT_WBINVD, "wbinvd" },
3613 { SVM_EXIT_MONITOR, "monitor" },
3614 { SVM_EXIT_MWAIT, "mwait" },
3615 { SVM_EXIT_NPF, "npf" },
3616 { -1, NULL }
3617};
3618
17cc3935 3619static int svm_get_lpage_level(void)
344f414f 3620{
17cc3935 3621 return PT_PDPE_LEVEL;
344f414f
JR		 3622}
3623
4e47c7a6
SY		 3624static bool svm_rdtscp_supported(void)
3625{
3626 return false;
3627}
3628
f5f48ee1
SY		 3629static bool svm_has_wbinvd_exit(void)
3630{
3631 return true;
3632}
3633
02daab21
AK		 3634static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3635{
3636 struct vcpu_svm *svm = to_svm(vcpu);
3637
02daab21 3638 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
2030753d 3639 if (is_guest_mode(vcpu))
66a562f7
JR		 3640 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3641 update_cr0_intercept(svm);
02daab21
AK		 3642}
3643
cbdd1bea 3644static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3645 .cpu_has_kvm_support = has_svm,
3646 .disabled_by_bios = is_disabled,
3647 .hardware_setup = svm_hardware_setup,
3648 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3649 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3650 .hardware_enable = svm_hardware_enable,
3651 .hardware_disable = svm_hardware_disable,
774ead3a 3652 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3653
3654 .vcpu_create = svm_create_vcpu,
3655 .vcpu_free = svm_free_vcpu,
04d2cc77 3656 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3657
04d2cc77 3658 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3659 .vcpu_load = svm_vcpu_load,
3660 .vcpu_put = svm_vcpu_put,
3661
3662 .set_guest_debug = svm_guest_debug,
3663 .get_msr = svm_get_msr,
3664 .set_msr = svm_set_msr,
3665 .get_segment_base = svm_get_segment_base,
3666 .get_segment = svm_get_segment,
3667 .set_segment = svm_set_segment,
2e4d2653 3668 .get_cpl = svm_get_cpl,
1747fb71 3669 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3670 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3671 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3672 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3673 .set_cr3 = svm_set_cr3,
3674 .set_cr4 = svm_set_cr4,
3675 .set_efer = svm_set_efer,
3676 .get_idt = svm_get_idt,
3677 .set_idt = svm_set_idt,
3678 .get_gdt = svm_get_gdt,
3679 .set_gdt = svm_set_gdt,
020df079 3680 .set_dr7 = svm_set_dr7,
6de4f3ad 3681 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3682 .get_rflags = svm_get_rflags,
3683 .set_rflags = svm_set_rflags,
6b52d186 3684 .fpu_activate = svm_fpu_activate,
02daab21 3685 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3686
6aa8b732 3687 .tlb_flush = svm_flush_tlb,
6aa8b732 3688
6aa8b732 3689 .run = svm_vcpu_run,
04d2cc77 3690 .handle_exit = handle_exit,
6aa8b732 3691 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3692 .set_interrupt_shadow = svm_set_interrupt_shadow,
3693 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3694 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3695 .set_irq = svm_set_irq,
95ba8273 3696 .set_nmi = svm_inject_nmi,
298101da 3697 .queue_exception = svm_queue_exception,
b463a6f7 3698 .cancel_injection = svm_cancel_injection,
78646121 3699 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3700 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3701 .get_nmi_mask = svm_get_nmi_mask,
3702 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3703 .enable_nmi_window = enable_nmi_window,
3704 .enable_irq_window = enable_irq_window,
3705 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3706
3707 .set_tss_addr = svm_set_tss_addr,
67253af5 3708 .get_tdp_level = get_npt_level,
4b12f0de 3709 .get_mt_mask = svm_get_mt_mask,
229456fc 3710
586f9607 3711 .get_exit_info = svm_get_exit_info,
229456fc 3712 .exit_reasons_str = svm_exit_reasons_str,
586f9607 3713
17cc3935 3714 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3715
3716 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3717
3718 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3719
3720 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3721
3722 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a
ZA		 3723
3724 .write_tsc_offset = svm_write_tsc_offset,
e48672fa 3725 .adjust_tsc_offset = svm_adjust_tsc_offset,
1c97f0a0
JR		 3726
3727 .set_tdp_cr3 = set_tdp_cr3,
6aa8b732
AK		 3728};
3729
3730static int __init svm_init(void)
3731{
cb498ea2 3732 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3733 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3734}
3735
3736static void __exit svm_exit(void)
3737{
cb498ea2 3738 kvm_exit();
6aa8b732
AK		 3739}
3740
3741module_init(svm_init)
3742module_exit(svm_exit)
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