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Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
42f61420 | 19 | #include <linux/cpu.h> |
fd63e9ce | 20 | #include <linux/delay.h> |
b60503ba MW |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/genhd.h> | |
4cc09e2d | 24 | #include <linux/hdreg.h> |
5aff9382 | 25 | #include <linux/idr.h> |
b60503ba MW |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kdev_t.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/mm.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
77bf25ea | 34 | #include <linux/mutex.h> |
b60503ba | 35 | #include <linux/pci.h> |
be7b6275 | 36 | #include <linux/poison.h> |
c3bfe717 | 37 | #include <linux/ptrace.h> |
b60503ba MW |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
e1e5e564 | 40 | #include <linux/t10-pi.h> |
2d55cd5f | 41 | #include <linux/timer.h> |
b60503ba | 42 | #include <linux/types.h> |
2f8e2c87 | 43 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 44 | #include <asm/unaligned.h> |
797a796a | 45 | |
f11bb3e2 CH |
46 | #include "nvme.h" |
47 | ||
9d43cf64 | 48 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 49 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
50 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
51 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
adf68f21 CH |
52 | |
53 | /* | |
54 | * We handle AEN commands ourselves and don't even let the | |
55 | * block layer know about them. | |
56 | */ | |
57 | #define NVME_NR_AEN_COMMANDS 1 | |
58 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) | |
9d43cf64 | 59 | |
58ffacb5 MW |
60 | static int use_threaded_interrupts; |
61 | module_param(use_threaded_interrupts, int, 0); | |
62 | ||
8ffaadf7 JD |
63 | static bool use_cmb_sqes = true; |
64 | module_param(use_cmb_sqes, bool, 0644); | |
65 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
66 | ||
9a6b9458 | 67 | static struct workqueue_struct *nvme_workq; |
1fa6aead | 68 | |
1c63dc66 CH |
69 | struct nvme_dev; |
70 | struct nvme_queue; | |
b3fffdef | 71 | |
4cc06521 | 72 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 73 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 74 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 75 | |
1c63dc66 CH |
76 | /* |
77 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
78 | */ | |
79 | struct nvme_dev { | |
1c63dc66 CH |
80 | struct nvme_queue **queues; |
81 | struct blk_mq_tag_set tagset; | |
82 | struct blk_mq_tag_set admin_tagset; | |
83 | u32 __iomem *dbs; | |
84 | struct device *dev; | |
85 | struct dma_pool *prp_page_pool; | |
86 | struct dma_pool *prp_small_pool; | |
87 | unsigned queue_count; | |
88 | unsigned online_queues; | |
89 | unsigned max_qid; | |
90 | int q_depth; | |
91 | u32 db_stride; | |
1c63dc66 CH |
92 | struct msix_entry *entry; |
93 | void __iomem *bar; | |
1c63dc66 | 94 | struct work_struct reset_work; |
1c63dc66 | 95 | struct work_struct scan_work; |
5c8809e6 | 96 | struct work_struct remove_work; |
9396dec9 | 97 | struct work_struct async_work; |
2d55cd5f | 98 | struct timer_list watchdog_timer; |
77bf25ea | 99 | struct mutex shutdown_lock; |
1c63dc66 | 100 | bool subsystem; |
1c63dc66 CH |
101 | void __iomem *cmb; |
102 | dma_addr_t cmb_dma_addr; | |
103 | u64 cmb_size; | |
104 | u32 cmbsz; | |
1c63dc66 | 105 | struct nvme_ctrl ctrl; |
db3cbfff | 106 | struct completion ioq_wait; |
4d115420 | 107 | }; |
1fa6aead | 108 | |
1c63dc66 CH |
109 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
110 | { | |
111 | return container_of(ctrl, struct nvme_dev, ctrl); | |
112 | } | |
113 | ||
b60503ba MW |
114 | /* |
115 | * An NVM Express queue. Each device has at least two (one for admin | |
116 | * commands and one for I/O commands). | |
117 | */ | |
118 | struct nvme_queue { | |
119 | struct device *q_dmadev; | |
091b6092 | 120 | struct nvme_dev *dev; |
3193f07b | 121 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
122 | spinlock_t q_lock; |
123 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 124 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 125 | volatile struct nvme_completion *cqes; |
42483228 | 126 | struct blk_mq_tags **tags; |
b60503ba MW |
127 | dma_addr_t sq_dma_addr; |
128 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
129 | u32 __iomem *q_db; |
130 | u16 q_depth; | |
6222d172 | 131 | s16 cq_vector; |
b60503ba MW |
132 | u16 sq_tail; |
133 | u16 cq_head; | |
c30341dc | 134 | u16 qid; |
e9539f47 MW |
135 | u8 cq_phase; |
136 | u8 cqe_seen; | |
b60503ba MW |
137 | }; |
138 | ||
71bd150c CH |
139 | /* |
140 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
141 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 142 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
143 | * allocated to store the PRP list. |
144 | */ | |
145 | struct nvme_iod { | |
f4800d6d CH |
146 | struct nvme_queue *nvmeq; |
147 | int aborted; | |
71bd150c | 148 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
149 | int nents; /* Used in scatterlist */ |
150 | int length; /* Of data, in bytes */ | |
151 | dma_addr_t first_dma; | |
bf684057 | 152 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
153 | struct scatterlist *sg; |
154 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
155 | }; |
156 | ||
157 | /* | |
158 | * Check we didin't inadvertently grow the command struct | |
159 | */ | |
160 | static inline void _nvme_check_size(void) | |
161 | { | |
162 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
163 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
164 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
165 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
166 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 167 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 168 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
169 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
170 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
171 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
172 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 173 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
174 | } |
175 | ||
ac3dd5bd JA |
176 | /* |
177 | * Max size of iod being embedded in the request payload | |
178 | */ | |
179 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 180 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
181 | |
182 | /* | |
183 | * Will slightly overestimate the number of pages needed. This is OK | |
184 | * as it only leads to a small amount of wasted memory for the lifetime of | |
185 | * the I/O. | |
186 | */ | |
187 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
188 | { | |
5fd4ce1b CH |
189 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
190 | dev->ctrl.page_size); | |
ac3dd5bd JA |
191 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
192 | } | |
193 | ||
f4800d6d CH |
194 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
195 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 196 | { |
f4800d6d CH |
197 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
198 | sizeof(struct scatterlist) * nseg; | |
199 | } | |
ac3dd5bd | 200 | |
f4800d6d CH |
201 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
202 | { | |
203 | return sizeof(struct nvme_iod) + | |
204 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
205 | } |
206 | ||
a4aea562 MB |
207 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
208 | unsigned int hctx_idx) | |
e85248e5 | 209 | { |
a4aea562 MB |
210 | struct nvme_dev *dev = data; |
211 | struct nvme_queue *nvmeq = dev->queues[0]; | |
212 | ||
42483228 KB |
213 | WARN_ON(hctx_idx != 0); |
214 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
215 | WARN_ON(nvmeq->tags); | |
216 | ||
a4aea562 | 217 | hctx->driver_data = nvmeq; |
42483228 | 218 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 219 | return 0; |
e85248e5 MW |
220 | } |
221 | ||
4af0e21c KB |
222 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
223 | { | |
224 | struct nvme_queue *nvmeq = hctx->driver_data; | |
225 | ||
226 | nvmeq->tags = NULL; | |
227 | } | |
228 | ||
a4aea562 MB |
229 | static int nvme_admin_init_request(void *data, struct request *req, |
230 | unsigned int hctx_idx, unsigned int rq_idx, | |
231 | unsigned int numa_node) | |
22404274 | 232 | { |
a4aea562 | 233 | struct nvme_dev *dev = data; |
f4800d6d | 234 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
235 | struct nvme_queue *nvmeq = dev->queues[0]; |
236 | ||
237 | BUG_ON(!nvmeq); | |
f4800d6d | 238 | iod->nvmeq = nvmeq; |
a4aea562 | 239 | return 0; |
22404274 KB |
240 | } |
241 | ||
a4aea562 MB |
242 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
243 | unsigned int hctx_idx) | |
b60503ba | 244 | { |
a4aea562 | 245 | struct nvme_dev *dev = data; |
42483228 | 246 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 247 | |
42483228 KB |
248 | if (!nvmeq->tags) |
249 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 250 | |
42483228 | 251 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
252 | hctx->driver_data = nvmeq; |
253 | return 0; | |
b60503ba MW |
254 | } |
255 | ||
a4aea562 MB |
256 | static int nvme_init_request(void *data, struct request *req, |
257 | unsigned int hctx_idx, unsigned int rq_idx, | |
258 | unsigned int numa_node) | |
b60503ba | 259 | { |
a4aea562 | 260 | struct nvme_dev *dev = data; |
f4800d6d | 261 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
262 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
263 | ||
264 | BUG_ON(!nvmeq); | |
f4800d6d | 265 | iod->nvmeq = nvmeq; |
a4aea562 MB |
266 | return 0; |
267 | } | |
268 | ||
646017a6 KB |
269 | static void nvme_queue_scan(struct nvme_dev *dev) |
270 | { | |
271 | /* | |
272 | * Do not queue new scan work when a controller is reset during | |
273 | * removal. | |
274 | */ | |
bb8d261e CH |
275 | if (dev->ctrl.state != NVME_CTRL_DELETING) |
276 | queue_work(nvme_workq, &dev->scan_work); | |
646017a6 KB |
277 | } |
278 | ||
adf68f21 CH |
279 | static void nvme_complete_async_event(struct nvme_dev *dev, |
280 | struct nvme_completion *cqe) | |
a4aea562 | 281 | { |
adf68f21 CH |
282 | u16 status = le16_to_cpu(cqe->status) >> 1; |
283 | u32 result = le32_to_cpu(cqe->result); | |
a4aea562 | 284 | |
9396dec9 | 285 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) { |
adf68f21 | 286 | ++dev->ctrl.event_limit; |
9396dec9 CH |
287 | queue_work(nvme_workq, &dev->async_work); |
288 | } | |
289 | ||
a5768aa8 KB |
290 | if (status != NVME_SC_SUCCESS) |
291 | return; | |
292 | ||
293 | switch (result & 0xff07) { | |
294 | case NVME_AER_NOTICE_NS_CHANGED: | |
1b3c47c1 | 295 | dev_info(dev->ctrl.device, "rescanning\n"); |
646017a6 | 296 | nvme_queue_scan(dev); |
a5768aa8 | 297 | default: |
1b3c47c1 | 298 | dev_warn(dev->ctrl.device, "async event result %08x\n", result); |
a4aea562 | 299 | } |
b60503ba MW |
300 | } |
301 | ||
302 | /** | |
adf68f21 | 303 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
304 | * @nvmeq: The queue to use |
305 | * @cmd: The command to send | |
306 | * | |
307 | * Safe to use from interrupt context | |
308 | */ | |
e3f879bf SB |
309 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
310 | struct nvme_command *cmd) | |
b60503ba | 311 | { |
a4aea562 MB |
312 | u16 tail = nvmeq->sq_tail; |
313 | ||
8ffaadf7 JD |
314 | if (nvmeq->sq_cmds_io) |
315 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
316 | else | |
317 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
318 | ||
b60503ba MW |
319 | if (++tail == nvmeq->q_depth) |
320 | tail = 0; | |
7547881d | 321 | writel(tail, nvmeq->q_db); |
b60503ba | 322 | nvmeq->sq_tail = tail; |
b60503ba MW |
323 | } |
324 | ||
f4800d6d | 325 | static __le64 **iod_list(struct request *req) |
b60503ba | 326 | { |
f4800d6d CH |
327 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
328 | return (__le64 **)(iod->sg + req->nr_phys_segments); | |
b60503ba MW |
329 | } |
330 | ||
58b45602 ML |
331 | static int nvme_init_iod(struct request *rq, unsigned size, |
332 | struct nvme_dev *dev) | |
ac3dd5bd | 333 | { |
f4800d6d CH |
334 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
335 | int nseg = rq->nr_phys_segments; | |
ac3dd5bd | 336 | |
f4800d6d CH |
337 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
338 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
339 | if (!iod->sg) | |
340 | return BLK_MQ_RQ_QUEUE_BUSY; | |
341 | } else { | |
342 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
343 | } |
344 | ||
f4800d6d CH |
345 | iod->aborted = 0; |
346 | iod->npages = -1; | |
347 | iod->nents = 0; | |
348 | iod->length = size; | |
349 | return 0; | |
ac3dd5bd JA |
350 | } |
351 | ||
f4800d6d | 352 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 353 | { |
f4800d6d | 354 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 355 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 356 | int i; |
f4800d6d | 357 | __le64 **list = iod_list(req); |
eca18b23 MW |
358 | dma_addr_t prp_dma = iod->first_dma; |
359 | ||
03b5929e ML |
360 | if (req->cmd_flags & REQ_DISCARD) |
361 | kfree(req->completion_data); | |
362 | ||
eca18b23 MW |
363 | if (iod->npages == 0) |
364 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
365 | for (i = 0; i < iod->npages; i++) { | |
366 | __le64 *prp_list = list[i]; | |
367 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
368 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
369 | prp_dma = next_prp_dma; | |
370 | } | |
ac3dd5bd | 371 | |
f4800d6d CH |
372 | if (iod->sg != iod->inline_sg) |
373 | kfree(iod->sg); | |
b4ff9c8d KB |
374 | } |
375 | ||
52b68d7e | 376 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
377 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
378 | { | |
379 | if (be32_to_cpu(pi->ref_tag) == v) | |
380 | pi->ref_tag = cpu_to_be32(p); | |
381 | } | |
382 | ||
383 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
384 | { | |
385 | if (be32_to_cpu(pi->ref_tag) == p) | |
386 | pi->ref_tag = cpu_to_be32(v); | |
387 | } | |
388 | ||
389 | /** | |
390 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
391 | * | |
392 | * The virtual start sector is the one that was originally submitted by the | |
393 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
394 | * start sector may be different. Remap protection information to match the | |
395 | * physical LBA on writes, and back to the original seed on reads. | |
396 | * | |
397 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
398 | */ | |
399 | static void nvme_dif_remap(struct request *req, | |
400 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
401 | { | |
402 | struct nvme_ns *ns = req->rq_disk->private_data; | |
403 | struct bio_integrity_payload *bip; | |
404 | struct t10_pi_tuple *pi; | |
405 | void *p, *pmap; | |
406 | u32 i, nlb, ts, phys, virt; | |
407 | ||
408 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
409 | return; | |
410 | ||
411 | bip = bio_integrity(req->bio); | |
412 | if (!bip) | |
413 | return; | |
414 | ||
415 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
416 | |
417 | p = pmap; | |
418 | virt = bip_get_seed(bip); | |
419 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
420 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 421 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
422 | |
423 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
424 | pi = (struct t10_pi_tuple *)p; | |
425 | dif_swap(phys, virt, pi); | |
426 | p += ts; | |
427 | } | |
428 | kunmap_atomic(pmap); | |
429 | } | |
52b68d7e KB |
430 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
431 | static void nvme_dif_remap(struct request *req, | |
432 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
433 | { | |
434 | } | |
435 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
436 | { | |
437 | } | |
438 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
439 | { | |
440 | } | |
52b68d7e KB |
441 | #endif |
442 | ||
f4800d6d | 443 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req, |
69d2b571 | 444 | int total_len) |
ff22b54f | 445 | { |
f4800d6d | 446 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 447 | struct dma_pool *pool; |
eca18b23 MW |
448 | int length = total_len; |
449 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
450 | int dma_len = sg_dma_len(sg); |
451 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 452 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 453 | int offset = dma_addr & (page_size - 1); |
e025344c | 454 | __le64 *prp_list; |
f4800d6d | 455 | __le64 **list = iod_list(req); |
e025344c | 456 | dma_addr_t prp_dma; |
eca18b23 | 457 | int nprps, i; |
ff22b54f | 458 | |
1d090624 | 459 | length -= (page_size - offset); |
ff22b54f | 460 | if (length <= 0) |
69d2b571 | 461 | return true; |
ff22b54f | 462 | |
1d090624 | 463 | dma_len -= (page_size - offset); |
ff22b54f | 464 | if (dma_len) { |
1d090624 | 465 | dma_addr += (page_size - offset); |
ff22b54f MW |
466 | } else { |
467 | sg = sg_next(sg); | |
468 | dma_addr = sg_dma_address(sg); | |
469 | dma_len = sg_dma_len(sg); | |
470 | } | |
471 | ||
1d090624 | 472 | if (length <= page_size) { |
edd10d33 | 473 | iod->first_dma = dma_addr; |
69d2b571 | 474 | return true; |
e025344c SMM |
475 | } |
476 | ||
1d090624 | 477 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
478 | if (nprps <= (256 / 8)) { |
479 | pool = dev->prp_small_pool; | |
eca18b23 | 480 | iod->npages = 0; |
99802a7a MW |
481 | } else { |
482 | pool = dev->prp_page_pool; | |
eca18b23 | 483 | iod->npages = 1; |
99802a7a MW |
484 | } |
485 | ||
69d2b571 | 486 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 487 | if (!prp_list) { |
edd10d33 | 488 | iod->first_dma = dma_addr; |
eca18b23 | 489 | iod->npages = -1; |
69d2b571 | 490 | return false; |
b77954cb | 491 | } |
eca18b23 MW |
492 | list[0] = prp_list; |
493 | iod->first_dma = prp_dma; | |
e025344c SMM |
494 | i = 0; |
495 | for (;;) { | |
1d090624 | 496 | if (i == page_size >> 3) { |
e025344c | 497 | __le64 *old_prp_list = prp_list; |
69d2b571 | 498 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 499 | if (!prp_list) |
69d2b571 | 500 | return false; |
eca18b23 | 501 | list[iod->npages++] = prp_list; |
7523d834 MW |
502 | prp_list[0] = old_prp_list[i - 1]; |
503 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
504 | i = 1; | |
e025344c SMM |
505 | } |
506 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
507 | dma_len -= page_size; |
508 | dma_addr += page_size; | |
509 | length -= page_size; | |
e025344c SMM |
510 | if (length <= 0) |
511 | break; | |
512 | if (dma_len > 0) | |
513 | continue; | |
514 | BUG_ON(dma_len < 0); | |
515 | sg = sg_next(sg); | |
516 | dma_addr = sg_dma_address(sg); | |
517 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
518 | } |
519 | ||
69d2b571 | 520 | return true; |
ff22b54f MW |
521 | } |
522 | ||
f4800d6d | 523 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
03b5929e | 524 | unsigned size, struct nvme_command *cmnd) |
d29ec824 | 525 | { |
f4800d6d | 526 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
527 | struct request_queue *q = req->q; |
528 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
529 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
530 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
d29ec824 | 531 | |
ba1ca37e CH |
532 | sg_init_table(iod->sg, req->nr_phys_segments); |
533 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
534 | if (!iod->nents) | |
535 | goto out; | |
d29ec824 | 536 | |
ba1ca37e CH |
537 | ret = BLK_MQ_RQ_QUEUE_BUSY; |
538 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
539 | goto out; | |
d29ec824 | 540 | |
03b5929e | 541 | if (!nvme_setup_prps(dev, req, size)) |
ba1ca37e | 542 | goto out_unmap; |
0e5e4f0e | 543 | |
ba1ca37e CH |
544 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
545 | if (blk_integrity_rq(req)) { | |
546 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
547 | goto out_unmap; | |
0e5e4f0e | 548 | |
bf684057 CH |
549 | sg_init_table(&iod->meta_sg, 1); |
550 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 551 | goto out_unmap; |
0e5e4f0e | 552 | |
ba1ca37e CH |
553 | if (rq_data_dir(req)) |
554 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 555 | |
bf684057 | 556 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 557 | goto out_unmap; |
d29ec824 | 558 | } |
00df5cb4 | 559 | |
ba1ca37e CH |
560 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
561 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
562 | if (blk_integrity_rq(req)) | |
bf684057 | 563 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e | 564 | return BLK_MQ_RQ_QUEUE_OK; |
00df5cb4 | 565 | |
ba1ca37e CH |
566 | out_unmap: |
567 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
568 | out: | |
569 | return ret; | |
00df5cb4 MW |
570 | } |
571 | ||
f4800d6d | 572 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 573 | { |
f4800d6d | 574 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
575 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
576 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
577 | ||
578 | if (iod->nents) { | |
579 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
580 | if (blk_integrity_rq(req)) { | |
581 | if (!rq_data_dir(req)) | |
582 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 583 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 584 | } |
e19b127f | 585 | } |
e1e5e564 | 586 | |
f4800d6d | 587 | nvme_free_iod(dev, req); |
d4f6c3ab | 588 | } |
b60503ba | 589 | |
d29ec824 CH |
590 | /* |
591 | * NOTE: ns is NULL when called on the admin queue. | |
592 | */ | |
a4aea562 MB |
593 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
594 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 595 | { |
a4aea562 MB |
596 | struct nvme_ns *ns = hctx->queue->queuedata; |
597 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 598 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 599 | struct request *req = bd->rq; |
ba1ca37e | 600 | struct nvme_command cmnd; |
58b45602 | 601 | unsigned map_len; |
ba1ca37e | 602 | int ret = BLK_MQ_RQ_QUEUE_OK; |
edd10d33 | 603 | |
e1e5e564 KB |
604 | /* |
605 | * If formated with metadata, require the block layer provide a buffer | |
606 | * unless this namespace is formated such that the metadata can be | |
607 | * stripped/generated by the controller with PRACT=1. | |
608 | */ | |
d29ec824 | 609 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
610 | if (!(ns->pi_type && ns->ms == 8) && |
611 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 612 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
613 | return BLK_MQ_RQ_QUEUE_OK; |
614 | } | |
615 | } | |
616 | ||
58b45602 ML |
617 | map_len = nvme_map_len(req); |
618 | ret = nvme_init_iod(req, map_len, dev); | |
f4800d6d CH |
619 | if (ret) |
620 | return ret; | |
a4aea562 | 621 | |
8093f7ca | 622 | ret = nvme_setup_cmd(ns, req, &cmnd); |
03b5929e ML |
623 | if (ret) |
624 | goto out; | |
625 | ||
626 | if (req->nr_phys_segments) | |
627 | ret = nvme_map_data(dev, req, map_len, &cmnd); | |
a4aea562 | 628 | |
ba1ca37e CH |
629 | if (ret) |
630 | goto out; | |
a4aea562 | 631 | |
ba1ca37e | 632 | cmnd.common.command_id = req->tag; |
aae239e1 | 633 | blk_mq_start_request(req); |
a4aea562 | 634 | |
ba1ca37e | 635 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 636 | if (unlikely(nvmeq->cq_vector < 0)) { |
69d9a99c KB |
637 | if (ns && !test_bit(NVME_NS_DEAD, &ns->flags)) |
638 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
639 | else | |
640 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
ae1fba20 KB |
641 | spin_unlock_irq(&nvmeq->q_lock); |
642 | goto out; | |
643 | } | |
ba1ca37e | 644 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
645 | nvme_process_cq(nvmeq); |
646 | spin_unlock_irq(&nvmeq->q_lock); | |
647 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 648 | out: |
f4800d6d | 649 | nvme_free_iod(dev, req); |
ba1ca37e | 650 | return ret; |
b60503ba | 651 | } |
e1e5e564 | 652 | |
eee417b0 CH |
653 | static void nvme_complete_rq(struct request *req) |
654 | { | |
f4800d6d CH |
655 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
656 | struct nvme_dev *dev = iod->nvmeq->dev; | |
eee417b0 | 657 | int error = 0; |
e1e5e564 | 658 | |
f4800d6d | 659 | nvme_unmap_data(dev, req); |
e1e5e564 | 660 | |
eee417b0 CH |
661 | if (unlikely(req->errors)) { |
662 | if (nvme_req_needs_retry(req, req->errors)) { | |
663 | nvme_requeue_req(req); | |
664 | return; | |
e1e5e564 | 665 | } |
1974b1ae | 666 | |
eee417b0 CH |
667 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) |
668 | error = req->errors; | |
669 | else | |
670 | error = nvme_error_status(req->errors); | |
671 | } | |
a4aea562 | 672 | |
f4800d6d | 673 | if (unlikely(iod->aborted)) { |
1b3c47c1 | 674 | dev_warn(dev->ctrl.device, |
eee417b0 CH |
675 | "completing aborted command with status: %04x\n", |
676 | req->errors); | |
677 | } | |
a4aea562 | 678 | |
eee417b0 | 679 | blk_mq_end_request(req, error); |
b60503ba MW |
680 | } |
681 | ||
d783e0bd MR |
682 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
683 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
684 | u16 phase) | |
685 | { | |
686 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
687 | } | |
688 | ||
a0fa9647 | 689 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 690 | { |
82123460 | 691 | u16 head, phase; |
b60503ba | 692 | |
b60503ba | 693 | head = nvmeq->cq_head; |
82123460 | 694 | phase = nvmeq->cq_phase; |
b60503ba | 695 | |
d783e0bd | 696 | while (nvme_cqe_valid(nvmeq, head, phase)) { |
b60503ba | 697 | struct nvme_completion cqe = nvmeq->cqes[head]; |
eee417b0 | 698 | struct request *req; |
adf68f21 | 699 | |
b60503ba MW |
700 | if (++head == nvmeq->q_depth) { |
701 | head = 0; | |
82123460 | 702 | phase = !phase; |
b60503ba | 703 | } |
adf68f21 | 704 | |
a0fa9647 JA |
705 | if (tag && *tag == cqe.command_id) |
706 | *tag = -1; | |
adf68f21 | 707 | |
aae239e1 | 708 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 709 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
710 | "invalid id %d completed on queue %d\n", |
711 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
712 | continue; | |
713 | } | |
714 | ||
adf68f21 CH |
715 | /* |
716 | * AEN requests are special as they don't time out and can | |
717 | * survive any kind of queue freeze and often don't respond to | |
718 | * aborts. We don't even bother to allocate a struct request | |
719 | * for them but rather special case them here. | |
720 | */ | |
721 | if (unlikely(nvmeq->qid == 0 && | |
722 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
723 | nvme_complete_async_event(nvmeq->dev, &cqe); | |
724 | continue; | |
725 | } | |
726 | ||
eee417b0 | 727 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
1cb3cce5 CH |
728 | if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special) |
729 | memcpy(req->special, &cqe, sizeof(cqe)); | |
d783e0bd | 730 | blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1); |
eee417b0 | 731 | |
b60503ba MW |
732 | } |
733 | ||
734 | /* If the controller ignores the cq head doorbell and continuously | |
735 | * writes to the queue, it is theoretically possible to wrap around | |
736 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
737 | * requires that 0.1% of your interrupts are handled, so this isn't | |
738 | * a big problem. | |
739 | */ | |
82123460 | 740 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 741 | return; |
b60503ba | 742 | |
604e8c8d KB |
743 | if (likely(nvmeq->cq_vector >= 0)) |
744 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 745 | nvmeq->cq_head = head; |
82123460 | 746 | nvmeq->cq_phase = phase; |
b60503ba | 747 | |
e9539f47 | 748 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
749 | } |
750 | ||
751 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
752 | { | |
753 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
754 | } |
755 | ||
756 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
757 | { |
758 | irqreturn_t result; | |
759 | struct nvme_queue *nvmeq = data; | |
760 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
761 | nvme_process_cq(nvmeq); |
762 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
763 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
764 | spin_unlock(&nvmeq->q_lock); |
765 | return result; | |
766 | } | |
767 | ||
768 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
769 | { | |
770 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
771 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
772 | return IRQ_WAKE_THREAD; | |
773 | return IRQ_NONE; | |
58ffacb5 MW |
774 | } |
775 | ||
a0fa9647 JA |
776 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
777 | { | |
778 | struct nvme_queue *nvmeq = hctx->driver_data; | |
779 | ||
d783e0bd | 780 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
a0fa9647 JA |
781 | spin_lock_irq(&nvmeq->q_lock); |
782 | __nvme_process_cq(nvmeq, &tag); | |
783 | spin_unlock_irq(&nvmeq->q_lock); | |
784 | ||
785 | if (tag == -1) | |
786 | return 1; | |
787 | } | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
9396dec9 | 792 | static void nvme_async_event_work(struct work_struct *work) |
b60503ba | 793 | { |
9396dec9 CH |
794 | struct nvme_dev *dev = container_of(work, struct nvme_dev, async_work); |
795 | struct nvme_queue *nvmeq = dev->queues[0]; | |
a4aea562 | 796 | struct nvme_command c; |
b60503ba | 797 | |
a4aea562 MB |
798 | memset(&c, 0, sizeof(c)); |
799 | c.common.opcode = nvme_admin_async_event; | |
3c0cf138 | 800 | |
9396dec9 CH |
801 | spin_lock_irq(&nvmeq->q_lock); |
802 | while (dev->ctrl.event_limit > 0) { | |
803 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + | |
804 | --dev->ctrl.event_limit; | |
805 | __nvme_submit_cmd(nvmeq, &c); | |
806 | } | |
807 | spin_unlock_irq(&nvmeq->q_lock); | |
f705f837 CH |
808 | } |
809 | ||
b60503ba | 810 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 811 | { |
b60503ba MW |
812 | struct nvme_command c; |
813 | ||
814 | memset(&c, 0, sizeof(c)); | |
815 | c.delete_queue.opcode = opcode; | |
816 | c.delete_queue.qid = cpu_to_le16(id); | |
817 | ||
1c63dc66 | 818 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
819 | } |
820 | ||
b60503ba MW |
821 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
822 | struct nvme_queue *nvmeq) | |
823 | { | |
b60503ba MW |
824 | struct nvme_command c; |
825 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
826 | ||
d29ec824 CH |
827 | /* |
828 | * Note: we (ab)use the fact the the prp fields survive if no data | |
829 | * is attached to the request. | |
830 | */ | |
b60503ba MW |
831 | memset(&c, 0, sizeof(c)); |
832 | c.create_cq.opcode = nvme_admin_create_cq; | |
833 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
834 | c.create_cq.cqid = cpu_to_le16(qid); | |
835 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
836 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
837 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
838 | ||
1c63dc66 | 839 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
840 | } |
841 | ||
842 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
843 | struct nvme_queue *nvmeq) | |
844 | { | |
b60503ba MW |
845 | struct nvme_command c; |
846 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
847 | ||
d29ec824 CH |
848 | /* |
849 | * Note: we (ab)use the fact the the prp fields survive if no data | |
850 | * is attached to the request. | |
851 | */ | |
b60503ba MW |
852 | memset(&c, 0, sizeof(c)); |
853 | c.create_sq.opcode = nvme_admin_create_sq; | |
854 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
855 | c.create_sq.sqid = cpu_to_le16(qid); | |
856 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
857 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
858 | c.create_sq.cqid = cpu_to_le16(qid); | |
859 | ||
1c63dc66 | 860 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
861 | } |
862 | ||
863 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
864 | { | |
865 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
866 | } | |
867 | ||
868 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
869 | { | |
870 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
871 | } | |
872 | ||
e7a2a87d | 873 | static void abort_endio(struct request *req, int error) |
bc5fc7e4 | 874 | { |
f4800d6d CH |
875 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
876 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d | 877 | u16 status = req->errors; |
e44ac588 | 878 | |
1cb3cce5 | 879 | dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status); |
e7a2a87d | 880 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 881 | blk_mq_free_request(req); |
bc5fc7e4 MW |
882 | } |
883 | ||
31c7c7d2 | 884 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 885 | { |
f4800d6d CH |
886 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
887 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 888 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 889 | struct request *abort_req; |
a4aea562 | 890 | struct nvme_command cmd; |
c30341dc | 891 | |
31c7c7d2 | 892 | /* |
fd634f41 CH |
893 | * Shutdown immediately if controller times out while starting. The |
894 | * reset work will see the pci device disabled when it gets the forced | |
895 | * cancellation error. All outstanding requests are completed on | |
896 | * shutdown, so we return BLK_EH_HANDLED. | |
897 | */ | |
bb8d261e | 898 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 899 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
900 | "I/O %d QID %d timeout, disable controller\n", |
901 | req->tag, nvmeq->qid); | |
a5cdb68c | 902 | nvme_dev_disable(dev, false); |
fd634f41 CH |
903 | req->errors = NVME_SC_CANCELLED; |
904 | return BLK_EH_HANDLED; | |
c30341dc KB |
905 | } |
906 | ||
fd634f41 CH |
907 | /* |
908 | * Shutdown the controller immediately and schedule a reset if the | |
909 | * command was already aborted once before and still hasn't been | |
910 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 911 | */ |
f4800d6d | 912 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 913 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
914 | "I/O %d QID %d timeout, reset controller\n", |
915 | req->tag, nvmeq->qid); | |
a5cdb68c | 916 | nvme_dev_disable(dev, false); |
e1569a16 | 917 | queue_work(nvme_workq, &dev->reset_work); |
c30341dc | 918 | |
e1569a16 KB |
919 | /* |
920 | * Mark the request as handled, since the inline shutdown | |
921 | * forces all outstanding requests to complete. | |
922 | */ | |
923 | req->errors = NVME_SC_CANCELLED; | |
924 | return BLK_EH_HANDLED; | |
c30341dc | 925 | } |
c30341dc | 926 | |
f4800d6d | 927 | iod->aborted = 1; |
c30341dc | 928 | |
e7a2a87d | 929 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 930 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 931 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 932 | } |
a4aea562 | 933 | |
c30341dc KB |
934 | memset(&cmd, 0, sizeof(cmd)); |
935 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 936 | cmd.abort.cid = req->tag; |
c30341dc | 937 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 938 | |
1b3c47c1 SG |
939 | dev_warn(nvmeq->dev->ctrl.device, |
940 | "I/O %d QID %d timeout, aborting\n", | |
941 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
942 | |
943 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
944 | BLK_MQ_REQ_NOWAIT); | |
945 | if (IS_ERR(abort_req)) { | |
946 | atomic_inc(&dev->ctrl.abort_limit); | |
947 | return BLK_EH_RESET_TIMER; | |
948 | } | |
949 | ||
950 | abort_req->timeout = ADMIN_TIMEOUT; | |
951 | abort_req->end_io_data = NULL; | |
952 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 953 | |
31c7c7d2 CH |
954 | /* |
955 | * The aborted req will be completed on receiving the abort req. | |
956 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
957 | * as the device then is in a faulty state. | |
958 | */ | |
959 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
960 | } |
961 | ||
82b4552b | 962 | static void nvme_cancel_io(struct request *req, void *data, bool reserved) |
a09115b2 | 963 | { |
aae239e1 | 964 | int status; |
cef6a948 KB |
965 | |
966 | if (!blk_mq_request_started(req)) | |
967 | return; | |
a09115b2 | 968 | |
7e197930 JA |
969 | dev_dbg_ratelimited(((struct nvme_dev *) data)->ctrl.device, |
970 | "Cancelling I/O %d", req->tag); | |
a4aea562 | 971 | |
1d49c38c | 972 | status = NVME_SC_ABORT_REQ; |
cef6a948 | 973 | if (blk_queue_dying(req->q)) |
aae239e1 CH |
974 | status |= NVME_SC_DNR; |
975 | blk_mq_complete_request(req, status); | |
a4aea562 | 976 | } |
22404274 | 977 | |
a4aea562 MB |
978 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
979 | { | |
9e866774 MW |
980 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
981 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
982 | if (nvmeq->sq_cmds) |
983 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
984 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
985 | kfree(nvmeq); | |
986 | } | |
987 | ||
a1a5ef99 | 988 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
989 | { |
990 | int i; | |
991 | ||
a1a5ef99 | 992 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 993 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 994 | dev->queue_count--; |
a4aea562 | 995 | dev->queues[i] = NULL; |
f435c282 | 996 | nvme_free_queue(nvmeq); |
121c7ad4 | 997 | } |
22404274 KB |
998 | } |
999 | ||
4d115420 KB |
1000 | /** |
1001 | * nvme_suspend_queue - put queue into suspended state | |
1002 | * @nvmeq - queue to suspend | |
4d115420 KB |
1003 | */ |
1004 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1005 | { |
2b25d981 | 1006 | int vector; |
b60503ba | 1007 | |
a09115b2 | 1008 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1009 | if (nvmeq->cq_vector == -1) { |
1010 | spin_unlock_irq(&nvmeq->q_lock); | |
1011 | return 1; | |
1012 | } | |
1013 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1014 | nvmeq->dev->online_queues--; |
2b25d981 | 1015 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1016 | spin_unlock_irq(&nvmeq->q_lock); |
1017 | ||
1c63dc66 | 1018 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 1019 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1020 | |
aba2080f MW |
1021 | irq_set_affinity_hint(vector, NULL); |
1022 | free_irq(vector, nvmeq); | |
b60503ba | 1023 | |
4d115420 KB |
1024 | return 0; |
1025 | } | |
b60503ba | 1026 | |
a5cdb68c | 1027 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1028 | { |
a5cdb68c | 1029 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
1030 | |
1031 | if (!nvmeq) | |
1032 | return; | |
1033 | if (nvme_suspend_queue(nvmeq)) | |
1034 | return; | |
1035 | ||
a5cdb68c KB |
1036 | if (shutdown) |
1037 | nvme_shutdown_ctrl(&dev->ctrl); | |
1038 | else | |
1039 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
1040 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
1041 | |
1042 | spin_lock_irq(&nvmeq->q_lock); | |
1043 | nvme_process_cq(nvmeq); | |
1044 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1045 | } |
1046 | ||
8ffaadf7 JD |
1047 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1048 | int entry_size) | |
1049 | { | |
1050 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1051 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1052 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1053 | |
1054 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1055 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1056 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1057 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1058 | |
1059 | /* | |
1060 | * Ensure the reduced q_depth is above some threshold where it | |
1061 | * would be better to map queues in system memory with the | |
1062 | * original depth | |
1063 | */ | |
1064 | if (q_depth < 64) | |
1065 | return -ENOMEM; | |
1066 | } | |
1067 | ||
1068 | return q_depth; | |
1069 | } | |
1070 | ||
1071 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1072 | int qid, int depth) | |
1073 | { | |
1074 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1075 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1076 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1077 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1078 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1079 | } else { | |
1080 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1081 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1082 | if (!nvmeq->sq_cmds) | |
1083 | return -ENOMEM; | |
1084 | } | |
1085 | ||
1086 | return 0; | |
1087 | } | |
1088 | ||
b60503ba | 1089 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1090 | int depth) |
b60503ba | 1091 | { |
a4aea562 | 1092 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1093 | if (!nvmeq) |
1094 | return NULL; | |
1095 | ||
e75ec752 | 1096 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1097 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1098 | if (!nvmeq->cqes) |
1099 | goto free_nvmeq; | |
b60503ba | 1100 | |
8ffaadf7 | 1101 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1102 | goto free_cqdma; |
1103 | ||
e75ec752 | 1104 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1105 | nvmeq->dev = dev; |
3193f07b | 1106 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1107 | dev->ctrl.instance, qid); |
b60503ba MW |
1108 | spin_lock_init(&nvmeq->q_lock); |
1109 | nvmeq->cq_head = 0; | |
82123460 | 1110 | nvmeq->cq_phase = 1; |
b80d5ccc | 1111 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1112 | nvmeq->q_depth = depth; |
c30341dc | 1113 | nvmeq->qid = qid; |
758dd7fd | 1114 | nvmeq->cq_vector = -1; |
a4aea562 | 1115 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1116 | dev->queue_count++; |
1117 | ||
b60503ba MW |
1118 | return nvmeq; |
1119 | ||
1120 | free_cqdma: | |
e75ec752 | 1121 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1122 | nvmeq->cq_dma_addr); |
1123 | free_nvmeq: | |
1124 | kfree(nvmeq); | |
1125 | return NULL; | |
1126 | } | |
1127 | ||
3001082c MW |
1128 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1129 | const char *name) | |
1130 | { | |
58ffacb5 MW |
1131 | if (use_threaded_interrupts) |
1132 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1133 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1134 | name, nvmeq); |
3001082c | 1135 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1136 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1137 | } |
1138 | ||
22404274 | 1139 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1140 | { |
22404274 | 1141 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1142 | |
7be50e93 | 1143 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1144 | nvmeq->sq_tail = 0; |
1145 | nvmeq->cq_head = 0; | |
1146 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1147 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1148 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1149 | dev->online_queues++; |
7be50e93 | 1150 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1151 | } |
1152 | ||
1153 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1154 | { | |
1155 | struct nvme_dev *dev = nvmeq->dev; | |
1156 | int result; | |
3f85d50b | 1157 | |
2b25d981 | 1158 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1159 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1160 | if (result < 0) | |
22404274 | 1161 | return result; |
b60503ba MW |
1162 | |
1163 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1164 | if (result < 0) | |
1165 | goto release_cq; | |
1166 | ||
3193f07b | 1167 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1168 | if (result < 0) |
1169 | goto release_sq; | |
1170 | ||
22404274 | 1171 | nvme_init_queue(nvmeq, qid); |
22404274 | 1172 | return result; |
b60503ba MW |
1173 | |
1174 | release_sq: | |
1175 | adapter_delete_sq(dev, qid); | |
1176 | release_cq: | |
1177 | adapter_delete_cq(dev, qid); | |
22404274 | 1178 | return result; |
b60503ba MW |
1179 | } |
1180 | ||
a4aea562 | 1181 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1182 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1183 | .complete = nvme_complete_rq, |
a4aea562 MB |
1184 | .map_queue = blk_mq_map_queue, |
1185 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1186 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1187 | .init_request = nvme_admin_init_request, |
1188 | .timeout = nvme_timeout, | |
1189 | }; | |
1190 | ||
1191 | static struct blk_mq_ops nvme_mq_ops = { | |
1192 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1193 | .complete = nvme_complete_rq, |
a4aea562 MB |
1194 | .map_queue = blk_mq_map_queue, |
1195 | .init_hctx = nvme_init_hctx, | |
1196 | .init_request = nvme_init_request, | |
1197 | .timeout = nvme_timeout, | |
a0fa9647 | 1198 | .poll = nvme_poll, |
a4aea562 MB |
1199 | }; |
1200 | ||
ea191d2f KB |
1201 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1202 | { | |
1c63dc66 | 1203 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1204 | /* |
1205 | * If the controller was reset during removal, it's possible | |
1206 | * user requests may be waiting on a stopped queue. Start the | |
1207 | * queue to flush these to completion. | |
1208 | */ | |
1209 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); | |
1c63dc66 | 1210 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1211 | blk_mq_free_tag_set(&dev->admin_tagset); |
1212 | } | |
1213 | } | |
1214 | ||
a4aea562 MB |
1215 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1216 | { | |
1c63dc66 | 1217 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1218 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1219 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1220 | |
1221 | /* | |
1222 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1223 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1224 | */ | |
1225 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1226 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1227 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1228 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1229 | dev->admin_tagset.driver_data = dev; |
1230 | ||
1231 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1232 | return -ENOMEM; | |
1233 | ||
1c63dc66 CH |
1234 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1235 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1236 | blk_mq_free_tag_set(&dev->admin_tagset); |
1237 | return -ENOMEM; | |
1238 | } | |
1c63dc66 | 1239 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1240 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1241 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1242 | return -ENODEV; |
1243 | } | |
0fb59cbc | 1244 | } else |
25646264 | 1245 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1246 | |
1247 | return 0; | |
1248 | } | |
1249 | ||
8d85fce7 | 1250 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1251 | { |
ba47e386 | 1252 | int result; |
b60503ba | 1253 | u32 aqa; |
7a67cbea | 1254 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1255 | struct nvme_queue *nvmeq; |
1256 | ||
7a67cbea | 1257 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1258 | NVME_CAP_NSSRC(cap) : 0; |
1259 | ||
7a67cbea CH |
1260 | if (dev->subsystem && |
1261 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1262 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1263 | |
5fd4ce1b | 1264 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1265 | if (result < 0) |
1266 | return result; | |
b60503ba | 1267 | |
a4aea562 | 1268 | nvmeq = dev->queues[0]; |
cd638946 | 1269 | if (!nvmeq) { |
2b25d981 | 1270 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1271 | if (!nvmeq) |
1272 | return -ENOMEM; | |
cd638946 | 1273 | } |
b60503ba MW |
1274 | |
1275 | aqa = nvmeq->q_depth - 1; | |
1276 | aqa |= aqa << 16; | |
1277 | ||
7a67cbea CH |
1278 | writel(aqa, dev->bar + NVME_REG_AQA); |
1279 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1280 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1281 | |
5fd4ce1b | 1282 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1283 | if (result) |
a4aea562 MB |
1284 | goto free_nvmeq; |
1285 | ||
2b25d981 | 1286 | nvmeq->cq_vector = 0; |
3193f07b | 1287 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1288 | if (result) { |
1289 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1290 | goto free_nvmeq; |
758dd7fd | 1291 | } |
025c557a | 1292 | |
b60503ba | 1293 | return result; |
a4aea562 | 1294 | |
a4aea562 MB |
1295 | free_nvmeq: |
1296 | nvme_free_queues(dev, 0); | |
1297 | return result; | |
b60503ba MW |
1298 | } |
1299 | ||
c875a709 GP |
1300 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1301 | { | |
1302 | ||
1303 | /* If true, indicates loss of adapter communication, possibly by a | |
1304 | * NVMe Subsystem reset. | |
1305 | */ | |
1306 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1307 | ||
1308 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
1309 | if (work_busy(&dev->reset_work)) | |
1310 | return false; | |
1311 | ||
1312 | /* We shouldn't reset unless the controller is on fatal error state | |
1313 | * _or_ if we lost the communication with it. | |
1314 | */ | |
1315 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1316 | return false; | |
1317 | ||
1318 | /* If PCI error recovery process is happening, we cannot reset or | |
1319 | * the recovery mechanism will surely fail. | |
1320 | */ | |
1321 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1322 | return false; | |
1323 | ||
1324 | return true; | |
1325 | } | |
1326 | ||
2d55cd5f | 1327 | static void nvme_watchdog_timer(unsigned long data) |
1fa6aead | 1328 | { |
2d55cd5f CH |
1329 | struct nvme_dev *dev = (struct nvme_dev *)data; |
1330 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1fa6aead | 1331 | |
c875a709 GP |
1332 | /* Skip controllers under certain specific conditions. */ |
1333 | if (nvme_should_reset(dev, csts)) { | |
1334 | if (queue_work(nvme_workq, &dev->reset_work)) | |
2d55cd5f CH |
1335 | dev_warn(dev->dev, |
1336 | "Failed status: 0x%x, reset controller.\n", | |
1337 | csts); | |
2d55cd5f | 1338 | return; |
1fa6aead | 1339 | } |
2d55cd5f CH |
1340 | |
1341 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); | |
1fa6aead MW |
1342 | } |
1343 | ||
749941f2 | 1344 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1345 | { |
949928c1 | 1346 | unsigned i, max; |
749941f2 | 1347 | int ret = 0; |
42f61420 | 1348 | |
749941f2 CH |
1349 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1350 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1351 | ret = -ENOMEM; | |
42f61420 | 1352 | break; |
749941f2 CH |
1353 | } |
1354 | } | |
42f61420 | 1355 | |
949928c1 KB |
1356 | max = min(dev->max_qid, dev->queue_count - 1); |
1357 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 CH |
1358 | ret = nvme_create_queue(dev->queues[i], i); |
1359 | if (ret) { | |
2659e57b | 1360 | nvme_free_queues(dev, i); |
42f61420 | 1361 | break; |
2659e57b | 1362 | } |
27e8166c | 1363 | } |
749941f2 CH |
1364 | |
1365 | /* | |
1366 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1367 | * than the desired aount of queues, and even a controller without | |
1368 | * I/O queues an still be used to issue admin commands. This might | |
1369 | * be useful to upgrade a buggy firmware for example. | |
1370 | */ | |
1371 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1372 | } |
1373 | ||
8ffaadf7 JD |
1374 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1375 | { | |
1376 | u64 szu, size, offset; | |
1377 | u32 cmbloc; | |
1378 | resource_size_t bar_size; | |
1379 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1380 | void __iomem *cmb; | |
1381 | dma_addr_t dma_addr; | |
1382 | ||
1383 | if (!use_cmb_sqes) | |
1384 | return NULL; | |
1385 | ||
7a67cbea | 1386 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1387 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1388 | return NULL; | |
1389 | ||
7a67cbea | 1390 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1391 | |
1392 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1393 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1394 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1395 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1396 | ||
1397 | if (offset > bar_size) | |
1398 | return NULL; | |
1399 | ||
1400 | /* | |
1401 | * Controllers may support a CMB size larger than their BAR, | |
1402 | * for example, due to being behind a bridge. Reduce the CMB to | |
1403 | * the reported size of the BAR | |
1404 | */ | |
1405 | if (size > bar_size - offset) | |
1406 | size = bar_size - offset; | |
1407 | ||
1408 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1409 | cmb = ioremap_wc(dma_addr, size); | |
1410 | if (!cmb) | |
1411 | return NULL; | |
1412 | ||
1413 | dev->cmb_dma_addr = dma_addr; | |
1414 | dev->cmb_size = size; | |
1415 | return cmb; | |
1416 | } | |
1417 | ||
1418 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1419 | { | |
1420 | if (dev->cmb) { | |
1421 | iounmap(dev->cmb); | |
1422 | dev->cmb = NULL; | |
1423 | } | |
1424 | } | |
1425 | ||
9d713c2b KB |
1426 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1427 | { | |
b80d5ccc | 1428 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1429 | } |
1430 | ||
8d85fce7 | 1431 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1432 | { |
a4aea562 | 1433 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1434 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1435 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1436 | |
42f61420 | 1437 | nr_io_queues = num_possible_cpus(); |
9a0be7ab CH |
1438 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1439 | if (result < 0) | |
1b23484b | 1440 | return result; |
9a0be7ab CH |
1441 | |
1442 | /* | |
1443 | * Degraded controllers might return an error when setting the queue | |
1444 | * count. We still want to be able to bring them online and offer | |
1445 | * access to the admin queue, as that might be only way to fix them up. | |
1446 | */ | |
1447 | if (result > 0) { | |
1b3c47c1 SG |
1448 | dev_err(dev->ctrl.device, |
1449 | "Could not set queue count (%d)\n", result); | |
788e15ab | 1450 | return 0; |
9a0be7ab | 1451 | } |
b60503ba | 1452 | |
8ffaadf7 JD |
1453 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1454 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1455 | sizeof(struct nvme_command)); | |
1456 | if (result > 0) | |
1457 | dev->q_depth = result; | |
1458 | else | |
1459 | nvme_release_cmb(dev); | |
1460 | } | |
1461 | ||
9d713c2b KB |
1462 | size = db_bar_size(dev, nr_io_queues); |
1463 | if (size > 8192) { | |
f1938f6e | 1464 | iounmap(dev->bar); |
9d713c2b KB |
1465 | do { |
1466 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1467 | if (dev->bar) | |
1468 | break; | |
1469 | if (!--nr_io_queues) | |
1470 | return -ENOMEM; | |
1471 | size = db_bar_size(dev, nr_io_queues); | |
1472 | } while (1); | |
7a67cbea | 1473 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1474 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1475 | } |
1476 | ||
9d713c2b | 1477 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1478 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1479 | |
e32efbfc JA |
1480 | /* |
1481 | * If we enable msix early due to not intx, disable it again before | |
1482 | * setting up the full range we need. | |
1483 | */ | |
788e15ab KB |
1484 | if (pdev->msi_enabled) |
1485 | pci_disable_msi(pdev); | |
1486 | else if (pdev->msix_enabled) | |
e32efbfc JA |
1487 | pci_disable_msix(pdev); |
1488 | ||
be577fab | 1489 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1490 | dev->entry[i].entry = i; |
be577fab AG |
1491 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1492 | if (vecs < 0) { | |
1493 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1494 | if (vecs < 0) { | |
1495 | vecs = 1; | |
1496 | } else { | |
1497 | for (i = 0; i < vecs; i++) | |
1498 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1499 | } |
1500 | } | |
1501 | ||
063a8096 MW |
1502 | /* |
1503 | * Should investigate if there's a performance win from allocating | |
1504 | * more queues than interrupt vectors; it might allow the submission | |
1505 | * path to scale better, even if the receive path is limited by the | |
1506 | * number of interrupts. | |
1507 | */ | |
1508 | nr_io_queues = vecs; | |
42f61420 | 1509 | dev->max_qid = nr_io_queues; |
063a8096 | 1510 | |
3193f07b | 1511 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1512 | if (result) { |
1513 | adminq->cq_vector = -1; | |
22404274 | 1514 | goto free_queues; |
758dd7fd | 1515 | } |
749941f2 | 1516 | return nvme_create_io_queues(dev); |
b60503ba | 1517 | |
22404274 | 1518 | free_queues: |
a1a5ef99 | 1519 | nvme_free_queues(dev, 1); |
22404274 | 1520 | return result; |
b60503ba MW |
1521 | } |
1522 | ||
bda4e0fb | 1523 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
a5768aa8 | 1524 | { |
bda4e0fb KB |
1525 | struct nvme_queue *nvmeq; |
1526 | int i; | |
a5768aa8 | 1527 | |
bda4e0fb KB |
1528 | for (i = 0; i < dev->online_queues; i++) { |
1529 | nvmeq = dev->queues[i]; | |
a5768aa8 | 1530 | |
bda4e0fb KB |
1531 | if (!nvmeq->tags || !(*nvmeq->tags)) |
1532 | continue; | |
a5768aa8 | 1533 | |
bda4e0fb KB |
1534 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, |
1535 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
a5768aa8 | 1536 | } |
a5768aa8 KB |
1537 | } |
1538 | ||
a5768aa8 | 1539 | static void nvme_dev_scan(struct work_struct *work) |
a5768aa8 | 1540 | { |
a5768aa8 | 1541 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); |
a5768aa8 KB |
1542 | |
1543 | if (!dev->tagset.tags) | |
1544 | return; | |
5bae7f73 | 1545 | nvme_scan_namespaces(&dev->ctrl); |
bda4e0fb | 1546 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
1547 | } |
1548 | ||
db3cbfff | 1549 | static void nvme_del_queue_end(struct request *req, int error) |
a5768aa8 | 1550 | { |
db3cbfff | 1551 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1552 | |
db3cbfff KB |
1553 | blk_mq_free_request(req); |
1554 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1555 | } |
1556 | ||
db3cbfff | 1557 | static void nvme_del_cq_end(struct request *req, int error) |
a5768aa8 | 1558 | { |
db3cbfff | 1559 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1560 | |
db3cbfff KB |
1561 | if (!error) { |
1562 | unsigned long flags; | |
1563 | ||
2e39e0f6 ML |
1564 | /* |
1565 | * We might be called with the AQ q_lock held | |
1566 | * and the I/O queue q_lock should always | |
1567 | * nest inside the AQ one. | |
1568 | */ | |
1569 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1570 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1571 | nvme_process_cq(nvmeq); |
1572 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1573 | } |
db3cbfff KB |
1574 | |
1575 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1576 | } |
1577 | ||
db3cbfff | 1578 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1579 | { |
db3cbfff KB |
1580 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1581 | struct request *req; | |
1582 | struct nvme_command cmd; | |
bda4e0fb | 1583 | |
db3cbfff KB |
1584 | memset(&cmd, 0, sizeof(cmd)); |
1585 | cmd.delete_queue.opcode = opcode; | |
1586 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1587 | |
db3cbfff KB |
1588 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); |
1589 | if (IS_ERR(req)) | |
1590 | return PTR_ERR(req); | |
bda4e0fb | 1591 | |
db3cbfff KB |
1592 | req->timeout = ADMIN_TIMEOUT; |
1593 | req->end_io_data = nvmeq; | |
1594 | ||
1595 | blk_execute_rq_nowait(q, NULL, req, false, | |
1596 | opcode == nvme_admin_delete_cq ? | |
1597 | nvme_del_cq_end : nvme_del_queue_end); | |
1598 | return 0; | |
bda4e0fb KB |
1599 | } |
1600 | ||
db3cbfff | 1601 | static void nvme_disable_io_queues(struct nvme_dev *dev) |
a5768aa8 | 1602 | { |
db3cbfff KB |
1603 | int pass; |
1604 | unsigned long timeout; | |
1605 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1606 | |
db3cbfff KB |
1607 | for (pass = 0; pass < 2; pass++) { |
1608 | int sent = 0, i = dev->queue_count - 1; | |
1609 | ||
1610 | reinit_completion(&dev->ioq_wait); | |
1611 | retry: | |
1612 | timeout = ADMIN_TIMEOUT; | |
1613 | for (; i > 0; i--) { | |
1614 | struct nvme_queue *nvmeq = dev->queues[i]; | |
1615 | ||
1616 | if (!pass) | |
1617 | nvme_suspend_queue(nvmeq); | |
1618 | if (nvme_delete_queue(nvmeq, opcode)) | |
1619 | break; | |
1620 | ++sent; | |
1621 | } | |
1622 | while (sent--) { | |
1623 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1624 | if (timeout == 0) | |
1625 | return; | |
1626 | if (i) | |
1627 | goto retry; | |
1628 | } | |
1629 | opcode = nvme_admin_delete_cq; | |
1630 | } | |
a5768aa8 KB |
1631 | } |
1632 | ||
422ef0c7 MW |
1633 | /* |
1634 | * Return: error value if an error occurred setting up the queues or calling | |
1635 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1636 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1637 | * failures should be reported. | |
1638 | */ | |
8d85fce7 | 1639 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1640 | { |
5bae7f73 | 1641 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1642 | dev->tagset.ops = &nvme_mq_ops; |
1643 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1644 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1645 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1646 | dev->tagset.queue_depth = | |
a4aea562 | 1647 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1648 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1649 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1650 | dev->tagset.driver_data = dev; | |
b60503ba | 1651 | |
ffe7704d KB |
1652 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1653 | return 0; | |
5bae7f73 | 1654 | dev->ctrl.tagset = &dev->tagset; |
949928c1 KB |
1655 | } else { |
1656 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1657 | ||
1658 | /* Free previously allocated queues that are no longer usable */ | |
1659 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1660 | } |
949928c1 | 1661 | |
646017a6 | 1662 | nvme_queue_scan(dev); |
e1e5e564 | 1663 | return 0; |
b60503ba MW |
1664 | } |
1665 | ||
b00a726a | 1666 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1667 | { |
42f61420 | 1668 | u64 cap; |
b00a726a | 1669 | int result = -ENOMEM; |
e75ec752 | 1670 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1671 | |
1672 | if (pci_enable_device_mem(pdev)) | |
1673 | return result; | |
1674 | ||
0877cb0d | 1675 | pci_set_master(pdev); |
0877cb0d | 1676 | |
e75ec752 CH |
1677 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1678 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1679 | goto disable; |
0877cb0d | 1680 | |
7a67cbea | 1681 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1682 | result = -ENODEV; |
b00a726a | 1683 | goto disable; |
0e53d180 | 1684 | } |
e32efbfc JA |
1685 | |
1686 | /* | |
788e15ab KB |
1687 | * Some devices and/or platforms don't advertise or work with INTx |
1688 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1689 | * adjust this later. | |
e32efbfc | 1690 | */ |
788e15ab KB |
1691 | if (pci_enable_msix(pdev, dev->entry, 1)) { |
1692 | pci_enable_msi(pdev); | |
1693 | dev->entry[0].vector = pdev->irq; | |
1694 | } | |
1695 | ||
1696 | if (!dev->entry[0].vector) { | |
1697 | result = -ENODEV; | |
1698 | goto disable; | |
e32efbfc JA |
1699 | } |
1700 | ||
7a67cbea CH |
1701 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1702 | ||
42f61420 KB |
1703 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1704 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1705 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1706 | |
1707 | /* | |
1708 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1709 | * some MacBook7,1 to avoid controller resets and data loss. | |
1710 | */ | |
1711 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1712 | dev->q_depth = 2; | |
1713 | dev_warn(dev->dev, "detected Apple NVMe controller, set " | |
1714 | "queue depth=%u to work around controller resets\n", | |
1715 | dev->q_depth); | |
1716 | } | |
1717 | ||
7a67cbea | 1718 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) |
8ffaadf7 | 1719 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1720 | |
a0a3408e KB |
1721 | pci_enable_pcie_error_reporting(pdev); |
1722 | pci_save_state(pdev); | |
0877cb0d KB |
1723 | return 0; |
1724 | ||
1725 | disable: | |
0877cb0d KB |
1726 | pci_disable_device(pdev); |
1727 | return result; | |
1728 | } | |
1729 | ||
1730 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1731 | { |
1732 | if (dev->bar) | |
1733 | iounmap(dev->bar); | |
1734 | pci_release_regions(to_pci_dev(dev->dev)); | |
1735 | } | |
1736 | ||
1737 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1738 | { |
e75ec752 CH |
1739 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1740 | ||
1741 | if (pdev->msi_enabled) | |
1742 | pci_disable_msi(pdev); | |
1743 | else if (pdev->msix_enabled) | |
1744 | pci_disable_msix(pdev); | |
0877cb0d | 1745 | |
a0a3408e KB |
1746 | if (pci_is_enabled(pdev)) { |
1747 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1748 | pci_disable_device(pdev); |
4d115420 | 1749 | } |
4d115420 KB |
1750 | } |
1751 | ||
a5cdb68c | 1752 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1753 | { |
22404274 | 1754 | int i; |
7c1b2450 | 1755 | u32 csts = -1; |
22404274 | 1756 | |
2d55cd5f | 1757 | del_timer_sync(&dev->watchdog_timer); |
1fa6aead | 1758 | |
77bf25ea | 1759 | mutex_lock(&dev->shutdown_lock); |
b00a726a | 1760 | if (pci_is_enabled(to_pci_dev(dev->dev))) { |
25646264 | 1761 | nvme_stop_queues(&dev->ctrl); |
7a67cbea | 1762 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1763 | } |
7c1b2450 | 1764 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 1765 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 1766 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 1767 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
1768 | } |
1769 | } else { | |
1770 | nvme_disable_io_queues(dev); | |
a5cdb68c | 1771 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1772 | } |
b00a726a | 1773 | nvme_pci_disable(dev); |
07836e65 | 1774 | |
82b4552b SG |
1775 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_io, dev); |
1776 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_io, dev); | |
77bf25ea | 1777 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
1778 | } |
1779 | ||
091b6092 MW |
1780 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1781 | { | |
e75ec752 | 1782 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1783 | PAGE_SIZE, PAGE_SIZE, 0); |
1784 | if (!dev->prp_page_pool) | |
1785 | return -ENOMEM; | |
1786 | ||
99802a7a | 1787 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1788 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1789 | 256, 256, 0); |
1790 | if (!dev->prp_small_pool) { | |
1791 | dma_pool_destroy(dev->prp_page_pool); | |
1792 | return -ENOMEM; | |
1793 | } | |
091b6092 MW |
1794 | return 0; |
1795 | } | |
1796 | ||
1797 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1798 | { | |
1799 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1800 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1801 | } |
1802 | ||
1673f1f0 | 1803 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1804 | { |
1673f1f0 | 1805 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1806 | |
e75ec752 | 1807 | put_device(dev->dev); |
4af0e21c KB |
1808 | if (dev->tagset.tags) |
1809 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1810 | if (dev->ctrl.admin_q) |
1811 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
1812 | kfree(dev->queues); |
1813 | kfree(dev->entry); | |
1814 | kfree(dev); | |
1815 | } | |
1816 | ||
f58944e2 KB |
1817 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
1818 | { | |
237045fc | 1819 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
1820 | |
1821 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 1822 | nvme_dev_disable(dev, false); |
f58944e2 KB |
1823 | if (!schedule_work(&dev->remove_work)) |
1824 | nvme_put_ctrl(&dev->ctrl); | |
1825 | } | |
1826 | ||
fd634f41 | 1827 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 1828 | { |
fd634f41 | 1829 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
f58944e2 | 1830 | int result = -ENODEV; |
5e82e952 | 1831 | |
bb8d261e | 1832 | if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING)) |
fd634f41 | 1833 | goto out; |
5e82e952 | 1834 | |
fd634f41 CH |
1835 | /* |
1836 | * If we're called to reset a live controller first shut it down before | |
1837 | * moving on. | |
1838 | */ | |
b00a726a | 1839 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 1840 | nvme_dev_disable(dev, false); |
5e82e952 | 1841 | |
bb8d261e CH |
1842 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) |
1843 | goto out; | |
f0b50732 | 1844 | |
b00a726a | 1845 | result = nvme_pci_enable(dev); |
f0b50732 | 1846 | if (result) |
3cf519b5 | 1847 | goto out; |
f0b50732 KB |
1848 | |
1849 | result = nvme_configure_admin_queue(dev); | |
1850 | if (result) | |
f58944e2 | 1851 | goto out; |
f0b50732 | 1852 | |
a4aea562 | 1853 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1854 | result = nvme_alloc_admin_tags(dev); |
1855 | if (result) | |
f58944e2 | 1856 | goto out; |
b9afca3e | 1857 | |
ce4541f4 CH |
1858 | result = nvme_init_identify(&dev->ctrl); |
1859 | if (result) | |
f58944e2 | 1860 | goto out; |
ce4541f4 | 1861 | |
f0b50732 | 1862 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1863 | if (result) |
f58944e2 | 1864 | goto out; |
f0b50732 | 1865 | |
21f033f7 KB |
1866 | /* |
1867 | * A controller that can not execute IO typically requires user | |
1868 | * intervention to correct. For such degraded controllers, the driver | |
1869 | * should not submit commands the user did not request, so skip | |
1870 | * registering for asynchronous event notification on this condition. | |
1871 | */ | |
1872 | if (dev->online_queues > 1) { | |
1873 | dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS; | |
1874 | queue_work(nvme_workq, &dev->async_work); | |
1875 | } | |
3cf519b5 | 1876 | |
2d55cd5f | 1877 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); |
3cf519b5 | 1878 | |
2659e57b CH |
1879 | /* |
1880 | * Keep the controller around but remove all namespaces if we don't have | |
1881 | * any working I/O queue. | |
1882 | */ | |
3cf519b5 | 1883 | if (dev->online_queues < 2) { |
1b3c47c1 | 1884 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 1885 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 1886 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1887 | } else { |
25646264 | 1888 | nvme_start_queues(&dev->ctrl); |
3cf519b5 CH |
1889 | nvme_dev_add(dev); |
1890 | } | |
1891 | ||
bb8d261e CH |
1892 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
1893 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
1894 | goto out; | |
1895 | } | |
3cf519b5 | 1896 | return; |
f0b50732 | 1897 | |
3cf519b5 | 1898 | out: |
f58944e2 | 1899 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
1900 | } |
1901 | ||
5c8809e6 | 1902 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1903 | { |
5c8809e6 | 1904 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1905 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 1906 | |
69d9a99c | 1907 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 1908 | if (pci_get_drvdata(pdev)) |
c81f4975 | 1909 | pci_stop_and_remove_bus_device_locked(pdev); |
1673f1f0 | 1910 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
1911 | } |
1912 | ||
4cc06521 | 1913 | static int nvme_reset(struct nvme_dev *dev) |
9a6b9458 | 1914 | { |
1c63dc66 | 1915 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 | 1916 | return -ENODEV; |
ffe7704d | 1917 | |
846cc05f CH |
1918 | if (!queue_work(nvme_workq, &dev->reset_work)) |
1919 | return -EBUSY; | |
ffe7704d | 1920 | |
846cc05f | 1921 | flush_work(&dev->reset_work); |
846cc05f | 1922 | return 0; |
9a6b9458 KB |
1923 | } |
1924 | ||
1c63dc66 | 1925 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 1926 | { |
1c63dc66 | 1927 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 1928 | return 0; |
9ca97374 TH |
1929 | } |
1930 | ||
5fd4ce1b | 1931 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 1932 | { |
5fd4ce1b CH |
1933 | writel(val, to_nvme_dev(ctrl)->bar + off); |
1934 | return 0; | |
1935 | } | |
4cc06521 | 1936 | |
7fd8930f CH |
1937 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
1938 | { | |
1939 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
1940 | return 0; | |
4cc06521 KB |
1941 | } |
1942 | ||
f3ca80fc CH |
1943 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
1944 | { | |
1945 | return nvme_reset(to_nvme_dev(ctrl)); | |
4cc06521 | 1946 | } |
f3ca80fc | 1947 | |
1c63dc66 | 1948 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
e439bb12 | 1949 | .module = THIS_MODULE, |
1c63dc66 | 1950 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 1951 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 1952 | .reg_read64 = nvme_pci_reg_read64, |
f3ca80fc | 1953 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 1954 | .free_ctrl = nvme_pci_free_ctrl, |
1c63dc66 | 1955 | }; |
4cc06521 | 1956 | |
b00a726a KB |
1957 | static int nvme_dev_map(struct nvme_dev *dev) |
1958 | { | |
1959 | int bars; | |
1960 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1961 | ||
1962 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
1963 | if (!bars) | |
1964 | return -ENODEV; | |
1965 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1966 | return -ENODEV; | |
1967 | ||
1968 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
1969 | if (!dev->bar) | |
1970 | goto release; | |
1971 | ||
1972 | return 0; | |
1973 | release: | |
1974 | pci_release_regions(pdev); | |
1975 | return -ENODEV; | |
1976 | } | |
1977 | ||
8d85fce7 | 1978 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 1979 | { |
a4aea562 | 1980 | int node, result = -ENOMEM; |
b60503ba MW |
1981 | struct nvme_dev *dev; |
1982 | ||
a4aea562 MB |
1983 | node = dev_to_node(&pdev->dev); |
1984 | if (node == NUMA_NO_NODE) | |
1985 | set_dev_node(&pdev->dev, 0); | |
1986 | ||
1987 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
1988 | if (!dev) |
1989 | return -ENOMEM; | |
a4aea562 MB |
1990 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
1991 | GFP_KERNEL, node); | |
b60503ba MW |
1992 | if (!dev->entry) |
1993 | goto free; | |
a4aea562 MB |
1994 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
1995 | GFP_KERNEL, node); | |
b60503ba MW |
1996 | if (!dev->queues) |
1997 | goto free; | |
1998 | ||
e75ec752 | 1999 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2000 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2001 | |
b00a726a KB |
2002 | result = nvme_dev_map(dev); |
2003 | if (result) | |
2004 | goto free; | |
2005 | ||
f3ca80fc | 2006 | INIT_WORK(&dev->scan_work, nvme_dev_scan); |
f3ca80fc | 2007 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 2008 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
9396dec9 | 2009 | INIT_WORK(&dev->async_work, nvme_async_event_work); |
2d55cd5f CH |
2010 | setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, |
2011 | (unsigned long)dev); | |
77bf25ea | 2012 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2013 | init_completion(&dev->ioq_wait); |
b60503ba | 2014 | |
091b6092 MW |
2015 | result = nvme_setup_prp_pools(dev); |
2016 | if (result) | |
a96d4f5c | 2017 | goto put_pci; |
4cc06521 | 2018 | |
f3ca80fc CH |
2019 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2020 | id->driver_data); | |
4cc06521 | 2021 | if (result) |
2e1d8448 | 2022 | goto release_pools; |
740216fc | 2023 | |
1b3c47c1 SG |
2024 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2025 | ||
92f7a162 | 2026 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
2027 | return 0; |
2028 | ||
0877cb0d | 2029 | release_pools: |
091b6092 | 2030 | nvme_release_prp_pools(dev); |
a96d4f5c | 2031 | put_pci: |
e75ec752 | 2032 | put_device(dev->dev); |
b00a726a | 2033 | nvme_dev_unmap(dev); |
b60503ba MW |
2034 | free: |
2035 | kfree(dev->queues); | |
2036 | kfree(dev->entry); | |
2037 | kfree(dev); | |
2038 | return result; | |
2039 | } | |
2040 | ||
f0d54a54 KB |
2041 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2042 | { | |
a6739479 | 2043 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2044 | |
a6739479 | 2045 | if (prepare) |
a5cdb68c | 2046 | nvme_dev_disable(dev, false); |
a6739479 | 2047 | else |
92f7a162 | 2048 | queue_work(nvme_workq, &dev->reset_work); |
f0d54a54 KB |
2049 | } |
2050 | ||
09ece142 KB |
2051 | static void nvme_shutdown(struct pci_dev *pdev) |
2052 | { | |
2053 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2054 | nvme_dev_disable(dev, true); |
09ece142 KB |
2055 | } |
2056 | ||
f58944e2 KB |
2057 | /* |
2058 | * The driver's remove may be called on a device in a partially initialized | |
2059 | * state. This function must not have any dependencies on the device state in | |
2060 | * order to proceed. | |
2061 | */ | |
8d85fce7 | 2062 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2063 | { |
2064 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2065 | |
2d55cd5f | 2066 | del_timer_sync(&dev->watchdog_timer); |
9a6b9458 | 2067 | |
bb8d261e CH |
2068 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2069 | ||
9a6b9458 | 2070 | pci_set_drvdata(pdev, NULL); |
9396dec9 | 2071 | flush_work(&dev->async_work); |
a5768aa8 | 2072 | flush_work(&dev->scan_work); |
5bae7f73 | 2073 | nvme_remove_namespaces(&dev->ctrl); |
53029b04 | 2074 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 2075 | nvme_dev_disable(dev, true); |
ff23a2a1 | 2076 | flush_work(&dev->reset_work); |
a4aea562 | 2077 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2078 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2079 | nvme_release_cmb(dev); |
9a6b9458 | 2080 | nvme_release_prp_pools(dev); |
b00a726a | 2081 | nvme_dev_unmap(dev); |
1673f1f0 | 2082 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2083 | } |
2084 | ||
671a6018 | 2085 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2086 | static int nvme_suspend(struct device *dev) |
2087 | { | |
2088 | struct pci_dev *pdev = to_pci_dev(dev); | |
2089 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2090 | ||
a5cdb68c | 2091 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2092 | return 0; |
2093 | } | |
2094 | ||
2095 | static int nvme_resume(struct device *dev) | |
2096 | { | |
2097 | struct pci_dev *pdev = to_pci_dev(dev); | |
2098 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2099 | |
92f7a162 | 2100 | queue_work(nvme_workq, &ndev->reset_work); |
9a6b9458 | 2101 | return 0; |
cd638946 | 2102 | } |
671a6018 | 2103 | #endif |
cd638946 KB |
2104 | |
2105 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2106 | |
a0a3408e KB |
2107 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2108 | pci_channel_state_t state) | |
2109 | { | |
2110 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2111 | ||
2112 | /* | |
2113 | * A frozen channel requires a reset. When detected, this method will | |
2114 | * shutdown the controller to quiesce. The controller will be restarted | |
2115 | * after the slot reset through driver's slot_reset callback. | |
2116 | */ | |
1b3c47c1 | 2117 | dev_warn(dev->ctrl.device, "error detected: state:%d\n", state); |
a0a3408e KB |
2118 | switch (state) { |
2119 | case pci_channel_io_normal: | |
2120 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2121 | case pci_channel_io_frozen: | |
a5cdb68c | 2122 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2123 | return PCI_ERS_RESULT_NEED_RESET; |
2124 | case pci_channel_io_perm_failure: | |
2125 | return PCI_ERS_RESULT_DISCONNECT; | |
2126 | } | |
2127 | return PCI_ERS_RESULT_NEED_RESET; | |
2128 | } | |
2129 | ||
2130 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2131 | { | |
2132 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2133 | ||
1b3c47c1 | 2134 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e KB |
2135 | pci_restore_state(pdev); |
2136 | queue_work(nvme_workq, &dev->reset_work); | |
2137 | return PCI_ERS_RESULT_RECOVERED; | |
2138 | } | |
2139 | ||
2140 | static void nvme_error_resume(struct pci_dev *pdev) | |
2141 | { | |
2142 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2143 | } | |
2144 | ||
1d352035 | 2145 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2146 | .error_detected = nvme_error_detected, |
b60503ba MW |
2147 | .slot_reset = nvme_slot_reset, |
2148 | .resume = nvme_error_resume, | |
f0d54a54 | 2149 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2150 | }; |
2151 | ||
2152 | /* Move to pci_ids.h later */ | |
2153 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2154 | ||
6eb0d698 | 2155 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2156 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 KB |
2157 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
2158 | NVME_QUIRK_DISCARD_ZEROES, }, | |
540c801c KB |
2159 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2160 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
b60503ba | 2161 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2162 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2163 | { 0, } |
2164 | }; | |
2165 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2166 | ||
2167 | static struct pci_driver nvme_driver = { | |
2168 | .name = "nvme", | |
2169 | .id_table = nvme_id_table, | |
2170 | .probe = nvme_probe, | |
8d85fce7 | 2171 | .remove = nvme_remove, |
09ece142 | 2172 | .shutdown = nvme_shutdown, |
cd638946 KB |
2173 | .driver = { |
2174 | .pm = &nvme_dev_pm_ops, | |
2175 | }, | |
b60503ba MW |
2176 | .err_handler = &nvme_err_handler, |
2177 | }; | |
2178 | ||
2179 | static int __init nvme_init(void) | |
2180 | { | |
0ac13140 | 2181 | int result; |
1fa6aead | 2182 | |
92f7a162 | 2183 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2184 | if (!nvme_workq) |
b9afca3e | 2185 | return -ENOMEM; |
9a6b9458 | 2186 | |
f3db22fe KB |
2187 | result = pci_register_driver(&nvme_driver); |
2188 | if (result) | |
576d55d6 | 2189 | destroy_workqueue(nvme_workq); |
b60503ba MW |
2190 | return result; |
2191 | } | |
2192 | ||
2193 | static void __exit nvme_exit(void) | |
2194 | { | |
2195 | pci_unregister_driver(&nvme_driver); | |
9a6b9458 | 2196 | destroy_workqueue(nvme_workq); |
21bd78bc | 2197 | _nvme_check_size(); |
b60503ba MW |
2198 | } |
2199 | ||
2200 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2201 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2202 | MODULE_VERSION("1.0"); |
b60503ba MW |
2203 | module_init(nvme_init); |
2204 | module_exit(nvme_exit); |