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target-i386: Attach ICC bus to CPU on its creation
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf
EH		 26#include "sysemu/cpus.h"
27#include "topology.h"
c6dc6f63 28
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
7b1b5d19 33#include "qapi/visitor.h"
9c17d615 34#include "sysemu/arch_init.h"
71ad61d3 35
28f52cc0
VR		 36#include "hyperv.h"
37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
62fc403f 44#include "hw/cpu/icc_bus.h"
bdeec802 45#ifndef CONFIG_USER_ONLY
0d09e41a 46#include "hw/xen/xen.h"
bdeec802 47#include "hw/sysbus.h"
0d09e41a 48#include "hw/i386/apic_internal.h"
bdeec802
IM		 49#endif
50
99b88a17
IM		 51static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
52 uint32_t vendor2, uint32_t vendor3)
53{
54 int i;
55 for (i = 0; i < 4; i++) {
56 dst[i] = vendor1 >> (8 * i);
57 dst[i + 4] = vendor2 >> (8 * i);
58 dst[i + 8] = vendor3 >> (8 * i);
59 }
60 dst[CPUID_VENDOR_SZ] = '\0';
61}
62
c6dc6f63
AP		 63/* feature flags taken from "Intel Processor Identification and the CPUID
64 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
65 * between feature naming conventions, aliases may be added.
66 */
67static const char *feature_name[] = {
68 "fpu", "vme", "de", "pse",
69 "tsc", "msr", "pae", "mce",
70 "cx8", "apic", NULL, "sep",
71 "mtrr", "pge", "mca", "cmov",
72 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
73 NULL, "ds" /* Intel dts */, "acpi", "mmx",
74 "fxsr", "sse", "sse2", "ss",
75 "ht" /* Intel htt */, "tm", "ia64", "pbe",
76};
77static const char *ext_feature_name[] = {
f370be3c 78 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 79 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 80 "tm2", "ssse3", "cid", NULL,
e117f772 81 "fma", "cx16", "xtpr", "pdcm",
434acb81 82 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 83 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 84 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 85 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 86};
3b671a40
EH		 87/* Feature names that are already defined on feature_name[] but are set on
88 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
89 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
90 * if and only if CPU vendor is AMD.
91 */
c6dc6f63 92static const char *ext2_feature_name[] = {
3b671a40
EH		 93 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
94 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
95 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
96 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
97 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
98 "nx|xd", NULL, "mmxext", NULL /* mmx */,
99 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 100 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 101};
102static const char *ext3_feature_name[] = {
103 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
104 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 105 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 106 "skinit", "wdt", NULL, "lwp",
107 "fma4", "tce", NULL, "nodeid_msr",
108 NULL, "tbm", "topoext", "perfctr_core",
109 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 110 NULL, NULL, NULL, NULL,
111};
112
89e49c8b
EH		 113static const char *ext4_feature_name[] = {
114 NULL, NULL, "xstore", "xstore-en",
115 NULL, NULL, "xcrypt", "xcrypt-en",
116 "ace2", "ace2-en", "phe", "phe-en",
117 "pmm", "pmm-en", NULL, NULL,
118 NULL, NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL,
120 NULL, NULL, NULL, NULL,
121 NULL, NULL, NULL, NULL,
122};
123
c6dc6f63 124static const char *kvm_feature_name[] = {
c3d39807
DS		 125 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
126 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131 NULL, NULL, NULL, NULL,
132 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 133};
134
296acb64
JR		 135static const char *svm_feature_name[] = {
136 "npt", "lbrv", "svm_lock", "nrip_save",
137 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
138 NULL, NULL, "pause_filter", NULL,
139 "pfthreshold", NULL, NULL, NULL,
140 NULL, NULL, NULL, NULL,
141 NULL, NULL, NULL, NULL,
142 NULL, NULL, NULL, NULL,
143 NULL, NULL, NULL, NULL,
144};
145
a9321a4d 146static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 147 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
148 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 149 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 150 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
151};
152
5ef57876
EH		 153typedef struct FeatureWordInfo {
154 const char **feat_names;
bffd67b0
EH		 155 uint32_t cpuid_eax; /* Input EAX for CPUID */
156 int cpuid_reg; /* R_* register constant */
5ef57876
EH		 157} FeatureWordInfo;
158
159static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 160 [FEAT_1_EDX] = {
161 .feat_names = feature_name,
162 .cpuid_eax = 1, .cpuid_reg = R_EDX,
163 },
164 [FEAT_1_ECX] = {
165 .feat_names = ext_feature_name,
166 .cpuid_eax = 1, .cpuid_reg = R_ECX,
167 },
168 [FEAT_8000_0001_EDX] = {
169 .feat_names = ext2_feature_name,
170 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
171 },
172 [FEAT_8000_0001_ECX] = {
173 .feat_names = ext3_feature_name,
174 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
175 },
89e49c8b
EH		 176 [FEAT_C000_0001_EDX] = {
177 .feat_names = ext4_feature_name,
178 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
179 },
bffd67b0
EH		 180 [FEAT_KVM] = {
181 .feat_names = kvm_feature_name,
182 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
183 },
184 [FEAT_SVM] = {
185 .feat_names = svm_feature_name,
186 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
187 },
188 [FEAT_7_0_EBX] = {
189 .feat_names = cpuid_7_0_ebx_feature_name,
190 .cpuid_eax = 7, .cpuid_reg = R_EBX,
191 },
5ef57876
EH		 192};
193
8b4beddc
EH		 194const char *get_register_name_32(unsigned int reg)
195{
196 static const char *reg_names[CPU_NB_REGS32] = {
197 [R_EAX] = "EAX",
198 [R_ECX] = "ECX",
199 [R_EDX] = "EDX",
200 [R_EBX] = "EBX",
201 [R_ESP] = "ESP",
202 [R_EBP] = "EBP",
203 [R_ESI] = "ESI",
204 [R_EDI] = "EDI",
205 };
206
207 if (reg > CPU_NB_REGS32) {
208 return NULL;
209 }
210 return reg_names[reg];
211}
212
c6dc6f63
AP		 213/* collects per-function cpuid data
214 */
215typedef struct model_features_t {
216 uint32_t *guest_feat;
217 uint32_t *host_feat;
bffd67b0 218 FeatureWord feat_word;
8b4beddc 219} model_features_t;
c6dc6f63
AP		 220
221int check_cpuid = 0;
222int enforce_cpuid = 0;
223
dc59944b
MT		 224static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
225 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 226 (1 << KVM_FEATURE_CLOCKSOURCE2) |
227 (1 << KVM_FEATURE_ASYNC_PF) |
228 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 229 (1 << KVM_FEATURE_PV_EOI) |
dc59944b 230 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
dc59944b 231
29694758 232void disable_kvm_pv_eoi(void)
dc59944b 233{
29694758 234 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
dc59944b
MT		 235}
236
bb44e0d1
JK		 237void host_cpuid(uint32_t function, uint32_t count,
238 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 239{
240#if defined(CONFIG_KVM)
a1fd24af
AL		 241 uint32_t vec[4];
242
243#ifdef __x86_64__
244 asm volatile("cpuid"
245 : "=a"(vec[0]), "=b"(vec[1]),
246 "=c"(vec[2]), "=d"(vec[3])
247 : "0"(function), "c"(count) : "cc");
248#else
249 asm volatile("pusha \n\t"
250 "cpuid \n\t"
251 "mov %%eax, 0(%2) \n\t"
252 "mov %%ebx, 4(%2) \n\t"
253 "mov %%ecx, 8(%2) \n\t"
254 "mov %%edx, 12(%2) \n\t"
255 "popa"
256 : : "a"(function), "c"(count), "S"(vec)
257 : "memory", "cc");
258#endif
259
bdde476a 260 if (eax)
a1fd24af 261 *eax = vec[0];
bdde476a 262 if (ebx)
a1fd24af 263 *ebx = vec[1];
bdde476a 264 if (ecx)
a1fd24af 265 *ecx = vec[2];
bdde476a 266 if (edx)
a1fd24af 267 *edx = vec[3];
bdde476a
AP		 268#endif
269}
c6dc6f63
AP		 270
271#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
272
273/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
274 * a substring. ex if !NULL points to the first char after a substring,
275 * otherwise the string is assumed to sized by a terminating nul.
276 * Return lexical ordering of *s1:*s2.
277 */
278static int sstrcmp(const char *s1, const char *e1, const char *s2,
279 const char *e2)
280{
281 for (;;) {
282 if (!*s1 || !*s2 || *s1 != *s2)
283 return (*s1 - *s2);
284 ++s1, ++s2;
285 if (s1 == e1 && s2 == e2)
286 return (0);
287 else if (s1 == e1)
288 return (*s2);
289 else if (s2 == e2)
290 return (*s1);
291 }
292}
293
294/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
295 * '|' delimited (possibly empty) strings in which case search for a match
296 * within the alternatives proceeds left to right. Return 0 for success,
297 * non-zero otherwise.
298 */
299static int altcmp(const char *s, const char *e, const char *altstr)
300{
301 const char *p, *q;
302
303 for (q = p = altstr; ; ) {
304 while (*p && *p != '|')
305 ++p;
306 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
307 return (0);
308 if (!*p)
309 return (1);
310 else
311 q = ++p;
312 }
313}
314
315/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 316 * *pval and return true, otherwise return false
c6dc6f63 317 */
e41e0fc6
JK		 318static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
319 const char **featureset)
c6dc6f63
AP		 320{
321 uint32_t mask;
322 const char **ppc;
e41e0fc6 323 bool found = false;
c6dc6f63 324
e41e0fc6 325 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 326 if (*ppc && !altcmp(s, e, *ppc)) {
327 *pval |= mask;
e41e0fc6 328 found = true;
c6dc6f63 329 }
e41e0fc6
JK		 330 }
331 return found;
c6dc6f63
AP		 332}
333
5ef57876
EH		 334static void add_flagname_to_bitmaps(const char *flagname,
335 FeatureWordArray words)
c6dc6f63 336{
5ef57876
EH		 337 FeatureWord w;
338 for (w = 0; w < FEATURE_WORDS; w++) {
339 FeatureWordInfo *wi = &feature_word_info[w];
340 if (wi->feat_names &&
341 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
342 break;
343 }
344 }
345 if (w == FEATURE_WORDS) {
346 fprintf(stderr, "CPU feature %s not found\n", flagname);
347 }
c6dc6f63
AP		 348}
349
350typedef struct x86_def_t {
c6dc6f63
AP		 351 const char *name;
352 uint32_t level;
99b88a17
IM		 353 /* vendor is zero-terminated, 12 character ASCII string */
354 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 355 int family;
356 int model;
357 int stepping;
296acb64
JR		 358 uint32_t features, ext_features, ext2_features, ext3_features;
359 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 360 uint32_t xlevel;
361 char model_id[48];
b3baa152
BW		 362 /* Store the results of Centaur's CPUID instructions */
363 uint32_t ext4_features;
364 uint32_t xlevel2;
13526728
EH		 365 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
366 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 367} x86_def_t;
368
369#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
370#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
371 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
372#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
373 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
374 CPUID_PSE36 | CPUID_FXSR)
375#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
376#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
377 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
378 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
379 CPUID_PAE | CPUID_SEP | CPUID_APIC)
380
551a2dec
AP		 381#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
382 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
383 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
384 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
385 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 386 /* partly implemented:
387 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
388 CPUID_PSE36 (needed for Solaris) */
389 /* missing:
390 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
e71827bc
AJ		 391#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
392 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
393 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
d640045a 394 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
8560efed 395 /* missing:
e71827bc
AJ		 396 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
397 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
398 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
d640045a
AJ		 399 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
400 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
83f7dc28 401 CPUID_EXT_RDRAND */
60032ac0 402#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 403 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
404 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 405 /* missing:
406 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 407#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
408 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 409#define TCG_SVM_FEATURES 0
7073fbad 410#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
cd7f97ca 411 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
111994ee 412 /* missing:
7073fbad
RH		 413 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
414 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
cd7f97ca 415 CPUID_7_0_EBX_RDSEED */
551a2dec 416
7fc9b714 417/* built-in CPU model definitions
c6dc6f63
AP		 418 */
419static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 420 {
421 .name = "qemu64",
422 .level = 4,
99b88a17 423 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 424 .family = 6,
425 .model = 2,
426 .stepping = 3,
427 .features = PPRO_FEATURES |
c6dc6f63 428 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 429 CPUID_PSE36,
430 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
60032ac0 431 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 432 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
433 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
434 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
435 .xlevel = 0x8000000A,
c6dc6f63
AP		 436 },
437 {
438 .name = "phenom",
439 .level = 5,
99b88a17 440 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 441 .family = 16,
442 .model = 2,
443 .stepping = 3,
c6dc6f63
AP		 444 .features = PPRO_FEATURES |
445 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 446 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 447 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
448 CPUID_EXT_POPCNT,
60032ac0 449 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 450 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
451 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 452 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 453 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
454 CPUID_EXT3_CR8LEG,
455 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
456 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
457 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
458 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 459 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 460 .xlevel = 0x8000001A,
461 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
462 },
463 {
464 .name = "core2duo",
465 .level = 10,
99b88a17 466 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 467 .family = 6,
468 .model = 15,
469 .stepping = 11,
c6dc6f63
AP		 470 .features = PPRO_FEATURES |
471 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 472 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
473 CPUID_HT | CPUID_TM | CPUID_PBE,
474 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
475 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
476 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 477 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
478 .ext3_features = CPUID_EXT3_LAHF_LM,
479 .xlevel = 0x80000008,
480 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
481 },
482 {
483 .name = "kvm64",
484 .level = 5,
99b88a17 485 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 486 .family = 15,
487 .model = 6,
488 .stepping = 1,
489 /* Missing: CPUID_VME, CPUID_HT */
490 .features = PPRO_FEATURES |
491 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
492 CPUID_PSE36,
493 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
494 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
495 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
60032ac0 496 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 497 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
498 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
499 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
500 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
501 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
502 .ext3_features = 0,
503 .xlevel = 0x80000008,
504 .model_id = "Common KVM processor"
505 },
c6dc6f63
AP		 506 {
507 .name = "qemu32",
508 .level = 4,
99b88a17 509 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 510 .family = 6,
511 .model = 3,
512 .stepping = 3,
513 .features = PPRO_FEATURES,
514 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 515 .xlevel = 0x80000004,
c6dc6f63 516 },
eafaf1e5
AP		 517 {
518 .name = "kvm32",
519 .level = 5,
99b88a17 520 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 521 .family = 15,
522 .model = 6,
523 .stepping = 1,
524 .features = PPRO_FEATURES |
525 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
526 .ext_features = CPUID_EXT_SSE3,
60032ac0 527 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
eafaf1e5
AP		 528 .ext3_features = 0,
529 .xlevel = 0x80000008,
530 .model_id = "Common 32-bit KVM processor"
531 },
c6dc6f63
AP		 532 {
533 .name = "coreduo",
534 .level = 10,
99b88a17 535 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 536 .family = 6,
537 .model = 14,
538 .stepping = 8,
c6dc6f63 539 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 540 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
541 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
542 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
543 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 544 .ext2_features = CPUID_EXT2_NX,
545 .xlevel = 0x80000008,
546 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
547 },
548 {
549 .name = "486",
58012d66 550 .level = 1,
99b88a17 551 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 552 .family = 4,
553 .model = 0,
554 .stepping = 0,
555 .features = I486_FEATURES,
556 .xlevel = 0,
557 },
558 {
559 .name = "pentium",
560 .level = 1,
99b88a17 561 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 562 .family = 5,
563 .model = 4,
564 .stepping = 3,
565 .features = PENTIUM_FEATURES,
566 .xlevel = 0,
567 },
568 {
569 .name = "pentium2",
570 .level = 2,
99b88a17 571 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 572 .family = 6,
573 .model = 5,
574 .stepping = 2,
575 .features = PENTIUM2_FEATURES,
576 .xlevel = 0,
577 },
578 {
579 .name = "pentium3",
580 .level = 2,
99b88a17 581 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 582 .family = 6,
583 .model = 7,
584 .stepping = 3,
585 .features = PENTIUM3_FEATURES,
586 .xlevel = 0,
587 },
588 {
589 .name = "athlon",
590 .level = 2,
99b88a17 591 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 592 .family = 6,
593 .model = 2,
594 .stepping = 3,
60032ac0
EH		 595 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
596 CPUID_MCA,
597 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
598 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 599 .xlevel = 0x80000008,
c6dc6f63
AP		 600 },
601 {
602 .name = "n270",
603 /* original is on level 10 */
604 .level = 5,
99b88a17 605 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 606 .family = 6,
607 .model = 28,
608 .stepping = 2,
609 .features = PPRO_FEATURES |
8560efed
AJ		 610 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
611 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 612 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 613 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
614 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
60032ac0
EH		 615 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
616 CPUID_EXT2_NX,
8560efed 617 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 618 .xlevel = 0x8000000A,
619 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
620 },
3eca4642
EH		 621 {
622 .name = "Conroe",
623 .level = 2,
99b88a17 624 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 625 .family = 6,
626 .model = 2,
627 .stepping = 3,
628 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
629 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
630 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
631 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
632 CPUID_DE | CPUID_FP87,
633 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
634 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
635 .ext3_features = CPUID_EXT3_LAHF_LM,
636 .xlevel = 0x8000000A,
637 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
638 },
639 {
640 .name = "Penryn",
641 .level = 2,
99b88a17 642 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 643 .family = 6,
644 .model = 2,
645 .stepping = 3,
646 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
647 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
648 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
649 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
650 CPUID_DE | CPUID_FP87,
651 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
652 CPUID_EXT_SSE3,
653 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
654 .ext3_features = CPUID_EXT3_LAHF_LM,
655 .xlevel = 0x8000000A,
656 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
657 },
658 {
659 .name = "Nehalem",
660 .level = 2,
99b88a17 661 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 662 .family = 6,
663 .model = 2,
664 .stepping = 3,
665 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
666 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
667 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
668 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
669 CPUID_DE | CPUID_FP87,
670 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
671 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
672 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
673 .ext3_features = CPUID_EXT3_LAHF_LM,
674 .xlevel = 0x8000000A,
675 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
676 },
677 {
678 .name = "Westmere",
679 .level = 11,
99b88a17 680 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 681 .family = 6,
682 .model = 44,
683 .stepping = 1,
684 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
685 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
686 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
687 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
688 CPUID_DE | CPUID_FP87,
689 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
690 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 691 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3eca4642
EH		 692 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
693 .ext3_features = CPUID_EXT3_LAHF_LM,
694 .xlevel = 0x8000000A,
695 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
696 },
697 {
698 .name = "SandyBridge",
699 .level = 0xd,
99b88a17 700 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 701 .family = 6,
702 .model = 42,
703 .stepping = 1,
704 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
705 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
706 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
707 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
708 CPUID_DE | CPUID_FP87,
709 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
710 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
711 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
712 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
713 CPUID_EXT_SSE3,
714 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
715 CPUID_EXT2_SYSCALL,
716 .ext3_features = CPUID_EXT3_LAHF_LM,
717 .xlevel = 0x8000000A,
718 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
719 },
37507094
EH		 720 {
721 .name = "Haswell",
722 .level = 0xd,
99b88a17 723 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 724 .family = 6,
725 .model = 60,
726 .stepping = 1,
727 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
728 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 729 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 730 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
731 CPUID_DE | CPUID_FP87,
732 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
733 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
734 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
735 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
736 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
737 CPUID_EXT_PCID,
80ae4160
EH		 738 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
739 CPUID_EXT2_SYSCALL,
37507094
EH		 740 .ext3_features = CPUID_EXT3_LAHF_LM,
741 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
742 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
743 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
744 CPUID_7_0_EBX_RTM,
745 .xlevel = 0x8000000A,
746 .model_id = "Intel Core Processor (Haswell)",
747 },
3eca4642
EH		 748 {
749 .name = "Opteron_G1",
750 .level = 5,
99b88a17 751 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 752 .family = 15,
753 .model = 6,
754 .stepping = 1,
755 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
756 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
757 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
758 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
759 CPUID_DE | CPUID_FP87,
760 .ext_features = CPUID_EXT_SSE3,
761 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
762 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
763 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
764 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
765 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
766 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
767 .xlevel = 0x80000008,
768 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
769 },
770 {
771 .name = "Opteron_G2",
772 .level = 5,
99b88a17 773 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 774 .family = 15,
775 .model = 6,
776 .stepping = 1,
777 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
778 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
779 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
780 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
781 CPUID_DE | CPUID_FP87,
782 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
783 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
784 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
785 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
786 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
787 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
788 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
789 CPUID_EXT2_DE | CPUID_EXT2_FPU,
790 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
791 .xlevel = 0x80000008,
792 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
793 },
794 {
795 .name = "Opteron_G3",
796 .level = 5,
99b88a17 797 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 798 .family = 15,
799 .model = 6,
800 .stepping = 1,
801 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
802 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
803 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
804 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
805 CPUID_DE | CPUID_FP87,
806 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
807 CPUID_EXT_SSE3,
808 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
809 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
810 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
811 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
812 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
813 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
814 CPUID_EXT2_DE | CPUID_EXT2_FPU,
815 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
816 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
817 .xlevel = 0x80000008,
818 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
819 },
820 {
821 .name = "Opteron_G4",
822 .level = 0xd,
99b88a17 823 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 824 .family = 21,
825 .model = 1,
826 .stepping = 2,
827 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
828 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
829 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
830 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
831 CPUID_DE | CPUID_FP87,
832 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
833 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
834 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
835 CPUID_EXT_SSE3,
836 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
837 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
838 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
839 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
840 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
841 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
842 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
843 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
844 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
845 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
846 CPUID_EXT3_LAHF_LM,
847 .xlevel = 0x8000001A,
848 .model_id = "AMD Opteron 62xx class CPU",
849 },
021941b9
AP		 850 {
851 .name = "Opteron_G5",
852 .level = 0xd,
99b88a17 853 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 854 .family = 21,
855 .model = 2,
856 .stepping = 0,
857 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
858 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
859 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
860 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
861 CPUID_DE | CPUID_FP87,
862 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
863 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
864 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
865 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
866 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
867 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
868 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
869 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
870 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
871 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
872 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
873 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
874 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
875 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
876 CPUID_EXT3_LAHF_LM,
877 .xlevel = 0x8000001A,
878 .model_id = "AMD Opteron 63xx class CPU",
879 },
c6dc6f63
AP		 880};
881
e4ab0d6b 882#ifdef CONFIG_KVM
c6dc6f63
AP		 883static int cpu_x86_fill_model_id(char *str)
884{
885 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
886 int i;
887
888 for (i = 0; i < 3; i++) {
889 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
890 memcpy(str + i * 16 + 0, &eax, 4);
891 memcpy(str + i * 16 + 4, &ebx, 4);
892 memcpy(str + i * 16 + 8, &ecx, 4);
893 memcpy(str + i * 16 + 12, &edx, 4);
894 }
895 return 0;
896}
e4ab0d6b 897#endif
c6dc6f63 898
6e746f30
EH		 899/* Fill a x86_def_t struct with information about the host CPU, and
900 * the CPU features supported by the host hardware + host kernel
901 *
902 * This function may be called only if KVM is enabled.
903 */
904static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 905{
e4ab0d6b 906#ifdef CONFIG_KVM
12869995 907 KVMState *s = kvm_state;
c6dc6f63
AP		 908 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
909
6e746f30
EH		 910 assert(kvm_enabled());
911
c6dc6f63
AP		 912 x86_cpu_def->name = "host";
913 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
99b88a17 914 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
c6dc6f63
AP		 915
916 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
917 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
918 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
919 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 920
12869995
EH		 921 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
922 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
923 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 924
6e746f30 925 if (x86_cpu_def->level >= 7) {
12869995
EH		 926 x86_cpu_def->cpuid_7_0_ebx_features =
927 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728
EH		 928 } else {
929 x86_cpu_def->cpuid_7_0_ebx_features = 0;
930 }
931
12869995
EH		 932 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
933 x86_cpu_def->ext2_features =
934 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
935 x86_cpu_def->ext3_features =
936 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 937
c6dc6f63 938 cpu_x86_fill_model_id(x86_cpu_def->model_id);
c6dc6f63 939
b3baa152 940 /* Call Centaur's CPUID instruction. */
99b88a17 941 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
b3baa152 942 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
12869995 943 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
b3baa152
BW		 944 if (eax >= 0xC0000001) {
945 /* Support VIA max extended level */
946 x86_cpu_def->xlevel2 = eax;
947 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
12869995
EH		 948 x86_cpu_def->ext4_features =
949 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
b3baa152
BW		 950 }
951 }
296acb64 952
fcb93c03
EH		 953 /* Other KVM-specific feature fields: */
954 x86_cpu_def->svm_features =
955 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
bd004bef
EH		 956 x86_cpu_def->kvm_features =
957 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 958
e4ab0d6b 959#endif /* CONFIG_KVM */
c6dc6f63
AP		 960}
961
bffd67b0 962static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 963{
964 int i;
965
966 for (i = 0; i < 32; ++i)
967 if (1 << i & mask) {
bffd67b0 968 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 969 assert(reg);
970 fprintf(stderr, "warning: host doesn't support requested feature: "
971 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 972 f->cpuid_eax, reg,
973 f->feat_names[i] ? "." : "",
974 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 975 break;
976 }
977 return 0;
978}
979
07ca5945
EH		 980/* Check if all requested cpu flags are making their way to the guest
981 *
982 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 983 *
984 * This function may be called only if KVM is enabled.
c6dc6f63 985 */
5ec01c2e 986static int kvm_check_features_against_host(X86CPU *cpu)
c6dc6f63 987{
5ec01c2e 988 CPUX86State *env = &cpu->env;
c6dc6f63
AP		 989 x86_def_t host_def;
990 uint32_t mask;
991 int rv, i;
992 struct model_features_t ft[] = {
5ec01c2e 993 {&env->cpuid_features, &host_def.features,
bffd67b0 994 FEAT_1_EDX },
5ec01c2e 995 {&env->cpuid_ext_features, &host_def.ext_features,
bffd67b0 996 FEAT_1_ECX },
5ec01c2e 997 {&env->cpuid_ext2_features, &host_def.ext2_features,
bffd67b0 998 FEAT_8000_0001_EDX },
5ec01c2e 999 {&env->cpuid_ext3_features, &host_def.ext3_features,
bffd67b0 1000 FEAT_8000_0001_ECX },
5ec01c2e 1001 {&env->cpuid_ext4_features, &host_def.ext4_features,
07ca5945 1002 FEAT_C000_0001_EDX },
5ec01c2e 1003 {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
07ca5945 1004 FEAT_7_0_EBX },
5ec01c2e 1005 {&env->cpuid_svm_features, &host_def.svm_features,
07ca5945 1006 FEAT_SVM },
5ec01c2e 1007 {&env->cpuid_kvm_features, &host_def.kvm_features,
07ca5945 1008 FEAT_KVM },
8b4beddc 1009 };
c6dc6f63 1010
6e746f30
EH		 1011 assert(kvm_enabled());
1012
1013 kvm_cpu_fill_host(&host_def);
bffd67b0
EH		 1014 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1015 FeatureWord w = ft[i].feat_word;
1016 FeatureWordInfo *wi = &feature_word_info[w];
1017 for (mask = 1; mask; mask <<= 1) {
e8beac00 1018 if (*ft[i].guest_feat & mask &&
c6dc6f63 1019 !(*ft[i].host_feat & mask)) {
bffd67b0
EH		 1020 unavailable_host_feature(wi, mask);
1021 rv = 1;
1022 }
1023 }
1024 }
c6dc6f63
AP		 1025 return rv;
1026}
1027
95b8519d
AF		 1028static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1029 const char *name, Error **errp)
1030{
1031 X86CPU *cpu = X86_CPU(obj);
1032 CPUX86State *env = &cpu->env;
1033 int64_t value;
1034
1035 value = (env->cpuid_version >> 8) & 0xf;
1036 if (value == 0xf) {
1037 value += (env->cpuid_version >> 20) & 0xff;
1038 }
1039 visit_type_int(v, &value, name, errp);
1040}
1041
71ad61d3
AF		 1042static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1043 const char *name, Error **errp)
ed5e1ec3 1044{
71ad61d3
AF		 1045 X86CPU *cpu = X86_CPU(obj);
1046 CPUX86State *env = &cpu->env;
1047 const int64_t min = 0;
1048 const int64_t max = 0xff + 0xf;
1049 int64_t value;
1050
1051 visit_type_int(v, &value, name, errp);
1052 if (error_is_set(errp)) {
1053 return;
1054 }
1055 if (value < min || value > max) {
1056 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1057 name ? name : "null", value, min, max);
1058 return;
1059 }
1060
ed5e1ec3 1061 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1062 if (value > 0x0f) {
1063 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1064 } else {
71ad61d3 1065 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1066 }
1067}
1068
67e30c83
AF		 1069static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1070 const char *name, Error **errp)
1071{
1072 X86CPU *cpu = X86_CPU(obj);
1073 CPUX86State *env = &cpu->env;
1074 int64_t value;
1075
1076 value = (env->cpuid_version >> 4) & 0xf;
1077 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1078 visit_type_int(v, &value, name, errp);
1079}
1080
c5291a4f
AF		 1081static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1082 const char *name, Error **errp)
b0704cbd 1083{
c5291a4f
AF		 1084 X86CPU *cpu = X86_CPU(obj);
1085 CPUX86State *env = &cpu->env;
1086 const int64_t min = 0;
1087 const int64_t max = 0xff;
1088 int64_t value;
1089
1090 visit_type_int(v, &value, name, errp);
1091 if (error_is_set(errp)) {
1092 return;
1093 }
1094 if (value < min || value > max) {
1095 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1096 name ? name : "null", value, min, max);
1097 return;
1098 }
1099
b0704cbd 1100 env->cpuid_version &= ~0xf00f0;
c5291a4f 1101 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1102}
1103
35112e41
AF		 1104static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1105 void *opaque, const char *name,
1106 Error **errp)
1107{
1108 X86CPU *cpu = X86_CPU(obj);
1109 CPUX86State *env = &cpu->env;
1110 int64_t value;
1111
1112 value = env->cpuid_version & 0xf;
1113 visit_type_int(v, &value, name, errp);
1114}
1115
036e2222
AF		 1116static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1117 void *opaque, const char *name,
1118 Error **errp)
38c3dc46 1119{
036e2222
AF		 1120 X86CPU *cpu = X86_CPU(obj);
1121 CPUX86State *env = &cpu->env;
1122 const int64_t min = 0;
1123 const int64_t max = 0xf;
1124 int64_t value;
1125
1126 visit_type_int(v, &value, name, errp);
1127 if (error_is_set(errp)) {
1128 return;
1129 }
1130 if (value < min || value > max) {
1131 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1132 name ? name : "null", value, min, max);
1133 return;
1134 }
1135
38c3dc46 1136 env->cpuid_version &= ~0xf;
036e2222 1137 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1138}
1139
8e1898bf
AF		 1140static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1141 const char *name, Error **errp)
1142{
1143 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1144
fa029887 1145 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1146}
1147
1148static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1149 const char *name, Error **errp)
1150{
1151 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1152
fa029887 1153 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1154}
1155
16b93aa8
AF		 1156static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1157 const char *name, Error **errp)
1158{
1159 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1160
fa029887 1161 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1162}
1163
1164static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1165 const char *name, Error **errp)
1166{
1167 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1168
fa029887 1169 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1170}
1171
d480e1af
AF		 1172static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1173{
1174 X86CPU *cpu = X86_CPU(obj);
1175 CPUX86State *env = &cpu->env;
1176 char *value;
d480e1af 1177
9df694ee 1178 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1179 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1180 env->cpuid_vendor3);
d480e1af
AF		 1181 return value;
1182}
1183
1184static void x86_cpuid_set_vendor(Object *obj, const char *value,
1185 Error **errp)
1186{
1187 X86CPU *cpu = X86_CPU(obj);
1188 CPUX86State *env = &cpu->env;
1189 int i;
1190
9df694ee 1191 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1192 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1193 "vendor", value);
1194 return;
1195 }
1196
1197 env->cpuid_vendor1 = 0;
1198 env->cpuid_vendor2 = 0;
1199 env->cpuid_vendor3 = 0;
1200 for (i = 0; i < 4; i++) {
1201 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1202 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1203 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1204 }
d480e1af
AF		 1205}
1206
63e886eb
AF		 1207static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1208{
1209 X86CPU *cpu = X86_CPU(obj);
1210 CPUX86State *env = &cpu->env;
1211 char *value;
1212 int i;
1213
1214 value = g_malloc(48 + 1);
1215 for (i = 0; i < 48; i++) {
1216 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1217 }
1218 value[48] = '\0';
1219 return value;
1220}
1221
938d4c25
AF		 1222static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1223 Error **errp)
dcce6675 1224{
938d4c25
AF		 1225 X86CPU *cpu = X86_CPU(obj);
1226 CPUX86State *env = &cpu->env;
dcce6675
AF		 1227 int c, len, i;
1228
1229 if (model_id == NULL) {
1230 model_id = "";
1231 }
1232 len = strlen(model_id);
d0a6acf4 1233 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1234 for (i = 0; i < 48; i++) {
1235 if (i >= len) {
1236 c = '\0';
1237 } else {
1238 c = (uint8_t)model_id[i];
1239 }
1240 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1241 }
1242}
1243
89e48965
AF		 1244static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1245 const char *name, Error **errp)
1246{
1247 X86CPU *cpu = X86_CPU(obj);
1248 int64_t value;
1249
1250 value = cpu->env.tsc_khz * 1000;
1251 visit_type_int(v, &value, name, errp);
1252}
1253
1254static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1255 const char *name, Error **errp)
1256{
1257 X86CPU *cpu = X86_CPU(obj);
1258 const int64_t min = 0;
2e84849a 1259 const int64_t max = INT64_MAX;
89e48965
AF		 1260 int64_t value;
1261
1262 visit_type_int(v, &value, name, errp);
1263 if (error_is_set(errp)) {
1264 return;
1265 }
1266 if (value < min || value > max) {
1267 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1268 name ? name : "null", value, min, max);
1269 return;
1270 }
1271
1272 cpu->env.tsc_khz = value / 1000;
1273}
1274
31050930
IM		 1275static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1276 const char *name, Error **errp)
1277{
1278 X86CPU *cpu = X86_CPU(obj);
1279 int64_t value = cpu->env.cpuid_apic_id;
1280
1281 visit_type_int(v, &value, name, errp);
1282}
1283
1284static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1285 const char *name, Error **errp)
1286{
1287 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1288 DeviceState *dev = DEVICE(obj);
31050930
IM		 1289 const int64_t min = 0;
1290 const int64_t max = UINT32_MAX;
1291 Error *error = NULL;
1292 int64_t value;
1293
8d6d4980
IM		 1294 if (dev->realized) {
1295 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1296 "it was realized", name, object_get_typename(obj));
1297 return;
1298 }
1299
31050930
IM		 1300 visit_type_int(v, &value, name, &error);
1301 if (error) {
1302 error_propagate(errp, error);
1303 return;
1304 }
1305 if (value < min || value > max) {
1306 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1307 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1308 object_get_typename(obj), name, value, min, max);
1309 return;
1310 }
1311
1312 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1313 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1314 return;
1315 }
1316 cpu->env.cpuid_apic_id = value;
1317}
1318
8f961357 1319static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
c6dc6f63 1320{
c6dc6f63 1321 x86_def_t *def;
7fc9b714 1322 int i;
c6dc6f63 1323
4bfe910d
AF		 1324 if (name == NULL) {
1325 return -1;
9f3fb565 1326 }
4bfe910d 1327 if (kvm_enabled() && strcmp(name, "host") == 0) {
6e746f30 1328 kvm_cpu_fill_host(x86_cpu_def);
4bfe910d 1329 return 0;
c6dc6f63
AP		 1330 }
1331
7fc9b714
AF		 1332 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1333 def = &builtin_x86_defs[i];
4bfe910d
AF		 1334 if (strcmp(name, def->name) == 0) {
1335 memcpy(x86_cpu_def, def, sizeof(*def));
11acfdd5
IM		 1336 /* sysenter isn't supported in compatibility mode on AMD,
1337 * syscall isn't supported in compatibility mode on Intel.
1338 * Normally we advertise the actual CPU vendor, but you can
1339 * override this using the 'vendor' property if you want to use
1340 * KVM's sysenter/syscall emulation in compatibility mode and
1341 * when doing cross vendor migration
1342 */
1343 if (kvm_enabled()) {
1344 uint32_t ebx = 0, ecx = 0, edx = 0;
1345 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1346 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1347 }
4bfe910d
AF		 1348 return 0;
1349 }
1350 }
1351
1352 return -1;
8f961357
EH		 1353}
1354
72ac2e87
IM		 1355/* Convert all '_' in a feature string option name to '-', to make feature
1356 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1357 */
1358static inline void feat2prop(char *s)
1359{
1360 while ((s = strchr(s, '_'))) {
1361 *s = '-';
1362 }
1363}
1364
8f961357
EH		 1365/* Parse "+feature,-feature,feature=foo" CPU feature string
1366 */
a91987c2 1367static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
8f961357 1368{
8f961357
EH		 1369 char *featurestr; /* Single 'key=value" string being parsed */
1370 /* Features to be added */
077c68c3 1371 FeatureWordArray plus_features = { 0 };
8f961357 1372 /* Features to be removed */
5ef57876 1373 FeatureWordArray minus_features = { 0 };
8f961357 1374 uint32_t numvalue;
a91987c2 1375 CPUX86State *env = &cpu->env;
8f961357 1376
8f961357 1377 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1378
1379 while (featurestr) {
1380 char *val;
1381 if (featurestr[0] == '+') {
5ef57876 1382 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1383 } else if (featurestr[0] == '-') {
5ef57876 1384 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1385 } else if ((val = strchr(featurestr, '='))) {
1386 *val = 0; val++;
72ac2e87 1387 feat2prop(featurestr);
c6dc6f63 1388 if (!strcmp(featurestr, "family")) {
a91987c2 1389 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1390 } else if (!strcmp(featurestr, "model")) {
a91987c2 1391 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1392 } else if (!strcmp(featurestr, "stepping")) {
a91987c2 1393 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1394 } else if (!strcmp(featurestr, "level")) {
a91987c2 1395 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63
AP		 1396 } else if (!strcmp(featurestr, "xlevel")) {
1397 char *err;
a91987c2
IM		 1398 char num[32];
1399
c6dc6f63
AP		 1400 numvalue = strtoul(val, &err, 0);
1401 if (!*val || *err) {
312fd5f2 1402 error_setg(errp, "bad numerical value %s", val);
a91987c2 1403 goto out;
c6dc6f63
AP		 1404 }
1405 if (numvalue < 0x80000000) {
8ba8a698
IM		 1406 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1407 ", fixup will be removed in future versions\n");
2f7a21c4 1408 numvalue += 0x80000000;
c6dc6f63 1409 }
a91987c2
IM		 1410 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1411 object_property_parse(OBJECT(cpu), num, featurestr, errp);
c6dc6f63 1412 } else if (!strcmp(featurestr, "vendor")) {
a91987c2 1413 object_property_parse(OBJECT(cpu), val, featurestr, errp);
72ac2e87
IM		 1414 } else if (!strcmp(featurestr, "model-id")) {
1415 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1416 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1417 int64_t tsc_freq;
1418 char *err;
a91987c2 1419 char num[32];
b862d1fe
JR		 1420
1421 tsc_freq = strtosz_suffix_unit(val, &err,
1422 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1423 if (tsc_freq < 0 || *err) {
312fd5f2 1424 error_setg(errp, "bad numerical value %s", val);
a91987c2 1425 goto out;
b862d1fe 1426 }
a91987c2
IM		 1427 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1428 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
72ac2e87 1429 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0
VR		 1430 char *err;
1431 numvalue = strtoul(val, &err, 0);
1432 if (!*val || *err) {
312fd5f2 1433 error_setg(errp, "bad numerical value %s", val);
a91987c2 1434 goto out;
28f52cc0
VR		 1435 }
1436 hyperv_set_spinlock_retries(numvalue);
c6dc6f63 1437 } else {
312fd5f2 1438 error_setg(errp, "unrecognized feature %s", featurestr);
a91987c2 1439 goto out;
c6dc6f63
AP		 1440 }
1441 } else if (!strcmp(featurestr, "check")) {
1442 check_cpuid = 1;
1443 } else if (!strcmp(featurestr, "enforce")) {
1444 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1445 } else if (!strcmp(featurestr, "hv_relaxed")) {
1446 hyperv_enable_relaxed_timing(true);
1447 } else if (!strcmp(featurestr, "hv_vapic")) {
1448 hyperv_enable_vapic_recommended(true);
c6dc6f63 1449 } else {
a91987c2 1450 error_setg(errp, "feature string `%s' not in format (+feature|"
312fd5f2 1451 "-feature|feature=xyz)", featurestr);
a91987c2
IM		 1452 goto out;
1453 }
1454 if (error_is_set(errp)) {
1455 goto out;
c6dc6f63
AP		 1456 }
1457 featurestr = strtok(NULL, ",");
1458 }
a91987c2
IM		 1459 env->cpuid_features |= plus_features[FEAT_1_EDX];
1460 env->cpuid_ext_features |= plus_features[FEAT_1_ECX];
1461 env->cpuid_ext2_features |= plus_features[FEAT_8000_0001_EDX];
1462 env->cpuid_ext3_features |= plus_features[FEAT_8000_0001_ECX];
1463 env->cpuid_ext4_features |= plus_features[FEAT_C000_0001_EDX];
1464 env->cpuid_kvm_features |= plus_features[FEAT_KVM];
1465 env->cpuid_svm_features |= plus_features[FEAT_SVM];
1466 env->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1467 env->cpuid_features &= ~minus_features[FEAT_1_EDX];
1468 env->cpuid_ext_features &= ~minus_features[FEAT_1_ECX];
1469 env->cpuid_ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1470 env->cpuid_ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1471 env->cpuid_ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
1472 env->cpuid_kvm_features &= ~minus_features[FEAT_KVM];
1473 env->cpuid_svm_features &= ~minus_features[FEAT_SVM];
1474 env->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63 1475
a91987c2
IM		 1476out:
1477 return;
c6dc6f63
AP		 1478}
1479
1480/* generate a composite string into buf of all cpuid names in featureset
1481 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1482 * if flags, suppress names undefined in featureset.
1483 */
1484static void listflags(char *buf, int bufsize, uint32_t fbits,
1485 const char **featureset, uint32_t flags)
1486{
1487 const char **p = &featureset[31];
1488 char *q, *b, bit;
1489 int nc;
1490
1491 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1492 *buf = '\0';
1493 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1494 if (fbits & 1 << bit && (*p || !flags)) {
1495 if (*p)
1496 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1497 else
1498 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1499 if (bufsize <= nc) {
1500 if (b) {
1501 memcpy(b, "...", sizeof("..."));
1502 }
1503 return;
1504 }
1505 q += nc;
1506 bufsize -= nc;
1507 }
1508}
1509
e916cbf8
PM		 1510/* generate CPU information. */
1511void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1512{
c6dc6f63
AP		 1513 x86_def_t *def;
1514 char buf[256];
7fc9b714 1515 int i;
c6dc6f63 1516
7fc9b714
AF		 1517 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1518 def = &builtin_x86_defs[i];
c04321b3 1519 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1520 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1521 }
21ad7789
JK		 1522#ifdef CONFIG_KVM
1523 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1524 "KVM processor with all supported host features "
1525 "(only available in KVM mode)");
1526#endif
1527
6cdf8854 1528 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1529 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1530 FeatureWordInfo *fw = &feature_word_info[i];
1531
1532 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1533 (*cpu_fprintf)(f, " %s\n", buf);
1534 }
c6dc6f63
AP		 1535}
1536
76b64a7a 1537CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1538{
1539 CpuDefinitionInfoList *cpu_list = NULL;
1540 x86_def_t *def;
7fc9b714 1541 int i;
e3966126 1542
7fc9b714 1543 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1544 CpuDefinitionInfoList *entry;
1545 CpuDefinitionInfo *info;
1546
7fc9b714 1547 def = &builtin_x86_defs[i];
e3966126
AL		 1548 info = g_malloc0(sizeof(*info));
1549 info->name = g_strdup(def->name);
1550
1551 entry = g_malloc0(sizeof(*entry));
1552 entry->value = info;
1553 entry->next = cpu_list;
1554 cpu_list = entry;
1555 }
1556
1557 return cpu_list;
1558}
1559
bc74b7db
EH		 1560#ifdef CONFIG_KVM
1561static void filter_features_for_kvm(X86CPU *cpu)
1562{
1563 CPUX86State *env = &cpu->env;
1564 KVMState *s = kvm_state;
1565
b8091f24
EH		 1566 env->cpuid_features &=
1567 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1568 env->cpuid_ext_features &=
1569 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1570 env->cpuid_ext2_features &=
1571 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1572 env->cpuid_ext3_features &=
1573 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1574 env->cpuid_svm_features &=
1575 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
ffa8c11f
EH		 1576 env->cpuid_7_0_ebx_features &=
1577 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
bc74b7db 1578 env->cpuid_kvm_features &=
b8091f24
EH		 1579 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1580 env->cpuid_ext4_features &=
1581 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
bc74b7db
EH		 1582
1583}
1584#endif
1585
2d64255b 1586static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
c6dc6f63 1587{
61dcd775 1588 CPUX86State *env = &cpu->env;
c6dc6f63
AP		 1589 x86_def_t def1, *def = &def1;
1590
db0ad1ba
JR		 1591 memset(def, 0, sizeof(*def));
1592
8f961357 1593 if (cpu_x86_find_by_name(def, name) < 0) {
2d64255b
AF		 1594 error_setg(errp, "Unable to find CPU definition: %s", name);
1595 return;
8f961357
EH		 1596 }
1597
aa87d458
EH		 1598 if (kvm_enabled()) {
1599 def->kvm_features |= kvm_default_features;
1600 }
077c68c3
IM		 1601 def->ext_features |= CPUID_EXT_HYPERVISOR;
1602
2d64255b
AF		 1603 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1604 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1605 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1606 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1607 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
c6dc6f63 1608 env->cpuid_features = def->features;
c6dc6f63
AP		 1609 env->cpuid_ext_features = def->ext_features;
1610 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1611 env->cpuid_ext3_features = def->ext3_features;
2d64255b 1612 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
c6dc6f63 1613 env->cpuid_kvm_features = def->kvm_features;
296acb64 1614 env->cpuid_svm_features = def->svm_features;
b3baa152 1615 env->cpuid_ext4_features = def->ext4_features;
a9321a4d 1616 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
b3baa152 1617 env->cpuid_xlevel2 = def->xlevel2;
3b671a40 1618
2d64255b 1619 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
c6dc6f63
AP		 1620}
1621
62fc403f
IM		 1622X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1623 Error **errp)
5c3c6a68 1624{
2d64255b 1625 X86CPU *cpu = NULL;
5c3c6a68 1626 CPUX86State *env;
2d64255b
AF		 1627 gchar **model_pieces;
1628 char *name, *features;
5c3c6a68
AF		 1629 Error *error = NULL;
1630
2d64255b
AF		 1631 model_pieces = g_strsplit(cpu_model, ",", 2);
1632 if (!model_pieces[0]) {
1633 error_setg(&error, "Invalid/empty CPU model name");
1634 goto out;
1635 }
1636 name = model_pieces[0];
1637 features = model_pieces[1];
1638
5c3c6a68 1639 cpu = X86_CPU(object_new(TYPE_X86_CPU));
62fc403f
IM		 1640#ifndef CONFIG_USER_ONLY
1641 if (icc_bridge == NULL) {
1642 error_setg(&error, "Invalid icc-bridge value");
1643 goto out;
1644 }
1645 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1646 object_unref(OBJECT(cpu));
1647#endif
5c3c6a68
AF		 1648 env = &cpu->env;
1649 env->cpu_model_str = cpu_model;
1650
2d64255b
AF		 1651 cpu_x86_register(cpu, name, &error);
1652 if (error) {
1653 goto out;
1654 }
1655
1656 cpu_x86_parse_featurestr(cpu, features, &error);
1657 if (error) {
1658 goto out;
5c3c6a68
AF		 1659 }
1660
7f833247
IM		 1661out:
1662 error_propagate(errp, error);
1663 g_strfreev(model_pieces);
1664 return cpu;
1665}
1666
1667X86CPU *cpu_x86_init(const char *cpu_model)
1668{
1669 Error *error = NULL;
1670 X86CPU *cpu;
1671
62fc403f 1672 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1673 if (error) {
2d64255b
AF		 1674 goto out;
1675 }
1676
7f833247
IM		 1677 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1678
2d64255b 1679out:
2d64255b
AF		 1680 if (error) {
1681 fprintf(stderr, "%s\n", error_get_pretty(error));
5c3c6a68 1682 error_free(error);
2d64255b
AF		 1683 if (cpu != NULL) {
1684 object_unref(OBJECT(cpu));
1685 cpu = NULL;
1686 }
5c3c6a68
AF		 1687 }
1688 return cpu;
1689}
1690
c6dc6f63 1691#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1692
0e26b7b8
BS		 1693void cpu_clear_apic_feature(CPUX86State *env)
1694{
1695 env->cpuid_features &= ~CPUID_APIC;
1696}
1697
c6dc6f63
AP		 1698#endif /* !CONFIG_USER_ONLY */
1699
c04321b3 1700/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1701 */
1702void x86_cpudef_setup(void)
1703{
93bfef4c
CV		 1704 int i, j;
1705 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1706
1707 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291 1708 x86_def_t *def = &builtin_x86_defs[i];
93bfef4c
CV		 1709
1710 /* Look for specific "cpudef" models that */
09faecf2 1711 /* have the QEMU version in .model_id */
93bfef4c 1712 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1713 if (strcmp(model_with_versions[j], def->name) == 0) {
1714 pstrcpy(def->model_id, sizeof(def->model_id),
1715 "QEMU Virtual CPU version ");
1716 pstrcat(def->model_id, sizeof(def->model_id),
1717 qemu_get_version());
93bfef4c
CV		 1718 break;
1719 }
1720 }
c6dc6f63 1721 }
c6dc6f63
AP		 1722}
1723
c6dc6f63
AP		 1724static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1725 uint32_t *ecx, uint32_t *edx)
1726{
1727 *ebx = env->cpuid_vendor1;
1728 *edx = env->cpuid_vendor2;
1729 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 1730}
1731
1732void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1733 uint32_t *eax, uint32_t *ebx,
1734 uint32_t *ecx, uint32_t *edx)
1735{
a60f24b5
AF		 1736 X86CPU *cpu = x86_env_get_cpu(env);
1737 CPUState *cs = CPU(cpu);
1738
c6dc6f63
AP		 1739 /* test if maximum index reached */
1740 if (index & 0x80000000) {
b3baa152
BW		 1741 if (index > env->cpuid_xlevel) {
1742 if (env->cpuid_xlevel2 > 0) {
1743 /* Handle the Centaur's CPUID instruction. */
1744 if (index > env->cpuid_xlevel2) {
1745 index = env->cpuid_xlevel2;
1746 } else if (index < 0xC0000000) {
1747 index = env->cpuid_xlevel;
1748 }
1749 } else {
57f26ae7
EH		 1750 /* Intel documentation states that invalid EAX input will
1751 * return the same information as EAX=cpuid_level
1752 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1753 */
1754 index = env->cpuid_level;
b3baa152
BW		 1755 }
1756 }
c6dc6f63
AP		 1757 } else {
1758 if (index > env->cpuid_level)
1759 index = env->cpuid_level;
1760 }
1761
1762 switch(index) {
1763 case 0:
1764 *eax = env->cpuid_level;
1765 get_cpuid_vendor(env, ebx, ecx, edx);
1766 break;
1767 case 1:
1768 *eax = env->cpuid_version;
1769 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1770 *ecx = env->cpuid_ext_features;
1771 *edx = env->cpuid_features;
ce3960eb
AF		 1772 if (cs->nr_cores * cs->nr_threads > 1) {
1773 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 1774 *edx |= 1 << 28; /* HTT bit */
1775 }
1776 break;
1777 case 2:
1778 /* cache info: needed for Pentium Pro compatibility */
1779 *eax = 1;
1780 *ebx = 0;
1781 *ecx = 0;
1782 *edx = 0x2c307d;
1783 break;
1784 case 4:
1785 /* cache info: needed for Core compatibility */
ce3960eb
AF		 1786 if (cs->nr_cores > 1) {
1787 *eax = (cs->nr_cores - 1) << 26;
c6dc6f63 1788 } else {
2f7a21c4 1789 *eax = 0;
c6dc6f63
AP		 1790 }
1791 switch (count) {
1792 case 0: /* L1 dcache info */
1793 *eax |= 0x0000121;
1794 *ebx = 0x1c0003f;
1795 *ecx = 0x000003f;
1796 *edx = 0x0000001;
1797 break;
1798 case 1: /* L1 icache info */
1799 *eax |= 0x0000122;
1800 *ebx = 0x1c0003f;
1801 *ecx = 0x000003f;
1802 *edx = 0x0000001;
1803 break;
1804 case 2: /* L2 cache info */
1805 *eax |= 0x0000143;
ce3960eb
AF		 1806 if (cs->nr_threads > 1) {
1807 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63
AP		 1808 }
1809 *ebx = 0x3c0003f;
1810 *ecx = 0x0000fff;
1811 *edx = 0x0000001;
1812 break;
1813 default: /* end of info */
1814 *eax = 0;
1815 *ebx = 0;
1816 *ecx = 0;
1817 *edx = 0;
1818 break;
1819 }
1820 break;
1821 case 5:
1822 /* mwait info: needed for Core compatibility */
1823 *eax = 0; /* Smallest monitor-line size in bytes */
1824 *ebx = 0; /* Largest monitor-line size in bytes */
1825 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1826 *edx = 0;
1827 break;
1828 case 6:
1829 /* Thermal and Power Leaf */
1830 *eax = 0;
1831 *ebx = 0;
1832 *ecx = 0;
1833 *edx = 0;
1834 break;
f7911686 1835 case 7:
13526728
EH		 1836 /* Structured Extended Feature Flags Enumeration Leaf */
1837 if (count == 0) {
1838 *eax = 0; /* Maximum ECX value for sub-leaves */
a9321a4d 1839 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
13526728
EH		 1840 *ecx = 0; /* Reserved */
1841 *edx = 0; /* Reserved */
f7911686
YW		 1842 } else {
1843 *eax = 0;
1844 *ebx = 0;
1845 *ecx = 0;
1846 *edx = 0;
1847 }
1848 break;
c6dc6f63
AP		 1849 case 9:
1850 /* Direct Cache Access Information Leaf */
1851 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1852 *ebx = 0;
1853 *ecx = 0;
1854 *edx = 0;
1855 break;
1856 case 0xA:
1857 /* Architectural Performance Monitoring Leaf */
a0fa8208 1858 if (kvm_enabled()) {
a60f24b5 1859 KVMState *s = cs->kvm_state;
a0fa8208
GN		 1860
1861 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1862 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1863 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1864 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1865 } else {
1866 *eax = 0;
1867 *ebx = 0;
1868 *ecx = 0;
1869 *edx = 0;
1870 }
c6dc6f63 1871 break;
51e49430
SY		 1872 case 0xD:
1873 /* Processor Extended State */
1874 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1875 *eax = 0;
1876 *ebx = 0;
1877 *ecx = 0;
1878 *edx = 0;
1879 break;
1880 }
1881 if (kvm_enabled()) {
a60f24b5 1882 KVMState *s = cs->kvm_state;
ba9bc59e
JK		 1883
1884 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1885 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1886 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1887 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1888 } else {
1889 *eax = 0;
1890 *ebx = 0;
1891 *ecx = 0;
1892 *edx = 0;
1893 }
1894 break;
c6dc6f63
AP		 1895 case 0x80000000:
1896 *eax = env->cpuid_xlevel;
1897 *ebx = env->cpuid_vendor1;
1898 *edx = env->cpuid_vendor2;
1899 *ecx = env->cpuid_vendor3;
1900 break;
1901 case 0x80000001:
1902 *eax = env->cpuid_version;
1903 *ebx = 0;
1904 *ecx = env->cpuid_ext3_features;
1905 *edx = env->cpuid_ext2_features;
1906
1907 /* The Linux kernel checks for the CMPLegacy bit and
1908 * discards multiple thread information if it is set.
1909 * So dont set it here for Intel to make Linux guests happy.
1910 */
ce3960eb 1911 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 1912 uint32_t tebx, tecx, tedx;
1913 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1914 if (tebx != CPUID_VENDOR_INTEL_1 ||
1915 tedx != CPUID_VENDOR_INTEL_2 ||
1916 tecx != CPUID_VENDOR_INTEL_3) {
1917 *ecx |= 1 << 1; /* CmpLegacy bit */
1918 }
1919 }
c6dc6f63
AP		 1920 break;
1921 case 0x80000002:
1922 case 0x80000003:
1923 case 0x80000004:
1924 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1925 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1926 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1927 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1928 break;
1929 case 0x80000005:
1930 /* cache info (L1 cache) */
1931 *eax = 0x01ff01ff;
1932 *ebx = 0x01ff01ff;
1933 *ecx = 0x40020140;
1934 *edx = 0x40020140;
1935 break;
1936 case 0x80000006:
1937 /* cache info (L2 cache) */
1938 *eax = 0;
1939 *ebx = 0x42004200;
1940 *ecx = 0x02008140;
1941 *edx = 0;
1942 break;
1943 case 0x80000008:
1944 /* virtual & phys address size in low 2 bytes. */
1945/* XXX: This value must match the one used in the MMU code. */
1946 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1947 /* 64 bit processor */
1948/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 1949 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 1950 } else {
dd13e088 1951 if (env->cpuid_features & CPUID_PSE36) {
c6dc6f63 1952 *eax = 0x00000024; /* 36 bits physical */
dd13e088 1953 } else {
c6dc6f63 1954 *eax = 0x00000020; /* 32 bits physical */
dd13e088 1955 }
c6dc6f63
AP		 1956 }
1957 *ebx = 0;
1958 *ecx = 0;
1959 *edx = 0;
ce3960eb
AF		 1960 if (cs->nr_cores * cs->nr_threads > 1) {
1961 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 1962 }
1963 break;
1964 case 0x8000000A:
9f3fb565
EH		 1965 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1966 *eax = 0x00000001; /* SVM Revision */
1967 *ebx = 0x00000010; /* nr of ASIDs */
1968 *ecx = 0;
1969 *edx = env->cpuid_svm_features; /* optional features */
1970 } else {
1971 *eax = 0;
1972 *ebx = 0;
1973 *ecx = 0;
1974 *edx = 0;
1975 }
c6dc6f63 1976 break;
b3baa152
BW		 1977 case 0xC0000000:
1978 *eax = env->cpuid_xlevel2;
1979 *ebx = 0;
1980 *ecx = 0;
1981 *edx = 0;
1982 break;
1983 case 0xC0000001:
1984 /* Support for VIA CPU's CPUID instruction */
1985 *eax = env->cpuid_version;
1986 *ebx = 0;
1987 *ecx = 0;
1988 *edx = env->cpuid_ext4_features;
1989 break;
1990 case 0xC0000002:
1991 case 0xC0000003:
1992 case 0xC0000004:
1993 /* Reserved for the future, and now filled with zero */
1994 *eax = 0;
1995 *ebx = 0;
1996 *ecx = 0;
1997 *edx = 0;
1998 break;
c6dc6f63
AP		 1999 default:
2000 /* reserved values: zero */
2001 *eax = 0;
2002 *ebx = 0;
2003 *ecx = 0;
2004 *edx = 0;
2005 break;
2006 }
2007}
5fd2087a
AF		 2008
2009/* CPUClass::reset() */
2010static void x86_cpu_reset(CPUState *s)
2011{
2012 X86CPU *cpu = X86_CPU(s);
2013 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2014 CPUX86State *env = &cpu->env;
c1958aea
AF		 2015 int i;
2016
2017 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 2018 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
6fd2a026 2019 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
c1958aea 2020 }
5fd2087a
AF		 2021
2022 xcc->parent_reset(s);
2023
c1958aea
AF		 2024
2025 memset(env, 0, offsetof(CPUX86State, breakpoints));
2026
2027 tlb_flush(env, 1);
2028
2029 env->old_exception = -1;
2030
2031 /* init to reset state */
2032
2033#ifdef CONFIG_SOFTMMU
2034 env->hflags |= HF_SOFTMMU_MASK;
2035#endif
2036 env->hflags2 |= HF2_GIF_MASK;
2037
2038 cpu_x86_update_cr0(env, 0x60000010);
2039 env->a20_mask = ~0x0;
2040 env->smbase = 0x30000;
2041
2042 env->idt.limit = 0xffff;
2043 env->gdt.limit = 0xffff;
2044 env->ldt.limit = 0xffff;
2045 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2046 env->tr.limit = 0xffff;
2047 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2048
2049 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2050 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2051 DESC_R_MASK | DESC_A_MASK);
2052 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2053 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2054 DESC_A_MASK);
2055 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2056 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2057 DESC_A_MASK);
2058 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2059 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2060 DESC_A_MASK);
2061 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2062 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2063 DESC_A_MASK);
2064 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2065 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2066 DESC_A_MASK);
2067
2068 env->eip = 0xfff0;
2069 env->regs[R_EDX] = env->cpuid_version;
2070
2071 env->eflags = 0x2;
2072
2073 /* FPU init */
2074 for (i = 0; i < 8; i++) {
2075 env->fptags[i] = 1;
2076 }
2077 env->fpuc = 0x37f;
2078
2079 env->mxcsr = 0x1f80;
2080
2081 env->pat = 0x0007040600070406ULL;
2082 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2083
2084 memset(env->dr, 0, sizeof(env->dr));
2085 env->dr[6] = DR6_FIXED_1;
2086 env->dr[7] = DR7_FIXED_1;
2087 cpu_breakpoint_remove_all(env, BP_CPU);
2088 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 2089
2090#if !defined(CONFIG_USER_ONLY)
2091 /* We hard-wire the BSP to the first CPU. */
55e5c285 2092 if (s->cpu_index == 0) {
dd673288
IM		 2093 apic_designate_bsp(env->apic_state);
2094 }
2095
259186a7 2096 s->halted = !cpu_is_bsp(cpu);
dd673288 2097#endif
5fd2087a
AF		 2098}
2099
dd673288
IM		 2100#ifndef CONFIG_USER_ONLY
2101bool cpu_is_bsp(X86CPU *cpu)
2102{
2103 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2104}
65dee380
IM		 2105
2106/* TODO: remove me, when reset over QOM tree is implemented */
2107static void x86_cpu_machine_reset_cb(void *opaque)
2108{
2109 X86CPU *cpu = opaque;
2110 cpu_reset(CPU(cpu));
2111}
dd673288
IM		 2112#endif
2113
de024815
AF		 2114static void mce_init(X86CPU *cpu)
2115{
2116 CPUX86State *cenv = &cpu->env;
2117 unsigned int bank;
2118
2119 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2120 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2121 (CPUID_MCE | CPUID_MCA)) {
2122 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2123 cenv->mcg_ctl = ~(uint64_t)0;
2124 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2125 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2126 }
2127 }
2128}
2129
bdeec802 2130#ifndef CONFIG_USER_ONLY
d3c64d6a 2131static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2132{
bdeec802 2133 CPUX86State *env = &cpu->env;
449994eb 2134 APICCommonState *apic;
bdeec802
IM		 2135 const char *apic_type = "apic";
2136
2137 if (kvm_irqchip_in_kernel()) {
2138 apic_type = "kvm-apic";
2139 } else if (xen_enabled()) {
2140 apic_type = "xen-apic";
2141 }
2142
2143 env->apic_state = qdev_try_create(NULL, apic_type);
2144 if (env->apic_state == NULL) {
2145 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2146 return;
2147 }
2148
2149 object_property_add_child(OBJECT(cpu), "apic",
2150 OBJECT(env->apic_state), NULL);
2151 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2152 /* TODO: convert to link<> */
449994eb 2153 apic = APIC_COMMON(env->apic_state);
60671e58 2154 apic->cpu = cpu;
d3c64d6a
IM		 2155}
2156
2157static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2158{
2159 CPUX86State *env = &cpu->env;
2160 static int apic_mapped;
2161
2162 if (env->apic_state == NULL) {
2163 return;
2164 }
bdeec802
IM		 2165
2166 if (qdev_init(env->apic_state)) {
2167 error_setg(errp, "APIC device '%s' could not be initialized",
2168 object_get_typename(OBJECT(env->apic_state)));
2169 return;
2170 }
2171
2172 /* XXX: mapping more APICs at the same memory location */
2173 if (apic_mapped == 0) {
2174 /* NOTE: the APIC is directly connected to the CPU - it is not
2175 on the global memory bus. */
2176 /* XXX: what if the base changes? */
7feb640c 2177 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(env->apic_state), 0,
dab86234 2178 APIC_DEFAULT_ADDRESS, 0x1000);
bdeec802
IM		 2179 apic_mapped = 1;
2180 }
2181}
d3c64d6a
IM		 2182#else
2183static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2184{
2185}
bdeec802
IM		 2186#endif
2187
2b6f294c 2188static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2189{
2b6f294c
AF		 2190 X86CPU *cpu = X86_CPU(dev);
2191 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2192 CPUX86State *env = &cpu->env;
2b6f294c 2193 Error *local_err = NULL;
b34d12d1
IM		 2194
2195 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2196 env->cpuid_level = 7;
2197 }
7a059953 2198
9b15cd9e
IM		 2199 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2200 * CPUID[1].EDX.
2201 */
2202 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2203 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2204 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2205 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2206 env->cpuid_ext2_features |= (env->cpuid_features
2207 & CPUID_EXT2_AMD_ALIASES);
2208 }
2209
4586f157
IM		 2210 if (!kvm_enabled()) {
2211 env->cpuid_features &= TCG_FEATURES;
2212 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2213 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2214#ifdef TARGET_X86_64
2215 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2216#endif
2217 );
2218 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2219 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2220 } else {
5ec01c2e
IM		 2221 if (check_cpuid && kvm_check_features_against_host(cpu)
2222 && enforce_cpuid) {
4dc1f449
IM		 2223 error_setg(&local_err,
2224 "Host's CPU doesn't support requested features");
2225 goto out;
5ec01c2e 2226 }
a509d632
EH		 2227#ifdef CONFIG_KVM
2228 filter_features_for_kvm(cpu);
2229#endif
4586f157
IM		 2230 }
2231
65dee380
IM		 2232#ifndef CONFIG_USER_ONLY
2233 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802
IM		 2234
2235 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2236 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2237 if (local_err != NULL) {
4dc1f449 2238 goto out;
bdeec802
IM		 2239 }
2240 }
65dee380
IM		 2241#endif
2242
7a059953
AF		 2243 mce_init(cpu);
2244 qemu_init_vcpu(&cpu->env);
d3c64d6a
IM		 2245
2246 x86_cpu_apic_realize(cpu, &local_err);
2247 if (local_err != NULL) {
2248 goto out;
2249 }
65dee380 2250 cpu_reset(CPU(cpu));
2b6f294c 2251
4dc1f449
IM		 2252 xcc->parent_realize(dev, &local_err);
2253out:
2254 if (local_err != NULL) {
2255 error_propagate(errp, local_err);
2256 return;
2257 }
7a059953
AF		 2258}
2259
8932cfdf
EH		 2260/* Enables contiguous-apic-ID mode, for compatibility */
2261static bool compat_apic_id_mode;
2262
2263void enable_compat_apic_id_mode(void)
2264{
2265 compat_apic_id_mode = true;
2266}
2267
cb41bad3
EH		 2268/* Calculates initial APIC ID for a specific CPU index
2269 *
2270 * Currently we need to be able to calculate the APIC ID from the CPU index
2271 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2272 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2273 * all CPUs up to max_cpus.
2274 */
2275uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2276{
8932cfdf
EH		 2277 uint32_t correct_id;
2278 static bool warned;
2279
2280 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2281 if (compat_apic_id_mode) {
2282 if (cpu_index != correct_id && !warned) {
2283 error_report("APIC IDs set in compatibility mode, "
2284 "CPU topology won't match the configuration");
2285 warned = true;
2286 }
2287 return cpu_index;
2288 } else {
2289 return correct_id;
2290 }
cb41bad3
EH		 2291}
2292
de024815
AF		 2293static void x86_cpu_initfn(Object *obj)
2294{
55e5c285 2295 CPUState *cs = CPU(obj);
de024815
AF		 2296 X86CPU *cpu = X86_CPU(obj);
2297 CPUX86State *env = &cpu->env;
d65e9815 2298 static int inited;
de024815 2299
c05efcb1 2300 cs->env_ptr = env;
de024815 2301 cpu_exec_init(env);
71ad61d3
AF		 2302
2303 object_property_add(obj, "family", "int",
95b8519d 2304 x86_cpuid_version_get_family,
71ad61d3 2305 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2306 object_property_add(obj, "model", "int",
67e30c83 2307 x86_cpuid_version_get_model,
c5291a4f 2308 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2309 object_property_add(obj, "stepping", "int",
35112e41 2310 x86_cpuid_version_get_stepping,
036e2222 2311 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2312 object_property_add(obj, "level", "int",
2313 x86_cpuid_get_level,
2314 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2315 object_property_add(obj, "xlevel", "int",
2316 x86_cpuid_get_xlevel,
2317 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2318 object_property_add_str(obj, "vendor",
2319 x86_cpuid_get_vendor,
2320 x86_cpuid_set_vendor, NULL);
938d4c25 2321 object_property_add_str(obj, "model-id",
63e886eb 2322 x86_cpuid_get_model_id,
938d4c25 2323 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2324 object_property_add(obj, "tsc-frequency", "int",
2325 x86_cpuid_get_tsc_freq,
2326 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2327 object_property_add(obj, "apic-id", "int",
2328 x86_cpuid_get_apic_id,
2329 x86_cpuid_set_apic_id, NULL, NULL, NULL);
71ad61d3 2330
cb41bad3 2331 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815
IM		 2332
2333 /* init various static tables used in TCG mode */
2334 if (tcg_enabled() && !inited) {
2335 inited = 1;
2336 optimize_flags_init();
2337#ifndef CONFIG_USER_ONLY
2338 cpu_set_debug_excp_handler(breakpoint_handler);
2339#endif
2340 }
de024815
AF		 2341}
2342
997395d3
IM		 2343static int64_t x86_cpu_get_arch_id(CPUState *cs)
2344{
2345 X86CPU *cpu = X86_CPU(cs);
2346 CPUX86State *env = &cpu->env;
2347
2348 return env->cpuid_apic_id;
2349}
2350
5fd2087a
AF		 2351static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2352{
2353 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2354 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2355 DeviceClass *dc = DEVICE_CLASS(oc);
2356
2357 xcc->parent_realize = dc->realize;
2358 dc->realize = x86_cpu_realizefn;
62fc403f 2359 dc->bus_type = TYPE_ICC_BUS;
5fd2087a
AF		 2360
2361 xcc->parent_reset = cc->reset;
2362 cc->reset = x86_cpu_reset;
f56e3a14 2363
97a8ea5a 2364 cc->do_interrupt = x86_cpu_do_interrupt;
c72bf468
JF		 2365#ifndef CONFIG_USER_ONLY
2366 cc->write_elf64_note = x86_cpu_write_elf64_note;
2367 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2368 cc->write_elf32_note = x86_cpu_write_elf32_note;
2369 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2370#endif
f56e3a14 2371 cpu_class_set_vmsd(cc, &vmstate_x86_cpu);
997395d3
IM		 2372
2373 cc->get_arch_id = x86_cpu_get_arch_id;
5fd2087a
AF		 2374}
2375
2376static const TypeInfo x86_cpu_type_info = {
2377 .name = TYPE_X86_CPU,
2378 .parent = TYPE_CPU,
2379 .instance_size = sizeof(X86CPU),
de024815 2380 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2381 .abstract = false,
2382 .class_size = sizeof(X86CPUClass),
2383 .class_init = x86_cpu_common_class_init,
2384};
2385
2386static void x86_cpu_register_types(void)
2387{
2388 type_register_static(&x86_cpu_type_info);
2389}
2390
2391type_init(x86_cpu_register_types)
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