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KVM: Use u64 for frame data types
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
221d059d 8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
cdc0e244
AK		 72#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74#define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 77 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 78#define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 80#define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
82 | X86_CR4_OSXMMEXCPT)
83
cdc0e244
AK		 84#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
86
78ac8b47
AK		 87#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
88
4b8d54f9
ZE		 89/*
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
99 */
100#define KVM_VMX_DEFAULT_PLE_GAP 41
101#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103module_param(ple_gap, int, S_IRUGO);
104
105static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106module_param(ple_window, int, S_IRUGO);
107
61d2ef2c
AK		 108#define NR_AUTOLOAD_MSRS 1
109
a2fa3e9f
GH		 110struct vmcs {
111 u32 revision_id;
112 u32 abort;
113 char data[0];
114};
115
26bb0981
AK		 116struct shared_msr_entry {
117 unsigned index;
118 u64 data;
d5696725 119 u64 mask;
26bb0981
AK		 120};
121
a2fa3e9f 122struct vcpu_vmx {
fb3f0f51 123 struct kvm_vcpu vcpu;
543e4243 124 struct list_head local_vcpus_link;
313dbd49 125 unsigned long host_rsp;
a2fa3e9f 126 int launched;
29bd8a78 127 u8 fail;
1155f76a 128 u32 idt_vectoring_info;
26bb0981 129 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 130 int nmsrs;
131 int save_nmsrs;
a2fa3e9f 132#ifdef CONFIG_X86_64
44ea2b17
AK		 133 u64 msr_host_kernel_gs_base;
134 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 135#endif
136 struct vmcs *vmcs;
61d2ef2c
AK		 137 struct msr_autoload {
138 unsigned nr;
139 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
140 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
141 } msr_autoload;
a2fa3e9f
GH		 142 struct {
143 int loaded;
144 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 145 int gs_ldt_reload_needed;
146 int fs_reload_needed;
d77c26fc 147 } host_state;
9c8cba37 148 struct {
7ffd92c5 149 int vm86_active;
78ac8b47 150 ulong save_rflags;
7ffd92c5
AK		 151 struct kvm_save_segment {
152 u16 selector;
153 unsigned long base;
154 u32 limit;
155 u32 ar;
156 } tr, es, ds, fs, gs;
9c8cba37
AK		 157 struct {
158 bool pending;
159 u8 vector;
160 unsigned rip;
161 } irq;
162 } rmode;
2384d2b3 163 int vpid;
04fa4d32 164 bool emulation_required;
3b86cd99
JK		 165
166 /* Support for vnmi-less CPUs */
167 int soft_vnmi_blocked;
168 ktime_t entry_time;
169 s64 vnmi_blocked_time;
a0861c02 170 u32 exit_reason;
4e47c7a6
SY		 171
172 bool rdtscp_enabled;
a2fa3e9f
GH		 173};
174
175static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
176{
fb3f0f51 177 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 178}
179
b7ebfb05 180static int init_rmode(struct kvm *kvm);
4e1096d2 181static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 182static void kvm_cpu_vmxon(u64 addr);
183static void kvm_cpu_vmxoff(void);
75880a01 184
6aa8b732
AK		 185static DEFINE_PER_CPU(struct vmcs *, vmxarea);
186static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 187static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 188
3e7c73e9
AK		 189static unsigned long *vmx_io_bitmap_a;
190static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 191static unsigned long *vmx_msr_bitmap_legacy;
192static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 193
2384d2b3
SY		 194static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
195static DEFINE_SPINLOCK(vmx_vpid_lock);
196
1c3d14fe 197static struct vmcs_config {
6aa8b732
AK		 198 int size;
199 int order;
200 u32 revision_id;
1c3d14fe
YS		 201 u32 pin_based_exec_ctrl;
202 u32 cpu_based_exec_ctrl;
f78e0e2e 203 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 204 u32 vmexit_ctrl;
205 u32 vmentry_ctrl;
206} vmcs_config;
6aa8b732 207
efff9e53 208static struct vmx_capability {
d56f546d
SY		 209 u32 ept;
210 u32 vpid;
211} vmx_capability;
212
6aa8b732
AK		 213#define VMX_SEGMENT_FIELD(seg) \
214 [VCPU_SREG_##seg] = { \
215 .selector = GUEST_##seg##_SELECTOR, \
216 .base = GUEST_##seg##_BASE, \
217 .limit = GUEST_##seg##_LIMIT, \
218 .ar_bytes = GUEST_##seg##_AR_BYTES, \
219 }
220
221static struct kvm_vmx_segment_field {
222 unsigned selector;
223 unsigned base;
224 unsigned limit;
225 unsigned ar_bytes;
226} kvm_vmx_segment_fields[] = {
227 VMX_SEGMENT_FIELD(CS),
228 VMX_SEGMENT_FIELD(DS),
229 VMX_SEGMENT_FIELD(ES),
230 VMX_SEGMENT_FIELD(FS),
231 VMX_SEGMENT_FIELD(GS),
232 VMX_SEGMENT_FIELD(SS),
233 VMX_SEGMENT_FIELD(TR),
234 VMX_SEGMENT_FIELD(LDTR),
235};
236
26bb0981
AK		 237static u64 host_efer;
238
6de4f3ad
AK		 239static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
240
4d56c8a7
AK		 241/*
242 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
243 * away by decrementing the array size.
244 */
6aa8b732 245static const u32 vmx_msr_index[] = {
05b3e0c2 246#ifdef CONFIG_X86_64
44ea2b17 247 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 248#endif
4e47c7a6 249 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
6aa8b732 250};
9d8f549d 251#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 252
31299944 253static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 254{
255 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
256 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 257 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 258}
259
31299944 260static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 261{
262 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
263 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 264 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 265}
266
31299944 267static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 268{
269 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
270 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 271 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 272}
273
31299944 274static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 275{
276 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
277 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
278}
279
31299944 280static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 281{
282 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
283 INTR_INFO_VALID_MASK)) ==
284 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
285}
286
31299944 287static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 288{
04547156 289 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 290}
291
31299944 292static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 293{
04547156 294 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 295}
296
31299944 297static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 298{
04547156 299 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 300}
301
31299944 302static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 303{
04547156
SY		 304 return vmcs_config.cpu_based_exec_ctrl &
305 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 306}
307
774ead3a 308static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 309{
04547156
SY		 310 return vmcs_config.cpu_based_2nd_exec_ctrl &
311 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
312}
313
314static inline bool cpu_has_vmx_flexpriority(void)
315{
316 return cpu_has_vmx_tpr_shadow() &&
317 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 318}
319
e799794e
MT		 320static inline bool cpu_has_vmx_ept_execute_only(void)
321{
31299944 322 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 323}
324
325static inline bool cpu_has_vmx_eptp_uncacheable(void)
326{
31299944 327 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 328}
329
330static inline bool cpu_has_vmx_eptp_writeback(void)
331{
31299944 332 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 333}
334
335static inline bool cpu_has_vmx_ept_2m_page(void)
336{
31299944 337 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 338}
339
878403b7
SY		 340static inline bool cpu_has_vmx_ept_1g_page(void)
341{
31299944 342 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 343}
344
4bc9b982
SY		 345static inline bool cpu_has_vmx_ept_4levels(void)
346{
347 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
348}
349
31299944 350static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 351{
31299944 352 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 353}
354
31299944 355static inline bool cpu_has_vmx_invept_context(void)
d56f546d 356{
31299944 357 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 358}
359
31299944 360static inline bool cpu_has_vmx_invept_global(void)
d56f546d 361{
31299944 362 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 363}
364
518c8aee
GJ		 365static inline bool cpu_has_vmx_invvpid_single(void)
366{
367 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
368}
369
b9d762fa
GJ		 370static inline bool cpu_has_vmx_invvpid_global(void)
371{
372 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
373}
374
31299944 375static inline bool cpu_has_vmx_ept(void)
d56f546d 376{
04547156
SY		 377 return vmcs_config.cpu_based_2nd_exec_ctrl &
378 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 379}
380
31299944 381static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 382{
383 return vmcs_config.cpu_based_2nd_exec_ctrl &
384 SECONDARY_EXEC_UNRESTRICTED_GUEST;
385}
386
31299944 387static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 388{
389 return vmcs_config.cpu_based_2nd_exec_ctrl &
390 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
391}
392
31299944 393static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 394{
6d3e435e 395 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 396}
397
31299944 398static inline bool cpu_has_vmx_vpid(void)
2384d2b3 399{
04547156
SY		 400 return vmcs_config.cpu_based_2nd_exec_ctrl &
401 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 402}
403
31299944 404static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 405{
406 return vmcs_config.cpu_based_2nd_exec_ctrl &
407 SECONDARY_EXEC_RDTSCP;
408}
409
31299944 410static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 411{
412 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
413}
414
f5f48ee1
SY		 415static inline bool cpu_has_vmx_wbinvd_exit(void)
416{
417 return vmcs_config.cpu_based_2nd_exec_ctrl &
418 SECONDARY_EXEC_WBINVD_EXITING;
419}
420
04547156
SY		 421static inline bool report_flexpriority(void)
422{
423 return flexpriority_enabled;
424}
425
8b9cf98c 426static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 427{
428 int i;
429
a2fa3e9f 430 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 431 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 432 return i;
433 return -1;
434}
435
2384d2b3
SY		 436static inline void __invvpid(int ext, u16 vpid, gva_t gva)
437{
438 struct {
439 u64 vpid : 16;
440 u64 rsvd : 48;
441 u64 gva;
442 } operand = { vpid, 0, gva };
443
4ecac3fd 444 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 445 /* CF==1 or ZF==1 --> rc = -1 */
446 "; ja 1f ; ud2 ; 1:"
447 : : "a"(&operand), "c"(ext) : "cc", "memory");
448}
449
1439442c
SY		 450static inline void __invept(int ext, u64 eptp, gpa_t gpa)
451{
452 struct {
453 u64 eptp, gpa;
454 } operand = {eptp, gpa};
455
4ecac3fd 456 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 457 /* CF==1 or ZF==1 --> rc = -1 */
458 "; ja 1f ; ud2 ; 1:\n"
459 : : "a" (&operand), "c" (ext) : "cc", "memory");
460}
461
26bb0981 462static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 463{
464 int i;
465
8b9cf98c 466 i = __find_msr_index(vmx, msr);
a75beee6 467 if (i >= 0)
a2fa3e9f 468 return &vmx->guest_msrs[i];
8b6d44c7 469 return NULL;
7725f0ba
AK		 470}
471
6aa8b732
AK		 472static void vmcs_clear(struct vmcs *vmcs)
473{
474 u64 phys_addr = __pa(vmcs);
475 u8 error;
476
4ecac3fd 477 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 478 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
479 : "cc", "memory");
480 if (error)
481 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
482 vmcs, phys_addr);
483}
484
7725b894
DX		 485static void vmcs_load(struct vmcs *vmcs)
486{
487 u64 phys_addr = __pa(vmcs);
488 u8 error;
489
490 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
491 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
492 : "cc", "memory");
493 if (error)
494 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
495 vmcs, phys_addr);
496}
497
6aa8b732
AK		 498static void __vcpu_clear(void *arg)
499{
8b9cf98c 500 struct vcpu_vmx *vmx = arg;
d3b2c338 501 int cpu = raw_smp_processor_id();
6aa8b732 502
8b9cf98c 503 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 504 vmcs_clear(vmx->vmcs);
505 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 506 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 507 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 508 list_del(&vmx->local_vcpus_link);
509 vmx->vcpu.cpu = -1;
510 vmx->launched = 0;
6aa8b732
AK		 511}
512
8b9cf98c 513static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 514{
eae5ecb5
AK		 515 if (vmx->vcpu.cpu == -1)
516 return;
8691e5a8 517 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 518}
519
1760dd49 520static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 521{
522 if (vmx->vpid == 0)
523 return;
524
518c8aee
GJ		 525 if (cpu_has_vmx_invvpid_single())
526 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 527}
528
b9d762fa
GJ		 529static inline void vpid_sync_vcpu_global(void)
530{
531 if (cpu_has_vmx_invvpid_global())
532 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
533}
534
535static inline void vpid_sync_context(struct vcpu_vmx *vmx)
536{
537 if (cpu_has_vmx_invvpid_single())
1760dd49 538 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 539 else
540 vpid_sync_vcpu_global();
541}
542
1439442c
SY		 543static inline void ept_sync_global(void)
544{
545 if (cpu_has_vmx_invept_global())
546 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
547}
548
549static inline void ept_sync_context(u64 eptp)
550{
089d034e 551 if (enable_ept) {
1439442c
SY		 552 if (cpu_has_vmx_invept_context())
553 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
554 else
555 ept_sync_global();
556 }
557}
558
559static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
560{
089d034e 561 if (enable_ept) {
1439442c
SY		 562 if (cpu_has_vmx_invept_individual_addr())
563 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
564 eptp, gpa);
565 else
566 ept_sync_context(eptp);
567 }
568}
569
6aa8b732
AK		 570static unsigned long vmcs_readl(unsigned long field)
571{
572 unsigned long value;
573
4ecac3fd 574 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 575 : "=a"(value) : "d"(field) : "cc");
576 return value;
577}
578
579static u16 vmcs_read16(unsigned long field)
580{
581 return vmcs_readl(field);
582}
583
584static u32 vmcs_read32(unsigned long field)
585{
586 return vmcs_readl(field);
587}
588
589static u64 vmcs_read64(unsigned long field)
590{
05b3e0c2 591#ifdef CONFIG_X86_64
6aa8b732
AK		 592 return vmcs_readl(field);
593#else
594 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
595#endif
596}
597
e52de1b8
AK		 598static noinline void vmwrite_error(unsigned long field, unsigned long value)
599{
600 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
601 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
602 dump_stack();
603}
604
6aa8b732
AK		 605static void vmcs_writel(unsigned long field, unsigned long value)
606{
607 u8 error;
608
4ecac3fd 609 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 610 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 611 if (unlikely(error))
612 vmwrite_error(field, value);
6aa8b732
AK		 613}
614
615static void vmcs_write16(unsigned long field, u16 value)
616{
617 vmcs_writel(field, value);
618}
619
620static void vmcs_write32(unsigned long field, u32 value)
621{
622 vmcs_writel(field, value);
623}
624
625static void vmcs_write64(unsigned long field, u64 value)
626{
6aa8b732 627 vmcs_writel(field, value);
7682f2d0 628#ifndef CONFIG_X86_64
6aa8b732
AK		 629 asm volatile ("");
630 vmcs_writel(field+1, value >> 32);
631#endif
632}
633
2ab455cc
AL		 634static void vmcs_clear_bits(unsigned long field, u32 mask)
635{
636 vmcs_writel(field, vmcs_readl(field) & ~mask);
637}
638
639static void vmcs_set_bits(unsigned long field, u32 mask)
640{
641 vmcs_writel(field, vmcs_readl(field) | mask);
642}
643
abd3f2d6
AK		 644static void update_exception_bitmap(struct kvm_vcpu *vcpu)
645{
646 u32 eb;
647
fd7373cc
JK		 648 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
649 (1u << NM_VECTOR) | (1u << DB_VECTOR);
650 if ((vcpu->guest_debug &
651 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
652 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
653 eb |= 1u << BP_VECTOR;
7ffd92c5 654 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 655 eb = ~0;
089d034e 656 if (enable_ept)
1439442c 657 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 658 if (vcpu->fpu_active)
659 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 660 vmcs_write32(EXCEPTION_BITMAP, eb);
661}
662
61d2ef2c
AK		 663static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
664{
665 unsigned i;
666 struct msr_autoload *m = &vmx->msr_autoload;
667
668 for (i = 0; i < m->nr; ++i)
669 if (m->guest[i].index == msr)
670 break;
671
672 if (i == m->nr)
673 return;
674 --m->nr;
675 m->guest[i] = m->guest[m->nr];
676 m->host[i] = m->host[m->nr];
677 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
678 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
679}
680
681static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
682 u64 guest_val, u64 host_val)
683{
684 unsigned i;
685 struct msr_autoload *m = &vmx->msr_autoload;
686
687 for (i = 0; i < m->nr; ++i)
688 if (m->guest[i].index == msr)
689 break;
690
691 if (i == m->nr) {
692 ++m->nr;
693 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
694 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
695 }
696
697 m->guest[i].index = msr;
698 m->guest[i].value = guest_val;
699 m->host[i].index = msr;
700 m->host[i].value = host_val;
701}
702
33ed6329
AK		 703static void reload_tss(void)
704{
33ed6329
AK		 705 /*
706 * VT restores TR but not its size. Useless.
707 */
89a27f4d 708 struct desc_ptr gdt;
a5f61300 709 struct desc_struct *descs;
33ed6329 710
d6ab1ed4 711 native_store_gdt(&gdt);
89a27f4d 712 descs = (void *)gdt.address;
33ed6329
AK		 713 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
714 load_TR_desc();
33ed6329
AK		 715}
716
92c0d900 717static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 718{
3a34a881 719 u64 guest_efer;
51c6cf66
AK		 720 u64 ignore_bits;
721
f6801dff 722 guest_efer = vmx->vcpu.arch.efer;
3a34a881 723
51c6cf66
AK		 724 /*
725 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
726 * outside long mode
727 */
728 ignore_bits = EFER_NX | EFER_SCE;
729#ifdef CONFIG_X86_64
730 ignore_bits |= EFER_LMA | EFER_LME;
731 /* SCE is meaningful only in long mode on Intel */
732 if (guest_efer & EFER_LMA)
733 ignore_bits &= ~(u64)EFER_SCE;
734#endif
51c6cf66
AK		 735 guest_efer &= ~ignore_bits;
736 guest_efer |= host_efer & ignore_bits;
26bb0981 737 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 738 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 739
740 clear_atomic_switch_msr(vmx, MSR_EFER);
741 /* On ept, can't emulate nx, and must switch nx atomically */
742 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
743 guest_efer = vmx->vcpu.arch.efer;
744 if (!(guest_efer & EFER_LMA))
745 guest_efer &= ~EFER_LME;
746 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
747 return false;
748 }
749
26bb0981 750 return true;
51c6cf66
AK		 751}
752
2d49ec72
GN		 753static unsigned long segment_base(u16 selector)
754{
755 struct desc_ptr gdt;
756 struct desc_struct *d;
757 unsigned long table_base;
758 unsigned long v;
759
760 if (!(selector & ~3))
761 return 0;
762
763 native_store_gdt(&gdt);
764 table_base = gdt.address;
765
766 if (selector & 4) { /* from ldt */
767 u16 ldt_selector = kvm_read_ldt();
768
769 if (!(ldt_selector & ~3))
770 return 0;
771
772 table_base = segment_base(ldt_selector);
773 }
774 d = (struct desc_struct *)(table_base + (selector & ~7));
775 v = get_desc_base(d);
776#ifdef CONFIG_X86_64
777 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
778 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
779#endif
780 return v;
781}
782
783static inline unsigned long kvm_read_tr_base(void)
784{
785 u16 tr;
786 asm("str %0" : "=g"(tr));
787 return segment_base(tr);
788}
789
04d2cc77 790static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 791{
04d2cc77 792 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 793 int i;
04d2cc77 794
a2fa3e9f 795 if (vmx->host_state.loaded)
33ed6329
AK		 796 return;
797
a2fa3e9f 798 vmx->host_state.loaded = 1;
33ed6329
AK		 799 /*
800 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
801 * allow segment selectors with cpl > 0 or ti == 1.
802 */
d6e88aec 803 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 804 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 805 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 806 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 807 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 808 vmx->host_state.fs_reload_needed = 0;
809 } else {
33ed6329 810 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 811 vmx->host_state.fs_reload_needed = 1;
33ed6329 812 }
d6e88aec 813 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 814 if (!(vmx->host_state.gs_sel & 7))
815 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 816 else {
817 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 818 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 819 }
820
821#ifdef CONFIG_X86_64
822 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
823 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
824#else
a2fa3e9f
GH		 825 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
826 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 827#endif
707c0874
AK		 828
829#ifdef CONFIG_X86_64
44ea2b17
AK		 830 if (is_long_mode(&vmx->vcpu)) {
831 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
832 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
833 }
707c0874 834#endif
26bb0981
AK		 835 for (i = 0; i < vmx->save_nmsrs; ++i)
836 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 837 vmx->guest_msrs[i].data,
838 vmx->guest_msrs[i].mask);
33ed6329
AK		 839}
840
a9b21b62 841static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 842{
15ad7146 843 unsigned long flags;
33ed6329 844
a2fa3e9f 845 if (!vmx->host_state.loaded)
33ed6329
AK		 846 return;
847
e1beb1d3 848 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 849 vmx->host_state.loaded = 0;
152d3f2f 850 if (vmx->host_state.fs_reload_needed)
d6e88aec 851 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 852 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 853 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 854 /*
855 * If we have to reload gs, we must take care to
856 * preserve our gs base.
857 */
15ad7146 858 local_irq_save(flags);
d6e88aec 859 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 860#ifdef CONFIG_X86_64
861 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
862#endif
15ad7146 863 local_irq_restore(flags);
33ed6329 864 }
152d3f2f 865 reload_tss();
44ea2b17
AK		 866#ifdef CONFIG_X86_64
867 if (is_long_mode(&vmx->vcpu)) {
868 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
869 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
870 }
871#endif
1c11e713
AK		 872 if (current_thread_info()->status & TS_USEDFPU)
873 clts();
33ed6329
AK		 874}
875
a9b21b62
AK		 876static void vmx_load_host_state(struct vcpu_vmx *vmx)
877{
878 preempt_disable();
879 __vmx_load_host_state(vmx);
880 preempt_enable();
881}
882
6aa8b732
AK		 883/*
884 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
885 * vcpu mutex is already taken.
886 */
15ad7146 887static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 888{
a2fa3e9f 889 struct vcpu_vmx *vmx = to_vmx(vcpu);
019960ae 890 u64 tsc_this, delta, new_offset;
4610c9cc 891 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 892
4610c9cc
DX		 893 if (!vmm_exclusive)
894 kvm_cpu_vmxon(phys_addr);
895 else if (vcpu->cpu != cpu)
8b9cf98c 896 vcpu_clear(vmx);
6aa8b732 897
a2fa3e9f 898 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 899 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 900 vmcs_load(vmx->vmcs);
6aa8b732
AK		 901 }
902
903 if (vcpu->cpu != cpu) {
89a27f4d 904 struct desc_ptr dt;
6aa8b732
AK		 905 unsigned long sysenter_esp;
906
92fe13be 907 kvm_migrate_timers(vcpu);
a8eeb04a 908 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be
DX		 909 local_irq_disable();
910 list_add(&vmx->local_vcpus_link,
911 &per_cpu(vcpus_on_cpu, cpu));
912 local_irq_enable();
913
6aa8b732
AK		 914 vcpu->cpu = cpu;
915 /*
916 * Linux uses per-cpu TSS and GDT, so set these when switching
917 * processors.
918 */
d6e88aec 919 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d6ab1ed4 920 native_store_gdt(&dt);
89a27f4d 921 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732
AK		 922
923 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
924 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 925
926 /*
927 * Make sure the time stamp counter is monotonous.
928 */
929 rdtscll(tsc_this);
019960ae
AK		 930 if (tsc_this < vcpu->arch.host_tsc) {
931 delta = vcpu->arch.host_tsc - tsc_this;
932 new_offset = vmcs_read64(TSC_OFFSET) + delta;
933 vmcs_write64(TSC_OFFSET, new_offset);
934 }
6aa8b732 935 }
6aa8b732
AK		 936}
937
938static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
939{
a9b21b62 940 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 941 if (!vmm_exclusive) {
b923e62e 942 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 943 kvm_cpu_vmxoff();
944 }
6aa8b732
AK		 945}
946
5fd86fcf
AK		 947static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
948{
81231c69
AK		 949 ulong cr0;
950
5fd86fcf
AK		 951 if (vcpu->fpu_active)
952 return;
953 vcpu->fpu_active = 1;
81231c69
AK		 954 cr0 = vmcs_readl(GUEST_CR0);
955 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
956 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
957 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 958 update_exception_bitmap(vcpu);
edcafe3c
AK		 959 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
960 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 961}
962
edcafe3c
AK		 963static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
964
5fd86fcf
AK		 965static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
966{
edcafe3c 967 vmx_decache_cr0_guest_bits(vcpu);
81231c69 968 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 969 update_exception_bitmap(vcpu);
edcafe3c
AK		 970 vcpu->arch.cr0_guest_owned_bits = 0;
971 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
972 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 973}
974
6aa8b732
AK		 975static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
976{
78ac8b47 977 unsigned long rflags, save_rflags;
345dcaa8
AK		 978
979 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 980 if (to_vmx(vcpu)->rmode.vm86_active) {
981 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
982 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
983 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
984 }
345dcaa8 985 return rflags;
6aa8b732
AK		 986}
987
988static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
989{
78ac8b47
AK		 990 if (to_vmx(vcpu)->rmode.vm86_active) {
991 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 992 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 993 }
6aa8b732
AK		 994 vmcs_writel(GUEST_RFLAGS, rflags);
995}
996
2809f5d2
GC		 997static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
998{
999 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1000 int ret = 0;
1001
1002 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1003 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1004 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1005 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1006
1007 return ret & mask;
1008}
1009
1010static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1011{
1012 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1013 u32 interruptibility = interruptibility_old;
1014
1015 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1016
48005f64 1017 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1018 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1019 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1020 interruptibility |= GUEST_INTR_STATE_STI;
1021
1022 if ((interruptibility != interruptibility_old))
1023 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1024}
1025
6aa8b732
AK		 1026static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1027{
1028 unsigned long rip;
6aa8b732 1029
5fdbf976 1030 rip = kvm_rip_read(vcpu);
6aa8b732 1031 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1032 kvm_rip_write(vcpu, rip);
6aa8b732 1033
2809f5d2
GC		 1034 /* skipping an emulated instruction also counts */
1035 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1036}
1037
298101da 1038static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1039 bool has_error_code, u32 error_code,
1040 bool reinject)
298101da 1041{
77ab6db0 1042 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1043 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1044
8ab2d2e2 1045 if (has_error_code) {
77ab6db0 1046 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1047 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1048 }
77ab6db0 1049
7ffd92c5 1050 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 1051 vmx->rmode.irq.pending = true;
1052 vmx->rmode.irq.vector = nr;
1053 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 1054 if (kvm_exception_is_soft(nr))
1055 vmx->rmode.irq.rip +=
1056 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 1057 intr_info |= INTR_TYPE_SOFT_INTR;
1058 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 1059 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1060 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1061 return;
1062 }
1063
66fd3f7f
GN		 1064 if (kvm_exception_is_soft(nr)) {
1065 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1066 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1067 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1068 } else
1069 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1070
1071 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1072}
1073
4e47c7a6
SY		 1074static bool vmx_rdtscp_supported(void)
1075{
1076 return cpu_has_vmx_rdtscp();
1077}
1078
a75beee6
ED		 1079/*
1080 * Swap MSR entry in host/guest MSR entry array.
1081 */
8b9cf98c 1082static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1083{
26bb0981 1084 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1085
1086 tmp = vmx->guest_msrs[to];
1087 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1088 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1089}
1090
e38aea3e
AK		 1091/*
1092 * Set up the vmcs to automatically save and restore system
1093 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1094 * mode, as fiddling with msrs is very expensive.
1095 */
8b9cf98c 1096static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1097{
26bb0981 1098 int save_nmsrs, index;
5897297b 1099 unsigned long *msr_bitmap;
e38aea3e 1100
33f9c505 1101 vmx_load_host_state(vmx);
a75beee6
ED		 1102 save_nmsrs = 0;
1103#ifdef CONFIG_X86_64
8b9cf98c 1104 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1105 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1106 if (index >= 0)
8b9cf98c
RR		 1107 move_msr_up(vmx, index, save_nmsrs++);
1108 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1109 if (index >= 0)
8b9cf98c
RR		 1110 move_msr_up(vmx, index, save_nmsrs++);
1111 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1112 if (index >= 0)
8b9cf98c 1113 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1114 index = __find_msr_index(vmx, MSR_TSC_AUX);
1115 if (index >= 0 && vmx->rdtscp_enabled)
1116 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1117 /*
1118 * MSR_K6_STAR is only needed on long mode guests, and only
1119 * if efer.sce is enabled.
1120 */
8b9cf98c 1121 index = __find_msr_index(vmx, MSR_K6_STAR);
f6801dff 1122 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1123 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1124 }
1125#endif
92c0d900
AK		 1126 index = __find_msr_index(vmx, MSR_EFER);
1127 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1128 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1129
26bb0981 1130 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1131
1132 if (cpu_has_vmx_msr_bitmap()) {
1133 if (is_long_mode(&vmx->vcpu))
1134 msr_bitmap = vmx_msr_bitmap_longmode;
1135 else
1136 msr_bitmap = vmx_msr_bitmap_legacy;
1137
1138 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1139 }
e38aea3e
AK		 1140}
1141
6aa8b732
AK		 1142/*
1143 * reads and returns guest's timestamp counter "register"
1144 * guest_tsc = host_tsc + tsc_offset -- 21.3
1145 */
1146static u64 guest_read_tsc(void)
1147{
1148 u64 host_tsc, tsc_offset;
1149
1150 rdtscll(host_tsc);
1151 tsc_offset = vmcs_read64(TSC_OFFSET);
1152 return host_tsc + tsc_offset;
1153}
1154
1155/*
1156 * writes 'guest_tsc' into guest's timestamp counter "register"
1157 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1158 */
53f658b3 1159static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 1160{
6aa8b732
AK		 1161 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1162}
1163
6aa8b732
AK		 1164/*
1165 * Reads an msr value (of 'msr_index') into 'pdata'.
1166 * Returns 0 on success, non-0 otherwise.
1167 * Assumes vcpu_load() was already called.
1168 */
1169static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1170{
1171 u64 data;
26bb0981 1172 struct shared_msr_entry *msr;
6aa8b732
AK		 1173
1174 if (!pdata) {
1175 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1176 return -EINVAL;
1177 }
1178
1179 switch (msr_index) {
05b3e0c2 1180#ifdef CONFIG_X86_64
6aa8b732
AK		 1181 case MSR_FS_BASE:
1182 data = vmcs_readl(GUEST_FS_BASE);
1183 break;
1184 case MSR_GS_BASE:
1185 data = vmcs_readl(GUEST_GS_BASE);
1186 break;
44ea2b17
AK		 1187 case MSR_KERNEL_GS_BASE:
1188 vmx_load_host_state(to_vmx(vcpu));
1189 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1190 break;
26bb0981 1191#endif
6aa8b732 1192 case MSR_EFER:
3bab1f5d 1193 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1194 case MSR_IA32_TSC:
6aa8b732
AK		 1195 data = guest_read_tsc();
1196 break;
1197 case MSR_IA32_SYSENTER_CS:
1198 data = vmcs_read32(GUEST_SYSENTER_CS);
1199 break;
1200 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1201 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1202 break;
1203 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1204 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1205 break;
4e47c7a6
SY		 1206 case MSR_TSC_AUX:
1207 if (!to_vmx(vcpu)->rdtscp_enabled)
1208 return 1;
1209 /* Otherwise falls through */
6aa8b732 1210 default:
26bb0981 1211 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1212 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1213 if (msr) {
542423b0 1214 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1215 data = msr->data;
1216 break;
6aa8b732 1217 }
3bab1f5d 1218 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1219 }
1220
1221 *pdata = data;
1222 return 0;
1223}
1224
1225/*
1226 * Writes msr value into into the appropriate "register".
1227 * Returns 0 on success, non-0 otherwise.
1228 * Assumes vcpu_load() was already called.
1229 */
1230static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1231{
a2fa3e9f 1232 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1233 struct shared_msr_entry *msr;
53f658b3 1234 u64 host_tsc;
2cc51560
ED		 1235 int ret = 0;
1236
6aa8b732 1237 switch (msr_index) {
3bab1f5d 1238 case MSR_EFER:
a9b21b62 1239 vmx_load_host_state(vmx);
2cc51560 1240 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1241 break;
16175a79 1242#ifdef CONFIG_X86_64
6aa8b732
AK		 1243 case MSR_FS_BASE:
1244 vmcs_writel(GUEST_FS_BASE, data);
1245 break;
1246 case MSR_GS_BASE:
1247 vmcs_writel(GUEST_GS_BASE, data);
1248 break;
44ea2b17
AK		 1249 case MSR_KERNEL_GS_BASE:
1250 vmx_load_host_state(vmx);
1251 vmx->msr_guest_kernel_gs_base = data;
1252 break;
6aa8b732
AK		 1253#endif
1254 case MSR_IA32_SYSENTER_CS:
1255 vmcs_write32(GUEST_SYSENTER_CS, data);
1256 break;
1257 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1258 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1259 break;
1260 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1261 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1262 break;
af24a4e4 1263 case MSR_IA32_TSC:
53f658b3
MT		 1264 rdtscll(host_tsc);
1265 guest_write_tsc(data, host_tsc);
6aa8b732 1266 break;
468d472f
SY		 1267 case MSR_IA32_CR_PAT:
1268 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1269 vmcs_write64(GUEST_IA32_PAT, data);
1270 vcpu->arch.pat = data;
1271 break;
1272 }
4e47c7a6
SY		 1273 ret = kvm_set_msr_common(vcpu, msr_index, data);
1274 break;
1275 case MSR_TSC_AUX:
1276 if (!vmx->rdtscp_enabled)
1277 return 1;
1278 /* Check reserved bit, higher 32 bits should be zero */
1279 if ((data >> 32) != 0)
1280 return 1;
1281 /* Otherwise falls through */
6aa8b732 1282 default:
8b9cf98c 1283 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1284 if (msr) {
542423b0 1285 vmx_load_host_state(vmx);
3bab1f5d
AK		 1286 msr->data = data;
1287 break;
6aa8b732 1288 }
2cc51560 1289 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1290 }
1291
2cc51560 1292 return ret;
6aa8b732
AK		 1293}
1294
5fdbf976 1295static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1296{
5fdbf976
MT		 1297 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1298 switch (reg) {
1299 case VCPU_REGS_RSP:
1300 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1301 break;
1302 case VCPU_REGS_RIP:
1303 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1304 break;
6de4f3ad
AK		 1305 case VCPU_EXREG_PDPTR:
1306 if (enable_ept)
1307 ept_save_pdptrs(vcpu);
1308 break;
5fdbf976
MT		 1309 default:
1310 break;
1311 }
6aa8b732
AK		 1312}
1313
355be0b9 1314static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1315{
ae675ef0
JK		 1316 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1317 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1318 else
1319 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1320
abd3f2d6 1321 update_exception_bitmap(vcpu);
6aa8b732
AK		 1322}
1323
1324static __init int cpu_has_kvm_support(void)
1325{
6210e37b 1326 return cpu_has_vmx();
6aa8b732
AK		 1327}
1328
1329static __init int vmx_disabled_by_bios(void)
1330{
1331 u64 msr;
1332
1333 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1334 if (msr & FEATURE_CONTROL_LOCKED) {
1335 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1336 && tboot_enabled())
1337 return 1;
1338 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1339 && !tboot_enabled())
1340 return 1;
1341 }
1342
1343 return 0;
62b3ffb8 1344 /* locked but not enabled */
6aa8b732
AK		 1345}
1346
7725b894
DX		 1347static void kvm_cpu_vmxon(u64 addr)
1348{
1349 asm volatile (ASM_VMX_VMXON_RAX
1350 : : "a"(&addr), "m"(addr)
1351 : "memory", "cc");
1352}
1353
10474ae8 1354static int hardware_enable(void *garbage)
6aa8b732
AK		 1355{
1356 int cpu = raw_smp_processor_id();
1357 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1358 u64 old, test_bits;
6aa8b732 1359
10474ae8
AG		 1360 if (read_cr4() & X86_CR4_VMXE)
1361 return -EBUSY;
1362
543e4243 1363 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1364 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1365
1366 test_bits = FEATURE_CONTROL_LOCKED;
1367 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1368 if (tboot_enabled())
1369 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1370
1371 if ((old & test_bits) != test_bits) {
6aa8b732 1372 /* enable and lock */
cafd6659
SW		 1373 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1374 }
66aee91a 1375 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1376
4610c9cc
DX		 1377 if (vmm_exclusive) {
1378 kvm_cpu_vmxon(phys_addr);
1379 ept_sync_global();
1380 }
10474ae8
AG		 1381
1382 return 0;
6aa8b732
AK		 1383}
1384
543e4243
AK		 1385static void vmclear_local_vcpus(void)
1386{
1387 int cpu = raw_smp_processor_id();
1388 struct vcpu_vmx *vmx, *n;
1389
1390 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1391 local_vcpus_link)
1392 __vcpu_clear(vmx);
1393}
1394
710ff4a8
EH		 1395
1396/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1397 * tricks.
1398 */
1399static void kvm_cpu_vmxoff(void)
6aa8b732 1400{
4ecac3fd 1401 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1402}
1403
710ff4a8
EH		 1404static void hardware_disable(void *garbage)
1405{
4610c9cc
DX		 1406 if (vmm_exclusive) {
1407 vmclear_local_vcpus();
1408 kvm_cpu_vmxoff();
1409 }
7725b894 1410 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1411}
1412
1c3d14fe 1413static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1414 u32 msr, u32 *result)
1c3d14fe
YS		 1415{
1416 u32 vmx_msr_low, vmx_msr_high;
1417 u32 ctl = ctl_min | ctl_opt;
1418
1419 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1420
1421 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1422 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1423
1424 /* Ensure minimum (required) set of control bits are supported. */
1425 if (ctl_min & ~ctl)
002c7f7c 1426 return -EIO;
1c3d14fe
YS		 1427
1428 *result = ctl;
1429 return 0;
1430}
1431
002c7f7c 1432static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1433{
1434 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1435 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1436 u32 _pin_based_exec_control = 0;
1437 u32 _cpu_based_exec_control = 0;
f78e0e2e 1438 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1439 u32 _vmexit_control = 0;
1440 u32 _vmentry_control = 0;
1441
1442 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1443 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1444 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1445 &_pin_based_exec_control) < 0)
002c7f7c 1446 return -EIO;
1c3d14fe
YS		 1447
1448 min = CPU_BASED_HLT_EXITING |
1449#ifdef CONFIG_X86_64
1450 CPU_BASED_CR8_LOAD_EXITING |
1451 CPU_BASED_CR8_STORE_EXITING |
1452#endif
d56f546d
SY		 1453 CPU_BASED_CR3_LOAD_EXITING |
1454 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1455 CPU_BASED_USE_IO_BITMAPS |
1456 CPU_BASED_MOV_DR_EXITING |
a7052897 1457 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1458 CPU_BASED_MWAIT_EXITING |
1459 CPU_BASED_MONITOR_EXITING |
a7052897 1460 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1461 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1462 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1463 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1464 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1465 &_cpu_based_exec_control) < 0)
002c7f7c 1466 return -EIO;
6e5d865c
YS		 1467#ifdef CONFIG_X86_64
1468 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1469 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1470 ~CPU_BASED_CR8_STORE_EXITING;
1471#endif
f78e0e2e 1472 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1473 min2 = 0;
1474 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1475 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1476 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1477 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1478 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1479 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1480 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1481 if (adjust_vmx_controls(min2, opt2,
1482 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1483 &_cpu_based_2nd_exec_control) < 0)
1484 return -EIO;
1485 }
1486#ifndef CONFIG_X86_64
1487 if (!(_cpu_based_2nd_exec_control &
1488 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1489 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1490#endif
d56f546d 1491 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1492 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1493 enabled */
5fff7d27
GN		 1494 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1495 CPU_BASED_CR3_STORE_EXITING |
1496 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1497 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1498 vmx_capability.ept, vmx_capability.vpid);
1499 }
1c3d14fe
YS		 1500
1501 min = 0;
1502#ifdef CONFIG_X86_64
1503 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1504#endif
468d472f 1505 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1506 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1507 &_vmexit_control) < 0)
002c7f7c 1508 return -EIO;
1c3d14fe 1509
468d472f
SY		 1510 min = 0;
1511 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1512 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1513 &_vmentry_control) < 0)
002c7f7c 1514 return -EIO;
6aa8b732 1515
c68876fd 1516 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1517
1518 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1519 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1520 return -EIO;
1c3d14fe
YS		 1521
1522#ifdef CONFIG_X86_64
1523 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1524 if (vmx_msr_high & (1u<<16))
002c7f7c 1525 return -EIO;
1c3d14fe
YS		 1526#endif
1527
1528 /* Require Write-Back (WB) memory type for VMCS accesses. */
1529 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1530 return -EIO;
1c3d14fe 1531
002c7f7c
YS		 1532 vmcs_conf->size = vmx_msr_high & 0x1fff;
1533 vmcs_conf->order = get_order(vmcs_config.size);
1534 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1535
002c7f7c
YS		 1536 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1537 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1538 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1539 vmcs_conf->vmexit_ctrl = _vmexit_control;
1540 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1541
1542 return 0;
c68876fd 1543}
6aa8b732
AK		 1544
1545static struct vmcs *alloc_vmcs_cpu(int cpu)
1546{
1547 int node = cpu_to_node(cpu);
1548 struct page *pages;
1549 struct vmcs *vmcs;
1550
6484eb3e 1551 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1552 if (!pages)
1553 return NULL;
1554 vmcs = page_address(pages);
1c3d14fe
YS		 1555 memset(vmcs, 0, vmcs_config.size);
1556 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1557 return vmcs;
1558}
1559
1560static struct vmcs *alloc_vmcs(void)
1561{
d3b2c338 1562 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1563}
1564
1565static void free_vmcs(struct vmcs *vmcs)
1566{
1c3d14fe 1567 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1568}
1569
39959588 1570static void free_kvm_area(void)
6aa8b732
AK		 1571{
1572 int cpu;
1573
3230bb47 1574 for_each_possible_cpu(cpu) {
6aa8b732 1575 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1576 per_cpu(vmxarea, cpu) = NULL;
1577 }
6aa8b732
AK		 1578}
1579
6aa8b732
AK		 1580static __init int alloc_kvm_area(void)
1581{
1582 int cpu;
1583
3230bb47 1584 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1585 struct vmcs *vmcs;
1586
1587 vmcs = alloc_vmcs_cpu(cpu);
1588 if (!vmcs) {
1589 free_kvm_area();
1590 return -ENOMEM;
1591 }
1592
1593 per_cpu(vmxarea, cpu) = vmcs;
1594 }
1595 return 0;
1596}
1597
1598static __init int hardware_setup(void)
1599{
002c7f7c
YS		 1600 if (setup_vmcs_config(&vmcs_config) < 0)
1601 return -EIO;
50a37eb4
JR		 1602
1603 if (boot_cpu_has(X86_FEATURE_NX))
1604 kvm_enable_efer_bits(EFER_NX);
1605
93ba03c2
SY		 1606 if (!cpu_has_vmx_vpid())
1607 enable_vpid = 0;
1608
4bc9b982
SY		 1609 if (!cpu_has_vmx_ept() ||
1610 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1611 enable_ept = 0;
3a624e29
NK		 1612 enable_unrestricted_guest = 0;
1613 }
1614
1615 if (!cpu_has_vmx_unrestricted_guest())
1616 enable_unrestricted_guest = 0;
93ba03c2
SY		 1617
1618 if (!cpu_has_vmx_flexpriority())
1619 flexpriority_enabled = 0;
1620
95ba8273
GN		 1621 if (!cpu_has_vmx_tpr_shadow())
1622 kvm_x86_ops->update_cr8_intercept = NULL;
1623
54dee993
MT		 1624 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1625 kvm_disable_largepages();
1626
4b8d54f9
ZE		 1627 if (!cpu_has_vmx_ple())
1628 ple_gap = 0;
1629
6aa8b732
AK		 1630 return alloc_kvm_area();
1631}
1632
1633static __exit void hardware_unsetup(void)
1634{
1635 free_kvm_area();
1636}
1637
6aa8b732
AK		 1638static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1639{
1640 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1641
6af11b9e 1642 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1643 vmcs_write16(sf->selector, save->selector);
1644 vmcs_writel(sf->base, save->base);
1645 vmcs_write32(sf->limit, save->limit);
1646 vmcs_write32(sf->ar_bytes, save->ar);
1647 } else {
1648 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1649 << AR_DPL_SHIFT;
1650 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1651 }
1652}
1653
1654static void enter_pmode(struct kvm_vcpu *vcpu)
1655{
1656 unsigned long flags;
a89a8fb9 1657 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1658
a89a8fb9 1659 vmx->emulation_required = 1;
7ffd92c5 1660 vmx->rmode.vm86_active = 0;
6aa8b732 1661
7ffd92c5
AK		 1662 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1663 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1664 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1665
1666 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1667 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1668 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1669 vmcs_writel(GUEST_RFLAGS, flags);
1670
66aee91a
RR		 1671 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1672 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1673
1674 update_exception_bitmap(vcpu);
1675
a89a8fb9
MG		 1676 if (emulate_invalid_guest_state)
1677 return;
1678
7ffd92c5
AK		 1679 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1680 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1681 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1682 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1683
1684 vmcs_write16(GUEST_SS_SELECTOR, 0);
1685 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1686
1687 vmcs_write16(GUEST_CS_SELECTOR,
1688 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1689 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1690}
1691
d77c26fc 1692static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1693{
bfc6d222 1694 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1695 struct kvm_memslots *slots;
1696 gfn_t base_gfn;
1697
90d83dc3 1698 slots = kvm_memslots(kvm);
f495c6e5 1699 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1700 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1701 return base_gfn << PAGE_SHIFT;
1702 }
bfc6d222 1703 return kvm->arch.tss_addr;
6aa8b732
AK		 1704}
1705
1706static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1707{
1708 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1709
1710 save->selector = vmcs_read16(sf->selector);
1711 save->base = vmcs_readl(sf->base);
1712 save->limit = vmcs_read32(sf->limit);
1713 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1714 vmcs_write16(sf->selector, save->base >> 4);
1715 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1716 vmcs_write32(sf->limit, 0xffff);
1717 vmcs_write32(sf->ar_bytes, 0xf3);
1718}
1719
1720static void enter_rmode(struct kvm_vcpu *vcpu)
1721{
1722 unsigned long flags;
a89a8fb9 1723 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1724
3a624e29
NK		 1725 if (enable_unrestricted_guest)
1726 return;
1727
a89a8fb9 1728 vmx->emulation_required = 1;
7ffd92c5 1729 vmx->rmode.vm86_active = 1;
6aa8b732 1730
7ffd92c5 1731 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1732 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1733
7ffd92c5 1734 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1735 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1736
7ffd92c5 1737 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1738 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1739
1740 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1741 vmx->rmode.save_rflags = flags;
6aa8b732 1742
053de044 1743 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1744
1745 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1746 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1747 update_exception_bitmap(vcpu);
1748
a89a8fb9
MG		 1749 if (emulate_invalid_guest_state)
1750 goto continue_rmode;
1751
6aa8b732
AK		 1752 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1753 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1754 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1755
1756 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1757 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1758 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1759 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1760 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1761
7ffd92c5
AK		 1762 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1763 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1764 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1765 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1766
a89a8fb9 1767continue_rmode:
8668a3c4 1768 kvm_mmu_reset_context(vcpu);
b7ebfb05 1769 init_rmode(vcpu->kvm);
6aa8b732
AK		 1770}
1771
401d10de
AS		 1772static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1773{
1774 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1775 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1776
1777 if (!msr)
1778 return;
401d10de 1779
44ea2b17
AK		 1780 /*
1781 * Force kernel_gs_base reloading before EFER changes, as control
1782 * of this msr depends on is_long_mode().
1783 */
1784 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1785 vcpu->arch.efer = efer;
401d10de
AS		 1786 if (efer & EFER_LMA) {
1787 vmcs_write32(VM_ENTRY_CONTROLS,
1788 vmcs_read32(VM_ENTRY_CONTROLS) |
1789 VM_ENTRY_IA32E_MODE);
1790 msr->data = efer;
1791 } else {
1792 vmcs_write32(VM_ENTRY_CONTROLS,
1793 vmcs_read32(VM_ENTRY_CONTROLS) &
1794 ~VM_ENTRY_IA32E_MODE);
1795
1796 msr->data = efer & ~EFER_LME;
1797 }
1798 setup_msrs(vmx);
1799}
1800
05b3e0c2 1801#ifdef CONFIG_X86_64
6aa8b732
AK		 1802
1803static void enter_lmode(struct kvm_vcpu *vcpu)
1804{
1805 u32 guest_tr_ar;
1806
1807 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1808 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1809 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1810 __func__);
6aa8b732
AK		 1811 vmcs_write32(GUEST_TR_AR_BYTES,
1812 (guest_tr_ar & ~AR_TYPE_MASK)
1813 | AR_TYPE_BUSY_64_TSS);
1814 }
da38f438 1815 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1816}
1817
1818static void exit_lmode(struct kvm_vcpu *vcpu)
1819{
6aa8b732
AK		 1820 vmcs_write32(VM_ENTRY_CONTROLS,
1821 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1822 & ~VM_ENTRY_IA32E_MODE);
da38f438 1823 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1824}
1825
1826#endif
1827
2384d2b3
SY		 1828static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1829{
b9d762fa 1830 vpid_sync_context(to_vmx(vcpu));
089d034e 1831 if (enable_ept)
4e1096d2 1832 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1833}
1834
e8467fda
AK		 1835static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1836{
1837 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1838
1839 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1840 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1841}
1842
25c4c276 1843static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1844{
fc78f519
AK		 1845 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1846
1847 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1848 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1849}
1850
1439442c
SY		 1851static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1852{
6de4f3ad
AK		 1853 if (!test_bit(VCPU_EXREG_PDPTR,
1854 (unsigned long *)&vcpu->arch.regs_dirty))
1855 return;
1856
1439442c 1857 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1858 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1859 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1860 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1861 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1862 }
1863}
1864
8f5d549f
AK		 1865static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1866{
1867 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1868 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1869 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1870 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1871 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1872 }
6de4f3ad
AK		 1873
1874 __set_bit(VCPU_EXREG_PDPTR,
1875 (unsigned long *)&vcpu->arch.regs_avail);
1876 __set_bit(VCPU_EXREG_PDPTR,
1877 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1878}
1879
1439442c
SY		 1880static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1881
1882static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1883 unsigned long cr0,
1884 struct kvm_vcpu *vcpu)
1885{
1886 if (!(cr0 & X86_CR0_PG)) {
1887 /* From paging/starting to nonpaging */
1888 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1889 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1890 (CPU_BASED_CR3_LOAD_EXITING |
1891 CPU_BASED_CR3_STORE_EXITING));
1892 vcpu->arch.cr0 = cr0;
fc78f519 1893 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1894 } else if (!is_paging(vcpu)) {
1895 /* From nonpaging to paging */
1896 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1897 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1898 ~(CPU_BASED_CR3_LOAD_EXITING |
1899 CPU_BASED_CR3_STORE_EXITING));
1900 vcpu->arch.cr0 = cr0;
fc78f519 1901 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1902 }
95eb84a7
SY		 1903
1904 if (!(cr0 & X86_CR0_WP))
1905 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1906}
1907
6aa8b732
AK		 1908static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1909{
7ffd92c5 1910 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1911 unsigned long hw_cr0;
1912
1913 if (enable_unrestricted_guest)
1914 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1915 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1916 else
1917 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1918
7ffd92c5 1919 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1920 enter_pmode(vcpu);
1921
7ffd92c5 1922 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1923 enter_rmode(vcpu);
1924
05b3e0c2 1925#ifdef CONFIG_X86_64
f6801dff 1926 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1927 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1928 enter_lmode(vcpu);
707d92fa 1929 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1930 exit_lmode(vcpu);
1931 }
1932#endif
1933
089d034e 1934 if (enable_ept)
1439442c
SY		 1935 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1936
02daab21 1937 if (!vcpu->fpu_active)
81231c69 1938 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1939
6aa8b732 1940 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1941 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1942 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1943}
1944
1439442c
SY		 1945static u64 construct_eptp(unsigned long root_hpa)
1946{
1947 u64 eptp;
1948
1949 /* TODO write the value reading from MSR */
1950 eptp = VMX_EPT_DEFAULT_MT |
1951 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1952 eptp |= (root_hpa & PAGE_MASK);
1953
1954 return eptp;
1955}
1956
6aa8b732
AK		 1957static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1958{
1439442c
SY		 1959 unsigned long guest_cr3;
1960 u64 eptp;
1961
1962 guest_cr3 = cr3;
089d034e 1963 if (enable_ept) {
1439442c
SY		 1964 eptp = construct_eptp(cr3);
1965 vmcs_write64(EPT_POINTER, eptp);
1439442c 1966 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1967 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1968 ept_load_pdptrs(vcpu);
1439442c
SY		 1969 }
1970
2384d2b3 1971 vmx_flush_tlb(vcpu);
1439442c 1972 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1973}
1974
1975static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1976{
7ffd92c5 1977 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1978 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1979
ad312c7c 1980 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1981 if (enable_ept) {
1982 if (!is_paging(vcpu)) {
1983 hw_cr4 &= ~X86_CR4_PAE;
1984 hw_cr4 |= X86_CR4_PSE;
1985 } else if (!(cr4 & X86_CR4_PAE)) {
1986 hw_cr4 &= ~X86_CR4_PAE;
1987 }
1988 }
1439442c
SY		 1989
1990 vmcs_writel(CR4_READ_SHADOW, cr4);
1991 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1992}
1993
6aa8b732
AK		 1994static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1995{
1996 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1997
1998 return vmcs_readl(sf->base);
1999}
2000
2001static void vmx_get_segment(struct kvm_vcpu *vcpu,
2002 struct kvm_segment *var, int seg)
2003{
2004 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2005 u32 ar;
2006
2007 var->base = vmcs_readl(sf->base);
2008 var->limit = vmcs_read32(sf->limit);
2009 var->selector = vmcs_read16(sf->selector);
2010 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 2011 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2012 ar = 0;
2013 var->type = ar & 15;
2014 var->s = (ar >> 4) & 1;
2015 var->dpl = (ar >> 5) & 3;
2016 var->present = (ar >> 7) & 1;
2017 var->avl = (ar >> 12) & 1;
2018 var->l = (ar >> 13) & 1;
2019 var->db = (ar >> 14) & 1;
2020 var->g = (ar >> 15) & 1;
2021 var->unusable = (ar >> 16) & 1;
2022}
2023
2e4d2653
IE		 2024static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2025{
3eeb3288 2026 if (!is_protmode(vcpu))
2e4d2653
IE		 2027 return 0;
2028
2029 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2030 return 3;
2031
eab4b8aa 2032 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2033}
2034
653e3108 2035static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2036{
6aa8b732
AK		 2037 u32 ar;
2038
653e3108 2039 if (var->unusable)
6aa8b732
AK		 2040 ar = 1 << 16;
2041 else {
2042 ar = var->type & 15;
2043 ar |= (var->s & 1) << 4;
2044 ar |= (var->dpl & 3) << 5;
2045 ar |= (var->present & 1) << 7;
2046 ar |= (var->avl & 1) << 12;
2047 ar |= (var->l & 1) << 13;
2048 ar |= (var->db & 1) << 14;
2049 ar |= (var->g & 1) << 15;
2050 }
f7fbf1fd
UL		 2051 if (ar == 0) /* a 0 value means unusable */
2052 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2053
2054 return ar;
2055}
2056
2057static void vmx_set_segment(struct kvm_vcpu *vcpu,
2058 struct kvm_segment *var, int seg)
2059{
7ffd92c5 2060 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2061 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2062 u32 ar;
2063
7ffd92c5
AK		 2064 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2065 vmx->rmode.tr.selector = var->selector;
2066 vmx->rmode.tr.base = var->base;
2067 vmx->rmode.tr.limit = var->limit;
2068 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2069 return;
2070 }
2071 vmcs_writel(sf->base, var->base);
2072 vmcs_write32(sf->limit, var->limit);
2073 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2074 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2075 /*
2076 * Hack real-mode segments into vm86 compatibility.
2077 */
2078 if (var->base == 0xffff0000 && var->selector == 0xf000)
2079 vmcs_writel(sf->base, 0xf0000);
2080 ar = 0xf3;
2081 } else
2082 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2083
2084 /*
2085 * Fix the "Accessed" bit in AR field of segment registers for older
2086 * qemu binaries.
2087 * IA32 arch specifies that at the time of processor reset the
2088 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2089 * is setting it to 0 in the usedland code. This causes invalid guest
2090 * state vmexit when "unrestricted guest" mode is turned on.
2091 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2092 * tree. Newer qemu binaries with that qemu fix would not need this
2093 * kvm hack.
2094 */
2095 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2096 ar |= 0x1; /* Accessed */
2097
6aa8b732
AK		 2098 vmcs_write32(sf->ar_bytes, ar);
2099}
2100
6aa8b732
AK		 2101static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2102{
2103 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2104
2105 *db = (ar >> 14) & 1;
2106 *l = (ar >> 13) & 1;
2107}
2108
89a27f4d 2109static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2110{
89a27f4d
GN		 2111 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2112 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2113}
2114
89a27f4d 2115static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2116{
89a27f4d
GN		 2117 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2118 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2119}
2120
89a27f4d 2121static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2122{
89a27f4d
GN		 2123 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2124 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2125}
2126
89a27f4d 2127static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2128{
89a27f4d
GN		 2129 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2130 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2131}
2132
648dfaa7
MG		 2133static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2134{
2135 struct kvm_segment var;
2136 u32 ar;
2137
2138 vmx_get_segment(vcpu, &var, seg);
2139 ar = vmx_segment_access_rights(&var);
2140
2141 if (var.base != (var.selector << 4))
2142 return false;
2143 if (var.limit != 0xffff)
2144 return false;
2145 if (ar != 0xf3)
2146 return false;
2147
2148 return true;
2149}
2150
2151static bool code_segment_valid(struct kvm_vcpu *vcpu)
2152{
2153 struct kvm_segment cs;
2154 unsigned int cs_rpl;
2155
2156 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2157 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2158
1872a3f4
AK		 2159 if (cs.unusable)
2160 return false;
648dfaa7
MG		 2161 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2162 return false;
2163 if (!cs.s)
2164 return false;
1872a3f4 2165 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2166 if (cs.dpl > cs_rpl)
2167 return false;
1872a3f4 2168 } else {
648dfaa7
MG		 2169 if (cs.dpl != cs_rpl)
2170 return false;
2171 }
2172 if (!cs.present)
2173 return false;
2174
2175 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2176 return true;
2177}
2178
2179static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2180{
2181 struct kvm_segment ss;
2182 unsigned int ss_rpl;
2183
2184 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2185 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2186
1872a3f4
AK		 2187 if (ss.unusable)
2188 return true;
2189 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2190 return false;
2191 if (!ss.s)
2192 return false;
2193 if (ss.dpl != ss_rpl) /* DPL != RPL */
2194 return false;
2195 if (!ss.present)
2196 return false;
2197
2198 return true;
2199}
2200
2201static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2202{
2203 struct kvm_segment var;
2204 unsigned int rpl;
2205
2206 vmx_get_segment(vcpu, &var, seg);
2207 rpl = var.selector & SELECTOR_RPL_MASK;
2208
1872a3f4
AK		 2209 if (var.unusable)
2210 return true;
648dfaa7
MG		 2211 if (!var.s)
2212 return false;
2213 if (!var.present)
2214 return false;
2215 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2216 if (var.dpl < rpl) /* DPL < RPL */
2217 return false;
2218 }
2219
2220 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2221 * rights flags
2222 */
2223 return true;
2224}
2225
2226static bool tr_valid(struct kvm_vcpu *vcpu)
2227{
2228 struct kvm_segment tr;
2229
2230 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2231
1872a3f4
AK		 2232 if (tr.unusable)
2233 return false;
648dfaa7
MG		 2234 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2235 return false;
1872a3f4 2236 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2237 return false;
2238 if (!tr.present)
2239 return false;
2240
2241 return true;
2242}
2243
2244static bool ldtr_valid(struct kvm_vcpu *vcpu)
2245{
2246 struct kvm_segment ldtr;
2247
2248 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2249
1872a3f4
AK		 2250 if (ldtr.unusable)
2251 return true;
648dfaa7
MG		 2252 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2253 return false;
2254 if (ldtr.type != 2)
2255 return false;
2256 if (!ldtr.present)
2257 return false;
2258
2259 return true;
2260}
2261
2262static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2263{
2264 struct kvm_segment cs, ss;
2265
2266 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2267 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2268
2269 return ((cs.selector & SELECTOR_RPL_MASK) ==
2270 (ss.selector & SELECTOR_RPL_MASK));
2271}
2272
2273/*
2274 * Check if guest state is valid. Returns true if valid, false if
2275 * not.
2276 * We assume that registers are always usable
2277 */
2278static bool guest_state_valid(struct kvm_vcpu *vcpu)
2279{
2280 /* real mode guest state checks */
3eeb3288 2281 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2282 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2283 return false;
2284 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2285 return false;
2286 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2287 return false;
2288 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2289 return false;
2290 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2291 return false;
2292 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2293 return false;
2294 } else {
2295 /* protected mode guest state checks */
2296 if (!cs_ss_rpl_check(vcpu))
2297 return false;
2298 if (!code_segment_valid(vcpu))
2299 return false;
2300 if (!stack_segment_valid(vcpu))
2301 return false;
2302 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2303 return false;
2304 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2305 return false;
2306 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2307 return false;
2308 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2309 return false;
2310 if (!tr_valid(vcpu))
2311 return false;
2312 if (!ldtr_valid(vcpu))
2313 return false;
2314 }
2315 /* TODO:
2316 * - Add checks on RIP
2317 * - Add checks on RFLAGS
2318 */
2319
2320 return true;
2321}
2322
d77c26fc 2323static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2324{
6aa8b732 2325 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2326 u16 data = 0;
10589a46 2327 int ret = 0;
195aefde 2328 int r;
6aa8b732 2329
195aefde
IE		 2330 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2331 if (r < 0)
10589a46 2332 goto out;
195aefde 2333 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2334 r = kvm_write_guest_page(kvm, fn++, &data,
2335 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2336 if (r < 0)
10589a46 2337 goto out;
195aefde
IE		 2338 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2339 if (r < 0)
10589a46 2340 goto out;
195aefde
IE		 2341 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2342 if (r < 0)
10589a46 2343 goto out;
195aefde 2344 data = ~0;
10589a46
MT		 2345 r = kvm_write_guest_page(kvm, fn, &data,
2346 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2347 sizeof(u8));
195aefde 2348 if (r < 0)
10589a46
MT		 2349 goto out;
2350
2351 ret = 1;
2352out:
10589a46 2353 return ret;
6aa8b732
AK		 2354}
2355
b7ebfb05
SY		 2356static int init_rmode_identity_map(struct kvm *kvm)
2357{
2358 int i, r, ret;
2359 pfn_t identity_map_pfn;
2360 u32 tmp;
2361
089d034e 2362 if (!enable_ept)
b7ebfb05
SY		 2363 return 1;
2364 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2365 printk(KERN_ERR "EPT: identity-mapping pagetable "
2366 "haven't been allocated!\n");
2367 return 0;
2368 }
2369 if (likely(kvm->arch.ept_identity_pagetable_done))
2370 return 1;
2371 ret = 0;
b927a3ce 2372 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2373 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2374 if (r < 0)
2375 goto out;
2376 /* Set up identity-mapping pagetable for EPT in real mode */
2377 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2378 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2379 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2380 r = kvm_write_guest_page(kvm, identity_map_pfn,
2381 &tmp, i * sizeof(tmp), sizeof(tmp));
2382 if (r < 0)
2383 goto out;
2384 }
2385 kvm->arch.ept_identity_pagetable_done = true;
2386 ret = 1;
2387out:
2388 return ret;
2389}
2390
6aa8b732
AK		 2391static void seg_setup(int seg)
2392{
2393 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2394 unsigned int ar;
6aa8b732
AK		 2395
2396 vmcs_write16(sf->selector, 0);
2397 vmcs_writel(sf->base, 0);
2398 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2399 if (enable_unrestricted_guest) {
2400 ar = 0x93;
2401 if (seg == VCPU_SREG_CS)
2402 ar |= 0x08; /* code segment */
2403 } else
2404 ar = 0xf3;
2405
2406 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2407}
2408
f78e0e2e
SY		 2409static int alloc_apic_access_page(struct kvm *kvm)
2410{
2411 struct kvm_userspace_memory_region kvm_userspace_mem;
2412 int r = 0;
2413
79fac95e 2414 mutex_lock(&kvm->slots_lock);
bfc6d222 2415 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2416 goto out;
2417 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2418 kvm_userspace_mem.flags = 0;
2419 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2420 kvm_userspace_mem.memory_size = PAGE_SIZE;
2421 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2422 if (r)
2423 goto out;
72dc67a6 2424
bfc6d222 2425 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2426out:
79fac95e 2427 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2428 return r;
2429}
2430
b7ebfb05
SY		 2431static int alloc_identity_pagetable(struct kvm *kvm)
2432{
2433 struct kvm_userspace_memory_region kvm_userspace_mem;
2434 int r = 0;
2435
79fac95e 2436 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2437 if (kvm->arch.ept_identity_pagetable)
2438 goto out;
2439 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2440 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2441 kvm_userspace_mem.guest_phys_addr =
2442 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2443 kvm_userspace_mem.memory_size = PAGE_SIZE;
2444 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2445 if (r)
2446 goto out;
2447
b7ebfb05 2448 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2449 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2450out:
79fac95e 2451 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2452 return r;
2453}
2454
2384d2b3
SY		 2455static void allocate_vpid(struct vcpu_vmx *vmx)
2456{
2457 int vpid;
2458
2459 vmx->vpid = 0;
919818ab 2460 if (!enable_vpid)
2384d2b3
SY		 2461 return;
2462 spin_lock(&vmx_vpid_lock);
2463 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2464 if (vpid < VMX_NR_VPIDS) {
2465 vmx->vpid = vpid;
2466 __set_bit(vpid, vmx_vpid_bitmap);
2467 }
2468 spin_unlock(&vmx_vpid_lock);
2469}
2470
cdbecfc3
LJ		 2471static void free_vpid(struct vcpu_vmx *vmx)
2472{
2473 if (!enable_vpid)
2474 return;
2475 spin_lock(&vmx_vpid_lock);
2476 if (vmx->vpid != 0)
2477 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2478 spin_unlock(&vmx_vpid_lock);
2479}
2480
5897297b 2481static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2482{
3e7c73e9 2483 int f = sizeof(unsigned long);
25c5f225
SY		 2484
2485 if (!cpu_has_vmx_msr_bitmap())
2486 return;
2487
2488 /*
2489 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2490 * have the write-low and read-high bitmap offsets the wrong way round.
2491 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2492 */
25c5f225 2493 if (msr <= 0x1fff) {
3e7c73e9
AK		 2494 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2495 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2496 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2497 msr &= 0x1fff;
3e7c73e9
AK		 2498 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2499 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2500 }
25c5f225
SY		 2501}
2502
5897297b
AK		 2503static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2504{
2505 if (!longmode_only)
2506 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2507 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2508}
2509
6aa8b732
AK		 2510/*
2511 * Sets up the vmcs for emulated real mode.
2512 */
8b9cf98c 2513static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2514{
468d472f 2515 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2516 u32 junk;
53f658b3 2517 u64 host_pat, tsc_this, tsc_base;
6aa8b732 2518 unsigned long a;
89a27f4d 2519 struct desc_ptr dt;
6aa8b732 2520 int i;
cd2276a7 2521 unsigned long kvm_vmx_return;
6e5d865c 2522 u32 exec_control;
6aa8b732 2523
6aa8b732 2524 /* I/O */
3e7c73e9
AK		 2525 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2526 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2527
25c5f225 2528 if (cpu_has_vmx_msr_bitmap())
5897297b 2529 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2530
6aa8b732
AK		 2531 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2532
6aa8b732 2533 /* Control */
1c3d14fe
YS		 2534 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2535 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2536
2537 exec_control = vmcs_config.cpu_based_exec_ctrl;
2538 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2539 exec_control &= ~CPU_BASED_TPR_SHADOW;
2540#ifdef CONFIG_X86_64
2541 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2542 CPU_BASED_CR8_LOAD_EXITING;
2543#endif
2544 }
089d034e 2545 if (!enable_ept)
d56f546d 2546 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2547 CPU_BASED_CR3_LOAD_EXITING |
2548 CPU_BASED_INVLPG_EXITING;
6e5d865c 2549 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2550
83ff3b9d
SY		 2551 if (cpu_has_secondary_exec_ctrls()) {
2552 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2553 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2554 exec_control &=
2555 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2556 if (vmx->vpid == 0)
2557 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2558 if (!enable_ept) {
d56f546d 2559 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2560 enable_unrestricted_guest = 0;
2561 }
3a624e29
NK		 2562 if (!enable_unrestricted_guest)
2563 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2564 if (!ple_gap)
2565 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2566 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2567 }
f78e0e2e 2568
4b8d54f9
ZE		 2569 if (ple_gap) {
2570 vmcs_write32(PLE_GAP, ple_gap);
2571 vmcs_write32(PLE_WINDOW, ple_window);
2572 }
2573
c7addb90
AK		 2574 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2575 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2576 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2577
1c11e713 2578 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2579 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2580 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2581
2582 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2583 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2584 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2585 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2586 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2587 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2588#ifdef CONFIG_X86_64
6aa8b732
AK		 2589 rdmsrl(MSR_FS_BASE, a);
2590 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2591 rdmsrl(MSR_GS_BASE, a);
2592 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2593#else
2594 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2595 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2596#endif
2597
2598 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2599
ec68798c 2600 native_store_idt(&dt);
89a27f4d 2601 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2602
d77c26fc 2603 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2604 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2605 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2606 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2607 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2608 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2609 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2610
2611 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2612 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2613 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2614 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2615 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2616 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2617
468d472f
SY		 2618 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2619 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2620 host_pat = msr_low | ((u64) msr_high << 32);
2621 vmcs_write64(HOST_IA32_PAT, host_pat);
2622 }
2623 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2624 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2625 host_pat = msr_low | ((u64) msr_high << 32);
2626 /* Write the default value follow host pat */
2627 vmcs_write64(GUEST_IA32_PAT, host_pat);
2628 /* Keep arch.pat sync with GUEST_IA32_PAT */
2629 vmx->vcpu.arch.pat = host_pat;
2630 }
2631
6aa8b732
AK		 2632 for (i = 0; i < NR_VMX_MSR; ++i) {
2633 u32 index = vmx_msr_index[i];
2634 u32 data_low, data_high;
a2fa3e9f 2635 int j = vmx->nmsrs;
6aa8b732
AK		 2636
2637 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2638 continue;
432bd6cb
AK		 2639 if (wrmsr_safe(index, data_low, data_high) < 0)
2640 continue;
26bb0981
AK		 2641 vmx->guest_msrs[j].index = i;
2642 vmx->guest_msrs[j].data = 0;
d5696725 2643 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2644 ++vmx->nmsrs;
6aa8b732 2645 }
6aa8b732 2646
1c3d14fe 2647 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2648
2649 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2650 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2651
e00c8cf2 2652 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2653 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2654 if (enable_ept)
2655 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2656 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2657
53f658b3
MT		 2658 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2659 rdtscll(tsc_this);
2660 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2661 tsc_base = tsc_this;
2662
2663 guest_write_tsc(0, tsc_base);
f78e0e2e 2664
e00c8cf2
AK		 2665 return 0;
2666}
2667
b7ebfb05
SY		 2668static int init_rmode(struct kvm *kvm)
2669{
4b9d3a04
XG		 2670 int idx, ret = 0;
2671
2672 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05 2673 if (!init_rmode_tss(kvm))
4b9d3a04 2674 goto exit;
b7ebfb05 2675 if (!init_rmode_identity_map(kvm))
4b9d3a04
XG		 2676 goto exit;
2677
2678 ret = 1;
2679exit:
2680 srcu_read_unlock(&kvm->srcu, idx);
2681 return ret;
b7ebfb05
SY		 2682}
2683
e00c8cf2
AK		 2684static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2685{
2686 struct vcpu_vmx *vmx = to_vmx(vcpu);
2687 u64 msr;
4b9d3a04 2688 int ret;
e00c8cf2 2689
5fdbf976 2690 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
b7ebfb05 2691 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2692 ret = -ENOMEM;
2693 goto out;
2694 }
2695
7ffd92c5 2696 vmx->rmode.vm86_active = 0;
e00c8cf2 2697
3b86cd99
JK		 2698 vmx->soft_vnmi_blocked = 0;
2699
ad312c7c 2700 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2701 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2702 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2703 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2704 msr |= MSR_IA32_APICBASE_BSP;
2705 kvm_set_apic_base(&vmx->vcpu, msr);
2706
10ab25cd
JK		 2707 ret = fx_init(&vmx->vcpu);
2708 if (ret != 0)
2709 goto out;
e00c8cf2 2710
5706be0d 2711 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2712 /*
2713 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2714 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2715 */
c5af89b6 2716 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2717 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2718 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2719 } else {
ad312c7c
ZX		 2720 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2721 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2722 }
e00c8cf2
AK		 2723
2724 seg_setup(VCPU_SREG_DS);
2725 seg_setup(VCPU_SREG_ES);
2726 seg_setup(VCPU_SREG_FS);
2727 seg_setup(VCPU_SREG_GS);
2728 seg_setup(VCPU_SREG_SS);
2729
2730 vmcs_write16(GUEST_TR_SELECTOR, 0);
2731 vmcs_writel(GUEST_TR_BASE, 0);
2732 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2733 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2734
2735 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2736 vmcs_writel(GUEST_LDTR_BASE, 0);
2737 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2738 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2739
2740 vmcs_write32(GUEST_SYSENTER_CS, 0);
2741 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2742 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2743
2744 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2745 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2746 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2747 else
5fdbf976
MT		 2748 kvm_rip_write(vcpu, 0);
2749 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2750
e00c8cf2
AK		 2751 vmcs_writel(GUEST_DR7, 0x400);
2752
2753 vmcs_writel(GUEST_GDTR_BASE, 0);
2754 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2755
2756 vmcs_writel(GUEST_IDTR_BASE, 0);
2757 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2758
2759 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2760 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2761 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2762
e00c8cf2
AK		 2763 /* Special registers */
2764 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2765
2766 setup_msrs(vmx);
2767
6aa8b732
AK		 2768 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2769
f78e0e2e
SY		 2770 if (cpu_has_vmx_tpr_shadow()) {
2771 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2772 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2773 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2774 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2775 vmcs_write32(TPR_THRESHOLD, 0);
2776 }
2777
2778 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2779 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2780 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2781
2384d2b3
SY		 2782 if (vmx->vpid != 0)
2783 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2784
fa40052c 2785 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2786 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2787 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2788 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2789 vmx_fpu_activate(&vmx->vcpu);
2790 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2791
b9d762fa 2792 vpid_sync_context(vmx);
2384d2b3 2793
3200f405 2794 ret = 0;
6aa8b732 2795
a89a8fb9
MG		 2796 /* HACK: Don't enable emulation on guest boot/reset */
2797 vmx->emulation_required = 0;
2798
6aa8b732
AK		 2799out:
2800 return ret;
2801}
2802
3b86cd99
JK		 2803static void enable_irq_window(struct kvm_vcpu *vcpu)
2804{
2805 u32 cpu_based_vm_exec_control;
2806
2807 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2808 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2809 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2810}
2811
2812static void enable_nmi_window(struct kvm_vcpu *vcpu)
2813{
2814 u32 cpu_based_vm_exec_control;
2815
2816 if (!cpu_has_virtual_nmis()) {
2817 enable_irq_window(vcpu);
2818 return;
2819 }
2820
2821 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2822 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2823 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2824}
2825
66fd3f7f 2826static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2827{
9c8cba37 2828 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2829 uint32_t intr;
2830 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2831
229456fc 2832 trace_kvm_inj_virq(irq);
2714d1d3 2833
fa89a817 2834 ++vcpu->stat.irq_injections;
7ffd92c5 2835 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2836 vmx->rmode.irq.pending = true;
2837 vmx->rmode.irq.vector = irq;
5fdbf976 2838 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2839 if (vcpu->arch.interrupt.soft)
2840 vmx->rmode.irq.rip +=
2841 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2842 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2843 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2844 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2845 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2846 return;
2847 }
66fd3f7f
GN		 2848 intr = irq | INTR_INFO_VALID_MASK;
2849 if (vcpu->arch.interrupt.soft) {
2850 intr |= INTR_TYPE_SOFT_INTR;
2851 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2852 vmx->vcpu.arch.event_exit_inst_len);
2853 } else
2854 intr |= INTR_TYPE_EXT_INTR;
2855 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2856}
2857
f08864b4
SY		 2858static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2859{
66a5a347
JK		 2860 struct vcpu_vmx *vmx = to_vmx(vcpu);
2861
3b86cd99
JK		 2862 if (!cpu_has_virtual_nmis()) {
2863 /*
2864 * Tracking the NMI-blocked state in software is built upon
2865 * finding the next open IRQ window. This, in turn, depends on
2866 * well-behaving guests: They have to keep IRQs disabled at
2867 * least as long as the NMI handler runs. Otherwise we may
2868 * cause NMI nesting, maybe breaking the guest. But as this is
2869 * highly unlikely, we can live with the residual risk.
2870 */
2871 vmx->soft_vnmi_blocked = 1;
2872 vmx->vnmi_blocked_time = 0;
2873 }
2874
487b391d 2875 ++vcpu->stat.nmi_injections;
7ffd92c5 2876 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2877 vmx->rmode.irq.pending = true;
2878 vmx->rmode.irq.vector = NMI_VECTOR;
2879 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2880 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2881 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2882 INTR_INFO_VALID_MASK);
2883 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2884 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2885 return;
2886 }
f08864b4
SY		 2887 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2888 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2889}
2890
c4282df9 2891static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2892{
3b86cd99 2893 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2894 return 0;
33f089ca 2895
c4282df9 2896 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
f8c5fae1 2897 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2898}
2899
3cfc3092
JK		 2900static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2901{
2902 if (!cpu_has_virtual_nmis())
2903 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2904 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2905}
2906
2907static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2908{
2909 struct vcpu_vmx *vmx = to_vmx(vcpu);
2910
2911 if (!cpu_has_virtual_nmis()) {
2912 if (vmx->soft_vnmi_blocked != masked) {
2913 vmx->soft_vnmi_blocked = masked;
2914 vmx->vnmi_blocked_time = 0;
2915 }
2916 } else {
2917 if (masked)
2918 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2919 GUEST_INTR_STATE_NMI);
2920 else
2921 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2922 GUEST_INTR_STATE_NMI);
2923 }
2924}
2925
78646121
GN		 2926static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2927{
c4282df9
GN		 2928 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2929 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2930 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2931}
2932
cbc94022
IE		 2933static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2934{
2935 int ret;
2936 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2937 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2938 .guest_phys_addr = addr,
2939 .memory_size = PAGE_SIZE * 3,
2940 .flags = 0,
2941 };
2942
2943 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2944 if (ret)
2945 return ret;
bfc6d222 2946 kvm->arch.tss_addr = addr;
cbc94022
IE		 2947 return 0;
2948}
2949
6aa8b732
AK		 2950static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2951 int vec, u32 err_code)
2952{
b3f37707
NK		 2953 /*
2954 * Instruction with address size override prefix opcode 0x67
2955 * Cause the #SS fault with 0 error code in VM86 mode.
2956 */
2957 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2958 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2959 return 1;
77ab6db0
JK		 2960 /*
2961 * Forward all other exceptions that are valid in real mode.
2962 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2963 * the required debugging infrastructure rework.
2964 */
2965 switch (vec) {
77ab6db0 2966 case DB_VECTOR:
d0bfb940
JK		 2967 if (vcpu->guest_debug &
2968 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2969 return 0;
2970 kvm_queue_exception(vcpu, vec);
2971 return 1;
77ab6db0 2972 case BP_VECTOR:
c573cd22
JK		 2973 /*
2974 * Update instruction length as we may reinject the exception
2975 * from user space while in guest debugging mode.
2976 */
2977 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2978 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2979 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2980 return 0;
2981 /* fall through */
2982 case DE_VECTOR:
77ab6db0
JK		 2983 case OF_VECTOR:
2984 case BR_VECTOR:
2985 case UD_VECTOR:
2986 case DF_VECTOR:
2987 case SS_VECTOR:
2988 case GP_VECTOR:
2989 case MF_VECTOR:
2990 kvm_queue_exception(vcpu, vec);
2991 return 1;
2992 }
6aa8b732
AK		 2993 return 0;
2994}
2995
a0861c02
AK		 2996/*
2997 * Trigger machine check on the host. We assume all the MSRs are already set up
2998 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2999 * We pass a fake environment to the machine check handler because we want
3000 * the guest to be always treated like user space, no matter what context
3001 * it used internally.
3002 */
3003static void kvm_machine_check(void)
3004{
3005#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3006 struct pt_regs regs = {
3007 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3008 .flags = X86_EFLAGS_IF,
3009 };
3010
3011 do_machine_check(&regs, 0);
3012#endif
3013}
3014
851ba692 3015static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3016{
3017 /* already handled by vcpu_run */
3018 return 1;
3019}
3020
851ba692 3021static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3022{
1155f76a 3023 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3024 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3025 u32 intr_info, ex_no, error_code;
42dbaa5a 3026 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3027 u32 vect_info;
3028 enum emulation_result er;
3029
1155f76a 3030 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 3031 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3032
a0861c02 3033 if (is_machine_check(intr_info))
851ba692 3034 return handle_machine_check(vcpu);
a0861c02 3035
6aa8b732 3036 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3037 !is_page_fault(intr_info)) {
3038 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3039 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3040 vcpu->run->internal.ndata = 2;
3041 vcpu->run->internal.data[0] = vect_info;
3042 vcpu->run->internal.data[1] = intr_info;
3043 return 0;
3044 }
6aa8b732 3045
e4a41889 3046 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3047 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3048
3049 if (is_no_device(intr_info)) {
5fd86fcf 3050 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3051 return 1;
3052 }
3053
7aa81cc0 3054 if (is_invalid_opcode(intr_info)) {
851ba692 3055 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 3056 if (er != EMULATE_DONE)
7ee5d940 3057 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3058 return 1;
3059 }
3060
6aa8b732 3061 error_code = 0;
5fdbf976 3062 rip = kvm_rip_read(vcpu);
2e11384c 3063 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3064 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3065 if (is_page_fault(intr_info)) {
1439442c 3066 /* EPT won't cause page fault directly */
089d034e 3067 if (enable_ept)
1439442c 3068 BUG();
6aa8b732 3069 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3070 trace_kvm_page_fault(cr2, error_code);
3071
3298b75c 3072 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3073 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 3074 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 3075 }
3076
7ffd92c5 3077 if (vmx->rmode.vm86_active &&
6aa8b732 3078 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3079 error_code)) {
ad312c7c
ZX		 3080 if (vcpu->arch.halt_request) {
3081 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3082 return kvm_emulate_halt(vcpu);
3083 }
6aa8b732 3084 return 1;
72d6e5a0 3085 }
6aa8b732 3086
d0bfb940 3087 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3088 switch (ex_no) {
3089 case DB_VECTOR:
3090 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3091 if (!(vcpu->guest_debug &
3092 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3093 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3094 kvm_queue_exception(vcpu, DB_VECTOR);
3095 return 1;
3096 }
3097 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3098 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3099 /* fall through */
3100 case BP_VECTOR:
c573cd22
JK		 3101 /*
3102 * Update instruction length as we may reinject #BP from
3103 * user space while in guest debugging mode. Reading it for
3104 * #DB as well causes no harm, it is not used in that case.
3105 */
3106 vmx->vcpu.arch.event_exit_inst_len =
3107 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3108 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3109 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3110 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3111 break;
3112 default:
d0bfb940
JK		 3113 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3114 kvm_run->ex.exception = ex_no;
3115 kvm_run->ex.error_code = error_code;
42dbaa5a 3116 break;
6aa8b732 3117 }
6aa8b732
AK		 3118 return 0;
3119}
3120
851ba692 3121static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3122{
1165f5fe 3123 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3124 return 1;
3125}
3126
851ba692 3127static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3128{
851ba692 3129 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3130 return 0;
3131}
6aa8b732 3132
851ba692 3133static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3134{
bfdaab09 3135 unsigned long exit_qualification;
34c33d16 3136 int size, in, string;
039576c0 3137 unsigned port;
6aa8b732 3138
bfdaab09 3139 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3140 string = (exit_qualification & 16) != 0;
cf8f70bf 3141 in = (exit_qualification & 8) != 0;
e70669ab 3142
cf8f70bf 3143 ++vcpu->stat.io_exits;
e70669ab 3144
cf8f70bf 3145 if (string || in)
6d77dbfc 3146 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
e70669ab 3147
cf8f70bf
GN		 3148 port = exit_qualification >> 16;
3149 size = (exit_qualification & 7) + 1;
e93f36bc 3150 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3151
3152 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3153}
3154
102d8325
IM		 3155static void
3156vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3157{
3158 /*
3159 * Patch in the VMCALL instruction:
3160 */
3161 hypercall[0] = 0x0f;
3162 hypercall[1] = 0x01;
3163 hypercall[2] = 0xc1;
102d8325
IM		 3164}
3165
49a9b07e
AK		 3166static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3167{
3168 if (err)
3169 kvm_inject_gp(vcpu, 0);
3170 else
3171 skip_emulated_instruction(vcpu);
3172}
3173
851ba692 3174static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3175{
229456fc 3176 unsigned long exit_qualification, val;
6aa8b732
AK		 3177 int cr;
3178 int reg;
49a9b07e 3179 int err;
6aa8b732 3180
bfdaab09 3181 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3182 cr = exit_qualification & 15;
3183 reg = (exit_qualification >> 8) & 15;
3184 switch ((exit_qualification >> 4) & 3) {
3185 case 0: /* mov to cr */
229456fc
MT		 3186 val = kvm_register_read(vcpu, reg);
3187 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3188 switch (cr) {
3189 case 0:
49a9b07e
AK		 3190 err = kvm_set_cr0(vcpu, val);
3191 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3192 return 1;
3193 case 3:
2390218b
AK		 3194 err = kvm_set_cr3(vcpu, val);
3195 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3196 return 1;
3197 case 4:
a83b29c6
AK		 3198 err = kvm_set_cr4(vcpu, val);
3199 complete_insn_gp(vcpu, err);
6aa8b732 3200 return 1;
0a5fff19
GN		 3201 case 8: {
3202 u8 cr8_prev = kvm_get_cr8(vcpu);
3203 u8 cr8 = kvm_register_read(vcpu, reg);
3204 kvm_set_cr8(vcpu, cr8);
3205 skip_emulated_instruction(vcpu);
3206 if (irqchip_in_kernel(vcpu->kvm))
3207 return 1;
3208 if (cr8_prev <= cr8)
3209 return 1;
851ba692 3210 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3211 return 0;
3212 }
6aa8b732
AK		 3213 };
3214 break;
25c4c276 3215 case 2: /* clts */
edcafe3c 3216 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3217 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3218 skip_emulated_instruction(vcpu);
6b52d186 3219 vmx_fpu_activate(vcpu);
25c4c276 3220 return 1;
6aa8b732
AK		 3221 case 1: /*mov from cr*/
3222 switch (cr) {
3223 case 3:
5fdbf976 3224 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3225 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3226 skip_emulated_instruction(vcpu);
3227 return 1;
3228 case 8:
229456fc
MT		 3229 val = kvm_get_cr8(vcpu);
3230 kvm_register_write(vcpu, reg, val);
3231 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3232 skip_emulated_instruction(vcpu);
3233 return 1;
3234 }
3235 break;
3236 case 3: /* lmsw */
a1f83a74 3237 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3238 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3239 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3240
3241 skip_emulated_instruction(vcpu);
3242 return 1;
3243 default:
3244 break;
3245 }
851ba692 3246 vcpu->run->exit_reason = 0;
f0242478 3247 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3248 (int)(exit_qualification >> 4) & 3, cr);
3249 return 0;
3250}
3251
851ba692 3252static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3253{
bfdaab09 3254 unsigned long exit_qualification;
6aa8b732
AK		 3255 int dr, reg;
3256
f2483415 3257 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3258 if (!kvm_require_cpl(vcpu, 0))
3259 return 1;
42dbaa5a
JK		 3260 dr = vmcs_readl(GUEST_DR7);
3261 if (dr & DR7_GD) {
3262 /*
3263 * As the vm-exit takes precedence over the debug trap, we
3264 * need to emulate the latter, either for the host or the
3265 * guest debugging itself.
3266 */
3267 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3268 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3269 vcpu->run->debug.arch.dr7 = dr;
3270 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3271 vmcs_readl(GUEST_CS_BASE) +
3272 vmcs_readl(GUEST_RIP);
851ba692
AK		 3273 vcpu->run->debug.arch.exception = DB_VECTOR;
3274 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3275 return 0;
3276 } else {
3277 vcpu->arch.dr7 &= ~DR7_GD;
3278 vcpu->arch.dr6 |= DR6_BD;
3279 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3280 kvm_queue_exception(vcpu, DB_VECTOR);
3281 return 1;
3282 }
3283 }
3284
bfdaab09 3285 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3286 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3287 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3288 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3289 unsigned long val;
3290 if (!kvm_get_dr(vcpu, dr, &val))
3291 kvm_register_write(vcpu, reg, val);
3292 } else
3293 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3294 skip_emulated_instruction(vcpu);
3295 return 1;
3296}
3297
020df079
GN		 3298static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3299{
3300 vmcs_writel(GUEST_DR7, val);
3301}
3302
851ba692 3303static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3304{
06465c5a
AK		 3305 kvm_emulate_cpuid(vcpu);
3306 return 1;
6aa8b732
AK		 3307}
3308
851ba692 3309static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3310{
ad312c7c 3311 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3312 u64 data;
3313
3314 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3315 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3316 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3317 return 1;
3318 }
3319
229456fc 3320 trace_kvm_msr_read(ecx, data);
2714d1d3 3321
6aa8b732 3322 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3323 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3324 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3325 skip_emulated_instruction(vcpu);
3326 return 1;
3327}
3328
851ba692 3329static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3330{
ad312c7c
ZX		 3331 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3332 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3333 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3334
3335 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3336 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3337 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3338 return 1;
3339 }
3340
59200273 3341 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3342 skip_emulated_instruction(vcpu);
3343 return 1;
3344}
3345
851ba692 3346static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3347{
3348 return 1;
3349}
3350
851ba692 3351static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3352{
85f455f7
ED		 3353 u32 cpu_based_vm_exec_control;
3354
3355 /* clear pending irq */
3356 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3357 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3358 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3359
a26bf12a 3360 ++vcpu->stat.irq_window_exits;
2714d1d3 3361
c1150d8c
DL		 3362 /*
3363 * If the user space waits to inject interrupts, exit as soon as
3364 * possible
3365 */
8061823a 3366 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3367 vcpu->run->request_interrupt_window &&
8061823a 3368 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3369 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3370 return 0;
3371 }
6aa8b732
AK		 3372 return 1;
3373}
3374
851ba692 3375static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3376{
3377 skip_emulated_instruction(vcpu);
d3bef15f 3378 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3379}
3380
851ba692 3381static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3382{
510043da 3383 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3384 kvm_emulate_hypercall(vcpu);
3385 return 1;
c21415e8
IM		 3386}
3387
851ba692 3388static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3389{
3390 kvm_queue_exception(vcpu, UD_VECTOR);
3391 return 1;
3392}
3393
851ba692 3394static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3395{
f9c617f6 3396 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3397
3398 kvm_mmu_invlpg(vcpu, exit_qualification);
3399 skip_emulated_instruction(vcpu);
3400 return 1;
3401}
3402
851ba692 3403static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3404{
3405 skip_emulated_instruction(vcpu);
f5f48ee1 3406 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3407 return 1;
3408}
3409
2acf923e
DC		 3410static int handle_xsetbv(struct kvm_vcpu *vcpu)
3411{
3412 u64 new_bv = kvm_read_edx_eax(vcpu);
3413 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3414
3415 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3416 skip_emulated_instruction(vcpu);
3417 return 1;
3418}
3419
851ba692 3420static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3421{
6d77dbfc 3422 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
f78e0e2e
SY		 3423}
3424
851ba692 3425static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3426{
60637aac 3427 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3428 unsigned long exit_qualification;
e269fb21
JK		 3429 bool has_error_code = false;
3430 u32 error_code = 0;
37817f29 3431 u16 tss_selector;
64a7ec06
GN		 3432 int reason, type, idt_v;
3433
3434 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3435 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3436
3437 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3438
3439 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3440 if (reason == TASK_SWITCH_GATE && idt_v) {
3441 switch (type) {
3442 case INTR_TYPE_NMI_INTR:
3443 vcpu->arch.nmi_injected = false;
3444 if (cpu_has_virtual_nmis())
3445 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3446 GUEST_INTR_STATE_NMI);
3447 break;
3448 case INTR_TYPE_EXT_INTR:
66fd3f7f 3449 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3450 kvm_clear_interrupt_queue(vcpu);
3451 break;
3452 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3453 if (vmx->idt_vectoring_info &
3454 VECTORING_INFO_DELIVER_CODE_MASK) {
3455 has_error_code = true;
3456 error_code =
3457 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3458 }
3459 /* fall through */
64a7ec06
GN		 3460 case INTR_TYPE_SOFT_EXCEPTION:
3461 kvm_clear_exception_queue(vcpu);
3462 break;
3463 default:
3464 break;
3465 }
60637aac 3466 }
37817f29
IE		 3467 tss_selector = exit_qualification;
3468
64a7ec06
GN		 3469 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3470 type != INTR_TYPE_EXT_INTR &&
3471 type != INTR_TYPE_NMI_INTR))
3472 skip_emulated_instruction(vcpu);
3473
acb54517
GN		 3474 if (kvm_task_switch(vcpu, tss_selector, reason,
3475 has_error_code, error_code) == EMULATE_FAIL) {
3476 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3477 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3478 vcpu->run->internal.ndata = 0;
42dbaa5a 3479 return 0;
acb54517 3480 }
42dbaa5a
JK		 3481
3482 /* clear all local breakpoint enable flags */
3483 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3484
3485 /*
3486 * TODO: What about debug traps on tss switch?
3487 * Are we supposed to inject them and update dr6?
3488 */
3489
3490 return 1;
37817f29
IE		 3491}
3492
851ba692 3493static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3494{
f9c617f6 3495 unsigned long exit_qualification;
1439442c 3496 gpa_t gpa;
1439442c 3497 int gla_validity;
1439442c 3498
f9c617f6 3499 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3500
3501 if (exit_qualification & (1 << 6)) {
3502 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3503 return -EINVAL;
1439442c
SY		 3504 }
3505
3506 gla_validity = (exit_qualification >> 7) & 0x3;
3507 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3508 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3509 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3510 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3511 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3512 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3513 (long unsigned int)exit_qualification);
851ba692
AK		 3514 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3515 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3516 return 0;
1439442c
SY		 3517 }
3518
3519 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3520 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3521 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3522}
3523
68f89400
MT		 3524static u64 ept_rsvd_mask(u64 spte, int level)
3525{
3526 int i;
3527 u64 mask = 0;
3528
3529 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3530 mask |= (1ULL << i);
3531
3532 if (level > 2)
3533 /* bits 7:3 reserved */
3534 mask |= 0xf8;
3535 else if (level == 2) {
3536 if (spte & (1ULL << 7))
3537 /* 2MB ref, bits 20:12 reserved */
3538 mask |= 0x1ff000;
3539 else
3540 /* bits 6:3 reserved */
3541 mask |= 0x78;
3542 }
3543
3544 return mask;
3545}
3546
3547static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3548 int level)
3549{
3550 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3551
3552 /* 010b (write-only) */
3553 WARN_ON((spte & 0x7) == 0x2);
3554
3555 /* 110b (write/execute) */
3556 WARN_ON((spte & 0x7) == 0x6);
3557
3558 /* 100b (execute-only) and value not supported by logical processor */
3559 if (!cpu_has_vmx_ept_execute_only())
3560 WARN_ON((spte & 0x7) == 0x4);
3561
3562 /* not 000b */
3563 if ((spte & 0x7)) {
3564 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3565
3566 if (rsvd_bits != 0) {
3567 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3568 __func__, rsvd_bits);
3569 WARN_ON(1);
3570 }
3571
3572 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3573 u64 ept_mem_type = (spte & 0x38) >> 3;
3574
3575 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3576 ept_mem_type == 7) {
3577 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3578 __func__, ept_mem_type);
3579 WARN_ON(1);
3580 }
3581 }
3582 }
3583}
3584
851ba692 3585static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3586{
3587 u64 sptes[4];
3588 int nr_sptes, i;
3589 gpa_t gpa;
3590
3591 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3592
3593 printk(KERN_ERR "EPT: Misconfiguration.\n");
3594 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3595
3596 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3597
3598 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3599 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3600
851ba692
AK		 3601 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3602 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3603
3604 return 0;
3605}
3606
851ba692 3607static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3608{
3609 u32 cpu_based_vm_exec_control;
3610
3611 /* clear pending NMI */
3612 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3613 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3614 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3615 ++vcpu->stat.nmi_window_exits;
3616
3617 return 1;
3618}
3619
80ced186 3620static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3621{
8b3079a5
AK		 3622 struct vcpu_vmx *vmx = to_vmx(vcpu);
3623 enum emulation_result err = EMULATE_DONE;
80ced186 3624 int ret = 1;
ea953ef0
MG		 3625
3626 while (!guest_state_valid(vcpu)) {
851ba692 3627 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3628
80ced186
MG		 3629 if (err == EMULATE_DO_MMIO) {
3630 ret = 0;
3631 goto out;
3632 }
1d5a4d9b 3633
6d77dbfc
GN		 3634 if (err != EMULATE_DONE)
3635 return 0;
ea953ef0
MG		 3636
3637 if (signal_pending(current))
80ced186 3638 goto out;
ea953ef0
MG		 3639 if (need_resched())
3640 schedule();
3641 }
3642
80ced186
MG		 3643 vmx->emulation_required = 0;
3644out:
3645 return ret;
ea953ef0
MG		 3646}
3647
4b8d54f9
ZE		 3648/*
3649 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3650 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3651 */
9fb41ba8 3652static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3653{
3654 skip_emulated_instruction(vcpu);
3655 kvm_vcpu_on_spin(vcpu);
3656
3657 return 1;
3658}
3659
59708670
SY		 3660static int handle_invalid_op(struct kvm_vcpu *vcpu)
3661{
3662 kvm_queue_exception(vcpu, UD_VECTOR);
3663 return 1;
3664}
3665
6aa8b732
AK		 3666/*
3667 * The exit handlers return 1 if the exit was handled fully and guest execution
3668 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3669 * to be done to userspace and return 0.
3670 */
851ba692 3671static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3672 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3673 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3674 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3675 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3676 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3677 [EXIT_REASON_CR_ACCESS] = handle_cr,
3678 [EXIT_REASON_DR_ACCESS] = handle_dr,
3679 [EXIT_REASON_CPUID] = handle_cpuid,
3680 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3681 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3682 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3683 [EXIT_REASON_HLT] = handle_halt,
a7052897 3684 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3685 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3686 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3687 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3688 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3689 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3690 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3691 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3692 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3693 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3694 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3695 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3696 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3697 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3698 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3699 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3700 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3701 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3702 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3703 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3704 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3705 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3706};
3707
3708static const int kvm_vmx_max_exit_handlers =
50a3485c 3709 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3710
3711/*
3712 * The guest has exited. See if we can fix it or if we need userspace
3713 * assistance.
3714 */
851ba692 3715static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3716{
29bd8a78 3717 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3718 u32 exit_reason = vmx->exit_reason;
1155f76a 3719 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3720
5bfd8b54 3721 trace_kvm_exit(exit_reason, vcpu);
2714d1d3 3722
80ced186
MG		 3723 /* If guest state is invalid, start emulating */
3724 if (vmx->emulation_required && emulate_invalid_guest_state)
3725 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3726
1439442c
SY		 3727 /* Access CR3 don't cause VMExit in paging mode, so we need
3728 * to sync with guest real CR3. */
6de4f3ad 3729 if (enable_ept && is_paging(vcpu))
1439442c 3730 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3731
5120702e
MG		 3732 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3733 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3734 vcpu->run->fail_entry.hardware_entry_failure_reason
3735 = exit_reason;
3736 return 0;
3737 }
3738
29bd8a78 3739 if (unlikely(vmx->fail)) {
851ba692
AK		 3740 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3741 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3742 = vmcs_read32(VM_INSTRUCTION_ERROR);
3743 return 0;
3744 }
6aa8b732 3745
d77c26fc 3746 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3747 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3748 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3749 exit_reason != EXIT_REASON_TASK_SWITCH))
3750 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3751 "(0x%x) and exit reason is 0x%x\n",
3752 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3753
3754 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3755 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3756 vmx->soft_vnmi_blocked = 0;
3b86cd99 3757 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3758 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3759 /*
3760 * This CPU don't support us in finding the end of an
3761 * NMI-blocked window if the guest runs with IRQs
3762 * disabled. So we pull the trigger after 1 s of
3763 * futile waiting, but inform the user about this.
3764 */
3765 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3766 "state on VCPU %d after 1 s timeout\n",
3767 __func__, vcpu->vcpu_id);
3768 vmx->soft_vnmi_blocked = 0;
3b86cd99 3769 }
3b86cd99
JK		 3770 }
3771
6aa8b732
AK		 3772 if (exit_reason < kvm_vmx_max_exit_handlers
3773 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3774 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3775 else {
851ba692
AK		 3776 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3777 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3778 }
3779 return 0;
3780}
3781
95ba8273 3782static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3783{
95ba8273 3784 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3785 vmcs_write32(TPR_THRESHOLD, 0);
3786 return;
3787 }
3788
95ba8273 3789 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3790}
3791
cf393f75
AK		 3792static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3793{
3794 u32 exit_intr_info;
7b4a25cb 3795 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3796 bool unblock_nmi;
3797 u8 vector;
668f612f
AK		 3798 int type;
3799 bool idtv_info_valid;
cf393f75
AK		 3800
3801 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3802
a0861c02
AK		 3803 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3804
3805 /* Handle machine checks before interrupts are enabled */
3806 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3807 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3808 && is_machine_check(exit_intr_info)))
3809 kvm_machine_check();
3810
20f65983
GN		 3811 /* We need to handle NMIs before interrupts are enabled */
3812 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3813 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3814 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3815 asm("int $2");
ff9d07a0
ZY		 3816 kvm_after_handle_nmi(&vmx->vcpu);
3817 }
20f65983
GN		 3818
3819 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3820
cf393f75
AK		 3821 if (cpu_has_virtual_nmis()) {
3822 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3823 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3824 /*
7b4a25cb 3825 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3826 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3827 * a guest IRET fault.
7b4a25cb
GN		 3828 * SDM 3: 23.2.2 (September 2008)
3829 * Bit 12 is undefined in any of the following cases:
3830 * If the VM exit sets the valid bit in the IDT-vectoring
3831 * information field.
3832 * If the VM exit is due to a double fault.
cf393f75 3833 */
7b4a25cb
GN		 3834 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3835 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3836 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3837 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3838 } else if (unlikely(vmx->soft_vnmi_blocked))
3839 vmx->vnmi_blocked_time +=
3840 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3841
37b96e98
GN		 3842 vmx->vcpu.arch.nmi_injected = false;
3843 kvm_clear_exception_queue(&vmx->vcpu);
3844 kvm_clear_interrupt_queue(&vmx->vcpu);
3845
3846 if (!idtv_info_valid)
3847 return;
3848
668f612f
AK		 3849 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3850 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3851
64a7ec06 3852 switch (type) {
37b96e98
GN		 3853 case INTR_TYPE_NMI_INTR:
3854 vmx->vcpu.arch.nmi_injected = true;
668f612f 3855 /*
7b4a25cb 3856 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3857 * Clear bit "block by NMI" before VM entry if a NMI
3858 * delivery faulted.
668f612f 3859 */
37b96e98
GN		 3860 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3861 GUEST_INTR_STATE_NMI);
3862 break;
37b96e98 3863 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3864 vmx->vcpu.arch.event_exit_inst_len =
3865 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3866 /* fall through */
3867 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3868 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3869 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3870 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3871 } else
3872 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3873 break;
66fd3f7f
GN		 3874 case INTR_TYPE_SOFT_INTR:
3875 vmx->vcpu.arch.event_exit_inst_len =
3876 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3877 /* fall through */
37b96e98 3878 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3879 kvm_queue_interrupt(&vmx->vcpu, vector,
3880 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3881 break;
3882 default:
3883 break;
f7d9238f 3884 }
cf393f75
AK		 3885}
3886
9c8cba37
AK		 3887/*
3888 * Failure to inject an interrupt should give us the information
3889 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3890 * when fetching the interrupt redirection bitmap in the real-mode
3891 * tss, this doesn't happen. So we do it ourselves.
3892 */
3893static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3894{
3895 vmx->rmode.irq.pending = 0;
5fdbf976 3896 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3897 return;
5fdbf976 3898 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3899 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3900 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3901 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3902 return;
3903 }
3904 vmx->idt_vectoring_info =
3905 VECTORING_INFO_VALID_MASK
3906 | INTR_TYPE_EXT_INTR
3907 | vmx->rmode.irq.vector;
3908}
3909
c801949d
AK		 3910#ifdef CONFIG_X86_64
3911#define R "r"
3912#define Q "q"
3913#else
3914#define R "e"
3915#define Q "l"
3916#endif
3917
851ba692 3918static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3919{
a2fa3e9f 3920 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3921
3b86cd99
JK		 3922 /* Record the guest's net vcpu time for enforced NMI injections. */
3923 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3924 vmx->entry_time = ktime_get();
3925
80ced186
MG		 3926 /* Don't enter VMX if guest state is invalid, let the exit handler
3927 start emulation until we arrive back to a valid state */
3928 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3929 return;
a89a8fb9 3930
5fdbf976
MT		 3931 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3932 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3933 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3934 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3935
787ff736
GN		 3936 /* When single-stepping over STI and MOV SS, we must clear the
3937 * corresponding interruptibility bits in the guest state. Otherwise
3938 * vmentry fails as it then expects bit 14 (BS) in pending debug
3939 * exceptions being set, but that's not correct for the guest debugging
3940 * case. */
3941 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3942 vmx_set_interrupt_shadow(vcpu, 0);
3943
d77c26fc 3944 asm(
6aa8b732 3945 /* Store host registers */
c801949d
AK		 3946 "push %%"R"dx; push %%"R"bp;"
3947 "push %%"R"cx \n\t"
313dbd49
AK		 3948 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3949 "je 1f \n\t"
3950 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3951 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3952 "1: \n\t"
d3edefc0
AK		 3953 /* Reload cr2 if changed */
3954 "mov %c[cr2](%0), %%"R"ax \n\t"
3955 "mov %%cr2, %%"R"dx \n\t"
3956 "cmp %%"R"ax, %%"R"dx \n\t"
3957 "je 2f \n\t"
3958 "mov %%"R"ax, %%cr2 \n\t"
3959 "2: \n\t"
6aa8b732 3960 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3961 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3962 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3963 "mov %c[rax](%0), %%"R"ax \n\t"
3964 "mov %c[rbx](%0), %%"R"bx \n\t"
3965 "mov %c[rdx](%0), %%"R"dx \n\t"
3966 "mov %c[rsi](%0), %%"R"si \n\t"
3967 "mov %c[rdi](%0), %%"R"di \n\t"
3968 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3969#ifdef CONFIG_X86_64
e08aa78a
AK		 3970 "mov %c[r8](%0), %%r8 \n\t"
3971 "mov %c[r9](%0), %%r9 \n\t"
3972 "mov %c[r10](%0), %%r10 \n\t"
3973 "mov %c[r11](%0), %%r11 \n\t"
3974 "mov %c[r12](%0), %%r12 \n\t"
3975 "mov %c[r13](%0), %%r13 \n\t"
3976 "mov %c[r14](%0), %%r14 \n\t"
3977 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3978#endif
c801949d
AK		 3979 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3980
6aa8b732 3981 /* Enter guest mode */
cd2276a7 3982 "jne .Llaunched \n\t"
4ecac3fd 3983 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3984 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3985 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3986 ".Lkvm_vmx_return: "
6aa8b732 3987 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3988 "xchg %0, (%%"R"sp) \n\t"
3989 "mov %%"R"ax, %c[rax](%0) \n\t"
3990 "mov %%"R"bx, %c[rbx](%0) \n\t"
3991 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3992 "mov %%"R"dx, %c[rdx](%0) \n\t"
3993 "mov %%"R"si, %c[rsi](%0) \n\t"
3994 "mov %%"R"di, %c[rdi](%0) \n\t"
3995 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3996#ifdef CONFIG_X86_64
e08aa78a
AK		 3997 "mov %%r8, %c[r8](%0) \n\t"
3998 "mov %%r9, %c[r9](%0) \n\t"
3999 "mov %%r10, %c[r10](%0) \n\t"
4000 "mov %%r11, %c[r11](%0) \n\t"
4001 "mov %%r12, %c[r12](%0) \n\t"
4002 "mov %%r13, %c[r13](%0) \n\t"
4003 "mov %%r14, %c[r14](%0) \n\t"
4004 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 4005#endif
c801949d
AK		 4006 "mov %%cr2, %%"R"ax \n\t"
4007 "mov %%"R"ax, %c[cr2](%0) \n\t"
4008
4009 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 4010 "setbe %c[fail](%0) \n\t"
4011 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4012 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4013 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 4014 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 4015 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4016 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4017 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4018 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4019 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4020 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4021 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4022#ifdef CONFIG_X86_64
ad312c7c
ZX		 4023 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4024 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4025 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4026 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4027 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4028 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4029 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4030 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4031#endif
ad312c7c 4032 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 4033 : "cc", "memory"
c801949d 4034 , R"bx", R"di", R"si"
c2036300 4035#ifdef CONFIG_X86_64
c2036300
LV		 4036 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4037#endif
4038 );
6aa8b732 4039
6de4f3ad
AK		 4040 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4041 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 4042 vcpu->arch.regs_dirty = 0;
4043
1155f76a 4044 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 4045 if (vmx->rmode.irq.pending)
4046 fixup_rmode_irq(vmx);
1155f76a 4047
d77c26fc 4048 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4049 vmx->launched = 1;
1b6269db 4050
cf393f75 4051 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4052}
4053
c801949d
AK		 4054#undef R
4055#undef Q
4056
6aa8b732
AK		 4057static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4058{
a2fa3e9f
GH		 4059 struct vcpu_vmx *vmx = to_vmx(vcpu);
4060
4061 if (vmx->vmcs) {
543e4243 4062 vcpu_clear(vmx);
a2fa3e9f
GH		 4063 free_vmcs(vmx->vmcs);
4064 vmx->vmcs = NULL;
6aa8b732
AK		 4065 }
4066}
4067
4068static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4069{
fb3f0f51
RR		 4070 struct vcpu_vmx *vmx = to_vmx(vcpu);
4071
cdbecfc3 4072 free_vpid(vmx);
6aa8b732 4073 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4074 kfree(vmx->guest_msrs);
4075 kvm_vcpu_uninit(vcpu);
a4770347 4076 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4077}
4078
4610c9cc
DX		 4079static inline void vmcs_init(struct vmcs *vmcs)
4080{
4081 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4082
4083 if (!vmm_exclusive)
4084 kvm_cpu_vmxon(phys_addr);
4085
4086 vmcs_clear(vmcs);
4087
4088 if (!vmm_exclusive)
4089 kvm_cpu_vmxoff();
4090}
4091
fb3f0f51 4092static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4093{
fb3f0f51 4094 int err;
c16f862d 4095 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4096 int cpu;
6aa8b732 4097
a2fa3e9f 4098 if (!vmx)
fb3f0f51
RR		 4099 return ERR_PTR(-ENOMEM);
4100
2384d2b3
SY		 4101 allocate_vpid(vmx);
4102
fb3f0f51
RR		 4103 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4104 if (err)
4105 goto free_vcpu;
965b58a5 4106
a2fa3e9f 4107 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4108 if (!vmx->guest_msrs) {
4109 err = -ENOMEM;
4110 goto uninit_vcpu;
4111 }
965b58a5 4112
a2fa3e9f
GH		 4113 vmx->vmcs = alloc_vmcs();
4114 if (!vmx->vmcs)
fb3f0f51 4115 goto free_msrs;
a2fa3e9f 4116
4610c9cc 4117 vmcs_init(vmx->vmcs);
a2fa3e9f 4118
15ad7146
AK		 4119 cpu = get_cpu();
4120 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 4121 err = vmx_vcpu_setup(vmx);
fb3f0f51 4122 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4123 put_cpu();
fb3f0f51
RR		 4124 if (err)
4125 goto free_vmcs;
5e4a0b3c
MT		 4126 if (vm_need_virtualize_apic_accesses(kvm))
4127 if (alloc_apic_access_page(kvm) != 0)
4128 goto free_vmcs;
fb3f0f51 4129
b927a3ce
SY		 4130 if (enable_ept) {
4131 if (!kvm->arch.ept_identity_map_addr)
4132 kvm->arch.ept_identity_map_addr =
4133 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4134 if (alloc_identity_pagetable(kvm) != 0)
4135 goto free_vmcs;
b927a3ce 4136 }
b7ebfb05 4137
fb3f0f51
RR		 4138 return &vmx->vcpu;
4139
4140free_vmcs:
4141 free_vmcs(vmx->vmcs);
4142free_msrs:
fb3f0f51
RR		 4143 kfree(vmx->guest_msrs);
4144uninit_vcpu:
4145 kvm_vcpu_uninit(&vmx->vcpu);
4146free_vcpu:
cdbecfc3 4147 free_vpid(vmx);
a4770347 4148 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4149 return ERR_PTR(err);
6aa8b732
AK		 4150}
4151
002c7f7c
YS		 4152static void __init vmx_check_processor_compat(void *rtn)
4153{
4154 struct vmcs_config vmcs_conf;
4155
4156 *(int *)rtn = 0;
4157 if (setup_vmcs_config(&vmcs_conf) < 0)
4158 *(int *)rtn = -EIO;
4159 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4160 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4161 smp_processor_id());
4162 *(int *)rtn = -EIO;
4163 }
4164}
4165
67253af5
SY		 4166static int get_ept_level(void)
4167{
4168 return VMX_EPT_DEFAULT_GAW + 1;
4169}
4170
4b12f0de 4171static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4172{
4b12f0de
SY		 4173 u64 ret;
4174
522c68c4
SY		 4175 /* For VT-d and EPT combination
4176 * 1. MMIO: always map as UC
4177 * 2. EPT with VT-d:
4178 * a. VT-d without snooping control feature: can't guarantee the
4179 * result, try to trust guest.
4180 * b. VT-d with snooping control feature: snooping control feature of
4181 * VT-d engine can guarantee the cache correctness. Just set it
4182 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4183 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4184 * consistent with host MTRR
4185 */
4b12f0de
SY		 4186 if (is_mmio)
4187 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4188 else if (vcpu->kvm->arch.iommu_domain &&
4189 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4190 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4191 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4192 else
522c68c4 4193 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4194 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4195
4196 return ret;
64d4d521
SY		 4197}
4198
f4c9e87c
AK		 4199#define _ER(x) { EXIT_REASON_##x, #x }
4200
229456fc 4201static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4202 _ER(EXCEPTION_NMI),
4203 _ER(EXTERNAL_INTERRUPT),
4204 _ER(TRIPLE_FAULT),
4205 _ER(PENDING_INTERRUPT),
4206 _ER(NMI_WINDOW),
4207 _ER(TASK_SWITCH),
4208 _ER(CPUID),
4209 _ER(HLT),
4210 _ER(INVLPG),
4211 _ER(RDPMC),
4212 _ER(RDTSC),
4213 _ER(VMCALL),
4214 _ER(VMCLEAR),
4215 _ER(VMLAUNCH),
4216 _ER(VMPTRLD),
4217 _ER(VMPTRST),
4218 _ER(VMREAD),
4219 _ER(VMRESUME),
4220 _ER(VMWRITE),
4221 _ER(VMOFF),
4222 _ER(VMON),
4223 _ER(CR_ACCESS),
4224 _ER(DR_ACCESS),
4225 _ER(IO_INSTRUCTION),
4226 _ER(MSR_READ),
4227 _ER(MSR_WRITE),
4228 _ER(MWAIT_INSTRUCTION),
4229 _ER(MONITOR_INSTRUCTION),
4230 _ER(PAUSE_INSTRUCTION),
4231 _ER(MCE_DURING_VMENTRY),
4232 _ER(TPR_BELOW_THRESHOLD),
4233 _ER(APIC_ACCESS),
4234 _ER(EPT_VIOLATION),
4235 _ER(EPT_MISCONFIG),
4236 _ER(WBINVD),
229456fc
MT		 4237 { -1, NULL }
4238};
4239
f4c9e87c
AK		 4240#undef _ER
4241
17cc3935 4242static int vmx_get_lpage_level(void)
344f414f 4243{
878403b7
SY		 4244 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4245 return PT_DIRECTORY_LEVEL;
4246 else
4247 /* For shadow and EPT supported 1GB page */
4248 return PT_PDPE_LEVEL;
344f414f
JR		 4249}
4250
4e47c7a6
SY		 4251static inline u32 bit(int bitno)
4252{
4253 return 1 << (bitno & 31);
4254}
4255
0e851880
SY		 4256static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4257{
4e47c7a6
SY		 4258 struct kvm_cpuid_entry2 *best;
4259 struct vcpu_vmx *vmx = to_vmx(vcpu);
4260 u32 exec_control;
4261
4262 vmx->rdtscp_enabled = false;
4263 if (vmx_rdtscp_supported()) {
4264 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4265 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4266 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4267 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4268 vmx->rdtscp_enabled = true;
4269 else {
4270 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4271 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4272 exec_control);
4273 }
4274 }
4275 }
0e851880
SY		 4276}
4277
d4330ef2
JR		 4278static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4279{
4280}
4281
cbdd1bea 4282static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4283 .cpu_has_kvm_support = cpu_has_kvm_support,
4284 .disabled_by_bios = vmx_disabled_by_bios,
4285 .hardware_setup = hardware_setup,
4286 .hardware_unsetup = hardware_unsetup,
002c7f7c 4287 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4288 .hardware_enable = hardware_enable,
4289 .hardware_disable = hardware_disable,
04547156 4290 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4291
4292 .vcpu_create = vmx_create_vcpu,
4293 .vcpu_free = vmx_free_vcpu,
04d2cc77 4294 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4295
04d2cc77 4296 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4297 .vcpu_load = vmx_vcpu_load,
4298 .vcpu_put = vmx_vcpu_put,
4299
4300 .set_guest_debug = set_guest_debug,
4301 .get_msr = vmx_get_msr,
4302 .set_msr = vmx_set_msr,
4303 .get_segment_base = vmx_get_segment_base,
4304 .get_segment = vmx_get_segment,
4305 .set_segment = vmx_set_segment,
2e4d2653 4306 .get_cpl = vmx_get_cpl,
6aa8b732 4307 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4308 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4309 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4310 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4311 .set_cr3 = vmx_set_cr3,
4312 .set_cr4 = vmx_set_cr4,
6aa8b732 4313 .set_efer = vmx_set_efer,
6aa8b732
AK		 4314 .get_idt = vmx_get_idt,
4315 .set_idt = vmx_set_idt,
4316 .get_gdt = vmx_get_gdt,
4317 .set_gdt = vmx_set_gdt,
020df079 4318 .set_dr7 = vmx_set_dr7,
5fdbf976 4319 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4320 .get_rflags = vmx_get_rflags,
4321 .set_rflags = vmx_set_rflags,
ebcbab4c 4322 .fpu_activate = vmx_fpu_activate,
02daab21 4323 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4324
4325 .tlb_flush = vmx_flush_tlb,
6aa8b732 4326
6aa8b732 4327 .run = vmx_vcpu_run,
6062d012 4328 .handle_exit = vmx_handle_exit,
6aa8b732 4329 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4330 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4331 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4332 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4333 .set_irq = vmx_inject_irq,
95ba8273 4334 .set_nmi = vmx_inject_nmi,
298101da 4335 .queue_exception = vmx_queue_exception,
78646121 4336 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4337 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4338 .get_nmi_mask = vmx_get_nmi_mask,
4339 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4340 .enable_nmi_window = enable_nmi_window,
4341 .enable_irq_window = enable_irq_window,
4342 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4343
cbc94022 4344 .set_tss_addr = vmx_set_tss_addr,
67253af5 4345 .get_tdp_level = get_ept_level,
4b12f0de 4346 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4347
4348 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4349 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4350
4351 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4352
4353 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4354
4355 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4356
4357 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
6aa8b732
AK		 4358};
4359
4360static int __init vmx_init(void)
4361{
26bb0981
AK		 4362 int r, i;
4363
4364 rdmsrl_safe(MSR_EFER, &host_efer);
4365
4366 for (i = 0; i < NR_VMX_MSR; ++i)
4367 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4368
3e7c73e9 4369 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4370 if (!vmx_io_bitmap_a)
4371 return -ENOMEM;
4372
3e7c73e9 4373 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4374 if (!vmx_io_bitmap_b) {
4375 r = -ENOMEM;
4376 goto out;
4377 }
4378
5897297b
AK		 4379 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4380 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4381 r = -ENOMEM;
4382 goto out1;
4383 }
4384
5897297b
AK		 4385 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4386 if (!vmx_msr_bitmap_longmode) {
4387 r = -ENOMEM;
4388 goto out2;
4389 }
4390
fdef3ad1
HQ		 4391 /*
4392 * Allow direct access to the PC debug port (it is often used for I/O
4393 * delays, but the vmexits simply slow things down).
4394 */
3e7c73e9
AK		 4395 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4396 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4397
3e7c73e9 4398 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4399
5897297b
AK		 4400 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4401 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4402
2384d2b3
SY		 4403 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4404
0ee75bea
AK		 4405 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4406 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4407 if (r)
5897297b 4408 goto out3;
25c5f225 4409
5897297b
AK		 4410 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4411 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4412 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4413 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4414 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4415 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4416
089d034e 4417 if (enable_ept) {
1439442c 4418 bypass_guest_pf = 0;
5fdbcb9d 4419 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4420 VMX_EPT_WRITABLE_MASK);
534e38b4 4421 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4422 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4423 kvm_enable_tdp();
4424 } else
4425 kvm_disable_tdp();
1439442c 4426
c7addb90
AK		 4427 if (bypass_guest_pf)
4428 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4429
fdef3ad1
HQ		 4430 return 0;
4431
5897297b
AK		 4432out3:
4433 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4434out2:
5897297b 4435 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4436out1:
3e7c73e9 4437 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4438out:
3e7c73e9 4439 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4440 return r;
6aa8b732
AK		 4441}
4442
4443static void __exit vmx_exit(void)
4444{
5897297b
AK		 4445 free_page((unsigned long)vmx_msr_bitmap_legacy);
4446 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4447 free_page((unsigned long)vmx_io_bitmap_b);
4448 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4449
cb498ea2 4450 kvm_exit();
6aa8b732
AK		 4451}
4452
4453module_init(vmx_init)
4454module_exit(vmx_exit)
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