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KVM: MMU: Fix regression with ept memory types merged into non-ept page tables
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
221d059d 8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
cdc0e244
AK		 72#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74#define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 77 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 78#define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 80#define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
82 | X86_CR4_OSXMMEXCPT)
83
cdc0e244
AK		 84#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
86
78ac8b47
AK		 87#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
88
4b8d54f9
ZE		 89/*
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
99 */
100#define KVM_VMX_DEFAULT_PLE_GAP 41
101#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103module_param(ple_gap, int, S_IRUGO);
104
105static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106module_param(ple_window, int, S_IRUGO);
107
61d2ef2c
AK		 108#define NR_AUTOLOAD_MSRS 1
109
a2fa3e9f
GH		 110struct vmcs {
111 u32 revision_id;
112 u32 abort;
113 char data[0];
114};
115
26bb0981
AK		 116struct shared_msr_entry {
117 unsigned index;
118 u64 data;
d5696725 119 u64 mask;
26bb0981
AK		 120};
121
a2fa3e9f 122struct vcpu_vmx {
fb3f0f51 123 struct kvm_vcpu vcpu;
543e4243 124 struct list_head local_vcpus_link;
313dbd49 125 unsigned long host_rsp;
a2fa3e9f 126 int launched;
29bd8a78 127 u8 fail;
1155f76a 128 u32 idt_vectoring_info;
26bb0981 129 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 130 int nmsrs;
131 int save_nmsrs;
a2fa3e9f 132#ifdef CONFIG_X86_64
44ea2b17
AK		 133 u64 msr_host_kernel_gs_base;
134 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 135#endif
136 struct vmcs *vmcs;
61d2ef2c
AK		 137 struct msr_autoload {
138 unsigned nr;
139 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
140 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
141 } msr_autoload;
a2fa3e9f
GH		 142 struct {
143 int loaded;
144 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 145 int gs_ldt_reload_needed;
146 int fs_reload_needed;
d77c26fc 147 } host_state;
9c8cba37 148 struct {
7ffd92c5 149 int vm86_active;
78ac8b47 150 ulong save_rflags;
7ffd92c5
AK		 151 struct kvm_save_segment {
152 u16 selector;
153 unsigned long base;
154 u32 limit;
155 u32 ar;
156 } tr, es, ds, fs, gs;
9c8cba37
AK		 157 struct {
158 bool pending;
159 u8 vector;
160 unsigned rip;
161 } irq;
162 } rmode;
2384d2b3 163 int vpid;
04fa4d32 164 bool emulation_required;
3b86cd99
JK		 165
166 /* Support for vnmi-less CPUs */
167 int soft_vnmi_blocked;
168 ktime_t entry_time;
169 s64 vnmi_blocked_time;
a0861c02 170 u32 exit_reason;
4e47c7a6
SY		 171
172 bool rdtscp_enabled;
a2fa3e9f
GH		 173};
174
175static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
176{
fb3f0f51 177 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 178}
179
b7ebfb05 180static int init_rmode(struct kvm *kvm);
4e1096d2 181static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 182static void kvm_cpu_vmxon(u64 addr);
183static void kvm_cpu_vmxoff(void);
75880a01 184
6aa8b732
AK		 185static DEFINE_PER_CPU(struct vmcs *, vmxarea);
186static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 187static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
3444d7da 188static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 189
3e7c73e9
AK		 190static unsigned long *vmx_io_bitmap_a;
191static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 192static unsigned long *vmx_msr_bitmap_legacy;
193static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 194
2384d2b3
SY		 195static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
196static DEFINE_SPINLOCK(vmx_vpid_lock);
197
1c3d14fe 198static struct vmcs_config {
6aa8b732
AK		 199 int size;
200 int order;
201 u32 revision_id;
1c3d14fe
YS		 202 u32 pin_based_exec_ctrl;
203 u32 cpu_based_exec_ctrl;
f78e0e2e 204 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 205 u32 vmexit_ctrl;
206 u32 vmentry_ctrl;
207} vmcs_config;
6aa8b732 208
efff9e53 209static struct vmx_capability {
d56f546d
SY		 210 u32 ept;
211 u32 vpid;
212} vmx_capability;
213
6aa8b732
AK		 214#define VMX_SEGMENT_FIELD(seg) \
215 [VCPU_SREG_##seg] = { \
216 .selector = GUEST_##seg##_SELECTOR, \
217 .base = GUEST_##seg##_BASE, \
218 .limit = GUEST_##seg##_LIMIT, \
219 .ar_bytes = GUEST_##seg##_AR_BYTES, \
220 }
221
222static struct kvm_vmx_segment_field {
223 unsigned selector;
224 unsigned base;
225 unsigned limit;
226 unsigned ar_bytes;
227} kvm_vmx_segment_fields[] = {
228 VMX_SEGMENT_FIELD(CS),
229 VMX_SEGMENT_FIELD(DS),
230 VMX_SEGMENT_FIELD(ES),
231 VMX_SEGMENT_FIELD(FS),
232 VMX_SEGMENT_FIELD(GS),
233 VMX_SEGMENT_FIELD(SS),
234 VMX_SEGMENT_FIELD(TR),
235 VMX_SEGMENT_FIELD(LDTR),
236};
237
26bb0981
AK		 238static u64 host_efer;
239
6de4f3ad
AK		 240static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
241
4d56c8a7 242/*
8c06585d 243 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 244 * away by decrementing the array size.
245 */
6aa8b732 246static const u32 vmx_msr_index[] = {
05b3e0c2 247#ifdef CONFIG_X86_64
44ea2b17 248 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 249#endif
8c06585d 250 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 251};
9d8f549d 252#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 253
31299944 254static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 255{
256 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
257 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 258 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 259}
260
31299944 261static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 262{
263 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
264 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 265 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 266}
267
31299944 268static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 269{
270 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
271 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 272 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 273}
274
31299944 275static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 276{
277 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
278 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
279}
280
31299944 281static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 282{
283 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
284 INTR_INFO_VALID_MASK)) ==
285 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
286}
287
31299944 288static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 289{
04547156 290 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 291}
292
31299944 293static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 294{
04547156 295 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 296}
297
31299944 298static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 299{
04547156 300 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 301}
302
31299944 303static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 304{
04547156
SY		 305 return vmcs_config.cpu_based_exec_ctrl &
306 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 307}
308
774ead3a 309static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 310{
04547156
SY		 311 return vmcs_config.cpu_based_2nd_exec_ctrl &
312 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
313}
314
315static inline bool cpu_has_vmx_flexpriority(void)
316{
317 return cpu_has_vmx_tpr_shadow() &&
318 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 319}
320
e799794e
MT		 321static inline bool cpu_has_vmx_ept_execute_only(void)
322{
31299944 323 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 324}
325
326static inline bool cpu_has_vmx_eptp_uncacheable(void)
327{
31299944 328 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 329}
330
331static inline bool cpu_has_vmx_eptp_writeback(void)
332{
31299944 333 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 334}
335
336static inline bool cpu_has_vmx_ept_2m_page(void)
337{
31299944 338 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 339}
340
878403b7
SY		 341static inline bool cpu_has_vmx_ept_1g_page(void)
342{
31299944 343 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 344}
345
4bc9b982
SY		 346static inline bool cpu_has_vmx_ept_4levels(void)
347{
348 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
349}
350
31299944 351static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 352{
31299944 353 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 354}
355
31299944 356static inline bool cpu_has_vmx_invept_context(void)
d56f546d 357{
31299944 358 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 359}
360
31299944 361static inline bool cpu_has_vmx_invept_global(void)
d56f546d 362{
31299944 363 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 364}
365
518c8aee
GJ		 366static inline bool cpu_has_vmx_invvpid_single(void)
367{
368 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
369}
370
b9d762fa
GJ		 371static inline bool cpu_has_vmx_invvpid_global(void)
372{
373 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
374}
375
31299944 376static inline bool cpu_has_vmx_ept(void)
d56f546d 377{
04547156
SY		 378 return vmcs_config.cpu_based_2nd_exec_ctrl &
379 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 380}
381
31299944 382static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 383{
384 return vmcs_config.cpu_based_2nd_exec_ctrl &
385 SECONDARY_EXEC_UNRESTRICTED_GUEST;
386}
387
31299944 388static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 389{
390 return vmcs_config.cpu_based_2nd_exec_ctrl &
391 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
392}
393
31299944 394static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 395{
6d3e435e 396 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 397}
398
31299944 399static inline bool cpu_has_vmx_vpid(void)
2384d2b3 400{
04547156
SY		 401 return vmcs_config.cpu_based_2nd_exec_ctrl &
402 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 403}
404
31299944 405static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 406{
407 return vmcs_config.cpu_based_2nd_exec_ctrl &
408 SECONDARY_EXEC_RDTSCP;
409}
410
31299944 411static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 412{
413 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
414}
415
f5f48ee1
SY		 416static inline bool cpu_has_vmx_wbinvd_exit(void)
417{
418 return vmcs_config.cpu_based_2nd_exec_ctrl &
419 SECONDARY_EXEC_WBINVD_EXITING;
420}
421
04547156
SY		 422static inline bool report_flexpriority(void)
423{
424 return flexpriority_enabled;
425}
426
8b9cf98c 427static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 428{
429 int i;
430
a2fa3e9f 431 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 432 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 433 return i;
434 return -1;
435}
436
2384d2b3
SY		 437static inline void __invvpid(int ext, u16 vpid, gva_t gva)
438{
439 struct {
440 u64 vpid : 16;
441 u64 rsvd : 48;
442 u64 gva;
443 } operand = { vpid, 0, gva };
444
4ecac3fd 445 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 446 /* CF==1 or ZF==1 --> rc = -1 */
447 "; ja 1f ; ud2 ; 1:"
448 : : "a"(&operand), "c"(ext) : "cc", "memory");
449}
450
1439442c
SY		 451static inline void __invept(int ext, u64 eptp, gpa_t gpa)
452{
453 struct {
454 u64 eptp, gpa;
455 } operand = {eptp, gpa};
456
4ecac3fd 457 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 458 /* CF==1 or ZF==1 --> rc = -1 */
459 "; ja 1f ; ud2 ; 1:\n"
460 : : "a" (&operand), "c" (ext) : "cc", "memory");
461}
462
26bb0981 463static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 464{
465 int i;
466
8b9cf98c 467 i = __find_msr_index(vmx, msr);
a75beee6 468 if (i >= 0)
a2fa3e9f 469 return &vmx->guest_msrs[i];
8b6d44c7 470 return NULL;
7725f0ba
AK		 471}
472
6aa8b732
AK		 473static void vmcs_clear(struct vmcs *vmcs)
474{
475 u64 phys_addr = __pa(vmcs);
476 u8 error;
477
4ecac3fd 478 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 479 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
480 : "cc", "memory");
481 if (error)
482 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
483 vmcs, phys_addr);
484}
485
7725b894
DX		 486static void vmcs_load(struct vmcs *vmcs)
487{
488 u64 phys_addr = __pa(vmcs);
489 u8 error;
490
491 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
492 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
493 : "cc", "memory");
494 if (error)
495 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
496 vmcs, phys_addr);
497}
498
6aa8b732
AK		 499static void __vcpu_clear(void *arg)
500{
8b9cf98c 501 struct vcpu_vmx *vmx = arg;
d3b2c338 502 int cpu = raw_smp_processor_id();
6aa8b732 503
8b9cf98c 504 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 505 vmcs_clear(vmx->vmcs);
506 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 507 per_cpu(current_vmcs, cpu) = NULL;
543e4243
AK		 508 list_del(&vmx->local_vcpus_link);
509 vmx->vcpu.cpu = -1;
510 vmx->launched = 0;
6aa8b732
AK		 511}
512
8b9cf98c 513static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 514{
eae5ecb5
AK		 515 if (vmx->vcpu.cpu == -1)
516 return;
8691e5a8 517 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 518}
519
1760dd49 520static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 521{
522 if (vmx->vpid == 0)
523 return;
524
518c8aee
GJ		 525 if (cpu_has_vmx_invvpid_single())
526 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 527}
528
b9d762fa
GJ		 529static inline void vpid_sync_vcpu_global(void)
530{
531 if (cpu_has_vmx_invvpid_global())
532 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
533}
534
535static inline void vpid_sync_context(struct vcpu_vmx *vmx)
536{
537 if (cpu_has_vmx_invvpid_single())
1760dd49 538 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 539 else
540 vpid_sync_vcpu_global();
541}
542
1439442c
SY		 543static inline void ept_sync_global(void)
544{
545 if (cpu_has_vmx_invept_global())
546 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
547}
548
549static inline void ept_sync_context(u64 eptp)
550{
089d034e 551 if (enable_ept) {
1439442c
SY		 552 if (cpu_has_vmx_invept_context())
553 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
554 else
555 ept_sync_global();
556 }
557}
558
559static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
560{
089d034e 561 if (enable_ept) {
1439442c
SY		 562 if (cpu_has_vmx_invept_individual_addr())
563 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
564 eptp, gpa);
565 else
566 ept_sync_context(eptp);
567 }
568}
569
6aa8b732
AK		 570static unsigned long vmcs_readl(unsigned long field)
571{
572 unsigned long value;
573
4ecac3fd 574 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 575 : "=a"(value) : "d"(field) : "cc");
576 return value;
577}
578
579static u16 vmcs_read16(unsigned long field)
580{
581 return vmcs_readl(field);
582}
583
584static u32 vmcs_read32(unsigned long field)
585{
586 return vmcs_readl(field);
587}
588
589static u64 vmcs_read64(unsigned long field)
590{
05b3e0c2 591#ifdef CONFIG_X86_64
6aa8b732
AK		 592 return vmcs_readl(field);
593#else
594 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
595#endif
596}
597
e52de1b8
AK		 598static noinline void vmwrite_error(unsigned long field, unsigned long value)
599{
600 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
601 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
602 dump_stack();
603}
604
6aa8b732
AK		 605static void vmcs_writel(unsigned long field, unsigned long value)
606{
607 u8 error;
608
4ecac3fd 609 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 610 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 611 if (unlikely(error))
612 vmwrite_error(field, value);
6aa8b732
AK		 613}
614
615static void vmcs_write16(unsigned long field, u16 value)
616{
617 vmcs_writel(field, value);
618}
619
620static void vmcs_write32(unsigned long field, u32 value)
621{
622 vmcs_writel(field, value);
623}
624
625static void vmcs_write64(unsigned long field, u64 value)
626{
6aa8b732 627 vmcs_writel(field, value);
7682f2d0 628#ifndef CONFIG_X86_64
6aa8b732
AK		 629 asm volatile ("");
630 vmcs_writel(field+1, value >> 32);
631#endif
632}
633
2ab455cc
AL		 634static void vmcs_clear_bits(unsigned long field, u32 mask)
635{
636 vmcs_writel(field, vmcs_readl(field) & ~mask);
637}
638
639static void vmcs_set_bits(unsigned long field, u32 mask)
640{
641 vmcs_writel(field, vmcs_readl(field) | mask);
642}
643
abd3f2d6
AK		 644static void update_exception_bitmap(struct kvm_vcpu *vcpu)
645{
646 u32 eb;
647
fd7373cc
JK		 648 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
649 (1u << NM_VECTOR) | (1u << DB_VECTOR);
650 if ((vcpu->guest_debug &
651 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
652 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
653 eb |= 1u << BP_VECTOR;
7ffd92c5 654 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 655 eb = ~0;
089d034e 656 if (enable_ept)
1439442c 657 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 658 if (vcpu->fpu_active)
659 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 660 vmcs_write32(EXCEPTION_BITMAP, eb);
661}
662
61d2ef2c
AK		 663static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
664{
665 unsigned i;
666 struct msr_autoload *m = &vmx->msr_autoload;
667
668 for (i = 0; i < m->nr; ++i)
669 if (m->guest[i].index == msr)
670 break;
671
672 if (i == m->nr)
673 return;
674 --m->nr;
675 m->guest[i] = m->guest[m->nr];
676 m->host[i] = m->host[m->nr];
677 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
678 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
679}
680
681static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
682 u64 guest_val, u64 host_val)
683{
684 unsigned i;
685 struct msr_autoload *m = &vmx->msr_autoload;
686
687 for (i = 0; i < m->nr; ++i)
688 if (m->guest[i].index == msr)
689 break;
690
691 if (i == m->nr) {
692 ++m->nr;
693 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
694 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
695 }
696
697 m->guest[i].index = msr;
698 m->guest[i].value = guest_val;
699 m->host[i].index = msr;
700 m->host[i].value = host_val;
701}
702
33ed6329
AK		 703static void reload_tss(void)
704{
33ed6329
AK		 705 /*
706 * VT restores TR but not its size. Useless.
707 */
d359192f 708 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 709 struct desc_struct *descs;
33ed6329 710
d359192f 711 descs = (void *)gdt->address;
33ed6329
AK		 712 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
713 load_TR_desc();
33ed6329
AK		 714}
715
92c0d900 716static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 717{
3a34a881 718 u64 guest_efer;
51c6cf66
AK		 719 u64 ignore_bits;
720
f6801dff 721 guest_efer = vmx->vcpu.arch.efer;
3a34a881 722
51c6cf66
AK		 723 /*
724 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
725 * outside long mode
726 */
727 ignore_bits = EFER_NX | EFER_SCE;
728#ifdef CONFIG_X86_64
729 ignore_bits |= EFER_LMA | EFER_LME;
730 /* SCE is meaningful only in long mode on Intel */
731 if (guest_efer & EFER_LMA)
732 ignore_bits &= ~(u64)EFER_SCE;
733#endif
51c6cf66
AK		 734 guest_efer &= ~ignore_bits;
735 guest_efer |= host_efer & ignore_bits;
26bb0981 736 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 737 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 738
739 clear_atomic_switch_msr(vmx, MSR_EFER);
740 /* On ept, can't emulate nx, and must switch nx atomically */
741 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
742 guest_efer = vmx->vcpu.arch.efer;
743 if (!(guest_efer & EFER_LMA))
744 guest_efer &= ~EFER_LME;
745 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
746 return false;
747 }
748
26bb0981 749 return true;
51c6cf66
AK		 750}
751
2d49ec72
GN		 752static unsigned long segment_base(u16 selector)
753{
d359192f 754 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 755 struct desc_struct *d;
756 unsigned long table_base;
757 unsigned long v;
758
759 if (!(selector & ~3))
760 return 0;
761
d359192f 762 table_base = gdt->address;
2d49ec72
GN		 763
764 if (selector & 4) { /* from ldt */
765 u16 ldt_selector = kvm_read_ldt();
766
767 if (!(ldt_selector & ~3))
768 return 0;
769
770 table_base = segment_base(ldt_selector);
771 }
772 d = (struct desc_struct *)(table_base + (selector & ~7));
773 v = get_desc_base(d);
774#ifdef CONFIG_X86_64
775 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
776 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
777#endif
778 return v;
779}
780
781static inline unsigned long kvm_read_tr_base(void)
782{
783 u16 tr;
784 asm("str %0" : "=g"(tr));
785 return segment_base(tr);
786}
787
04d2cc77 788static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 789{
04d2cc77 790 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 791 int i;
04d2cc77 792
a2fa3e9f 793 if (vmx->host_state.loaded)
33ed6329
AK		 794 return;
795
a2fa3e9f 796 vmx->host_state.loaded = 1;
33ed6329
AK		 797 /*
798 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
799 * allow segment selectors with cpl > 0 or ti == 1.
800 */
d6e88aec 801 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 802 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 803 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 804 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 805 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 806 vmx->host_state.fs_reload_needed = 0;
807 } else {
33ed6329 808 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 809 vmx->host_state.fs_reload_needed = 1;
33ed6329 810 }
9581d442 811 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 812 if (!(vmx->host_state.gs_sel & 7))
813 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 814 else {
815 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 816 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 817 }
818
819#ifdef CONFIG_X86_64
820 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
821 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
822#else
a2fa3e9f
GH		 823 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
824 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 825#endif
707c0874
AK		 826
827#ifdef CONFIG_X86_64
44ea2b17
AK		 828 if (is_long_mode(&vmx->vcpu)) {
829 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
830 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
831 }
707c0874 832#endif
26bb0981
AK		 833 for (i = 0; i < vmx->save_nmsrs; ++i)
834 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 835 vmx->guest_msrs[i].data,
836 vmx->guest_msrs[i].mask);
33ed6329
AK		 837}
838
a9b21b62 839static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 840{
a2fa3e9f 841 if (!vmx->host_state.loaded)
33ed6329
AK		 842 return;
843
e1beb1d3 844 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 845 vmx->host_state.loaded = 0;
152d3f2f 846 if (vmx->host_state.fs_reload_needed)
9581d442 847 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 848 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 849 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 850#ifdef CONFIG_X86_64
9581d442
AK		 851 load_gs_index(vmx->host_state.gs_sel);
852 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
853#else
854 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 855#endif
33ed6329 856 }
152d3f2f 857 reload_tss();
44ea2b17
AK		 858#ifdef CONFIG_X86_64
859 if (is_long_mode(&vmx->vcpu)) {
860 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
861 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
862 }
863#endif
1c11e713
AK		 864 if (current_thread_info()->status & TS_USEDFPU)
865 clts();
3444d7da 866 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 867}
868
a9b21b62
AK		 869static void vmx_load_host_state(struct vcpu_vmx *vmx)
870{
871 preempt_disable();
872 __vmx_load_host_state(vmx);
873 preempt_enable();
874}
875
6aa8b732
AK		 876/*
877 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
878 * vcpu mutex is already taken.
879 */
15ad7146 880static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 881{
a2fa3e9f 882 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 883 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 884
4610c9cc
DX		 885 if (!vmm_exclusive)
886 kvm_cpu_vmxon(phys_addr);
887 else if (vcpu->cpu != cpu)
8b9cf98c 888 vcpu_clear(vmx);
6aa8b732 889
a2fa3e9f 890 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 891 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 892 vmcs_load(vmx->vmcs);
6aa8b732
AK		 893 }
894
895 if (vcpu->cpu != cpu) {
d359192f 896 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 897 unsigned long sysenter_esp;
898
a8eeb04a 899 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be
DX		 900 local_irq_disable();
901 list_add(&vmx->local_vcpus_link,
902 &per_cpu(vcpus_on_cpu, cpu));
903 local_irq_enable();
904
6aa8b732
AK		 905 /*
906 * Linux uses per-cpu TSS and GDT, so set these when switching
907 * processors.
908 */
d6e88aec 909 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 910 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 911
912 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
913 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
914 }
6aa8b732
AK		 915}
916
917static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
918{
a9b21b62 919 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 920 if (!vmm_exclusive) {
b923e62e 921 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 922 kvm_cpu_vmxoff();
923 }
6aa8b732
AK		 924}
925
5fd86fcf
AK		 926static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
927{
81231c69
AK		 928 ulong cr0;
929
5fd86fcf
AK		 930 if (vcpu->fpu_active)
931 return;
932 vcpu->fpu_active = 1;
81231c69
AK		 933 cr0 = vmcs_readl(GUEST_CR0);
934 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
935 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
936 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 937 update_exception_bitmap(vcpu);
edcafe3c
AK		 938 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
939 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 940}
941
edcafe3c
AK		 942static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
943
5fd86fcf
AK		 944static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
945{
edcafe3c 946 vmx_decache_cr0_guest_bits(vcpu);
81231c69 947 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 948 update_exception_bitmap(vcpu);
edcafe3c
AK		 949 vcpu->arch.cr0_guest_owned_bits = 0;
950 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
951 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 952}
953
6aa8b732
AK		 954static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
955{
78ac8b47 956 unsigned long rflags, save_rflags;
345dcaa8
AK		 957
958 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 959 if (to_vmx(vcpu)->rmode.vm86_active) {
960 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
961 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
962 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
963 }
345dcaa8 964 return rflags;
6aa8b732
AK		 965}
966
967static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
968{
78ac8b47
AK		 969 if (to_vmx(vcpu)->rmode.vm86_active) {
970 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 971 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 972 }
6aa8b732
AK		 973 vmcs_writel(GUEST_RFLAGS, rflags);
974}
975
2809f5d2
GC		 976static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
977{
978 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
979 int ret = 0;
980
981 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 982 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 983 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 984 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 985
986 return ret & mask;
987}
988
989static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
990{
991 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
992 u32 interruptibility = interruptibility_old;
993
994 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
995
48005f64 996 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 997 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 998 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 999 interruptibility |= GUEST_INTR_STATE_STI;
1000
1001 if ((interruptibility != interruptibility_old))
1002 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1003}
1004
6aa8b732
AK		 1005static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1006{
1007 unsigned long rip;
6aa8b732 1008
5fdbf976 1009 rip = kvm_rip_read(vcpu);
6aa8b732 1010 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1011 kvm_rip_write(vcpu, rip);
6aa8b732 1012
2809f5d2
GC		 1013 /* skipping an emulated instruction also counts */
1014 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1015}
1016
298101da 1017static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1018 bool has_error_code, u32 error_code,
1019 bool reinject)
298101da 1020{
77ab6db0 1021 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1022 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1023
8ab2d2e2 1024 if (has_error_code) {
77ab6db0 1025 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1026 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1027 }
77ab6db0 1028
7ffd92c5 1029 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 1030 vmx->rmode.irq.pending = true;
1031 vmx->rmode.irq.vector = nr;
1032 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 1033 if (kvm_exception_is_soft(nr))
1034 vmx->rmode.irq.rip +=
1035 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 1036 intr_info |= INTR_TYPE_SOFT_INTR;
1037 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 1038 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1039 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1040 return;
1041 }
1042
66fd3f7f
GN		 1043 if (kvm_exception_is_soft(nr)) {
1044 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1045 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1046 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1047 } else
1048 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1049
1050 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1051}
1052
4e47c7a6
SY		 1053static bool vmx_rdtscp_supported(void)
1054{
1055 return cpu_has_vmx_rdtscp();
1056}
1057
a75beee6
ED		 1058/*
1059 * Swap MSR entry in host/guest MSR entry array.
1060 */
8b9cf98c 1061static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1062{
26bb0981 1063 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1064
1065 tmp = vmx->guest_msrs[to];
1066 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1067 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1068}
1069
e38aea3e
AK		 1070/*
1071 * Set up the vmcs to automatically save and restore system
1072 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1073 * mode, as fiddling with msrs is very expensive.
1074 */
8b9cf98c 1075static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1076{
26bb0981 1077 int save_nmsrs, index;
5897297b 1078 unsigned long *msr_bitmap;
e38aea3e 1079
33f9c505 1080 vmx_load_host_state(vmx);
a75beee6
ED		 1081 save_nmsrs = 0;
1082#ifdef CONFIG_X86_64
8b9cf98c 1083 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1084 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1085 if (index >= 0)
8b9cf98c
RR		 1086 move_msr_up(vmx, index, save_nmsrs++);
1087 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1088 if (index >= 0)
8b9cf98c
RR		 1089 move_msr_up(vmx, index, save_nmsrs++);
1090 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1091 if (index >= 0)
8b9cf98c 1092 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1093 index = __find_msr_index(vmx, MSR_TSC_AUX);
1094 if (index >= 0 && vmx->rdtscp_enabled)
1095 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1096 /*
8c06585d 1097 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1098 * if efer.sce is enabled.
1099 */
8c06585d 1100 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1101 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1102 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1103 }
1104#endif
92c0d900
AK		 1105 index = __find_msr_index(vmx, MSR_EFER);
1106 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1107 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1108
26bb0981 1109 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1110
1111 if (cpu_has_vmx_msr_bitmap()) {
1112 if (is_long_mode(&vmx->vcpu))
1113 msr_bitmap = vmx_msr_bitmap_longmode;
1114 else
1115 msr_bitmap = vmx_msr_bitmap_legacy;
1116
1117 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1118 }
e38aea3e
AK		 1119}
1120
6aa8b732
AK		 1121/*
1122 * reads and returns guest's timestamp counter "register"
1123 * guest_tsc = host_tsc + tsc_offset -- 21.3
1124 */
1125static u64 guest_read_tsc(void)
1126{
1127 u64 host_tsc, tsc_offset;
1128
1129 rdtscll(host_tsc);
1130 tsc_offset = vmcs_read64(TSC_OFFSET);
1131 return host_tsc + tsc_offset;
1132}
1133
1134/*
99e3e30a 1135 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1136 */
99e3e30a 1137static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1138{
f4e1b3c8 1139 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1140}
1141
e48672fa
ZA		 1142static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1143{
1144 u64 offset = vmcs_read64(TSC_OFFSET);
1145 vmcs_write64(TSC_OFFSET, offset + adjustment);
1146}
1147
6aa8b732
AK		 1148/*
1149 * Reads an msr value (of 'msr_index') into 'pdata'.
1150 * Returns 0 on success, non-0 otherwise.
1151 * Assumes vcpu_load() was already called.
1152 */
1153static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1154{
1155 u64 data;
26bb0981 1156 struct shared_msr_entry *msr;
6aa8b732
AK		 1157
1158 if (!pdata) {
1159 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1160 return -EINVAL;
1161 }
1162
1163 switch (msr_index) {
05b3e0c2 1164#ifdef CONFIG_X86_64
6aa8b732
AK		 1165 case MSR_FS_BASE:
1166 data = vmcs_readl(GUEST_FS_BASE);
1167 break;
1168 case MSR_GS_BASE:
1169 data = vmcs_readl(GUEST_GS_BASE);
1170 break;
44ea2b17
AK		 1171 case MSR_KERNEL_GS_BASE:
1172 vmx_load_host_state(to_vmx(vcpu));
1173 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1174 break;
26bb0981 1175#endif
6aa8b732 1176 case MSR_EFER:
3bab1f5d 1177 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1178 case MSR_IA32_TSC:
6aa8b732
AK		 1179 data = guest_read_tsc();
1180 break;
1181 case MSR_IA32_SYSENTER_CS:
1182 data = vmcs_read32(GUEST_SYSENTER_CS);
1183 break;
1184 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1185 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1186 break;
1187 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1188 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1189 break;
4e47c7a6
SY		 1190 case MSR_TSC_AUX:
1191 if (!to_vmx(vcpu)->rdtscp_enabled)
1192 return 1;
1193 /* Otherwise falls through */
6aa8b732 1194 default:
26bb0981 1195 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1196 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1197 if (msr) {
542423b0 1198 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1199 data = msr->data;
1200 break;
6aa8b732 1201 }
3bab1f5d 1202 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1203 }
1204
1205 *pdata = data;
1206 return 0;
1207}
1208
1209/*
1210 * Writes msr value into into the appropriate "register".
1211 * Returns 0 on success, non-0 otherwise.
1212 * Assumes vcpu_load() was already called.
1213 */
1214static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1215{
a2fa3e9f 1216 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1217 struct shared_msr_entry *msr;
2cc51560
ED		 1218 int ret = 0;
1219
6aa8b732 1220 switch (msr_index) {
3bab1f5d 1221 case MSR_EFER:
a9b21b62 1222 vmx_load_host_state(vmx);
2cc51560 1223 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1224 break;
16175a79 1225#ifdef CONFIG_X86_64
6aa8b732
AK		 1226 case MSR_FS_BASE:
1227 vmcs_writel(GUEST_FS_BASE, data);
1228 break;
1229 case MSR_GS_BASE:
1230 vmcs_writel(GUEST_GS_BASE, data);
1231 break;
44ea2b17
AK		 1232 case MSR_KERNEL_GS_BASE:
1233 vmx_load_host_state(vmx);
1234 vmx->msr_guest_kernel_gs_base = data;
1235 break;
6aa8b732
AK		 1236#endif
1237 case MSR_IA32_SYSENTER_CS:
1238 vmcs_write32(GUEST_SYSENTER_CS, data);
1239 break;
1240 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1241 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1242 break;
1243 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1244 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1245 break;
af24a4e4 1246 case MSR_IA32_TSC:
99e3e30a 1247 kvm_write_tsc(vcpu, data);
6aa8b732 1248 break;
468d472f
SY		 1249 case MSR_IA32_CR_PAT:
1250 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1251 vmcs_write64(GUEST_IA32_PAT, data);
1252 vcpu->arch.pat = data;
1253 break;
1254 }
4e47c7a6
SY		 1255 ret = kvm_set_msr_common(vcpu, msr_index, data);
1256 break;
1257 case MSR_TSC_AUX:
1258 if (!vmx->rdtscp_enabled)
1259 return 1;
1260 /* Check reserved bit, higher 32 bits should be zero */
1261 if ((data >> 32) != 0)
1262 return 1;
1263 /* Otherwise falls through */
6aa8b732 1264 default:
8b9cf98c 1265 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1266 if (msr) {
542423b0 1267 vmx_load_host_state(vmx);
3bab1f5d
AK		 1268 msr->data = data;
1269 break;
6aa8b732 1270 }
2cc51560 1271 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1272 }
1273
2cc51560 1274 return ret;
6aa8b732
AK		 1275}
1276
5fdbf976 1277static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1278{
5fdbf976
MT		 1279 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1280 switch (reg) {
1281 case VCPU_REGS_RSP:
1282 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1283 break;
1284 case VCPU_REGS_RIP:
1285 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1286 break;
6de4f3ad
AK		 1287 case VCPU_EXREG_PDPTR:
1288 if (enable_ept)
1289 ept_save_pdptrs(vcpu);
1290 break;
5fdbf976
MT		 1291 default:
1292 break;
1293 }
6aa8b732
AK		 1294}
1295
355be0b9 1296static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1297{
ae675ef0
JK		 1298 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1299 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1300 else
1301 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1302
abd3f2d6 1303 update_exception_bitmap(vcpu);
6aa8b732
AK		 1304}
1305
1306static __init int cpu_has_kvm_support(void)
1307{
6210e37b 1308 return cpu_has_vmx();
6aa8b732
AK		 1309}
1310
1311static __init int vmx_disabled_by_bios(void)
1312{
1313 u64 msr;
1314
1315 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1316 if (msr & FEATURE_CONTROL_LOCKED) {
1317 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1318 && tboot_enabled())
1319 return 1;
1320 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1321 && !tboot_enabled())
1322 return 1;
1323 }
1324
1325 return 0;
62b3ffb8 1326 /* locked but not enabled */
6aa8b732
AK		 1327}
1328
7725b894
DX		 1329static void kvm_cpu_vmxon(u64 addr)
1330{
1331 asm volatile (ASM_VMX_VMXON_RAX
1332 : : "a"(&addr), "m"(addr)
1333 : "memory", "cc");
1334}
1335
10474ae8 1336static int hardware_enable(void *garbage)
6aa8b732
AK		 1337{
1338 int cpu = raw_smp_processor_id();
1339 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1340 u64 old, test_bits;
6aa8b732 1341
10474ae8
AG		 1342 if (read_cr4() & X86_CR4_VMXE)
1343 return -EBUSY;
1344
543e4243 1345 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1346 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1347
1348 test_bits = FEATURE_CONTROL_LOCKED;
1349 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1350 if (tboot_enabled())
1351 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1352
1353 if ((old & test_bits) != test_bits) {
6aa8b732 1354 /* enable and lock */
cafd6659
SW		 1355 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1356 }
66aee91a 1357 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1358
4610c9cc
DX		 1359 if (vmm_exclusive) {
1360 kvm_cpu_vmxon(phys_addr);
1361 ept_sync_global();
1362 }
10474ae8 1363
3444d7da
AK		 1364 store_gdt(&__get_cpu_var(host_gdt));
1365
10474ae8 1366 return 0;
6aa8b732
AK		 1367}
1368
543e4243
AK		 1369static void vmclear_local_vcpus(void)
1370{
1371 int cpu = raw_smp_processor_id();
1372 struct vcpu_vmx *vmx, *n;
1373
1374 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1375 local_vcpus_link)
1376 __vcpu_clear(vmx);
1377}
1378
710ff4a8
EH		 1379
1380/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1381 * tricks.
1382 */
1383static void kvm_cpu_vmxoff(void)
6aa8b732 1384{
4ecac3fd 1385 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1386}
1387
710ff4a8
EH		 1388static void hardware_disable(void *garbage)
1389{
4610c9cc
DX		 1390 if (vmm_exclusive) {
1391 vmclear_local_vcpus();
1392 kvm_cpu_vmxoff();
1393 }
7725b894 1394 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1395}
1396
1c3d14fe 1397static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1398 u32 msr, u32 *result)
1c3d14fe
YS		 1399{
1400 u32 vmx_msr_low, vmx_msr_high;
1401 u32 ctl = ctl_min | ctl_opt;
1402
1403 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1404
1405 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1406 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1407
1408 /* Ensure minimum (required) set of control bits are supported. */
1409 if (ctl_min & ~ctl)
002c7f7c 1410 return -EIO;
1c3d14fe
YS		 1411
1412 *result = ctl;
1413 return 0;
1414}
1415
002c7f7c 1416static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1417{
1418 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1419 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1420 u32 _pin_based_exec_control = 0;
1421 u32 _cpu_based_exec_control = 0;
f78e0e2e 1422 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1423 u32 _vmexit_control = 0;
1424 u32 _vmentry_control = 0;
1425
1426 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1427 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1428 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1429 &_pin_based_exec_control) < 0)
002c7f7c 1430 return -EIO;
1c3d14fe
YS		 1431
1432 min = CPU_BASED_HLT_EXITING |
1433#ifdef CONFIG_X86_64
1434 CPU_BASED_CR8_LOAD_EXITING |
1435 CPU_BASED_CR8_STORE_EXITING |
1436#endif
d56f546d
SY		 1437 CPU_BASED_CR3_LOAD_EXITING |
1438 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1439 CPU_BASED_USE_IO_BITMAPS |
1440 CPU_BASED_MOV_DR_EXITING |
a7052897 1441 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1442 CPU_BASED_MWAIT_EXITING |
1443 CPU_BASED_MONITOR_EXITING |
a7052897 1444 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1445 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1446 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1447 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1448 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1449 &_cpu_based_exec_control) < 0)
002c7f7c 1450 return -EIO;
6e5d865c
YS		 1451#ifdef CONFIG_X86_64
1452 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1453 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1454 ~CPU_BASED_CR8_STORE_EXITING;
1455#endif
f78e0e2e 1456 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1457 min2 = 0;
1458 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1459 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1460 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1461 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1462 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1463 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1464 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1465 if (adjust_vmx_controls(min2, opt2,
1466 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1467 &_cpu_based_2nd_exec_control) < 0)
1468 return -EIO;
1469 }
1470#ifndef CONFIG_X86_64
1471 if (!(_cpu_based_2nd_exec_control &
1472 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1473 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1474#endif
d56f546d 1475 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1476 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1477 enabled */
5fff7d27
GN		 1478 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1479 CPU_BASED_CR3_STORE_EXITING |
1480 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1481 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1482 vmx_capability.ept, vmx_capability.vpid);
1483 }
1c3d14fe
YS		 1484
1485 min = 0;
1486#ifdef CONFIG_X86_64
1487 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1488#endif
468d472f 1489 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1490 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1491 &_vmexit_control) < 0)
002c7f7c 1492 return -EIO;
1c3d14fe 1493
468d472f
SY		 1494 min = 0;
1495 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1496 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1497 &_vmentry_control) < 0)
002c7f7c 1498 return -EIO;
6aa8b732 1499
c68876fd 1500 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1501
1502 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1503 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1504 return -EIO;
1c3d14fe
YS		 1505
1506#ifdef CONFIG_X86_64
1507 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1508 if (vmx_msr_high & (1u<<16))
002c7f7c 1509 return -EIO;
1c3d14fe
YS		 1510#endif
1511
1512 /* Require Write-Back (WB) memory type for VMCS accesses. */
1513 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1514 return -EIO;
1c3d14fe 1515
002c7f7c
YS		 1516 vmcs_conf->size = vmx_msr_high & 0x1fff;
1517 vmcs_conf->order = get_order(vmcs_config.size);
1518 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1519
002c7f7c
YS		 1520 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1521 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1522 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1523 vmcs_conf->vmexit_ctrl = _vmexit_control;
1524 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1525
1526 return 0;
c68876fd 1527}
6aa8b732
AK		 1528
1529static struct vmcs *alloc_vmcs_cpu(int cpu)
1530{
1531 int node = cpu_to_node(cpu);
1532 struct page *pages;
1533 struct vmcs *vmcs;
1534
6484eb3e 1535 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1536 if (!pages)
1537 return NULL;
1538 vmcs = page_address(pages);
1c3d14fe
YS		 1539 memset(vmcs, 0, vmcs_config.size);
1540 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1541 return vmcs;
1542}
1543
1544static struct vmcs *alloc_vmcs(void)
1545{
d3b2c338 1546 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1547}
1548
1549static void free_vmcs(struct vmcs *vmcs)
1550{
1c3d14fe 1551 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1552}
1553
39959588 1554static void free_kvm_area(void)
6aa8b732
AK		 1555{
1556 int cpu;
1557
3230bb47 1558 for_each_possible_cpu(cpu) {
6aa8b732 1559 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1560 per_cpu(vmxarea, cpu) = NULL;
1561 }
6aa8b732
AK		 1562}
1563
6aa8b732
AK		 1564static __init int alloc_kvm_area(void)
1565{
1566 int cpu;
1567
3230bb47 1568 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1569 struct vmcs *vmcs;
1570
1571 vmcs = alloc_vmcs_cpu(cpu);
1572 if (!vmcs) {
1573 free_kvm_area();
1574 return -ENOMEM;
1575 }
1576
1577 per_cpu(vmxarea, cpu) = vmcs;
1578 }
1579 return 0;
1580}
1581
1582static __init int hardware_setup(void)
1583{
002c7f7c
YS		 1584 if (setup_vmcs_config(&vmcs_config) < 0)
1585 return -EIO;
50a37eb4
JR		 1586
1587 if (boot_cpu_has(X86_FEATURE_NX))
1588 kvm_enable_efer_bits(EFER_NX);
1589
93ba03c2
SY		 1590 if (!cpu_has_vmx_vpid())
1591 enable_vpid = 0;
1592
4bc9b982
SY		 1593 if (!cpu_has_vmx_ept() ||
1594 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1595 enable_ept = 0;
3a624e29
NK		 1596 enable_unrestricted_guest = 0;
1597 }
1598
1599 if (!cpu_has_vmx_unrestricted_guest())
1600 enable_unrestricted_guest = 0;
93ba03c2
SY		 1601
1602 if (!cpu_has_vmx_flexpriority())
1603 flexpriority_enabled = 0;
1604
95ba8273
GN		 1605 if (!cpu_has_vmx_tpr_shadow())
1606 kvm_x86_ops->update_cr8_intercept = NULL;
1607
54dee993
MT		 1608 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1609 kvm_disable_largepages();
1610
4b8d54f9
ZE		 1611 if (!cpu_has_vmx_ple())
1612 ple_gap = 0;
1613
6aa8b732
AK		 1614 return alloc_kvm_area();
1615}
1616
1617static __exit void hardware_unsetup(void)
1618{
1619 free_kvm_area();
1620}
1621
6aa8b732
AK		 1622static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1623{
1624 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1625
6af11b9e 1626 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1627 vmcs_write16(sf->selector, save->selector);
1628 vmcs_writel(sf->base, save->base);
1629 vmcs_write32(sf->limit, save->limit);
1630 vmcs_write32(sf->ar_bytes, save->ar);
1631 } else {
1632 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1633 << AR_DPL_SHIFT;
1634 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1635 }
1636}
1637
1638static void enter_pmode(struct kvm_vcpu *vcpu)
1639{
1640 unsigned long flags;
a89a8fb9 1641 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1642
a89a8fb9 1643 vmx->emulation_required = 1;
7ffd92c5 1644 vmx->rmode.vm86_active = 0;
6aa8b732 1645
7ffd92c5
AK		 1646 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1647 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1648 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1649
1650 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1651 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1652 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1653 vmcs_writel(GUEST_RFLAGS, flags);
1654
66aee91a
RR		 1655 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1656 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1657
1658 update_exception_bitmap(vcpu);
1659
a89a8fb9
MG		 1660 if (emulate_invalid_guest_state)
1661 return;
1662
7ffd92c5
AK		 1663 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1664 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1665 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1666 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1667
1668 vmcs_write16(GUEST_SS_SELECTOR, 0);
1669 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1670
1671 vmcs_write16(GUEST_CS_SELECTOR,
1672 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1673 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1674}
1675
d77c26fc 1676static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1677{
bfc6d222 1678 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1679 struct kvm_memslots *slots;
1680 gfn_t base_gfn;
1681
90d83dc3 1682 slots = kvm_memslots(kvm);
f495c6e5 1683 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1684 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1685 return base_gfn << PAGE_SHIFT;
1686 }
bfc6d222 1687 return kvm->arch.tss_addr;
6aa8b732
AK		 1688}
1689
1690static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1691{
1692 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1693
1694 save->selector = vmcs_read16(sf->selector);
1695 save->base = vmcs_readl(sf->base);
1696 save->limit = vmcs_read32(sf->limit);
1697 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1698 vmcs_write16(sf->selector, save->base >> 4);
1699 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1700 vmcs_write32(sf->limit, 0xffff);
1701 vmcs_write32(sf->ar_bytes, 0xf3);
1702}
1703
1704static void enter_rmode(struct kvm_vcpu *vcpu)
1705{
1706 unsigned long flags;
a89a8fb9 1707 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1708
3a624e29
NK		 1709 if (enable_unrestricted_guest)
1710 return;
1711
a89a8fb9 1712 vmx->emulation_required = 1;
7ffd92c5 1713 vmx->rmode.vm86_active = 1;
6aa8b732 1714
7ffd92c5 1715 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1716 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1717
7ffd92c5 1718 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1719 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1720
7ffd92c5 1721 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1722 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1723
1724 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1725 vmx->rmode.save_rflags = flags;
6aa8b732 1726
053de044 1727 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1728
1729 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1730 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1731 update_exception_bitmap(vcpu);
1732
a89a8fb9
MG		 1733 if (emulate_invalid_guest_state)
1734 goto continue_rmode;
1735
6aa8b732
AK		 1736 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1737 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1738 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1739
1740 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1741 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1742 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1743 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1744 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1745
7ffd92c5
AK		 1746 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1747 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1748 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1749 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1750
a89a8fb9 1751continue_rmode:
8668a3c4 1752 kvm_mmu_reset_context(vcpu);
b7ebfb05 1753 init_rmode(vcpu->kvm);
6aa8b732
AK		 1754}
1755
401d10de
AS		 1756static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1757{
1758 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1759 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1760
1761 if (!msr)
1762 return;
401d10de 1763
44ea2b17
AK		 1764 /*
1765 * Force kernel_gs_base reloading before EFER changes, as control
1766 * of this msr depends on is_long_mode().
1767 */
1768 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1769 vcpu->arch.efer = efer;
401d10de
AS		 1770 if (efer & EFER_LMA) {
1771 vmcs_write32(VM_ENTRY_CONTROLS,
1772 vmcs_read32(VM_ENTRY_CONTROLS) |
1773 VM_ENTRY_IA32E_MODE);
1774 msr->data = efer;
1775 } else {
1776 vmcs_write32(VM_ENTRY_CONTROLS,
1777 vmcs_read32(VM_ENTRY_CONTROLS) &
1778 ~VM_ENTRY_IA32E_MODE);
1779
1780 msr->data = efer & ~EFER_LME;
1781 }
1782 setup_msrs(vmx);
1783}
1784
05b3e0c2 1785#ifdef CONFIG_X86_64
6aa8b732
AK		 1786
1787static void enter_lmode(struct kvm_vcpu *vcpu)
1788{
1789 u32 guest_tr_ar;
1790
1791 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1792 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1793 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1794 __func__);
6aa8b732
AK		 1795 vmcs_write32(GUEST_TR_AR_BYTES,
1796 (guest_tr_ar & ~AR_TYPE_MASK)
1797 | AR_TYPE_BUSY_64_TSS);
1798 }
da38f438 1799 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1800}
1801
1802static void exit_lmode(struct kvm_vcpu *vcpu)
1803{
6aa8b732
AK		 1804 vmcs_write32(VM_ENTRY_CONTROLS,
1805 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1806 & ~VM_ENTRY_IA32E_MODE);
da38f438 1807 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1808}
1809
1810#endif
1811
2384d2b3
SY		 1812static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1813{
b9d762fa 1814 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 1815 if (enable_ept) {
1816 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1817 return;
4e1096d2 1818 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 1819 }
2384d2b3
SY		 1820}
1821
e8467fda
AK		 1822static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1823{
1824 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1825
1826 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1827 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1828}
1829
25c4c276 1830static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1831{
fc78f519
AK		 1832 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1833
1834 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1835 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1836}
1837
1439442c
SY		 1838static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1839{
6de4f3ad
AK		 1840 if (!test_bit(VCPU_EXREG_PDPTR,
1841 (unsigned long *)&vcpu->arch.regs_dirty))
1842 return;
1843
1439442c 1844 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1845 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1846 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1847 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1848 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 1849 }
1850}
1851
8f5d549f
AK		 1852static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1853{
1854 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1855 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1856 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1857 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1858 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 1859 }
6de4f3ad
AK		 1860
1861 __set_bit(VCPU_EXREG_PDPTR,
1862 (unsigned long *)&vcpu->arch.regs_avail);
1863 __set_bit(VCPU_EXREG_PDPTR,
1864 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1865}
1866
1439442c
SY		 1867static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1868
1869static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1870 unsigned long cr0,
1871 struct kvm_vcpu *vcpu)
1872{
1873 if (!(cr0 & X86_CR0_PG)) {
1874 /* From paging/starting to nonpaging */
1875 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1876 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1877 (CPU_BASED_CR3_LOAD_EXITING |
1878 CPU_BASED_CR3_STORE_EXITING));
1879 vcpu->arch.cr0 = cr0;
fc78f519 1880 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1881 } else if (!is_paging(vcpu)) {
1882 /* From nonpaging to paging */
1883 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1884 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1885 ~(CPU_BASED_CR3_LOAD_EXITING |
1886 CPU_BASED_CR3_STORE_EXITING));
1887 vcpu->arch.cr0 = cr0;
fc78f519 1888 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1889 }
95eb84a7
SY		 1890
1891 if (!(cr0 & X86_CR0_WP))
1892 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1893}
1894
6aa8b732
AK		 1895static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1896{
7ffd92c5 1897 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1898 unsigned long hw_cr0;
1899
1900 if (enable_unrestricted_guest)
1901 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1902 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1903 else
1904 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1905
7ffd92c5 1906 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1907 enter_pmode(vcpu);
1908
7ffd92c5 1909 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1910 enter_rmode(vcpu);
1911
05b3e0c2 1912#ifdef CONFIG_X86_64
f6801dff 1913 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1914 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1915 enter_lmode(vcpu);
707d92fa 1916 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1917 exit_lmode(vcpu);
1918 }
1919#endif
1920
089d034e 1921 if (enable_ept)
1439442c
SY		 1922 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1923
02daab21 1924 if (!vcpu->fpu_active)
81231c69 1925 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1926
6aa8b732 1927 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1928 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1929 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1930}
1931
1439442c
SY		 1932static u64 construct_eptp(unsigned long root_hpa)
1933{
1934 u64 eptp;
1935
1936 /* TODO write the value reading from MSR */
1937 eptp = VMX_EPT_DEFAULT_MT |
1938 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1939 eptp |= (root_hpa & PAGE_MASK);
1940
1941 return eptp;
1942}
1943
6aa8b732
AK		 1944static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1945{
1439442c
SY		 1946 unsigned long guest_cr3;
1947 u64 eptp;
1948
1949 guest_cr3 = cr3;
089d034e 1950 if (enable_ept) {
1439442c
SY		 1951 eptp = construct_eptp(cr3);
1952 vmcs_write64(EPT_POINTER, eptp);
1439442c 1953 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1954 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1955 ept_load_pdptrs(vcpu);
1439442c
SY		 1956 }
1957
2384d2b3 1958 vmx_flush_tlb(vcpu);
1439442c 1959 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1960}
1961
1962static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1963{
7ffd92c5 1964 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1965 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1966
ad312c7c 1967 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1968 if (enable_ept) {
1969 if (!is_paging(vcpu)) {
1970 hw_cr4 &= ~X86_CR4_PAE;
1971 hw_cr4 |= X86_CR4_PSE;
1972 } else if (!(cr4 & X86_CR4_PAE)) {
1973 hw_cr4 &= ~X86_CR4_PAE;
1974 }
1975 }
1439442c
SY		 1976
1977 vmcs_writel(CR4_READ_SHADOW, cr4);
1978 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1979}
1980
6aa8b732
AK		 1981static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1982{
1983 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1984
1985 return vmcs_readl(sf->base);
1986}
1987
1988static void vmx_get_segment(struct kvm_vcpu *vcpu,
1989 struct kvm_segment *var, int seg)
1990{
1991 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1992 u32 ar;
1993
1994 var->base = vmcs_readl(sf->base);
1995 var->limit = vmcs_read32(sf->limit);
1996 var->selector = vmcs_read16(sf->selector);
1997 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1998 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1999 ar = 0;
2000 var->type = ar & 15;
2001 var->s = (ar >> 4) & 1;
2002 var->dpl = (ar >> 5) & 3;
2003 var->present = (ar >> 7) & 1;
2004 var->avl = (ar >> 12) & 1;
2005 var->l = (ar >> 13) & 1;
2006 var->db = (ar >> 14) & 1;
2007 var->g = (ar >> 15) & 1;
2008 var->unusable = (ar >> 16) & 1;
2009}
2010
2e4d2653
IE		 2011static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2012{
3eeb3288 2013 if (!is_protmode(vcpu))
2e4d2653
IE		 2014 return 0;
2015
2016 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2017 return 3;
2018
eab4b8aa 2019 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2020}
2021
653e3108 2022static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2023{
6aa8b732
AK		 2024 u32 ar;
2025
653e3108 2026 if (var->unusable)
6aa8b732
AK		 2027 ar = 1 << 16;
2028 else {
2029 ar = var->type & 15;
2030 ar |= (var->s & 1) << 4;
2031 ar |= (var->dpl & 3) << 5;
2032 ar |= (var->present & 1) << 7;
2033 ar |= (var->avl & 1) << 12;
2034 ar |= (var->l & 1) << 13;
2035 ar |= (var->db & 1) << 14;
2036 ar |= (var->g & 1) << 15;
2037 }
f7fbf1fd
UL		 2038 if (ar == 0) /* a 0 value means unusable */
2039 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2040
2041 return ar;
2042}
2043
2044static void vmx_set_segment(struct kvm_vcpu *vcpu,
2045 struct kvm_segment *var, int seg)
2046{
7ffd92c5 2047 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2048 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2049 u32 ar;
2050
7ffd92c5
AK		 2051 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2052 vmx->rmode.tr.selector = var->selector;
2053 vmx->rmode.tr.base = var->base;
2054 vmx->rmode.tr.limit = var->limit;
2055 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2056 return;
2057 }
2058 vmcs_writel(sf->base, var->base);
2059 vmcs_write32(sf->limit, var->limit);
2060 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2061 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2062 /*
2063 * Hack real-mode segments into vm86 compatibility.
2064 */
2065 if (var->base == 0xffff0000 && var->selector == 0xf000)
2066 vmcs_writel(sf->base, 0xf0000);
2067 ar = 0xf3;
2068 } else
2069 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2070
2071 /*
2072 * Fix the "Accessed" bit in AR field of segment registers for older
2073 * qemu binaries.
2074 * IA32 arch specifies that at the time of processor reset the
2075 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2076 * is setting it to 0 in the usedland code. This causes invalid guest
2077 * state vmexit when "unrestricted guest" mode is turned on.
2078 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2079 * tree. Newer qemu binaries with that qemu fix would not need this
2080 * kvm hack.
2081 */
2082 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2083 ar |= 0x1; /* Accessed */
2084
6aa8b732
AK		 2085 vmcs_write32(sf->ar_bytes, ar);
2086}
2087
6aa8b732
AK		 2088static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2089{
2090 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2091
2092 *db = (ar >> 14) & 1;
2093 *l = (ar >> 13) & 1;
2094}
2095
89a27f4d 2096static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2097{
89a27f4d
GN		 2098 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2099 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2100}
2101
89a27f4d 2102static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2103{
89a27f4d
GN		 2104 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2105 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2106}
2107
89a27f4d 2108static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2109{
89a27f4d
GN		 2110 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2111 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2112}
2113
89a27f4d 2114static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2115{
89a27f4d
GN		 2116 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2117 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2118}
2119
648dfaa7
MG		 2120static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2121{
2122 struct kvm_segment var;
2123 u32 ar;
2124
2125 vmx_get_segment(vcpu, &var, seg);
2126 ar = vmx_segment_access_rights(&var);
2127
2128 if (var.base != (var.selector << 4))
2129 return false;
2130 if (var.limit != 0xffff)
2131 return false;
2132 if (ar != 0xf3)
2133 return false;
2134
2135 return true;
2136}
2137
2138static bool code_segment_valid(struct kvm_vcpu *vcpu)
2139{
2140 struct kvm_segment cs;
2141 unsigned int cs_rpl;
2142
2143 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2144 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2145
1872a3f4
AK		 2146 if (cs.unusable)
2147 return false;
648dfaa7
MG		 2148 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2149 return false;
2150 if (!cs.s)
2151 return false;
1872a3f4 2152 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2153 if (cs.dpl > cs_rpl)
2154 return false;
1872a3f4 2155 } else {
648dfaa7
MG		 2156 if (cs.dpl != cs_rpl)
2157 return false;
2158 }
2159 if (!cs.present)
2160 return false;
2161
2162 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2163 return true;
2164}
2165
2166static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2167{
2168 struct kvm_segment ss;
2169 unsigned int ss_rpl;
2170
2171 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2172 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2173
1872a3f4
AK		 2174 if (ss.unusable)
2175 return true;
2176 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2177 return false;
2178 if (!ss.s)
2179 return false;
2180 if (ss.dpl != ss_rpl) /* DPL != RPL */
2181 return false;
2182 if (!ss.present)
2183 return false;
2184
2185 return true;
2186}
2187
2188static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2189{
2190 struct kvm_segment var;
2191 unsigned int rpl;
2192
2193 vmx_get_segment(vcpu, &var, seg);
2194 rpl = var.selector & SELECTOR_RPL_MASK;
2195
1872a3f4
AK		 2196 if (var.unusable)
2197 return true;
648dfaa7
MG		 2198 if (!var.s)
2199 return false;
2200 if (!var.present)
2201 return false;
2202 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2203 if (var.dpl < rpl) /* DPL < RPL */
2204 return false;
2205 }
2206
2207 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2208 * rights flags
2209 */
2210 return true;
2211}
2212
2213static bool tr_valid(struct kvm_vcpu *vcpu)
2214{
2215 struct kvm_segment tr;
2216
2217 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2218
1872a3f4
AK		 2219 if (tr.unusable)
2220 return false;
648dfaa7
MG		 2221 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2222 return false;
1872a3f4 2223 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2224 return false;
2225 if (!tr.present)
2226 return false;
2227
2228 return true;
2229}
2230
2231static bool ldtr_valid(struct kvm_vcpu *vcpu)
2232{
2233 struct kvm_segment ldtr;
2234
2235 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2236
1872a3f4
AK		 2237 if (ldtr.unusable)
2238 return true;
648dfaa7
MG		 2239 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2240 return false;
2241 if (ldtr.type != 2)
2242 return false;
2243 if (!ldtr.present)
2244 return false;
2245
2246 return true;
2247}
2248
2249static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2250{
2251 struct kvm_segment cs, ss;
2252
2253 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2254 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2255
2256 return ((cs.selector & SELECTOR_RPL_MASK) ==
2257 (ss.selector & SELECTOR_RPL_MASK));
2258}
2259
2260/*
2261 * Check if guest state is valid. Returns true if valid, false if
2262 * not.
2263 * We assume that registers are always usable
2264 */
2265static bool guest_state_valid(struct kvm_vcpu *vcpu)
2266{
2267 /* real mode guest state checks */
3eeb3288 2268 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2269 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2270 return false;
2271 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2272 return false;
2273 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2274 return false;
2275 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2276 return false;
2277 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2278 return false;
2279 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2280 return false;
2281 } else {
2282 /* protected mode guest state checks */
2283 if (!cs_ss_rpl_check(vcpu))
2284 return false;
2285 if (!code_segment_valid(vcpu))
2286 return false;
2287 if (!stack_segment_valid(vcpu))
2288 return false;
2289 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2290 return false;
2291 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2292 return false;
2293 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2294 return false;
2295 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2296 return false;
2297 if (!tr_valid(vcpu))
2298 return false;
2299 if (!ldtr_valid(vcpu))
2300 return false;
2301 }
2302 /* TODO:
2303 * - Add checks on RIP
2304 * - Add checks on RFLAGS
2305 */
2306
2307 return true;
2308}
2309
d77c26fc 2310static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2311{
6aa8b732 2312 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2313 u16 data = 0;
10589a46 2314 int ret = 0;
195aefde 2315 int r;
6aa8b732 2316
195aefde
IE		 2317 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2318 if (r < 0)
10589a46 2319 goto out;
195aefde 2320 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2321 r = kvm_write_guest_page(kvm, fn++, &data,
2322 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2323 if (r < 0)
10589a46 2324 goto out;
195aefde
IE		 2325 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2326 if (r < 0)
10589a46 2327 goto out;
195aefde
IE		 2328 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2329 if (r < 0)
10589a46 2330 goto out;
195aefde 2331 data = ~0;
10589a46
MT		 2332 r = kvm_write_guest_page(kvm, fn, &data,
2333 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2334 sizeof(u8));
195aefde 2335 if (r < 0)
10589a46
MT		 2336 goto out;
2337
2338 ret = 1;
2339out:
10589a46 2340 return ret;
6aa8b732
AK		 2341}
2342
b7ebfb05
SY		 2343static int init_rmode_identity_map(struct kvm *kvm)
2344{
2345 int i, r, ret;
2346 pfn_t identity_map_pfn;
2347 u32 tmp;
2348
089d034e 2349 if (!enable_ept)
b7ebfb05
SY		 2350 return 1;
2351 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2352 printk(KERN_ERR "EPT: identity-mapping pagetable "
2353 "haven't been allocated!\n");
2354 return 0;
2355 }
2356 if (likely(kvm->arch.ept_identity_pagetable_done))
2357 return 1;
2358 ret = 0;
b927a3ce 2359 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2360 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2361 if (r < 0)
2362 goto out;
2363 /* Set up identity-mapping pagetable for EPT in real mode */
2364 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2365 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2366 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2367 r = kvm_write_guest_page(kvm, identity_map_pfn,
2368 &tmp, i * sizeof(tmp), sizeof(tmp));
2369 if (r < 0)
2370 goto out;
2371 }
2372 kvm->arch.ept_identity_pagetable_done = true;
2373 ret = 1;
2374out:
2375 return ret;
2376}
2377
6aa8b732
AK		 2378static void seg_setup(int seg)
2379{
2380 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2381 unsigned int ar;
6aa8b732
AK		 2382
2383 vmcs_write16(sf->selector, 0);
2384 vmcs_writel(sf->base, 0);
2385 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2386 if (enable_unrestricted_guest) {
2387 ar = 0x93;
2388 if (seg == VCPU_SREG_CS)
2389 ar |= 0x08; /* code segment */
2390 } else
2391 ar = 0xf3;
2392
2393 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2394}
2395
f78e0e2e
SY		 2396static int alloc_apic_access_page(struct kvm *kvm)
2397{
2398 struct kvm_userspace_memory_region kvm_userspace_mem;
2399 int r = 0;
2400
79fac95e 2401 mutex_lock(&kvm->slots_lock);
bfc6d222 2402 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2403 goto out;
2404 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2405 kvm_userspace_mem.flags = 0;
2406 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2407 kvm_userspace_mem.memory_size = PAGE_SIZE;
2408 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2409 if (r)
2410 goto out;
72dc67a6 2411
bfc6d222 2412 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2413out:
79fac95e 2414 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2415 return r;
2416}
2417
b7ebfb05
SY		 2418static int alloc_identity_pagetable(struct kvm *kvm)
2419{
2420 struct kvm_userspace_memory_region kvm_userspace_mem;
2421 int r = 0;
2422
79fac95e 2423 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2424 if (kvm->arch.ept_identity_pagetable)
2425 goto out;
2426 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2427 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2428 kvm_userspace_mem.guest_phys_addr =
2429 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2430 kvm_userspace_mem.memory_size = PAGE_SIZE;
2431 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2432 if (r)
2433 goto out;
2434
b7ebfb05 2435 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2436 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2437out:
79fac95e 2438 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2439 return r;
2440}
2441
2384d2b3
SY		 2442static void allocate_vpid(struct vcpu_vmx *vmx)
2443{
2444 int vpid;
2445
2446 vmx->vpid = 0;
919818ab 2447 if (!enable_vpid)
2384d2b3
SY		 2448 return;
2449 spin_lock(&vmx_vpid_lock);
2450 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2451 if (vpid < VMX_NR_VPIDS) {
2452 vmx->vpid = vpid;
2453 __set_bit(vpid, vmx_vpid_bitmap);
2454 }
2455 spin_unlock(&vmx_vpid_lock);
2456}
2457
cdbecfc3
LJ		 2458static void free_vpid(struct vcpu_vmx *vmx)
2459{
2460 if (!enable_vpid)
2461 return;
2462 spin_lock(&vmx_vpid_lock);
2463 if (vmx->vpid != 0)
2464 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2465 spin_unlock(&vmx_vpid_lock);
2466}
2467
5897297b 2468static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2469{
3e7c73e9 2470 int f = sizeof(unsigned long);
25c5f225
SY		 2471
2472 if (!cpu_has_vmx_msr_bitmap())
2473 return;
2474
2475 /*
2476 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2477 * have the write-low and read-high bitmap offsets the wrong way round.
2478 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2479 */
25c5f225 2480 if (msr <= 0x1fff) {
3e7c73e9
AK		 2481 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2482 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2483 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2484 msr &= 0x1fff;
3e7c73e9
AK		 2485 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2486 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2487 }
25c5f225
SY		 2488}
2489
5897297b
AK		 2490static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2491{
2492 if (!longmode_only)
2493 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2494 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2495}
2496
6aa8b732
AK		 2497/*
2498 * Sets up the vmcs for emulated real mode.
2499 */
8b9cf98c 2500static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2501{
468d472f 2502 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2503 u32 junk;
f4e1b3c8 2504 u64 host_pat;
6aa8b732 2505 unsigned long a;
89a27f4d 2506 struct desc_ptr dt;
6aa8b732 2507 int i;
cd2276a7 2508 unsigned long kvm_vmx_return;
6e5d865c 2509 u32 exec_control;
6aa8b732 2510
6aa8b732 2511 /* I/O */
3e7c73e9
AK		 2512 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2513 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2514
25c5f225 2515 if (cpu_has_vmx_msr_bitmap())
5897297b 2516 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2517
6aa8b732
AK		 2518 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2519
6aa8b732 2520 /* Control */
1c3d14fe
YS		 2521 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2522 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2523
2524 exec_control = vmcs_config.cpu_based_exec_ctrl;
2525 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2526 exec_control &= ~CPU_BASED_TPR_SHADOW;
2527#ifdef CONFIG_X86_64
2528 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2529 CPU_BASED_CR8_LOAD_EXITING;
2530#endif
2531 }
089d034e 2532 if (!enable_ept)
d56f546d 2533 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2534 CPU_BASED_CR3_LOAD_EXITING |
2535 CPU_BASED_INVLPG_EXITING;
6e5d865c 2536 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2537
83ff3b9d
SY		 2538 if (cpu_has_secondary_exec_ctrls()) {
2539 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2540 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2541 exec_control &=
2542 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2543 if (vmx->vpid == 0)
2544 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2545 if (!enable_ept) {
d56f546d 2546 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2547 enable_unrestricted_guest = 0;
2548 }
3a624e29
NK		 2549 if (!enable_unrestricted_guest)
2550 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2551 if (!ple_gap)
2552 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2553 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2554 }
f78e0e2e 2555
4b8d54f9
ZE		 2556 if (ple_gap) {
2557 vmcs_write32(PLE_GAP, ple_gap);
2558 vmcs_write32(PLE_WINDOW, ple_window);
2559 }
2560
c7addb90
AK		 2561 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2562 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2563 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2564
1c11e713 2565 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2566 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2567 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2568
2569 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2570 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2571 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
9581d442
AK		 2572 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2573 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6aa8b732 2574 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2575#ifdef CONFIG_X86_64
6aa8b732
AK		 2576 rdmsrl(MSR_FS_BASE, a);
2577 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2578 rdmsrl(MSR_GS_BASE, a);
2579 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2580#else
2581 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2582 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2583#endif
2584
2585 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2586
ec68798c 2587 native_store_idt(&dt);
89a27f4d 2588 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2589
d77c26fc 2590 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2591 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2592 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2593 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2594 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2595 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2596 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2597
2598 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2599 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2600 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2601 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2602 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2603 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2604
468d472f
SY		 2605 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2606 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2607 host_pat = msr_low | ((u64) msr_high << 32);
2608 vmcs_write64(HOST_IA32_PAT, host_pat);
2609 }
2610 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2611 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2612 host_pat = msr_low | ((u64) msr_high << 32);
2613 /* Write the default value follow host pat */
2614 vmcs_write64(GUEST_IA32_PAT, host_pat);
2615 /* Keep arch.pat sync with GUEST_IA32_PAT */
2616 vmx->vcpu.arch.pat = host_pat;
2617 }
2618
6aa8b732
AK		 2619 for (i = 0; i < NR_VMX_MSR; ++i) {
2620 u32 index = vmx_msr_index[i];
2621 u32 data_low, data_high;
a2fa3e9f 2622 int j = vmx->nmsrs;
6aa8b732
AK		 2623
2624 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2625 continue;
432bd6cb
AK		 2626 if (wrmsr_safe(index, data_low, data_high) < 0)
2627 continue;
26bb0981
AK		 2628 vmx->guest_msrs[j].index = i;
2629 vmx->guest_msrs[j].data = 0;
d5696725 2630 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2631 ++vmx->nmsrs;
6aa8b732 2632 }
6aa8b732 2633
1c3d14fe 2634 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2635
2636 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2637 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2638
e00c8cf2 2639 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2640 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2641 if (enable_ept)
2642 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2643 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2644
99e3e30a 2645 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 2646
e00c8cf2
AK		 2647 return 0;
2648}
2649
b7ebfb05
SY		 2650static int init_rmode(struct kvm *kvm)
2651{
4b9d3a04
XG		 2652 int idx, ret = 0;
2653
2654 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05 2655 if (!init_rmode_tss(kvm))
4b9d3a04 2656 goto exit;
b7ebfb05 2657 if (!init_rmode_identity_map(kvm))
4b9d3a04
XG		 2658 goto exit;
2659
2660 ret = 1;
2661exit:
2662 srcu_read_unlock(&kvm->srcu, idx);
2663 return ret;
b7ebfb05
SY		 2664}
2665
e00c8cf2
AK		 2666static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2667{
2668 struct vcpu_vmx *vmx = to_vmx(vcpu);
2669 u64 msr;
4b9d3a04 2670 int ret;
e00c8cf2 2671
5fdbf976 2672 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
b7ebfb05 2673 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2674 ret = -ENOMEM;
2675 goto out;
2676 }
2677
7ffd92c5 2678 vmx->rmode.vm86_active = 0;
e00c8cf2 2679
3b86cd99
JK		 2680 vmx->soft_vnmi_blocked = 0;
2681
ad312c7c 2682 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2683 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2684 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2685 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2686 msr |= MSR_IA32_APICBASE_BSP;
2687 kvm_set_apic_base(&vmx->vcpu, msr);
2688
10ab25cd
JK		 2689 ret = fx_init(&vmx->vcpu);
2690 if (ret != 0)
2691 goto out;
e00c8cf2 2692
5706be0d 2693 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2694 /*
2695 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2696 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2697 */
c5af89b6 2698 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2699 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2700 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2701 } else {
ad312c7c
ZX		 2702 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2703 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2704 }
e00c8cf2
AK		 2705
2706 seg_setup(VCPU_SREG_DS);
2707 seg_setup(VCPU_SREG_ES);
2708 seg_setup(VCPU_SREG_FS);
2709 seg_setup(VCPU_SREG_GS);
2710 seg_setup(VCPU_SREG_SS);
2711
2712 vmcs_write16(GUEST_TR_SELECTOR, 0);
2713 vmcs_writel(GUEST_TR_BASE, 0);
2714 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2715 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2716
2717 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2718 vmcs_writel(GUEST_LDTR_BASE, 0);
2719 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2720 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2721
2722 vmcs_write32(GUEST_SYSENTER_CS, 0);
2723 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2724 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2725
2726 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2727 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2728 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2729 else
5fdbf976
MT		 2730 kvm_rip_write(vcpu, 0);
2731 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2732
e00c8cf2
AK		 2733 vmcs_writel(GUEST_DR7, 0x400);
2734
2735 vmcs_writel(GUEST_GDTR_BASE, 0);
2736 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2737
2738 vmcs_writel(GUEST_IDTR_BASE, 0);
2739 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2740
2741 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2742 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2743 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2744
e00c8cf2
AK		 2745 /* Special registers */
2746 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2747
2748 setup_msrs(vmx);
2749
6aa8b732
AK		 2750 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2751
f78e0e2e
SY		 2752 if (cpu_has_vmx_tpr_shadow()) {
2753 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2754 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2755 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2756 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2757 vmcs_write32(TPR_THRESHOLD, 0);
2758 }
2759
2760 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2761 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2762 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2763
2384d2b3
SY		 2764 if (vmx->vpid != 0)
2765 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2766
fa40052c 2767 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2768 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2769 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2770 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2771 vmx_fpu_activate(&vmx->vcpu);
2772 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2773
b9d762fa 2774 vpid_sync_context(vmx);
2384d2b3 2775
3200f405 2776 ret = 0;
6aa8b732 2777
a89a8fb9
MG		 2778 /* HACK: Don't enable emulation on guest boot/reset */
2779 vmx->emulation_required = 0;
2780
6aa8b732
AK		 2781out:
2782 return ret;
2783}
2784
3b86cd99
JK		 2785static void enable_irq_window(struct kvm_vcpu *vcpu)
2786{
2787 u32 cpu_based_vm_exec_control;
2788
2789 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2790 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2791 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2792}
2793
2794static void enable_nmi_window(struct kvm_vcpu *vcpu)
2795{
2796 u32 cpu_based_vm_exec_control;
2797
2798 if (!cpu_has_virtual_nmis()) {
2799 enable_irq_window(vcpu);
2800 return;
2801 }
2802
2803 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2804 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2805 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2806}
2807
66fd3f7f 2808static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2809{
9c8cba37 2810 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2811 uint32_t intr;
2812 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2813
229456fc 2814 trace_kvm_inj_virq(irq);
2714d1d3 2815
fa89a817 2816 ++vcpu->stat.irq_injections;
7ffd92c5 2817 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2818 vmx->rmode.irq.pending = true;
2819 vmx->rmode.irq.vector = irq;
5fdbf976 2820 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2821 if (vcpu->arch.interrupt.soft)
2822 vmx->rmode.irq.rip +=
2823 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2824 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2825 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2826 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2827 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2828 return;
2829 }
66fd3f7f
GN		 2830 intr = irq | INTR_INFO_VALID_MASK;
2831 if (vcpu->arch.interrupt.soft) {
2832 intr |= INTR_TYPE_SOFT_INTR;
2833 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2834 vmx->vcpu.arch.event_exit_inst_len);
2835 } else
2836 intr |= INTR_TYPE_EXT_INTR;
2837 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2838}
2839
f08864b4
SY		 2840static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2841{
66a5a347
JK		 2842 struct vcpu_vmx *vmx = to_vmx(vcpu);
2843
3b86cd99
JK		 2844 if (!cpu_has_virtual_nmis()) {
2845 /*
2846 * Tracking the NMI-blocked state in software is built upon
2847 * finding the next open IRQ window. This, in turn, depends on
2848 * well-behaving guests: They have to keep IRQs disabled at
2849 * least as long as the NMI handler runs. Otherwise we may
2850 * cause NMI nesting, maybe breaking the guest. But as this is
2851 * highly unlikely, we can live with the residual risk.
2852 */
2853 vmx->soft_vnmi_blocked = 1;
2854 vmx->vnmi_blocked_time = 0;
2855 }
2856
487b391d 2857 ++vcpu->stat.nmi_injections;
7ffd92c5 2858 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2859 vmx->rmode.irq.pending = true;
2860 vmx->rmode.irq.vector = NMI_VECTOR;
2861 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2862 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2863 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2864 INTR_INFO_VALID_MASK);
2865 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2866 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2867 return;
2868 }
f08864b4
SY		 2869 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2870 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2871}
2872
c4282df9 2873static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2874{
3b86cd99 2875 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2876 return 0;
33f089ca 2877
c4282df9 2878 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
f8c5fae1 2879 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2880}
2881
3cfc3092
JK		 2882static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2883{
2884 if (!cpu_has_virtual_nmis())
2885 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2886 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2887}
2888
2889static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2890{
2891 struct vcpu_vmx *vmx = to_vmx(vcpu);
2892
2893 if (!cpu_has_virtual_nmis()) {
2894 if (vmx->soft_vnmi_blocked != masked) {
2895 vmx->soft_vnmi_blocked = masked;
2896 vmx->vnmi_blocked_time = 0;
2897 }
2898 } else {
2899 if (masked)
2900 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2901 GUEST_INTR_STATE_NMI);
2902 else
2903 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2904 GUEST_INTR_STATE_NMI);
2905 }
2906}
2907
78646121
GN		 2908static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2909{
c4282df9
GN		 2910 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2911 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2912 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2913}
2914
cbc94022
IE		 2915static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2916{
2917 int ret;
2918 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2919 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2920 .guest_phys_addr = addr,
2921 .memory_size = PAGE_SIZE * 3,
2922 .flags = 0,
2923 };
2924
2925 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2926 if (ret)
2927 return ret;
bfc6d222 2928 kvm->arch.tss_addr = addr;
cbc94022
IE		 2929 return 0;
2930}
2931
6aa8b732
AK		 2932static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2933 int vec, u32 err_code)
2934{
b3f37707
NK		 2935 /*
2936 * Instruction with address size override prefix opcode 0x67
2937 * Cause the #SS fault with 0 error code in VM86 mode.
2938 */
2939 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2940 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2941 return 1;
77ab6db0
JK		 2942 /*
2943 * Forward all other exceptions that are valid in real mode.
2944 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2945 * the required debugging infrastructure rework.
2946 */
2947 switch (vec) {
77ab6db0 2948 case DB_VECTOR:
d0bfb940
JK		 2949 if (vcpu->guest_debug &
2950 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2951 return 0;
2952 kvm_queue_exception(vcpu, vec);
2953 return 1;
77ab6db0 2954 case BP_VECTOR:
c573cd22
JK		 2955 /*
2956 * Update instruction length as we may reinject the exception
2957 * from user space while in guest debugging mode.
2958 */
2959 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2960 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2961 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2962 return 0;
2963 /* fall through */
2964 case DE_VECTOR:
77ab6db0
JK		 2965 case OF_VECTOR:
2966 case BR_VECTOR:
2967 case UD_VECTOR:
2968 case DF_VECTOR:
2969 case SS_VECTOR:
2970 case GP_VECTOR:
2971 case MF_VECTOR:
2972 kvm_queue_exception(vcpu, vec);
2973 return 1;
2974 }
6aa8b732
AK		 2975 return 0;
2976}
2977
a0861c02
AK		 2978/*
2979 * Trigger machine check on the host. We assume all the MSRs are already set up
2980 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2981 * We pass a fake environment to the machine check handler because we want
2982 * the guest to be always treated like user space, no matter what context
2983 * it used internally.
2984 */
2985static void kvm_machine_check(void)
2986{
2987#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2988 struct pt_regs regs = {
2989 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2990 .flags = X86_EFLAGS_IF,
2991 };
2992
2993 do_machine_check(&regs, 0);
2994#endif
2995}
2996
851ba692 2997static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2998{
2999 /* already handled by vcpu_run */
3000 return 1;
3001}
3002
851ba692 3003static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3004{
1155f76a 3005 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3006 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3007 u32 intr_info, ex_no, error_code;
42dbaa5a 3008 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3009 u32 vect_info;
3010 enum emulation_result er;
3011
1155f76a 3012 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 3013 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3014
a0861c02 3015 if (is_machine_check(intr_info))
851ba692 3016 return handle_machine_check(vcpu);
a0861c02 3017
6aa8b732 3018 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3019 !is_page_fault(intr_info)) {
3020 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3021 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3022 vcpu->run->internal.ndata = 2;
3023 vcpu->run->internal.data[0] = vect_info;
3024 vcpu->run->internal.data[1] = intr_info;
3025 return 0;
3026 }
6aa8b732 3027
e4a41889 3028 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3029 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3030
3031 if (is_no_device(intr_info)) {
5fd86fcf 3032 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3033 return 1;
3034 }
3035
7aa81cc0 3036 if (is_invalid_opcode(intr_info)) {
851ba692 3037 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 3038 if (er != EMULATE_DONE)
7ee5d940 3039 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3040 return 1;
3041 }
3042
6aa8b732 3043 error_code = 0;
5fdbf976 3044 rip = kvm_rip_read(vcpu);
2e11384c 3045 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3046 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3047 if (is_page_fault(intr_info)) {
1439442c 3048 /* EPT won't cause page fault directly */
089d034e 3049 if (enable_ept)
1439442c 3050 BUG();
6aa8b732 3051 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3052 trace_kvm_page_fault(cr2, error_code);
3053
3298b75c 3054 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3055 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 3056 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 3057 }
3058
7ffd92c5 3059 if (vmx->rmode.vm86_active &&
6aa8b732 3060 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3061 error_code)) {
ad312c7c
ZX		 3062 if (vcpu->arch.halt_request) {
3063 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3064 return kvm_emulate_halt(vcpu);
3065 }
6aa8b732 3066 return 1;
72d6e5a0 3067 }
6aa8b732 3068
d0bfb940 3069 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3070 switch (ex_no) {
3071 case DB_VECTOR:
3072 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3073 if (!(vcpu->guest_debug &
3074 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3075 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3076 kvm_queue_exception(vcpu, DB_VECTOR);
3077 return 1;
3078 }
3079 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3080 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3081 /* fall through */
3082 case BP_VECTOR:
c573cd22
JK		 3083 /*
3084 * Update instruction length as we may reinject #BP from
3085 * user space while in guest debugging mode. Reading it for
3086 * #DB as well causes no harm, it is not used in that case.
3087 */
3088 vmx->vcpu.arch.event_exit_inst_len =
3089 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3090 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3091 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3092 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3093 break;
3094 default:
d0bfb940
JK		 3095 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3096 kvm_run->ex.exception = ex_no;
3097 kvm_run->ex.error_code = error_code;
42dbaa5a 3098 break;
6aa8b732 3099 }
6aa8b732
AK		 3100 return 0;
3101}
3102
851ba692 3103static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3104{
1165f5fe 3105 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3106 return 1;
3107}
3108
851ba692 3109static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3110{
851ba692 3111 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3112 return 0;
3113}
6aa8b732 3114
851ba692 3115static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3116{
bfdaab09 3117 unsigned long exit_qualification;
34c33d16 3118 int size, in, string;
039576c0 3119 unsigned port;
6aa8b732 3120
bfdaab09 3121 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3122 string = (exit_qualification & 16) != 0;
cf8f70bf 3123 in = (exit_qualification & 8) != 0;
e70669ab 3124
cf8f70bf 3125 ++vcpu->stat.io_exits;
e70669ab 3126
cf8f70bf 3127 if (string || in)
6d77dbfc 3128 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
e70669ab 3129
cf8f70bf
GN		 3130 port = exit_qualification >> 16;
3131 size = (exit_qualification & 7) + 1;
e93f36bc 3132 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3133
3134 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3135}
3136
102d8325
IM		 3137static void
3138vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3139{
3140 /*
3141 * Patch in the VMCALL instruction:
3142 */
3143 hypercall[0] = 0x0f;
3144 hypercall[1] = 0x01;
3145 hypercall[2] = 0xc1;
102d8325
IM		 3146}
3147
49a9b07e
AK		 3148static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3149{
3150 if (err)
3151 kvm_inject_gp(vcpu, 0);
3152 else
3153 skip_emulated_instruction(vcpu);
3154}
3155
851ba692 3156static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3157{
229456fc 3158 unsigned long exit_qualification, val;
6aa8b732
AK		 3159 int cr;
3160 int reg;
49a9b07e 3161 int err;
6aa8b732 3162
bfdaab09 3163 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3164 cr = exit_qualification & 15;
3165 reg = (exit_qualification >> 8) & 15;
3166 switch ((exit_qualification >> 4) & 3) {
3167 case 0: /* mov to cr */
229456fc
MT		 3168 val = kvm_register_read(vcpu, reg);
3169 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3170 switch (cr) {
3171 case 0:
49a9b07e
AK		 3172 err = kvm_set_cr0(vcpu, val);
3173 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3174 return 1;
3175 case 3:
2390218b
AK		 3176 err = kvm_set_cr3(vcpu, val);
3177 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3178 return 1;
3179 case 4:
a83b29c6
AK		 3180 err = kvm_set_cr4(vcpu, val);
3181 complete_insn_gp(vcpu, err);
6aa8b732 3182 return 1;
0a5fff19
GN		 3183 case 8: {
3184 u8 cr8_prev = kvm_get_cr8(vcpu);
3185 u8 cr8 = kvm_register_read(vcpu, reg);
3186 kvm_set_cr8(vcpu, cr8);
3187 skip_emulated_instruction(vcpu);
3188 if (irqchip_in_kernel(vcpu->kvm))
3189 return 1;
3190 if (cr8_prev <= cr8)
3191 return 1;
851ba692 3192 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3193 return 0;
3194 }
6aa8b732
AK		 3195 };
3196 break;
25c4c276 3197 case 2: /* clts */
edcafe3c 3198 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3199 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3200 skip_emulated_instruction(vcpu);
6b52d186 3201 vmx_fpu_activate(vcpu);
25c4c276 3202 return 1;
6aa8b732
AK		 3203 case 1: /*mov from cr*/
3204 switch (cr) {
3205 case 3:
5fdbf976 3206 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3207 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3208 skip_emulated_instruction(vcpu);
3209 return 1;
3210 case 8:
229456fc
MT		 3211 val = kvm_get_cr8(vcpu);
3212 kvm_register_write(vcpu, reg, val);
3213 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3214 skip_emulated_instruction(vcpu);
3215 return 1;
3216 }
3217 break;
3218 case 3: /* lmsw */
a1f83a74 3219 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3220 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3221 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3222
3223 skip_emulated_instruction(vcpu);
3224 return 1;
3225 default:
3226 break;
3227 }
851ba692 3228 vcpu->run->exit_reason = 0;
f0242478 3229 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3230 (int)(exit_qualification >> 4) & 3, cr);
3231 return 0;
3232}
3233
851ba692 3234static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3235{
bfdaab09 3236 unsigned long exit_qualification;
6aa8b732
AK		 3237 int dr, reg;
3238
f2483415 3239 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3240 if (!kvm_require_cpl(vcpu, 0))
3241 return 1;
42dbaa5a
JK		 3242 dr = vmcs_readl(GUEST_DR7);
3243 if (dr & DR7_GD) {
3244 /*
3245 * As the vm-exit takes precedence over the debug trap, we
3246 * need to emulate the latter, either for the host or the
3247 * guest debugging itself.
3248 */
3249 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3250 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3251 vcpu->run->debug.arch.dr7 = dr;
3252 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3253 vmcs_readl(GUEST_CS_BASE) +
3254 vmcs_readl(GUEST_RIP);
851ba692
AK		 3255 vcpu->run->debug.arch.exception = DB_VECTOR;
3256 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3257 return 0;
3258 } else {
3259 vcpu->arch.dr7 &= ~DR7_GD;
3260 vcpu->arch.dr6 |= DR6_BD;
3261 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3262 kvm_queue_exception(vcpu, DB_VECTOR);
3263 return 1;
3264 }
3265 }
3266
bfdaab09 3267 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3268 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3269 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3270 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3271 unsigned long val;
3272 if (!kvm_get_dr(vcpu, dr, &val))
3273 kvm_register_write(vcpu, reg, val);
3274 } else
3275 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3276 skip_emulated_instruction(vcpu);
3277 return 1;
3278}
3279
020df079
GN		 3280static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3281{
3282 vmcs_writel(GUEST_DR7, val);
3283}
3284
851ba692 3285static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3286{
06465c5a
AK		 3287 kvm_emulate_cpuid(vcpu);
3288 return 1;
6aa8b732
AK		 3289}
3290
851ba692 3291static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3292{
ad312c7c 3293 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3294 u64 data;
3295
3296 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3297 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3298 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3299 return 1;
3300 }
3301
229456fc 3302 trace_kvm_msr_read(ecx, data);
2714d1d3 3303
6aa8b732 3304 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3305 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3306 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3307 skip_emulated_instruction(vcpu);
3308 return 1;
3309}
3310
851ba692 3311static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3312{
ad312c7c
ZX		 3313 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3314 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3315 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3316
3317 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3318 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3319 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3320 return 1;
3321 }
3322
59200273 3323 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3324 skip_emulated_instruction(vcpu);
3325 return 1;
3326}
3327
851ba692 3328static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3329{
3330 return 1;
3331}
3332
851ba692 3333static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3334{
85f455f7
ED		 3335 u32 cpu_based_vm_exec_control;
3336
3337 /* clear pending irq */
3338 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3339 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3340 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3341
a26bf12a 3342 ++vcpu->stat.irq_window_exits;
2714d1d3 3343
c1150d8c
DL		 3344 /*
3345 * If the user space waits to inject interrupts, exit as soon as
3346 * possible
3347 */
8061823a 3348 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3349 vcpu->run->request_interrupt_window &&
8061823a 3350 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3351 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3352 return 0;
3353 }
6aa8b732
AK		 3354 return 1;
3355}
3356
851ba692 3357static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3358{
3359 skip_emulated_instruction(vcpu);
d3bef15f 3360 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3361}
3362
851ba692 3363static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3364{
510043da 3365 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3366 kvm_emulate_hypercall(vcpu);
3367 return 1;
c21415e8
IM		 3368}
3369
851ba692 3370static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3371{
3372 kvm_queue_exception(vcpu, UD_VECTOR);
3373 return 1;
3374}
3375
851ba692 3376static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3377{
f9c617f6 3378 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3379
3380 kvm_mmu_invlpg(vcpu, exit_qualification);
3381 skip_emulated_instruction(vcpu);
3382 return 1;
3383}
3384
851ba692 3385static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3386{
3387 skip_emulated_instruction(vcpu);
f5f48ee1 3388 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3389 return 1;
3390}
3391
2acf923e
DC		 3392static int handle_xsetbv(struct kvm_vcpu *vcpu)
3393{
3394 u64 new_bv = kvm_read_edx_eax(vcpu);
3395 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3396
3397 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3398 skip_emulated_instruction(vcpu);
3399 return 1;
3400}
3401
851ba692 3402static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3403{
6d77dbfc 3404 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
f78e0e2e
SY		 3405}
3406
851ba692 3407static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3408{
60637aac 3409 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3410 unsigned long exit_qualification;
e269fb21
JK		 3411 bool has_error_code = false;
3412 u32 error_code = 0;
37817f29 3413 u16 tss_selector;
64a7ec06
GN		 3414 int reason, type, idt_v;
3415
3416 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3417 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3418
3419 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3420
3421 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3422 if (reason == TASK_SWITCH_GATE && idt_v) {
3423 switch (type) {
3424 case INTR_TYPE_NMI_INTR:
3425 vcpu->arch.nmi_injected = false;
3426 if (cpu_has_virtual_nmis())
3427 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3428 GUEST_INTR_STATE_NMI);
3429 break;
3430 case INTR_TYPE_EXT_INTR:
66fd3f7f 3431 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3432 kvm_clear_interrupt_queue(vcpu);
3433 break;
3434 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3435 if (vmx->idt_vectoring_info &
3436 VECTORING_INFO_DELIVER_CODE_MASK) {
3437 has_error_code = true;
3438 error_code =
3439 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3440 }
3441 /* fall through */
64a7ec06
GN		 3442 case INTR_TYPE_SOFT_EXCEPTION:
3443 kvm_clear_exception_queue(vcpu);
3444 break;
3445 default:
3446 break;
3447 }
60637aac 3448 }
37817f29
IE		 3449 tss_selector = exit_qualification;
3450
64a7ec06
GN		 3451 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3452 type != INTR_TYPE_EXT_INTR &&
3453 type != INTR_TYPE_NMI_INTR))
3454 skip_emulated_instruction(vcpu);
3455
acb54517
GN		 3456 if (kvm_task_switch(vcpu, tss_selector, reason,
3457 has_error_code, error_code) == EMULATE_FAIL) {
3458 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3459 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3460 vcpu->run->internal.ndata = 0;
42dbaa5a 3461 return 0;
acb54517 3462 }
42dbaa5a
JK		 3463
3464 /* clear all local breakpoint enable flags */
3465 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3466
3467 /*
3468 * TODO: What about debug traps on tss switch?
3469 * Are we supposed to inject them and update dr6?
3470 */
3471
3472 return 1;
37817f29
IE		 3473}
3474
851ba692 3475static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3476{
f9c617f6 3477 unsigned long exit_qualification;
1439442c 3478 gpa_t gpa;
1439442c 3479 int gla_validity;
1439442c 3480
f9c617f6 3481 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3482
3483 if (exit_qualification & (1 << 6)) {
3484 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3485 return -EINVAL;
1439442c
SY		 3486 }
3487
3488 gla_validity = (exit_qualification >> 7) & 0x3;
3489 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3490 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3491 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3492 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3493 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3494 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3495 (long unsigned int)exit_qualification);
851ba692
AK		 3496 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3497 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3498 return 0;
1439442c
SY		 3499 }
3500
3501 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3502 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3503 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3504}
3505
68f89400
MT		 3506static u64 ept_rsvd_mask(u64 spte, int level)
3507{
3508 int i;
3509 u64 mask = 0;
3510
3511 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3512 mask |= (1ULL << i);
3513
3514 if (level > 2)
3515 /* bits 7:3 reserved */
3516 mask |= 0xf8;
3517 else if (level == 2) {
3518 if (spte & (1ULL << 7))
3519 /* 2MB ref, bits 20:12 reserved */
3520 mask |= 0x1ff000;
3521 else
3522 /* bits 6:3 reserved */
3523 mask |= 0x78;
3524 }
3525
3526 return mask;
3527}
3528
3529static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3530 int level)
3531{
3532 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3533
3534 /* 010b (write-only) */
3535 WARN_ON((spte & 0x7) == 0x2);
3536
3537 /* 110b (write/execute) */
3538 WARN_ON((spte & 0x7) == 0x6);
3539
3540 /* 100b (execute-only) and value not supported by logical processor */
3541 if (!cpu_has_vmx_ept_execute_only())
3542 WARN_ON((spte & 0x7) == 0x4);
3543
3544 /* not 000b */
3545 if ((spte & 0x7)) {
3546 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3547
3548 if (rsvd_bits != 0) {
3549 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3550 __func__, rsvd_bits);
3551 WARN_ON(1);
3552 }
3553
3554 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3555 u64 ept_mem_type = (spte & 0x38) >> 3;
3556
3557 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3558 ept_mem_type == 7) {
3559 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3560 __func__, ept_mem_type);
3561 WARN_ON(1);
3562 }
3563 }
3564 }
3565}
3566
851ba692 3567static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3568{
3569 u64 sptes[4];
3570 int nr_sptes, i;
3571 gpa_t gpa;
3572
3573 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3574
3575 printk(KERN_ERR "EPT: Misconfiguration.\n");
3576 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3577
3578 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3579
3580 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3581 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3582
851ba692
AK		 3583 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3584 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3585
3586 return 0;
3587}
3588
851ba692 3589static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3590{
3591 u32 cpu_based_vm_exec_control;
3592
3593 /* clear pending NMI */
3594 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3595 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3596 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3597 ++vcpu->stat.nmi_window_exits;
3598
3599 return 1;
3600}
3601
80ced186 3602static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3603{
8b3079a5
AK		 3604 struct vcpu_vmx *vmx = to_vmx(vcpu);
3605 enum emulation_result err = EMULATE_DONE;
80ced186 3606 int ret = 1;
ea953ef0
MG		 3607
3608 while (!guest_state_valid(vcpu)) {
851ba692 3609 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3610
80ced186
MG		 3611 if (err == EMULATE_DO_MMIO) {
3612 ret = 0;
3613 goto out;
3614 }
1d5a4d9b 3615
6d77dbfc
GN		 3616 if (err != EMULATE_DONE)
3617 return 0;
ea953ef0
MG		 3618
3619 if (signal_pending(current))
80ced186 3620 goto out;
ea953ef0
MG		 3621 if (need_resched())
3622 schedule();
3623 }
3624
80ced186
MG		 3625 vmx->emulation_required = 0;
3626out:
3627 return ret;
ea953ef0
MG		 3628}
3629
4b8d54f9
ZE		 3630/*
3631 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3632 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3633 */
9fb41ba8 3634static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3635{
3636 skip_emulated_instruction(vcpu);
3637 kvm_vcpu_on_spin(vcpu);
3638
3639 return 1;
3640}
3641
59708670
SY		 3642static int handle_invalid_op(struct kvm_vcpu *vcpu)
3643{
3644 kvm_queue_exception(vcpu, UD_VECTOR);
3645 return 1;
3646}
3647
6aa8b732
AK		 3648/*
3649 * The exit handlers return 1 if the exit was handled fully and guest execution
3650 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3651 * to be done to userspace and return 0.
3652 */
851ba692 3653static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3654 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3655 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3656 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3657 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3658 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3659 [EXIT_REASON_CR_ACCESS] = handle_cr,
3660 [EXIT_REASON_DR_ACCESS] = handle_dr,
3661 [EXIT_REASON_CPUID] = handle_cpuid,
3662 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3663 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3664 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3665 [EXIT_REASON_HLT] = handle_halt,
a7052897 3666 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3667 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3668 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3669 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3670 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3671 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3672 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3673 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3674 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3675 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3676 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3677 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3678 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3679 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3680 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3681 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3682 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3683 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3684 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3685 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3686 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3687 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3688};
3689
3690static const int kvm_vmx_max_exit_handlers =
50a3485c 3691 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3692
3693/*
3694 * The guest has exited. See if we can fix it or if we need userspace
3695 * assistance.
3696 */
851ba692 3697static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3698{
29bd8a78 3699 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3700 u32 exit_reason = vmx->exit_reason;
1155f76a 3701 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3702
5bfd8b54 3703 trace_kvm_exit(exit_reason, vcpu);
2714d1d3 3704
80ced186
MG		 3705 /* If guest state is invalid, start emulating */
3706 if (vmx->emulation_required && emulate_invalid_guest_state)
3707 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3708
1439442c
SY		 3709 /* Access CR3 don't cause VMExit in paging mode, so we need
3710 * to sync with guest real CR3. */
6de4f3ad 3711 if (enable_ept && is_paging(vcpu))
1439442c 3712 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3713
5120702e
MG		 3714 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3715 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3716 vcpu->run->fail_entry.hardware_entry_failure_reason
3717 = exit_reason;
3718 return 0;
3719 }
3720
29bd8a78 3721 if (unlikely(vmx->fail)) {
851ba692
AK		 3722 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3723 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3724 = vmcs_read32(VM_INSTRUCTION_ERROR);
3725 return 0;
3726 }
6aa8b732 3727
d77c26fc 3728 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3729 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3730 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3731 exit_reason != EXIT_REASON_TASK_SWITCH))
3732 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3733 "(0x%x) and exit reason is 0x%x\n",
3734 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3735
3736 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3737 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3738 vmx->soft_vnmi_blocked = 0;
3b86cd99 3739 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3740 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3741 /*
3742 * This CPU don't support us in finding the end of an
3743 * NMI-blocked window if the guest runs with IRQs
3744 * disabled. So we pull the trigger after 1 s of
3745 * futile waiting, but inform the user about this.
3746 */
3747 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3748 "state on VCPU %d after 1 s timeout\n",
3749 __func__, vcpu->vcpu_id);
3750 vmx->soft_vnmi_blocked = 0;
3b86cd99 3751 }
3b86cd99
JK		 3752 }
3753
6aa8b732
AK		 3754 if (exit_reason < kvm_vmx_max_exit_handlers
3755 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3756 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3757 else {
851ba692
AK		 3758 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3759 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3760 }
3761 return 0;
3762}
3763
95ba8273 3764static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3765{
95ba8273 3766 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3767 vmcs_write32(TPR_THRESHOLD, 0);
3768 return;
3769 }
3770
95ba8273 3771 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3772}
3773
cf393f75
AK		 3774static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3775{
3776 u32 exit_intr_info;
7b4a25cb 3777 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3778 bool unblock_nmi;
3779 u8 vector;
668f612f
AK		 3780 int type;
3781 bool idtv_info_valid;
cf393f75
AK		 3782
3783 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3784
a0861c02
AK		 3785 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3786
3787 /* Handle machine checks before interrupts are enabled */
3788 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3789 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3790 && is_machine_check(exit_intr_info)))
3791 kvm_machine_check();
3792
20f65983
GN		 3793 /* We need to handle NMIs before interrupts are enabled */
3794 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3795 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3796 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3797 asm("int $2");
ff9d07a0
ZY		 3798 kvm_after_handle_nmi(&vmx->vcpu);
3799 }
20f65983
GN		 3800
3801 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3802
cf393f75
AK		 3803 if (cpu_has_virtual_nmis()) {
3804 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3805 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3806 /*
7b4a25cb 3807 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3808 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3809 * a guest IRET fault.
7b4a25cb
GN		 3810 * SDM 3: 23.2.2 (September 2008)
3811 * Bit 12 is undefined in any of the following cases:
3812 * If the VM exit sets the valid bit in the IDT-vectoring
3813 * information field.
3814 * If the VM exit is due to a double fault.
cf393f75 3815 */
7b4a25cb
GN		 3816 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3817 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3818 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3819 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3820 } else if (unlikely(vmx->soft_vnmi_blocked))
3821 vmx->vnmi_blocked_time +=
3822 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3823
37b96e98
GN		 3824 vmx->vcpu.arch.nmi_injected = false;
3825 kvm_clear_exception_queue(&vmx->vcpu);
3826 kvm_clear_interrupt_queue(&vmx->vcpu);
3827
3828 if (!idtv_info_valid)
3829 return;
3830
668f612f
AK		 3831 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3832 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3833
64a7ec06 3834 switch (type) {
37b96e98
GN		 3835 case INTR_TYPE_NMI_INTR:
3836 vmx->vcpu.arch.nmi_injected = true;
668f612f 3837 /*
7b4a25cb 3838 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3839 * Clear bit "block by NMI" before VM entry if a NMI
3840 * delivery faulted.
668f612f 3841 */
37b96e98
GN		 3842 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3843 GUEST_INTR_STATE_NMI);
3844 break;
37b96e98 3845 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3846 vmx->vcpu.arch.event_exit_inst_len =
3847 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3848 /* fall through */
3849 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3850 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3851 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3852 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3853 } else
3854 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3855 break;
66fd3f7f
GN		 3856 case INTR_TYPE_SOFT_INTR:
3857 vmx->vcpu.arch.event_exit_inst_len =
3858 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3859 /* fall through */
37b96e98 3860 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3861 kvm_queue_interrupt(&vmx->vcpu, vector,
3862 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3863 break;
3864 default:
3865 break;
f7d9238f 3866 }
cf393f75
AK		 3867}
3868
9c8cba37
AK		 3869/*
3870 * Failure to inject an interrupt should give us the information
3871 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3872 * when fetching the interrupt redirection bitmap in the real-mode
3873 * tss, this doesn't happen. So we do it ourselves.
3874 */
3875static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3876{
3877 vmx->rmode.irq.pending = 0;
5fdbf976 3878 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3879 return;
5fdbf976 3880 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3881 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3882 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3883 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3884 return;
3885 }
3886 vmx->idt_vectoring_info =
3887 VECTORING_INFO_VALID_MASK
3888 | INTR_TYPE_EXT_INTR
3889 | vmx->rmode.irq.vector;
3890}
3891
c801949d
AK		 3892#ifdef CONFIG_X86_64
3893#define R "r"
3894#define Q "q"
3895#else
3896#define R "e"
3897#define Q "l"
3898#endif
3899
851ba692 3900static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3901{
a2fa3e9f 3902 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3903
3b86cd99
JK		 3904 /* Record the guest's net vcpu time for enforced NMI injections. */
3905 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3906 vmx->entry_time = ktime_get();
3907
80ced186
MG		 3908 /* Don't enter VMX if guest state is invalid, let the exit handler
3909 start emulation until we arrive back to a valid state */
3910 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3911 return;
a89a8fb9 3912
5fdbf976
MT		 3913 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3914 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3915 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3916 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3917
787ff736
GN		 3918 /* When single-stepping over STI and MOV SS, we must clear the
3919 * corresponding interruptibility bits in the guest state. Otherwise
3920 * vmentry fails as it then expects bit 14 (BS) in pending debug
3921 * exceptions being set, but that's not correct for the guest debugging
3922 * case. */
3923 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3924 vmx_set_interrupt_shadow(vcpu, 0);
3925
d77c26fc 3926 asm(
6aa8b732 3927 /* Store host registers */
c801949d
AK		 3928 "push %%"R"dx; push %%"R"bp;"
3929 "push %%"R"cx \n\t"
313dbd49
AK		 3930 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3931 "je 1f \n\t"
3932 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3933 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3934 "1: \n\t"
d3edefc0
AK		 3935 /* Reload cr2 if changed */
3936 "mov %c[cr2](%0), %%"R"ax \n\t"
3937 "mov %%cr2, %%"R"dx \n\t"
3938 "cmp %%"R"ax, %%"R"dx \n\t"
3939 "je 2f \n\t"
3940 "mov %%"R"ax, %%cr2 \n\t"
3941 "2: \n\t"
6aa8b732 3942 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3943 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3944 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3945 "mov %c[rax](%0), %%"R"ax \n\t"
3946 "mov %c[rbx](%0), %%"R"bx \n\t"
3947 "mov %c[rdx](%0), %%"R"dx \n\t"
3948 "mov %c[rsi](%0), %%"R"si \n\t"
3949 "mov %c[rdi](%0), %%"R"di \n\t"
3950 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3951#ifdef CONFIG_X86_64
e08aa78a
AK		 3952 "mov %c[r8](%0), %%r8 \n\t"
3953 "mov %c[r9](%0), %%r9 \n\t"
3954 "mov %c[r10](%0), %%r10 \n\t"
3955 "mov %c[r11](%0), %%r11 \n\t"
3956 "mov %c[r12](%0), %%r12 \n\t"
3957 "mov %c[r13](%0), %%r13 \n\t"
3958 "mov %c[r14](%0), %%r14 \n\t"
3959 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3960#endif
c801949d
AK		 3961 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3962
6aa8b732 3963 /* Enter guest mode */
cd2276a7 3964 "jne .Llaunched \n\t"
4ecac3fd 3965 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3966 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3967 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3968 ".Lkvm_vmx_return: "
6aa8b732 3969 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3970 "xchg %0, (%%"R"sp) \n\t"
3971 "mov %%"R"ax, %c[rax](%0) \n\t"
3972 "mov %%"R"bx, %c[rbx](%0) \n\t"
3973 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3974 "mov %%"R"dx, %c[rdx](%0) \n\t"
3975 "mov %%"R"si, %c[rsi](%0) \n\t"
3976 "mov %%"R"di, %c[rdi](%0) \n\t"
3977 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3978#ifdef CONFIG_X86_64
e08aa78a
AK		 3979 "mov %%r8, %c[r8](%0) \n\t"
3980 "mov %%r9, %c[r9](%0) \n\t"
3981 "mov %%r10, %c[r10](%0) \n\t"
3982 "mov %%r11, %c[r11](%0) \n\t"
3983 "mov %%r12, %c[r12](%0) \n\t"
3984 "mov %%r13, %c[r13](%0) \n\t"
3985 "mov %%r14, %c[r14](%0) \n\t"
3986 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3987#endif
c801949d
AK		 3988 "mov %%cr2, %%"R"ax \n\t"
3989 "mov %%"R"ax, %c[cr2](%0) \n\t"
3990
3991 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3992 "setbe %c[fail](%0) \n\t"
3993 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3994 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3995 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3996 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3997 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3998 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3999 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4000 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4001 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4002 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4003 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4004#ifdef CONFIG_X86_64
ad312c7c
ZX		 4005 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4006 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4007 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4008 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4009 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4010 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4011 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4012 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4013#endif
ad312c7c 4014 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 4015 : "cc", "memory"
c801949d 4016 , R"bx", R"di", R"si"
c2036300 4017#ifdef CONFIG_X86_64
c2036300
LV		 4018 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4019#endif
4020 );
6aa8b732 4021
6de4f3ad
AK		 4022 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4023 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 4024 vcpu->arch.regs_dirty = 0;
4025
1155f76a 4026 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 4027 if (vmx->rmode.irq.pending)
4028 fixup_rmode_irq(vmx);
1155f76a 4029
d77c26fc 4030 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4031 vmx->launched = 1;
1b6269db 4032
cf393f75 4033 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4034}
4035
c801949d
AK		 4036#undef R
4037#undef Q
4038
6aa8b732
AK		 4039static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4040{
a2fa3e9f
GH		 4041 struct vcpu_vmx *vmx = to_vmx(vcpu);
4042
4043 if (vmx->vmcs) {
543e4243 4044 vcpu_clear(vmx);
a2fa3e9f
GH		 4045 free_vmcs(vmx->vmcs);
4046 vmx->vmcs = NULL;
6aa8b732
AK		 4047 }
4048}
4049
4050static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4051{
fb3f0f51
RR		 4052 struct vcpu_vmx *vmx = to_vmx(vcpu);
4053
cdbecfc3 4054 free_vpid(vmx);
6aa8b732 4055 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4056 kfree(vmx->guest_msrs);
4057 kvm_vcpu_uninit(vcpu);
a4770347 4058 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4059}
4060
4610c9cc
DX		 4061static inline void vmcs_init(struct vmcs *vmcs)
4062{
4063 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4064
4065 if (!vmm_exclusive)
4066 kvm_cpu_vmxon(phys_addr);
4067
4068 vmcs_clear(vmcs);
4069
4070 if (!vmm_exclusive)
4071 kvm_cpu_vmxoff();
4072}
4073
fb3f0f51 4074static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4075{
fb3f0f51 4076 int err;
c16f862d 4077 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4078 int cpu;
6aa8b732 4079
a2fa3e9f 4080 if (!vmx)
fb3f0f51
RR		 4081 return ERR_PTR(-ENOMEM);
4082
2384d2b3
SY		 4083 allocate_vpid(vmx);
4084
fb3f0f51
RR		 4085 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4086 if (err)
4087 goto free_vcpu;
965b58a5 4088
a2fa3e9f 4089 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4090 if (!vmx->guest_msrs) {
4091 err = -ENOMEM;
4092 goto uninit_vcpu;
4093 }
965b58a5 4094
a2fa3e9f
GH		 4095 vmx->vmcs = alloc_vmcs();
4096 if (!vmx->vmcs)
fb3f0f51 4097 goto free_msrs;
a2fa3e9f 4098
4610c9cc 4099 vmcs_init(vmx->vmcs);
a2fa3e9f 4100
15ad7146
AK		 4101 cpu = get_cpu();
4102 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 4103 vmx->vcpu.cpu = cpu;
8b9cf98c 4104 err = vmx_vcpu_setup(vmx);
fb3f0f51 4105 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4106 put_cpu();
fb3f0f51
RR		 4107 if (err)
4108 goto free_vmcs;
5e4a0b3c
MT		 4109 if (vm_need_virtualize_apic_accesses(kvm))
4110 if (alloc_apic_access_page(kvm) != 0)
4111 goto free_vmcs;
fb3f0f51 4112
b927a3ce
SY		 4113 if (enable_ept) {
4114 if (!kvm->arch.ept_identity_map_addr)
4115 kvm->arch.ept_identity_map_addr =
4116 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4117 if (alloc_identity_pagetable(kvm) != 0)
4118 goto free_vmcs;
b927a3ce 4119 }
b7ebfb05 4120
fb3f0f51
RR		 4121 return &vmx->vcpu;
4122
4123free_vmcs:
4124 free_vmcs(vmx->vmcs);
4125free_msrs:
fb3f0f51
RR		 4126 kfree(vmx->guest_msrs);
4127uninit_vcpu:
4128 kvm_vcpu_uninit(&vmx->vcpu);
4129free_vcpu:
cdbecfc3 4130 free_vpid(vmx);
a4770347 4131 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4132 return ERR_PTR(err);
6aa8b732
AK		 4133}
4134
002c7f7c
YS		 4135static void __init vmx_check_processor_compat(void *rtn)
4136{
4137 struct vmcs_config vmcs_conf;
4138
4139 *(int *)rtn = 0;
4140 if (setup_vmcs_config(&vmcs_conf) < 0)
4141 *(int *)rtn = -EIO;
4142 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4143 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4144 smp_processor_id());
4145 *(int *)rtn = -EIO;
4146 }
4147}
4148
67253af5
SY		 4149static int get_ept_level(void)
4150{
4151 return VMX_EPT_DEFAULT_GAW + 1;
4152}
4153
4b12f0de 4154static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4155{
4b12f0de
SY		 4156 u64 ret;
4157
522c68c4
SY		 4158 /* For VT-d and EPT combination
4159 * 1. MMIO: always map as UC
4160 * 2. EPT with VT-d:
4161 * a. VT-d without snooping control feature: can't guarantee the
4162 * result, try to trust guest.
4163 * b. VT-d with snooping control feature: snooping control feature of
4164 * VT-d engine can guarantee the cache correctness. Just set it
4165 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4166 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4167 * consistent with host MTRR
4168 */
4b12f0de
SY		 4169 if (is_mmio)
4170 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4171 else if (vcpu->kvm->arch.iommu_domain &&
4172 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4173 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4174 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4175 else
522c68c4 4176 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4177 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4178
4179 return ret;
64d4d521
SY		 4180}
4181
f4c9e87c
AK		 4182#define _ER(x) { EXIT_REASON_##x, #x }
4183
229456fc 4184static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4185 _ER(EXCEPTION_NMI),
4186 _ER(EXTERNAL_INTERRUPT),
4187 _ER(TRIPLE_FAULT),
4188 _ER(PENDING_INTERRUPT),
4189 _ER(NMI_WINDOW),
4190 _ER(TASK_SWITCH),
4191 _ER(CPUID),
4192 _ER(HLT),
4193 _ER(INVLPG),
4194 _ER(RDPMC),
4195 _ER(RDTSC),
4196 _ER(VMCALL),
4197 _ER(VMCLEAR),
4198 _ER(VMLAUNCH),
4199 _ER(VMPTRLD),
4200 _ER(VMPTRST),
4201 _ER(VMREAD),
4202 _ER(VMRESUME),
4203 _ER(VMWRITE),
4204 _ER(VMOFF),
4205 _ER(VMON),
4206 _ER(CR_ACCESS),
4207 _ER(DR_ACCESS),
4208 _ER(IO_INSTRUCTION),
4209 _ER(MSR_READ),
4210 _ER(MSR_WRITE),
4211 _ER(MWAIT_INSTRUCTION),
4212 _ER(MONITOR_INSTRUCTION),
4213 _ER(PAUSE_INSTRUCTION),
4214 _ER(MCE_DURING_VMENTRY),
4215 _ER(TPR_BELOW_THRESHOLD),
4216 _ER(APIC_ACCESS),
4217 _ER(EPT_VIOLATION),
4218 _ER(EPT_MISCONFIG),
4219 _ER(WBINVD),
229456fc
MT		 4220 { -1, NULL }
4221};
4222
f4c9e87c
AK		 4223#undef _ER
4224
17cc3935 4225static int vmx_get_lpage_level(void)
344f414f 4226{
878403b7
SY		 4227 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4228 return PT_DIRECTORY_LEVEL;
4229 else
4230 /* For shadow and EPT supported 1GB page */
4231 return PT_PDPE_LEVEL;
344f414f
JR		 4232}
4233
4e47c7a6
SY		 4234static inline u32 bit(int bitno)
4235{
4236 return 1 << (bitno & 31);
4237}
4238
0e851880
SY		 4239static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4240{
4e47c7a6
SY		 4241 struct kvm_cpuid_entry2 *best;
4242 struct vcpu_vmx *vmx = to_vmx(vcpu);
4243 u32 exec_control;
4244
4245 vmx->rdtscp_enabled = false;
4246 if (vmx_rdtscp_supported()) {
4247 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4248 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4249 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4250 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4251 vmx->rdtscp_enabled = true;
4252 else {
4253 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4254 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4255 exec_control);
4256 }
4257 }
4258 }
0e851880
SY		 4259}
4260
d4330ef2
JR		 4261static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4262{
4263}
4264
cbdd1bea 4265static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4266 .cpu_has_kvm_support = cpu_has_kvm_support,
4267 .disabled_by_bios = vmx_disabled_by_bios,
4268 .hardware_setup = hardware_setup,
4269 .hardware_unsetup = hardware_unsetup,
002c7f7c 4270 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4271 .hardware_enable = hardware_enable,
4272 .hardware_disable = hardware_disable,
04547156 4273 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4274
4275 .vcpu_create = vmx_create_vcpu,
4276 .vcpu_free = vmx_free_vcpu,
04d2cc77 4277 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4278
04d2cc77 4279 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4280 .vcpu_load = vmx_vcpu_load,
4281 .vcpu_put = vmx_vcpu_put,
4282
4283 .set_guest_debug = set_guest_debug,
4284 .get_msr = vmx_get_msr,
4285 .set_msr = vmx_set_msr,
4286 .get_segment_base = vmx_get_segment_base,
4287 .get_segment = vmx_get_segment,
4288 .set_segment = vmx_set_segment,
2e4d2653 4289 .get_cpl = vmx_get_cpl,
6aa8b732 4290 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4291 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4292 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4293 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4294 .set_cr3 = vmx_set_cr3,
4295 .set_cr4 = vmx_set_cr4,
6aa8b732 4296 .set_efer = vmx_set_efer,
6aa8b732
AK		 4297 .get_idt = vmx_get_idt,
4298 .set_idt = vmx_set_idt,
4299 .get_gdt = vmx_get_gdt,
4300 .set_gdt = vmx_set_gdt,
020df079 4301 .set_dr7 = vmx_set_dr7,
5fdbf976 4302 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4303 .get_rflags = vmx_get_rflags,
4304 .set_rflags = vmx_set_rflags,
ebcbab4c 4305 .fpu_activate = vmx_fpu_activate,
02daab21 4306 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4307
4308 .tlb_flush = vmx_flush_tlb,
6aa8b732 4309
6aa8b732 4310 .run = vmx_vcpu_run,
6062d012 4311 .handle_exit = vmx_handle_exit,
6aa8b732 4312 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4313 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4314 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4315 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4316 .set_irq = vmx_inject_irq,
95ba8273 4317 .set_nmi = vmx_inject_nmi,
298101da 4318 .queue_exception = vmx_queue_exception,
78646121 4319 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4320 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4321 .get_nmi_mask = vmx_get_nmi_mask,
4322 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4323 .enable_nmi_window = enable_nmi_window,
4324 .enable_irq_window = enable_irq_window,
4325 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4326
cbc94022 4327 .set_tss_addr = vmx_set_tss_addr,
67253af5 4328 .get_tdp_level = get_ept_level,
4b12f0de 4329 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4330
4331 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4332 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4333
4334 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4335
4336 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4337
4338 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4339
4340 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA		 4341
4342 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 4343 .adjust_tsc_offset = vmx_adjust_tsc_offset,
1c97f0a0
JR		 4344
4345 .set_tdp_cr3 = vmx_set_cr3,
6aa8b732
AK		 4346};
4347
4348static int __init vmx_init(void)
4349{
26bb0981
AK		 4350 int r, i;
4351
4352 rdmsrl_safe(MSR_EFER, &host_efer);
4353
4354 for (i = 0; i < NR_VMX_MSR; ++i)
4355 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4356
3e7c73e9 4357 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4358 if (!vmx_io_bitmap_a)
4359 return -ENOMEM;
4360
3e7c73e9 4361 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4362 if (!vmx_io_bitmap_b) {
4363 r = -ENOMEM;
4364 goto out;
4365 }
4366
5897297b
AK		 4367 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4368 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4369 r = -ENOMEM;
4370 goto out1;
4371 }
4372
5897297b
AK		 4373 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4374 if (!vmx_msr_bitmap_longmode) {
4375 r = -ENOMEM;
4376 goto out2;
4377 }
4378
fdef3ad1
HQ		 4379 /*
4380 * Allow direct access to the PC debug port (it is often used for I/O
4381 * delays, but the vmexits simply slow things down).
4382 */
3e7c73e9
AK		 4383 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4384 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4385
3e7c73e9 4386 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4387
5897297b
AK		 4388 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4389 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4390
2384d2b3
SY		 4391 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4392
0ee75bea
AK		 4393 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4394 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4395 if (r)
5897297b 4396 goto out3;
25c5f225 4397
5897297b
AK		 4398 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4399 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4400 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4401 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4402 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4403 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4404
089d034e 4405 if (enable_ept) {
1439442c 4406 bypass_guest_pf = 0;
5fdbcb9d 4407 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4408 VMX_EPT_WRITABLE_MASK);
534e38b4 4409 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4410 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4411 kvm_enable_tdp();
4412 } else
4413 kvm_disable_tdp();
1439442c 4414
c7addb90
AK		 4415 if (bypass_guest_pf)
4416 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4417
fdef3ad1
HQ		 4418 return 0;
4419
5897297b
AK		 4420out3:
4421 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4422out2:
5897297b 4423 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4424out1:
3e7c73e9 4425 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4426out:
3e7c73e9 4427 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4428 return r;
6aa8b732
AK		 4429}
4430
4431static void __exit vmx_exit(void)
4432{
5897297b
AK		 4433 free_page((unsigned long)vmx_msr_bitmap_legacy);
4434 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4435 free_page((unsigned long)vmx_io_bitmap_b);
4436 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4437
cb498ea2 4438 kvm_exit();
6aa8b732
AK		 4439}
4440
4441module_init(vmx_init)
4442module_exit(vmx_exit)
Ubuntu Artful kernel mirror