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KVM: Add Documentation/kvm/msr.txt
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
221d059d 8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
6aa8b732 40
229456fc
MT		 41#include "trace.h"
42
4ecac3fd
AK		 43#define __ex(x) __kvm_handle_fault_on_reboot(x)
44
6aa8b732
AK		 45MODULE_AUTHOR("Qumranet");
46MODULE_LICENSE("GPL");
47
4462d21a 48static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 49module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 50
4462d21a 51static int __read_mostly enable_vpid = 1;
736caefe 52module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 53
4462d21a 54static int __read_mostly flexpriority_enabled = 1;
736caefe 55module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 56
4462d21a 57static int __read_mostly enable_ept = 1;
736caefe 58module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 59
3a624e29
NK		 60static int __read_mostly enable_unrestricted_guest = 1;
61module_param_named(unrestricted_guest,
62 enable_unrestricted_guest, bool, S_IRUGO);
63
4462d21a 64static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 65module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 66
b923e62e
DX		 67static int __read_mostly vmm_exclusive = 1;
68module_param(vmm_exclusive, bool, S_IRUGO);
69
cdc0e244
AK		 70#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
71 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
72#define KVM_GUEST_CR0_MASK \
73 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
74#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 75 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 76#define KVM_VM_CR0_ALWAYS_ON \
77 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 78#define KVM_CR4_GUEST_OWNED_BITS \
79 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
80 | X86_CR4_OSXMMEXCPT)
81
cdc0e244
AK		 82#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
83#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
84
78ac8b47
AK		 85#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
86
4b8d54f9
ZE		 87/*
88 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
89 * ple_gap: upper bound on the amount of time between two successive
90 * executions of PAUSE in a loop. Also indicate if ple enabled.
91 * According to test, this time is usually small than 41 cycles.
92 * ple_window: upper bound on the amount of time a guest is allowed to execute
93 * in a PAUSE loop. Tests indicate that most spinlocks are held for
94 * less than 2^12 cycles
95 * Time is measured based on a counter that runs at the same rate as the TSC,
96 * refer SDM volume 3b section 21.6.13 & 22.1.3.
97 */
98#define KVM_VMX_DEFAULT_PLE_GAP 41
99#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
100static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
101module_param(ple_gap, int, S_IRUGO);
102
103static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
104module_param(ple_window, int, S_IRUGO);
105
61d2ef2c
AK		 106#define NR_AUTOLOAD_MSRS 1
107
a2fa3e9f
GH		 108struct vmcs {
109 u32 revision_id;
110 u32 abort;
111 char data[0];
112};
113
26bb0981
AK		 114struct shared_msr_entry {
115 unsigned index;
116 u64 data;
d5696725 117 u64 mask;
26bb0981
AK		 118};
119
a2fa3e9f 120struct vcpu_vmx {
fb3f0f51 121 struct kvm_vcpu vcpu;
543e4243 122 struct list_head local_vcpus_link;
313dbd49 123 unsigned long host_rsp;
a2fa3e9f 124 int launched;
29bd8a78 125 u8 fail;
1155f76a 126 u32 idt_vectoring_info;
26bb0981 127 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 128 int nmsrs;
129 int save_nmsrs;
a2fa3e9f 130#ifdef CONFIG_X86_64
44ea2b17
AK		 131 u64 msr_host_kernel_gs_base;
132 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 133#endif
134 struct vmcs *vmcs;
61d2ef2c
AK		 135 struct msr_autoload {
136 unsigned nr;
137 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
138 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
139 } msr_autoload;
a2fa3e9f
GH		 140 struct {
141 int loaded;
142 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 143 int gs_ldt_reload_needed;
144 int fs_reload_needed;
d77c26fc 145 } host_state;
9c8cba37 146 struct {
7ffd92c5 147 int vm86_active;
78ac8b47 148 ulong save_rflags;
7ffd92c5
AK		 149 struct kvm_save_segment {
150 u16 selector;
151 unsigned long base;
152 u32 limit;
153 u32 ar;
154 } tr, es, ds, fs, gs;
9c8cba37
AK		 155 struct {
156 bool pending;
157 u8 vector;
158 unsigned rip;
159 } irq;
160 } rmode;
2384d2b3 161 int vpid;
04fa4d32 162 bool emulation_required;
3b86cd99
JK		 163
164 /* Support for vnmi-less CPUs */
165 int soft_vnmi_blocked;
166 ktime_t entry_time;
167 s64 vnmi_blocked_time;
a0861c02 168 u32 exit_reason;
4e47c7a6
SY		 169
170 bool rdtscp_enabled;
a2fa3e9f
GH		 171};
172
173static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
174{
fb3f0f51 175 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 176}
177
b7ebfb05 178static int init_rmode(struct kvm *kvm);
4e1096d2 179static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 180static void kvm_cpu_vmxon(u64 addr);
181static void kvm_cpu_vmxoff(void);
75880a01 182
6aa8b732
AK		 183static DEFINE_PER_CPU(struct vmcs *, vmxarea);
184static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 185static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 186
3e7c73e9
AK		 187static unsigned long *vmx_io_bitmap_a;
188static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 189static unsigned long *vmx_msr_bitmap_legacy;
190static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 191
2384d2b3
SY		 192static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
193static DEFINE_SPINLOCK(vmx_vpid_lock);
194
1c3d14fe 195static struct vmcs_config {
6aa8b732
AK		 196 int size;
197 int order;
198 u32 revision_id;
1c3d14fe
YS		 199 u32 pin_based_exec_ctrl;
200 u32 cpu_based_exec_ctrl;
f78e0e2e 201 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 202 u32 vmexit_ctrl;
203 u32 vmentry_ctrl;
204} vmcs_config;
6aa8b732 205
efff9e53 206static struct vmx_capability {
d56f546d
SY		 207 u32 ept;
208 u32 vpid;
209} vmx_capability;
210
6aa8b732
AK		 211#define VMX_SEGMENT_FIELD(seg) \
212 [VCPU_SREG_##seg] = { \
213 .selector = GUEST_##seg##_SELECTOR, \
214 .base = GUEST_##seg##_BASE, \
215 .limit = GUEST_##seg##_LIMIT, \
216 .ar_bytes = GUEST_##seg##_AR_BYTES, \
217 }
218
219static struct kvm_vmx_segment_field {
220 unsigned selector;
221 unsigned base;
222 unsigned limit;
223 unsigned ar_bytes;
224} kvm_vmx_segment_fields[] = {
225 VMX_SEGMENT_FIELD(CS),
226 VMX_SEGMENT_FIELD(DS),
227 VMX_SEGMENT_FIELD(ES),
228 VMX_SEGMENT_FIELD(FS),
229 VMX_SEGMENT_FIELD(GS),
230 VMX_SEGMENT_FIELD(SS),
231 VMX_SEGMENT_FIELD(TR),
232 VMX_SEGMENT_FIELD(LDTR),
233};
234
26bb0981
AK		 235static u64 host_efer;
236
6de4f3ad
AK		 237static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
238
4d56c8a7
AK		 239/*
240 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
241 * away by decrementing the array size.
242 */
6aa8b732 243static const u32 vmx_msr_index[] = {
05b3e0c2 244#ifdef CONFIG_X86_64
44ea2b17 245 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 246#endif
4e47c7a6 247 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
6aa8b732 248};
9d8f549d 249#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 250
31299944 251static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 252{
253 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
254 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 255 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 256}
257
31299944 258static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 259{
260 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
261 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 262 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 263}
264
31299944 265static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 266{
267 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
268 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 269 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 270}
271
31299944 272static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 273{
274 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
275 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
276}
277
31299944 278static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 279{
280 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
281 INTR_INFO_VALID_MASK)) ==
282 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
283}
284
31299944 285static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 286{
04547156 287 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 288}
289
31299944 290static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 291{
04547156 292 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 293}
294
31299944 295static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 296{
04547156 297 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 298}
299
31299944 300static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 301{
04547156
SY		 302 return vmcs_config.cpu_based_exec_ctrl &
303 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 304}
305
774ead3a 306static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 307{
04547156
SY		 308 return vmcs_config.cpu_based_2nd_exec_ctrl &
309 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
310}
311
312static inline bool cpu_has_vmx_flexpriority(void)
313{
314 return cpu_has_vmx_tpr_shadow() &&
315 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 316}
317
e799794e
MT		 318static inline bool cpu_has_vmx_ept_execute_only(void)
319{
31299944 320 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 321}
322
323static inline bool cpu_has_vmx_eptp_uncacheable(void)
324{
31299944 325 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 326}
327
328static inline bool cpu_has_vmx_eptp_writeback(void)
329{
31299944 330 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 331}
332
333static inline bool cpu_has_vmx_ept_2m_page(void)
334{
31299944 335 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 336}
337
878403b7
SY		 338static inline bool cpu_has_vmx_ept_1g_page(void)
339{
31299944 340 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 341}
342
31299944 343static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 344{
31299944 345 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 346}
347
31299944 348static inline bool cpu_has_vmx_invept_context(void)
d56f546d 349{
31299944 350 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 351}
352
31299944 353static inline bool cpu_has_vmx_invept_global(void)
d56f546d 354{
31299944 355 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 356}
357
31299944 358static inline bool cpu_has_vmx_ept(void)
d56f546d 359{
04547156
SY		 360 return vmcs_config.cpu_based_2nd_exec_ctrl &
361 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 362}
363
31299944 364static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 365{
366 return vmcs_config.cpu_based_2nd_exec_ctrl &
367 SECONDARY_EXEC_UNRESTRICTED_GUEST;
368}
369
31299944 370static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 371{
372 return vmcs_config.cpu_based_2nd_exec_ctrl &
373 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
374}
375
31299944 376static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 377{
6d3e435e 378 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 379}
380
31299944 381static inline bool cpu_has_vmx_vpid(void)
2384d2b3 382{
04547156
SY		 383 return vmcs_config.cpu_based_2nd_exec_ctrl &
384 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 385}
386
31299944 387static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 388{
389 return vmcs_config.cpu_based_2nd_exec_ctrl &
390 SECONDARY_EXEC_RDTSCP;
391}
392
31299944 393static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 394{
395 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
396}
397
04547156
SY		 398static inline bool report_flexpriority(void)
399{
400 return flexpriority_enabled;
401}
402
8b9cf98c 403static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 404{
405 int i;
406
a2fa3e9f 407 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 408 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 409 return i;
410 return -1;
411}
412
2384d2b3
SY		 413static inline void __invvpid(int ext, u16 vpid, gva_t gva)
414{
415 struct {
416 u64 vpid : 16;
417 u64 rsvd : 48;
418 u64 gva;
419 } operand = { vpid, 0, gva };
420
4ecac3fd 421 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 422 /* CF==1 or ZF==1 --> rc = -1 */
423 "; ja 1f ; ud2 ; 1:"
424 : : "a"(&operand), "c"(ext) : "cc", "memory");
425}
426
1439442c
SY		 427static inline void __invept(int ext, u64 eptp, gpa_t gpa)
428{
429 struct {
430 u64 eptp, gpa;
431 } operand = {eptp, gpa};
432
4ecac3fd 433 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 434 /* CF==1 or ZF==1 --> rc = -1 */
435 "; ja 1f ; ud2 ; 1:\n"
436 : : "a" (&operand), "c" (ext) : "cc", "memory");
437}
438
26bb0981 439static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 440{
441 int i;
442
8b9cf98c 443 i = __find_msr_index(vmx, msr);
a75beee6 444 if (i >= 0)
a2fa3e9f 445 return &vmx->guest_msrs[i];
8b6d44c7 446 return NULL;
7725f0ba
AK		 447}
448
6aa8b732
AK		 449static void vmcs_clear(struct vmcs *vmcs)
450{
451 u64 phys_addr = __pa(vmcs);
452 u8 error;
453
4ecac3fd 454 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 455 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
456 : "cc", "memory");
457 if (error)
458 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
459 vmcs, phys_addr);
460}
461
7725b894
DX		 462static void vmcs_load(struct vmcs *vmcs)
463{
464 u64 phys_addr = __pa(vmcs);
465 u8 error;
466
467 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
468 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
469 : "cc", "memory");
470 if (error)
471 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
472 vmcs, phys_addr);
473}
474
6aa8b732
AK		 475static void __vcpu_clear(void *arg)
476{
8b9cf98c 477 struct vcpu_vmx *vmx = arg;
d3b2c338 478 int cpu = raw_smp_processor_id();
6aa8b732 479
8b9cf98c 480 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 481 vmcs_clear(vmx->vmcs);
482 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 483 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 484 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 485 list_del(&vmx->local_vcpus_link);
486 vmx->vcpu.cpu = -1;
487 vmx->launched = 0;
6aa8b732
AK		 488}
489
8b9cf98c 490static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 491{
eae5ecb5
AK		 492 if (vmx->vcpu.cpu == -1)
493 return;
8691e5a8 494 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 495}
496
2384d2b3
SY		 497static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
498{
499 if (vmx->vpid == 0)
500 return;
501
502 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
503}
504
1439442c
SY		 505static inline void ept_sync_global(void)
506{
507 if (cpu_has_vmx_invept_global())
508 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
509}
510
511static inline void ept_sync_context(u64 eptp)
512{
089d034e 513 if (enable_ept) {
1439442c
SY		 514 if (cpu_has_vmx_invept_context())
515 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
516 else
517 ept_sync_global();
518 }
519}
520
521static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
522{
089d034e 523 if (enable_ept) {
1439442c
SY		 524 if (cpu_has_vmx_invept_individual_addr())
525 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
526 eptp, gpa);
527 else
528 ept_sync_context(eptp);
529 }
530}
531
6aa8b732
AK		 532static unsigned long vmcs_readl(unsigned long field)
533{
534 unsigned long value;
535
4ecac3fd 536 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 537 : "=a"(value) : "d"(field) : "cc");
538 return value;
539}
540
541static u16 vmcs_read16(unsigned long field)
542{
543 return vmcs_readl(field);
544}
545
546static u32 vmcs_read32(unsigned long field)
547{
548 return vmcs_readl(field);
549}
550
551static u64 vmcs_read64(unsigned long field)
552{
05b3e0c2 553#ifdef CONFIG_X86_64
6aa8b732
AK		 554 return vmcs_readl(field);
555#else
556 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
557#endif
558}
559
e52de1b8
AK		 560static noinline void vmwrite_error(unsigned long field, unsigned long value)
561{
562 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
563 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
564 dump_stack();
565}
566
6aa8b732
AK		 567static void vmcs_writel(unsigned long field, unsigned long value)
568{
569 u8 error;
570
4ecac3fd 571 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 572 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 573 if (unlikely(error))
574 vmwrite_error(field, value);
6aa8b732
AK		 575}
576
577static void vmcs_write16(unsigned long field, u16 value)
578{
579 vmcs_writel(field, value);
580}
581
582static void vmcs_write32(unsigned long field, u32 value)
583{
584 vmcs_writel(field, value);
585}
586
587static void vmcs_write64(unsigned long field, u64 value)
588{
6aa8b732 589 vmcs_writel(field, value);
7682f2d0 590#ifndef CONFIG_X86_64
6aa8b732
AK		 591 asm volatile ("");
592 vmcs_writel(field+1, value >> 32);
593#endif
594}
595
2ab455cc
AL		 596static void vmcs_clear_bits(unsigned long field, u32 mask)
597{
598 vmcs_writel(field, vmcs_readl(field) & ~mask);
599}
600
601static void vmcs_set_bits(unsigned long field, u32 mask)
602{
603 vmcs_writel(field, vmcs_readl(field) | mask);
604}
605
abd3f2d6
AK		 606static void update_exception_bitmap(struct kvm_vcpu *vcpu)
607{
608 u32 eb;
609
fd7373cc
JK		 610 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
611 (1u << NM_VECTOR) | (1u << DB_VECTOR);
612 if ((vcpu->guest_debug &
613 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
614 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
615 eb |= 1u << BP_VECTOR;
7ffd92c5 616 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 617 eb = ~0;
089d034e 618 if (enable_ept)
1439442c 619 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 620 if (vcpu->fpu_active)
621 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 622 vmcs_write32(EXCEPTION_BITMAP, eb);
623}
624
61d2ef2c
AK		 625static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
626{
627 unsigned i;
628 struct msr_autoload *m = &vmx->msr_autoload;
629
630 for (i = 0; i < m->nr; ++i)
631 if (m->guest[i].index == msr)
632 break;
633
634 if (i == m->nr)
635 return;
636 --m->nr;
637 m->guest[i] = m->guest[m->nr];
638 m->host[i] = m->host[m->nr];
639 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
640 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
641}
642
643static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
644 u64 guest_val, u64 host_val)
645{
646 unsigned i;
647 struct msr_autoload *m = &vmx->msr_autoload;
648
649 for (i = 0; i < m->nr; ++i)
650 if (m->guest[i].index == msr)
651 break;
652
653 if (i == m->nr) {
654 ++m->nr;
655 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
656 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
657 }
658
659 m->guest[i].index = msr;
660 m->guest[i].value = guest_val;
661 m->host[i].index = msr;
662 m->host[i].value = host_val;
663}
664
33ed6329
AK		 665static void reload_tss(void)
666{
33ed6329
AK		 667 /*
668 * VT restores TR but not its size. Useless.
669 */
89a27f4d 670 struct desc_ptr gdt;
a5f61300 671 struct desc_struct *descs;
33ed6329 672
d6ab1ed4 673 native_store_gdt(&gdt);
89a27f4d 674 descs = (void *)gdt.address;
33ed6329
AK		 675 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
676 load_TR_desc();
33ed6329
AK		 677}
678
92c0d900 679static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 680{
3a34a881 681 u64 guest_efer;
51c6cf66
AK		 682 u64 ignore_bits;
683
f6801dff 684 guest_efer = vmx->vcpu.arch.efer;
3a34a881 685
51c6cf66
AK		 686 /*
687 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
688 * outside long mode
689 */
690 ignore_bits = EFER_NX | EFER_SCE;
691#ifdef CONFIG_X86_64
692 ignore_bits |= EFER_LMA | EFER_LME;
693 /* SCE is meaningful only in long mode on Intel */
694 if (guest_efer & EFER_LMA)
695 ignore_bits &= ~(u64)EFER_SCE;
696#endif
51c6cf66
AK		 697 guest_efer &= ~ignore_bits;
698 guest_efer |= host_efer & ignore_bits;
26bb0981 699 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 700 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 701
702 clear_atomic_switch_msr(vmx, MSR_EFER);
703 /* On ept, can't emulate nx, and must switch nx atomically */
704 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
705 guest_efer = vmx->vcpu.arch.efer;
706 if (!(guest_efer & EFER_LMA))
707 guest_efer &= ~EFER_LME;
708 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
709 return false;
710 }
711
26bb0981 712 return true;
51c6cf66
AK		 713}
714
2d49ec72
GN		 715static unsigned long segment_base(u16 selector)
716{
717 struct desc_ptr gdt;
718 struct desc_struct *d;
719 unsigned long table_base;
720 unsigned long v;
721
722 if (!(selector & ~3))
723 return 0;
724
725 native_store_gdt(&gdt);
726 table_base = gdt.address;
727
728 if (selector & 4) { /* from ldt */
729 u16 ldt_selector = kvm_read_ldt();
730
731 if (!(ldt_selector & ~3))
732 return 0;
733
734 table_base = segment_base(ldt_selector);
735 }
736 d = (struct desc_struct *)(table_base + (selector & ~7));
737 v = get_desc_base(d);
738#ifdef CONFIG_X86_64
739 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
740 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
741#endif
742 return v;
743}
744
745static inline unsigned long kvm_read_tr_base(void)
746{
747 u16 tr;
748 asm("str %0" : "=g"(tr));
749 return segment_base(tr);
750}
751
04d2cc77 752static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 753{
04d2cc77 754 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 755 int i;
04d2cc77 756
a2fa3e9f 757 if (vmx->host_state.loaded)
33ed6329
AK		 758 return;
759
a2fa3e9f 760 vmx->host_state.loaded = 1;
33ed6329
AK		 761 /*
762 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
763 * allow segment selectors with cpl > 0 or ti == 1.
764 */
d6e88aec 765 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 766 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 767 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 768 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 769 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 770 vmx->host_state.fs_reload_needed = 0;
771 } else {
33ed6329 772 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 773 vmx->host_state.fs_reload_needed = 1;
33ed6329 774 }
d6e88aec 775 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 776 if (!(vmx->host_state.gs_sel & 7))
777 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 778 else {
779 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 780 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 781 }
782
783#ifdef CONFIG_X86_64
784 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
785 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
786#else
a2fa3e9f
GH		 787 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
788 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 789#endif
707c0874
AK		 790
791#ifdef CONFIG_X86_64
44ea2b17
AK		 792 if (is_long_mode(&vmx->vcpu)) {
793 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
794 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
795 }
707c0874 796#endif
26bb0981
AK		 797 for (i = 0; i < vmx->save_nmsrs; ++i)
798 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 799 vmx->guest_msrs[i].data,
800 vmx->guest_msrs[i].mask);
33ed6329
AK		 801}
802
a9b21b62 803static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 804{
15ad7146 805 unsigned long flags;
33ed6329 806
a2fa3e9f 807 if (!vmx->host_state.loaded)
33ed6329
AK		 808 return;
809
e1beb1d3 810 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 811 vmx->host_state.loaded = 0;
152d3f2f 812 if (vmx->host_state.fs_reload_needed)
d6e88aec 813 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 814 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 815 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 816 /*
817 * If we have to reload gs, we must take care to
818 * preserve our gs base.
819 */
15ad7146 820 local_irq_save(flags);
d6e88aec 821 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 822#ifdef CONFIG_X86_64
823 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
824#endif
15ad7146 825 local_irq_restore(flags);
33ed6329 826 }
152d3f2f 827 reload_tss();
44ea2b17
AK		 828#ifdef CONFIG_X86_64
829 if (is_long_mode(&vmx->vcpu)) {
830 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
831 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
832 }
833#endif
1c11e713
AK		 834 if (current_thread_info()->status & TS_USEDFPU)
835 clts();
33ed6329
AK		 836}
837
a9b21b62
AK		 838static void vmx_load_host_state(struct vcpu_vmx *vmx)
839{
840 preempt_disable();
841 __vmx_load_host_state(vmx);
842 preempt_enable();
843}
844
6aa8b732
AK		 845/*
846 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
847 * vcpu mutex is already taken.
848 */
15ad7146 849static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 850{
a2fa3e9f 851 struct vcpu_vmx *vmx = to_vmx(vcpu);
019960ae 852 u64 tsc_this, delta, new_offset;
4610c9cc 853 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 854
4610c9cc
DX		 855 if (!vmm_exclusive)
856 kvm_cpu_vmxon(phys_addr);
857 else if (vcpu->cpu != cpu)
8b9cf98c 858 vcpu_clear(vmx);
6aa8b732 859
a2fa3e9f 860 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 861 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 862 vmcs_load(vmx->vmcs);
6aa8b732
AK		 863 }
864
865 if (vcpu->cpu != cpu) {
89a27f4d 866 struct desc_ptr dt;
6aa8b732
AK		 867 unsigned long sysenter_esp;
868
92fe13be
DX		 869 kvm_migrate_timers(vcpu);
870 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
871 local_irq_disable();
872 list_add(&vmx->local_vcpus_link,
873 &per_cpu(vcpus_on_cpu, cpu));
874 local_irq_enable();
875
6aa8b732
AK		 876 vcpu->cpu = cpu;
877 /*
878 * Linux uses per-cpu TSS and GDT, so set these when switching
879 * processors.
880 */
d6e88aec 881 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d6ab1ed4 882 native_store_gdt(&dt);
89a27f4d 883 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732
AK		 884
885 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
886 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 887
888 /*
889 * Make sure the time stamp counter is monotonous.
890 */
891 rdtscll(tsc_this);
019960ae
AK		 892 if (tsc_this < vcpu->arch.host_tsc) {
893 delta = vcpu->arch.host_tsc - tsc_this;
894 new_offset = vmcs_read64(TSC_OFFSET) + delta;
895 vmcs_write64(TSC_OFFSET, new_offset);
896 }
6aa8b732 897 }
6aa8b732
AK		 898}
899
900static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
901{
a9b21b62 902 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 903 if (!vmm_exclusive) {
b923e62e 904 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 905 kvm_cpu_vmxoff();
906 }
6aa8b732
AK		 907}
908
5fd86fcf
AK		 909static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
910{
81231c69
AK		 911 ulong cr0;
912
5fd86fcf
AK		 913 if (vcpu->fpu_active)
914 return;
915 vcpu->fpu_active = 1;
81231c69
AK		 916 cr0 = vmcs_readl(GUEST_CR0);
917 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
918 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
919 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 920 update_exception_bitmap(vcpu);
edcafe3c
AK		 921 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
922 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 923}
924
edcafe3c
AK		 925static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
926
5fd86fcf
AK		 927static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
928{
edcafe3c 929 vmx_decache_cr0_guest_bits(vcpu);
81231c69 930 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 931 update_exception_bitmap(vcpu);
edcafe3c
AK		 932 vcpu->arch.cr0_guest_owned_bits = 0;
933 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
934 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 935}
936
6aa8b732
AK		 937static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
938{
78ac8b47 939 unsigned long rflags, save_rflags;
345dcaa8
AK		 940
941 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 942 if (to_vmx(vcpu)->rmode.vm86_active) {
943 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
944 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
945 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
946 }
345dcaa8 947 return rflags;
6aa8b732
AK		 948}
949
950static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
951{
78ac8b47
AK		 952 if (to_vmx(vcpu)->rmode.vm86_active) {
953 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 954 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 955 }
6aa8b732
AK		 956 vmcs_writel(GUEST_RFLAGS, rflags);
957}
958
2809f5d2
GC		 959static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
960{
961 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
962 int ret = 0;
963
964 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 965 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 966 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 967 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 968
969 return ret & mask;
970}
971
972static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
973{
974 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
975 u32 interruptibility = interruptibility_old;
976
977 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
978
48005f64 979 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 980 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 981 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 982 interruptibility |= GUEST_INTR_STATE_STI;
983
984 if ((interruptibility != interruptibility_old))
985 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
986}
987
6aa8b732
AK		 988static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
989{
990 unsigned long rip;
6aa8b732 991
5fdbf976 992 rip = kvm_rip_read(vcpu);
6aa8b732 993 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 994 kvm_rip_write(vcpu, rip);
6aa8b732 995
2809f5d2
GC		 996 /* skipping an emulated instruction also counts */
997 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 998}
999
298101da 1000static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1001 bool has_error_code, u32 error_code,
1002 bool reinject)
298101da 1003{
77ab6db0 1004 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1005 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1006
8ab2d2e2 1007 if (has_error_code) {
77ab6db0 1008 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1009 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1010 }
77ab6db0 1011
7ffd92c5 1012 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 1013 vmx->rmode.irq.pending = true;
1014 vmx->rmode.irq.vector = nr;
1015 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 1016 if (kvm_exception_is_soft(nr))
1017 vmx->rmode.irq.rip +=
1018 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 1019 intr_info |= INTR_TYPE_SOFT_INTR;
1020 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 1021 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1022 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1023 return;
1024 }
1025
66fd3f7f
GN		 1026 if (kvm_exception_is_soft(nr)) {
1027 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1028 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1029 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1030 } else
1031 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1032
1033 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1034}
1035
4e47c7a6
SY		 1036static bool vmx_rdtscp_supported(void)
1037{
1038 return cpu_has_vmx_rdtscp();
1039}
1040
a75beee6
ED		 1041/*
1042 * Swap MSR entry in host/guest MSR entry array.
1043 */
8b9cf98c 1044static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1045{
26bb0981 1046 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1047
1048 tmp = vmx->guest_msrs[to];
1049 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1050 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1051}
1052
e38aea3e
AK		 1053/*
1054 * Set up the vmcs to automatically save and restore system
1055 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1056 * mode, as fiddling with msrs is very expensive.
1057 */
8b9cf98c 1058static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1059{
26bb0981 1060 int save_nmsrs, index;
5897297b 1061 unsigned long *msr_bitmap;
e38aea3e 1062
33f9c505 1063 vmx_load_host_state(vmx);
a75beee6
ED		 1064 save_nmsrs = 0;
1065#ifdef CONFIG_X86_64
8b9cf98c 1066 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1067 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1068 if (index >= 0)
8b9cf98c
RR		 1069 move_msr_up(vmx, index, save_nmsrs++);
1070 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1071 if (index >= 0)
8b9cf98c
RR		 1072 move_msr_up(vmx, index, save_nmsrs++);
1073 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1074 if (index >= 0)
8b9cf98c 1075 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1076 index = __find_msr_index(vmx, MSR_TSC_AUX);
1077 if (index >= 0 && vmx->rdtscp_enabled)
1078 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1079 /*
1080 * MSR_K6_STAR is only needed on long mode guests, and only
1081 * if efer.sce is enabled.
1082 */
8b9cf98c 1083 index = __find_msr_index(vmx, MSR_K6_STAR);
f6801dff 1084 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1085 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1086 }
1087#endif
92c0d900
AK		 1088 index = __find_msr_index(vmx, MSR_EFER);
1089 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1090 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1091
26bb0981 1092 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1093
1094 if (cpu_has_vmx_msr_bitmap()) {
1095 if (is_long_mode(&vmx->vcpu))
1096 msr_bitmap = vmx_msr_bitmap_longmode;
1097 else
1098 msr_bitmap = vmx_msr_bitmap_legacy;
1099
1100 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1101 }
e38aea3e
AK		 1102}
1103
6aa8b732
AK		 1104/*
1105 * reads and returns guest's timestamp counter "register"
1106 * guest_tsc = host_tsc + tsc_offset -- 21.3
1107 */
1108static u64 guest_read_tsc(void)
1109{
1110 u64 host_tsc, tsc_offset;
1111
1112 rdtscll(host_tsc);
1113 tsc_offset = vmcs_read64(TSC_OFFSET);
1114 return host_tsc + tsc_offset;
1115}
1116
1117/*
1118 * writes 'guest_tsc' into guest's timestamp counter "register"
1119 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1120 */
53f658b3 1121static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 1122{
6aa8b732
AK		 1123 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1124}
1125
6aa8b732
AK		 1126/*
1127 * Reads an msr value (of 'msr_index') into 'pdata'.
1128 * Returns 0 on success, non-0 otherwise.
1129 * Assumes vcpu_load() was already called.
1130 */
1131static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1132{
1133 u64 data;
26bb0981 1134 struct shared_msr_entry *msr;
6aa8b732
AK		 1135
1136 if (!pdata) {
1137 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1138 return -EINVAL;
1139 }
1140
1141 switch (msr_index) {
05b3e0c2 1142#ifdef CONFIG_X86_64
6aa8b732
AK		 1143 case MSR_FS_BASE:
1144 data = vmcs_readl(GUEST_FS_BASE);
1145 break;
1146 case MSR_GS_BASE:
1147 data = vmcs_readl(GUEST_GS_BASE);
1148 break;
44ea2b17
AK		 1149 case MSR_KERNEL_GS_BASE:
1150 vmx_load_host_state(to_vmx(vcpu));
1151 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1152 break;
26bb0981 1153#endif
6aa8b732 1154 case MSR_EFER:
3bab1f5d 1155 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1156 case MSR_IA32_TSC:
6aa8b732
AK		 1157 data = guest_read_tsc();
1158 break;
1159 case MSR_IA32_SYSENTER_CS:
1160 data = vmcs_read32(GUEST_SYSENTER_CS);
1161 break;
1162 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1163 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1164 break;
1165 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1166 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1167 break;
4e47c7a6
SY		 1168 case MSR_TSC_AUX:
1169 if (!to_vmx(vcpu)->rdtscp_enabled)
1170 return 1;
1171 /* Otherwise falls through */
6aa8b732 1172 default:
26bb0981 1173 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1174 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1175 if (msr) {
542423b0 1176 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1177 data = msr->data;
1178 break;
6aa8b732 1179 }
3bab1f5d 1180 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1181 }
1182
1183 *pdata = data;
1184 return 0;
1185}
1186
1187/*
1188 * Writes msr value into into the appropriate "register".
1189 * Returns 0 on success, non-0 otherwise.
1190 * Assumes vcpu_load() was already called.
1191 */
1192static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1193{
a2fa3e9f 1194 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1195 struct shared_msr_entry *msr;
53f658b3 1196 u64 host_tsc;
2cc51560
ED		 1197 int ret = 0;
1198
6aa8b732 1199 switch (msr_index) {
3bab1f5d 1200 case MSR_EFER:
a9b21b62 1201 vmx_load_host_state(vmx);
2cc51560 1202 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1203 break;
16175a79 1204#ifdef CONFIG_X86_64
6aa8b732
AK		 1205 case MSR_FS_BASE:
1206 vmcs_writel(GUEST_FS_BASE, data);
1207 break;
1208 case MSR_GS_BASE:
1209 vmcs_writel(GUEST_GS_BASE, data);
1210 break;
44ea2b17
AK		 1211 case MSR_KERNEL_GS_BASE:
1212 vmx_load_host_state(vmx);
1213 vmx->msr_guest_kernel_gs_base = data;
1214 break;
6aa8b732
AK		 1215#endif
1216 case MSR_IA32_SYSENTER_CS:
1217 vmcs_write32(GUEST_SYSENTER_CS, data);
1218 break;
1219 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1220 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1221 break;
1222 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1223 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1224 break;
af24a4e4 1225 case MSR_IA32_TSC:
53f658b3
MT		 1226 rdtscll(host_tsc);
1227 guest_write_tsc(data, host_tsc);
6aa8b732 1228 break;
468d472f
SY		 1229 case MSR_IA32_CR_PAT:
1230 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1231 vmcs_write64(GUEST_IA32_PAT, data);
1232 vcpu->arch.pat = data;
1233 break;
1234 }
4e47c7a6
SY		 1235 ret = kvm_set_msr_common(vcpu, msr_index, data);
1236 break;
1237 case MSR_TSC_AUX:
1238 if (!vmx->rdtscp_enabled)
1239 return 1;
1240 /* Check reserved bit, higher 32 bits should be zero */
1241 if ((data >> 32) != 0)
1242 return 1;
1243 /* Otherwise falls through */
6aa8b732 1244 default:
8b9cf98c 1245 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1246 if (msr) {
542423b0 1247 vmx_load_host_state(vmx);
3bab1f5d
AK		 1248 msr->data = data;
1249 break;
6aa8b732 1250 }
2cc51560 1251 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1252 }
1253
2cc51560 1254 return ret;
6aa8b732
AK		 1255}
1256
5fdbf976 1257static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1258{
5fdbf976
MT		 1259 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1260 switch (reg) {
1261 case VCPU_REGS_RSP:
1262 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1263 break;
1264 case VCPU_REGS_RIP:
1265 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1266 break;
6de4f3ad
AK		 1267 case VCPU_EXREG_PDPTR:
1268 if (enable_ept)
1269 ept_save_pdptrs(vcpu);
1270 break;
5fdbf976
MT		 1271 default:
1272 break;
1273 }
6aa8b732
AK		 1274}
1275
355be0b9 1276static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1277{
ae675ef0
JK		 1278 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1279 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1280 else
1281 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1282
abd3f2d6 1283 update_exception_bitmap(vcpu);
6aa8b732
AK		 1284}
1285
1286static __init int cpu_has_kvm_support(void)
1287{
6210e37b 1288 return cpu_has_vmx();
6aa8b732
AK		 1289}
1290
1291static __init int vmx_disabled_by_bios(void)
1292{
1293 u64 msr;
1294
1295 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1296 if (msr & FEATURE_CONTROL_LOCKED) {
1297 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1298 && tboot_enabled())
1299 return 1;
1300 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1301 && !tboot_enabled())
1302 return 1;
1303 }
1304
1305 return 0;
62b3ffb8 1306 /* locked but not enabled */
6aa8b732
AK		 1307}
1308
7725b894
DX		 1309static void kvm_cpu_vmxon(u64 addr)
1310{
1311 asm volatile (ASM_VMX_VMXON_RAX
1312 : : "a"(&addr), "m"(addr)
1313 : "memory", "cc");
1314}
1315
10474ae8 1316static int hardware_enable(void *garbage)
6aa8b732
AK		 1317{
1318 int cpu = raw_smp_processor_id();
1319 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1320 u64 old, test_bits;
6aa8b732 1321
10474ae8
AG		 1322 if (read_cr4() & X86_CR4_VMXE)
1323 return -EBUSY;
1324
543e4243 1325 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1326 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1327
1328 test_bits = FEATURE_CONTROL_LOCKED;
1329 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1330 if (tboot_enabled())
1331 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1332
1333 if ((old & test_bits) != test_bits) {
6aa8b732 1334 /* enable and lock */
cafd6659
SW		 1335 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1336 }
66aee91a 1337 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1338
4610c9cc
DX		 1339 if (vmm_exclusive) {
1340 kvm_cpu_vmxon(phys_addr);
1341 ept_sync_global();
1342 }
10474ae8
AG		 1343
1344 return 0;
6aa8b732
AK		 1345}
1346
543e4243
AK		 1347static void vmclear_local_vcpus(void)
1348{
1349 int cpu = raw_smp_processor_id();
1350 struct vcpu_vmx *vmx, *n;
1351
1352 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1353 local_vcpus_link)
1354 __vcpu_clear(vmx);
1355}
1356
710ff4a8
EH		 1357
1358/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1359 * tricks.
1360 */
1361static void kvm_cpu_vmxoff(void)
6aa8b732 1362{
4ecac3fd 1363 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1364}
1365
710ff4a8
EH		 1366static void hardware_disable(void *garbage)
1367{
4610c9cc
DX		 1368 if (vmm_exclusive) {
1369 vmclear_local_vcpus();
1370 kvm_cpu_vmxoff();
1371 }
7725b894 1372 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1373}
1374
1c3d14fe 1375static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1376 u32 msr, u32 *result)
1c3d14fe
YS		 1377{
1378 u32 vmx_msr_low, vmx_msr_high;
1379 u32 ctl = ctl_min | ctl_opt;
1380
1381 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1382
1383 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1384 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1385
1386 /* Ensure minimum (required) set of control bits are supported. */
1387 if (ctl_min & ~ctl)
002c7f7c 1388 return -EIO;
1c3d14fe
YS		 1389
1390 *result = ctl;
1391 return 0;
1392}
1393
002c7f7c 1394static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1395{
1396 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1397 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1398 u32 _pin_based_exec_control = 0;
1399 u32 _cpu_based_exec_control = 0;
f78e0e2e 1400 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1401 u32 _vmexit_control = 0;
1402 u32 _vmentry_control = 0;
1403
1404 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1405 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1406 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1407 &_pin_based_exec_control) < 0)
002c7f7c 1408 return -EIO;
1c3d14fe
YS		 1409
1410 min = CPU_BASED_HLT_EXITING |
1411#ifdef CONFIG_X86_64
1412 CPU_BASED_CR8_LOAD_EXITING |
1413 CPU_BASED_CR8_STORE_EXITING |
1414#endif
d56f546d
SY		 1415 CPU_BASED_CR3_LOAD_EXITING |
1416 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1417 CPU_BASED_USE_IO_BITMAPS |
1418 CPU_BASED_MOV_DR_EXITING |
a7052897 1419 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1420 CPU_BASED_MWAIT_EXITING |
1421 CPU_BASED_MONITOR_EXITING |
a7052897 1422 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1423 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1424 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1425 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1426 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1427 &_cpu_based_exec_control) < 0)
002c7f7c 1428 return -EIO;
6e5d865c
YS		 1429#ifdef CONFIG_X86_64
1430 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1431 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1432 ~CPU_BASED_CR8_STORE_EXITING;
1433#endif
f78e0e2e 1434 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1435 min2 = 0;
1436 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1437 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1438 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1439 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1440 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1441 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1442 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1443 if (adjust_vmx_controls(min2, opt2,
1444 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1445 &_cpu_based_2nd_exec_control) < 0)
1446 return -EIO;
1447 }
1448#ifndef CONFIG_X86_64
1449 if (!(_cpu_based_2nd_exec_control &
1450 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1451 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1452#endif
d56f546d 1453 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1454 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1455 enabled */
5fff7d27
GN		 1456 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1457 CPU_BASED_CR3_STORE_EXITING |
1458 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1459 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1460 vmx_capability.ept, vmx_capability.vpid);
1461 }
1c3d14fe
YS		 1462
1463 min = 0;
1464#ifdef CONFIG_X86_64
1465 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1466#endif
468d472f 1467 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1468 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1469 &_vmexit_control) < 0)
002c7f7c 1470 return -EIO;
1c3d14fe 1471
468d472f
SY		 1472 min = 0;
1473 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1474 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1475 &_vmentry_control) < 0)
002c7f7c 1476 return -EIO;
6aa8b732 1477
c68876fd 1478 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1479
1480 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1481 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1482 return -EIO;
1c3d14fe
YS		 1483
1484#ifdef CONFIG_X86_64
1485 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1486 if (vmx_msr_high & (1u<<16))
002c7f7c 1487 return -EIO;
1c3d14fe
YS		 1488#endif
1489
1490 /* Require Write-Back (WB) memory type for VMCS accesses. */
1491 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1492 return -EIO;
1c3d14fe 1493
002c7f7c
YS		 1494 vmcs_conf->size = vmx_msr_high & 0x1fff;
1495 vmcs_conf->order = get_order(vmcs_config.size);
1496 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1497
002c7f7c
YS		 1498 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1499 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1500 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1501 vmcs_conf->vmexit_ctrl = _vmexit_control;
1502 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1503
1504 return 0;
c68876fd 1505}
6aa8b732
AK		 1506
1507static struct vmcs *alloc_vmcs_cpu(int cpu)
1508{
1509 int node = cpu_to_node(cpu);
1510 struct page *pages;
1511 struct vmcs *vmcs;
1512
6484eb3e 1513 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1514 if (!pages)
1515 return NULL;
1516 vmcs = page_address(pages);
1c3d14fe
YS		 1517 memset(vmcs, 0, vmcs_config.size);
1518 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1519 return vmcs;
1520}
1521
1522static struct vmcs *alloc_vmcs(void)
1523{
d3b2c338 1524 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1525}
1526
1527static void free_vmcs(struct vmcs *vmcs)
1528{
1c3d14fe 1529 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1530}
1531
39959588 1532static void free_kvm_area(void)
6aa8b732
AK		 1533{
1534 int cpu;
1535
3230bb47 1536 for_each_possible_cpu(cpu) {
6aa8b732 1537 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1538 per_cpu(vmxarea, cpu) = NULL;
1539 }
6aa8b732
AK		 1540}
1541
6aa8b732
AK		 1542static __init int alloc_kvm_area(void)
1543{
1544 int cpu;
1545
3230bb47 1546 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1547 struct vmcs *vmcs;
1548
1549 vmcs = alloc_vmcs_cpu(cpu);
1550 if (!vmcs) {
1551 free_kvm_area();
1552 return -ENOMEM;
1553 }
1554
1555 per_cpu(vmxarea, cpu) = vmcs;
1556 }
1557 return 0;
1558}
1559
1560static __init int hardware_setup(void)
1561{
002c7f7c
YS		 1562 if (setup_vmcs_config(&vmcs_config) < 0)
1563 return -EIO;
50a37eb4
JR		 1564
1565 if (boot_cpu_has(X86_FEATURE_NX))
1566 kvm_enable_efer_bits(EFER_NX);
1567
93ba03c2
SY		 1568 if (!cpu_has_vmx_vpid())
1569 enable_vpid = 0;
1570
3a624e29 1571 if (!cpu_has_vmx_ept()) {
93ba03c2 1572 enable_ept = 0;
3a624e29
NK		 1573 enable_unrestricted_guest = 0;
1574 }
1575
1576 if (!cpu_has_vmx_unrestricted_guest())
1577 enable_unrestricted_guest = 0;
93ba03c2
SY		 1578
1579 if (!cpu_has_vmx_flexpriority())
1580 flexpriority_enabled = 0;
1581
95ba8273
GN		 1582 if (!cpu_has_vmx_tpr_shadow())
1583 kvm_x86_ops->update_cr8_intercept = NULL;
1584
54dee993
MT		 1585 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1586 kvm_disable_largepages();
1587
4b8d54f9
ZE		 1588 if (!cpu_has_vmx_ple())
1589 ple_gap = 0;
1590
6aa8b732
AK		 1591 return alloc_kvm_area();
1592}
1593
1594static __exit void hardware_unsetup(void)
1595{
1596 free_kvm_area();
1597}
1598
6aa8b732
AK		 1599static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1600{
1601 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1602
6af11b9e 1603 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1604 vmcs_write16(sf->selector, save->selector);
1605 vmcs_writel(sf->base, save->base);
1606 vmcs_write32(sf->limit, save->limit);
1607 vmcs_write32(sf->ar_bytes, save->ar);
1608 } else {
1609 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1610 << AR_DPL_SHIFT;
1611 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1612 }
1613}
1614
1615static void enter_pmode(struct kvm_vcpu *vcpu)
1616{
1617 unsigned long flags;
a89a8fb9 1618 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1619
a89a8fb9 1620 vmx->emulation_required = 1;
7ffd92c5 1621 vmx->rmode.vm86_active = 0;
6aa8b732 1622
7ffd92c5
AK		 1623 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1624 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1625 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1626
1627 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1628 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1629 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1630 vmcs_writel(GUEST_RFLAGS, flags);
1631
66aee91a
RR		 1632 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1633 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1634
1635 update_exception_bitmap(vcpu);
1636
a89a8fb9
MG		 1637 if (emulate_invalid_guest_state)
1638 return;
1639
7ffd92c5
AK		 1640 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1641 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1642 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1643 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1644
1645 vmcs_write16(GUEST_SS_SELECTOR, 0);
1646 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1647
1648 vmcs_write16(GUEST_CS_SELECTOR,
1649 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1650 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1651}
1652
d77c26fc 1653static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1654{
bfc6d222 1655 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1656 struct kvm_memslots *slots;
1657 gfn_t base_gfn;
1658
90d83dc3 1659 slots = kvm_memslots(kvm);
bc6678a3 1660 base_gfn = kvm->memslots->memslots[0].base_gfn +
46a26bf5 1661 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1662 return base_gfn << PAGE_SHIFT;
1663 }
bfc6d222 1664 return kvm->arch.tss_addr;
6aa8b732
AK		 1665}
1666
1667static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1668{
1669 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1670
1671 save->selector = vmcs_read16(sf->selector);
1672 save->base = vmcs_readl(sf->base);
1673 save->limit = vmcs_read32(sf->limit);
1674 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1675 vmcs_write16(sf->selector, save->base >> 4);
1676 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1677 vmcs_write32(sf->limit, 0xffff);
1678 vmcs_write32(sf->ar_bytes, 0xf3);
1679}
1680
1681static void enter_rmode(struct kvm_vcpu *vcpu)
1682{
1683 unsigned long flags;
a89a8fb9 1684 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1685
3a624e29
NK		 1686 if (enable_unrestricted_guest)
1687 return;
1688
a89a8fb9 1689 vmx->emulation_required = 1;
7ffd92c5 1690 vmx->rmode.vm86_active = 1;
6aa8b732 1691
7ffd92c5 1692 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1693 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1694
7ffd92c5 1695 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1696 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1697
7ffd92c5 1698 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1699 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1700
1701 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1702 vmx->rmode.save_rflags = flags;
6aa8b732 1703
053de044 1704 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1705
1706 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1707 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1708 update_exception_bitmap(vcpu);
1709
a89a8fb9
MG		 1710 if (emulate_invalid_guest_state)
1711 goto continue_rmode;
1712
6aa8b732
AK		 1713 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1714 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1715 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1716
1717 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1718 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1719 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1720 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1721 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1722
7ffd92c5
AK		 1723 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1724 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1725 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1726 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1727
a89a8fb9 1728continue_rmode:
8668a3c4 1729 kvm_mmu_reset_context(vcpu);
b7ebfb05 1730 init_rmode(vcpu->kvm);
6aa8b732
AK		 1731}
1732
401d10de
AS		 1733static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1734{
1735 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1736 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1737
1738 if (!msr)
1739 return;
401d10de 1740
44ea2b17
AK		 1741 /*
1742 * Force kernel_gs_base reloading before EFER changes, as control
1743 * of this msr depends on is_long_mode().
1744 */
1745 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1746 vcpu->arch.efer = efer;
401d10de
AS		 1747 if (efer & EFER_LMA) {
1748 vmcs_write32(VM_ENTRY_CONTROLS,
1749 vmcs_read32(VM_ENTRY_CONTROLS) |
1750 VM_ENTRY_IA32E_MODE);
1751 msr->data = efer;
1752 } else {
1753 vmcs_write32(VM_ENTRY_CONTROLS,
1754 vmcs_read32(VM_ENTRY_CONTROLS) &
1755 ~VM_ENTRY_IA32E_MODE);
1756
1757 msr->data = efer & ~EFER_LME;
1758 }
1759 setup_msrs(vmx);
1760}
1761
05b3e0c2 1762#ifdef CONFIG_X86_64
6aa8b732
AK		 1763
1764static void enter_lmode(struct kvm_vcpu *vcpu)
1765{
1766 u32 guest_tr_ar;
1767
1768 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1769 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1770 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1771 __func__);
6aa8b732
AK		 1772 vmcs_write32(GUEST_TR_AR_BYTES,
1773 (guest_tr_ar & ~AR_TYPE_MASK)
1774 | AR_TYPE_BUSY_64_TSS);
1775 }
da38f438 1776 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1777}
1778
1779static void exit_lmode(struct kvm_vcpu *vcpu)
1780{
6aa8b732
AK		 1781 vmcs_write32(VM_ENTRY_CONTROLS,
1782 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1783 & ~VM_ENTRY_IA32E_MODE);
da38f438 1784 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1785}
1786
1787#endif
1788
2384d2b3
SY		 1789static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1790{
1791 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1792 if (enable_ept)
4e1096d2 1793 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1794}
1795
e8467fda
AK		 1796static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1797{
1798 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1799
1800 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1801 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1802}
1803
25c4c276 1804static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1805{
fc78f519
AK		 1806 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1807
1808 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1809 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1810}
1811
1439442c
SY		 1812static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1813{
6de4f3ad
AK		 1814 if (!test_bit(VCPU_EXREG_PDPTR,
1815 (unsigned long *)&vcpu->arch.regs_dirty))
1816 return;
1817
1439442c 1818 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1819 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1820 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1821 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1822 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1823 }
1824}
1825
8f5d549f
AK		 1826static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1827{
1828 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1829 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1830 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1831 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1832 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1833 }
6de4f3ad
AK		 1834
1835 __set_bit(VCPU_EXREG_PDPTR,
1836 (unsigned long *)&vcpu->arch.regs_avail);
1837 __set_bit(VCPU_EXREG_PDPTR,
1838 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1839}
1840
1439442c
SY		 1841static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1842
1843static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1844 unsigned long cr0,
1845 struct kvm_vcpu *vcpu)
1846{
1847 if (!(cr0 & X86_CR0_PG)) {
1848 /* From paging/starting to nonpaging */
1849 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1850 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1851 (CPU_BASED_CR3_LOAD_EXITING |
1852 CPU_BASED_CR3_STORE_EXITING));
1853 vcpu->arch.cr0 = cr0;
fc78f519 1854 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1855 } else if (!is_paging(vcpu)) {
1856 /* From nonpaging to paging */
1857 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1858 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1859 ~(CPU_BASED_CR3_LOAD_EXITING |
1860 CPU_BASED_CR3_STORE_EXITING));
1861 vcpu->arch.cr0 = cr0;
fc78f519 1862 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1863 }
95eb84a7
SY		 1864
1865 if (!(cr0 & X86_CR0_WP))
1866 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1867}
1868
6aa8b732
AK		 1869static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1870{
7ffd92c5 1871 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1872 unsigned long hw_cr0;
1873
1874 if (enable_unrestricted_guest)
1875 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1876 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1877 else
1878 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1879
7ffd92c5 1880 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1881 enter_pmode(vcpu);
1882
7ffd92c5 1883 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1884 enter_rmode(vcpu);
1885
05b3e0c2 1886#ifdef CONFIG_X86_64
f6801dff 1887 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1888 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1889 enter_lmode(vcpu);
707d92fa 1890 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1891 exit_lmode(vcpu);
1892 }
1893#endif
1894
089d034e 1895 if (enable_ept)
1439442c
SY		 1896 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1897
02daab21 1898 if (!vcpu->fpu_active)
81231c69 1899 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1900
6aa8b732 1901 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1902 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1903 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1904}
1905
1439442c
SY		 1906static u64 construct_eptp(unsigned long root_hpa)
1907{
1908 u64 eptp;
1909
1910 /* TODO write the value reading from MSR */
1911 eptp = VMX_EPT_DEFAULT_MT |
1912 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1913 eptp |= (root_hpa & PAGE_MASK);
1914
1915 return eptp;
1916}
1917
6aa8b732
AK		 1918static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1919{
1439442c
SY		 1920 unsigned long guest_cr3;
1921 u64 eptp;
1922
1923 guest_cr3 = cr3;
089d034e 1924 if (enable_ept) {
1439442c
SY		 1925 eptp = construct_eptp(cr3);
1926 vmcs_write64(EPT_POINTER, eptp);
1439442c 1927 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1928 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1929 ept_load_pdptrs(vcpu);
1439442c
SY		 1930 }
1931
2384d2b3 1932 vmx_flush_tlb(vcpu);
1439442c 1933 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1934}
1935
1936static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1937{
7ffd92c5 1938 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1939 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1940
ad312c7c 1941 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1942 if (enable_ept) {
1943 if (!is_paging(vcpu)) {
1944 hw_cr4 &= ~X86_CR4_PAE;
1945 hw_cr4 |= X86_CR4_PSE;
1946 } else if (!(cr4 & X86_CR4_PAE)) {
1947 hw_cr4 &= ~X86_CR4_PAE;
1948 }
1949 }
1439442c
SY		 1950
1951 vmcs_writel(CR4_READ_SHADOW, cr4);
1952 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1953}
1954
6aa8b732
AK		 1955static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1956{
1957 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1958
1959 return vmcs_readl(sf->base);
1960}
1961
1962static void vmx_get_segment(struct kvm_vcpu *vcpu,
1963 struct kvm_segment *var, int seg)
1964{
1965 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1966 u32 ar;
1967
1968 var->base = vmcs_readl(sf->base);
1969 var->limit = vmcs_read32(sf->limit);
1970 var->selector = vmcs_read16(sf->selector);
1971 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1972 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1973 ar = 0;
1974 var->type = ar & 15;
1975 var->s = (ar >> 4) & 1;
1976 var->dpl = (ar >> 5) & 3;
1977 var->present = (ar >> 7) & 1;
1978 var->avl = (ar >> 12) & 1;
1979 var->l = (ar >> 13) & 1;
1980 var->db = (ar >> 14) & 1;
1981 var->g = (ar >> 15) & 1;
1982 var->unusable = (ar >> 16) & 1;
1983}
1984
2e4d2653
IE		 1985static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1986{
3eeb3288 1987 if (!is_protmode(vcpu))
2e4d2653
IE		 1988 return 0;
1989
1990 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1991 return 3;
1992
eab4b8aa 1993 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1994}
1995
653e3108 1996static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1997{
6aa8b732
AK		 1998 u32 ar;
1999
653e3108 2000 if (var->unusable)
6aa8b732
AK		 2001 ar = 1 << 16;
2002 else {
2003 ar = var->type & 15;
2004 ar |= (var->s & 1) << 4;
2005 ar |= (var->dpl & 3) << 5;
2006 ar |= (var->present & 1) << 7;
2007 ar |= (var->avl & 1) << 12;
2008 ar |= (var->l & 1) << 13;
2009 ar |= (var->db & 1) << 14;
2010 ar |= (var->g & 1) << 15;
2011 }
f7fbf1fd
UL		 2012 if (ar == 0) /* a 0 value means unusable */
2013 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2014
2015 return ar;
2016}
2017
2018static void vmx_set_segment(struct kvm_vcpu *vcpu,
2019 struct kvm_segment *var, int seg)
2020{
7ffd92c5 2021 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2022 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2023 u32 ar;
2024
7ffd92c5
AK		 2025 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2026 vmx->rmode.tr.selector = var->selector;
2027 vmx->rmode.tr.base = var->base;
2028 vmx->rmode.tr.limit = var->limit;
2029 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2030 return;
2031 }
2032 vmcs_writel(sf->base, var->base);
2033 vmcs_write32(sf->limit, var->limit);
2034 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2035 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2036 /*
2037 * Hack real-mode segments into vm86 compatibility.
2038 */
2039 if (var->base == 0xffff0000 && var->selector == 0xf000)
2040 vmcs_writel(sf->base, 0xf0000);
2041 ar = 0xf3;
2042 } else
2043 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2044
2045 /*
2046 * Fix the "Accessed" bit in AR field of segment registers for older
2047 * qemu binaries.
2048 * IA32 arch specifies that at the time of processor reset the
2049 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2050 * is setting it to 0 in the usedland code. This causes invalid guest
2051 * state vmexit when "unrestricted guest" mode is turned on.
2052 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2053 * tree. Newer qemu binaries with that qemu fix would not need this
2054 * kvm hack.
2055 */
2056 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2057 ar |= 0x1; /* Accessed */
2058
6aa8b732
AK		 2059 vmcs_write32(sf->ar_bytes, ar);
2060}
2061
6aa8b732
AK		 2062static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2063{
2064 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2065
2066 *db = (ar >> 14) & 1;
2067 *l = (ar >> 13) & 1;
2068}
2069
89a27f4d 2070static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2071{
89a27f4d
GN		 2072 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2073 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2074}
2075
89a27f4d 2076static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2077{
89a27f4d
GN		 2078 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2079 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2080}
2081
89a27f4d 2082static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2083{
89a27f4d
GN		 2084 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2085 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2086}
2087
89a27f4d 2088static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2089{
89a27f4d
GN		 2090 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2091 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2092}
2093
648dfaa7
MG		 2094static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2095{
2096 struct kvm_segment var;
2097 u32 ar;
2098
2099 vmx_get_segment(vcpu, &var, seg);
2100 ar = vmx_segment_access_rights(&var);
2101
2102 if (var.base != (var.selector << 4))
2103 return false;
2104 if (var.limit != 0xffff)
2105 return false;
2106 if (ar != 0xf3)
2107 return false;
2108
2109 return true;
2110}
2111
2112static bool code_segment_valid(struct kvm_vcpu *vcpu)
2113{
2114 struct kvm_segment cs;
2115 unsigned int cs_rpl;
2116
2117 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2118 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2119
1872a3f4
AK		 2120 if (cs.unusable)
2121 return false;
648dfaa7
MG		 2122 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2123 return false;
2124 if (!cs.s)
2125 return false;
1872a3f4 2126 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2127 if (cs.dpl > cs_rpl)
2128 return false;
1872a3f4 2129 } else {
648dfaa7
MG		 2130 if (cs.dpl != cs_rpl)
2131 return false;
2132 }
2133 if (!cs.present)
2134 return false;
2135
2136 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2137 return true;
2138}
2139
2140static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2141{
2142 struct kvm_segment ss;
2143 unsigned int ss_rpl;
2144
2145 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2146 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2147
1872a3f4
AK		 2148 if (ss.unusable)
2149 return true;
2150 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2151 return false;
2152 if (!ss.s)
2153 return false;
2154 if (ss.dpl != ss_rpl) /* DPL != RPL */
2155 return false;
2156 if (!ss.present)
2157 return false;
2158
2159 return true;
2160}
2161
2162static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2163{
2164 struct kvm_segment var;
2165 unsigned int rpl;
2166
2167 vmx_get_segment(vcpu, &var, seg);
2168 rpl = var.selector & SELECTOR_RPL_MASK;
2169
1872a3f4
AK		 2170 if (var.unusable)
2171 return true;
648dfaa7
MG		 2172 if (!var.s)
2173 return false;
2174 if (!var.present)
2175 return false;
2176 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2177 if (var.dpl < rpl) /* DPL < RPL */
2178 return false;
2179 }
2180
2181 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2182 * rights flags
2183 */
2184 return true;
2185}
2186
2187static bool tr_valid(struct kvm_vcpu *vcpu)
2188{
2189 struct kvm_segment tr;
2190
2191 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2192
1872a3f4
AK		 2193 if (tr.unusable)
2194 return false;
648dfaa7
MG		 2195 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2196 return false;
1872a3f4 2197 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2198 return false;
2199 if (!tr.present)
2200 return false;
2201
2202 return true;
2203}
2204
2205static bool ldtr_valid(struct kvm_vcpu *vcpu)
2206{
2207 struct kvm_segment ldtr;
2208
2209 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2210
1872a3f4
AK		 2211 if (ldtr.unusable)
2212 return true;
648dfaa7
MG		 2213 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2214 return false;
2215 if (ldtr.type != 2)
2216 return false;
2217 if (!ldtr.present)
2218 return false;
2219
2220 return true;
2221}
2222
2223static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2224{
2225 struct kvm_segment cs, ss;
2226
2227 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2228 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2229
2230 return ((cs.selector & SELECTOR_RPL_MASK) ==
2231 (ss.selector & SELECTOR_RPL_MASK));
2232}
2233
2234/*
2235 * Check if guest state is valid. Returns true if valid, false if
2236 * not.
2237 * We assume that registers are always usable
2238 */
2239static bool guest_state_valid(struct kvm_vcpu *vcpu)
2240{
2241 /* real mode guest state checks */
3eeb3288 2242 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2243 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2244 return false;
2245 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2246 return false;
2247 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2248 return false;
2249 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2250 return false;
2251 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2252 return false;
2253 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2254 return false;
2255 } else {
2256 /* protected mode guest state checks */
2257 if (!cs_ss_rpl_check(vcpu))
2258 return false;
2259 if (!code_segment_valid(vcpu))
2260 return false;
2261 if (!stack_segment_valid(vcpu))
2262 return false;
2263 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2264 return false;
2265 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2266 return false;
2267 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2268 return false;
2269 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2270 return false;
2271 if (!tr_valid(vcpu))
2272 return false;
2273 if (!ldtr_valid(vcpu))
2274 return false;
2275 }
2276 /* TODO:
2277 * - Add checks on RIP
2278 * - Add checks on RFLAGS
2279 */
2280
2281 return true;
2282}
2283
d77c26fc 2284static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2285{
6aa8b732 2286 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2287 u16 data = 0;
10589a46 2288 int ret = 0;
195aefde 2289 int r;
6aa8b732 2290
195aefde
IE		 2291 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2292 if (r < 0)
10589a46 2293 goto out;
195aefde 2294 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2295 r = kvm_write_guest_page(kvm, fn++, &data,
2296 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2297 if (r < 0)
10589a46 2298 goto out;
195aefde
IE		 2299 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2300 if (r < 0)
10589a46 2301 goto out;
195aefde
IE		 2302 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2303 if (r < 0)
10589a46 2304 goto out;
195aefde 2305 data = ~0;
10589a46
MT		 2306 r = kvm_write_guest_page(kvm, fn, &data,
2307 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2308 sizeof(u8));
195aefde 2309 if (r < 0)
10589a46
MT		 2310 goto out;
2311
2312 ret = 1;
2313out:
10589a46 2314 return ret;
6aa8b732
AK		 2315}
2316
b7ebfb05
SY		 2317static int init_rmode_identity_map(struct kvm *kvm)
2318{
2319 int i, r, ret;
2320 pfn_t identity_map_pfn;
2321 u32 tmp;
2322
089d034e 2323 if (!enable_ept)
b7ebfb05
SY		 2324 return 1;
2325 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2326 printk(KERN_ERR "EPT: identity-mapping pagetable "
2327 "haven't been allocated!\n");
2328 return 0;
2329 }
2330 if (likely(kvm->arch.ept_identity_pagetable_done))
2331 return 1;
2332 ret = 0;
b927a3ce 2333 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2334 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2335 if (r < 0)
2336 goto out;
2337 /* Set up identity-mapping pagetable for EPT in real mode */
2338 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2339 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2340 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2341 r = kvm_write_guest_page(kvm, identity_map_pfn,
2342 &tmp, i * sizeof(tmp), sizeof(tmp));
2343 if (r < 0)
2344 goto out;
2345 }
2346 kvm->arch.ept_identity_pagetable_done = true;
2347 ret = 1;
2348out:
2349 return ret;
2350}
2351
6aa8b732
AK		 2352static void seg_setup(int seg)
2353{
2354 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2355 unsigned int ar;
6aa8b732
AK		 2356
2357 vmcs_write16(sf->selector, 0);
2358 vmcs_writel(sf->base, 0);
2359 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2360 if (enable_unrestricted_guest) {
2361 ar = 0x93;
2362 if (seg == VCPU_SREG_CS)
2363 ar |= 0x08; /* code segment */
2364 } else
2365 ar = 0xf3;
2366
2367 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2368}
2369
f78e0e2e
SY		 2370static int alloc_apic_access_page(struct kvm *kvm)
2371{
2372 struct kvm_userspace_memory_region kvm_userspace_mem;
2373 int r = 0;
2374
79fac95e 2375 mutex_lock(&kvm->slots_lock);
bfc6d222 2376 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2377 goto out;
2378 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2379 kvm_userspace_mem.flags = 0;
2380 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2381 kvm_userspace_mem.memory_size = PAGE_SIZE;
2382 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2383 if (r)
2384 goto out;
72dc67a6 2385
bfc6d222 2386 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2387out:
79fac95e 2388 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2389 return r;
2390}
2391
b7ebfb05
SY		 2392static int alloc_identity_pagetable(struct kvm *kvm)
2393{
2394 struct kvm_userspace_memory_region kvm_userspace_mem;
2395 int r = 0;
2396
79fac95e 2397 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2398 if (kvm->arch.ept_identity_pagetable)
2399 goto out;
2400 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2401 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2402 kvm_userspace_mem.guest_phys_addr =
2403 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2404 kvm_userspace_mem.memory_size = PAGE_SIZE;
2405 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2406 if (r)
2407 goto out;
2408
b7ebfb05 2409 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2410 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2411out:
79fac95e 2412 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2413 return r;
2414}
2415
2384d2b3
SY		 2416static void allocate_vpid(struct vcpu_vmx *vmx)
2417{
2418 int vpid;
2419
2420 vmx->vpid = 0;
919818ab 2421 if (!enable_vpid)
2384d2b3
SY		 2422 return;
2423 spin_lock(&vmx_vpid_lock);
2424 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2425 if (vpid < VMX_NR_VPIDS) {
2426 vmx->vpid = vpid;
2427 __set_bit(vpid, vmx_vpid_bitmap);
2428 }
2429 spin_unlock(&vmx_vpid_lock);
2430}
2431
cdbecfc3
LJ		 2432static void free_vpid(struct vcpu_vmx *vmx)
2433{
2434 if (!enable_vpid)
2435 return;
2436 spin_lock(&vmx_vpid_lock);
2437 if (vmx->vpid != 0)
2438 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2439 spin_unlock(&vmx_vpid_lock);
2440}
2441
5897297b 2442static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2443{
3e7c73e9 2444 int f = sizeof(unsigned long);
25c5f225
SY		 2445
2446 if (!cpu_has_vmx_msr_bitmap())
2447 return;
2448
2449 /*
2450 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2451 * have the write-low and read-high bitmap offsets the wrong way round.
2452 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2453 */
25c5f225 2454 if (msr <= 0x1fff) {
3e7c73e9
AK		 2455 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2456 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2457 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2458 msr &= 0x1fff;
3e7c73e9
AK		 2459 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2460 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2461 }
25c5f225
SY		 2462}
2463
5897297b
AK		 2464static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2465{
2466 if (!longmode_only)
2467 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2468 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2469}
2470
6aa8b732
AK		 2471/*
2472 * Sets up the vmcs for emulated real mode.
2473 */
8b9cf98c 2474static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2475{
468d472f 2476 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2477 u32 junk;
53f658b3 2478 u64 host_pat, tsc_this, tsc_base;
6aa8b732 2479 unsigned long a;
89a27f4d 2480 struct desc_ptr dt;
6aa8b732 2481 int i;
cd2276a7 2482 unsigned long kvm_vmx_return;
6e5d865c 2483 u32 exec_control;
6aa8b732 2484
6aa8b732 2485 /* I/O */
3e7c73e9
AK		 2486 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2487 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2488
25c5f225 2489 if (cpu_has_vmx_msr_bitmap())
5897297b 2490 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2491
6aa8b732
AK		 2492 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2493
6aa8b732 2494 /* Control */
1c3d14fe
YS		 2495 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2496 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2497
2498 exec_control = vmcs_config.cpu_based_exec_ctrl;
2499 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2500 exec_control &= ~CPU_BASED_TPR_SHADOW;
2501#ifdef CONFIG_X86_64
2502 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2503 CPU_BASED_CR8_LOAD_EXITING;
2504#endif
2505 }
089d034e 2506 if (!enable_ept)
d56f546d 2507 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2508 CPU_BASED_CR3_LOAD_EXITING |
2509 CPU_BASED_INVLPG_EXITING;
6e5d865c 2510 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2511
83ff3b9d
SY		 2512 if (cpu_has_secondary_exec_ctrls()) {
2513 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2514 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2515 exec_control &=
2516 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2517 if (vmx->vpid == 0)
2518 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2519 if (!enable_ept) {
d56f546d 2520 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2521 enable_unrestricted_guest = 0;
2522 }
3a624e29
NK		 2523 if (!enable_unrestricted_guest)
2524 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2525 if (!ple_gap)
2526 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2527 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2528 }
f78e0e2e 2529
4b8d54f9
ZE		 2530 if (ple_gap) {
2531 vmcs_write32(PLE_GAP, ple_gap);
2532 vmcs_write32(PLE_WINDOW, ple_window);
2533 }
2534
c7addb90
AK		 2535 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2536 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2537 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2538
1c11e713 2539 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2540 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2541 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2542
2543 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2544 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2545 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2546 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2547 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2548 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2549#ifdef CONFIG_X86_64
6aa8b732
AK		 2550 rdmsrl(MSR_FS_BASE, a);
2551 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2552 rdmsrl(MSR_GS_BASE, a);
2553 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2554#else
2555 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2556 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2557#endif
2558
2559 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2560
ec68798c 2561 native_store_idt(&dt);
89a27f4d 2562 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2563
d77c26fc 2564 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2565 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2566 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2567 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2568 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2569 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2570 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2571
2572 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2573 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2574 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2575 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2576 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2577 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2578
468d472f
SY		 2579 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2580 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2581 host_pat = msr_low | ((u64) msr_high << 32);
2582 vmcs_write64(HOST_IA32_PAT, host_pat);
2583 }
2584 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2585 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2586 host_pat = msr_low | ((u64) msr_high << 32);
2587 /* Write the default value follow host pat */
2588 vmcs_write64(GUEST_IA32_PAT, host_pat);
2589 /* Keep arch.pat sync with GUEST_IA32_PAT */
2590 vmx->vcpu.arch.pat = host_pat;
2591 }
2592
6aa8b732
AK		 2593 for (i = 0; i < NR_VMX_MSR; ++i) {
2594 u32 index = vmx_msr_index[i];
2595 u32 data_low, data_high;
a2fa3e9f 2596 int j = vmx->nmsrs;
6aa8b732
AK		 2597
2598 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2599 continue;
432bd6cb
AK		 2600 if (wrmsr_safe(index, data_low, data_high) < 0)
2601 continue;
26bb0981
AK		 2602 vmx->guest_msrs[j].index = i;
2603 vmx->guest_msrs[j].data = 0;
d5696725 2604 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2605 ++vmx->nmsrs;
6aa8b732 2606 }
6aa8b732 2607
1c3d14fe 2608 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2609
2610 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2611 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2612
e00c8cf2 2613 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2614 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2615 if (enable_ept)
2616 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2617 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2618
53f658b3
MT		 2619 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2620 rdtscll(tsc_this);
2621 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2622 tsc_base = tsc_this;
2623
2624 guest_write_tsc(0, tsc_base);
f78e0e2e 2625
e00c8cf2
AK		 2626 return 0;
2627}
2628
b7ebfb05
SY		 2629static int init_rmode(struct kvm *kvm)
2630{
2631 if (!init_rmode_tss(kvm))
2632 return 0;
2633 if (!init_rmode_identity_map(kvm))
2634 return 0;
2635 return 1;
2636}
2637
e00c8cf2
AK		 2638static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2639{
2640 struct vcpu_vmx *vmx = to_vmx(vcpu);
2641 u64 msr;
f656ce01 2642 int ret, idx;
e00c8cf2 2643
5fdbf976 2644 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
f656ce01 2645 idx = srcu_read_lock(&vcpu->kvm->srcu);
b7ebfb05 2646 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2647 ret = -ENOMEM;
2648 goto out;
2649 }
2650
7ffd92c5 2651 vmx->rmode.vm86_active = 0;
e00c8cf2 2652
3b86cd99
JK		 2653 vmx->soft_vnmi_blocked = 0;
2654
ad312c7c 2655 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2656 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2657 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2658 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2659 msr |= MSR_IA32_APICBASE_BSP;
2660 kvm_set_apic_base(&vmx->vcpu, msr);
2661
10ab25cd
JK		 2662 ret = fx_init(&vmx->vcpu);
2663 if (ret != 0)
2664 goto out;
e00c8cf2 2665
5706be0d 2666 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2667 /*
2668 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2669 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2670 */
c5af89b6 2671 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2672 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2673 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2674 } else {
ad312c7c
ZX		 2675 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2676 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2677 }
e00c8cf2
AK		 2678
2679 seg_setup(VCPU_SREG_DS);
2680 seg_setup(VCPU_SREG_ES);
2681 seg_setup(VCPU_SREG_FS);
2682 seg_setup(VCPU_SREG_GS);
2683 seg_setup(VCPU_SREG_SS);
2684
2685 vmcs_write16(GUEST_TR_SELECTOR, 0);
2686 vmcs_writel(GUEST_TR_BASE, 0);
2687 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2688 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2689
2690 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2691 vmcs_writel(GUEST_LDTR_BASE, 0);
2692 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2693 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2694
2695 vmcs_write32(GUEST_SYSENTER_CS, 0);
2696 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2697 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2698
2699 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2700 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2701 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2702 else
5fdbf976
MT		 2703 kvm_rip_write(vcpu, 0);
2704 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2705
e00c8cf2
AK		 2706 vmcs_writel(GUEST_DR7, 0x400);
2707
2708 vmcs_writel(GUEST_GDTR_BASE, 0);
2709 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2710
2711 vmcs_writel(GUEST_IDTR_BASE, 0);
2712 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2713
2714 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2715 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2716 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2717
e00c8cf2
AK		 2718 /* Special registers */
2719 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2720
2721 setup_msrs(vmx);
2722
6aa8b732
AK		 2723 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2724
f78e0e2e
SY		 2725 if (cpu_has_vmx_tpr_shadow()) {
2726 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2727 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2728 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2729 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2730 vmcs_write32(TPR_THRESHOLD, 0);
2731 }
2732
2733 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2734 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2735 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2736
2384d2b3
SY		 2737 if (vmx->vpid != 0)
2738 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2739
fa40052c 2740 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2741 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2742 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2743 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2744 vmx_fpu_activate(&vmx->vcpu);
2745 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2746
2384d2b3
SY		 2747 vpid_sync_vcpu_all(vmx);
2748
3200f405 2749 ret = 0;
6aa8b732 2750
a89a8fb9
MG		 2751 /* HACK: Don't enable emulation on guest boot/reset */
2752 vmx->emulation_required = 0;
2753
6aa8b732 2754out:
f656ce01 2755 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6aa8b732
AK		 2756 return ret;
2757}
2758
3b86cd99
JK		 2759static void enable_irq_window(struct kvm_vcpu *vcpu)
2760{
2761 u32 cpu_based_vm_exec_control;
2762
2763 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2764 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2765 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2766}
2767
2768static void enable_nmi_window(struct kvm_vcpu *vcpu)
2769{
2770 u32 cpu_based_vm_exec_control;
2771
2772 if (!cpu_has_virtual_nmis()) {
2773 enable_irq_window(vcpu);
2774 return;
2775 }
2776
2777 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2778 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2779 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2780}
2781
66fd3f7f 2782static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2783{
9c8cba37 2784 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2785 uint32_t intr;
2786 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2787
229456fc 2788 trace_kvm_inj_virq(irq);
2714d1d3 2789
fa89a817 2790 ++vcpu->stat.irq_injections;
7ffd92c5 2791 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2792 vmx->rmode.irq.pending = true;
2793 vmx->rmode.irq.vector = irq;
5fdbf976 2794 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2795 if (vcpu->arch.interrupt.soft)
2796 vmx->rmode.irq.rip +=
2797 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2798 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2799 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2800 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2801 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2802 return;
2803 }
66fd3f7f
GN		 2804 intr = irq | INTR_INFO_VALID_MASK;
2805 if (vcpu->arch.interrupt.soft) {
2806 intr |= INTR_TYPE_SOFT_INTR;
2807 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2808 vmx->vcpu.arch.event_exit_inst_len);
2809 } else
2810 intr |= INTR_TYPE_EXT_INTR;
2811 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2812}
2813
f08864b4
SY		 2814static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2815{
66a5a347
JK		 2816 struct vcpu_vmx *vmx = to_vmx(vcpu);
2817
3b86cd99
JK		 2818 if (!cpu_has_virtual_nmis()) {
2819 /*
2820 * Tracking the NMI-blocked state in software is built upon
2821 * finding the next open IRQ window. This, in turn, depends on
2822 * well-behaving guests: They have to keep IRQs disabled at
2823 * least as long as the NMI handler runs. Otherwise we may
2824 * cause NMI nesting, maybe breaking the guest. But as this is
2825 * highly unlikely, we can live with the residual risk.
2826 */
2827 vmx->soft_vnmi_blocked = 1;
2828 vmx->vnmi_blocked_time = 0;
2829 }
2830
487b391d 2831 ++vcpu->stat.nmi_injections;
7ffd92c5 2832 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2833 vmx->rmode.irq.pending = true;
2834 vmx->rmode.irq.vector = NMI_VECTOR;
2835 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2836 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2837 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2838 INTR_INFO_VALID_MASK);
2839 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2840 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2841 return;
2842 }
f08864b4
SY		 2843 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2844 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2845}
2846
c4282df9 2847static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2848{
3b86cd99 2849 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2850 return 0;
33f089ca 2851
c4282df9 2852 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
f8c5fae1 2853 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2854}
2855
3cfc3092
JK		 2856static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2857{
2858 if (!cpu_has_virtual_nmis())
2859 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2860 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2861}
2862
2863static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2864{
2865 struct vcpu_vmx *vmx = to_vmx(vcpu);
2866
2867 if (!cpu_has_virtual_nmis()) {
2868 if (vmx->soft_vnmi_blocked != masked) {
2869 vmx->soft_vnmi_blocked = masked;
2870 vmx->vnmi_blocked_time = 0;
2871 }
2872 } else {
2873 if (masked)
2874 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2875 GUEST_INTR_STATE_NMI);
2876 else
2877 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2878 GUEST_INTR_STATE_NMI);
2879 }
2880}
2881
78646121
GN		 2882static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2883{
c4282df9
GN		 2884 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2885 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2886 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2887}
2888
cbc94022
IE		 2889static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2890{
2891 int ret;
2892 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2893 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2894 .guest_phys_addr = addr,
2895 .memory_size = PAGE_SIZE * 3,
2896 .flags = 0,
2897 };
2898
2899 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2900 if (ret)
2901 return ret;
bfc6d222 2902 kvm->arch.tss_addr = addr;
cbc94022
IE		 2903 return 0;
2904}
2905
6aa8b732
AK		 2906static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2907 int vec, u32 err_code)
2908{
b3f37707
NK		 2909 /*
2910 * Instruction with address size override prefix opcode 0x67
2911 * Cause the #SS fault with 0 error code in VM86 mode.
2912 */
2913 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2914 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2915 return 1;
77ab6db0
JK		 2916 /*
2917 * Forward all other exceptions that are valid in real mode.
2918 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2919 * the required debugging infrastructure rework.
2920 */
2921 switch (vec) {
77ab6db0 2922 case DB_VECTOR:
d0bfb940
JK		 2923 if (vcpu->guest_debug &
2924 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2925 return 0;
2926 kvm_queue_exception(vcpu, vec);
2927 return 1;
77ab6db0 2928 case BP_VECTOR:
c573cd22
JK		 2929 /*
2930 * Update instruction length as we may reinject the exception
2931 * from user space while in guest debugging mode.
2932 */
2933 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2934 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2935 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2936 return 0;
2937 /* fall through */
2938 case DE_VECTOR:
77ab6db0
JK		 2939 case OF_VECTOR:
2940 case BR_VECTOR:
2941 case UD_VECTOR:
2942 case DF_VECTOR:
2943 case SS_VECTOR:
2944 case GP_VECTOR:
2945 case MF_VECTOR:
2946 kvm_queue_exception(vcpu, vec);
2947 return 1;
2948 }
6aa8b732
AK		 2949 return 0;
2950}
2951
a0861c02
AK		 2952/*
2953 * Trigger machine check on the host. We assume all the MSRs are already set up
2954 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2955 * We pass a fake environment to the machine check handler because we want
2956 * the guest to be always treated like user space, no matter what context
2957 * it used internally.
2958 */
2959static void kvm_machine_check(void)
2960{
2961#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2962 struct pt_regs regs = {
2963 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2964 .flags = X86_EFLAGS_IF,
2965 };
2966
2967 do_machine_check(&regs, 0);
2968#endif
2969}
2970
851ba692 2971static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2972{
2973 /* already handled by vcpu_run */
2974 return 1;
2975}
2976
851ba692 2977static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2978{
1155f76a 2979 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2980 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2981 u32 intr_info, ex_no, error_code;
42dbaa5a 2982 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2983 u32 vect_info;
2984 enum emulation_result er;
2985
1155f76a 2986 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2987 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2988
a0861c02 2989 if (is_machine_check(intr_info))
851ba692 2990 return handle_machine_check(vcpu);
a0861c02 2991
6aa8b732 2992 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2993 !is_page_fault(intr_info)) {
2994 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2995 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2996 vcpu->run->internal.ndata = 2;
2997 vcpu->run->internal.data[0] = vect_info;
2998 vcpu->run->internal.data[1] = intr_info;
2999 return 0;
3000 }
6aa8b732 3001
e4a41889 3002 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3003 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3004
3005 if (is_no_device(intr_info)) {
5fd86fcf 3006 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3007 return 1;
3008 }
3009
7aa81cc0 3010 if (is_invalid_opcode(intr_info)) {
851ba692 3011 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 3012 if (er != EMULATE_DONE)
7ee5d940 3013 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3014 return 1;
3015 }
3016
6aa8b732 3017 error_code = 0;
5fdbf976 3018 rip = kvm_rip_read(vcpu);
2e11384c 3019 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3020 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3021 if (is_page_fault(intr_info)) {
1439442c 3022 /* EPT won't cause page fault directly */
089d034e 3023 if (enable_ept)
1439442c 3024 BUG();
6aa8b732 3025 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3026 trace_kvm_page_fault(cr2, error_code);
3027
3298b75c 3028 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3029 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 3030 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 3031 }
3032
7ffd92c5 3033 if (vmx->rmode.vm86_active &&
6aa8b732 3034 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3035 error_code)) {
ad312c7c
ZX		 3036 if (vcpu->arch.halt_request) {
3037 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3038 return kvm_emulate_halt(vcpu);
3039 }
6aa8b732 3040 return 1;
72d6e5a0 3041 }
6aa8b732 3042
d0bfb940 3043 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3044 switch (ex_no) {
3045 case DB_VECTOR:
3046 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3047 if (!(vcpu->guest_debug &
3048 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3049 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3050 kvm_queue_exception(vcpu, DB_VECTOR);
3051 return 1;
3052 }
3053 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3054 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3055 /* fall through */
3056 case BP_VECTOR:
c573cd22
JK		 3057 /*
3058 * Update instruction length as we may reinject #BP from
3059 * user space while in guest debugging mode. Reading it for
3060 * #DB as well causes no harm, it is not used in that case.
3061 */
3062 vmx->vcpu.arch.event_exit_inst_len =
3063 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3064 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3065 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3066 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3067 break;
3068 default:
d0bfb940
JK		 3069 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3070 kvm_run->ex.exception = ex_no;
3071 kvm_run->ex.error_code = error_code;
42dbaa5a 3072 break;
6aa8b732 3073 }
6aa8b732
AK		 3074 return 0;
3075}
3076
851ba692 3077static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3078{
1165f5fe 3079 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3080 return 1;
3081}
3082
851ba692 3083static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3084{
851ba692 3085 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3086 return 0;
3087}
6aa8b732 3088
851ba692 3089static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3090{
bfdaab09 3091 unsigned long exit_qualification;
34c33d16 3092 int size, in, string;
039576c0 3093 unsigned port;
6aa8b732 3094
bfdaab09 3095 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3096 string = (exit_qualification & 16) != 0;
cf8f70bf 3097 in = (exit_qualification & 8) != 0;
e70669ab 3098
cf8f70bf 3099 ++vcpu->stat.io_exits;
e70669ab 3100
cf8f70bf 3101 if (string || in)
6d77dbfc 3102 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
e70669ab 3103
cf8f70bf
GN		 3104 port = exit_qualification >> 16;
3105 size = (exit_qualification & 7) + 1;
e93f36bc 3106 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3107
3108 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3109}
3110
102d8325
IM		 3111static void
3112vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3113{
3114 /*
3115 * Patch in the VMCALL instruction:
3116 */
3117 hypercall[0] = 0x0f;
3118 hypercall[1] = 0x01;
3119 hypercall[2] = 0xc1;
102d8325
IM		 3120}
3121
851ba692 3122static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3123{
229456fc 3124 unsigned long exit_qualification, val;
6aa8b732
AK		 3125 int cr;
3126 int reg;
3127
bfdaab09 3128 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3129 cr = exit_qualification & 15;
3130 reg = (exit_qualification >> 8) & 15;
3131 switch ((exit_qualification >> 4) & 3) {
3132 case 0: /* mov to cr */
229456fc
MT		 3133 val = kvm_register_read(vcpu, reg);
3134 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3135 switch (cr) {
3136 case 0:
229456fc 3137 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 3138 skip_emulated_instruction(vcpu);
3139 return 1;
3140 case 3:
229456fc 3141 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 3142 skip_emulated_instruction(vcpu);
3143 return 1;
3144 case 4:
229456fc 3145 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 3146 skip_emulated_instruction(vcpu);
3147 return 1;
0a5fff19
GN		 3148 case 8: {
3149 u8 cr8_prev = kvm_get_cr8(vcpu);
3150 u8 cr8 = kvm_register_read(vcpu, reg);
3151 kvm_set_cr8(vcpu, cr8);
3152 skip_emulated_instruction(vcpu);
3153 if (irqchip_in_kernel(vcpu->kvm))
3154 return 1;
3155 if (cr8_prev <= cr8)
3156 return 1;
851ba692 3157 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3158 return 0;
3159 }
6aa8b732
AK		 3160 };
3161 break;
25c4c276 3162 case 2: /* clts */
edcafe3c 3163 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3164 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3165 skip_emulated_instruction(vcpu);
6b52d186 3166 vmx_fpu_activate(vcpu);
25c4c276 3167 return 1;
6aa8b732
AK		 3168 case 1: /*mov from cr*/
3169 switch (cr) {
3170 case 3:
5fdbf976 3171 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3172 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3173 skip_emulated_instruction(vcpu);
3174 return 1;
3175 case 8:
229456fc
MT		 3176 val = kvm_get_cr8(vcpu);
3177 kvm_register_write(vcpu, reg, val);
3178 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3179 skip_emulated_instruction(vcpu);
3180 return 1;
3181 }
3182 break;
3183 case 3: /* lmsw */
a1f83a74 3184 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3185 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3186 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3187
3188 skip_emulated_instruction(vcpu);
3189 return 1;
3190 default:
3191 break;
3192 }
851ba692 3193 vcpu->run->exit_reason = 0;
f0242478 3194 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3195 (int)(exit_qualification >> 4) & 3, cr);
3196 return 0;
3197}
3198
851ba692 3199static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3200{
bfdaab09 3201 unsigned long exit_qualification;
6aa8b732
AK		 3202 int dr, reg;
3203
f2483415 3204 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3205 if (!kvm_require_cpl(vcpu, 0))
3206 return 1;
42dbaa5a
JK		 3207 dr = vmcs_readl(GUEST_DR7);
3208 if (dr & DR7_GD) {
3209 /*
3210 * As the vm-exit takes precedence over the debug trap, we
3211 * need to emulate the latter, either for the host or the
3212 * guest debugging itself.
3213 */
3214 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3215 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3216 vcpu->run->debug.arch.dr7 = dr;
3217 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3218 vmcs_readl(GUEST_CS_BASE) +
3219 vmcs_readl(GUEST_RIP);
851ba692
AK		 3220 vcpu->run->debug.arch.exception = DB_VECTOR;
3221 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3222 return 0;
3223 } else {
3224 vcpu->arch.dr7 &= ~DR7_GD;
3225 vcpu->arch.dr6 |= DR6_BD;
3226 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3227 kvm_queue_exception(vcpu, DB_VECTOR);
3228 return 1;
3229 }
3230 }
3231
bfdaab09 3232 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3233 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3234 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3235 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3236 unsigned long val;
3237 if (!kvm_get_dr(vcpu, dr, &val))
3238 kvm_register_write(vcpu, reg, val);
3239 } else
3240 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3241 skip_emulated_instruction(vcpu);
3242 return 1;
3243}
3244
020df079
GN		 3245static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3246{
3247 vmcs_writel(GUEST_DR7, val);
3248}
3249
851ba692 3250static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3251{
06465c5a
AK		 3252 kvm_emulate_cpuid(vcpu);
3253 return 1;
6aa8b732
AK		 3254}
3255
851ba692 3256static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3257{
ad312c7c 3258 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3259 u64 data;
3260
3261 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3262 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3263 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3264 return 1;
3265 }
3266
229456fc 3267 trace_kvm_msr_read(ecx, data);
2714d1d3 3268
6aa8b732 3269 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3270 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3271 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3272 skip_emulated_instruction(vcpu);
3273 return 1;
3274}
3275
851ba692 3276static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3277{
ad312c7c
ZX		 3278 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3279 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3280 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3281
3282 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3283 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3284 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3285 return 1;
3286 }
3287
59200273 3288 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3289 skip_emulated_instruction(vcpu);
3290 return 1;
3291}
3292
851ba692 3293static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3294{
3295 return 1;
3296}
3297
851ba692 3298static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3299{
85f455f7
ED		 3300 u32 cpu_based_vm_exec_control;
3301
3302 /* clear pending irq */
3303 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3304 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3305 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3306
a26bf12a 3307 ++vcpu->stat.irq_window_exits;
2714d1d3 3308
c1150d8c
DL		 3309 /*
3310 * If the user space waits to inject interrupts, exit as soon as
3311 * possible
3312 */
8061823a 3313 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3314 vcpu->run->request_interrupt_window &&
8061823a 3315 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3316 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3317 return 0;
3318 }
6aa8b732
AK		 3319 return 1;
3320}
3321
851ba692 3322static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3323{
3324 skip_emulated_instruction(vcpu);
d3bef15f 3325 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3326}
3327
851ba692 3328static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3329{
510043da 3330 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3331 kvm_emulate_hypercall(vcpu);
3332 return 1;
c21415e8
IM		 3333}
3334
851ba692 3335static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3336{
3337 kvm_queue_exception(vcpu, UD_VECTOR);
3338 return 1;
3339}
3340
851ba692 3341static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3342{
f9c617f6 3343 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3344
3345 kvm_mmu_invlpg(vcpu, exit_qualification);
3346 skip_emulated_instruction(vcpu);
3347 return 1;
3348}
3349
851ba692 3350static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3351{
3352 skip_emulated_instruction(vcpu);
3353 /* TODO: Add support for VT-d/pass-through device */
3354 return 1;
3355}
3356
851ba692 3357static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3358{
6d77dbfc 3359 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
f78e0e2e
SY		 3360}
3361
851ba692 3362static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3363{
60637aac 3364 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3365 unsigned long exit_qualification;
e269fb21
JK		 3366 bool has_error_code = false;
3367 u32 error_code = 0;
37817f29 3368 u16 tss_selector;
64a7ec06
GN		 3369 int reason, type, idt_v;
3370
3371 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3372 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3373
3374 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3375
3376 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3377 if (reason == TASK_SWITCH_GATE && idt_v) {
3378 switch (type) {
3379 case INTR_TYPE_NMI_INTR:
3380 vcpu->arch.nmi_injected = false;
3381 if (cpu_has_virtual_nmis())
3382 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3383 GUEST_INTR_STATE_NMI);
3384 break;
3385 case INTR_TYPE_EXT_INTR:
66fd3f7f 3386 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3387 kvm_clear_interrupt_queue(vcpu);
3388 break;
3389 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3390 if (vmx->idt_vectoring_info &
3391 VECTORING_INFO_DELIVER_CODE_MASK) {
3392 has_error_code = true;
3393 error_code =
3394 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3395 }
3396 /* fall through */
64a7ec06
GN		 3397 case INTR_TYPE_SOFT_EXCEPTION:
3398 kvm_clear_exception_queue(vcpu);
3399 break;
3400 default:
3401 break;
3402 }
60637aac 3403 }
37817f29
IE		 3404 tss_selector = exit_qualification;
3405
64a7ec06
GN		 3406 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3407 type != INTR_TYPE_EXT_INTR &&
3408 type != INTR_TYPE_NMI_INTR))
3409 skip_emulated_instruction(vcpu);
3410
acb54517
GN		 3411 if (kvm_task_switch(vcpu, tss_selector, reason,
3412 has_error_code, error_code) == EMULATE_FAIL) {
3413 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3414 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3415 vcpu->run->internal.ndata = 0;
42dbaa5a 3416 return 0;
acb54517 3417 }
42dbaa5a
JK		 3418
3419 /* clear all local breakpoint enable flags */
3420 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3421
3422 /*
3423 * TODO: What about debug traps on tss switch?
3424 * Are we supposed to inject them and update dr6?
3425 */
3426
3427 return 1;
37817f29
IE		 3428}
3429
851ba692 3430static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3431{
f9c617f6 3432 unsigned long exit_qualification;
1439442c 3433 gpa_t gpa;
1439442c 3434 int gla_validity;
1439442c 3435
f9c617f6 3436 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3437
3438 if (exit_qualification & (1 << 6)) {
3439 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3440 return -EINVAL;
1439442c
SY		 3441 }
3442
3443 gla_validity = (exit_qualification >> 7) & 0x3;
3444 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3445 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3446 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3447 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3448 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3449 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3450 (long unsigned int)exit_qualification);
851ba692
AK		 3451 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3452 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3453 return 0;
1439442c
SY		 3454 }
3455
3456 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3457 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3458 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3459}
3460
68f89400
MT		 3461static u64 ept_rsvd_mask(u64 spte, int level)
3462{
3463 int i;
3464 u64 mask = 0;
3465
3466 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3467 mask |= (1ULL << i);
3468
3469 if (level > 2)
3470 /* bits 7:3 reserved */
3471 mask |= 0xf8;
3472 else if (level == 2) {
3473 if (spte & (1ULL << 7))
3474 /* 2MB ref, bits 20:12 reserved */
3475 mask |= 0x1ff000;
3476 else
3477 /* bits 6:3 reserved */
3478 mask |= 0x78;
3479 }
3480
3481 return mask;
3482}
3483
3484static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3485 int level)
3486{
3487 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3488
3489 /* 010b (write-only) */
3490 WARN_ON((spte & 0x7) == 0x2);
3491
3492 /* 110b (write/execute) */
3493 WARN_ON((spte & 0x7) == 0x6);
3494
3495 /* 100b (execute-only) and value not supported by logical processor */
3496 if (!cpu_has_vmx_ept_execute_only())
3497 WARN_ON((spte & 0x7) == 0x4);
3498
3499 /* not 000b */
3500 if ((spte & 0x7)) {
3501 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3502
3503 if (rsvd_bits != 0) {
3504 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3505 __func__, rsvd_bits);
3506 WARN_ON(1);
3507 }
3508
3509 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3510 u64 ept_mem_type = (spte & 0x38) >> 3;
3511
3512 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3513 ept_mem_type == 7) {
3514 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3515 __func__, ept_mem_type);
3516 WARN_ON(1);
3517 }
3518 }
3519 }
3520}
3521
851ba692 3522static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3523{
3524 u64 sptes[4];
3525 int nr_sptes, i;
3526 gpa_t gpa;
3527
3528 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3529
3530 printk(KERN_ERR "EPT: Misconfiguration.\n");
3531 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3532
3533 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3534
3535 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3536 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3537
851ba692
AK		 3538 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3539 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3540
3541 return 0;
3542}
3543
851ba692 3544static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3545{
3546 u32 cpu_based_vm_exec_control;
3547
3548 /* clear pending NMI */
3549 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3550 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3551 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3552 ++vcpu->stat.nmi_window_exits;
3553
3554 return 1;
3555}
3556
80ced186 3557static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3558{
8b3079a5
AK		 3559 struct vcpu_vmx *vmx = to_vmx(vcpu);
3560 enum emulation_result err = EMULATE_DONE;
80ced186 3561 int ret = 1;
ea953ef0
MG		 3562
3563 while (!guest_state_valid(vcpu)) {
851ba692 3564 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3565
80ced186
MG		 3566 if (err == EMULATE_DO_MMIO) {
3567 ret = 0;
3568 goto out;
3569 }
1d5a4d9b 3570
6d77dbfc
GN		 3571 if (err != EMULATE_DONE)
3572 return 0;
ea953ef0
MG		 3573
3574 if (signal_pending(current))
80ced186 3575 goto out;
ea953ef0
MG		 3576 if (need_resched())
3577 schedule();
3578 }
3579
80ced186
MG		 3580 vmx->emulation_required = 0;
3581out:
3582 return ret;
ea953ef0
MG		 3583}
3584
4b8d54f9
ZE		 3585/*
3586 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3587 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3588 */
9fb41ba8 3589static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3590{
3591 skip_emulated_instruction(vcpu);
3592 kvm_vcpu_on_spin(vcpu);
3593
3594 return 1;
3595}
3596
59708670
SY		 3597static int handle_invalid_op(struct kvm_vcpu *vcpu)
3598{
3599 kvm_queue_exception(vcpu, UD_VECTOR);
3600 return 1;
3601}
3602
6aa8b732
AK		 3603/*
3604 * The exit handlers return 1 if the exit was handled fully and guest execution
3605 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3606 * to be done to userspace and return 0.
3607 */
851ba692 3608static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3609 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3610 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3611 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3612 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3613 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3614 [EXIT_REASON_CR_ACCESS] = handle_cr,
3615 [EXIT_REASON_DR_ACCESS] = handle_dr,
3616 [EXIT_REASON_CPUID] = handle_cpuid,
3617 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3618 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3619 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3620 [EXIT_REASON_HLT] = handle_halt,
a7052897 3621 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3622 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3623 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3624 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3625 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3626 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3627 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3628 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3629 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3630 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3631 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3632 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3633 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3634 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3635 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3636 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3637 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3638 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3639 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3640 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3641 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3642};
3643
3644static const int kvm_vmx_max_exit_handlers =
50a3485c 3645 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3646
3647/*
3648 * The guest has exited. See if we can fix it or if we need userspace
3649 * assistance.
3650 */
851ba692 3651static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3652{
29bd8a78 3653 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3654 u32 exit_reason = vmx->exit_reason;
1155f76a 3655 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3656
5bfd8b54 3657 trace_kvm_exit(exit_reason, vcpu);
2714d1d3 3658
80ced186
MG		 3659 /* If guest state is invalid, start emulating */
3660 if (vmx->emulation_required && emulate_invalid_guest_state)
3661 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3662
1439442c
SY		 3663 /* Access CR3 don't cause VMExit in paging mode, so we need
3664 * to sync with guest real CR3. */
6de4f3ad 3665 if (enable_ept && is_paging(vcpu))
1439442c 3666 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3667
5120702e
MG		 3668 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3669 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3670 vcpu->run->fail_entry.hardware_entry_failure_reason
3671 = exit_reason;
3672 return 0;
3673 }
3674
29bd8a78 3675 if (unlikely(vmx->fail)) {
851ba692
AK		 3676 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3677 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3678 = vmcs_read32(VM_INSTRUCTION_ERROR);
3679 return 0;
3680 }
6aa8b732 3681
d77c26fc 3682 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3683 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3684 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3685 exit_reason != EXIT_REASON_TASK_SWITCH))
3686 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3687 "(0x%x) and exit reason is 0x%x\n",
3688 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3689
3690 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3691 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3692 vmx->soft_vnmi_blocked = 0;
3b86cd99 3693 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3694 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3695 /*
3696 * This CPU don't support us in finding the end of an
3697 * NMI-blocked window if the guest runs with IRQs
3698 * disabled. So we pull the trigger after 1 s of
3699 * futile waiting, but inform the user about this.
3700 */
3701 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3702 "state on VCPU %d after 1 s timeout\n",
3703 __func__, vcpu->vcpu_id);
3704 vmx->soft_vnmi_blocked = 0;
3b86cd99 3705 }
3b86cd99
JK		 3706 }
3707
6aa8b732
AK		 3708 if (exit_reason < kvm_vmx_max_exit_handlers
3709 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3710 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3711 else {
851ba692
AK		 3712 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3713 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3714 }
3715 return 0;
3716}
3717
95ba8273 3718static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3719{
95ba8273 3720 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3721 vmcs_write32(TPR_THRESHOLD, 0);
3722 return;
3723 }
3724
95ba8273 3725 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3726}
3727
cf393f75
AK		 3728static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3729{
3730 u32 exit_intr_info;
7b4a25cb 3731 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3732 bool unblock_nmi;
3733 u8 vector;
668f612f
AK		 3734 int type;
3735 bool idtv_info_valid;
cf393f75
AK		 3736
3737 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3738
a0861c02
AK		 3739 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3740
3741 /* Handle machine checks before interrupts are enabled */
3742 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3743 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3744 && is_machine_check(exit_intr_info)))
3745 kvm_machine_check();
3746
20f65983
GN		 3747 /* We need to handle NMIs before interrupts are enabled */
3748 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3749 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3750 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3751 asm("int $2");
ff9d07a0
ZY		 3752 kvm_after_handle_nmi(&vmx->vcpu);
3753 }
20f65983
GN		 3754
3755 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3756
cf393f75
AK		 3757 if (cpu_has_virtual_nmis()) {
3758 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3759 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3760 /*
7b4a25cb 3761 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3762 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3763 * a guest IRET fault.
7b4a25cb
GN		 3764 * SDM 3: 23.2.2 (September 2008)
3765 * Bit 12 is undefined in any of the following cases:
3766 * If the VM exit sets the valid bit in the IDT-vectoring
3767 * information field.
3768 * If the VM exit is due to a double fault.
cf393f75 3769 */
7b4a25cb
GN		 3770 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3771 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3772 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3773 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3774 } else if (unlikely(vmx->soft_vnmi_blocked))
3775 vmx->vnmi_blocked_time +=
3776 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3777
37b96e98
GN		 3778 vmx->vcpu.arch.nmi_injected = false;
3779 kvm_clear_exception_queue(&vmx->vcpu);
3780 kvm_clear_interrupt_queue(&vmx->vcpu);
3781
3782 if (!idtv_info_valid)
3783 return;
3784
668f612f
AK		 3785 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3786 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3787
64a7ec06 3788 switch (type) {
37b96e98
GN		 3789 case INTR_TYPE_NMI_INTR:
3790 vmx->vcpu.arch.nmi_injected = true;
668f612f 3791 /*
7b4a25cb 3792 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3793 * Clear bit "block by NMI" before VM entry if a NMI
3794 * delivery faulted.
668f612f 3795 */
37b96e98
GN		 3796 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3797 GUEST_INTR_STATE_NMI);
3798 break;
37b96e98 3799 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3800 vmx->vcpu.arch.event_exit_inst_len =
3801 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3802 /* fall through */
3803 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3804 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3805 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3806 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3807 } else
3808 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3809 break;
66fd3f7f
GN		 3810 case INTR_TYPE_SOFT_INTR:
3811 vmx->vcpu.arch.event_exit_inst_len =
3812 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3813 /* fall through */
37b96e98 3814 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3815 kvm_queue_interrupt(&vmx->vcpu, vector,
3816 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3817 break;
3818 default:
3819 break;
f7d9238f 3820 }
cf393f75
AK		 3821}
3822
9c8cba37
AK		 3823/*
3824 * Failure to inject an interrupt should give us the information
3825 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3826 * when fetching the interrupt redirection bitmap in the real-mode
3827 * tss, this doesn't happen. So we do it ourselves.
3828 */
3829static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3830{
3831 vmx->rmode.irq.pending = 0;
5fdbf976 3832 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3833 return;
5fdbf976 3834 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3835 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3836 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3837 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3838 return;
3839 }
3840 vmx->idt_vectoring_info =
3841 VECTORING_INFO_VALID_MASK
3842 | INTR_TYPE_EXT_INTR
3843 | vmx->rmode.irq.vector;
3844}
3845
c801949d
AK		 3846#ifdef CONFIG_X86_64
3847#define R "r"
3848#define Q "q"
3849#else
3850#define R "e"
3851#define Q "l"
3852#endif
3853
851ba692 3854static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3855{
a2fa3e9f 3856 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3857
3b86cd99
JK		 3858 /* Record the guest's net vcpu time for enforced NMI injections. */
3859 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3860 vmx->entry_time = ktime_get();
3861
80ced186
MG		 3862 /* Don't enter VMX if guest state is invalid, let the exit handler
3863 start emulation until we arrive back to a valid state */
3864 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3865 return;
a89a8fb9 3866
5fdbf976
MT		 3867 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3868 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3869 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3870 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3871
787ff736
GN		 3872 /* When single-stepping over STI and MOV SS, we must clear the
3873 * corresponding interruptibility bits in the guest state. Otherwise
3874 * vmentry fails as it then expects bit 14 (BS) in pending debug
3875 * exceptions being set, but that's not correct for the guest debugging
3876 * case. */
3877 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3878 vmx_set_interrupt_shadow(vcpu, 0);
3879
d77c26fc 3880 asm(
6aa8b732 3881 /* Store host registers */
c801949d
AK		 3882 "push %%"R"dx; push %%"R"bp;"
3883 "push %%"R"cx \n\t"
313dbd49
AK		 3884 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3885 "je 1f \n\t"
3886 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3887 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3888 "1: \n\t"
d3edefc0
AK		 3889 /* Reload cr2 if changed */
3890 "mov %c[cr2](%0), %%"R"ax \n\t"
3891 "mov %%cr2, %%"R"dx \n\t"
3892 "cmp %%"R"ax, %%"R"dx \n\t"
3893 "je 2f \n\t"
3894 "mov %%"R"ax, %%cr2 \n\t"
3895 "2: \n\t"
6aa8b732 3896 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3897 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3898 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3899 "mov %c[rax](%0), %%"R"ax \n\t"
3900 "mov %c[rbx](%0), %%"R"bx \n\t"
3901 "mov %c[rdx](%0), %%"R"dx \n\t"
3902 "mov %c[rsi](%0), %%"R"si \n\t"
3903 "mov %c[rdi](%0), %%"R"di \n\t"
3904 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3905#ifdef CONFIG_X86_64
e08aa78a
AK		 3906 "mov %c[r8](%0), %%r8 \n\t"
3907 "mov %c[r9](%0), %%r9 \n\t"
3908 "mov %c[r10](%0), %%r10 \n\t"
3909 "mov %c[r11](%0), %%r11 \n\t"
3910 "mov %c[r12](%0), %%r12 \n\t"
3911 "mov %c[r13](%0), %%r13 \n\t"
3912 "mov %c[r14](%0), %%r14 \n\t"
3913 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3914#endif
c801949d
AK		 3915 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3916
6aa8b732 3917 /* Enter guest mode */
cd2276a7 3918 "jne .Llaunched \n\t"
4ecac3fd 3919 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3920 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3921 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3922 ".Lkvm_vmx_return: "
6aa8b732 3923 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3924 "xchg %0, (%%"R"sp) \n\t"
3925 "mov %%"R"ax, %c[rax](%0) \n\t"
3926 "mov %%"R"bx, %c[rbx](%0) \n\t"
3927 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3928 "mov %%"R"dx, %c[rdx](%0) \n\t"
3929 "mov %%"R"si, %c[rsi](%0) \n\t"
3930 "mov %%"R"di, %c[rdi](%0) \n\t"
3931 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3932#ifdef CONFIG_X86_64
e08aa78a
AK		 3933 "mov %%r8, %c[r8](%0) \n\t"
3934 "mov %%r9, %c[r9](%0) \n\t"
3935 "mov %%r10, %c[r10](%0) \n\t"
3936 "mov %%r11, %c[r11](%0) \n\t"
3937 "mov %%r12, %c[r12](%0) \n\t"
3938 "mov %%r13, %c[r13](%0) \n\t"
3939 "mov %%r14, %c[r14](%0) \n\t"
3940 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3941#endif
c801949d
AK		 3942 "mov %%cr2, %%"R"ax \n\t"
3943 "mov %%"R"ax, %c[cr2](%0) \n\t"
3944
3945 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3946 "setbe %c[fail](%0) \n\t"
3947 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3948 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3949 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3950 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3951 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3952 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3953 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3954 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3955 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3956 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3957 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3958#ifdef CONFIG_X86_64
ad312c7c
ZX		 3959 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3960 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3961 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3962 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3963 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3964 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3965 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3966 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3967#endif
ad312c7c 3968 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3969 : "cc", "memory"
c801949d 3970 , R"bx", R"di", R"si"
c2036300 3971#ifdef CONFIG_X86_64
c2036300
LV		 3972 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3973#endif
3974 );
6aa8b732 3975
6de4f3ad
AK		 3976 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3977 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3978 vcpu->arch.regs_dirty = 0;
3979
1155f76a 3980 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3981 if (vmx->rmode.irq.pending)
3982 fixup_rmode_irq(vmx);
1155f76a 3983
d77c26fc 3984 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3985 vmx->launched = 1;
1b6269db 3986
cf393f75 3987 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3988}
3989
c801949d
AK		 3990#undef R
3991#undef Q
3992
6aa8b732
AK		 3993static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3994{
a2fa3e9f
GH		 3995 struct vcpu_vmx *vmx = to_vmx(vcpu);
3996
3997 if (vmx->vmcs) {
543e4243 3998 vcpu_clear(vmx);
a2fa3e9f
GH		 3999 free_vmcs(vmx->vmcs);
4000 vmx->vmcs = NULL;
6aa8b732
AK		 4001 }
4002}
4003
4004static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4005{
fb3f0f51
RR		 4006 struct vcpu_vmx *vmx = to_vmx(vcpu);
4007
cdbecfc3 4008 free_vpid(vmx);
6aa8b732 4009 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4010 kfree(vmx->guest_msrs);
4011 kvm_vcpu_uninit(vcpu);
a4770347 4012 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4013}
4014
4610c9cc
DX		 4015static inline void vmcs_init(struct vmcs *vmcs)
4016{
4017 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4018
4019 if (!vmm_exclusive)
4020 kvm_cpu_vmxon(phys_addr);
4021
4022 vmcs_clear(vmcs);
4023
4024 if (!vmm_exclusive)
4025 kvm_cpu_vmxoff();
4026}
4027
fb3f0f51 4028static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4029{
fb3f0f51 4030 int err;
c16f862d 4031 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4032 int cpu;
6aa8b732 4033
a2fa3e9f 4034 if (!vmx)
fb3f0f51
RR		 4035 return ERR_PTR(-ENOMEM);
4036
2384d2b3
SY		 4037 allocate_vpid(vmx);
4038
fb3f0f51
RR		 4039 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4040 if (err)
4041 goto free_vcpu;
965b58a5 4042
a2fa3e9f 4043 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4044 if (!vmx->guest_msrs) {
4045 err = -ENOMEM;
4046 goto uninit_vcpu;
4047 }
965b58a5 4048
a2fa3e9f
GH		 4049 vmx->vmcs = alloc_vmcs();
4050 if (!vmx->vmcs)
fb3f0f51 4051 goto free_msrs;
a2fa3e9f 4052
4610c9cc 4053 vmcs_init(vmx->vmcs);
a2fa3e9f 4054
15ad7146
AK		 4055 cpu = get_cpu();
4056 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 4057 err = vmx_vcpu_setup(vmx);
fb3f0f51 4058 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4059 put_cpu();
fb3f0f51
RR		 4060 if (err)
4061 goto free_vmcs;
5e4a0b3c
MT		 4062 if (vm_need_virtualize_apic_accesses(kvm))
4063 if (alloc_apic_access_page(kvm) != 0)
4064 goto free_vmcs;
fb3f0f51 4065
b927a3ce
SY		 4066 if (enable_ept) {
4067 if (!kvm->arch.ept_identity_map_addr)
4068 kvm->arch.ept_identity_map_addr =
4069 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4070 if (alloc_identity_pagetable(kvm) != 0)
4071 goto free_vmcs;
b927a3ce 4072 }
b7ebfb05 4073
fb3f0f51
RR		 4074 return &vmx->vcpu;
4075
4076free_vmcs:
4077 free_vmcs(vmx->vmcs);
4078free_msrs:
fb3f0f51
RR		 4079 kfree(vmx->guest_msrs);
4080uninit_vcpu:
4081 kvm_vcpu_uninit(&vmx->vcpu);
4082free_vcpu:
cdbecfc3 4083 free_vpid(vmx);
a4770347 4084 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4085 return ERR_PTR(err);
6aa8b732
AK		 4086}
4087
002c7f7c
YS		 4088static void __init vmx_check_processor_compat(void *rtn)
4089{
4090 struct vmcs_config vmcs_conf;
4091
4092 *(int *)rtn = 0;
4093 if (setup_vmcs_config(&vmcs_conf) < 0)
4094 *(int *)rtn = -EIO;
4095 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4096 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4097 smp_processor_id());
4098 *(int *)rtn = -EIO;
4099 }
4100}
4101
67253af5
SY		 4102static int get_ept_level(void)
4103{
4104 return VMX_EPT_DEFAULT_GAW + 1;
4105}
4106
4b12f0de 4107static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4108{
4b12f0de
SY		 4109 u64 ret;
4110
522c68c4
SY		 4111 /* For VT-d and EPT combination
4112 * 1. MMIO: always map as UC
4113 * 2. EPT with VT-d:
4114 * a. VT-d without snooping control feature: can't guarantee the
4115 * result, try to trust guest.
4116 * b. VT-d with snooping control feature: snooping control feature of
4117 * VT-d engine can guarantee the cache correctness. Just set it
4118 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4119 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4120 * consistent with host MTRR
4121 */
4b12f0de
SY		 4122 if (is_mmio)
4123 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4124 else if (vcpu->kvm->arch.iommu_domain &&
4125 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4126 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4127 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4128 else
522c68c4 4129 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4130 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4131
4132 return ret;
64d4d521
SY		 4133}
4134
f4c9e87c
AK		 4135#define _ER(x) { EXIT_REASON_##x, #x }
4136
229456fc 4137static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4138 _ER(EXCEPTION_NMI),
4139 _ER(EXTERNAL_INTERRUPT),
4140 _ER(TRIPLE_FAULT),
4141 _ER(PENDING_INTERRUPT),
4142 _ER(NMI_WINDOW),
4143 _ER(TASK_SWITCH),
4144 _ER(CPUID),
4145 _ER(HLT),
4146 _ER(INVLPG),
4147 _ER(RDPMC),
4148 _ER(RDTSC),
4149 _ER(VMCALL),
4150 _ER(VMCLEAR),
4151 _ER(VMLAUNCH),
4152 _ER(VMPTRLD),
4153 _ER(VMPTRST),
4154 _ER(VMREAD),
4155 _ER(VMRESUME),
4156 _ER(VMWRITE),
4157 _ER(VMOFF),
4158 _ER(VMON),
4159 _ER(CR_ACCESS),
4160 _ER(DR_ACCESS),
4161 _ER(IO_INSTRUCTION),
4162 _ER(MSR_READ),
4163 _ER(MSR_WRITE),
4164 _ER(MWAIT_INSTRUCTION),
4165 _ER(MONITOR_INSTRUCTION),
4166 _ER(PAUSE_INSTRUCTION),
4167 _ER(MCE_DURING_VMENTRY),
4168 _ER(TPR_BELOW_THRESHOLD),
4169 _ER(APIC_ACCESS),
4170 _ER(EPT_VIOLATION),
4171 _ER(EPT_MISCONFIG),
4172 _ER(WBINVD),
229456fc
MT		 4173 { -1, NULL }
4174};
4175
f4c9e87c
AK		 4176#undef _ER
4177
17cc3935 4178static int vmx_get_lpage_level(void)
344f414f 4179{
878403b7
SY		 4180 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4181 return PT_DIRECTORY_LEVEL;
4182 else
4183 /* For shadow and EPT supported 1GB page */
4184 return PT_PDPE_LEVEL;
344f414f
JR		 4185}
4186
4e47c7a6
SY		 4187static inline u32 bit(int bitno)
4188{
4189 return 1 << (bitno & 31);
4190}
4191
0e851880
SY		 4192static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4193{
4e47c7a6
SY		 4194 struct kvm_cpuid_entry2 *best;
4195 struct vcpu_vmx *vmx = to_vmx(vcpu);
4196 u32 exec_control;
4197
4198 vmx->rdtscp_enabled = false;
4199 if (vmx_rdtscp_supported()) {
4200 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4201 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4202 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4203 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4204 vmx->rdtscp_enabled = true;
4205 else {
4206 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4207 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4208 exec_control);
4209 }
4210 }
4211 }
0e851880
SY		 4212}
4213
d4330ef2
JR		 4214static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4215{
4216}
4217
cbdd1bea 4218static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4219 .cpu_has_kvm_support = cpu_has_kvm_support,
4220 .disabled_by_bios = vmx_disabled_by_bios,
4221 .hardware_setup = hardware_setup,
4222 .hardware_unsetup = hardware_unsetup,
002c7f7c 4223 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4224 .hardware_enable = hardware_enable,
4225 .hardware_disable = hardware_disable,
04547156 4226 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4227
4228 .vcpu_create = vmx_create_vcpu,
4229 .vcpu_free = vmx_free_vcpu,
04d2cc77 4230 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4231
04d2cc77 4232 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4233 .vcpu_load = vmx_vcpu_load,
4234 .vcpu_put = vmx_vcpu_put,
4235
4236 .set_guest_debug = set_guest_debug,
4237 .get_msr = vmx_get_msr,
4238 .set_msr = vmx_set_msr,
4239 .get_segment_base = vmx_get_segment_base,
4240 .get_segment = vmx_get_segment,
4241 .set_segment = vmx_set_segment,
2e4d2653 4242 .get_cpl = vmx_get_cpl,
6aa8b732 4243 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4244 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4245 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4246 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4247 .set_cr3 = vmx_set_cr3,
4248 .set_cr4 = vmx_set_cr4,
6aa8b732 4249 .set_efer = vmx_set_efer,
6aa8b732
AK		 4250 .get_idt = vmx_get_idt,
4251 .set_idt = vmx_set_idt,
4252 .get_gdt = vmx_get_gdt,
4253 .set_gdt = vmx_set_gdt,
020df079 4254 .set_dr7 = vmx_set_dr7,
5fdbf976 4255 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4256 .get_rflags = vmx_get_rflags,
4257 .set_rflags = vmx_set_rflags,
ebcbab4c 4258 .fpu_activate = vmx_fpu_activate,
02daab21 4259 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4260
4261 .tlb_flush = vmx_flush_tlb,
6aa8b732 4262
6aa8b732 4263 .run = vmx_vcpu_run,
6062d012 4264 .handle_exit = vmx_handle_exit,
6aa8b732 4265 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4266 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4267 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4268 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4269 .set_irq = vmx_inject_irq,
95ba8273 4270 .set_nmi = vmx_inject_nmi,
298101da 4271 .queue_exception = vmx_queue_exception,
78646121 4272 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4273 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4274 .get_nmi_mask = vmx_get_nmi_mask,
4275 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4276 .enable_nmi_window = enable_nmi_window,
4277 .enable_irq_window = enable_irq_window,
4278 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4279
cbc94022 4280 .set_tss_addr = vmx_set_tss_addr,
67253af5 4281 .get_tdp_level = get_ept_level,
4b12f0de 4282 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4283
4284 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4285 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4286
4287 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4288
4289 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4290
4291 .set_supported_cpuid = vmx_set_supported_cpuid,
6aa8b732
AK		 4292};
4293
4294static int __init vmx_init(void)
4295{
26bb0981
AK		 4296 int r, i;
4297
4298 rdmsrl_safe(MSR_EFER, &host_efer);
4299
4300 for (i = 0; i < NR_VMX_MSR; ++i)
4301 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4302
3e7c73e9 4303 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4304 if (!vmx_io_bitmap_a)
4305 return -ENOMEM;
4306
3e7c73e9 4307 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4308 if (!vmx_io_bitmap_b) {
4309 r = -ENOMEM;
4310 goto out;
4311 }
4312
5897297b
AK		 4313 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4314 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4315 r = -ENOMEM;
4316 goto out1;
4317 }
4318
5897297b
AK		 4319 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4320 if (!vmx_msr_bitmap_longmode) {
4321 r = -ENOMEM;
4322 goto out2;
4323 }
4324
fdef3ad1
HQ		 4325 /*
4326 * Allow direct access to the PC debug port (it is often used for I/O
4327 * delays, but the vmexits simply slow things down).
4328 */
3e7c73e9
AK		 4329 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4330 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4331
3e7c73e9 4332 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4333
5897297b
AK		 4334 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4335 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4336
2384d2b3
SY		 4337 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4338
0ee75bea
AK		 4339 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4340 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4341 if (r)
5897297b 4342 goto out3;
25c5f225 4343
5897297b
AK		 4344 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4345 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4346 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4347 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4348 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4349 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4350
089d034e 4351 if (enable_ept) {
1439442c 4352 bypass_guest_pf = 0;
5fdbcb9d 4353 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4354 VMX_EPT_WRITABLE_MASK);
534e38b4 4355 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4356 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4357 kvm_enable_tdp();
4358 } else
4359 kvm_disable_tdp();
1439442c 4360
c7addb90
AK		 4361 if (bypass_guest_pf)
4362 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4363
fdef3ad1
HQ		 4364 return 0;
4365
5897297b
AK		 4366out3:
4367 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4368out2:
5897297b 4369 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4370out1:
3e7c73e9 4371 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4372out:
3e7c73e9 4373 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4374 return r;
6aa8b732
AK		 4375}
4376
4377static void __exit vmx_exit(void)
4378{
5897297b
AK		 4379 free_page((unsigned long)vmx_msr_bitmap_legacy);
4380 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4381 free_page((unsigned long)vmx_io_bitmap_b);
4382 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4383
cb498ea2 4384 kvm_exit();
6aa8b732
AK		 4385}
4386
4387module_init(vmx_init)
4388module_exit(vmx_exit)
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