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KVM: x86: Convert TSC writes to TSC offset writes
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
221d059d 8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
cdc0e244
AK		 72#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74#define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 77 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 78#define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 80#define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
82 | X86_CR4_OSXMMEXCPT)
83
cdc0e244
AK		 84#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
86
78ac8b47
AK		 87#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
88
4b8d54f9
ZE		 89/*
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
99 */
100#define KVM_VMX_DEFAULT_PLE_GAP 41
101#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103module_param(ple_gap, int, S_IRUGO);
104
105static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106module_param(ple_window, int, S_IRUGO);
107
61d2ef2c
AK		 108#define NR_AUTOLOAD_MSRS 1
109
a2fa3e9f
GH		 110struct vmcs {
111 u32 revision_id;
112 u32 abort;
113 char data[0];
114};
115
26bb0981
AK		 116struct shared_msr_entry {
117 unsigned index;
118 u64 data;
d5696725 119 u64 mask;
26bb0981
AK		 120};
121
a2fa3e9f 122struct vcpu_vmx {
fb3f0f51 123 struct kvm_vcpu vcpu;
543e4243 124 struct list_head local_vcpus_link;
313dbd49 125 unsigned long host_rsp;
a2fa3e9f 126 int launched;
29bd8a78 127 u8 fail;
1155f76a 128 u32 idt_vectoring_info;
26bb0981 129 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 130 int nmsrs;
131 int save_nmsrs;
a2fa3e9f 132#ifdef CONFIG_X86_64
44ea2b17
AK		 133 u64 msr_host_kernel_gs_base;
134 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 135#endif
136 struct vmcs *vmcs;
61d2ef2c
AK		 137 struct msr_autoload {
138 unsigned nr;
139 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
140 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
141 } msr_autoload;
a2fa3e9f
GH		 142 struct {
143 int loaded;
144 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 145 int gs_ldt_reload_needed;
146 int fs_reload_needed;
d77c26fc 147 } host_state;
9c8cba37 148 struct {
7ffd92c5 149 int vm86_active;
78ac8b47 150 ulong save_rflags;
7ffd92c5
AK		 151 struct kvm_save_segment {
152 u16 selector;
153 unsigned long base;
154 u32 limit;
155 u32 ar;
156 } tr, es, ds, fs, gs;
9c8cba37
AK		 157 struct {
158 bool pending;
159 u8 vector;
160 unsigned rip;
161 } irq;
162 } rmode;
2384d2b3 163 int vpid;
04fa4d32 164 bool emulation_required;
3b86cd99
JK		 165
166 /* Support for vnmi-less CPUs */
167 int soft_vnmi_blocked;
168 ktime_t entry_time;
169 s64 vnmi_blocked_time;
a0861c02 170 u32 exit_reason;
4e47c7a6
SY		 171
172 bool rdtscp_enabled;
a2fa3e9f
GH		 173};
174
175static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
176{
fb3f0f51 177 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 178}
179
b7ebfb05 180static int init_rmode(struct kvm *kvm);
4e1096d2 181static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 182static void kvm_cpu_vmxon(u64 addr);
183static void kvm_cpu_vmxoff(void);
75880a01 184
6aa8b732
AK		 185static DEFINE_PER_CPU(struct vmcs *, vmxarea);
186static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 187static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
3444d7da 188static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 189
3e7c73e9
AK		 190static unsigned long *vmx_io_bitmap_a;
191static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 192static unsigned long *vmx_msr_bitmap_legacy;
193static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 194
2384d2b3
SY		 195static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
196static DEFINE_SPINLOCK(vmx_vpid_lock);
197
1c3d14fe 198static struct vmcs_config {
6aa8b732
AK		 199 int size;
200 int order;
201 u32 revision_id;
1c3d14fe
YS		 202 u32 pin_based_exec_ctrl;
203 u32 cpu_based_exec_ctrl;
f78e0e2e 204 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 205 u32 vmexit_ctrl;
206 u32 vmentry_ctrl;
207} vmcs_config;
6aa8b732 208
efff9e53 209static struct vmx_capability {
d56f546d
SY		 210 u32 ept;
211 u32 vpid;
212} vmx_capability;
213
6aa8b732
AK		 214#define VMX_SEGMENT_FIELD(seg) \
215 [VCPU_SREG_##seg] = { \
216 .selector = GUEST_##seg##_SELECTOR, \
217 .base = GUEST_##seg##_BASE, \
218 .limit = GUEST_##seg##_LIMIT, \
219 .ar_bytes = GUEST_##seg##_AR_BYTES, \
220 }
221
222static struct kvm_vmx_segment_field {
223 unsigned selector;
224 unsigned base;
225 unsigned limit;
226 unsigned ar_bytes;
227} kvm_vmx_segment_fields[] = {
228 VMX_SEGMENT_FIELD(CS),
229 VMX_SEGMENT_FIELD(DS),
230 VMX_SEGMENT_FIELD(ES),
231 VMX_SEGMENT_FIELD(FS),
232 VMX_SEGMENT_FIELD(GS),
233 VMX_SEGMENT_FIELD(SS),
234 VMX_SEGMENT_FIELD(TR),
235 VMX_SEGMENT_FIELD(LDTR),
236};
237
26bb0981
AK		 238static u64 host_efer;
239
6de4f3ad
AK		 240static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
241
4d56c8a7 242/*
8c06585d 243 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 244 * away by decrementing the array size.
245 */
6aa8b732 246static const u32 vmx_msr_index[] = {
05b3e0c2 247#ifdef CONFIG_X86_64
44ea2b17 248 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 249#endif
8c06585d 250 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 251};
9d8f549d 252#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 253
31299944 254static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 255{
256 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
257 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 258 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 259}
260
31299944 261static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 262{
263 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
264 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 265 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 266}
267
31299944 268static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 269{
270 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
271 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 272 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 273}
274
31299944 275static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 276{
277 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
278 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
279}
280
31299944 281static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 282{
283 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
284 INTR_INFO_VALID_MASK)) ==
285 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
286}
287
31299944 288static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 289{
04547156 290 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 291}
292
31299944 293static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 294{
04547156 295 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 296}
297
31299944 298static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 299{
04547156 300 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 301}
302
31299944 303static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 304{
04547156
SY		 305 return vmcs_config.cpu_based_exec_ctrl &
306 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 307}
308
774ead3a 309static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 310{
04547156
SY		 311 return vmcs_config.cpu_based_2nd_exec_ctrl &
312 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
313}
314
315static inline bool cpu_has_vmx_flexpriority(void)
316{
317 return cpu_has_vmx_tpr_shadow() &&
318 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 319}
320
e799794e
MT		 321static inline bool cpu_has_vmx_ept_execute_only(void)
322{
31299944 323 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 324}
325
326static inline bool cpu_has_vmx_eptp_uncacheable(void)
327{
31299944 328 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 329}
330
331static inline bool cpu_has_vmx_eptp_writeback(void)
332{
31299944 333 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 334}
335
336static inline bool cpu_has_vmx_ept_2m_page(void)
337{
31299944 338 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 339}
340
878403b7
SY		 341static inline bool cpu_has_vmx_ept_1g_page(void)
342{
31299944 343 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 344}
345
4bc9b982
SY		 346static inline bool cpu_has_vmx_ept_4levels(void)
347{
348 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
349}
350
31299944 351static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 352{
31299944 353 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 354}
355
31299944 356static inline bool cpu_has_vmx_invept_context(void)
d56f546d 357{
31299944 358 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 359}
360
31299944 361static inline bool cpu_has_vmx_invept_global(void)
d56f546d 362{
31299944 363 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 364}
365
518c8aee
GJ		 366static inline bool cpu_has_vmx_invvpid_single(void)
367{
368 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
369}
370
b9d762fa
GJ		 371static inline bool cpu_has_vmx_invvpid_global(void)
372{
373 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
374}
375
31299944 376static inline bool cpu_has_vmx_ept(void)
d56f546d 377{
04547156
SY		 378 return vmcs_config.cpu_based_2nd_exec_ctrl &
379 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 380}
381
31299944 382static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 383{
384 return vmcs_config.cpu_based_2nd_exec_ctrl &
385 SECONDARY_EXEC_UNRESTRICTED_GUEST;
386}
387
31299944 388static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 389{
390 return vmcs_config.cpu_based_2nd_exec_ctrl &
391 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
392}
393
31299944 394static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 395{
6d3e435e 396 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 397}
398
31299944 399static inline bool cpu_has_vmx_vpid(void)
2384d2b3 400{
04547156
SY		 401 return vmcs_config.cpu_based_2nd_exec_ctrl &
402 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 403}
404
31299944 405static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 406{
407 return vmcs_config.cpu_based_2nd_exec_ctrl &
408 SECONDARY_EXEC_RDTSCP;
409}
410
31299944 411static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 412{
413 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
414}
415
f5f48ee1
SY		 416static inline bool cpu_has_vmx_wbinvd_exit(void)
417{
418 return vmcs_config.cpu_based_2nd_exec_ctrl &
419 SECONDARY_EXEC_WBINVD_EXITING;
420}
421
04547156
SY		 422static inline bool report_flexpriority(void)
423{
424 return flexpriority_enabled;
425}
426
8b9cf98c 427static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 428{
429 int i;
430
a2fa3e9f 431 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 432 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 433 return i;
434 return -1;
435}
436
2384d2b3
SY		 437static inline void __invvpid(int ext, u16 vpid, gva_t gva)
438{
439 struct {
440 u64 vpid : 16;
441 u64 rsvd : 48;
442 u64 gva;
443 } operand = { vpid, 0, gva };
444
4ecac3fd 445 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 446 /* CF==1 or ZF==1 --> rc = -1 */
447 "; ja 1f ; ud2 ; 1:"
448 : : "a"(&operand), "c"(ext) : "cc", "memory");
449}
450
1439442c
SY		 451static inline void __invept(int ext, u64 eptp, gpa_t gpa)
452{
453 struct {
454 u64 eptp, gpa;
455 } operand = {eptp, gpa};
456
4ecac3fd 457 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 458 /* CF==1 or ZF==1 --> rc = -1 */
459 "; ja 1f ; ud2 ; 1:\n"
460 : : "a" (&operand), "c" (ext) : "cc", "memory");
461}
462
26bb0981 463static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 464{
465 int i;
466
8b9cf98c 467 i = __find_msr_index(vmx, msr);
a75beee6 468 if (i >= 0)
a2fa3e9f 469 return &vmx->guest_msrs[i];
8b6d44c7 470 return NULL;
7725f0ba
AK		 471}
472
6aa8b732
AK		 473static void vmcs_clear(struct vmcs *vmcs)
474{
475 u64 phys_addr = __pa(vmcs);
476 u8 error;
477
4ecac3fd 478 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 479 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
480 : "cc", "memory");
481 if (error)
482 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
483 vmcs, phys_addr);
484}
485
7725b894
DX		 486static void vmcs_load(struct vmcs *vmcs)
487{
488 u64 phys_addr = __pa(vmcs);
489 u8 error;
490
491 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
492 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
493 : "cc", "memory");
494 if (error)
495 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
496 vmcs, phys_addr);
497}
498
6aa8b732
AK		 499static void __vcpu_clear(void *arg)
500{
8b9cf98c 501 struct vcpu_vmx *vmx = arg;
d3b2c338 502 int cpu = raw_smp_processor_id();
6aa8b732 503
8b9cf98c 504 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 505 vmcs_clear(vmx->vmcs);
506 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 507 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 508 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 509 list_del(&vmx->local_vcpus_link);
510 vmx->vcpu.cpu = -1;
511 vmx->launched = 0;
6aa8b732
AK		 512}
513
8b9cf98c 514static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 515{
eae5ecb5
AK		 516 if (vmx->vcpu.cpu == -1)
517 return;
8691e5a8 518 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 519}
520
1760dd49 521static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 522{
523 if (vmx->vpid == 0)
524 return;
525
518c8aee
GJ		 526 if (cpu_has_vmx_invvpid_single())
527 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 528}
529
b9d762fa
GJ		 530static inline void vpid_sync_vcpu_global(void)
531{
532 if (cpu_has_vmx_invvpid_global())
533 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
534}
535
536static inline void vpid_sync_context(struct vcpu_vmx *vmx)
537{
538 if (cpu_has_vmx_invvpid_single())
1760dd49 539 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 540 else
541 vpid_sync_vcpu_global();
542}
543
1439442c
SY		 544static inline void ept_sync_global(void)
545{
546 if (cpu_has_vmx_invept_global())
547 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
548}
549
550static inline void ept_sync_context(u64 eptp)
551{
089d034e 552 if (enable_ept) {
1439442c
SY		 553 if (cpu_has_vmx_invept_context())
554 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
555 else
556 ept_sync_global();
557 }
558}
559
560static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
561{
089d034e 562 if (enable_ept) {
1439442c
SY		 563 if (cpu_has_vmx_invept_individual_addr())
564 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
565 eptp, gpa);
566 else
567 ept_sync_context(eptp);
568 }
569}
570
6aa8b732
AK		 571static unsigned long vmcs_readl(unsigned long field)
572{
573 unsigned long value;
574
4ecac3fd 575 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 576 : "=a"(value) : "d"(field) : "cc");
577 return value;
578}
579
580static u16 vmcs_read16(unsigned long field)
581{
582 return vmcs_readl(field);
583}
584
585static u32 vmcs_read32(unsigned long field)
586{
587 return vmcs_readl(field);
588}
589
590static u64 vmcs_read64(unsigned long field)
591{
05b3e0c2 592#ifdef CONFIG_X86_64
6aa8b732
AK		 593 return vmcs_readl(field);
594#else
595 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
596#endif
597}
598
e52de1b8
AK		 599static noinline void vmwrite_error(unsigned long field, unsigned long value)
600{
601 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
602 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
603 dump_stack();
604}
605
6aa8b732
AK		 606static void vmcs_writel(unsigned long field, unsigned long value)
607{
608 u8 error;
609
4ecac3fd 610 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 611 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 612 if (unlikely(error))
613 vmwrite_error(field, value);
6aa8b732
AK		 614}
615
616static void vmcs_write16(unsigned long field, u16 value)
617{
618 vmcs_writel(field, value);
619}
620
621static void vmcs_write32(unsigned long field, u32 value)
622{
623 vmcs_writel(field, value);
624}
625
626static void vmcs_write64(unsigned long field, u64 value)
627{
6aa8b732 628 vmcs_writel(field, value);
7682f2d0 629#ifndef CONFIG_X86_64
6aa8b732
AK		 630 asm volatile ("");
631 vmcs_writel(field+1, value >> 32);
632#endif
633}
634
2ab455cc
AL		 635static void vmcs_clear_bits(unsigned long field, u32 mask)
636{
637 vmcs_writel(field, vmcs_readl(field) & ~mask);
638}
639
640static void vmcs_set_bits(unsigned long field, u32 mask)
641{
642 vmcs_writel(field, vmcs_readl(field) | mask);
643}
644
abd3f2d6
AK		 645static void update_exception_bitmap(struct kvm_vcpu *vcpu)
646{
647 u32 eb;
648
fd7373cc
JK		 649 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
650 (1u << NM_VECTOR) | (1u << DB_VECTOR);
651 if ((vcpu->guest_debug &
652 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
653 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
654 eb |= 1u << BP_VECTOR;
7ffd92c5 655 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 656 eb = ~0;
089d034e 657 if (enable_ept)
1439442c 658 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 659 if (vcpu->fpu_active)
660 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 661 vmcs_write32(EXCEPTION_BITMAP, eb);
662}
663
61d2ef2c
AK		 664static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
665{
666 unsigned i;
667 struct msr_autoload *m = &vmx->msr_autoload;
668
669 for (i = 0; i < m->nr; ++i)
670 if (m->guest[i].index == msr)
671 break;
672
673 if (i == m->nr)
674 return;
675 --m->nr;
676 m->guest[i] = m->guest[m->nr];
677 m->host[i] = m->host[m->nr];
678 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
679 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
680}
681
682static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
683 u64 guest_val, u64 host_val)
684{
685 unsigned i;
686 struct msr_autoload *m = &vmx->msr_autoload;
687
688 for (i = 0; i < m->nr; ++i)
689 if (m->guest[i].index == msr)
690 break;
691
692 if (i == m->nr) {
693 ++m->nr;
694 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
695 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
696 }
697
698 m->guest[i].index = msr;
699 m->guest[i].value = guest_val;
700 m->host[i].index = msr;
701 m->host[i].value = host_val;
702}
703
33ed6329
AK		 704static void reload_tss(void)
705{
33ed6329
AK		 706 /*
707 * VT restores TR but not its size. Useless.
708 */
d359192f 709 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 710 struct desc_struct *descs;
33ed6329 711
d359192f 712 descs = (void *)gdt->address;
33ed6329
AK		 713 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
714 load_TR_desc();
33ed6329
AK		 715}
716
92c0d900 717static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 718{
3a34a881 719 u64 guest_efer;
51c6cf66
AK		 720 u64 ignore_bits;
721
f6801dff 722 guest_efer = vmx->vcpu.arch.efer;
3a34a881 723
51c6cf66
AK		 724 /*
725 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
726 * outside long mode
727 */
728 ignore_bits = EFER_NX | EFER_SCE;
729#ifdef CONFIG_X86_64
730 ignore_bits |= EFER_LMA | EFER_LME;
731 /* SCE is meaningful only in long mode on Intel */
732 if (guest_efer & EFER_LMA)
733 ignore_bits &= ~(u64)EFER_SCE;
734#endif
51c6cf66
AK		 735 guest_efer &= ~ignore_bits;
736 guest_efer |= host_efer & ignore_bits;
26bb0981 737 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 738 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 739
740 clear_atomic_switch_msr(vmx, MSR_EFER);
741 /* On ept, can't emulate nx, and must switch nx atomically */
742 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
743 guest_efer = vmx->vcpu.arch.efer;
744 if (!(guest_efer & EFER_LMA))
745 guest_efer &= ~EFER_LME;
746 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
747 return false;
748 }
749
26bb0981 750 return true;
51c6cf66
AK		 751}
752
2d49ec72
GN		 753static unsigned long segment_base(u16 selector)
754{
d359192f 755 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 756 struct desc_struct *d;
757 unsigned long table_base;
758 unsigned long v;
759
760 if (!(selector & ~3))
761 return 0;
762
d359192f 763 table_base = gdt->address;
2d49ec72
GN		 764
765 if (selector & 4) { /* from ldt */
766 u16 ldt_selector = kvm_read_ldt();
767
768 if (!(ldt_selector & ~3))
769 return 0;
770
771 table_base = segment_base(ldt_selector);
772 }
773 d = (struct desc_struct *)(table_base + (selector & ~7));
774 v = get_desc_base(d);
775#ifdef CONFIG_X86_64
776 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
777 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
778#endif
779 return v;
780}
781
782static inline unsigned long kvm_read_tr_base(void)
783{
784 u16 tr;
785 asm("str %0" : "=g"(tr));
786 return segment_base(tr);
787}
788
04d2cc77 789static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 790{
04d2cc77 791 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 792 int i;
04d2cc77 793
a2fa3e9f 794 if (vmx->host_state.loaded)
33ed6329
AK		 795 return;
796
a2fa3e9f 797 vmx->host_state.loaded = 1;
33ed6329
AK		 798 /*
799 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
800 * allow segment selectors with cpl > 0 or ti == 1.
801 */
d6e88aec 802 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 803 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 804 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 805 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 806 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 807 vmx->host_state.fs_reload_needed = 0;
808 } else {
33ed6329 809 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 810 vmx->host_state.fs_reload_needed = 1;
33ed6329 811 }
9581d442 812 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 813 if (!(vmx->host_state.gs_sel & 7))
814 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 815 else {
816 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 817 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 818 }
819
820#ifdef CONFIG_X86_64
821 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
822 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
823#else
a2fa3e9f
GH		 824 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
825 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 826#endif
707c0874
AK		 827
828#ifdef CONFIG_X86_64
44ea2b17
AK		 829 if (is_long_mode(&vmx->vcpu)) {
830 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
831 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
832 }
707c0874 833#endif
26bb0981
AK		 834 for (i = 0; i < vmx->save_nmsrs; ++i)
835 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 836 vmx->guest_msrs[i].data,
837 vmx->guest_msrs[i].mask);
33ed6329
AK		 838}
839
a9b21b62 840static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 841{
a2fa3e9f 842 if (!vmx->host_state.loaded)
33ed6329
AK		 843 return;
844
e1beb1d3 845 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 846 vmx->host_state.loaded = 0;
152d3f2f 847 if (vmx->host_state.fs_reload_needed)
9581d442 848 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 849 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 850 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 851#ifdef CONFIG_X86_64
9581d442
AK		 852 load_gs_index(vmx->host_state.gs_sel);
853 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
854#else
855 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 856#endif
33ed6329 857 }
152d3f2f 858 reload_tss();
44ea2b17
AK		 859#ifdef CONFIG_X86_64
860 if (is_long_mode(&vmx->vcpu)) {
861 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
862 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
863 }
864#endif
1c11e713
AK		 865 if (current_thread_info()->status & TS_USEDFPU)
866 clts();
3444d7da 867 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 868}
869
a9b21b62
AK		 870static void vmx_load_host_state(struct vcpu_vmx *vmx)
871{
872 preempt_disable();
873 __vmx_load_host_state(vmx);
874 preempt_enable();
875}
876
6aa8b732
AK		 877/*
878 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
879 * vcpu mutex is already taken.
880 */
15ad7146 881static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 882{
a2fa3e9f 883 struct vcpu_vmx *vmx = to_vmx(vcpu);
019960ae 884 u64 tsc_this, delta, new_offset;
4610c9cc 885 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 886
4610c9cc
DX		 887 if (!vmm_exclusive)
888 kvm_cpu_vmxon(phys_addr);
889 else if (vcpu->cpu != cpu)
8b9cf98c 890 vcpu_clear(vmx);
6aa8b732 891
a2fa3e9f 892 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 893 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 894 vmcs_load(vmx->vmcs);
6aa8b732
AK		 895 }
896
897 if (vcpu->cpu != cpu) {
d359192f 898 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 899 unsigned long sysenter_esp;
900
92fe13be 901 kvm_migrate_timers(vcpu);
a8eeb04a 902 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be
DX		 903 local_irq_disable();
904 list_add(&vmx->local_vcpus_link,
905 &per_cpu(vcpus_on_cpu, cpu));
906 local_irq_enable();
907
6aa8b732
AK		 908 vcpu->cpu = cpu;
909 /*
910 * Linux uses per-cpu TSS and GDT, so set these when switching
911 * processors.
912 */
d6e88aec 913 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 914 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 915
916 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
917 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 918
919 /*
920 * Make sure the time stamp counter is monotonous.
921 */
922 rdtscll(tsc_this);
019960ae
AK		 923 if (tsc_this < vcpu->arch.host_tsc) {
924 delta = vcpu->arch.host_tsc - tsc_this;
925 new_offset = vmcs_read64(TSC_OFFSET) + delta;
926 vmcs_write64(TSC_OFFSET, new_offset);
927 }
6aa8b732 928 }
6aa8b732
AK		 929}
930
931static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
932{
a9b21b62 933 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 934 if (!vmm_exclusive) {
b923e62e 935 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 936 kvm_cpu_vmxoff();
937 }
6aa8b732
AK		 938}
939
5fd86fcf
AK		 940static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
941{
81231c69
AK		 942 ulong cr0;
943
5fd86fcf
AK		 944 if (vcpu->fpu_active)
945 return;
946 vcpu->fpu_active = 1;
81231c69
AK		 947 cr0 = vmcs_readl(GUEST_CR0);
948 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
949 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
950 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 951 update_exception_bitmap(vcpu);
edcafe3c
AK		 952 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
953 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 954}
955
edcafe3c
AK		 956static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
957
5fd86fcf
AK		 958static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
959{
edcafe3c 960 vmx_decache_cr0_guest_bits(vcpu);
81231c69 961 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 962 update_exception_bitmap(vcpu);
edcafe3c
AK		 963 vcpu->arch.cr0_guest_owned_bits = 0;
964 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
965 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 966}
967
6aa8b732
AK		 968static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
969{
78ac8b47 970 unsigned long rflags, save_rflags;
345dcaa8
AK		 971
972 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 973 if (to_vmx(vcpu)->rmode.vm86_active) {
974 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
975 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
976 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
977 }
345dcaa8 978 return rflags;
6aa8b732
AK		 979}
980
981static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
982{
78ac8b47
AK		 983 if (to_vmx(vcpu)->rmode.vm86_active) {
984 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 985 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 986 }
6aa8b732
AK		 987 vmcs_writel(GUEST_RFLAGS, rflags);
988}
989
2809f5d2
GC		 990static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
991{
992 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
993 int ret = 0;
994
995 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 996 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 997 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 998 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 999
1000 return ret & mask;
1001}
1002
1003static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1004{
1005 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1006 u32 interruptibility = interruptibility_old;
1007
1008 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1009
48005f64 1010 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1011 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1012 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1013 interruptibility |= GUEST_INTR_STATE_STI;
1014
1015 if ((interruptibility != interruptibility_old))
1016 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1017}
1018
6aa8b732
AK		 1019static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1020{
1021 unsigned long rip;
6aa8b732 1022
5fdbf976 1023 rip = kvm_rip_read(vcpu);
6aa8b732 1024 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1025 kvm_rip_write(vcpu, rip);
6aa8b732 1026
2809f5d2
GC		 1027 /* skipping an emulated instruction also counts */
1028 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1029}
1030
298101da 1031static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1032 bool has_error_code, u32 error_code,
1033 bool reinject)
298101da 1034{
77ab6db0 1035 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1036 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1037
8ab2d2e2 1038 if (has_error_code) {
77ab6db0 1039 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1040 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1041 }
77ab6db0 1042
7ffd92c5 1043 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 1044 vmx->rmode.irq.pending = true;
1045 vmx->rmode.irq.vector = nr;
1046 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 1047 if (kvm_exception_is_soft(nr))
1048 vmx->rmode.irq.rip +=
1049 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 1050 intr_info |= INTR_TYPE_SOFT_INTR;
1051 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 1052 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1053 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1054 return;
1055 }
1056
66fd3f7f
GN		 1057 if (kvm_exception_is_soft(nr)) {
1058 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1059 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1060 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1061 } else
1062 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1063
1064 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1065}
1066
4e47c7a6
SY		 1067static bool vmx_rdtscp_supported(void)
1068{
1069 return cpu_has_vmx_rdtscp();
1070}
1071
a75beee6
ED		 1072/*
1073 * Swap MSR entry in host/guest MSR entry array.
1074 */
8b9cf98c 1075static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1076{
26bb0981 1077 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1078
1079 tmp = vmx->guest_msrs[to];
1080 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1081 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1082}
1083
e38aea3e
AK		 1084/*
1085 * Set up the vmcs to automatically save and restore system
1086 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1087 * mode, as fiddling with msrs is very expensive.
1088 */
8b9cf98c 1089static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1090{
26bb0981 1091 int save_nmsrs, index;
5897297b 1092 unsigned long *msr_bitmap;
e38aea3e 1093
33f9c505 1094 vmx_load_host_state(vmx);
a75beee6
ED		 1095 save_nmsrs = 0;
1096#ifdef CONFIG_X86_64
8b9cf98c 1097 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1098 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1099 if (index >= 0)
8b9cf98c
RR		 1100 move_msr_up(vmx, index, save_nmsrs++);
1101 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1102 if (index >= 0)
8b9cf98c
RR		 1103 move_msr_up(vmx, index, save_nmsrs++);
1104 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1105 if (index >= 0)
8b9cf98c 1106 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1107 index = __find_msr_index(vmx, MSR_TSC_AUX);
1108 if (index >= 0 && vmx->rdtscp_enabled)
1109 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1110 /*
8c06585d 1111 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1112 * if efer.sce is enabled.
1113 */
8c06585d 1114 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1115 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1116 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1117 }
1118#endif
92c0d900
AK		 1119 index = __find_msr_index(vmx, MSR_EFER);
1120 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1121 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1122
26bb0981 1123 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1124
1125 if (cpu_has_vmx_msr_bitmap()) {
1126 if (is_long_mode(&vmx->vcpu))
1127 msr_bitmap = vmx_msr_bitmap_longmode;
1128 else
1129 msr_bitmap = vmx_msr_bitmap_legacy;
1130
1131 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1132 }
e38aea3e
AK		 1133}
1134
6aa8b732
AK		 1135/*
1136 * reads and returns guest's timestamp counter "register"
1137 * guest_tsc = host_tsc + tsc_offset -- 21.3
1138 */
1139static u64 guest_read_tsc(void)
1140{
1141 u64 host_tsc, tsc_offset;
1142
1143 rdtscll(host_tsc);
1144 tsc_offset = vmcs_read64(TSC_OFFSET);
1145 return host_tsc + tsc_offset;
1146}
1147
1148/*
1149 * writes 'guest_tsc' into guest's timestamp counter "register"
1150 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1151 */
f4e1b3c8 1152static void vmx_write_tsc_offset(u64 offset)
6aa8b732 1153{
f4e1b3c8 1154 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1155}
1156
6aa8b732
AK		 1157/*
1158 * Reads an msr value (of 'msr_index') into 'pdata'.
1159 * Returns 0 on success, non-0 otherwise.
1160 * Assumes vcpu_load() was already called.
1161 */
1162static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1163{
1164 u64 data;
26bb0981 1165 struct shared_msr_entry *msr;
6aa8b732
AK		 1166
1167 if (!pdata) {
1168 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1169 return -EINVAL;
1170 }
1171
1172 switch (msr_index) {
05b3e0c2 1173#ifdef CONFIG_X86_64
6aa8b732
AK		 1174 case MSR_FS_BASE:
1175 data = vmcs_readl(GUEST_FS_BASE);
1176 break;
1177 case MSR_GS_BASE:
1178 data = vmcs_readl(GUEST_GS_BASE);
1179 break;
44ea2b17
AK		 1180 case MSR_KERNEL_GS_BASE:
1181 vmx_load_host_state(to_vmx(vcpu));
1182 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1183 break;
26bb0981 1184#endif
6aa8b732 1185 case MSR_EFER:
3bab1f5d 1186 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1187 case MSR_IA32_TSC:
6aa8b732
AK		 1188 data = guest_read_tsc();
1189 break;
1190 case MSR_IA32_SYSENTER_CS:
1191 data = vmcs_read32(GUEST_SYSENTER_CS);
1192 break;
1193 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1194 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1195 break;
1196 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1197 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1198 break;
4e47c7a6
SY		 1199 case MSR_TSC_AUX:
1200 if (!to_vmx(vcpu)->rdtscp_enabled)
1201 return 1;
1202 /* Otherwise falls through */
6aa8b732 1203 default:
26bb0981 1204 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1205 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1206 if (msr) {
542423b0 1207 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1208 data = msr->data;
1209 break;
6aa8b732 1210 }
3bab1f5d 1211 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1212 }
1213
1214 *pdata = data;
1215 return 0;
1216}
1217
1218/*
1219 * Writes msr value into into the appropriate "register".
1220 * Returns 0 on success, non-0 otherwise.
1221 * Assumes vcpu_load() was already called.
1222 */
1223static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1224{
a2fa3e9f 1225 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1226 struct shared_msr_entry *msr;
53f658b3 1227 u64 host_tsc;
2cc51560
ED		 1228 int ret = 0;
1229
6aa8b732 1230 switch (msr_index) {
3bab1f5d 1231 case MSR_EFER:
a9b21b62 1232 vmx_load_host_state(vmx);
2cc51560 1233 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1234 break;
16175a79 1235#ifdef CONFIG_X86_64
6aa8b732
AK		 1236 case MSR_FS_BASE:
1237 vmcs_writel(GUEST_FS_BASE, data);
1238 break;
1239 case MSR_GS_BASE:
1240 vmcs_writel(GUEST_GS_BASE, data);
1241 break;
44ea2b17
AK		 1242 case MSR_KERNEL_GS_BASE:
1243 vmx_load_host_state(vmx);
1244 vmx->msr_guest_kernel_gs_base = data;
1245 break;
6aa8b732
AK		 1246#endif
1247 case MSR_IA32_SYSENTER_CS:
1248 vmcs_write32(GUEST_SYSENTER_CS, data);
1249 break;
1250 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1251 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1252 break;
1253 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1254 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1255 break;
af24a4e4 1256 case MSR_IA32_TSC:
53f658b3 1257 rdtscll(host_tsc);
f4e1b3c8 1258 vmx_write_tsc_offset(data - host_tsc);
6aa8b732 1259 break;
468d472f
SY		 1260 case MSR_IA32_CR_PAT:
1261 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1262 vmcs_write64(GUEST_IA32_PAT, data);
1263 vcpu->arch.pat = data;
1264 break;
1265 }
4e47c7a6
SY		 1266 ret = kvm_set_msr_common(vcpu, msr_index, data);
1267 break;
1268 case MSR_TSC_AUX:
1269 if (!vmx->rdtscp_enabled)
1270 return 1;
1271 /* Check reserved bit, higher 32 bits should be zero */
1272 if ((data >> 32) != 0)
1273 return 1;
1274 /* Otherwise falls through */
6aa8b732 1275 default:
8b9cf98c 1276 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1277 if (msr) {
542423b0 1278 vmx_load_host_state(vmx);
3bab1f5d
AK		 1279 msr->data = data;
1280 break;
6aa8b732 1281 }
2cc51560 1282 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1283 }
1284
2cc51560 1285 return ret;
6aa8b732
AK		 1286}
1287
5fdbf976 1288static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1289{
5fdbf976
MT		 1290 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1291 switch (reg) {
1292 case VCPU_REGS_RSP:
1293 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1294 break;
1295 case VCPU_REGS_RIP:
1296 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1297 break;
6de4f3ad
AK		 1298 case VCPU_EXREG_PDPTR:
1299 if (enable_ept)
1300 ept_save_pdptrs(vcpu);
1301 break;
5fdbf976
MT		 1302 default:
1303 break;
1304 }
6aa8b732
AK		 1305}
1306
355be0b9 1307static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1308{
ae675ef0
JK		 1309 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1310 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1311 else
1312 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1313
abd3f2d6 1314 update_exception_bitmap(vcpu);
6aa8b732
AK		 1315}
1316
1317static __init int cpu_has_kvm_support(void)
1318{
6210e37b 1319 return cpu_has_vmx();
6aa8b732
AK		 1320}
1321
1322static __init int vmx_disabled_by_bios(void)
1323{
1324 u64 msr;
1325
1326 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1327 if (msr & FEATURE_CONTROL_LOCKED) {
1328 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1329 && tboot_enabled())
1330 return 1;
1331 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1332 && !tboot_enabled())
1333 return 1;
1334 }
1335
1336 return 0;
62b3ffb8 1337 /* locked but not enabled */
6aa8b732
AK		 1338}
1339
7725b894
DX		 1340static void kvm_cpu_vmxon(u64 addr)
1341{
1342 asm volatile (ASM_VMX_VMXON_RAX
1343 : : "a"(&addr), "m"(addr)
1344 : "memory", "cc");
1345}
1346
10474ae8 1347static int hardware_enable(void *garbage)
6aa8b732
AK		 1348{
1349 int cpu = raw_smp_processor_id();
1350 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1351 u64 old, test_bits;
6aa8b732 1352
10474ae8
AG		 1353 if (read_cr4() & X86_CR4_VMXE)
1354 return -EBUSY;
1355
543e4243 1356 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1357 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1358
1359 test_bits = FEATURE_CONTROL_LOCKED;
1360 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1361 if (tboot_enabled())
1362 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1363
1364 if ((old & test_bits) != test_bits) {
6aa8b732 1365 /* enable and lock */
cafd6659
SW		 1366 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1367 }
66aee91a 1368 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1369
4610c9cc
DX		 1370 if (vmm_exclusive) {
1371 kvm_cpu_vmxon(phys_addr);
1372 ept_sync_global();
1373 }
10474ae8 1374
3444d7da
AK		 1375 store_gdt(&__get_cpu_var(host_gdt));
1376
10474ae8 1377 return 0;
6aa8b732
AK		 1378}
1379
543e4243
AK		 1380static void vmclear_local_vcpus(void)
1381{
1382 int cpu = raw_smp_processor_id();
1383 struct vcpu_vmx *vmx, *n;
1384
1385 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1386 local_vcpus_link)
1387 __vcpu_clear(vmx);
1388}
1389
710ff4a8
EH		 1390
1391/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1392 * tricks.
1393 */
1394static void kvm_cpu_vmxoff(void)
6aa8b732 1395{
4ecac3fd 1396 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1397}
1398
710ff4a8
EH		 1399static void hardware_disable(void *garbage)
1400{
4610c9cc
DX		 1401 if (vmm_exclusive) {
1402 vmclear_local_vcpus();
1403 kvm_cpu_vmxoff();
1404 }
7725b894 1405 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1406}
1407
1c3d14fe 1408static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1409 u32 msr, u32 *result)
1c3d14fe
YS		 1410{
1411 u32 vmx_msr_low, vmx_msr_high;
1412 u32 ctl = ctl_min | ctl_opt;
1413
1414 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1415
1416 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1417 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1418
1419 /* Ensure minimum (required) set of control bits are supported. */
1420 if (ctl_min & ~ctl)
002c7f7c 1421 return -EIO;
1c3d14fe
YS		 1422
1423 *result = ctl;
1424 return 0;
1425}
1426
002c7f7c 1427static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1428{
1429 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1430 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1431 u32 _pin_based_exec_control = 0;
1432 u32 _cpu_based_exec_control = 0;
f78e0e2e 1433 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1434 u32 _vmexit_control = 0;
1435 u32 _vmentry_control = 0;
1436
1437 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1438 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1439 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1440 &_pin_based_exec_control) < 0)
002c7f7c 1441 return -EIO;
1c3d14fe
YS		 1442
1443 min = CPU_BASED_HLT_EXITING |
1444#ifdef CONFIG_X86_64
1445 CPU_BASED_CR8_LOAD_EXITING |
1446 CPU_BASED_CR8_STORE_EXITING |
1447#endif
d56f546d
SY		 1448 CPU_BASED_CR3_LOAD_EXITING |
1449 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1450 CPU_BASED_USE_IO_BITMAPS |
1451 CPU_BASED_MOV_DR_EXITING |
a7052897 1452 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1453 CPU_BASED_MWAIT_EXITING |
1454 CPU_BASED_MONITOR_EXITING |
a7052897 1455 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1456 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1457 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1458 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1459 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1460 &_cpu_based_exec_control) < 0)
002c7f7c 1461 return -EIO;
6e5d865c
YS		 1462#ifdef CONFIG_X86_64
1463 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1464 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1465 ~CPU_BASED_CR8_STORE_EXITING;
1466#endif
f78e0e2e 1467 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1468 min2 = 0;
1469 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1470 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1471 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1472 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1473 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1474 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1475 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1476 if (adjust_vmx_controls(min2, opt2,
1477 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1478 &_cpu_based_2nd_exec_control) < 0)
1479 return -EIO;
1480 }
1481#ifndef CONFIG_X86_64
1482 if (!(_cpu_based_2nd_exec_control &
1483 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1484 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1485#endif
d56f546d 1486 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1487 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1488 enabled */
5fff7d27
GN		 1489 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1490 CPU_BASED_CR3_STORE_EXITING |
1491 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1492 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1493 vmx_capability.ept, vmx_capability.vpid);
1494 }
1c3d14fe
YS		 1495
1496 min = 0;
1497#ifdef CONFIG_X86_64
1498 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1499#endif
468d472f 1500 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1501 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1502 &_vmexit_control) < 0)
002c7f7c 1503 return -EIO;
1c3d14fe 1504
468d472f
SY		 1505 min = 0;
1506 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1507 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1508 &_vmentry_control) < 0)
002c7f7c 1509 return -EIO;
6aa8b732 1510
c68876fd 1511 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1512
1513 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1514 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1515 return -EIO;
1c3d14fe
YS		 1516
1517#ifdef CONFIG_X86_64
1518 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1519 if (vmx_msr_high & (1u<<16))
002c7f7c 1520 return -EIO;
1c3d14fe
YS		 1521#endif
1522
1523 /* Require Write-Back (WB) memory type for VMCS accesses. */
1524 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1525 return -EIO;
1c3d14fe 1526
002c7f7c
YS		 1527 vmcs_conf->size = vmx_msr_high & 0x1fff;
1528 vmcs_conf->order = get_order(vmcs_config.size);
1529 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1530
002c7f7c
YS		 1531 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1532 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1533 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1534 vmcs_conf->vmexit_ctrl = _vmexit_control;
1535 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1536
1537 return 0;
c68876fd 1538}
6aa8b732
AK		 1539
1540static struct vmcs *alloc_vmcs_cpu(int cpu)
1541{
1542 int node = cpu_to_node(cpu);
1543 struct page *pages;
1544 struct vmcs *vmcs;
1545
6484eb3e 1546 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1547 if (!pages)
1548 return NULL;
1549 vmcs = page_address(pages);
1c3d14fe
YS		 1550 memset(vmcs, 0, vmcs_config.size);
1551 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1552 return vmcs;
1553}
1554
1555static struct vmcs *alloc_vmcs(void)
1556{
d3b2c338 1557 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1558}
1559
1560static void free_vmcs(struct vmcs *vmcs)
1561{
1c3d14fe 1562 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1563}
1564
39959588 1565static void free_kvm_area(void)
6aa8b732
AK		 1566{
1567 int cpu;
1568
3230bb47 1569 for_each_possible_cpu(cpu) {
6aa8b732 1570 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1571 per_cpu(vmxarea, cpu) = NULL;
1572 }
6aa8b732
AK		 1573}
1574
6aa8b732
AK		 1575static __init int alloc_kvm_area(void)
1576{
1577 int cpu;
1578
3230bb47 1579 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1580 struct vmcs *vmcs;
1581
1582 vmcs = alloc_vmcs_cpu(cpu);
1583 if (!vmcs) {
1584 free_kvm_area();
1585 return -ENOMEM;
1586 }
1587
1588 per_cpu(vmxarea, cpu) = vmcs;
1589 }
1590 return 0;
1591}
1592
1593static __init int hardware_setup(void)
1594{
002c7f7c
YS		 1595 if (setup_vmcs_config(&vmcs_config) < 0)
1596 return -EIO;
50a37eb4
JR		 1597
1598 if (boot_cpu_has(X86_FEATURE_NX))
1599 kvm_enable_efer_bits(EFER_NX);
1600
93ba03c2
SY		 1601 if (!cpu_has_vmx_vpid())
1602 enable_vpid = 0;
1603
4bc9b982
SY		 1604 if (!cpu_has_vmx_ept() ||
1605 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1606 enable_ept = 0;
3a624e29
NK		 1607 enable_unrestricted_guest = 0;
1608 }
1609
1610 if (!cpu_has_vmx_unrestricted_guest())
1611 enable_unrestricted_guest = 0;
93ba03c2
SY		 1612
1613 if (!cpu_has_vmx_flexpriority())
1614 flexpriority_enabled = 0;
1615
95ba8273
GN		 1616 if (!cpu_has_vmx_tpr_shadow())
1617 kvm_x86_ops->update_cr8_intercept = NULL;
1618
54dee993
MT		 1619 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1620 kvm_disable_largepages();
1621
4b8d54f9
ZE		 1622 if (!cpu_has_vmx_ple())
1623 ple_gap = 0;
1624
6aa8b732
AK		 1625 return alloc_kvm_area();
1626}
1627
1628static __exit void hardware_unsetup(void)
1629{
1630 free_kvm_area();
1631}
1632
6aa8b732
AK		 1633static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1634{
1635 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1636
6af11b9e 1637 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1638 vmcs_write16(sf->selector, save->selector);
1639 vmcs_writel(sf->base, save->base);
1640 vmcs_write32(sf->limit, save->limit);
1641 vmcs_write32(sf->ar_bytes, save->ar);
1642 } else {
1643 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1644 << AR_DPL_SHIFT;
1645 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1646 }
1647}
1648
1649static void enter_pmode(struct kvm_vcpu *vcpu)
1650{
1651 unsigned long flags;
a89a8fb9 1652 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1653
a89a8fb9 1654 vmx->emulation_required = 1;
7ffd92c5 1655 vmx->rmode.vm86_active = 0;
6aa8b732 1656
7ffd92c5
AK		 1657 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1658 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1659 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1660
1661 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1662 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1663 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1664 vmcs_writel(GUEST_RFLAGS, flags);
1665
66aee91a
RR		 1666 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1667 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1668
1669 update_exception_bitmap(vcpu);
1670
a89a8fb9
MG		 1671 if (emulate_invalid_guest_state)
1672 return;
1673
7ffd92c5
AK		 1674 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1675 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1676 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1677 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1678
1679 vmcs_write16(GUEST_SS_SELECTOR, 0);
1680 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1681
1682 vmcs_write16(GUEST_CS_SELECTOR,
1683 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1684 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1685}
1686
d77c26fc 1687static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1688{
bfc6d222 1689 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1690 struct kvm_memslots *slots;
1691 gfn_t base_gfn;
1692
90d83dc3 1693 slots = kvm_memslots(kvm);
f495c6e5 1694 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1695 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1696 return base_gfn << PAGE_SHIFT;
1697 }
bfc6d222 1698 return kvm->arch.tss_addr;
6aa8b732
AK		 1699}
1700
1701static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1702{
1703 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1704
1705 save->selector = vmcs_read16(sf->selector);
1706 save->base = vmcs_readl(sf->base);
1707 save->limit = vmcs_read32(sf->limit);
1708 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1709 vmcs_write16(sf->selector, save->base >> 4);
1710 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1711 vmcs_write32(sf->limit, 0xffff);
1712 vmcs_write32(sf->ar_bytes, 0xf3);
1713}
1714
1715static void enter_rmode(struct kvm_vcpu *vcpu)
1716{
1717 unsigned long flags;
a89a8fb9 1718 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1719
3a624e29
NK		 1720 if (enable_unrestricted_guest)
1721 return;
1722
a89a8fb9 1723 vmx->emulation_required = 1;
7ffd92c5 1724 vmx->rmode.vm86_active = 1;
6aa8b732 1725
7ffd92c5 1726 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1727 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1728
7ffd92c5 1729 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1730 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1731
7ffd92c5 1732 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1733 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1734
1735 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1736 vmx->rmode.save_rflags = flags;
6aa8b732 1737
053de044 1738 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1739
1740 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1741 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1742 update_exception_bitmap(vcpu);
1743
a89a8fb9
MG		 1744 if (emulate_invalid_guest_state)
1745 goto continue_rmode;
1746
6aa8b732
AK		 1747 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1748 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1749 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1750
1751 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1752 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1753 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1754 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1755 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1756
7ffd92c5
AK		 1757 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1758 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1759 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1760 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1761
a89a8fb9 1762continue_rmode:
8668a3c4 1763 kvm_mmu_reset_context(vcpu);
b7ebfb05 1764 init_rmode(vcpu->kvm);
6aa8b732
AK		 1765}
1766
401d10de
AS		 1767static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1768{
1769 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1770 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1771
1772 if (!msr)
1773 return;
401d10de 1774
44ea2b17
AK		 1775 /*
1776 * Force kernel_gs_base reloading before EFER changes, as control
1777 * of this msr depends on is_long_mode().
1778 */
1779 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1780 vcpu->arch.efer = efer;
401d10de
AS		 1781 if (efer & EFER_LMA) {
1782 vmcs_write32(VM_ENTRY_CONTROLS,
1783 vmcs_read32(VM_ENTRY_CONTROLS) |
1784 VM_ENTRY_IA32E_MODE);
1785 msr->data = efer;
1786 } else {
1787 vmcs_write32(VM_ENTRY_CONTROLS,
1788 vmcs_read32(VM_ENTRY_CONTROLS) &
1789 ~VM_ENTRY_IA32E_MODE);
1790
1791 msr->data = efer & ~EFER_LME;
1792 }
1793 setup_msrs(vmx);
1794}
1795
05b3e0c2 1796#ifdef CONFIG_X86_64
6aa8b732
AK		 1797
1798static void enter_lmode(struct kvm_vcpu *vcpu)
1799{
1800 u32 guest_tr_ar;
1801
1802 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1803 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1804 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1805 __func__);
6aa8b732
AK		 1806 vmcs_write32(GUEST_TR_AR_BYTES,
1807 (guest_tr_ar & ~AR_TYPE_MASK)
1808 | AR_TYPE_BUSY_64_TSS);
1809 }
da38f438 1810 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1811}
1812
1813static void exit_lmode(struct kvm_vcpu *vcpu)
1814{
6aa8b732
AK		 1815 vmcs_write32(VM_ENTRY_CONTROLS,
1816 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1817 & ~VM_ENTRY_IA32E_MODE);
da38f438 1818 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1819}
1820
1821#endif
1822
2384d2b3
SY		 1823static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1824{
b9d762fa 1825 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 1826 if (enable_ept) {
1827 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1828 return;
4e1096d2 1829 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 1830 }
2384d2b3
SY		 1831}
1832
e8467fda
AK		 1833static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1834{
1835 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1836
1837 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1838 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1839}
1840
25c4c276 1841static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1842{
fc78f519
AK		 1843 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1844
1845 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1846 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1847}
1848
1439442c
SY		 1849static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1850{
6de4f3ad
AK		 1851 if (!test_bit(VCPU_EXREG_PDPTR,
1852 (unsigned long *)&vcpu->arch.regs_dirty))
1853 return;
1854
1439442c 1855 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1856 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1857 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1858 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1859 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1860 }
1861}
1862
8f5d549f
AK		 1863static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1864{
1865 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1866 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1867 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1868 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1869 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1870 }
6de4f3ad
AK		 1871
1872 __set_bit(VCPU_EXREG_PDPTR,
1873 (unsigned long *)&vcpu->arch.regs_avail);
1874 __set_bit(VCPU_EXREG_PDPTR,
1875 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1876}
1877
1439442c
SY		 1878static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1879
1880static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1881 unsigned long cr0,
1882 struct kvm_vcpu *vcpu)
1883{
1884 if (!(cr0 & X86_CR0_PG)) {
1885 /* From paging/starting to nonpaging */
1886 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1887 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1888 (CPU_BASED_CR3_LOAD_EXITING |
1889 CPU_BASED_CR3_STORE_EXITING));
1890 vcpu->arch.cr0 = cr0;
fc78f519 1891 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1892 } else if (!is_paging(vcpu)) {
1893 /* From nonpaging to paging */
1894 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1895 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1896 ~(CPU_BASED_CR3_LOAD_EXITING |
1897 CPU_BASED_CR3_STORE_EXITING));
1898 vcpu->arch.cr0 = cr0;
fc78f519 1899 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1900 }
95eb84a7
SY		 1901
1902 if (!(cr0 & X86_CR0_WP))
1903 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1904}
1905
6aa8b732
AK		 1906static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1907{
7ffd92c5 1908 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1909 unsigned long hw_cr0;
1910
1911 if (enable_unrestricted_guest)
1912 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1913 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1914 else
1915 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1916
7ffd92c5 1917 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1918 enter_pmode(vcpu);
1919
7ffd92c5 1920 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1921 enter_rmode(vcpu);
1922
05b3e0c2 1923#ifdef CONFIG_X86_64
f6801dff 1924 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1925 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1926 enter_lmode(vcpu);
707d92fa 1927 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1928 exit_lmode(vcpu);
1929 }
1930#endif
1931
089d034e 1932 if (enable_ept)
1439442c
SY		 1933 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1934
02daab21 1935 if (!vcpu->fpu_active)
81231c69 1936 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1937
6aa8b732 1938 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1939 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1940 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1941}
1942
1439442c
SY		 1943static u64 construct_eptp(unsigned long root_hpa)
1944{
1945 u64 eptp;
1946
1947 /* TODO write the value reading from MSR */
1948 eptp = VMX_EPT_DEFAULT_MT |
1949 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1950 eptp |= (root_hpa & PAGE_MASK);
1951
1952 return eptp;
1953}
1954
6aa8b732
AK		 1955static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1956{
1439442c
SY		 1957 unsigned long guest_cr3;
1958 u64 eptp;
1959
1960 guest_cr3 = cr3;
089d034e 1961 if (enable_ept) {
1439442c
SY		 1962 eptp = construct_eptp(cr3);
1963 vmcs_write64(EPT_POINTER, eptp);
1439442c 1964 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1965 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1966 ept_load_pdptrs(vcpu);
1439442c
SY		 1967 }
1968
2384d2b3 1969 vmx_flush_tlb(vcpu);
1439442c 1970 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1971}
1972
1973static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1974{
7ffd92c5 1975 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1976 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1977
ad312c7c 1978 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1979 if (enable_ept) {
1980 if (!is_paging(vcpu)) {
1981 hw_cr4 &= ~X86_CR4_PAE;
1982 hw_cr4 |= X86_CR4_PSE;
1983 } else if (!(cr4 & X86_CR4_PAE)) {
1984 hw_cr4 &= ~X86_CR4_PAE;
1985 }
1986 }
1439442c
SY		 1987
1988 vmcs_writel(CR4_READ_SHADOW, cr4);
1989 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1990}
1991
6aa8b732
AK		 1992static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1993{
1994 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1995
1996 return vmcs_readl(sf->base);
1997}
1998
1999static void vmx_get_segment(struct kvm_vcpu *vcpu,
2000 struct kvm_segment *var, int seg)
2001{
2002 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2003 u32 ar;
2004
2005 var->base = vmcs_readl(sf->base);
2006 var->limit = vmcs_read32(sf->limit);
2007 var->selector = vmcs_read16(sf->selector);
2008 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 2009 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2010 ar = 0;
2011 var->type = ar & 15;
2012 var->s = (ar >> 4) & 1;
2013 var->dpl = (ar >> 5) & 3;
2014 var->present = (ar >> 7) & 1;
2015 var->avl = (ar >> 12) & 1;
2016 var->l = (ar >> 13) & 1;
2017 var->db = (ar >> 14) & 1;
2018 var->g = (ar >> 15) & 1;
2019 var->unusable = (ar >> 16) & 1;
2020}
2021
2e4d2653
IE		 2022static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2023{
3eeb3288 2024 if (!is_protmode(vcpu))
2e4d2653
IE		 2025 return 0;
2026
2027 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2028 return 3;
2029
eab4b8aa 2030 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2031}
2032
653e3108 2033static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2034{
6aa8b732
AK		 2035 u32 ar;
2036
653e3108 2037 if (var->unusable)
6aa8b732
AK		 2038 ar = 1 << 16;
2039 else {
2040 ar = var->type & 15;
2041 ar |= (var->s & 1) << 4;
2042 ar |= (var->dpl & 3) << 5;
2043 ar |= (var->present & 1) << 7;
2044 ar |= (var->avl & 1) << 12;
2045 ar |= (var->l & 1) << 13;
2046 ar |= (var->db & 1) << 14;
2047 ar |= (var->g & 1) << 15;
2048 }
f7fbf1fd
UL		 2049 if (ar == 0) /* a 0 value means unusable */
2050 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2051
2052 return ar;
2053}
2054
2055static void vmx_set_segment(struct kvm_vcpu *vcpu,
2056 struct kvm_segment *var, int seg)
2057{
7ffd92c5 2058 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2059 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2060 u32 ar;
2061
7ffd92c5
AK		 2062 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2063 vmx->rmode.tr.selector = var->selector;
2064 vmx->rmode.tr.base = var->base;
2065 vmx->rmode.tr.limit = var->limit;
2066 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2067 return;
2068 }
2069 vmcs_writel(sf->base, var->base);
2070 vmcs_write32(sf->limit, var->limit);
2071 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2072 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2073 /*
2074 * Hack real-mode segments into vm86 compatibility.
2075 */
2076 if (var->base == 0xffff0000 && var->selector == 0xf000)
2077 vmcs_writel(sf->base, 0xf0000);
2078 ar = 0xf3;
2079 } else
2080 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2081
2082 /*
2083 * Fix the "Accessed" bit in AR field of segment registers for older
2084 * qemu binaries.
2085 * IA32 arch specifies that at the time of processor reset the
2086 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2087 * is setting it to 0 in the usedland code. This causes invalid guest
2088 * state vmexit when "unrestricted guest" mode is turned on.
2089 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2090 * tree. Newer qemu binaries with that qemu fix would not need this
2091 * kvm hack.
2092 */
2093 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2094 ar |= 0x1; /* Accessed */
2095
6aa8b732
AK		 2096 vmcs_write32(sf->ar_bytes, ar);
2097}
2098
6aa8b732
AK		 2099static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2100{
2101 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2102
2103 *db = (ar >> 14) & 1;
2104 *l = (ar >> 13) & 1;
2105}
2106
89a27f4d 2107static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2108{
89a27f4d
GN		 2109 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2110 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2111}
2112
89a27f4d 2113static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2114{
89a27f4d
GN		 2115 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2116 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2117}
2118
89a27f4d 2119static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2120{
89a27f4d
GN		 2121 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2122 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2123}
2124
89a27f4d 2125static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2126{
89a27f4d
GN		 2127 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2128 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2129}
2130
648dfaa7
MG		 2131static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2132{
2133 struct kvm_segment var;
2134 u32 ar;
2135
2136 vmx_get_segment(vcpu, &var, seg);
2137 ar = vmx_segment_access_rights(&var);
2138
2139 if (var.base != (var.selector << 4))
2140 return false;
2141 if (var.limit != 0xffff)
2142 return false;
2143 if (ar != 0xf3)
2144 return false;
2145
2146 return true;
2147}
2148
2149static bool code_segment_valid(struct kvm_vcpu *vcpu)
2150{
2151 struct kvm_segment cs;
2152 unsigned int cs_rpl;
2153
2154 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2155 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2156
1872a3f4
AK		 2157 if (cs.unusable)
2158 return false;
648dfaa7
MG		 2159 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2160 return false;
2161 if (!cs.s)
2162 return false;
1872a3f4 2163 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2164 if (cs.dpl > cs_rpl)
2165 return false;
1872a3f4 2166 } else {
648dfaa7
MG		 2167 if (cs.dpl != cs_rpl)
2168 return false;
2169 }
2170 if (!cs.present)
2171 return false;
2172
2173 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2174 return true;
2175}
2176
2177static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2178{
2179 struct kvm_segment ss;
2180 unsigned int ss_rpl;
2181
2182 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2183 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2184
1872a3f4
AK		 2185 if (ss.unusable)
2186 return true;
2187 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2188 return false;
2189 if (!ss.s)
2190 return false;
2191 if (ss.dpl != ss_rpl) /* DPL != RPL */
2192 return false;
2193 if (!ss.present)
2194 return false;
2195
2196 return true;
2197}
2198
2199static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2200{
2201 struct kvm_segment var;
2202 unsigned int rpl;
2203
2204 vmx_get_segment(vcpu, &var, seg);
2205 rpl = var.selector & SELECTOR_RPL_MASK;
2206
1872a3f4
AK		 2207 if (var.unusable)
2208 return true;
648dfaa7
MG		 2209 if (!var.s)
2210 return false;
2211 if (!var.present)
2212 return false;
2213 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2214 if (var.dpl < rpl) /* DPL < RPL */
2215 return false;
2216 }
2217
2218 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2219 * rights flags
2220 */
2221 return true;
2222}
2223
2224static bool tr_valid(struct kvm_vcpu *vcpu)
2225{
2226 struct kvm_segment tr;
2227
2228 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2229
1872a3f4
AK		 2230 if (tr.unusable)
2231 return false;
648dfaa7
MG		 2232 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2233 return false;
1872a3f4 2234 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2235 return false;
2236 if (!tr.present)
2237 return false;
2238
2239 return true;
2240}
2241
2242static bool ldtr_valid(struct kvm_vcpu *vcpu)
2243{
2244 struct kvm_segment ldtr;
2245
2246 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2247
1872a3f4
AK		 2248 if (ldtr.unusable)
2249 return true;
648dfaa7
MG		 2250 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2251 return false;
2252 if (ldtr.type != 2)
2253 return false;
2254 if (!ldtr.present)
2255 return false;
2256
2257 return true;
2258}
2259
2260static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2261{
2262 struct kvm_segment cs, ss;
2263
2264 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2265 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2266
2267 return ((cs.selector & SELECTOR_RPL_MASK) ==
2268 (ss.selector & SELECTOR_RPL_MASK));
2269}
2270
2271/*
2272 * Check if guest state is valid. Returns true if valid, false if
2273 * not.
2274 * We assume that registers are always usable
2275 */
2276static bool guest_state_valid(struct kvm_vcpu *vcpu)
2277{
2278 /* real mode guest state checks */
3eeb3288 2279 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2280 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2281 return false;
2282 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2283 return false;
2284 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2285 return false;
2286 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2287 return false;
2288 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2289 return false;
2290 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2291 return false;
2292 } else {
2293 /* protected mode guest state checks */
2294 if (!cs_ss_rpl_check(vcpu))
2295 return false;
2296 if (!code_segment_valid(vcpu))
2297 return false;
2298 if (!stack_segment_valid(vcpu))
2299 return false;
2300 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2301 return false;
2302 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2303 return false;
2304 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2305 return false;
2306 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2307 return false;
2308 if (!tr_valid(vcpu))
2309 return false;
2310 if (!ldtr_valid(vcpu))
2311 return false;
2312 }
2313 /* TODO:
2314 * - Add checks on RIP
2315 * - Add checks on RFLAGS
2316 */
2317
2318 return true;
2319}
2320
d77c26fc 2321static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2322{
6aa8b732 2323 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2324 u16 data = 0;
10589a46 2325 int ret = 0;
195aefde 2326 int r;
6aa8b732 2327
195aefde
IE		 2328 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2329 if (r < 0)
10589a46 2330 goto out;
195aefde 2331 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2332 r = kvm_write_guest_page(kvm, fn++, &data,
2333 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2334 if (r < 0)
10589a46 2335 goto out;
195aefde
IE		 2336 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2337 if (r < 0)
10589a46 2338 goto out;
195aefde
IE		 2339 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2340 if (r < 0)
10589a46 2341 goto out;
195aefde 2342 data = ~0;
10589a46
MT		 2343 r = kvm_write_guest_page(kvm, fn, &data,
2344 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2345 sizeof(u8));
195aefde 2346 if (r < 0)
10589a46
MT		 2347 goto out;
2348
2349 ret = 1;
2350out:
10589a46 2351 return ret;
6aa8b732
AK		 2352}
2353
b7ebfb05
SY		 2354static int init_rmode_identity_map(struct kvm *kvm)
2355{
2356 int i, r, ret;
2357 pfn_t identity_map_pfn;
2358 u32 tmp;
2359
089d034e 2360 if (!enable_ept)
b7ebfb05
SY		 2361 return 1;
2362 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2363 printk(KERN_ERR "EPT: identity-mapping pagetable "
2364 "haven't been allocated!\n");
2365 return 0;
2366 }
2367 if (likely(kvm->arch.ept_identity_pagetable_done))
2368 return 1;
2369 ret = 0;
b927a3ce 2370 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2371 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2372 if (r < 0)
2373 goto out;
2374 /* Set up identity-mapping pagetable for EPT in real mode */
2375 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2376 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2377 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2378 r = kvm_write_guest_page(kvm, identity_map_pfn,
2379 &tmp, i * sizeof(tmp), sizeof(tmp));
2380 if (r < 0)
2381 goto out;
2382 }
2383 kvm->arch.ept_identity_pagetable_done = true;
2384 ret = 1;
2385out:
2386 return ret;
2387}
2388
6aa8b732
AK		 2389static void seg_setup(int seg)
2390{
2391 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2392 unsigned int ar;
6aa8b732
AK		 2393
2394 vmcs_write16(sf->selector, 0);
2395 vmcs_writel(sf->base, 0);
2396 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2397 if (enable_unrestricted_guest) {
2398 ar = 0x93;
2399 if (seg == VCPU_SREG_CS)
2400 ar |= 0x08; /* code segment */
2401 } else
2402 ar = 0xf3;
2403
2404 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2405}
2406
f78e0e2e
SY		 2407static int alloc_apic_access_page(struct kvm *kvm)
2408{
2409 struct kvm_userspace_memory_region kvm_userspace_mem;
2410 int r = 0;
2411
79fac95e 2412 mutex_lock(&kvm->slots_lock);
bfc6d222 2413 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2414 goto out;
2415 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2416 kvm_userspace_mem.flags = 0;
2417 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2418 kvm_userspace_mem.memory_size = PAGE_SIZE;
2419 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2420 if (r)
2421 goto out;
72dc67a6 2422
bfc6d222 2423 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2424out:
79fac95e 2425 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2426 return r;
2427}
2428
b7ebfb05
SY		 2429static int alloc_identity_pagetable(struct kvm *kvm)
2430{
2431 struct kvm_userspace_memory_region kvm_userspace_mem;
2432 int r = 0;
2433
79fac95e 2434 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2435 if (kvm->arch.ept_identity_pagetable)
2436 goto out;
2437 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2438 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2439 kvm_userspace_mem.guest_phys_addr =
2440 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2441 kvm_userspace_mem.memory_size = PAGE_SIZE;
2442 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2443 if (r)
2444 goto out;
2445
b7ebfb05 2446 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2447 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2448out:
79fac95e 2449 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2450 return r;
2451}
2452
2384d2b3
SY		 2453static void allocate_vpid(struct vcpu_vmx *vmx)
2454{
2455 int vpid;
2456
2457 vmx->vpid = 0;
919818ab 2458 if (!enable_vpid)
2384d2b3
SY		 2459 return;
2460 spin_lock(&vmx_vpid_lock);
2461 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2462 if (vpid < VMX_NR_VPIDS) {
2463 vmx->vpid = vpid;
2464 __set_bit(vpid, vmx_vpid_bitmap);
2465 }
2466 spin_unlock(&vmx_vpid_lock);
2467}
2468
cdbecfc3
LJ		 2469static void free_vpid(struct vcpu_vmx *vmx)
2470{
2471 if (!enable_vpid)
2472 return;
2473 spin_lock(&vmx_vpid_lock);
2474 if (vmx->vpid != 0)
2475 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2476 spin_unlock(&vmx_vpid_lock);
2477}
2478
5897297b 2479static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2480{
3e7c73e9 2481 int f = sizeof(unsigned long);
25c5f225
SY		 2482
2483 if (!cpu_has_vmx_msr_bitmap())
2484 return;
2485
2486 /*
2487 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2488 * have the write-low and read-high bitmap offsets the wrong way round.
2489 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2490 */
25c5f225 2491 if (msr <= 0x1fff) {
3e7c73e9
AK		 2492 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2493 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2494 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2495 msr &= 0x1fff;
3e7c73e9
AK		 2496 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2497 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2498 }
25c5f225
SY		 2499}
2500
5897297b
AK		 2501static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2502{
2503 if (!longmode_only)
2504 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2505 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2506}
2507
6aa8b732
AK		 2508/*
2509 * Sets up the vmcs for emulated real mode.
2510 */
8b9cf98c 2511static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2512{
468d472f 2513 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2514 u32 junk;
f4e1b3c8 2515 u64 host_pat;
6aa8b732 2516 unsigned long a;
89a27f4d 2517 struct desc_ptr dt;
6aa8b732 2518 int i;
cd2276a7 2519 unsigned long kvm_vmx_return;
6e5d865c 2520 u32 exec_control;
6aa8b732 2521
6aa8b732 2522 /* I/O */
3e7c73e9
AK		 2523 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2524 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2525
25c5f225 2526 if (cpu_has_vmx_msr_bitmap())
5897297b 2527 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2528
6aa8b732
AK		 2529 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2530
6aa8b732 2531 /* Control */
1c3d14fe
YS		 2532 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2533 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2534
2535 exec_control = vmcs_config.cpu_based_exec_ctrl;
2536 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2537 exec_control &= ~CPU_BASED_TPR_SHADOW;
2538#ifdef CONFIG_X86_64
2539 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2540 CPU_BASED_CR8_LOAD_EXITING;
2541#endif
2542 }
089d034e 2543 if (!enable_ept)
d56f546d 2544 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2545 CPU_BASED_CR3_LOAD_EXITING |
2546 CPU_BASED_INVLPG_EXITING;
6e5d865c 2547 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2548
83ff3b9d
SY		 2549 if (cpu_has_secondary_exec_ctrls()) {
2550 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2551 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2552 exec_control &=
2553 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2554 if (vmx->vpid == 0)
2555 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2556 if (!enable_ept) {
d56f546d 2557 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2558 enable_unrestricted_guest = 0;
2559 }
3a624e29
NK		 2560 if (!enable_unrestricted_guest)
2561 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2562 if (!ple_gap)
2563 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2564 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2565 }
f78e0e2e 2566
4b8d54f9
ZE		 2567 if (ple_gap) {
2568 vmcs_write32(PLE_GAP, ple_gap);
2569 vmcs_write32(PLE_WINDOW, ple_window);
2570 }
2571
c7addb90
AK		 2572 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2573 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2574 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2575
1c11e713 2576 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2577 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2578 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2579
2580 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2581 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2582 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
9581d442
AK		 2583 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2584 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6aa8b732 2585 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2586#ifdef CONFIG_X86_64
6aa8b732
AK		 2587 rdmsrl(MSR_FS_BASE, a);
2588 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2589 rdmsrl(MSR_GS_BASE, a);
2590 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2591#else
2592 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2593 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2594#endif
2595
2596 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2597
ec68798c 2598 native_store_idt(&dt);
89a27f4d 2599 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2600
d77c26fc 2601 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2602 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2603 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2604 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2605 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2606 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2607 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2608
2609 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2610 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2611 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2612 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2613 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2614 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2615
468d472f
SY		 2616 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2617 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2618 host_pat = msr_low | ((u64) msr_high << 32);
2619 vmcs_write64(HOST_IA32_PAT, host_pat);
2620 }
2621 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2622 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2623 host_pat = msr_low | ((u64) msr_high << 32);
2624 /* Write the default value follow host pat */
2625 vmcs_write64(GUEST_IA32_PAT, host_pat);
2626 /* Keep arch.pat sync with GUEST_IA32_PAT */
2627 vmx->vcpu.arch.pat = host_pat;
2628 }
2629
6aa8b732
AK		 2630 for (i = 0; i < NR_VMX_MSR; ++i) {
2631 u32 index = vmx_msr_index[i];
2632 u32 data_low, data_high;
a2fa3e9f 2633 int j = vmx->nmsrs;
6aa8b732
AK		 2634
2635 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2636 continue;
432bd6cb
AK		 2637 if (wrmsr_safe(index, data_low, data_high) < 0)
2638 continue;
26bb0981
AK		 2639 vmx->guest_msrs[j].index = i;
2640 vmx->guest_msrs[j].data = 0;
d5696725 2641 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2642 ++vmx->nmsrs;
6aa8b732 2643 }
6aa8b732 2644
1c3d14fe 2645 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2646
2647 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2648 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2649
e00c8cf2 2650 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2651 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2652 if (enable_ept)
2653 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2654 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2655
f4e1b3c8 2656 vmx_write_tsc_offset(0-native_read_tsc());
f78e0e2e 2657
e00c8cf2
AK		 2658 return 0;
2659}
2660
b7ebfb05
SY		 2661static int init_rmode(struct kvm *kvm)
2662{
4b9d3a04
XG		 2663 int idx, ret = 0;
2664
2665 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05 2666 if (!init_rmode_tss(kvm))
4b9d3a04 2667 goto exit;
b7ebfb05 2668 if (!init_rmode_identity_map(kvm))
4b9d3a04
XG		 2669 goto exit;
2670
2671 ret = 1;
2672exit:
2673 srcu_read_unlock(&kvm->srcu, idx);
2674 return ret;
b7ebfb05
SY		 2675}
2676
e00c8cf2
AK		 2677static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2678{
2679 struct vcpu_vmx *vmx = to_vmx(vcpu);
2680 u64 msr;
4b9d3a04 2681 int ret;
e00c8cf2 2682
5fdbf976 2683 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
b7ebfb05 2684 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2685 ret = -ENOMEM;
2686 goto out;
2687 }
2688
7ffd92c5 2689 vmx->rmode.vm86_active = 0;
e00c8cf2 2690
3b86cd99
JK		 2691 vmx->soft_vnmi_blocked = 0;
2692
ad312c7c 2693 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2694 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2695 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2696 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2697 msr |= MSR_IA32_APICBASE_BSP;
2698 kvm_set_apic_base(&vmx->vcpu, msr);
2699
10ab25cd
JK		 2700 ret = fx_init(&vmx->vcpu);
2701 if (ret != 0)
2702 goto out;
e00c8cf2 2703
5706be0d 2704 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2705 /*
2706 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2707 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2708 */
c5af89b6 2709 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2710 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2711 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2712 } else {
ad312c7c
ZX		 2713 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2714 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2715 }
e00c8cf2
AK		 2716
2717 seg_setup(VCPU_SREG_DS);
2718 seg_setup(VCPU_SREG_ES);
2719 seg_setup(VCPU_SREG_FS);
2720 seg_setup(VCPU_SREG_GS);
2721 seg_setup(VCPU_SREG_SS);
2722
2723 vmcs_write16(GUEST_TR_SELECTOR, 0);
2724 vmcs_writel(GUEST_TR_BASE, 0);
2725 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2726 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2727
2728 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2729 vmcs_writel(GUEST_LDTR_BASE, 0);
2730 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2731 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2732
2733 vmcs_write32(GUEST_SYSENTER_CS, 0);
2734 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2735 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2736
2737 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2738 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2739 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2740 else
5fdbf976
MT		 2741 kvm_rip_write(vcpu, 0);
2742 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2743
e00c8cf2
AK		 2744 vmcs_writel(GUEST_DR7, 0x400);
2745
2746 vmcs_writel(GUEST_GDTR_BASE, 0);
2747 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2748
2749 vmcs_writel(GUEST_IDTR_BASE, 0);
2750 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2751
2752 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2753 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2754 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2755
e00c8cf2
AK		 2756 /* Special registers */
2757 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2758
2759 setup_msrs(vmx);
2760
6aa8b732
AK		 2761 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2762
f78e0e2e
SY		 2763 if (cpu_has_vmx_tpr_shadow()) {
2764 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2765 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2766 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2767 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2768 vmcs_write32(TPR_THRESHOLD, 0);
2769 }
2770
2771 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2772 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2773 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2774
2384d2b3
SY		 2775 if (vmx->vpid != 0)
2776 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2777
fa40052c 2778 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2779 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2780 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2781 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2782 vmx_fpu_activate(&vmx->vcpu);
2783 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2784
b9d762fa 2785 vpid_sync_context(vmx);
2384d2b3 2786
3200f405 2787 ret = 0;
6aa8b732 2788
a89a8fb9
MG		 2789 /* HACK: Don't enable emulation on guest boot/reset */
2790 vmx->emulation_required = 0;
2791
6aa8b732
AK		 2792out:
2793 return ret;
2794}
2795
3b86cd99
JK		 2796static void enable_irq_window(struct kvm_vcpu *vcpu)
2797{
2798 u32 cpu_based_vm_exec_control;
2799
2800 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2801 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2802 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2803}
2804
2805static void enable_nmi_window(struct kvm_vcpu *vcpu)
2806{
2807 u32 cpu_based_vm_exec_control;
2808
2809 if (!cpu_has_virtual_nmis()) {
2810 enable_irq_window(vcpu);
2811 return;
2812 }
2813
2814 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2815 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2816 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2817}
2818
66fd3f7f 2819static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2820{
9c8cba37 2821 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2822 uint32_t intr;
2823 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2824
229456fc 2825 trace_kvm_inj_virq(irq);
2714d1d3 2826
fa89a817 2827 ++vcpu->stat.irq_injections;
7ffd92c5 2828 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2829 vmx->rmode.irq.pending = true;
2830 vmx->rmode.irq.vector = irq;
5fdbf976 2831 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2832 if (vcpu->arch.interrupt.soft)
2833 vmx->rmode.irq.rip +=
2834 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2835 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2836 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2837 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2838 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2839 return;
2840 }
66fd3f7f
GN		 2841 intr = irq | INTR_INFO_VALID_MASK;
2842 if (vcpu->arch.interrupt.soft) {
2843 intr |= INTR_TYPE_SOFT_INTR;
2844 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2845 vmx->vcpu.arch.event_exit_inst_len);
2846 } else
2847 intr |= INTR_TYPE_EXT_INTR;
2848 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2849}
2850
f08864b4
SY		 2851static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2852{
66a5a347
JK		 2853 struct vcpu_vmx *vmx = to_vmx(vcpu);
2854
3b86cd99
JK		 2855 if (!cpu_has_virtual_nmis()) {
2856 /*
2857 * Tracking the NMI-blocked state in software is built upon
2858 * finding the next open IRQ window. This, in turn, depends on
2859 * well-behaving guests: They have to keep IRQs disabled at
2860 * least as long as the NMI handler runs. Otherwise we may
2861 * cause NMI nesting, maybe breaking the guest. But as this is
2862 * highly unlikely, we can live with the residual risk.
2863 */
2864 vmx->soft_vnmi_blocked = 1;
2865 vmx->vnmi_blocked_time = 0;
2866 }
2867
487b391d 2868 ++vcpu->stat.nmi_injections;
7ffd92c5 2869 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2870 vmx->rmode.irq.pending = true;
2871 vmx->rmode.irq.vector = NMI_VECTOR;
2872 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2873 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2874 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2875 INTR_INFO_VALID_MASK);
2876 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2877 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2878 return;
2879 }
f08864b4
SY		 2880 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2881 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2882}
2883
c4282df9 2884static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2885{
3b86cd99 2886 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2887 return 0;
33f089ca 2888
c4282df9 2889 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
f8c5fae1 2890 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2891}
2892
3cfc3092
JK		 2893static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2894{
2895 if (!cpu_has_virtual_nmis())
2896 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2897 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2898}
2899
2900static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2901{
2902 struct vcpu_vmx *vmx = to_vmx(vcpu);
2903
2904 if (!cpu_has_virtual_nmis()) {
2905 if (vmx->soft_vnmi_blocked != masked) {
2906 vmx->soft_vnmi_blocked = masked;
2907 vmx->vnmi_blocked_time = 0;
2908 }
2909 } else {
2910 if (masked)
2911 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2912 GUEST_INTR_STATE_NMI);
2913 else
2914 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2915 GUEST_INTR_STATE_NMI);
2916 }
2917}
2918
78646121
GN		 2919static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2920{
c4282df9
GN		 2921 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2922 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2923 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2924}
2925
cbc94022
IE		 2926static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2927{
2928 int ret;
2929 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2930 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2931 .guest_phys_addr = addr,
2932 .memory_size = PAGE_SIZE * 3,
2933 .flags = 0,
2934 };
2935
2936 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2937 if (ret)
2938 return ret;
bfc6d222 2939 kvm->arch.tss_addr = addr;
cbc94022
IE		 2940 return 0;
2941}
2942
6aa8b732
AK		 2943static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2944 int vec, u32 err_code)
2945{
b3f37707
NK		 2946 /*
2947 * Instruction with address size override prefix opcode 0x67
2948 * Cause the #SS fault with 0 error code in VM86 mode.
2949 */
2950 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2951 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2952 return 1;
77ab6db0
JK		 2953 /*
2954 * Forward all other exceptions that are valid in real mode.
2955 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2956 * the required debugging infrastructure rework.
2957 */
2958 switch (vec) {
77ab6db0 2959 case DB_VECTOR:
d0bfb940
JK		 2960 if (vcpu->guest_debug &
2961 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2962 return 0;
2963 kvm_queue_exception(vcpu, vec);
2964 return 1;
77ab6db0 2965 case BP_VECTOR:
c573cd22
JK		 2966 /*
2967 * Update instruction length as we may reinject the exception
2968 * from user space while in guest debugging mode.
2969 */
2970 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2971 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2972 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2973 return 0;
2974 /* fall through */
2975 case DE_VECTOR:
77ab6db0
JK		 2976 case OF_VECTOR:
2977 case BR_VECTOR:
2978 case UD_VECTOR:
2979 case DF_VECTOR:
2980 case SS_VECTOR:
2981 case GP_VECTOR:
2982 case MF_VECTOR:
2983 kvm_queue_exception(vcpu, vec);
2984 return 1;
2985 }
6aa8b732
AK		 2986 return 0;
2987}
2988
a0861c02
AK		 2989/*
2990 * Trigger machine check on the host. We assume all the MSRs are already set up
2991 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2992 * We pass a fake environment to the machine check handler because we want
2993 * the guest to be always treated like user space, no matter what context
2994 * it used internally.
2995 */
2996static void kvm_machine_check(void)
2997{
2998#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2999 struct pt_regs regs = {
3000 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3001 .flags = X86_EFLAGS_IF,
3002 };
3003
3004 do_machine_check(&regs, 0);
3005#endif
3006}
3007
851ba692 3008static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3009{
3010 /* already handled by vcpu_run */
3011 return 1;
3012}
3013
851ba692 3014static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3015{
1155f76a 3016 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3017 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3018 u32 intr_info, ex_no, error_code;
42dbaa5a 3019 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3020 u32 vect_info;
3021 enum emulation_result er;
3022
1155f76a 3023 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 3024 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3025
a0861c02 3026 if (is_machine_check(intr_info))
851ba692 3027 return handle_machine_check(vcpu);
a0861c02 3028
6aa8b732 3029 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3030 !is_page_fault(intr_info)) {
3031 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3032 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3033 vcpu->run->internal.ndata = 2;
3034 vcpu->run->internal.data[0] = vect_info;
3035 vcpu->run->internal.data[1] = intr_info;
3036 return 0;
3037 }
6aa8b732 3038
e4a41889 3039 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3040 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3041
3042 if (is_no_device(intr_info)) {
5fd86fcf 3043 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3044 return 1;
3045 }
3046
7aa81cc0 3047 if (is_invalid_opcode(intr_info)) {
851ba692 3048 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 3049 if (er != EMULATE_DONE)
7ee5d940 3050 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3051 return 1;
3052 }
3053
6aa8b732 3054 error_code = 0;
5fdbf976 3055 rip = kvm_rip_read(vcpu);
2e11384c 3056 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3057 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3058 if (is_page_fault(intr_info)) {
1439442c 3059 /* EPT won't cause page fault directly */
089d034e 3060 if (enable_ept)
1439442c 3061 BUG();
6aa8b732 3062 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3063 trace_kvm_page_fault(cr2, error_code);
3064
3298b75c 3065 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3066 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 3067 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 3068 }
3069
7ffd92c5 3070 if (vmx->rmode.vm86_active &&
6aa8b732 3071 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3072 error_code)) {
ad312c7c
ZX		 3073 if (vcpu->arch.halt_request) {
3074 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3075 return kvm_emulate_halt(vcpu);
3076 }
6aa8b732 3077 return 1;
72d6e5a0 3078 }
6aa8b732 3079
d0bfb940 3080 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3081 switch (ex_no) {
3082 case DB_VECTOR:
3083 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3084 if (!(vcpu->guest_debug &
3085 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3086 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3087 kvm_queue_exception(vcpu, DB_VECTOR);
3088 return 1;
3089 }
3090 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3091 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3092 /* fall through */
3093 case BP_VECTOR:
c573cd22
JK		 3094 /*
3095 * Update instruction length as we may reinject #BP from
3096 * user space while in guest debugging mode. Reading it for
3097 * #DB as well causes no harm, it is not used in that case.
3098 */
3099 vmx->vcpu.arch.event_exit_inst_len =
3100 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3101 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3102 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3103 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3104 break;
3105 default:
d0bfb940
JK		 3106 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3107 kvm_run->ex.exception = ex_no;
3108 kvm_run->ex.error_code = error_code;
42dbaa5a 3109 break;
6aa8b732 3110 }
6aa8b732
AK		 3111 return 0;
3112}
3113
851ba692 3114static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3115{
1165f5fe 3116 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3117 return 1;
3118}
3119
851ba692 3120static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3121{
851ba692 3122 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3123 return 0;
3124}
6aa8b732 3125
851ba692 3126static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3127{
bfdaab09 3128 unsigned long exit_qualification;
34c33d16 3129 int size, in, string;
039576c0 3130 unsigned port;
6aa8b732 3131
bfdaab09 3132 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3133 string = (exit_qualification & 16) != 0;
cf8f70bf 3134 in = (exit_qualification & 8) != 0;
e70669ab 3135
cf8f70bf 3136 ++vcpu->stat.io_exits;
e70669ab 3137
cf8f70bf 3138 if (string || in)
6d77dbfc 3139 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
e70669ab 3140
cf8f70bf
GN		 3141 port = exit_qualification >> 16;
3142 size = (exit_qualification & 7) + 1;
e93f36bc 3143 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3144
3145 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3146}
3147
102d8325
IM		 3148static void
3149vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3150{
3151 /*
3152 * Patch in the VMCALL instruction:
3153 */
3154 hypercall[0] = 0x0f;
3155 hypercall[1] = 0x01;
3156 hypercall[2] = 0xc1;
102d8325
IM		 3157}
3158
49a9b07e
AK		 3159static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3160{
3161 if (err)
3162 kvm_inject_gp(vcpu, 0);
3163 else
3164 skip_emulated_instruction(vcpu);
3165}
3166
851ba692 3167static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3168{
229456fc 3169 unsigned long exit_qualification, val;
6aa8b732
AK		 3170 int cr;
3171 int reg;
49a9b07e 3172 int err;
6aa8b732 3173
bfdaab09 3174 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3175 cr = exit_qualification & 15;
3176 reg = (exit_qualification >> 8) & 15;
3177 switch ((exit_qualification >> 4) & 3) {
3178 case 0: /* mov to cr */
229456fc
MT		 3179 val = kvm_register_read(vcpu, reg);
3180 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3181 switch (cr) {
3182 case 0:
49a9b07e
AK		 3183 err = kvm_set_cr0(vcpu, val);
3184 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3185 return 1;
3186 case 3:
2390218b
AK		 3187 err = kvm_set_cr3(vcpu, val);
3188 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3189 return 1;
3190 case 4:
a83b29c6
AK		 3191 err = kvm_set_cr4(vcpu, val);
3192 complete_insn_gp(vcpu, err);
6aa8b732 3193 return 1;
0a5fff19
GN		 3194 case 8: {
3195 u8 cr8_prev = kvm_get_cr8(vcpu);
3196 u8 cr8 = kvm_register_read(vcpu, reg);
3197 kvm_set_cr8(vcpu, cr8);
3198 skip_emulated_instruction(vcpu);
3199 if (irqchip_in_kernel(vcpu->kvm))
3200 return 1;
3201 if (cr8_prev <= cr8)
3202 return 1;
851ba692 3203 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3204 return 0;
3205 }
6aa8b732
AK		 3206 };
3207 break;
25c4c276 3208 case 2: /* clts */
edcafe3c 3209 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3210 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3211 skip_emulated_instruction(vcpu);
6b52d186 3212 vmx_fpu_activate(vcpu);
25c4c276 3213 return 1;
6aa8b732
AK		 3214 case 1: /*mov from cr*/
3215 switch (cr) {
3216 case 3:
5fdbf976 3217 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3218 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3219 skip_emulated_instruction(vcpu);
3220 return 1;
3221 case 8:
229456fc
MT		 3222 val = kvm_get_cr8(vcpu);
3223 kvm_register_write(vcpu, reg, val);
3224 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3225 skip_emulated_instruction(vcpu);
3226 return 1;
3227 }
3228 break;
3229 case 3: /* lmsw */
a1f83a74 3230 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3231 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3232 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3233
3234 skip_emulated_instruction(vcpu);
3235 return 1;
3236 default:
3237 break;
3238 }
851ba692 3239 vcpu->run->exit_reason = 0;
f0242478 3240 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3241 (int)(exit_qualification >> 4) & 3, cr);
3242 return 0;
3243}
3244
851ba692 3245static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3246{
bfdaab09 3247 unsigned long exit_qualification;
6aa8b732
AK		 3248 int dr, reg;
3249
f2483415 3250 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3251 if (!kvm_require_cpl(vcpu, 0))
3252 return 1;
42dbaa5a
JK		 3253 dr = vmcs_readl(GUEST_DR7);
3254 if (dr & DR7_GD) {
3255 /*
3256 * As the vm-exit takes precedence over the debug trap, we
3257 * need to emulate the latter, either for the host or the
3258 * guest debugging itself.
3259 */
3260 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3261 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3262 vcpu->run->debug.arch.dr7 = dr;
3263 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3264 vmcs_readl(GUEST_CS_BASE) +
3265 vmcs_readl(GUEST_RIP);
851ba692
AK		 3266 vcpu->run->debug.arch.exception = DB_VECTOR;
3267 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3268 return 0;
3269 } else {
3270 vcpu->arch.dr7 &= ~DR7_GD;
3271 vcpu->arch.dr6 |= DR6_BD;
3272 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3273 kvm_queue_exception(vcpu, DB_VECTOR);
3274 return 1;
3275 }
3276 }
3277
bfdaab09 3278 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3279 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3280 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3281 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3282 unsigned long val;
3283 if (!kvm_get_dr(vcpu, dr, &val))
3284 kvm_register_write(vcpu, reg, val);
3285 } else
3286 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3287 skip_emulated_instruction(vcpu);
3288 return 1;
3289}
3290
020df079
GN		 3291static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3292{
3293 vmcs_writel(GUEST_DR7, val);
3294}
3295
851ba692 3296static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3297{
06465c5a
AK		 3298 kvm_emulate_cpuid(vcpu);
3299 return 1;
6aa8b732
AK		 3300}
3301
851ba692 3302static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3303{
ad312c7c 3304 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3305 u64 data;
3306
3307 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3308 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3309 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3310 return 1;
3311 }
3312
229456fc 3313 trace_kvm_msr_read(ecx, data);
2714d1d3 3314
6aa8b732 3315 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3316 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3317 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3318 skip_emulated_instruction(vcpu);
3319 return 1;
3320}
3321
851ba692 3322static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3323{
ad312c7c
ZX		 3324 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3325 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3326 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3327
3328 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3329 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3330 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3331 return 1;
3332 }
3333
59200273 3334 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3335 skip_emulated_instruction(vcpu);
3336 return 1;
3337}
3338
851ba692 3339static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3340{
3341 return 1;
3342}
3343
851ba692 3344static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3345{
85f455f7
ED		 3346 u32 cpu_based_vm_exec_control;
3347
3348 /* clear pending irq */
3349 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3350 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3351 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3352
a26bf12a 3353 ++vcpu->stat.irq_window_exits;
2714d1d3 3354
c1150d8c
DL		 3355 /*
3356 * If the user space waits to inject interrupts, exit as soon as
3357 * possible
3358 */
8061823a 3359 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3360 vcpu->run->request_interrupt_window &&
8061823a 3361 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3362 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3363 return 0;
3364 }
6aa8b732
AK		 3365 return 1;
3366}
3367
851ba692 3368static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3369{
3370 skip_emulated_instruction(vcpu);
d3bef15f 3371 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3372}
3373
851ba692 3374static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3375{
510043da 3376 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3377 kvm_emulate_hypercall(vcpu);
3378 return 1;
c21415e8
IM		 3379}
3380
851ba692 3381static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3382{
3383 kvm_queue_exception(vcpu, UD_VECTOR);
3384 return 1;
3385}
3386
851ba692 3387static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3388{
f9c617f6 3389 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3390
3391 kvm_mmu_invlpg(vcpu, exit_qualification);
3392 skip_emulated_instruction(vcpu);
3393 return 1;
3394}
3395
851ba692 3396static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3397{
3398 skip_emulated_instruction(vcpu);
f5f48ee1 3399 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3400 return 1;
3401}
3402
2acf923e
DC		 3403static int handle_xsetbv(struct kvm_vcpu *vcpu)
3404{
3405 u64 new_bv = kvm_read_edx_eax(vcpu);
3406 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3407
3408 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3409 skip_emulated_instruction(vcpu);
3410 return 1;
3411}
3412
851ba692 3413static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3414{
6d77dbfc 3415 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
f78e0e2e
SY		 3416}
3417
851ba692 3418static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3419{
60637aac 3420 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3421 unsigned long exit_qualification;
e269fb21
JK		 3422 bool has_error_code = false;
3423 u32 error_code = 0;
37817f29 3424 u16 tss_selector;
64a7ec06
GN		 3425 int reason, type, idt_v;
3426
3427 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3428 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3429
3430 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3431
3432 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3433 if (reason == TASK_SWITCH_GATE && idt_v) {
3434 switch (type) {
3435 case INTR_TYPE_NMI_INTR:
3436 vcpu->arch.nmi_injected = false;
3437 if (cpu_has_virtual_nmis())
3438 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3439 GUEST_INTR_STATE_NMI);
3440 break;
3441 case INTR_TYPE_EXT_INTR:
66fd3f7f 3442 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3443 kvm_clear_interrupt_queue(vcpu);
3444 break;
3445 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3446 if (vmx->idt_vectoring_info &
3447 VECTORING_INFO_DELIVER_CODE_MASK) {
3448 has_error_code = true;
3449 error_code =
3450 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3451 }
3452 /* fall through */
64a7ec06
GN		 3453 case INTR_TYPE_SOFT_EXCEPTION:
3454 kvm_clear_exception_queue(vcpu);
3455 break;
3456 default:
3457 break;
3458 }
60637aac 3459 }
37817f29
IE		 3460 tss_selector = exit_qualification;
3461
64a7ec06
GN		 3462 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3463 type != INTR_TYPE_EXT_INTR &&
3464 type != INTR_TYPE_NMI_INTR))
3465 skip_emulated_instruction(vcpu);
3466
acb54517
GN		 3467 if (kvm_task_switch(vcpu, tss_selector, reason,
3468 has_error_code, error_code) == EMULATE_FAIL) {
3469 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3470 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3471 vcpu->run->internal.ndata = 0;
42dbaa5a 3472 return 0;
acb54517 3473 }
42dbaa5a
JK		 3474
3475 /* clear all local breakpoint enable flags */
3476 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3477
3478 /*
3479 * TODO: What about debug traps on tss switch?
3480 * Are we supposed to inject them and update dr6?
3481 */
3482
3483 return 1;
37817f29
IE		 3484}
3485
851ba692 3486static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3487{
f9c617f6 3488 unsigned long exit_qualification;
1439442c 3489 gpa_t gpa;
1439442c 3490 int gla_validity;
1439442c 3491
f9c617f6 3492 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3493
3494 if (exit_qualification & (1 << 6)) {
3495 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3496 return -EINVAL;
1439442c
SY		 3497 }
3498
3499 gla_validity = (exit_qualification >> 7) & 0x3;
3500 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3501 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3502 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3503 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3504 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3505 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3506 (long unsigned int)exit_qualification);
851ba692
AK		 3507 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3508 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3509 return 0;
1439442c
SY		 3510 }
3511
3512 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3513 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3514 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3515}
3516
68f89400
MT		 3517static u64 ept_rsvd_mask(u64 spte, int level)
3518{
3519 int i;
3520 u64 mask = 0;
3521
3522 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3523 mask |= (1ULL << i);
3524
3525 if (level > 2)
3526 /* bits 7:3 reserved */
3527 mask |= 0xf8;
3528 else if (level == 2) {
3529 if (spte & (1ULL << 7))
3530 /* 2MB ref, bits 20:12 reserved */
3531 mask |= 0x1ff000;
3532 else
3533 /* bits 6:3 reserved */
3534 mask |= 0x78;
3535 }
3536
3537 return mask;
3538}
3539
3540static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3541 int level)
3542{
3543 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3544
3545 /* 010b (write-only) */
3546 WARN_ON((spte & 0x7) == 0x2);
3547
3548 /* 110b (write/execute) */
3549 WARN_ON((spte & 0x7) == 0x6);
3550
3551 /* 100b (execute-only) and value not supported by logical processor */
3552 if (!cpu_has_vmx_ept_execute_only())
3553 WARN_ON((spte & 0x7) == 0x4);
3554
3555 /* not 000b */
3556 if ((spte & 0x7)) {
3557 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3558
3559 if (rsvd_bits != 0) {
3560 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3561 __func__, rsvd_bits);
3562 WARN_ON(1);
3563 }
3564
3565 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3566 u64 ept_mem_type = (spte & 0x38) >> 3;
3567
3568 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3569 ept_mem_type == 7) {
3570 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3571 __func__, ept_mem_type);
3572 WARN_ON(1);
3573 }
3574 }
3575 }
3576}
3577
851ba692 3578static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3579{
3580 u64 sptes[4];
3581 int nr_sptes, i;
3582 gpa_t gpa;
3583
3584 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3585
3586 printk(KERN_ERR "EPT: Misconfiguration.\n");
3587 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3588
3589 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3590
3591 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3592 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3593
851ba692
AK		 3594 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3595 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3596
3597 return 0;
3598}
3599
851ba692 3600static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3601{
3602 u32 cpu_based_vm_exec_control;
3603
3604 /* clear pending NMI */
3605 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3606 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3607 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3608 ++vcpu->stat.nmi_window_exits;
3609
3610 return 1;
3611}
3612
80ced186 3613static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3614{
8b3079a5
AK		 3615 struct vcpu_vmx *vmx = to_vmx(vcpu);
3616 enum emulation_result err = EMULATE_DONE;
80ced186 3617 int ret = 1;
ea953ef0
MG		 3618
3619 while (!guest_state_valid(vcpu)) {
851ba692 3620 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3621
80ced186
MG		 3622 if (err == EMULATE_DO_MMIO) {
3623 ret = 0;
3624 goto out;
3625 }
1d5a4d9b 3626
6d77dbfc
GN		 3627 if (err != EMULATE_DONE)
3628 return 0;
ea953ef0
MG		 3629
3630 if (signal_pending(current))
80ced186 3631 goto out;
ea953ef0
MG		 3632 if (need_resched())
3633 schedule();
3634 }
3635
80ced186
MG		 3636 vmx->emulation_required = 0;
3637out:
3638 return ret;
ea953ef0
MG		 3639}
3640
4b8d54f9
ZE		 3641/*
3642 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3643 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3644 */
9fb41ba8 3645static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3646{
3647 skip_emulated_instruction(vcpu);
3648 kvm_vcpu_on_spin(vcpu);
3649
3650 return 1;
3651}
3652
59708670
SY		 3653static int handle_invalid_op(struct kvm_vcpu *vcpu)
3654{
3655 kvm_queue_exception(vcpu, UD_VECTOR);
3656 return 1;
3657}
3658
6aa8b732
AK		 3659/*
3660 * The exit handlers return 1 if the exit was handled fully and guest execution
3661 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3662 * to be done to userspace and return 0.
3663 */
851ba692 3664static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3665 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3666 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3667 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3668 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3669 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3670 [EXIT_REASON_CR_ACCESS] = handle_cr,
3671 [EXIT_REASON_DR_ACCESS] = handle_dr,
3672 [EXIT_REASON_CPUID] = handle_cpuid,
3673 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3674 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3675 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3676 [EXIT_REASON_HLT] = handle_halt,
a7052897 3677 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3678 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3679 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3680 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3681 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3682 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3683 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3684 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3685 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3686 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3687 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3688 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3689 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3690 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3691 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3692 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3693 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3694 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3695 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3696 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3697 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3698 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3699};
3700
3701static const int kvm_vmx_max_exit_handlers =
50a3485c 3702 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3703
3704/*
3705 * The guest has exited. See if we can fix it or if we need userspace
3706 * assistance.
3707 */
851ba692 3708static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3709{
29bd8a78 3710 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3711 u32 exit_reason = vmx->exit_reason;
1155f76a 3712 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3713
5bfd8b54 3714 trace_kvm_exit(exit_reason, vcpu);
2714d1d3 3715
80ced186
MG		 3716 /* If guest state is invalid, start emulating */
3717 if (vmx->emulation_required && emulate_invalid_guest_state)
3718 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3719
1439442c
SY		 3720 /* Access CR3 don't cause VMExit in paging mode, so we need
3721 * to sync with guest real CR3. */
6de4f3ad 3722 if (enable_ept && is_paging(vcpu))
1439442c 3723 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3724
5120702e
MG		 3725 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3726 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3727 vcpu->run->fail_entry.hardware_entry_failure_reason
3728 = exit_reason;
3729 return 0;
3730 }
3731
29bd8a78 3732 if (unlikely(vmx->fail)) {
851ba692
AK		 3733 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3734 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3735 = vmcs_read32(VM_INSTRUCTION_ERROR);
3736 return 0;
3737 }
6aa8b732 3738
d77c26fc 3739 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3740 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3741 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3742 exit_reason != EXIT_REASON_TASK_SWITCH))
3743 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3744 "(0x%x) and exit reason is 0x%x\n",
3745 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3746
3747 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3748 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3749 vmx->soft_vnmi_blocked = 0;
3b86cd99 3750 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3751 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3752 /*
3753 * This CPU don't support us in finding the end of an
3754 * NMI-blocked window if the guest runs with IRQs
3755 * disabled. So we pull the trigger after 1 s of
3756 * futile waiting, but inform the user about this.
3757 */
3758 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3759 "state on VCPU %d after 1 s timeout\n",
3760 __func__, vcpu->vcpu_id);
3761 vmx->soft_vnmi_blocked = 0;
3b86cd99 3762 }
3b86cd99
JK		 3763 }
3764
6aa8b732
AK		 3765 if (exit_reason < kvm_vmx_max_exit_handlers
3766 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3767 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3768 else {
851ba692
AK		 3769 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3770 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3771 }
3772 return 0;
3773}
3774
95ba8273 3775static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3776{
95ba8273 3777 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3778 vmcs_write32(TPR_THRESHOLD, 0);
3779 return;
3780 }
3781
95ba8273 3782 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3783}
3784
cf393f75
AK		 3785static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3786{
3787 u32 exit_intr_info;
7b4a25cb 3788 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3789 bool unblock_nmi;
3790 u8 vector;
668f612f
AK		 3791 int type;
3792 bool idtv_info_valid;
cf393f75
AK		 3793
3794 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3795
a0861c02
AK		 3796 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3797
3798 /* Handle machine checks before interrupts are enabled */
3799 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3800 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3801 && is_machine_check(exit_intr_info)))
3802 kvm_machine_check();
3803
20f65983
GN		 3804 /* We need to handle NMIs before interrupts are enabled */
3805 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3806 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3807 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3808 asm("int $2");
ff9d07a0
ZY		 3809 kvm_after_handle_nmi(&vmx->vcpu);
3810 }
20f65983
GN		 3811
3812 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3813
cf393f75
AK		 3814 if (cpu_has_virtual_nmis()) {
3815 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3816 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3817 /*
7b4a25cb 3818 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3819 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3820 * a guest IRET fault.
7b4a25cb
GN		 3821 * SDM 3: 23.2.2 (September 2008)
3822 * Bit 12 is undefined in any of the following cases:
3823 * If the VM exit sets the valid bit in the IDT-vectoring
3824 * information field.
3825 * If the VM exit is due to a double fault.
cf393f75 3826 */
7b4a25cb
GN		 3827 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3828 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3829 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3830 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3831 } else if (unlikely(vmx->soft_vnmi_blocked))
3832 vmx->vnmi_blocked_time +=
3833 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3834
37b96e98
GN		 3835 vmx->vcpu.arch.nmi_injected = false;
3836 kvm_clear_exception_queue(&vmx->vcpu);
3837 kvm_clear_interrupt_queue(&vmx->vcpu);
3838
3839 if (!idtv_info_valid)
3840 return;
3841
668f612f
AK		 3842 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3843 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3844
64a7ec06 3845 switch (type) {
37b96e98
GN		 3846 case INTR_TYPE_NMI_INTR:
3847 vmx->vcpu.arch.nmi_injected = true;
668f612f 3848 /*
7b4a25cb 3849 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3850 * Clear bit "block by NMI" before VM entry if a NMI
3851 * delivery faulted.
668f612f 3852 */
37b96e98
GN		 3853 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3854 GUEST_INTR_STATE_NMI);
3855 break;
37b96e98 3856 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3857 vmx->vcpu.arch.event_exit_inst_len =
3858 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3859 /* fall through */
3860 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3861 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3862 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3863 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3864 } else
3865 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3866 break;
66fd3f7f
GN		 3867 case INTR_TYPE_SOFT_INTR:
3868 vmx->vcpu.arch.event_exit_inst_len =
3869 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3870 /* fall through */
37b96e98 3871 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3872 kvm_queue_interrupt(&vmx->vcpu, vector,
3873 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3874 break;
3875 default:
3876 break;
f7d9238f 3877 }
cf393f75
AK		 3878}
3879
9c8cba37
AK		 3880/*
3881 * Failure to inject an interrupt should give us the information
3882 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3883 * when fetching the interrupt redirection bitmap in the real-mode
3884 * tss, this doesn't happen. So we do it ourselves.
3885 */
3886static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3887{
3888 vmx->rmode.irq.pending = 0;
5fdbf976 3889 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3890 return;
5fdbf976 3891 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3892 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3893 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3894 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3895 return;
3896 }
3897 vmx->idt_vectoring_info =
3898 VECTORING_INFO_VALID_MASK
3899 | INTR_TYPE_EXT_INTR
3900 | vmx->rmode.irq.vector;
3901}
3902
c801949d
AK		 3903#ifdef CONFIG_X86_64
3904#define R "r"
3905#define Q "q"
3906#else
3907#define R "e"
3908#define Q "l"
3909#endif
3910
851ba692 3911static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3912{
a2fa3e9f 3913 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3914
3b86cd99
JK		 3915 /* Record the guest's net vcpu time for enforced NMI injections. */
3916 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3917 vmx->entry_time = ktime_get();
3918
80ced186
MG		 3919 /* Don't enter VMX if guest state is invalid, let the exit handler
3920 start emulation until we arrive back to a valid state */
3921 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3922 return;
a89a8fb9 3923
5fdbf976
MT		 3924 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3925 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3926 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3927 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3928
787ff736
GN		 3929 /* When single-stepping over STI and MOV SS, we must clear the
3930 * corresponding interruptibility bits in the guest state. Otherwise
3931 * vmentry fails as it then expects bit 14 (BS) in pending debug
3932 * exceptions being set, but that's not correct for the guest debugging
3933 * case. */
3934 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3935 vmx_set_interrupt_shadow(vcpu, 0);
3936
d77c26fc 3937 asm(
6aa8b732 3938 /* Store host registers */
c801949d
AK		 3939 "push %%"R"dx; push %%"R"bp;"
3940 "push %%"R"cx \n\t"
313dbd49
AK		 3941 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3942 "je 1f \n\t"
3943 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3944 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3945 "1: \n\t"
d3edefc0
AK		 3946 /* Reload cr2 if changed */
3947 "mov %c[cr2](%0), %%"R"ax \n\t"
3948 "mov %%cr2, %%"R"dx \n\t"
3949 "cmp %%"R"ax, %%"R"dx \n\t"
3950 "je 2f \n\t"
3951 "mov %%"R"ax, %%cr2 \n\t"
3952 "2: \n\t"
6aa8b732 3953 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3954 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3955 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3956 "mov %c[rax](%0), %%"R"ax \n\t"
3957 "mov %c[rbx](%0), %%"R"bx \n\t"
3958 "mov %c[rdx](%0), %%"R"dx \n\t"
3959 "mov %c[rsi](%0), %%"R"si \n\t"
3960 "mov %c[rdi](%0), %%"R"di \n\t"
3961 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3962#ifdef CONFIG_X86_64
e08aa78a
AK		 3963 "mov %c[r8](%0), %%r8 \n\t"
3964 "mov %c[r9](%0), %%r9 \n\t"
3965 "mov %c[r10](%0), %%r10 \n\t"
3966 "mov %c[r11](%0), %%r11 \n\t"
3967 "mov %c[r12](%0), %%r12 \n\t"
3968 "mov %c[r13](%0), %%r13 \n\t"
3969 "mov %c[r14](%0), %%r14 \n\t"
3970 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3971#endif
c801949d
AK		 3972 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3973
6aa8b732 3974 /* Enter guest mode */
cd2276a7 3975 "jne .Llaunched \n\t"
4ecac3fd 3976 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3977 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3978 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3979 ".Lkvm_vmx_return: "
6aa8b732 3980 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3981 "xchg %0, (%%"R"sp) \n\t"
3982 "mov %%"R"ax, %c[rax](%0) \n\t"
3983 "mov %%"R"bx, %c[rbx](%0) \n\t"
3984 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3985 "mov %%"R"dx, %c[rdx](%0) \n\t"
3986 "mov %%"R"si, %c[rsi](%0) \n\t"
3987 "mov %%"R"di, %c[rdi](%0) \n\t"
3988 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3989#ifdef CONFIG_X86_64
e08aa78a
AK		 3990 "mov %%r8, %c[r8](%0) \n\t"
3991 "mov %%r9, %c[r9](%0) \n\t"
3992 "mov %%r10, %c[r10](%0) \n\t"
3993 "mov %%r11, %c[r11](%0) \n\t"
3994 "mov %%r12, %c[r12](%0) \n\t"
3995 "mov %%r13, %c[r13](%0) \n\t"
3996 "mov %%r14, %c[r14](%0) \n\t"
3997 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3998#endif
c801949d
AK		 3999 "mov %%cr2, %%"R"ax \n\t"
4000 "mov %%"R"ax, %c[cr2](%0) \n\t"
4001
4002 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 4003 "setbe %c[fail](%0) \n\t"
4004 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4005 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4006 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 4007 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 4008 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4009 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4010 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4011 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4012 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4013 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4014 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4015#ifdef CONFIG_X86_64
ad312c7c
ZX		 4016 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4017 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4018 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4019 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4020 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4021 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4022 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4023 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4024#endif
ad312c7c 4025 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 4026 : "cc", "memory"
c801949d 4027 , R"bx", R"di", R"si"
c2036300 4028#ifdef CONFIG_X86_64
c2036300
LV		 4029 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4030#endif
4031 );
6aa8b732 4032
6de4f3ad
AK		 4033 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4034 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 4035 vcpu->arch.regs_dirty = 0;
4036
1155f76a 4037 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 4038 if (vmx->rmode.irq.pending)
4039 fixup_rmode_irq(vmx);
1155f76a 4040
d77c26fc 4041 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4042 vmx->launched = 1;
1b6269db 4043
cf393f75 4044 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4045}
4046
c801949d
AK		 4047#undef R
4048#undef Q
4049
6aa8b732
AK		 4050static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4051{
a2fa3e9f
GH		 4052 struct vcpu_vmx *vmx = to_vmx(vcpu);
4053
4054 if (vmx->vmcs) {
543e4243 4055 vcpu_clear(vmx);
a2fa3e9f
GH		 4056 free_vmcs(vmx->vmcs);
4057 vmx->vmcs = NULL;
6aa8b732
AK		 4058 }
4059}
4060
4061static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4062{
fb3f0f51
RR		 4063 struct vcpu_vmx *vmx = to_vmx(vcpu);
4064
cdbecfc3 4065 free_vpid(vmx);
6aa8b732 4066 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4067 kfree(vmx->guest_msrs);
4068 kvm_vcpu_uninit(vcpu);
a4770347 4069 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4070}
4071
4610c9cc
DX		 4072static inline void vmcs_init(struct vmcs *vmcs)
4073{
4074 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4075
4076 if (!vmm_exclusive)
4077 kvm_cpu_vmxon(phys_addr);
4078
4079 vmcs_clear(vmcs);
4080
4081 if (!vmm_exclusive)
4082 kvm_cpu_vmxoff();
4083}
4084
fb3f0f51 4085static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4086{
fb3f0f51 4087 int err;
c16f862d 4088 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4089 int cpu;
6aa8b732 4090
a2fa3e9f 4091 if (!vmx)
fb3f0f51
RR		 4092 return ERR_PTR(-ENOMEM);
4093
2384d2b3
SY		 4094 allocate_vpid(vmx);
4095
fb3f0f51
RR		 4096 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4097 if (err)
4098 goto free_vcpu;
965b58a5 4099
a2fa3e9f 4100 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4101 if (!vmx->guest_msrs) {
4102 err = -ENOMEM;
4103 goto uninit_vcpu;
4104 }
965b58a5 4105
a2fa3e9f
GH		 4106 vmx->vmcs = alloc_vmcs();
4107 if (!vmx->vmcs)
fb3f0f51 4108 goto free_msrs;
a2fa3e9f 4109
4610c9cc 4110 vmcs_init(vmx->vmcs);
a2fa3e9f 4111
15ad7146
AK		 4112 cpu = get_cpu();
4113 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 4114 err = vmx_vcpu_setup(vmx);
fb3f0f51 4115 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4116 put_cpu();
fb3f0f51
RR		 4117 if (err)
4118 goto free_vmcs;
5e4a0b3c
MT		 4119 if (vm_need_virtualize_apic_accesses(kvm))
4120 if (alloc_apic_access_page(kvm) != 0)
4121 goto free_vmcs;
fb3f0f51 4122
b927a3ce
SY		 4123 if (enable_ept) {
4124 if (!kvm->arch.ept_identity_map_addr)
4125 kvm->arch.ept_identity_map_addr =
4126 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4127 if (alloc_identity_pagetable(kvm) != 0)
4128 goto free_vmcs;
b927a3ce 4129 }
b7ebfb05 4130
fb3f0f51
RR		 4131 return &vmx->vcpu;
4132
4133free_vmcs:
4134 free_vmcs(vmx->vmcs);
4135free_msrs:
fb3f0f51
RR		 4136 kfree(vmx->guest_msrs);
4137uninit_vcpu:
4138 kvm_vcpu_uninit(&vmx->vcpu);
4139free_vcpu:
cdbecfc3 4140 free_vpid(vmx);
a4770347 4141 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4142 return ERR_PTR(err);
6aa8b732
AK		 4143}
4144
002c7f7c
YS		 4145static void __init vmx_check_processor_compat(void *rtn)
4146{
4147 struct vmcs_config vmcs_conf;
4148
4149 *(int *)rtn = 0;
4150 if (setup_vmcs_config(&vmcs_conf) < 0)
4151 *(int *)rtn = -EIO;
4152 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4153 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4154 smp_processor_id());
4155 *(int *)rtn = -EIO;
4156 }
4157}
4158
67253af5
SY		 4159static int get_ept_level(void)
4160{
4161 return VMX_EPT_DEFAULT_GAW + 1;
4162}
4163
4b12f0de 4164static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4165{
4b12f0de
SY		 4166 u64 ret;
4167
522c68c4
SY		 4168 /* For VT-d and EPT combination
4169 * 1. MMIO: always map as UC
4170 * 2. EPT with VT-d:
4171 * a. VT-d without snooping control feature: can't guarantee the
4172 * result, try to trust guest.
4173 * b. VT-d with snooping control feature: snooping control feature of
4174 * VT-d engine can guarantee the cache correctness. Just set it
4175 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4176 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4177 * consistent with host MTRR
4178 */
4b12f0de
SY		 4179 if (is_mmio)
4180 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4181 else if (vcpu->kvm->arch.iommu_domain &&
4182 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4183 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4184 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4185 else
522c68c4 4186 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4187 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4188
4189 return ret;
64d4d521
SY		 4190}
4191
f4c9e87c
AK		 4192#define _ER(x) { EXIT_REASON_##x, #x }
4193
229456fc 4194static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4195 _ER(EXCEPTION_NMI),
4196 _ER(EXTERNAL_INTERRUPT),
4197 _ER(TRIPLE_FAULT),
4198 _ER(PENDING_INTERRUPT),
4199 _ER(NMI_WINDOW),
4200 _ER(TASK_SWITCH),
4201 _ER(CPUID),
4202 _ER(HLT),
4203 _ER(INVLPG),
4204 _ER(RDPMC),
4205 _ER(RDTSC),
4206 _ER(VMCALL),
4207 _ER(VMCLEAR),
4208 _ER(VMLAUNCH),
4209 _ER(VMPTRLD),
4210 _ER(VMPTRST),
4211 _ER(VMREAD),
4212 _ER(VMRESUME),
4213 _ER(VMWRITE),
4214 _ER(VMOFF),
4215 _ER(VMON),
4216 _ER(CR_ACCESS),
4217 _ER(DR_ACCESS),
4218 _ER(IO_INSTRUCTION),
4219 _ER(MSR_READ),
4220 _ER(MSR_WRITE),
4221 _ER(MWAIT_INSTRUCTION),
4222 _ER(MONITOR_INSTRUCTION),
4223 _ER(PAUSE_INSTRUCTION),
4224 _ER(MCE_DURING_VMENTRY),
4225 _ER(TPR_BELOW_THRESHOLD),
4226 _ER(APIC_ACCESS),
4227 _ER(EPT_VIOLATION),
4228 _ER(EPT_MISCONFIG),
4229 _ER(WBINVD),
229456fc
MT		 4230 { -1, NULL }
4231};
4232
f4c9e87c
AK		 4233#undef _ER
4234
17cc3935 4235static int vmx_get_lpage_level(void)
344f414f 4236{
878403b7
SY		 4237 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4238 return PT_DIRECTORY_LEVEL;
4239 else
4240 /* For shadow and EPT supported 1GB page */
4241 return PT_PDPE_LEVEL;
344f414f
JR		 4242}
4243
4e47c7a6
SY		 4244static inline u32 bit(int bitno)
4245{
4246 return 1 << (bitno & 31);
4247}
4248
0e851880
SY		 4249static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4250{
4e47c7a6
SY		 4251 struct kvm_cpuid_entry2 *best;
4252 struct vcpu_vmx *vmx = to_vmx(vcpu);
4253 u32 exec_control;
4254
4255 vmx->rdtscp_enabled = false;
4256 if (vmx_rdtscp_supported()) {
4257 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4258 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4259 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4260 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4261 vmx->rdtscp_enabled = true;
4262 else {
4263 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4264 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4265 exec_control);
4266 }
4267 }
4268 }
0e851880
SY		 4269}
4270
d4330ef2
JR		 4271static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4272{
4273}
4274
cbdd1bea 4275static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4276 .cpu_has_kvm_support = cpu_has_kvm_support,
4277 .disabled_by_bios = vmx_disabled_by_bios,
4278 .hardware_setup = hardware_setup,
4279 .hardware_unsetup = hardware_unsetup,
002c7f7c 4280 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4281 .hardware_enable = hardware_enable,
4282 .hardware_disable = hardware_disable,
04547156 4283 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4284
4285 .vcpu_create = vmx_create_vcpu,
4286 .vcpu_free = vmx_free_vcpu,
04d2cc77 4287 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4288
04d2cc77 4289 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4290 .vcpu_load = vmx_vcpu_load,
4291 .vcpu_put = vmx_vcpu_put,
4292
4293 .set_guest_debug = set_guest_debug,
4294 .get_msr = vmx_get_msr,
4295 .set_msr = vmx_set_msr,
4296 .get_segment_base = vmx_get_segment_base,
4297 .get_segment = vmx_get_segment,
4298 .set_segment = vmx_set_segment,
2e4d2653 4299 .get_cpl = vmx_get_cpl,
6aa8b732 4300 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4301 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4302 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4303 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4304 .set_cr3 = vmx_set_cr3,
4305 .set_cr4 = vmx_set_cr4,
6aa8b732 4306 .set_efer = vmx_set_efer,
6aa8b732
AK		 4307 .get_idt = vmx_get_idt,
4308 .set_idt = vmx_set_idt,
4309 .get_gdt = vmx_get_gdt,
4310 .set_gdt = vmx_set_gdt,
020df079 4311 .set_dr7 = vmx_set_dr7,
5fdbf976 4312 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4313 .get_rflags = vmx_get_rflags,
4314 .set_rflags = vmx_set_rflags,
ebcbab4c 4315 .fpu_activate = vmx_fpu_activate,
02daab21 4316 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4317
4318 .tlb_flush = vmx_flush_tlb,
6aa8b732 4319
6aa8b732 4320 .run = vmx_vcpu_run,
6062d012 4321 .handle_exit = vmx_handle_exit,
6aa8b732 4322 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4323 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4324 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4325 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4326 .set_irq = vmx_inject_irq,
95ba8273 4327 .set_nmi = vmx_inject_nmi,
298101da 4328 .queue_exception = vmx_queue_exception,
78646121 4329 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4330 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4331 .get_nmi_mask = vmx_get_nmi_mask,
4332 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4333 .enable_nmi_window = enable_nmi_window,
4334 .enable_irq_window = enable_irq_window,
4335 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4336
cbc94022 4337 .set_tss_addr = vmx_set_tss_addr,
67253af5 4338 .get_tdp_level = get_ept_level,
4b12f0de 4339 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4340
4341 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4342 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4343
4344 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4345
4346 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4347
4348 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4349
4350 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
6aa8b732
AK		 4351};
4352
4353static int __init vmx_init(void)
4354{
26bb0981
AK		 4355 int r, i;
4356
4357 rdmsrl_safe(MSR_EFER, &host_efer);
4358
4359 for (i = 0; i < NR_VMX_MSR; ++i)
4360 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4361
3e7c73e9 4362 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4363 if (!vmx_io_bitmap_a)
4364 return -ENOMEM;
4365
3e7c73e9 4366 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4367 if (!vmx_io_bitmap_b) {
4368 r = -ENOMEM;
4369 goto out;
4370 }
4371
5897297b
AK		 4372 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4373 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4374 r = -ENOMEM;
4375 goto out1;
4376 }
4377
5897297b
AK		 4378 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4379 if (!vmx_msr_bitmap_longmode) {
4380 r = -ENOMEM;
4381 goto out2;
4382 }
4383
fdef3ad1
HQ		 4384 /*
4385 * Allow direct access to the PC debug port (it is often used for I/O
4386 * delays, but the vmexits simply slow things down).
4387 */
3e7c73e9
AK		 4388 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4389 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4390
3e7c73e9 4391 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4392
5897297b
AK		 4393 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4394 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4395
2384d2b3
SY		 4396 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4397
0ee75bea
AK		 4398 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4399 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4400 if (r)
5897297b 4401 goto out3;
25c5f225 4402
5897297b
AK		 4403 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4404 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4405 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4406 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4407 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4408 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4409
089d034e 4410 if (enable_ept) {
1439442c 4411 bypass_guest_pf = 0;
5fdbcb9d 4412 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4413 VMX_EPT_WRITABLE_MASK);
534e38b4 4414 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4415 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4416 kvm_enable_tdp();
4417 } else
4418 kvm_disable_tdp();
1439442c 4419
c7addb90
AK		 4420 if (bypass_guest_pf)
4421 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4422
fdef3ad1
HQ		 4423 return 0;
4424
5897297b
AK		 4425out3:
4426 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4427out2:
5897297b 4428 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4429out1:
3e7c73e9 4430 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4431out:
3e7c73e9 4432 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4433 return r;
6aa8b732
AK		 4434}
4435
4436static void __exit vmx_exit(void)
4437{
5897297b
AK		 4438 free_page((unsigned long)vmx_msr_bitmap_legacy);
4439 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4440 free_page((unsigned long)vmx_io_bitmap_b);
4441 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4442
cb498ea2 4443 kvm_exit();
6aa8b732
AK		 4444}
4445
4446module_init(vmx_init)
4447module_exit(vmx_exit)
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