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Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
dca51e78 | 19 | #include <linux/blk-mq-pci.h> |
42f61420 | 20 | #include <linux/cpu.h> |
fd63e9ce | 21 | #include <linux/delay.h> |
ff5350a8 | 22 | #include <linux/dmi.h> |
b60503ba MW |
23 | #include <linux/errno.h> |
24 | #include <linux/fs.h> | |
25 | #include <linux/genhd.h> | |
4cc09e2d | 26 | #include <linux/hdreg.h> |
5aff9382 | 27 | #include <linux/idr.h> |
b60503ba MW |
28 | #include <linux/init.h> |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/kdev_t.h> | |
32 | #include <linux/kernel.h> | |
33 | #include <linux/mm.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/moduleparam.h> | |
77bf25ea | 36 | #include <linux/mutex.h> |
b60503ba | 37 | #include <linux/pci.h> |
be7b6275 | 38 | #include <linux/poison.h> |
c3bfe717 | 39 | #include <linux/ptrace.h> |
b60503ba MW |
40 | #include <linux/sched.h> |
41 | #include <linux/slab.h> | |
e1e5e564 | 42 | #include <linux/t10-pi.h> |
2d55cd5f | 43 | #include <linux/timer.h> |
b60503ba | 44 | #include <linux/types.h> |
2f8e2c87 | 45 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 46 | #include <asm/unaligned.h> |
a98e58e5 | 47 | #include <linux/sed-opal.h> |
797a796a | 48 | |
f11bb3e2 CH |
49 | #include "nvme.h" |
50 | ||
9d43cf64 | 51 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 52 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
53 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
54 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
c965809c | 55 | |
adf68f21 CH |
56 | /* |
57 | * We handle AEN commands ourselves and don't even let the | |
58 | * block layer know about them. | |
59 | */ | |
f866fc42 | 60 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) |
9d43cf64 | 61 | |
58ffacb5 MW |
62 | static int use_threaded_interrupts; |
63 | module_param(use_threaded_interrupts, int, 0); | |
64 | ||
8ffaadf7 JD |
65 | static bool use_cmb_sqes = true; |
66 | module_param(use_cmb_sqes, bool, 0644); | |
67 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
68 | ||
9a6b9458 | 69 | static struct workqueue_struct *nvme_workq; |
1fa6aead | 70 | |
1c63dc66 CH |
71 | struct nvme_dev; |
72 | struct nvme_queue; | |
b3fffdef | 73 | |
4cc06521 | 74 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 75 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 76 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 77 | |
1c63dc66 CH |
78 | /* |
79 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
80 | */ | |
81 | struct nvme_dev { | |
1c63dc66 CH |
82 | struct nvme_queue **queues; |
83 | struct blk_mq_tag_set tagset; | |
84 | struct blk_mq_tag_set admin_tagset; | |
85 | u32 __iomem *dbs; | |
86 | struct device *dev; | |
87 | struct dma_pool *prp_page_pool; | |
88 | struct dma_pool *prp_small_pool; | |
89 | unsigned queue_count; | |
90 | unsigned online_queues; | |
91 | unsigned max_qid; | |
92 | int q_depth; | |
93 | u32 db_stride; | |
1c63dc66 | 94 | void __iomem *bar; |
1c63dc66 | 95 | struct work_struct reset_work; |
5c8809e6 | 96 | struct work_struct remove_work; |
2d55cd5f | 97 | struct timer_list watchdog_timer; |
77bf25ea | 98 | struct mutex shutdown_lock; |
1c63dc66 | 99 | bool subsystem; |
1c63dc66 CH |
100 | void __iomem *cmb; |
101 | dma_addr_t cmb_dma_addr; | |
102 | u64 cmb_size; | |
103 | u32 cmbsz; | |
202021c1 | 104 | u32 cmbloc; |
1c63dc66 | 105 | struct nvme_ctrl ctrl; |
db3cbfff | 106 | struct completion ioq_wait; |
f9f38e33 HK |
107 | u32 *dbbuf_dbs; |
108 | dma_addr_t dbbuf_dbs_dma_addr; | |
109 | u32 *dbbuf_eis; | |
110 | dma_addr_t dbbuf_eis_dma_addr; | |
4d115420 | 111 | }; |
1fa6aead | 112 | |
f9f38e33 HK |
113 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
114 | { | |
115 | return qid * 2 * stride; | |
116 | } | |
117 | ||
118 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) | |
119 | { | |
120 | return (qid * 2 + 1) * stride; | |
121 | } | |
122 | ||
1c63dc66 CH |
123 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
124 | { | |
125 | return container_of(ctrl, struct nvme_dev, ctrl); | |
126 | } | |
127 | ||
b60503ba MW |
128 | /* |
129 | * An NVM Express queue. Each device has at least two (one for admin | |
130 | * commands and one for I/O commands). | |
131 | */ | |
132 | struct nvme_queue { | |
133 | struct device *q_dmadev; | |
091b6092 | 134 | struct nvme_dev *dev; |
b60503ba MW |
135 | spinlock_t q_lock; |
136 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 137 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 138 | volatile struct nvme_completion *cqes; |
42483228 | 139 | struct blk_mq_tags **tags; |
b60503ba MW |
140 | dma_addr_t sq_dma_addr; |
141 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
142 | u32 __iomem *q_db; |
143 | u16 q_depth; | |
6222d172 | 144 | s16 cq_vector; |
b60503ba MW |
145 | u16 sq_tail; |
146 | u16 cq_head; | |
c30341dc | 147 | u16 qid; |
e9539f47 MW |
148 | u8 cq_phase; |
149 | u8 cqe_seen; | |
f9f38e33 HK |
150 | u32 *dbbuf_sq_db; |
151 | u32 *dbbuf_cq_db; | |
152 | u32 *dbbuf_sq_ei; | |
153 | u32 *dbbuf_cq_ei; | |
b60503ba MW |
154 | }; |
155 | ||
71bd150c CH |
156 | /* |
157 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
158 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 159 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
160 | * allocated to store the PRP list. |
161 | */ | |
162 | struct nvme_iod { | |
d49187e9 | 163 | struct nvme_request req; |
f4800d6d CH |
164 | struct nvme_queue *nvmeq; |
165 | int aborted; | |
71bd150c | 166 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
167 | int nents; /* Used in scatterlist */ |
168 | int length; /* Of data, in bytes */ | |
169 | dma_addr_t first_dma; | |
bf684057 | 170 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
171 | struct scatterlist *sg; |
172 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
173 | }; |
174 | ||
175 | /* | |
176 | * Check we didin't inadvertently grow the command struct | |
177 | */ | |
178 | static inline void _nvme_check_size(void) | |
179 | { | |
180 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
181 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
182 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
183 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
184 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 185 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 186 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
187 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
188 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
189 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
190 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 191 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
f9f38e33 HK |
192 | BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); |
193 | } | |
194 | ||
195 | static inline unsigned int nvme_dbbuf_size(u32 stride) | |
196 | { | |
197 | return ((num_possible_cpus() + 1) * 8 * stride); | |
198 | } | |
199 | ||
200 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) | |
201 | { | |
202 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
203 | ||
204 | if (dev->dbbuf_dbs) | |
205 | return 0; | |
206 | ||
207 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, | |
208 | &dev->dbbuf_dbs_dma_addr, | |
209 | GFP_KERNEL); | |
210 | if (!dev->dbbuf_dbs) | |
211 | return -ENOMEM; | |
212 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, | |
213 | &dev->dbbuf_eis_dma_addr, | |
214 | GFP_KERNEL); | |
215 | if (!dev->dbbuf_eis) { | |
216 | dma_free_coherent(dev->dev, mem_size, | |
217 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
218 | dev->dbbuf_dbs = NULL; | |
219 | return -ENOMEM; | |
220 | } | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) | |
226 | { | |
227 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
228 | ||
229 | if (dev->dbbuf_dbs) { | |
230 | dma_free_coherent(dev->dev, mem_size, | |
231 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
232 | dev->dbbuf_dbs = NULL; | |
233 | } | |
234 | if (dev->dbbuf_eis) { | |
235 | dma_free_coherent(dev->dev, mem_size, | |
236 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); | |
237 | dev->dbbuf_eis = NULL; | |
238 | } | |
239 | } | |
240 | ||
241 | static void nvme_dbbuf_init(struct nvme_dev *dev, | |
242 | struct nvme_queue *nvmeq, int qid) | |
243 | { | |
244 | if (!dev->dbbuf_dbs || !qid) | |
245 | return; | |
246 | ||
247 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; | |
248 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; | |
249 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; | |
250 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; | |
251 | } | |
252 | ||
253 | static void nvme_dbbuf_set(struct nvme_dev *dev) | |
254 | { | |
255 | struct nvme_command c; | |
256 | ||
257 | if (!dev->dbbuf_dbs) | |
258 | return; | |
259 | ||
260 | memset(&c, 0, sizeof(c)); | |
261 | c.dbbuf.opcode = nvme_admin_dbbuf; | |
262 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); | |
263 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); | |
264 | ||
265 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { | |
9bdcfb10 | 266 | dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); |
f9f38e33 HK |
267 | /* Free memory and continue on */ |
268 | nvme_dbbuf_dma_free(dev); | |
269 | } | |
270 | } | |
271 | ||
272 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) | |
273 | { | |
274 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
275 | } | |
276 | ||
277 | /* Update dbbuf and return true if an MMIO is required */ | |
278 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, | |
279 | volatile u32 *dbbuf_ei) | |
280 | { | |
281 | if (dbbuf_db) { | |
282 | u16 old_value; | |
283 | ||
284 | /* | |
285 | * Ensure that the queue is written before updating | |
286 | * the doorbell in memory | |
287 | */ | |
288 | wmb(); | |
289 | ||
290 | old_value = *dbbuf_db; | |
291 | *dbbuf_db = value; | |
292 | ||
293 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) | |
294 | return false; | |
295 | } | |
296 | ||
297 | return true; | |
b60503ba MW |
298 | } |
299 | ||
ac3dd5bd JA |
300 | /* |
301 | * Max size of iod being embedded in the request payload | |
302 | */ | |
303 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 304 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
305 | |
306 | /* | |
307 | * Will slightly overestimate the number of pages needed. This is OK | |
308 | * as it only leads to a small amount of wasted memory for the lifetime of | |
309 | * the I/O. | |
310 | */ | |
311 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
312 | { | |
5fd4ce1b CH |
313 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
314 | dev->ctrl.page_size); | |
ac3dd5bd JA |
315 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
316 | } | |
317 | ||
f4800d6d CH |
318 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
319 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 320 | { |
f4800d6d CH |
321 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
322 | sizeof(struct scatterlist) * nseg; | |
323 | } | |
ac3dd5bd | 324 | |
f4800d6d CH |
325 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
326 | { | |
327 | return sizeof(struct nvme_iod) + | |
328 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
329 | } |
330 | ||
a4aea562 MB |
331 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
332 | unsigned int hctx_idx) | |
e85248e5 | 333 | { |
a4aea562 MB |
334 | struct nvme_dev *dev = data; |
335 | struct nvme_queue *nvmeq = dev->queues[0]; | |
336 | ||
42483228 KB |
337 | WARN_ON(hctx_idx != 0); |
338 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
339 | WARN_ON(nvmeq->tags); | |
340 | ||
a4aea562 | 341 | hctx->driver_data = nvmeq; |
42483228 | 342 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 343 | return 0; |
e85248e5 MW |
344 | } |
345 | ||
4af0e21c KB |
346 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
347 | { | |
348 | struct nvme_queue *nvmeq = hctx->driver_data; | |
349 | ||
350 | nvmeq->tags = NULL; | |
351 | } | |
352 | ||
d6296d39 CH |
353 | static int nvme_admin_init_request(struct blk_mq_tag_set *set, |
354 | struct request *req, unsigned int hctx_idx, | |
355 | unsigned int numa_node) | |
22404274 | 356 | { |
d6296d39 | 357 | struct nvme_dev *dev = set->driver_data; |
f4800d6d | 358 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
359 | struct nvme_queue *nvmeq = dev->queues[0]; |
360 | ||
361 | BUG_ON(!nvmeq); | |
f4800d6d | 362 | iod->nvmeq = nvmeq; |
a4aea562 | 363 | return 0; |
22404274 KB |
364 | } |
365 | ||
a4aea562 MB |
366 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
367 | unsigned int hctx_idx) | |
b60503ba | 368 | { |
a4aea562 | 369 | struct nvme_dev *dev = data; |
42483228 | 370 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 371 | |
42483228 KB |
372 | if (!nvmeq->tags) |
373 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 374 | |
42483228 | 375 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
376 | hctx->driver_data = nvmeq; |
377 | return 0; | |
b60503ba MW |
378 | } |
379 | ||
d6296d39 CH |
380 | static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, |
381 | unsigned int hctx_idx, unsigned int numa_node) | |
b60503ba | 382 | { |
d6296d39 | 383 | struct nvme_dev *dev = set->driver_data; |
f4800d6d | 384 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
385 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
386 | ||
387 | BUG_ON(!nvmeq); | |
f4800d6d | 388 | iod->nvmeq = nvmeq; |
a4aea562 MB |
389 | return 0; |
390 | } | |
391 | ||
dca51e78 CH |
392 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
393 | { | |
394 | struct nvme_dev *dev = set->driver_data; | |
395 | ||
396 | return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); | |
397 | } | |
398 | ||
b60503ba | 399 | /** |
adf68f21 | 400 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
401 | * @nvmeq: The queue to use |
402 | * @cmd: The command to send | |
403 | * | |
404 | * Safe to use from interrupt context | |
405 | */ | |
e3f879bf SB |
406 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
407 | struct nvme_command *cmd) | |
b60503ba | 408 | { |
a4aea562 MB |
409 | u16 tail = nvmeq->sq_tail; |
410 | ||
8ffaadf7 JD |
411 | if (nvmeq->sq_cmds_io) |
412 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
413 | else | |
414 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
415 | ||
b60503ba MW |
416 | if (++tail == nvmeq->q_depth) |
417 | tail = 0; | |
f9f38e33 HK |
418 | if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, |
419 | nvmeq->dbbuf_sq_ei)) | |
420 | writel(tail, nvmeq->q_db); | |
b60503ba | 421 | nvmeq->sq_tail = tail; |
b60503ba MW |
422 | } |
423 | ||
f4800d6d | 424 | static __le64 **iod_list(struct request *req) |
b60503ba | 425 | { |
f4800d6d | 426 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
f9d03f96 | 427 | return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
428 | } |
429 | ||
b131c61d | 430 | static int nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 431 | { |
f4800d6d | 432 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
f9d03f96 | 433 | int nseg = blk_rq_nr_phys_segments(rq); |
b131c61d | 434 | unsigned int size = blk_rq_payload_bytes(rq); |
ac3dd5bd | 435 | |
f4800d6d CH |
436 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
437 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
438 | if (!iod->sg) | |
439 | return BLK_MQ_RQ_QUEUE_BUSY; | |
440 | } else { | |
441 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
442 | } |
443 | ||
f4800d6d CH |
444 | iod->aborted = 0; |
445 | iod->npages = -1; | |
446 | iod->nents = 0; | |
447 | iod->length = size; | |
f80ec966 | 448 | |
bac0000a | 449 | return BLK_MQ_RQ_QUEUE_OK; |
ac3dd5bd JA |
450 | } |
451 | ||
f4800d6d | 452 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 453 | { |
f4800d6d | 454 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 455 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 456 | int i; |
f4800d6d | 457 | __le64 **list = iod_list(req); |
eca18b23 MW |
458 | dma_addr_t prp_dma = iod->first_dma; |
459 | ||
460 | if (iod->npages == 0) | |
461 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
462 | for (i = 0; i < iod->npages; i++) { | |
463 | __le64 *prp_list = list[i]; | |
464 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
465 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
466 | prp_dma = next_prp_dma; | |
467 | } | |
ac3dd5bd | 468 | |
f4800d6d CH |
469 | if (iod->sg != iod->inline_sg) |
470 | kfree(iod->sg); | |
b4ff9c8d KB |
471 | } |
472 | ||
52b68d7e | 473 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
474 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
475 | { | |
476 | if (be32_to_cpu(pi->ref_tag) == v) | |
477 | pi->ref_tag = cpu_to_be32(p); | |
478 | } | |
479 | ||
480 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
481 | { | |
482 | if (be32_to_cpu(pi->ref_tag) == p) | |
483 | pi->ref_tag = cpu_to_be32(v); | |
484 | } | |
485 | ||
486 | /** | |
487 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
488 | * | |
489 | * The virtual start sector is the one that was originally submitted by the | |
490 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
491 | * start sector may be different. Remap protection information to match the | |
492 | * physical LBA on writes, and back to the original seed on reads. | |
493 | * | |
494 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
495 | */ | |
496 | static void nvme_dif_remap(struct request *req, | |
497 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
498 | { | |
499 | struct nvme_ns *ns = req->rq_disk->private_data; | |
500 | struct bio_integrity_payload *bip; | |
501 | struct t10_pi_tuple *pi; | |
502 | void *p, *pmap; | |
503 | u32 i, nlb, ts, phys, virt; | |
504 | ||
505 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
506 | return; | |
507 | ||
508 | bip = bio_integrity(req->bio); | |
509 | if (!bip) | |
510 | return; | |
511 | ||
512 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
513 | |
514 | p = pmap; | |
515 | virt = bip_get_seed(bip); | |
516 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
517 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 518 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
519 | |
520 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
521 | pi = (struct t10_pi_tuple *)p; | |
522 | dif_swap(phys, virt, pi); | |
523 | p += ts; | |
524 | } | |
525 | kunmap_atomic(pmap); | |
526 | } | |
52b68d7e KB |
527 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
528 | static void nvme_dif_remap(struct request *req, | |
529 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
530 | { | |
531 | } | |
532 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
533 | { | |
534 | } | |
535 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
536 | { | |
537 | } | |
52b68d7e KB |
538 | #endif |
539 | ||
b131c61d | 540 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req) |
ff22b54f | 541 | { |
f4800d6d | 542 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 543 | struct dma_pool *pool; |
b131c61d | 544 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 545 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
546 | int dma_len = sg_dma_len(sg); |
547 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 548 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 549 | int offset = dma_addr & (page_size - 1); |
e025344c | 550 | __le64 *prp_list; |
f4800d6d | 551 | __le64 **list = iod_list(req); |
e025344c | 552 | dma_addr_t prp_dma; |
eca18b23 | 553 | int nprps, i; |
ff22b54f | 554 | |
1d090624 | 555 | length -= (page_size - offset); |
ff22b54f | 556 | if (length <= 0) |
69d2b571 | 557 | return true; |
ff22b54f | 558 | |
1d090624 | 559 | dma_len -= (page_size - offset); |
ff22b54f | 560 | if (dma_len) { |
1d090624 | 561 | dma_addr += (page_size - offset); |
ff22b54f MW |
562 | } else { |
563 | sg = sg_next(sg); | |
564 | dma_addr = sg_dma_address(sg); | |
565 | dma_len = sg_dma_len(sg); | |
566 | } | |
567 | ||
1d090624 | 568 | if (length <= page_size) { |
edd10d33 | 569 | iod->first_dma = dma_addr; |
69d2b571 | 570 | return true; |
e025344c SMM |
571 | } |
572 | ||
1d090624 | 573 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
574 | if (nprps <= (256 / 8)) { |
575 | pool = dev->prp_small_pool; | |
eca18b23 | 576 | iod->npages = 0; |
99802a7a MW |
577 | } else { |
578 | pool = dev->prp_page_pool; | |
eca18b23 | 579 | iod->npages = 1; |
99802a7a MW |
580 | } |
581 | ||
69d2b571 | 582 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 583 | if (!prp_list) { |
edd10d33 | 584 | iod->first_dma = dma_addr; |
eca18b23 | 585 | iod->npages = -1; |
69d2b571 | 586 | return false; |
b77954cb | 587 | } |
eca18b23 MW |
588 | list[0] = prp_list; |
589 | iod->first_dma = prp_dma; | |
e025344c SMM |
590 | i = 0; |
591 | for (;;) { | |
1d090624 | 592 | if (i == page_size >> 3) { |
e025344c | 593 | __le64 *old_prp_list = prp_list; |
69d2b571 | 594 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 595 | if (!prp_list) |
69d2b571 | 596 | return false; |
eca18b23 | 597 | list[iod->npages++] = prp_list; |
7523d834 MW |
598 | prp_list[0] = old_prp_list[i - 1]; |
599 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
600 | i = 1; | |
e025344c SMM |
601 | } |
602 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
603 | dma_len -= page_size; |
604 | dma_addr += page_size; | |
605 | length -= page_size; | |
e025344c SMM |
606 | if (length <= 0) |
607 | break; | |
608 | if (dma_len > 0) | |
609 | continue; | |
610 | BUG_ON(dma_len < 0); | |
611 | sg = sg_next(sg); | |
612 | dma_addr = sg_dma_address(sg); | |
613 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
614 | } |
615 | ||
69d2b571 | 616 | return true; |
ff22b54f MW |
617 | } |
618 | ||
f4800d6d | 619 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 620 | struct nvme_command *cmnd) |
d29ec824 | 621 | { |
f4800d6d | 622 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
623 | struct request_queue *q = req->q; |
624 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
625 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
626 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
d29ec824 | 627 | |
f9d03f96 | 628 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
ba1ca37e CH |
629 | iod->nents = blk_rq_map_sg(q, req, iod->sg); |
630 | if (!iod->nents) | |
631 | goto out; | |
d29ec824 | 632 | |
ba1ca37e | 633 | ret = BLK_MQ_RQ_QUEUE_BUSY; |
2b6b535d MFO |
634 | if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, |
635 | DMA_ATTR_NO_WARN)) | |
ba1ca37e | 636 | goto out; |
d29ec824 | 637 | |
b131c61d | 638 | if (!nvme_setup_prps(dev, req)) |
ba1ca37e | 639 | goto out_unmap; |
0e5e4f0e | 640 | |
ba1ca37e CH |
641 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
642 | if (blk_integrity_rq(req)) { | |
643 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
644 | goto out_unmap; | |
0e5e4f0e | 645 | |
bf684057 CH |
646 | sg_init_table(&iod->meta_sg, 1); |
647 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 648 | goto out_unmap; |
0e5e4f0e | 649 | |
ba1ca37e CH |
650 | if (rq_data_dir(req)) |
651 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 652 | |
bf684057 | 653 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 654 | goto out_unmap; |
d29ec824 | 655 | } |
00df5cb4 | 656 | |
eb793e2c CH |
657 | cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
658 | cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); | |
ba1ca37e | 659 | if (blk_integrity_rq(req)) |
bf684057 | 660 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e | 661 | return BLK_MQ_RQ_QUEUE_OK; |
00df5cb4 | 662 | |
ba1ca37e CH |
663 | out_unmap: |
664 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
665 | out: | |
666 | return ret; | |
00df5cb4 MW |
667 | } |
668 | ||
f4800d6d | 669 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 670 | { |
f4800d6d | 671 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
672 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
673 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
674 | ||
675 | if (iod->nents) { | |
676 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
677 | if (blk_integrity_rq(req)) { | |
678 | if (!rq_data_dir(req)) | |
679 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 680 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 681 | } |
e19b127f | 682 | } |
e1e5e564 | 683 | |
f9d03f96 | 684 | nvme_cleanup_cmd(req); |
f4800d6d | 685 | nvme_free_iod(dev, req); |
d4f6c3ab | 686 | } |
b60503ba | 687 | |
d29ec824 CH |
688 | /* |
689 | * NOTE: ns is NULL when called on the admin queue. | |
690 | */ | |
a4aea562 MB |
691 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
692 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 693 | { |
a4aea562 MB |
694 | struct nvme_ns *ns = hctx->queue->queuedata; |
695 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 696 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 697 | struct request *req = bd->rq; |
ba1ca37e CH |
698 | struct nvme_command cmnd; |
699 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 700 | |
e1e5e564 KB |
701 | /* |
702 | * If formated with metadata, require the block layer provide a buffer | |
703 | * unless this namespace is formated such that the metadata can be | |
704 | * stripped/generated by the controller with PRACT=1. | |
705 | */ | |
d29ec824 | 706 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 | 707 | if (!(ns->pi_type && ns->ms == 8) && |
57292b58 | 708 | !blk_rq_is_passthrough(req)) { |
eee417b0 | 709 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
710 | return BLK_MQ_RQ_QUEUE_OK; |
711 | } | |
712 | } | |
713 | ||
f9d03f96 | 714 | ret = nvme_setup_cmd(ns, req, &cmnd); |
bac0000a | 715 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f4800d6d | 716 | return ret; |
a4aea562 | 717 | |
b131c61d | 718 | ret = nvme_init_iod(req, dev); |
bac0000a | 719 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f9d03f96 | 720 | goto out_free_cmd; |
a4aea562 | 721 | |
f9d03f96 | 722 | if (blk_rq_nr_phys_segments(req)) |
b131c61d | 723 | ret = nvme_map_data(dev, req, &cmnd); |
a4aea562 | 724 | |
bac0000a | 725 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f9d03f96 | 726 | goto out_cleanup_iod; |
a4aea562 | 727 | |
aae239e1 | 728 | blk_mq_start_request(req); |
a4aea562 | 729 | |
ba1ca37e | 730 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 731 | if (unlikely(nvmeq->cq_vector < 0)) { |
9ef3932e | 732 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
ae1fba20 | 733 | spin_unlock_irq(&nvmeq->q_lock); |
f9d03f96 | 734 | goto out_cleanup_iod; |
ae1fba20 | 735 | } |
ba1ca37e | 736 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
737 | nvme_process_cq(nvmeq); |
738 | spin_unlock_irq(&nvmeq->q_lock); | |
739 | return BLK_MQ_RQ_QUEUE_OK; | |
f9d03f96 | 740 | out_cleanup_iod: |
f4800d6d | 741 | nvme_free_iod(dev, req); |
f9d03f96 CH |
742 | out_free_cmd: |
743 | nvme_cleanup_cmd(req); | |
ba1ca37e | 744 | return ret; |
b60503ba | 745 | } |
e1e5e564 | 746 | |
77f02a7a | 747 | static void nvme_pci_complete_rq(struct request *req) |
eee417b0 | 748 | { |
f4800d6d | 749 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 | 750 | |
77f02a7a CH |
751 | nvme_unmap_data(iod->nvmeq->dev, req); |
752 | nvme_complete_rq(req); | |
b60503ba MW |
753 | } |
754 | ||
d783e0bd MR |
755 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
756 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
757 | u16 phase) | |
758 | { | |
759 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
760 | } | |
761 | ||
a0fa9647 | 762 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 763 | { |
82123460 | 764 | u16 head, phase; |
b60503ba | 765 | |
b60503ba | 766 | head = nvmeq->cq_head; |
82123460 | 767 | phase = nvmeq->cq_phase; |
b60503ba | 768 | |
d783e0bd | 769 | while (nvme_cqe_valid(nvmeq, head, phase)) { |
b60503ba | 770 | struct nvme_completion cqe = nvmeq->cqes[head]; |
eee417b0 | 771 | struct request *req; |
adf68f21 | 772 | |
b60503ba MW |
773 | if (++head == nvmeq->q_depth) { |
774 | head = 0; | |
82123460 | 775 | phase = !phase; |
b60503ba | 776 | } |
adf68f21 | 777 | |
a0fa9647 JA |
778 | if (tag && *tag == cqe.command_id) |
779 | *tag = -1; | |
adf68f21 | 780 | |
aae239e1 | 781 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 782 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
783 | "invalid id %d completed on queue %d\n", |
784 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
785 | continue; | |
786 | } | |
787 | ||
adf68f21 CH |
788 | /* |
789 | * AEN requests are special as they don't time out and can | |
790 | * survive any kind of queue freeze and often don't respond to | |
791 | * aborts. We don't even bother to allocate a struct request | |
792 | * for them but rather special case them here. | |
793 | */ | |
794 | if (unlikely(nvmeq->qid == 0 && | |
795 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
7bf58533 CH |
796 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
797 | cqe.status, &cqe.result); | |
adf68f21 CH |
798 | continue; |
799 | } | |
800 | ||
eee417b0 | 801 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
27fa9bc5 | 802 | nvme_end_request(req, cqe.status, cqe.result); |
b60503ba MW |
803 | } |
804 | ||
82123460 | 805 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 806 | return; |
b60503ba | 807 | |
604e8c8d | 808 | if (likely(nvmeq->cq_vector >= 0)) |
f9f38e33 HK |
809 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, |
810 | nvmeq->dbbuf_cq_ei)) | |
811 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 812 | nvmeq->cq_head = head; |
82123460 | 813 | nvmeq->cq_phase = phase; |
b60503ba | 814 | |
e9539f47 | 815 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
816 | } |
817 | ||
818 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
819 | { | |
820 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
821 | } |
822 | ||
823 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
824 | { |
825 | irqreturn_t result; | |
826 | struct nvme_queue *nvmeq = data; | |
827 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
828 | nvme_process_cq(nvmeq); |
829 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
830 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
831 | spin_unlock(&nvmeq->q_lock); |
832 | return result; | |
833 | } | |
834 | ||
835 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
836 | { | |
837 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
838 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
839 | return IRQ_WAKE_THREAD; | |
840 | return IRQ_NONE; | |
58ffacb5 MW |
841 | } |
842 | ||
7776db1c | 843 | static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) |
a0fa9647 | 844 | { |
d783e0bd | 845 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
a0fa9647 JA |
846 | spin_lock_irq(&nvmeq->q_lock); |
847 | __nvme_process_cq(nvmeq, &tag); | |
848 | spin_unlock_irq(&nvmeq->q_lock); | |
849 | ||
850 | if (tag == -1) | |
851 | return 1; | |
852 | } | |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
7776db1c KB |
857 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
858 | { | |
859 | struct nvme_queue *nvmeq = hctx->driver_data; | |
860 | ||
861 | return __nvme_poll(nvmeq, tag); | |
862 | } | |
863 | ||
f866fc42 | 864 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) |
b60503ba | 865 | { |
f866fc42 | 866 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 867 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 868 | struct nvme_command c; |
b60503ba | 869 | |
a4aea562 MB |
870 | memset(&c, 0, sizeof(c)); |
871 | c.common.opcode = nvme_admin_async_event; | |
f866fc42 | 872 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; |
3c0cf138 | 873 | |
9396dec9 | 874 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 875 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 876 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
877 | } |
878 | ||
b60503ba | 879 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 880 | { |
b60503ba MW |
881 | struct nvme_command c; |
882 | ||
883 | memset(&c, 0, sizeof(c)); | |
884 | c.delete_queue.opcode = opcode; | |
885 | c.delete_queue.qid = cpu_to_le16(id); | |
886 | ||
1c63dc66 | 887 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
888 | } |
889 | ||
b60503ba MW |
890 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
891 | struct nvme_queue *nvmeq) | |
892 | { | |
b60503ba MW |
893 | struct nvme_command c; |
894 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
895 | ||
d29ec824 CH |
896 | /* |
897 | * Note: we (ab)use the fact the the prp fields survive if no data | |
898 | * is attached to the request. | |
899 | */ | |
b60503ba MW |
900 | memset(&c, 0, sizeof(c)); |
901 | c.create_cq.opcode = nvme_admin_create_cq; | |
902 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
903 | c.create_cq.cqid = cpu_to_le16(qid); | |
904 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
905 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
906 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
907 | ||
1c63dc66 | 908 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
909 | } |
910 | ||
911 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
912 | struct nvme_queue *nvmeq) | |
913 | { | |
b60503ba | 914 | struct nvme_command c; |
81c1cd98 | 915 | int flags = NVME_QUEUE_PHYS_CONTIG; |
b60503ba | 916 | |
d29ec824 CH |
917 | /* |
918 | * Note: we (ab)use the fact the the prp fields survive if no data | |
919 | * is attached to the request. | |
920 | */ | |
b60503ba MW |
921 | memset(&c, 0, sizeof(c)); |
922 | c.create_sq.opcode = nvme_admin_create_sq; | |
923 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
924 | c.create_sq.sqid = cpu_to_le16(qid); | |
925 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
926 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
927 | c.create_sq.cqid = cpu_to_le16(qid); | |
928 | ||
1c63dc66 | 929 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
930 | } |
931 | ||
932 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
933 | { | |
934 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
935 | } | |
936 | ||
937 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
938 | { | |
939 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
940 | } | |
941 | ||
e7a2a87d | 942 | static void abort_endio(struct request *req, int error) |
bc5fc7e4 | 943 | { |
f4800d6d CH |
944 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
945 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e44ac588 | 946 | |
27fa9bc5 CH |
947 | dev_warn(nvmeq->dev->ctrl.device, |
948 | "Abort status: 0x%x", nvme_req(req)->status); | |
e7a2a87d | 949 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 950 | blk_mq_free_request(req); |
bc5fc7e4 MW |
951 | } |
952 | ||
31c7c7d2 | 953 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 954 | { |
f4800d6d CH |
955 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
956 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 957 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 958 | struct request *abort_req; |
a4aea562 | 959 | struct nvme_command cmd; |
c30341dc | 960 | |
7776db1c KB |
961 | /* |
962 | * Did we miss an interrupt? | |
963 | */ | |
964 | if (__nvme_poll(nvmeq, req->tag)) { | |
965 | dev_warn(dev->ctrl.device, | |
966 | "I/O %d QID %d timeout, completion polled\n", | |
967 | req->tag, nvmeq->qid); | |
968 | return BLK_EH_HANDLED; | |
969 | } | |
970 | ||
31c7c7d2 | 971 | /* |
fd634f41 CH |
972 | * Shutdown immediately if controller times out while starting. The |
973 | * reset work will see the pci device disabled when it gets the forced | |
974 | * cancellation error. All outstanding requests are completed on | |
975 | * shutdown, so we return BLK_EH_HANDLED. | |
976 | */ | |
bb8d261e | 977 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 978 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
979 | "I/O %d QID %d timeout, disable controller\n", |
980 | req->tag, nvmeq->qid); | |
a5cdb68c | 981 | nvme_dev_disable(dev, false); |
27fa9bc5 | 982 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
fd634f41 | 983 | return BLK_EH_HANDLED; |
c30341dc KB |
984 | } |
985 | ||
fd634f41 CH |
986 | /* |
987 | * Shutdown the controller immediately and schedule a reset if the | |
988 | * command was already aborted once before and still hasn't been | |
989 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 990 | */ |
f4800d6d | 991 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 992 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
993 | "I/O %d QID %d timeout, reset controller\n", |
994 | req->tag, nvmeq->qid); | |
a5cdb68c | 995 | nvme_dev_disable(dev, false); |
c5f6ce97 | 996 | nvme_reset(dev); |
c30341dc | 997 | |
e1569a16 KB |
998 | /* |
999 | * Mark the request as handled, since the inline shutdown | |
1000 | * forces all outstanding requests to complete. | |
1001 | */ | |
27fa9bc5 | 1002 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
e1569a16 | 1003 | return BLK_EH_HANDLED; |
c30341dc | 1004 | } |
c30341dc | 1005 | |
e7a2a87d | 1006 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 1007 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 1008 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1009 | } |
7bf7d778 | 1010 | iod->aborted = 1; |
a4aea562 | 1011 | |
c30341dc KB |
1012 | memset(&cmd, 0, sizeof(cmd)); |
1013 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1014 | cmd.abort.cid = req->tag; |
c30341dc | 1015 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1016 | |
1b3c47c1 SG |
1017 | dev_warn(nvmeq->dev->ctrl.device, |
1018 | "I/O %d QID %d timeout, aborting\n", | |
1019 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
1020 | |
1021 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 1022 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
1023 | if (IS_ERR(abort_req)) { |
1024 | atomic_inc(&dev->ctrl.abort_limit); | |
1025 | return BLK_EH_RESET_TIMER; | |
1026 | } | |
1027 | ||
1028 | abort_req->timeout = ADMIN_TIMEOUT; | |
1029 | abort_req->end_io_data = NULL; | |
1030 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 1031 | |
31c7c7d2 CH |
1032 | /* |
1033 | * The aborted req will be completed on receiving the abort req. | |
1034 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1035 | * as the device then is in a faulty state. | |
1036 | */ | |
1037 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1038 | } |
1039 | ||
a4aea562 MB |
1040 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1041 | { | |
9e866774 MW |
1042 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1043 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1044 | if (nvmeq->sq_cmds) |
1045 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1046 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1047 | kfree(nvmeq); | |
1048 | } | |
1049 | ||
a1a5ef99 | 1050 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1051 | { |
1052 | int i; | |
1053 | ||
a1a5ef99 | 1054 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1055 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1056 | dev->queue_count--; |
a4aea562 | 1057 | dev->queues[i] = NULL; |
f435c282 | 1058 | nvme_free_queue(nvmeq); |
121c7ad4 | 1059 | } |
22404274 KB |
1060 | } |
1061 | ||
4d115420 KB |
1062 | /** |
1063 | * nvme_suspend_queue - put queue into suspended state | |
1064 | * @nvmeq - queue to suspend | |
4d115420 KB |
1065 | */ |
1066 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1067 | { |
2b25d981 | 1068 | int vector; |
b60503ba | 1069 | |
a09115b2 | 1070 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1071 | if (nvmeq->cq_vector == -1) { |
1072 | spin_unlock_irq(&nvmeq->q_lock); | |
1073 | return 1; | |
1074 | } | |
0ff199cb | 1075 | vector = nvmeq->cq_vector; |
42f61420 | 1076 | nvmeq->dev->online_queues--; |
2b25d981 | 1077 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1078 | spin_unlock_irq(&nvmeq->q_lock); |
1079 | ||
1c63dc66 | 1080 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 1081 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1082 | |
0ff199cb | 1083 | pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); |
b60503ba | 1084 | |
4d115420 KB |
1085 | return 0; |
1086 | } | |
b60503ba | 1087 | |
a5cdb68c | 1088 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1089 | { |
a5cdb68c | 1090 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
1091 | |
1092 | if (!nvmeq) | |
1093 | return; | |
1094 | if (nvme_suspend_queue(nvmeq)) | |
1095 | return; | |
1096 | ||
a5cdb68c KB |
1097 | if (shutdown) |
1098 | nvme_shutdown_ctrl(&dev->ctrl); | |
1099 | else | |
1100 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
1101 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
1102 | |
1103 | spin_lock_irq(&nvmeq->q_lock); | |
1104 | nvme_process_cq(nvmeq); | |
1105 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1106 | } |
1107 | ||
8ffaadf7 JD |
1108 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1109 | int entry_size) | |
1110 | { | |
1111 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1112 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1113 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1114 | |
1115 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1116 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1117 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1118 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1119 | |
1120 | /* | |
1121 | * Ensure the reduced q_depth is above some threshold where it | |
1122 | * would be better to map queues in system memory with the | |
1123 | * original depth | |
1124 | */ | |
1125 | if (q_depth < 64) | |
1126 | return -ENOMEM; | |
1127 | } | |
1128 | ||
1129 | return q_depth; | |
1130 | } | |
1131 | ||
1132 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1133 | int qid, int depth) | |
1134 | { | |
1135 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1136 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1137 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1138 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1139 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1140 | } else { | |
1141 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1142 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1143 | if (!nvmeq->sq_cmds) | |
1144 | return -ENOMEM; | |
1145 | } | |
1146 | ||
1147 | return 0; | |
1148 | } | |
1149 | ||
b60503ba | 1150 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
d3af3ecd | 1151 | int depth, int node) |
b60503ba | 1152 | { |
d3af3ecd SL |
1153 | struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, |
1154 | node); | |
b60503ba MW |
1155 | if (!nvmeq) |
1156 | return NULL; | |
1157 | ||
e75ec752 | 1158 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1159 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1160 | if (!nvmeq->cqes) |
1161 | goto free_nvmeq; | |
b60503ba | 1162 | |
8ffaadf7 | 1163 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1164 | goto free_cqdma; |
1165 | ||
e75ec752 | 1166 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1167 | nvmeq->dev = dev; |
b60503ba MW |
1168 | spin_lock_init(&nvmeq->q_lock); |
1169 | nvmeq->cq_head = 0; | |
82123460 | 1170 | nvmeq->cq_phase = 1; |
b80d5ccc | 1171 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1172 | nvmeq->q_depth = depth; |
c30341dc | 1173 | nvmeq->qid = qid; |
758dd7fd | 1174 | nvmeq->cq_vector = -1; |
a4aea562 | 1175 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1176 | dev->queue_count++; |
1177 | ||
b60503ba MW |
1178 | return nvmeq; |
1179 | ||
1180 | free_cqdma: | |
e75ec752 | 1181 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1182 | nvmeq->cq_dma_addr); |
1183 | free_nvmeq: | |
1184 | kfree(nvmeq); | |
1185 | return NULL; | |
1186 | } | |
1187 | ||
dca51e78 | 1188 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1189 | { |
0ff199cb CH |
1190 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
1191 | int nr = nvmeq->dev->ctrl.instance; | |
1192 | ||
1193 | if (use_threaded_interrupts) { | |
1194 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, | |
1195 | nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1196 | } else { | |
1197 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, | |
1198 | NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1199 | } | |
3001082c MW |
1200 | } |
1201 | ||
22404274 | 1202 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1203 | { |
22404274 | 1204 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1205 | |
7be50e93 | 1206 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1207 | nvmeq->sq_tail = 0; |
1208 | nvmeq->cq_head = 0; | |
1209 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1210 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1211 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
f9f38e33 | 1212 | nvme_dbbuf_init(dev, nvmeq, qid); |
42f61420 | 1213 | dev->online_queues++; |
7be50e93 | 1214 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1215 | } |
1216 | ||
1217 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1218 | { | |
1219 | struct nvme_dev *dev = nvmeq->dev; | |
1220 | int result; | |
3f85d50b | 1221 | |
2b25d981 | 1222 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1223 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1224 | if (result < 0) | |
22404274 | 1225 | return result; |
b60503ba MW |
1226 | |
1227 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1228 | if (result < 0) | |
1229 | goto release_cq; | |
1230 | ||
dca51e78 | 1231 | result = queue_request_irq(nvmeq); |
b60503ba MW |
1232 | if (result < 0) |
1233 | goto release_sq; | |
1234 | ||
22404274 | 1235 | nvme_init_queue(nvmeq, qid); |
22404274 | 1236 | return result; |
b60503ba MW |
1237 | |
1238 | release_sq: | |
1239 | adapter_delete_sq(dev, qid); | |
1240 | release_cq: | |
1241 | adapter_delete_cq(dev, qid); | |
22404274 | 1242 | return result; |
b60503ba MW |
1243 | } |
1244 | ||
f363b089 | 1245 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1246 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1247 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1248 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1249 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1250 | .init_request = nvme_admin_init_request, |
1251 | .timeout = nvme_timeout, | |
1252 | }; | |
1253 | ||
f363b089 | 1254 | static const struct blk_mq_ops nvme_mq_ops = { |
a4aea562 | 1255 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1256 | .complete = nvme_pci_complete_rq, |
a4aea562 MB |
1257 | .init_hctx = nvme_init_hctx, |
1258 | .init_request = nvme_init_request, | |
dca51e78 | 1259 | .map_queues = nvme_pci_map_queues, |
a4aea562 | 1260 | .timeout = nvme_timeout, |
a0fa9647 | 1261 | .poll = nvme_poll, |
a4aea562 MB |
1262 | }; |
1263 | ||
ea191d2f KB |
1264 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1265 | { | |
1c63dc66 | 1266 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1267 | /* |
1268 | * If the controller was reset during removal, it's possible | |
1269 | * user requests may be waiting on a stopped queue. Start the | |
1270 | * queue to flush these to completion. | |
1271 | */ | |
1272 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); | |
1c63dc66 | 1273 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1274 | blk_mq_free_tag_set(&dev->admin_tagset); |
1275 | } | |
1276 | } | |
1277 | ||
a4aea562 MB |
1278 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1279 | { | |
1c63dc66 | 1280 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1281 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1282 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1283 | |
1284 | /* | |
1285 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1286 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1287 | */ | |
1288 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1289 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1290 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1291 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
d3484991 | 1292 | dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; |
a4aea562 MB |
1293 | dev->admin_tagset.driver_data = dev; |
1294 | ||
1295 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1296 | return -ENOMEM; | |
1297 | ||
1c63dc66 CH |
1298 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1299 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1300 | blk_mq_free_tag_set(&dev->admin_tagset); |
1301 | return -ENOMEM; | |
1302 | } | |
1c63dc66 | 1303 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1304 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1305 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1306 | return -ENODEV; |
1307 | } | |
0fb59cbc | 1308 | } else |
25646264 | 1309 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1310 | |
1311 | return 0; | |
1312 | } | |
1313 | ||
8d85fce7 | 1314 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1315 | { |
ba47e386 | 1316 | int result; |
b60503ba | 1317 | u32 aqa; |
7a67cbea | 1318 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1319 | struct nvme_queue *nvmeq; |
1320 | ||
8ef2074d | 1321 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
dfbac8c7 KB |
1322 | NVME_CAP_NSSRC(cap) : 0; |
1323 | ||
7a67cbea CH |
1324 | if (dev->subsystem && |
1325 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1326 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1327 | |
5fd4ce1b | 1328 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1329 | if (result < 0) |
1330 | return result; | |
b60503ba | 1331 | |
a4aea562 | 1332 | nvmeq = dev->queues[0]; |
cd638946 | 1333 | if (!nvmeq) { |
d3af3ecd SL |
1334 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, |
1335 | dev_to_node(dev->dev)); | |
cd638946 KB |
1336 | if (!nvmeq) |
1337 | return -ENOMEM; | |
cd638946 | 1338 | } |
b60503ba MW |
1339 | |
1340 | aqa = nvmeq->q_depth - 1; | |
1341 | aqa |= aqa << 16; | |
1342 | ||
7a67cbea CH |
1343 | writel(aqa, dev->bar + NVME_REG_AQA); |
1344 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1345 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1346 | |
5fd4ce1b | 1347 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1348 | if (result) |
d4875622 | 1349 | return result; |
a4aea562 | 1350 | |
2b25d981 | 1351 | nvmeq->cq_vector = 0; |
dca51e78 | 1352 | result = queue_request_irq(nvmeq); |
758dd7fd JD |
1353 | if (result) { |
1354 | nvmeq->cq_vector = -1; | |
d4875622 | 1355 | return result; |
758dd7fd | 1356 | } |
025c557a | 1357 | |
b60503ba MW |
1358 | return result; |
1359 | } | |
1360 | ||
c875a709 GP |
1361 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1362 | { | |
1363 | ||
1364 | /* If true, indicates loss of adapter communication, possibly by a | |
1365 | * NVMe Subsystem reset. | |
1366 | */ | |
1367 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1368 | ||
1369 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
82b057ca | 1370 | if (dev->ctrl.state == NVME_CTRL_RESETTING) |
c875a709 GP |
1371 | return false; |
1372 | ||
1373 | /* We shouldn't reset unless the controller is on fatal error state | |
1374 | * _or_ if we lost the communication with it. | |
1375 | */ | |
1376 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1377 | return false; | |
1378 | ||
1379 | /* If PCI error recovery process is happening, we cannot reset or | |
1380 | * the recovery mechanism will surely fail. | |
1381 | */ | |
1382 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1383 | return false; | |
1384 | ||
1385 | return true; | |
1386 | } | |
1387 | ||
d2a61918 AL |
1388 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) |
1389 | { | |
1390 | /* Read a config register to help see what died. */ | |
1391 | u16 pci_status; | |
1392 | int result; | |
1393 | ||
1394 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1395 | &pci_status); | |
1396 | if (result == PCIBIOS_SUCCESSFUL) | |
9bdcfb10 | 1397 | dev_warn(dev->ctrl.device, |
d2a61918 AL |
1398 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", |
1399 | csts, pci_status); | |
1400 | else | |
9bdcfb10 | 1401 | dev_warn(dev->ctrl.device, |
d2a61918 AL |
1402 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", |
1403 | csts, result); | |
1404 | } | |
1405 | ||
2d55cd5f | 1406 | static void nvme_watchdog_timer(unsigned long data) |
1fa6aead | 1407 | { |
2d55cd5f CH |
1408 | struct nvme_dev *dev = (struct nvme_dev *)data; |
1409 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1fa6aead | 1410 | |
c875a709 GP |
1411 | /* Skip controllers under certain specific conditions. */ |
1412 | if (nvme_should_reset(dev, csts)) { | |
c5f6ce97 | 1413 | if (!nvme_reset(dev)) |
d2a61918 | 1414 | nvme_warn_reset(dev, csts); |
2d55cd5f | 1415 | return; |
1fa6aead | 1416 | } |
2d55cd5f CH |
1417 | |
1418 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); | |
1fa6aead MW |
1419 | } |
1420 | ||
749941f2 | 1421 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1422 | { |
949928c1 | 1423 | unsigned i, max; |
749941f2 | 1424 | int ret = 0; |
42f61420 | 1425 | |
749941f2 | 1426 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
d3af3ecd SL |
1427 | /* vector == qid - 1, match nvme_create_queue */ |
1428 | if (!nvme_alloc_queue(dev, i, dev->q_depth, | |
1429 | pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { | |
749941f2 | 1430 | ret = -ENOMEM; |
42f61420 | 1431 | break; |
749941f2 CH |
1432 | } |
1433 | } | |
42f61420 | 1434 | |
949928c1 KB |
1435 | max = min(dev->max_qid, dev->queue_count - 1); |
1436 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 | 1437 | ret = nvme_create_queue(dev->queues[i], i); |
d4875622 | 1438 | if (ret) |
42f61420 | 1439 | break; |
27e8166c | 1440 | } |
749941f2 CH |
1441 | |
1442 | /* | |
1443 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1444 | * than the desired aount of queues, and even a controller without | |
1445 | * I/O queues an still be used to issue admin commands. This might | |
1446 | * be useful to upgrade a buggy firmware for example. | |
1447 | */ | |
1448 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1449 | } |
1450 | ||
202021c1 SB |
1451 | static ssize_t nvme_cmb_show(struct device *dev, |
1452 | struct device_attribute *attr, | |
1453 | char *buf) | |
1454 | { | |
1455 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1456 | ||
c965809c | 1457 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
202021c1 SB |
1458 | ndev->cmbloc, ndev->cmbsz); |
1459 | } | |
1460 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1461 | ||
8ffaadf7 JD |
1462 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1463 | { | |
1464 | u64 szu, size, offset; | |
8ffaadf7 JD |
1465 | resource_size_t bar_size; |
1466 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1467 | void __iomem *cmb; | |
1468 | dma_addr_t dma_addr; | |
1469 | ||
7a67cbea | 1470 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1471 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1472 | return NULL; | |
202021c1 | 1473 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1474 | |
202021c1 SB |
1475 | if (!use_cmb_sqes) |
1476 | return NULL; | |
8ffaadf7 JD |
1477 | |
1478 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1479 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
202021c1 SB |
1480 | offset = szu * NVME_CMB_OFST(dev->cmbloc); |
1481 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); | |
8ffaadf7 JD |
1482 | |
1483 | if (offset > bar_size) | |
1484 | return NULL; | |
1485 | ||
1486 | /* | |
1487 | * Controllers may support a CMB size larger than their BAR, | |
1488 | * for example, due to being behind a bridge. Reduce the CMB to | |
1489 | * the reported size of the BAR | |
1490 | */ | |
1491 | if (size > bar_size - offset) | |
1492 | size = bar_size - offset; | |
1493 | ||
202021c1 | 1494 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; |
8ffaadf7 JD |
1495 | cmb = ioremap_wc(dma_addr, size); |
1496 | if (!cmb) | |
1497 | return NULL; | |
1498 | ||
1499 | dev->cmb_dma_addr = dma_addr; | |
1500 | dev->cmb_size = size; | |
1501 | return cmb; | |
1502 | } | |
1503 | ||
1504 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1505 | { | |
1506 | if (dev->cmb) { | |
1507 | iounmap(dev->cmb); | |
1508 | dev->cmb = NULL; | |
f63572df JD |
1509 | if (dev->cmbsz) { |
1510 | sysfs_remove_file_from_group(&dev->ctrl.device->kobj, | |
1511 | &dev_attr_cmb.attr, NULL); | |
1512 | dev->cmbsz = 0; | |
1513 | } | |
8ffaadf7 JD |
1514 | } |
1515 | } | |
1516 | ||
9d713c2b KB |
1517 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1518 | { | |
b80d5ccc | 1519 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1520 | } |
1521 | ||
8d85fce7 | 1522 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1523 | { |
a4aea562 | 1524 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1525 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
dca51e78 | 1526 | int result, nr_io_queues, size; |
b60503ba | 1527 | |
2800b8e7 | 1528 | nr_io_queues = num_online_cpus(); |
9a0be7ab CH |
1529 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1530 | if (result < 0) | |
1b23484b | 1531 | return result; |
9a0be7ab | 1532 | |
f5fa90dc | 1533 | if (nr_io_queues == 0) |
a5229050 | 1534 | return 0; |
b60503ba | 1535 | |
8ffaadf7 JD |
1536 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1537 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1538 | sizeof(struct nvme_command)); | |
1539 | if (result > 0) | |
1540 | dev->q_depth = result; | |
1541 | else | |
1542 | nvme_release_cmb(dev); | |
1543 | } | |
1544 | ||
9d713c2b KB |
1545 | size = db_bar_size(dev, nr_io_queues); |
1546 | if (size > 8192) { | |
f1938f6e | 1547 | iounmap(dev->bar); |
9d713c2b KB |
1548 | do { |
1549 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1550 | if (dev->bar) | |
1551 | break; | |
1552 | if (!--nr_io_queues) | |
1553 | return -ENOMEM; | |
1554 | size = db_bar_size(dev, nr_io_queues); | |
1555 | } while (1); | |
7a67cbea | 1556 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1557 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1558 | } |
1559 | ||
9d713c2b | 1560 | /* Deregister the admin queue's interrupt */ |
0ff199cb | 1561 | pci_free_irq(pdev, 0, adminq); |
9d713c2b | 1562 | |
e32efbfc JA |
1563 | /* |
1564 | * If we enable msix early due to not intx, disable it again before | |
1565 | * setting up the full range we need. | |
1566 | */ | |
dca51e78 CH |
1567 | pci_free_irq_vectors(pdev); |
1568 | nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, | |
1569 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); | |
1570 | if (nr_io_queues <= 0) | |
1571 | return -EIO; | |
1572 | dev->max_qid = nr_io_queues; | |
fa08a396 | 1573 | |
063a8096 MW |
1574 | /* |
1575 | * Should investigate if there's a performance win from allocating | |
1576 | * more queues than interrupt vectors; it might allow the submission | |
1577 | * path to scale better, even if the receive path is limited by the | |
1578 | * number of interrupts. | |
1579 | */ | |
063a8096 | 1580 | |
dca51e78 | 1581 | result = queue_request_irq(adminq); |
758dd7fd JD |
1582 | if (result) { |
1583 | adminq->cq_vector = -1; | |
d4875622 | 1584 | return result; |
758dd7fd | 1585 | } |
749941f2 | 1586 | return nvme_create_io_queues(dev); |
b60503ba MW |
1587 | } |
1588 | ||
db3cbfff | 1589 | static void nvme_del_queue_end(struct request *req, int error) |
a5768aa8 | 1590 | { |
db3cbfff | 1591 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1592 | |
db3cbfff KB |
1593 | blk_mq_free_request(req); |
1594 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1595 | } |
1596 | ||
db3cbfff | 1597 | static void nvme_del_cq_end(struct request *req, int error) |
a5768aa8 | 1598 | { |
db3cbfff | 1599 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1600 | |
db3cbfff KB |
1601 | if (!error) { |
1602 | unsigned long flags; | |
1603 | ||
2e39e0f6 ML |
1604 | /* |
1605 | * We might be called with the AQ q_lock held | |
1606 | * and the I/O queue q_lock should always | |
1607 | * nest inside the AQ one. | |
1608 | */ | |
1609 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1610 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1611 | nvme_process_cq(nvmeq); |
1612 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1613 | } |
db3cbfff KB |
1614 | |
1615 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1616 | } |
1617 | ||
db3cbfff | 1618 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1619 | { |
db3cbfff KB |
1620 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1621 | struct request *req; | |
1622 | struct nvme_command cmd; | |
bda4e0fb | 1623 | |
db3cbfff KB |
1624 | memset(&cmd, 0, sizeof(cmd)); |
1625 | cmd.delete_queue.opcode = opcode; | |
1626 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1627 | |
eb71f435 | 1628 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
1629 | if (IS_ERR(req)) |
1630 | return PTR_ERR(req); | |
bda4e0fb | 1631 | |
db3cbfff KB |
1632 | req->timeout = ADMIN_TIMEOUT; |
1633 | req->end_io_data = nvmeq; | |
1634 | ||
1635 | blk_execute_rq_nowait(q, NULL, req, false, | |
1636 | opcode == nvme_admin_delete_cq ? | |
1637 | nvme_del_cq_end : nvme_del_queue_end); | |
1638 | return 0; | |
bda4e0fb KB |
1639 | } |
1640 | ||
70659060 | 1641 | static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) |
a5768aa8 | 1642 | { |
70659060 | 1643 | int pass; |
db3cbfff KB |
1644 | unsigned long timeout; |
1645 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1646 | |
db3cbfff | 1647 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 1648 | int sent = 0, i = queues; |
db3cbfff KB |
1649 | |
1650 | reinit_completion(&dev->ioq_wait); | |
1651 | retry: | |
1652 | timeout = ADMIN_TIMEOUT; | |
c21377f8 GKB |
1653 | for (; i > 0; i--, sent++) |
1654 | if (nvme_delete_queue(dev->queues[i], opcode)) | |
db3cbfff | 1655 | break; |
c21377f8 | 1656 | |
db3cbfff KB |
1657 | while (sent--) { |
1658 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1659 | if (timeout == 0) | |
1660 | return; | |
1661 | if (i) | |
1662 | goto retry; | |
1663 | } | |
1664 | opcode = nvme_admin_delete_cq; | |
1665 | } | |
a5768aa8 KB |
1666 | } |
1667 | ||
422ef0c7 MW |
1668 | /* |
1669 | * Return: error value if an error occurred setting up the queues or calling | |
1670 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1671 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1672 | * failures should be reported. | |
1673 | */ | |
8d85fce7 | 1674 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1675 | { |
5bae7f73 | 1676 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1677 | dev->tagset.ops = &nvme_mq_ops; |
1678 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1679 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1680 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1681 | dev->tagset.queue_depth = | |
a4aea562 | 1682 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1683 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1684 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1685 | dev->tagset.driver_data = dev; | |
b60503ba | 1686 | |
ffe7704d KB |
1687 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1688 | return 0; | |
5bae7f73 | 1689 | dev->ctrl.tagset = &dev->tagset; |
f9f38e33 HK |
1690 | |
1691 | nvme_dbbuf_set(dev); | |
949928c1 KB |
1692 | } else { |
1693 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1694 | ||
1695 | /* Free previously allocated queues that are no longer usable */ | |
1696 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1697 | } |
949928c1 | 1698 | |
e1e5e564 | 1699 | return 0; |
b60503ba MW |
1700 | } |
1701 | ||
b00a726a | 1702 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1703 | { |
42f61420 | 1704 | u64 cap; |
b00a726a | 1705 | int result = -ENOMEM; |
e75ec752 | 1706 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1707 | |
1708 | if (pci_enable_device_mem(pdev)) | |
1709 | return result; | |
1710 | ||
0877cb0d | 1711 | pci_set_master(pdev); |
0877cb0d | 1712 | |
e75ec752 CH |
1713 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1714 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1715 | goto disable; |
0877cb0d | 1716 | |
7a67cbea | 1717 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1718 | result = -ENODEV; |
b00a726a | 1719 | goto disable; |
0e53d180 | 1720 | } |
e32efbfc JA |
1721 | |
1722 | /* | |
a5229050 KB |
1723 | * Some devices and/or platforms don't advertise or work with INTx |
1724 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1725 | * adjust this later. | |
e32efbfc | 1726 | */ |
dca51e78 CH |
1727 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
1728 | if (result < 0) | |
1729 | return result; | |
e32efbfc | 1730 | |
7a67cbea CH |
1731 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1732 | ||
42f61420 KB |
1733 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1734 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1735 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1736 | |
1737 | /* | |
1738 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1739 | * some MacBook7,1 to avoid controller resets and data loss. | |
1740 | */ | |
1741 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1742 | dev->q_depth = 2; | |
9bdcfb10 CH |
1743 | dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " |
1744 | "set queue depth=%u to work around controller resets\n", | |
1f390c1f SG |
1745 | dev->q_depth); |
1746 | } | |
1747 | ||
202021c1 SB |
1748 | /* |
1749 | * CMBs can currently only exist on >=1.2 PCIe devices. We only | |
1750 | * populate sysfs if a CMB is implemented. Note that we add the | |
1751 | * CMB attribute to the nvme_ctrl kobj which removes the need to remove | |
1752 | * it on exit. Since nvme_dev_attrs_group has no name we can pass | |
1753 | * NULL as final argument to sysfs_add_file_to_group. | |
1754 | */ | |
1755 | ||
8ef2074d | 1756 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { |
8ffaadf7 | 1757 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1758 | |
202021c1 SB |
1759 | if (dev->cmbsz) { |
1760 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, | |
1761 | &dev_attr_cmb.attr, NULL)) | |
9bdcfb10 | 1762 | dev_warn(dev->ctrl.device, |
202021c1 SB |
1763 | "failed to add sysfs attribute for CMB\n"); |
1764 | } | |
1765 | } | |
1766 | ||
a0a3408e KB |
1767 | pci_enable_pcie_error_reporting(pdev); |
1768 | pci_save_state(pdev); | |
0877cb0d KB |
1769 | return 0; |
1770 | ||
1771 | disable: | |
0877cb0d KB |
1772 | pci_disable_device(pdev); |
1773 | return result; | |
1774 | } | |
1775 | ||
1776 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1777 | { |
1778 | if (dev->bar) | |
1779 | iounmap(dev->bar); | |
a1f447b3 | 1780 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
1781 | } |
1782 | ||
1783 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1784 | { |
e75ec752 CH |
1785 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1786 | ||
f63572df | 1787 | nvme_release_cmb(dev); |
dca51e78 | 1788 | pci_free_irq_vectors(pdev); |
0877cb0d | 1789 | |
a0a3408e KB |
1790 | if (pci_is_enabled(pdev)) { |
1791 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1792 | pci_disable_device(pdev); |
4d115420 | 1793 | } |
4d115420 KB |
1794 | } |
1795 | ||
a5cdb68c | 1796 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1797 | { |
70659060 | 1798 | int i, queues; |
302ad8cc KB |
1799 | bool dead = true; |
1800 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
22404274 | 1801 | |
2d55cd5f | 1802 | del_timer_sync(&dev->watchdog_timer); |
1fa6aead | 1803 | |
77bf25ea | 1804 | mutex_lock(&dev->shutdown_lock); |
302ad8cc KB |
1805 | if (pci_is_enabled(pdev)) { |
1806 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1807 | ||
1808 | if (dev->ctrl.state == NVME_CTRL_LIVE) | |
1809 | nvme_start_freeze(&dev->ctrl); | |
1810 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || | |
1811 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 1812 | } |
c21377f8 | 1813 | |
302ad8cc KB |
1814 | /* |
1815 | * Give the controller a chance to complete all entered requests if | |
1816 | * doing a safe shutdown. | |
1817 | */ | |
1818 | if (!dead && shutdown) | |
1819 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
1820 | nvme_stop_queues(&dev->ctrl); | |
1821 | ||
70659060 | 1822 | queues = dev->online_queues - 1; |
c21377f8 GKB |
1823 | for (i = dev->queue_count - 1; i > 0; i--) |
1824 | nvme_suspend_queue(dev->queues[i]); | |
1825 | ||
302ad8cc | 1826 | if (dead) { |
82469c59 GKB |
1827 | /* A device might become IO incapable very soon during |
1828 | * probe, before the admin queue is configured. Thus, | |
1829 | * queue_count can be 0 here. | |
1830 | */ | |
1831 | if (dev->queue_count) | |
1832 | nvme_suspend_queue(dev->queues[0]); | |
4d115420 | 1833 | } else { |
70659060 | 1834 | nvme_disable_io_queues(dev, queues); |
a5cdb68c | 1835 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1836 | } |
b00a726a | 1837 | nvme_pci_disable(dev); |
07836e65 | 1838 | |
e1958e65 ML |
1839 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
1840 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
302ad8cc KB |
1841 | |
1842 | /* | |
1843 | * The driver will not be starting up queues again if shutting down so | |
1844 | * must flush all entered requests to their failed completion to avoid | |
1845 | * deadlocking blk-mq hot-cpu notifier. | |
1846 | */ | |
1847 | if (shutdown) | |
1848 | nvme_start_queues(&dev->ctrl); | |
77bf25ea | 1849 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
1850 | } |
1851 | ||
091b6092 MW |
1852 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1853 | { | |
e75ec752 | 1854 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1855 | PAGE_SIZE, PAGE_SIZE, 0); |
1856 | if (!dev->prp_page_pool) | |
1857 | return -ENOMEM; | |
1858 | ||
99802a7a | 1859 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1860 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1861 | 256, 256, 0); |
1862 | if (!dev->prp_small_pool) { | |
1863 | dma_pool_destroy(dev->prp_page_pool); | |
1864 | return -ENOMEM; | |
1865 | } | |
091b6092 MW |
1866 | return 0; |
1867 | } | |
1868 | ||
1869 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1870 | { | |
1871 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1872 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1873 | } |
1874 | ||
1673f1f0 | 1875 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1876 | { |
1673f1f0 | 1877 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1878 | |
f9f38e33 | 1879 | nvme_dbbuf_dma_free(dev); |
e75ec752 | 1880 | put_device(dev->dev); |
4af0e21c KB |
1881 | if (dev->tagset.tags) |
1882 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1883 | if (dev->ctrl.admin_q) |
1884 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 1885 | kfree(dev->queues); |
e286bcfc | 1886 | free_opal_dev(dev->ctrl.opal_dev); |
5e82e952 KB |
1887 | kfree(dev); |
1888 | } | |
1889 | ||
f58944e2 KB |
1890 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
1891 | { | |
237045fc | 1892 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
1893 | |
1894 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 1895 | nvme_dev_disable(dev, false); |
f58944e2 KB |
1896 | if (!schedule_work(&dev->remove_work)) |
1897 | nvme_put_ctrl(&dev->ctrl); | |
1898 | } | |
1899 | ||
fd634f41 | 1900 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 1901 | { |
fd634f41 | 1902 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
a98e58e5 | 1903 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
f58944e2 | 1904 | int result = -ENODEV; |
5e82e952 | 1905 | |
82b057ca | 1906 | if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) |
fd634f41 | 1907 | goto out; |
5e82e952 | 1908 | |
fd634f41 CH |
1909 | /* |
1910 | * If we're called to reset a live controller first shut it down before | |
1911 | * moving on. | |
1912 | */ | |
b00a726a | 1913 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 1914 | nvme_dev_disable(dev, false); |
5e82e952 | 1915 | |
b00a726a | 1916 | result = nvme_pci_enable(dev); |
f0b50732 | 1917 | if (result) |
3cf519b5 | 1918 | goto out; |
f0b50732 KB |
1919 | |
1920 | result = nvme_configure_admin_queue(dev); | |
1921 | if (result) | |
f58944e2 | 1922 | goto out; |
f0b50732 | 1923 | |
a4aea562 | 1924 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1925 | result = nvme_alloc_admin_tags(dev); |
1926 | if (result) | |
f58944e2 | 1927 | goto out; |
b9afca3e | 1928 | |
ce4541f4 CH |
1929 | result = nvme_init_identify(&dev->ctrl); |
1930 | if (result) | |
f58944e2 | 1931 | goto out; |
ce4541f4 | 1932 | |
e286bcfc SB |
1933 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
1934 | if (!dev->ctrl.opal_dev) | |
1935 | dev->ctrl.opal_dev = | |
1936 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); | |
1937 | else if (was_suspend) | |
1938 | opal_unlock_from_suspend(dev->ctrl.opal_dev); | |
1939 | } else { | |
1940 | free_opal_dev(dev->ctrl.opal_dev); | |
1941 | dev->ctrl.opal_dev = NULL; | |
4f1244c8 | 1942 | } |
a98e58e5 | 1943 | |
f9f38e33 HK |
1944 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
1945 | result = nvme_dbbuf_dma_alloc(dev); | |
1946 | if (result) | |
1947 | dev_warn(dev->dev, | |
1948 | "unable to allocate dma for dbbuf\n"); | |
1949 | } | |
1950 | ||
f0b50732 | 1951 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1952 | if (result) |
f58944e2 | 1953 | goto out; |
f0b50732 | 1954 | |
21f033f7 KB |
1955 | /* |
1956 | * A controller that can not execute IO typically requires user | |
1957 | * intervention to correct. For such degraded controllers, the driver | |
1958 | * should not submit commands the user did not request, so skip | |
1959 | * registering for asynchronous event notification on this condition. | |
1960 | */ | |
f866fc42 CH |
1961 | if (dev->online_queues > 1) |
1962 | nvme_queue_async_events(&dev->ctrl); | |
3cf519b5 | 1963 | |
2d55cd5f | 1964 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); |
3cf519b5 | 1965 | |
2659e57b CH |
1966 | /* |
1967 | * Keep the controller around but remove all namespaces if we don't have | |
1968 | * any working I/O queue. | |
1969 | */ | |
3cf519b5 | 1970 | if (dev->online_queues < 2) { |
1b3c47c1 | 1971 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 1972 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 1973 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1974 | } else { |
25646264 | 1975 | nvme_start_queues(&dev->ctrl); |
302ad8cc | 1976 | nvme_wait_freeze(&dev->ctrl); |
3cf519b5 | 1977 | nvme_dev_add(dev); |
302ad8cc | 1978 | nvme_unfreeze(&dev->ctrl); |
3cf519b5 CH |
1979 | } |
1980 | ||
bb8d261e CH |
1981 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
1982 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
1983 | goto out; | |
1984 | } | |
92911a55 CH |
1985 | |
1986 | if (dev->online_queues > 1) | |
5955be21 | 1987 | nvme_queue_scan(&dev->ctrl); |
3cf519b5 | 1988 | return; |
f0b50732 | 1989 | |
3cf519b5 | 1990 | out: |
f58944e2 | 1991 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
1992 | } |
1993 | ||
5c8809e6 | 1994 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1995 | { |
5c8809e6 | 1996 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1997 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 1998 | |
69d9a99c | 1999 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 2000 | if (pci_get_drvdata(pdev)) |
921920ab | 2001 | device_release_driver(&pdev->dev); |
1673f1f0 | 2002 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2003 | } |
2004 | ||
4cc06521 | 2005 | static int nvme_reset(struct nvme_dev *dev) |
9a6b9458 | 2006 | { |
1c63dc66 | 2007 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 | 2008 | return -ENODEV; |
82b057ca RP |
2009 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) |
2010 | return -EBUSY; | |
846cc05f CH |
2011 | if (!queue_work(nvme_workq, &dev->reset_work)) |
2012 | return -EBUSY; | |
846cc05f | 2013 | return 0; |
9a6b9458 KB |
2014 | } |
2015 | ||
1c63dc66 | 2016 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2017 | { |
1c63dc66 | 2018 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2019 | return 0; |
9ca97374 TH |
2020 | } |
2021 | ||
5fd4ce1b | 2022 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2023 | { |
5fd4ce1b CH |
2024 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2025 | return 0; | |
2026 | } | |
4cc06521 | 2027 | |
7fd8930f CH |
2028 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2029 | { | |
2030 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2031 | return 0; | |
4cc06521 KB |
2032 | } |
2033 | ||
f3ca80fc CH |
2034 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
2035 | { | |
c5f6ce97 KB |
2036 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
2037 | int ret = nvme_reset(dev); | |
2038 | ||
2039 | if (!ret) | |
2040 | flush_work(&dev->reset_work); | |
2041 | return ret; | |
4cc06521 | 2042 | } |
f3ca80fc | 2043 | |
1c63dc66 | 2044 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 2045 | .name = "pcie", |
e439bb12 | 2046 | .module = THIS_MODULE, |
c81bfba9 | 2047 | .flags = NVME_F_METADATA_SUPPORTED, |
1c63dc66 | 2048 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 2049 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2050 | .reg_read64 = nvme_pci_reg_read64, |
f3ca80fc | 2051 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 2052 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 2053 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 2054 | }; |
4cc06521 | 2055 | |
b00a726a KB |
2056 | static int nvme_dev_map(struct nvme_dev *dev) |
2057 | { | |
b00a726a KB |
2058 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2059 | ||
a1f447b3 | 2060 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
2061 | return -ENODEV; |
2062 | ||
2063 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
2064 | if (!dev->bar) | |
2065 | goto release; | |
2066 | ||
9fa196e7 | 2067 | return 0; |
b00a726a | 2068 | release: |
9fa196e7 MG |
2069 | pci_release_mem_regions(pdev); |
2070 | return -ENODEV; | |
b00a726a KB |
2071 | } |
2072 | ||
ff5350a8 AL |
2073 | static unsigned long check_dell_samsung_bug(struct pci_dev *pdev) |
2074 | { | |
2075 | if (pdev->vendor == 0x144d && pdev->device == 0xa802) { | |
2076 | /* | |
2077 | * Several Samsung devices seem to drop off the PCIe bus | |
2078 | * randomly when APST is on and uses the deepest sleep state. | |
2079 | * This has been observed on a Samsung "SM951 NVMe SAMSUNG | |
2080 | * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD | |
2081 | * 950 PRO 256GB", but it seems to be restricted to two Dell | |
2082 | * laptops. | |
2083 | */ | |
2084 | if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && | |
2085 | (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || | |
2086 | dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) | |
2087 | return NVME_QUIRK_NO_DEEPEST_PS; | |
2088 | } | |
2089 | ||
2090 | return 0; | |
2091 | } | |
2092 | ||
8d85fce7 | 2093 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2094 | { |
a4aea562 | 2095 | int node, result = -ENOMEM; |
b60503ba | 2096 | struct nvme_dev *dev; |
ff5350a8 | 2097 | unsigned long quirks = id->driver_data; |
b60503ba | 2098 | |
a4aea562 MB |
2099 | node = dev_to_node(&pdev->dev); |
2100 | if (node == NUMA_NO_NODE) | |
2fa84351 | 2101 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
2102 | |
2103 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2104 | if (!dev) |
2105 | return -ENOMEM; | |
a4aea562 MB |
2106 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2107 | GFP_KERNEL, node); | |
b60503ba MW |
2108 | if (!dev->queues) |
2109 | goto free; | |
2110 | ||
e75ec752 | 2111 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2112 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2113 | |
b00a726a KB |
2114 | result = nvme_dev_map(dev); |
2115 | if (result) | |
2116 | goto free; | |
2117 | ||
f3ca80fc | 2118 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 2119 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
2d55cd5f CH |
2120 | setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, |
2121 | (unsigned long)dev); | |
77bf25ea | 2122 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2123 | init_completion(&dev->ioq_wait); |
b60503ba | 2124 | |
091b6092 MW |
2125 | result = nvme_setup_prp_pools(dev); |
2126 | if (result) | |
a96d4f5c | 2127 | goto put_pci; |
4cc06521 | 2128 | |
ff5350a8 AL |
2129 | quirks |= check_dell_samsung_bug(pdev); |
2130 | ||
f3ca80fc | 2131 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
ff5350a8 | 2132 | quirks); |
4cc06521 | 2133 | if (result) |
2e1d8448 | 2134 | goto release_pools; |
740216fc | 2135 | |
82b057ca | 2136 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING); |
1b3c47c1 SG |
2137 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2138 | ||
92f7a162 | 2139 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
2140 | return 0; |
2141 | ||
0877cb0d | 2142 | release_pools: |
091b6092 | 2143 | nvme_release_prp_pools(dev); |
a96d4f5c | 2144 | put_pci: |
e75ec752 | 2145 | put_device(dev->dev); |
b00a726a | 2146 | nvme_dev_unmap(dev); |
b60503ba MW |
2147 | free: |
2148 | kfree(dev->queues); | |
b60503ba MW |
2149 | kfree(dev); |
2150 | return result; | |
2151 | } | |
2152 | ||
f0d54a54 KB |
2153 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2154 | { | |
a6739479 | 2155 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2156 | |
a6739479 | 2157 | if (prepare) |
a5cdb68c | 2158 | nvme_dev_disable(dev, false); |
a6739479 | 2159 | else |
c5f6ce97 | 2160 | nvme_reset(dev); |
f0d54a54 KB |
2161 | } |
2162 | ||
09ece142 KB |
2163 | static void nvme_shutdown(struct pci_dev *pdev) |
2164 | { | |
2165 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2166 | nvme_dev_disable(dev, true); |
09ece142 KB |
2167 | } |
2168 | ||
f58944e2 KB |
2169 | /* |
2170 | * The driver's remove may be called on a device in a partially initialized | |
2171 | * state. This function must not have any dependencies on the device state in | |
2172 | * order to proceed. | |
2173 | */ | |
8d85fce7 | 2174 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2175 | { |
2176 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2177 | |
bb8d261e CH |
2178 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2179 | ||
82b057ca | 2180 | cancel_work_sync(&dev->reset_work); |
9a6b9458 | 2181 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 2182 | |
6db28eda | 2183 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 2184 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
6db28eda KB |
2185 | nvme_dev_disable(dev, false); |
2186 | } | |
0ff9d4e1 | 2187 | |
9bf2b972 | 2188 | flush_work(&dev->reset_work); |
53029b04 | 2189 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 2190 | nvme_dev_disable(dev, true); |
a4aea562 | 2191 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2192 | nvme_free_queues(dev, 0); |
9a6b9458 | 2193 | nvme_release_prp_pools(dev); |
b00a726a | 2194 | nvme_dev_unmap(dev); |
1673f1f0 | 2195 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2196 | } |
2197 | ||
13880f5b KB |
2198 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2199 | { | |
2200 | int ret = 0; | |
2201 | ||
2202 | if (numvfs == 0) { | |
2203 | if (pci_vfs_assigned(pdev)) { | |
2204 | dev_warn(&pdev->dev, | |
2205 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2206 | return -EPERM; | |
2207 | } | |
2208 | pci_disable_sriov(pdev); | |
2209 | return 0; | |
2210 | } | |
2211 | ||
2212 | ret = pci_enable_sriov(pdev, numvfs); | |
2213 | return ret ? ret : numvfs; | |
2214 | } | |
2215 | ||
671a6018 | 2216 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2217 | static int nvme_suspend(struct device *dev) |
2218 | { | |
2219 | struct pci_dev *pdev = to_pci_dev(dev); | |
2220 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2221 | ||
a5cdb68c | 2222 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2223 | return 0; |
2224 | } | |
2225 | ||
2226 | static int nvme_resume(struct device *dev) | |
2227 | { | |
2228 | struct pci_dev *pdev = to_pci_dev(dev); | |
2229 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2230 | |
c5f6ce97 | 2231 | nvme_reset(ndev); |
9a6b9458 | 2232 | return 0; |
cd638946 | 2233 | } |
671a6018 | 2234 | #endif |
cd638946 KB |
2235 | |
2236 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2237 | |
a0a3408e KB |
2238 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2239 | pci_channel_state_t state) | |
2240 | { | |
2241 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2242 | ||
2243 | /* | |
2244 | * A frozen channel requires a reset. When detected, this method will | |
2245 | * shutdown the controller to quiesce. The controller will be restarted | |
2246 | * after the slot reset through driver's slot_reset callback. | |
2247 | */ | |
a0a3408e KB |
2248 | switch (state) { |
2249 | case pci_channel_io_normal: | |
2250 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2251 | case pci_channel_io_frozen: | |
d011fb31 KB |
2252 | dev_warn(dev->ctrl.device, |
2253 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2254 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2255 | return PCI_ERS_RESULT_NEED_RESET; |
2256 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2257 | dev_warn(dev->ctrl.device, |
2258 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2259 | return PCI_ERS_RESULT_DISCONNECT; |
2260 | } | |
2261 | return PCI_ERS_RESULT_NEED_RESET; | |
2262 | } | |
2263 | ||
2264 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2265 | { | |
2266 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2267 | ||
1b3c47c1 | 2268 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2269 | pci_restore_state(pdev); |
c5f6ce97 | 2270 | nvme_reset(dev); |
a0a3408e KB |
2271 | return PCI_ERS_RESULT_RECOVERED; |
2272 | } | |
2273 | ||
2274 | static void nvme_error_resume(struct pci_dev *pdev) | |
2275 | { | |
2276 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2277 | } | |
2278 | ||
1d352035 | 2279 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2280 | .error_detected = nvme_error_detected, |
b60503ba MW |
2281 | .slot_reset = nvme_slot_reset, |
2282 | .resume = nvme_error_resume, | |
f0d54a54 | 2283 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2284 | }; |
2285 | ||
6eb0d698 | 2286 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2287 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 | 2288 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 2289 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2290 | { PCI_VDEVICE(INTEL, 0x0a53), |
2291 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2292 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2293 | { PCI_VDEVICE(INTEL, 0x0a54), |
2294 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2295 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
50af47d0 AL |
2296 | { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ |
2297 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, | |
540c801c KB |
2298 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2299 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
54adc010 GP |
2300 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2301 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2302 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2303 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
b60503ba | 2304 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2305 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
124298bd | 2306 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
b60503ba MW |
2307 | { 0, } |
2308 | }; | |
2309 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2310 | ||
2311 | static struct pci_driver nvme_driver = { | |
2312 | .name = "nvme", | |
2313 | .id_table = nvme_id_table, | |
2314 | .probe = nvme_probe, | |
8d85fce7 | 2315 | .remove = nvme_remove, |
09ece142 | 2316 | .shutdown = nvme_shutdown, |
cd638946 KB |
2317 | .driver = { |
2318 | .pm = &nvme_dev_pm_ops, | |
2319 | }, | |
13880f5b | 2320 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2321 | .err_handler = &nvme_err_handler, |
2322 | }; | |
2323 | ||
2324 | static int __init nvme_init(void) | |
2325 | { | |
0ac13140 | 2326 | int result; |
1fa6aead | 2327 | |
92f7a162 | 2328 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2329 | if (!nvme_workq) |
b9afca3e | 2330 | return -ENOMEM; |
9a6b9458 | 2331 | |
f3db22fe KB |
2332 | result = pci_register_driver(&nvme_driver); |
2333 | if (result) | |
576d55d6 | 2334 | destroy_workqueue(nvme_workq); |
b60503ba MW |
2335 | return result; |
2336 | } | |
2337 | ||
2338 | static void __exit nvme_exit(void) | |
2339 | { | |
2340 | pci_unregister_driver(&nvme_driver); | |
9a6b9458 | 2341 | destroy_workqueue(nvme_workq); |
21bd78bc | 2342 | _nvme_check_size(); |
b60503ba MW |
2343 | } |
2344 | ||
2345 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2346 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2347 | MODULE_VERSION("1.0"); |
b60503ba MW |
2348 | module_init(nvme_init); |
2349 | module_exit(nvme_exit); |