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Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
dca51e78 | 19 | #include <linux/blk-mq-pci.h> |
42f61420 | 20 | #include <linux/cpu.h> |
fd63e9ce | 21 | #include <linux/delay.h> |
b60503ba MW |
22 | #include <linux/errno.h> |
23 | #include <linux/fs.h> | |
24 | #include <linux/genhd.h> | |
4cc09e2d | 25 | #include <linux/hdreg.h> |
5aff9382 | 26 | #include <linux/idr.h> |
b60503ba MW |
27 | #include <linux/init.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/kdev_t.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
77bf25ea | 35 | #include <linux/mutex.h> |
b60503ba | 36 | #include <linux/pci.h> |
be7b6275 | 37 | #include <linux/poison.h> |
c3bfe717 | 38 | #include <linux/ptrace.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
e1e5e564 | 41 | #include <linux/t10-pi.h> |
2d55cd5f | 42 | #include <linux/timer.h> |
b60503ba | 43 | #include <linux/types.h> |
2f8e2c87 | 44 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 45 | #include <asm/unaligned.h> |
a98e58e5 | 46 | #include <linux/sed-opal.h> |
797a796a | 47 | |
f11bb3e2 CH |
48 | #include "nvme.h" |
49 | ||
9d43cf64 | 50 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 51 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
52 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
53 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
c965809c | 54 | |
adf68f21 CH |
55 | /* |
56 | * We handle AEN commands ourselves and don't even let the | |
57 | * block layer know about them. | |
58 | */ | |
f866fc42 | 59 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) |
9d43cf64 | 60 | |
58ffacb5 MW |
61 | static int use_threaded_interrupts; |
62 | module_param(use_threaded_interrupts, int, 0); | |
63 | ||
8ffaadf7 JD |
64 | static bool use_cmb_sqes = true; |
65 | module_param(use_cmb_sqes, bool, 0644); | |
66 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
67 | ||
9a6b9458 | 68 | static struct workqueue_struct *nvme_workq; |
1fa6aead | 69 | |
1c63dc66 CH |
70 | struct nvme_dev; |
71 | struct nvme_queue; | |
b3fffdef | 72 | |
4cc06521 | 73 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 74 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 75 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 76 | |
1c63dc66 CH |
77 | /* |
78 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
79 | */ | |
80 | struct nvme_dev { | |
1c63dc66 CH |
81 | struct nvme_queue **queues; |
82 | struct blk_mq_tag_set tagset; | |
83 | struct blk_mq_tag_set admin_tagset; | |
84 | u32 __iomem *dbs; | |
85 | struct device *dev; | |
86 | struct dma_pool *prp_page_pool; | |
87 | struct dma_pool *prp_small_pool; | |
88 | unsigned queue_count; | |
89 | unsigned online_queues; | |
90 | unsigned max_qid; | |
91 | int q_depth; | |
92 | u32 db_stride; | |
1c63dc66 | 93 | void __iomem *bar; |
1c63dc66 | 94 | struct work_struct reset_work; |
5c8809e6 | 95 | struct work_struct remove_work; |
2d55cd5f | 96 | struct timer_list watchdog_timer; |
77bf25ea | 97 | struct mutex shutdown_lock; |
1c63dc66 | 98 | bool subsystem; |
1c63dc66 CH |
99 | void __iomem *cmb; |
100 | dma_addr_t cmb_dma_addr; | |
101 | u64 cmb_size; | |
102 | u32 cmbsz; | |
202021c1 | 103 | u32 cmbloc; |
1c63dc66 | 104 | struct nvme_ctrl ctrl; |
db3cbfff | 105 | struct completion ioq_wait; |
4d115420 | 106 | }; |
1fa6aead | 107 | |
1c63dc66 CH |
108 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
109 | { | |
110 | return container_of(ctrl, struct nvme_dev, ctrl); | |
111 | } | |
112 | ||
b60503ba MW |
113 | /* |
114 | * An NVM Express queue. Each device has at least two (one for admin | |
115 | * commands and one for I/O commands). | |
116 | */ | |
117 | struct nvme_queue { | |
118 | struct device *q_dmadev; | |
091b6092 | 119 | struct nvme_dev *dev; |
3193f07b | 120 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
121 | spinlock_t q_lock; |
122 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 123 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 124 | volatile struct nvme_completion *cqes; |
42483228 | 125 | struct blk_mq_tags **tags; |
b60503ba MW |
126 | dma_addr_t sq_dma_addr; |
127 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
128 | u32 __iomem *q_db; |
129 | u16 q_depth; | |
6222d172 | 130 | s16 cq_vector; |
b60503ba MW |
131 | u16 sq_tail; |
132 | u16 cq_head; | |
c30341dc | 133 | u16 qid; |
e9539f47 MW |
134 | u8 cq_phase; |
135 | u8 cqe_seen; | |
b60503ba MW |
136 | }; |
137 | ||
71bd150c CH |
138 | /* |
139 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
140 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 141 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
142 | * allocated to store the PRP list. |
143 | */ | |
144 | struct nvme_iod { | |
d49187e9 | 145 | struct nvme_request req; |
f4800d6d CH |
146 | struct nvme_queue *nvmeq; |
147 | int aborted; | |
71bd150c | 148 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
149 | int nents; /* Used in scatterlist */ |
150 | int length; /* Of data, in bytes */ | |
151 | dma_addr_t first_dma; | |
bf684057 | 152 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
153 | struct scatterlist *sg; |
154 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
155 | }; |
156 | ||
157 | /* | |
158 | * Check we didin't inadvertently grow the command struct | |
159 | */ | |
160 | static inline void _nvme_check_size(void) | |
161 | { | |
162 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
163 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
164 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
165 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
166 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 167 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 168 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
169 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
170 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
171 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
172 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 173 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
174 | } |
175 | ||
ac3dd5bd JA |
176 | /* |
177 | * Max size of iod being embedded in the request payload | |
178 | */ | |
179 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 180 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
181 | |
182 | /* | |
183 | * Will slightly overestimate the number of pages needed. This is OK | |
184 | * as it only leads to a small amount of wasted memory for the lifetime of | |
185 | * the I/O. | |
186 | */ | |
187 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
188 | { | |
5fd4ce1b CH |
189 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
190 | dev->ctrl.page_size); | |
ac3dd5bd JA |
191 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
192 | } | |
193 | ||
f4800d6d CH |
194 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
195 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 196 | { |
f4800d6d CH |
197 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
198 | sizeof(struct scatterlist) * nseg; | |
199 | } | |
ac3dd5bd | 200 | |
f4800d6d CH |
201 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
202 | { | |
203 | return sizeof(struct nvme_iod) + | |
204 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
205 | } |
206 | ||
dca51e78 CH |
207 | static int nvmeq_irq(struct nvme_queue *nvmeq) |
208 | { | |
209 | return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector); | |
210 | } | |
211 | ||
a4aea562 MB |
212 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
213 | unsigned int hctx_idx) | |
e85248e5 | 214 | { |
a4aea562 MB |
215 | struct nvme_dev *dev = data; |
216 | struct nvme_queue *nvmeq = dev->queues[0]; | |
217 | ||
42483228 KB |
218 | WARN_ON(hctx_idx != 0); |
219 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
220 | WARN_ON(nvmeq->tags); | |
221 | ||
a4aea562 | 222 | hctx->driver_data = nvmeq; |
42483228 | 223 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 224 | return 0; |
e85248e5 MW |
225 | } |
226 | ||
4af0e21c KB |
227 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
228 | { | |
229 | struct nvme_queue *nvmeq = hctx->driver_data; | |
230 | ||
231 | nvmeq->tags = NULL; | |
232 | } | |
233 | ||
a4aea562 MB |
234 | static int nvme_admin_init_request(void *data, struct request *req, |
235 | unsigned int hctx_idx, unsigned int rq_idx, | |
236 | unsigned int numa_node) | |
22404274 | 237 | { |
a4aea562 | 238 | struct nvme_dev *dev = data; |
f4800d6d | 239 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
240 | struct nvme_queue *nvmeq = dev->queues[0]; |
241 | ||
242 | BUG_ON(!nvmeq); | |
f4800d6d | 243 | iod->nvmeq = nvmeq; |
a4aea562 | 244 | return 0; |
22404274 KB |
245 | } |
246 | ||
a4aea562 MB |
247 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
248 | unsigned int hctx_idx) | |
b60503ba | 249 | { |
a4aea562 | 250 | struct nvme_dev *dev = data; |
42483228 | 251 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 252 | |
42483228 KB |
253 | if (!nvmeq->tags) |
254 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 255 | |
42483228 | 256 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
257 | hctx->driver_data = nvmeq; |
258 | return 0; | |
b60503ba MW |
259 | } |
260 | ||
a4aea562 MB |
261 | static int nvme_init_request(void *data, struct request *req, |
262 | unsigned int hctx_idx, unsigned int rq_idx, | |
263 | unsigned int numa_node) | |
b60503ba | 264 | { |
a4aea562 | 265 | struct nvme_dev *dev = data; |
f4800d6d | 266 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
267 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
268 | ||
269 | BUG_ON(!nvmeq); | |
f4800d6d | 270 | iod->nvmeq = nvmeq; |
a4aea562 MB |
271 | return 0; |
272 | } | |
273 | ||
dca51e78 CH |
274 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
275 | { | |
276 | struct nvme_dev *dev = set->driver_data; | |
277 | ||
278 | return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); | |
279 | } | |
280 | ||
b60503ba | 281 | /** |
adf68f21 | 282 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
283 | * @nvmeq: The queue to use |
284 | * @cmd: The command to send | |
285 | * | |
286 | * Safe to use from interrupt context | |
287 | */ | |
e3f879bf SB |
288 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
289 | struct nvme_command *cmd) | |
b60503ba | 290 | { |
a4aea562 MB |
291 | u16 tail = nvmeq->sq_tail; |
292 | ||
8ffaadf7 JD |
293 | if (nvmeq->sq_cmds_io) |
294 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
295 | else | |
296 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
297 | ||
b60503ba MW |
298 | if (++tail == nvmeq->q_depth) |
299 | tail = 0; | |
7547881d | 300 | writel(tail, nvmeq->q_db); |
b60503ba | 301 | nvmeq->sq_tail = tail; |
b60503ba MW |
302 | } |
303 | ||
f4800d6d | 304 | static __le64 **iod_list(struct request *req) |
b60503ba | 305 | { |
f4800d6d | 306 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
f9d03f96 | 307 | return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
308 | } |
309 | ||
b131c61d | 310 | static int nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 311 | { |
f4800d6d | 312 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
f9d03f96 | 313 | int nseg = blk_rq_nr_phys_segments(rq); |
b131c61d | 314 | unsigned int size = blk_rq_payload_bytes(rq); |
ac3dd5bd | 315 | |
f4800d6d CH |
316 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
317 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
318 | if (!iod->sg) | |
319 | return BLK_MQ_RQ_QUEUE_BUSY; | |
320 | } else { | |
321 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
322 | } |
323 | ||
f4800d6d CH |
324 | iod->aborted = 0; |
325 | iod->npages = -1; | |
326 | iod->nents = 0; | |
327 | iod->length = size; | |
f80ec966 | 328 | |
bac0000a | 329 | return BLK_MQ_RQ_QUEUE_OK; |
ac3dd5bd JA |
330 | } |
331 | ||
f4800d6d | 332 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 333 | { |
f4800d6d | 334 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 335 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 336 | int i; |
f4800d6d | 337 | __le64 **list = iod_list(req); |
eca18b23 MW |
338 | dma_addr_t prp_dma = iod->first_dma; |
339 | ||
340 | if (iod->npages == 0) | |
341 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
342 | for (i = 0; i < iod->npages; i++) { | |
343 | __le64 *prp_list = list[i]; | |
344 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
345 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
346 | prp_dma = next_prp_dma; | |
347 | } | |
ac3dd5bd | 348 | |
f4800d6d CH |
349 | if (iod->sg != iod->inline_sg) |
350 | kfree(iod->sg); | |
b4ff9c8d KB |
351 | } |
352 | ||
52b68d7e | 353 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
354 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
355 | { | |
356 | if (be32_to_cpu(pi->ref_tag) == v) | |
357 | pi->ref_tag = cpu_to_be32(p); | |
358 | } | |
359 | ||
360 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
361 | { | |
362 | if (be32_to_cpu(pi->ref_tag) == p) | |
363 | pi->ref_tag = cpu_to_be32(v); | |
364 | } | |
365 | ||
366 | /** | |
367 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
368 | * | |
369 | * The virtual start sector is the one that was originally submitted by the | |
370 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
371 | * start sector may be different. Remap protection information to match the | |
372 | * physical LBA on writes, and back to the original seed on reads. | |
373 | * | |
374 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
375 | */ | |
376 | static void nvme_dif_remap(struct request *req, | |
377 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
378 | { | |
379 | struct nvme_ns *ns = req->rq_disk->private_data; | |
380 | struct bio_integrity_payload *bip; | |
381 | struct t10_pi_tuple *pi; | |
382 | void *p, *pmap; | |
383 | u32 i, nlb, ts, phys, virt; | |
384 | ||
385 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
386 | return; | |
387 | ||
388 | bip = bio_integrity(req->bio); | |
389 | if (!bip) | |
390 | return; | |
391 | ||
392 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
393 | |
394 | p = pmap; | |
395 | virt = bip_get_seed(bip); | |
396 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
397 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 398 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
399 | |
400 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
401 | pi = (struct t10_pi_tuple *)p; | |
402 | dif_swap(phys, virt, pi); | |
403 | p += ts; | |
404 | } | |
405 | kunmap_atomic(pmap); | |
406 | } | |
52b68d7e KB |
407 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
408 | static void nvme_dif_remap(struct request *req, | |
409 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
410 | { | |
411 | } | |
412 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
413 | { | |
414 | } | |
415 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
416 | { | |
417 | } | |
52b68d7e KB |
418 | #endif |
419 | ||
b131c61d | 420 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req) |
ff22b54f | 421 | { |
f4800d6d | 422 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 423 | struct dma_pool *pool; |
b131c61d | 424 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 425 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
426 | int dma_len = sg_dma_len(sg); |
427 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 428 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 429 | int offset = dma_addr & (page_size - 1); |
e025344c | 430 | __le64 *prp_list; |
f4800d6d | 431 | __le64 **list = iod_list(req); |
e025344c | 432 | dma_addr_t prp_dma; |
eca18b23 | 433 | int nprps, i; |
ff22b54f | 434 | |
1d090624 | 435 | length -= (page_size - offset); |
ff22b54f | 436 | if (length <= 0) |
69d2b571 | 437 | return true; |
ff22b54f | 438 | |
1d090624 | 439 | dma_len -= (page_size - offset); |
ff22b54f | 440 | if (dma_len) { |
1d090624 | 441 | dma_addr += (page_size - offset); |
ff22b54f MW |
442 | } else { |
443 | sg = sg_next(sg); | |
444 | dma_addr = sg_dma_address(sg); | |
445 | dma_len = sg_dma_len(sg); | |
446 | } | |
447 | ||
1d090624 | 448 | if (length <= page_size) { |
edd10d33 | 449 | iod->first_dma = dma_addr; |
69d2b571 | 450 | return true; |
e025344c SMM |
451 | } |
452 | ||
1d090624 | 453 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
454 | if (nprps <= (256 / 8)) { |
455 | pool = dev->prp_small_pool; | |
eca18b23 | 456 | iod->npages = 0; |
99802a7a MW |
457 | } else { |
458 | pool = dev->prp_page_pool; | |
eca18b23 | 459 | iod->npages = 1; |
99802a7a MW |
460 | } |
461 | ||
69d2b571 | 462 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 463 | if (!prp_list) { |
edd10d33 | 464 | iod->first_dma = dma_addr; |
eca18b23 | 465 | iod->npages = -1; |
69d2b571 | 466 | return false; |
b77954cb | 467 | } |
eca18b23 MW |
468 | list[0] = prp_list; |
469 | iod->first_dma = prp_dma; | |
e025344c SMM |
470 | i = 0; |
471 | for (;;) { | |
1d090624 | 472 | if (i == page_size >> 3) { |
e025344c | 473 | __le64 *old_prp_list = prp_list; |
69d2b571 | 474 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 475 | if (!prp_list) |
69d2b571 | 476 | return false; |
eca18b23 | 477 | list[iod->npages++] = prp_list; |
7523d834 MW |
478 | prp_list[0] = old_prp_list[i - 1]; |
479 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
480 | i = 1; | |
e025344c SMM |
481 | } |
482 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
483 | dma_len -= page_size; |
484 | dma_addr += page_size; | |
485 | length -= page_size; | |
e025344c SMM |
486 | if (length <= 0) |
487 | break; | |
488 | if (dma_len > 0) | |
489 | continue; | |
490 | BUG_ON(dma_len < 0); | |
491 | sg = sg_next(sg); | |
492 | dma_addr = sg_dma_address(sg); | |
493 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
494 | } |
495 | ||
69d2b571 | 496 | return true; |
ff22b54f MW |
497 | } |
498 | ||
f4800d6d | 499 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 500 | struct nvme_command *cmnd) |
d29ec824 | 501 | { |
f4800d6d | 502 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
503 | struct request_queue *q = req->q; |
504 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
505 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
506 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
d29ec824 | 507 | |
f9d03f96 | 508 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
ba1ca37e CH |
509 | iod->nents = blk_rq_map_sg(q, req, iod->sg); |
510 | if (!iod->nents) | |
511 | goto out; | |
d29ec824 | 512 | |
ba1ca37e | 513 | ret = BLK_MQ_RQ_QUEUE_BUSY; |
2b6b535d MFO |
514 | if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, |
515 | DMA_ATTR_NO_WARN)) | |
ba1ca37e | 516 | goto out; |
d29ec824 | 517 | |
b131c61d | 518 | if (!nvme_setup_prps(dev, req)) |
ba1ca37e | 519 | goto out_unmap; |
0e5e4f0e | 520 | |
ba1ca37e CH |
521 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
522 | if (blk_integrity_rq(req)) { | |
523 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
524 | goto out_unmap; | |
0e5e4f0e | 525 | |
bf684057 CH |
526 | sg_init_table(&iod->meta_sg, 1); |
527 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 528 | goto out_unmap; |
0e5e4f0e | 529 | |
ba1ca37e CH |
530 | if (rq_data_dir(req)) |
531 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 532 | |
bf684057 | 533 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 534 | goto out_unmap; |
d29ec824 | 535 | } |
00df5cb4 | 536 | |
eb793e2c CH |
537 | cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
538 | cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); | |
ba1ca37e | 539 | if (blk_integrity_rq(req)) |
bf684057 | 540 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e | 541 | return BLK_MQ_RQ_QUEUE_OK; |
00df5cb4 | 542 | |
ba1ca37e CH |
543 | out_unmap: |
544 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
545 | out: | |
546 | return ret; | |
00df5cb4 MW |
547 | } |
548 | ||
f4800d6d | 549 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 550 | { |
f4800d6d | 551 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
552 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
553 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
554 | ||
555 | if (iod->nents) { | |
556 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
557 | if (blk_integrity_rq(req)) { | |
558 | if (!rq_data_dir(req)) | |
559 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 560 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 561 | } |
e19b127f | 562 | } |
e1e5e564 | 563 | |
f9d03f96 | 564 | nvme_cleanup_cmd(req); |
f4800d6d | 565 | nvme_free_iod(dev, req); |
d4f6c3ab | 566 | } |
b60503ba | 567 | |
d29ec824 CH |
568 | /* |
569 | * NOTE: ns is NULL when called on the admin queue. | |
570 | */ | |
a4aea562 MB |
571 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
572 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 573 | { |
a4aea562 MB |
574 | struct nvme_ns *ns = hctx->queue->queuedata; |
575 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 576 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 577 | struct request *req = bd->rq; |
ba1ca37e CH |
578 | struct nvme_command cmnd; |
579 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 580 | |
e1e5e564 KB |
581 | /* |
582 | * If formated with metadata, require the block layer provide a buffer | |
583 | * unless this namespace is formated such that the metadata can be | |
584 | * stripped/generated by the controller with PRACT=1. | |
585 | */ | |
d29ec824 | 586 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 | 587 | if (!(ns->pi_type && ns->ms == 8) && |
57292b58 | 588 | !blk_rq_is_passthrough(req)) { |
eee417b0 | 589 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
590 | return BLK_MQ_RQ_QUEUE_OK; |
591 | } | |
592 | } | |
593 | ||
f9d03f96 | 594 | ret = nvme_setup_cmd(ns, req, &cmnd); |
bac0000a | 595 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f4800d6d | 596 | return ret; |
a4aea562 | 597 | |
b131c61d | 598 | ret = nvme_init_iod(req, dev); |
bac0000a | 599 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f9d03f96 | 600 | goto out_free_cmd; |
a4aea562 | 601 | |
f9d03f96 | 602 | if (blk_rq_nr_phys_segments(req)) |
b131c61d | 603 | ret = nvme_map_data(dev, req, &cmnd); |
a4aea562 | 604 | |
bac0000a | 605 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f9d03f96 | 606 | goto out_cleanup_iod; |
a4aea562 | 607 | |
aae239e1 | 608 | blk_mq_start_request(req); |
a4aea562 | 609 | |
ba1ca37e | 610 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 611 | if (unlikely(nvmeq->cq_vector < 0)) { |
9ef3932e | 612 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
ae1fba20 | 613 | spin_unlock_irq(&nvmeq->q_lock); |
f9d03f96 | 614 | goto out_cleanup_iod; |
ae1fba20 | 615 | } |
ba1ca37e | 616 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
617 | nvme_process_cq(nvmeq); |
618 | spin_unlock_irq(&nvmeq->q_lock); | |
619 | return BLK_MQ_RQ_QUEUE_OK; | |
f9d03f96 | 620 | out_cleanup_iod: |
f4800d6d | 621 | nvme_free_iod(dev, req); |
f9d03f96 CH |
622 | out_free_cmd: |
623 | nvme_cleanup_cmd(req); | |
ba1ca37e | 624 | return ret; |
b60503ba | 625 | } |
e1e5e564 | 626 | |
77f02a7a | 627 | static void nvme_pci_complete_rq(struct request *req) |
eee417b0 | 628 | { |
f4800d6d | 629 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
e1e5e564 | 630 | |
77f02a7a CH |
631 | nvme_unmap_data(iod->nvmeq->dev, req); |
632 | nvme_complete_rq(req); | |
b60503ba MW |
633 | } |
634 | ||
d783e0bd MR |
635 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
636 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
637 | u16 phase) | |
638 | { | |
639 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
640 | } | |
641 | ||
a0fa9647 | 642 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 643 | { |
82123460 | 644 | u16 head, phase; |
b60503ba | 645 | |
b60503ba | 646 | head = nvmeq->cq_head; |
82123460 | 647 | phase = nvmeq->cq_phase; |
b60503ba | 648 | |
d783e0bd | 649 | while (nvme_cqe_valid(nvmeq, head, phase)) { |
b60503ba | 650 | struct nvme_completion cqe = nvmeq->cqes[head]; |
eee417b0 | 651 | struct request *req; |
adf68f21 | 652 | |
b60503ba MW |
653 | if (++head == nvmeq->q_depth) { |
654 | head = 0; | |
82123460 | 655 | phase = !phase; |
b60503ba | 656 | } |
adf68f21 | 657 | |
a0fa9647 JA |
658 | if (tag && *tag == cqe.command_id) |
659 | *tag = -1; | |
adf68f21 | 660 | |
aae239e1 | 661 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 662 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
663 | "invalid id %d completed on queue %d\n", |
664 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
665 | continue; | |
666 | } | |
667 | ||
adf68f21 CH |
668 | /* |
669 | * AEN requests are special as they don't time out and can | |
670 | * survive any kind of queue freeze and often don't respond to | |
671 | * aborts. We don't even bother to allocate a struct request | |
672 | * for them but rather special case them here. | |
673 | */ | |
674 | if (unlikely(nvmeq->qid == 0 && | |
675 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
7bf58533 CH |
676 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
677 | cqe.status, &cqe.result); | |
adf68f21 CH |
678 | continue; |
679 | } | |
680 | ||
eee417b0 | 681 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
d49187e9 | 682 | nvme_req(req)->result = cqe.result; |
d783e0bd | 683 | blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1); |
b60503ba MW |
684 | } |
685 | ||
82123460 | 686 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 687 | return; |
b60503ba | 688 | |
604e8c8d KB |
689 | if (likely(nvmeq->cq_vector >= 0)) |
690 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 691 | nvmeq->cq_head = head; |
82123460 | 692 | nvmeq->cq_phase = phase; |
b60503ba | 693 | |
e9539f47 | 694 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
695 | } |
696 | ||
697 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
698 | { | |
699 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
700 | } |
701 | ||
702 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
703 | { |
704 | irqreturn_t result; | |
705 | struct nvme_queue *nvmeq = data; | |
706 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
707 | nvme_process_cq(nvmeq); |
708 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
709 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
710 | spin_unlock(&nvmeq->q_lock); |
711 | return result; | |
712 | } | |
713 | ||
714 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
715 | { | |
716 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
717 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
718 | return IRQ_WAKE_THREAD; | |
719 | return IRQ_NONE; | |
58ffacb5 MW |
720 | } |
721 | ||
a0fa9647 JA |
722 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
723 | { | |
724 | struct nvme_queue *nvmeq = hctx->driver_data; | |
725 | ||
d783e0bd | 726 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
a0fa9647 JA |
727 | spin_lock_irq(&nvmeq->q_lock); |
728 | __nvme_process_cq(nvmeq, &tag); | |
729 | spin_unlock_irq(&nvmeq->q_lock); | |
730 | ||
731 | if (tag == -1) | |
732 | return 1; | |
733 | } | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
f866fc42 | 738 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) |
b60503ba | 739 | { |
f866fc42 | 740 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 741 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 742 | struct nvme_command c; |
b60503ba | 743 | |
a4aea562 MB |
744 | memset(&c, 0, sizeof(c)); |
745 | c.common.opcode = nvme_admin_async_event; | |
f866fc42 | 746 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; |
3c0cf138 | 747 | |
9396dec9 | 748 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 749 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 750 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
751 | } |
752 | ||
b60503ba | 753 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 754 | { |
b60503ba MW |
755 | struct nvme_command c; |
756 | ||
757 | memset(&c, 0, sizeof(c)); | |
758 | c.delete_queue.opcode = opcode; | |
759 | c.delete_queue.qid = cpu_to_le16(id); | |
760 | ||
1c63dc66 | 761 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
762 | } |
763 | ||
b60503ba MW |
764 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
765 | struct nvme_queue *nvmeq) | |
766 | { | |
b60503ba MW |
767 | struct nvme_command c; |
768 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
769 | ||
d29ec824 CH |
770 | /* |
771 | * Note: we (ab)use the fact the the prp fields survive if no data | |
772 | * is attached to the request. | |
773 | */ | |
b60503ba MW |
774 | memset(&c, 0, sizeof(c)); |
775 | c.create_cq.opcode = nvme_admin_create_cq; | |
776 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
777 | c.create_cq.cqid = cpu_to_le16(qid); | |
778 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
779 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
780 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
781 | ||
1c63dc66 | 782 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
783 | } |
784 | ||
785 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
786 | struct nvme_queue *nvmeq) | |
787 | { | |
b60503ba MW |
788 | struct nvme_command c; |
789 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
790 | ||
d29ec824 CH |
791 | /* |
792 | * Note: we (ab)use the fact the the prp fields survive if no data | |
793 | * is attached to the request. | |
794 | */ | |
b60503ba MW |
795 | memset(&c, 0, sizeof(c)); |
796 | c.create_sq.opcode = nvme_admin_create_sq; | |
797 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
798 | c.create_sq.sqid = cpu_to_le16(qid); | |
799 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
800 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
801 | c.create_sq.cqid = cpu_to_le16(qid); | |
802 | ||
1c63dc66 | 803 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
804 | } |
805 | ||
806 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
807 | { | |
808 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
809 | } | |
810 | ||
811 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
812 | { | |
813 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
814 | } | |
815 | ||
e7a2a87d | 816 | static void abort_endio(struct request *req, int error) |
bc5fc7e4 | 817 | { |
f4800d6d CH |
818 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
819 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d | 820 | u16 status = req->errors; |
e44ac588 | 821 | |
1cb3cce5 | 822 | dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status); |
e7a2a87d | 823 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 824 | blk_mq_free_request(req); |
bc5fc7e4 MW |
825 | } |
826 | ||
31c7c7d2 | 827 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 828 | { |
f4800d6d CH |
829 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
830 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 831 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 832 | struct request *abort_req; |
a4aea562 | 833 | struct nvme_command cmd; |
c30341dc | 834 | |
31c7c7d2 | 835 | /* |
fd634f41 CH |
836 | * Shutdown immediately if controller times out while starting. The |
837 | * reset work will see the pci device disabled when it gets the forced | |
838 | * cancellation error. All outstanding requests are completed on | |
839 | * shutdown, so we return BLK_EH_HANDLED. | |
840 | */ | |
bb8d261e | 841 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 842 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
843 | "I/O %d QID %d timeout, disable controller\n", |
844 | req->tag, nvmeq->qid); | |
a5cdb68c | 845 | nvme_dev_disable(dev, false); |
fd634f41 CH |
846 | req->errors = NVME_SC_CANCELLED; |
847 | return BLK_EH_HANDLED; | |
c30341dc KB |
848 | } |
849 | ||
fd634f41 CH |
850 | /* |
851 | * Shutdown the controller immediately and schedule a reset if the | |
852 | * command was already aborted once before and still hasn't been | |
853 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 854 | */ |
f4800d6d | 855 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 856 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
857 | "I/O %d QID %d timeout, reset controller\n", |
858 | req->tag, nvmeq->qid); | |
a5cdb68c | 859 | nvme_dev_disable(dev, false); |
c5f6ce97 | 860 | nvme_reset(dev); |
c30341dc | 861 | |
e1569a16 KB |
862 | /* |
863 | * Mark the request as handled, since the inline shutdown | |
864 | * forces all outstanding requests to complete. | |
865 | */ | |
866 | req->errors = NVME_SC_CANCELLED; | |
867 | return BLK_EH_HANDLED; | |
c30341dc | 868 | } |
c30341dc | 869 | |
e7a2a87d | 870 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 871 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 872 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 873 | } |
7bf7d778 | 874 | iod->aborted = 1; |
a4aea562 | 875 | |
c30341dc KB |
876 | memset(&cmd, 0, sizeof(cmd)); |
877 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 878 | cmd.abort.cid = req->tag; |
c30341dc | 879 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 880 | |
1b3c47c1 SG |
881 | dev_warn(nvmeq->dev->ctrl.device, |
882 | "I/O %d QID %d timeout, aborting\n", | |
883 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
884 | |
885 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 886 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
887 | if (IS_ERR(abort_req)) { |
888 | atomic_inc(&dev->ctrl.abort_limit); | |
889 | return BLK_EH_RESET_TIMER; | |
890 | } | |
891 | ||
892 | abort_req->timeout = ADMIN_TIMEOUT; | |
893 | abort_req->end_io_data = NULL; | |
894 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 895 | |
31c7c7d2 CH |
896 | /* |
897 | * The aborted req will be completed on receiving the abort req. | |
898 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
899 | * as the device then is in a faulty state. | |
900 | */ | |
901 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
902 | } |
903 | ||
a4aea562 MB |
904 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
905 | { | |
9e866774 MW |
906 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
907 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
908 | if (nvmeq->sq_cmds) |
909 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
910 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
911 | kfree(nvmeq); | |
912 | } | |
913 | ||
a1a5ef99 | 914 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
915 | { |
916 | int i; | |
917 | ||
a1a5ef99 | 918 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 919 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 920 | dev->queue_count--; |
a4aea562 | 921 | dev->queues[i] = NULL; |
f435c282 | 922 | nvme_free_queue(nvmeq); |
121c7ad4 | 923 | } |
22404274 KB |
924 | } |
925 | ||
4d115420 KB |
926 | /** |
927 | * nvme_suspend_queue - put queue into suspended state | |
928 | * @nvmeq - queue to suspend | |
4d115420 KB |
929 | */ |
930 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 931 | { |
2b25d981 | 932 | int vector; |
b60503ba | 933 | |
a09115b2 | 934 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
935 | if (nvmeq->cq_vector == -1) { |
936 | spin_unlock_irq(&nvmeq->q_lock); | |
937 | return 1; | |
938 | } | |
dca51e78 | 939 | vector = nvmeq_irq(nvmeq); |
42f61420 | 940 | nvmeq->dev->online_queues--; |
2b25d981 | 941 | nvmeq->cq_vector = -1; |
a09115b2 MW |
942 | spin_unlock_irq(&nvmeq->q_lock); |
943 | ||
1c63dc66 | 944 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 945 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 946 | |
aba2080f | 947 | free_irq(vector, nvmeq); |
b60503ba | 948 | |
4d115420 KB |
949 | return 0; |
950 | } | |
b60503ba | 951 | |
a5cdb68c | 952 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 953 | { |
a5cdb68c | 954 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
955 | |
956 | if (!nvmeq) | |
957 | return; | |
958 | if (nvme_suspend_queue(nvmeq)) | |
959 | return; | |
960 | ||
a5cdb68c KB |
961 | if (shutdown) |
962 | nvme_shutdown_ctrl(&dev->ctrl); | |
963 | else | |
964 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
965 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
966 | |
967 | spin_lock_irq(&nvmeq->q_lock); | |
968 | nvme_process_cq(nvmeq); | |
969 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
970 | } |
971 | ||
8ffaadf7 JD |
972 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
973 | int entry_size) | |
974 | { | |
975 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
976 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
977 | dev->ctrl.page_size); | |
8ffaadf7 JD |
978 | |
979 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 980 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 981 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 982 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
983 | |
984 | /* | |
985 | * Ensure the reduced q_depth is above some threshold where it | |
986 | * would be better to map queues in system memory with the | |
987 | * original depth | |
988 | */ | |
989 | if (q_depth < 64) | |
990 | return -ENOMEM; | |
991 | } | |
992 | ||
993 | return q_depth; | |
994 | } | |
995 | ||
996 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
997 | int qid, int depth) | |
998 | { | |
999 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1000 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1001 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1002 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1003 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1004 | } else { | |
1005 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1006 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1007 | if (!nvmeq->sq_cmds) | |
1008 | return -ENOMEM; | |
1009 | } | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
b60503ba | 1014 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
d3af3ecd | 1015 | int depth, int node) |
b60503ba | 1016 | { |
d3af3ecd SL |
1017 | struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, |
1018 | node); | |
b60503ba MW |
1019 | if (!nvmeq) |
1020 | return NULL; | |
1021 | ||
e75ec752 | 1022 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1023 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1024 | if (!nvmeq->cqes) |
1025 | goto free_nvmeq; | |
b60503ba | 1026 | |
8ffaadf7 | 1027 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1028 | goto free_cqdma; |
1029 | ||
e75ec752 | 1030 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1031 | nvmeq->dev = dev; |
3193f07b | 1032 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1033 | dev->ctrl.instance, qid); |
b60503ba MW |
1034 | spin_lock_init(&nvmeq->q_lock); |
1035 | nvmeq->cq_head = 0; | |
82123460 | 1036 | nvmeq->cq_phase = 1; |
b80d5ccc | 1037 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1038 | nvmeq->q_depth = depth; |
c30341dc | 1039 | nvmeq->qid = qid; |
758dd7fd | 1040 | nvmeq->cq_vector = -1; |
a4aea562 | 1041 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1042 | dev->queue_count++; |
1043 | ||
b60503ba MW |
1044 | return nvmeq; |
1045 | ||
1046 | free_cqdma: | |
e75ec752 | 1047 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1048 | nvmeq->cq_dma_addr); |
1049 | free_nvmeq: | |
1050 | kfree(nvmeq); | |
1051 | return NULL; | |
1052 | } | |
1053 | ||
dca51e78 | 1054 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1055 | { |
58ffacb5 | 1056 | if (use_threaded_interrupts) |
dca51e78 CH |
1057 | return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check, |
1058 | nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq); | |
1059 | else | |
1060 | return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED, | |
1061 | nvmeq->irqname, nvmeq); | |
3001082c MW |
1062 | } |
1063 | ||
22404274 | 1064 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1065 | { |
22404274 | 1066 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1067 | |
7be50e93 | 1068 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1069 | nvmeq->sq_tail = 0; |
1070 | nvmeq->cq_head = 0; | |
1071 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1072 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1073 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1074 | dev->online_queues++; |
7be50e93 | 1075 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1076 | } |
1077 | ||
1078 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1079 | { | |
1080 | struct nvme_dev *dev = nvmeq->dev; | |
1081 | int result; | |
3f85d50b | 1082 | |
2b25d981 | 1083 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1084 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1085 | if (result < 0) | |
22404274 | 1086 | return result; |
b60503ba MW |
1087 | |
1088 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1089 | if (result < 0) | |
1090 | goto release_cq; | |
1091 | ||
dca51e78 | 1092 | result = queue_request_irq(nvmeq); |
b60503ba MW |
1093 | if (result < 0) |
1094 | goto release_sq; | |
1095 | ||
22404274 | 1096 | nvme_init_queue(nvmeq, qid); |
22404274 | 1097 | return result; |
b60503ba MW |
1098 | |
1099 | release_sq: | |
1100 | adapter_delete_sq(dev, qid); | |
1101 | release_cq: | |
1102 | adapter_delete_cq(dev, qid); | |
22404274 | 1103 | return result; |
b60503ba MW |
1104 | } |
1105 | ||
f363b089 | 1106 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1107 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1108 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1109 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1110 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1111 | .init_request = nvme_admin_init_request, |
1112 | .timeout = nvme_timeout, | |
1113 | }; | |
1114 | ||
f363b089 | 1115 | static const struct blk_mq_ops nvme_mq_ops = { |
a4aea562 | 1116 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1117 | .complete = nvme_pci_complete_rq, |
a4aea562 MB |
1118 | .init_hctx = nvme_init_hctx, |
1119 | .init_request = nvme_init_request, | |
dca51e78 | 1120 | .map_queues = nvme_pci_map_queues, |
a4aea562 | 1121 | .timeout = nvme_timeout, |
a0fa9647 | 1122 | .poll = nvme_poll, |
a4aea562 MB |
1123 | }; |
1124 | ||
ea191d2f KB |
1125 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1126 | { | |
1c63dc66 | 1127 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1128 | /* |
1129 | * If the controller was reset during removal, it's possible | |
1130 | * user requests may be waiting on a stopped queue. Start the | |
1131 | * queue to flush these to completion. | |
1132 | */ | |
1133 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); | |
1c63dc66 | 1134 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1135 | blk_mq_free_tag_set(&dev->admin_tagset); |
1136 | } | |
1137 | } | |
1138 | ||
a4aea562 MB |
1139 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1140 | { | |
1c63dc66 | 1141 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1142 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1143 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1144 | |
1145 | /* | |
1146 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1147 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1148 | */ | |
1149 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1150 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1151 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1152 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
d3484991 | 1153 | dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; |
a4aea562 MB |
1154 | dev->admin_tagset.driver_data = dev; |
1155 | ||
1156 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1157 | return -ENOMEM; | |
1158 | ||
1c63dc66 CH |
1159 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1160 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1161 | blk_mq_free_tag_set(&dev->admin_tagset); |
1162 | return -ENOMEM; | |
1163 | } | |
1c63dc66 | 1164 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1165 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1166 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1167 | return -ENODEV; |
1168 | } | |
0fb59cbc | 1169 | } else |
25646264 | 1170 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1171 | |
1172 | return 0; | |
1173 | } | |
1174 | ||
8d85fce7 | 1175 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1176 | { |
ba47e386 | 1177 | int result; |
b60503ba | 1178 | u32 aqa; |
7a67cbea | 1179 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1180 | struct nvme_queue *nvmeq; |
1181 | ||
8ef2074d | 1182 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
dfbac8c7 KB |
1183 | NVME_CAP_NSSRC(cap) : 0; |
1184 | ||
7a67cbea CH |
1185 | if (dev->subsystem && |
1186 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1187 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1188 | |
5fd4ce1b | 1189 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1190 | if (result < 0) |
1191 | return result; | |
b60503ba | 1192 | |
a4aea562 | 1193 | nvmeq = dev->queues[0]; |
cd638946 | 1194 | if (!nvmeq) { |
d3af3ecd SL |
1195 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, |
1196 | dev_to_node(dev->dev)); | |
cd638946 KB |
1197 | if (!nvmeq) |
1198 | return -ENOMEM; | |
cd638946 | 1199 | } |
b60503ba MW |
1200 | |
1201 | aqa = nvmeq->q_depth - 1; | |
1202 | aqa |= aqa << 16; | |
1203 | ||
7a67cbea CH |
1204 | writel(aqa, dev->bar + NVME_REG_AQA); |
1205 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1206 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1207 | |
5fd4ce1b | 1208 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1209 | if (result) |
d4875622 | 1210 | return result; |
a4aea562 | 1211 | |
2b25d981 | 1212 | nvmeq->cq_vector = 0; |
dca51e78 | 1213 | result = queue_request_irq(nvmeq); |
758dd7fd JD |
1214 | if (result) { |
1215 | nvmeq->cq_vector = -1; | |
d4875622 | 1216 | return result; |
758dd7fd | 1217 | } |
025c557a | 1218 | |
b60503ba MW |
1219 | return result; |
1220 | } | |
1221 | ||
c875a709 GP |
1222 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1223 | { | |
1224 | ||
1225 | /* If true, indicates loss of adapter communication, possibly by a | |
1226 | * NVMe Subsystem reset. | |
1227 | */ | |
1228 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1229 | ||
1230 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
1231 | if (work_busy(&dev->reset_work)) | |
1232 | return false; | |
1233 | ||
1234 | /* We shouldn't reset unless the controller is on fatal error state | |
1235 | * _or_ if we lost the communication with it. | |
1236 | */ | |
1237 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1238 | return false; | |
1239 | ||
1240 | /* If PCI error recovery process is happening, we cannot reset or | |
1241 | * the recovery mechanism will surely fail. | |
1242 | */ | |
1243 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1244 | return false; | |
1245 | ||
1246 | return true; | |
1247 | } | |
1248 | ||
d2a61918 AL |
1249 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) |
1250 | { | |
1251 | /* Read a config register to help see what died. */ | |
1252 | u16 pci_status; | |
1253 | int result; | |
1254 | ||
1255 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1256 | &pci_status); | |
1257 | if (result == PCIBIOS_SUCCESSFUL) | |
1258 | dev_warn(dev->dev, | |
1259 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1260 | csts, pci_status); | |
1261 | else | |
1262 | dev_warn(dev->dev, | |
1263 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1264 | csts, result); | |
1265 | } | |
1266 | ||
2d55cd5f | 1267 | static void nvme_watchdog_timer(unsigned long data) |
1fa6aead | 1268 | { |
2d55cd5f CH |
1269 | struct nvme_dev *dev = (struct nvme_dev *)data; |
1270 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1fa6aead | 1271 | |
c875a709 GP |
1272 | /* Skip controllers under certain specific conditions. */ |
1273 | if (nvme_should_reset(dev, csts)) { | |
c5f6ce97 | 1274 | if (!nvme_reset(dev)) |
d2a61918 | 1275 | nvme_warn_reset(dev, csts); |
2d55cd5f | 1276 | return; |
1fa6aead | 1277 | } |
2d55cd5f CH |
1278 | |
1279 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); | |
1fa6aead MW |
1280 | } |
1281 | ||
749941f2 | 1282 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1283 | { |
949928c1 | 1284 | unsigned i, max; |
749941f2 | 1285 | int ret = 0; |
42f61420 | 1286 | |
749941f2 | 1287 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
d3af3ecd SL |
1288 | /* vector == qid - 1, match nvme_create_queue */ |
1289 | if (!nvme_alloc_queue(dev, i, dev->q_depth, | |
1290 | pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { | |
749941f2 | 1291 | ret = -ENOMEM; |
42f61420 | 1292 | break; |
749941f2 CH |
1293 | } |
1294 | } | |
42f61420 | 1295 | |
949928c1 KB |
1296 | max = min(dev->max_qid, dev->queue_count - 1); |
1297 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 | 1298 | ret = nvme_create_queue(dev->queues[i], i); |
d4875622 | 1299 | if (ret) |
42f61420 | 1300 | break; |
27e8166c | 1301 | } |
749941f2 CH |
1302 | |
1303 | /* | |
1304 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1305 | * than the desired aount of queues, and even a controller without | |
1306 | * I/O queues an still be used to issue admin commands. This might | |
1307 | * be useful to upgrade a buggy firmware for example. | |
1308 | */ | |
1309 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1310 | } |
1311 | ||
202021c1 SB |
1312 | static ssize_t nvme_cmb_show(struct device *dev, |
1313 | struct device_attribute *attr, | |
1314 | char *buf) | |
1315 | { | |
1316 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1317 | ||
c965809c | 1318 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
202021c1 SB |
1319 | ndev->cmbloc, ndev->cmbsz); |
1320 | } | |
1321 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1322 | ||
8ffaadf7 JD |
1323 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1324 | { | |
1325 | u64 szu, size, offset; | |
8ffaadf7 JD |
1326 | resource_size_t bar_size; |
1327 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1328 | void __iomem *cmb; | |
1329 | dma_addr_t dma_addr; | |
1330 | ||
7a67cbea | 1331 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1332 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1333 | return NULL; | |
202021c1 | 1334 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1335 | |
202021c1 SB |
1336 | if (!use_cmb_sqes) |
1337 | return NULL; | |
8ffaadf7 JD |
1338 | |
1339 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1340 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
202021c1 SB |
1341 | offset = szu * NVME_CMB_OFST(dev->cmbloc); |
1342 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); | |
8ffaadf7 JD |
1343 | |
1344 | if (offset > bar_size) | |
1345 | return NULL; | |
1346 | ||
1347 | /* | |
1348 | * Controllers may support a CMB size larger than their BAR, | |
1349 | * for example, due to being behind a bridge. Reduce the CMB to | |
1350 | * the reported size of the BAR | |
1351 | */ | |
1352 | if (size > bar_size - offset) | |
1353 | size = bar_size - offset; | |
1354 | ||
202021c1 | 1355 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; |
8ffaadf7 JD |
1356 | cmb = ioremap_wc(dma_addr, size); |
1357 | if (!cmb) | |
1358 | return NULL; | |
1359 | ||
1360 | dev->cmb_dma_addr = dma_addr; | |
1361 | dev->cmb_size = size; | |
1362 | return cmb; | |
1363 | } | |
1364 | ||
1365 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1366 | { | |
1367 | if (dev->cmb) { | |
1368 | iounmap(dev->cmb); | |
1369 | dev->cmb = NULL; | |
1370 | } | |
1371 | } | |
1372 | ||
9d713c2b KB |
1373 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1374 | { | |
b80d5ccc | 1375 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1376 | } |
1377 | ||
8d85fce7 | 1378 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1379 | { |
a4aea562 | 1380 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1381 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
dca51e78 | 1382 | int result, nr_io_queues, size; |
b60503ba | 1383 | |
2800b8e7 | 1384 | nr_io_queues = num_online_cpus(); |
9a0be7ab CH |
1385 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1386 | if (result < 0) | |
1b23484b | 1387 | return result; |
9a0be7ab | 1388 | |
f5fa90dc | 1389 | if (nr_io_queues == 0) |
a5229050 | 1390 | return 0; |
b60503ba | 1391 | |
8ffaadf7 JD |
1392 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1393 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1394 | sizeof(struct nvme_command)); | |
1395 | if (result > 0) | |
1396 | dev->q_depth = result; | |
1397 | else | |
1398 | nvme_release_cmb(dev); | |
1399 | } | |
1400 | ||
9d713c2b KB |
1401 | size = db_bar_size(dev, nr_io_queues); |
1402 | if (size > 8192) { | |
f1938f6e | 1403 | iounmap(dev->bar); |
9d713c2b KB |
1404 | do { |
1405 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1406 | if (dev->bar) | |
1407 | break; | |
1408 | if (!--nr_io_queues) | |
1409 | return -ENOMEM; | |
1410 | size = db_bar_size(dev, nr_io_queues); | |
1411 | } while (1); | |
7a67cbea | 1412 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1413 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1414 | } |
1415 | ||
9d713c2b | 1416 | /* Deregister the admin queue's interrupt */ |
dca51e78 | 1417 | free_irq(pci_irq_vector(pdev, 0), adminq); |
9d713c2b | 1418 | |
e32efbfc JA |
1419 | /* |
1420 | * If we enable msix early due to not intx, disable it again before | |
1421 | * setting up the full range we need. | |
1422 | */ | |
dca51e78 CH |
1423 | pci_free_irq_vectors(pdev); |
1424 | nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, | |
1425 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); | |
1426 | if (nr_io_queues <= 0) | |
1427 | return -EIO; | |
1428 | dev->max_qid = nr_io_queues; | |
fa08a396 | 1429 | |
063a8096 MW |
1430 | /* |
1431 | * Should investigate if there's a performance win from allocating | |
1432 | * more queues than interrupt vectors; it might allow the submission | |
1433 | * path to scale better, even if the receive path is limited by the | |
1434 | * number of interrupts. | |
1435 | */ | |
063a8096 | 1436 | |
dca51e78 | 1437 | result = queue_request_irq(adminq); |
758dd7fd JD |
1438 | if (result) { |
1439 | adminq->cq_vector = -1; | |
d4875622 | 1440 | return result; |
758dd7fd | 1441 | } |
749941f2 | 1442 | return nvme_create_io_queues(dev); |
b60503ba MW |
1443 | } |
1444 | ||
db3cbfff | 1445 | static void nvme_del_queue_end(struct request *req, int error) |
a5768aa8 | 1446 | { |
db3cbfff | 1447 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1448 | |
db3cbfff KB |
1449 | blk_mq_free_request(req); |
1450 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1451 | } |
1452 | ||
db3cbfff | 1453 | static void nvme_del_cq_end(struct request *req, int error) |
a5768aa8 | 1454 | { |
db3cbfff | 1455 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1456 | |
db3cbfff KB |
1457 | if (!error) { |
1458 | unsigned long flags; | |
1459 | ||
2e39e0f6 ML |
1460 | /* |
1461 | * We might be called with the AQ q_lock held | |
1462 | * and the I/O queue q_lock should always | |
1463 | * nest inside the AQ one. | |
1464 | */ | |
1465 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1466 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1467 | nvme_process_cq(nvmeq); |
1468 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1469 | } |
db3cbfff KB |
1470 | |
1471 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1472 | } |
1473 | ||
db3cbfff | 1474 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1475 | { |
db3cbfff KB |
1476 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1477 | struct request *req; | |
1478 | struct nvme_command cmd; | |
bda4e0fb | 1479 | |
db3cbfff KB |
1480 | memset(&cmd, 0, sizeof(cmd)); |
1481 | cmd.delete_queue.opcode = opcode; | |
1482 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1483 | |
eb71f435 | 1484 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
1485 | if (IS_ERR(req)) |
1486 | return PTR_ERR(req); | |
bda4e0fb | 1487 | |
db3cbfff KB |
1488 | req->timeout = ADMIN_TIMEOUT; |
1489 | req->end_io_data = nvmeq; | |
1490 | ||
1491 | blk_execute_rq_nowait(q, NULL, req, false, | |
1492 | opcode == nvme_admin_delete_cq ? | |
1493 | nvme_del_cq_end : nvme_del_queue_end); | |
1494 | return 0; | |
bda4e0fb KB |
1495 | } |
1496 | ||
70659060 | 1497 | static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) |
a5768aa8 | 1498 | { |
70659060 | 1499 | int pass; |
db3cbfff KB |
1500 | unsigned long timeout; |
1501 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1502 | |
db3cbfff | 1503 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 1504 | int sent = 0, i = queues; |
db3cbfff KB |
1505 | |
1506 | reinit_completion(&dev->ioq_wait); | |
1507 | retry: | |
1508 | timeout = ADMIN_TIMEOUT; | |
c21377f8 GKB |
1509 | for (; i > 0; i--, sent++) |
1510 | if (nvme_delete_queue(dev->queues[i], opcode)) | |
db3cbfff | 1511 | break; |
c21377f8 | 1512 | |
db3cbfff KB |
1513 | while (sent--) { |
1514 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1515 | if (timeout == 0) | |
1516 | return; | |
1517 | if (i) | |
1518 | goto retry; | |
1519 | } | |
1520 | opcode = nvme_admin_delete_cq; | |
1521 | } | |
a5768aa8 KB |
1522 | } |
1523 | ||
422ef0c7 MW |
1524 | /* |
1525 | * Return: error value if an error occurred setting up the queues or calling | |
1526 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1527 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1528 | * failures should be reported. | |
1529 | */ | |
8d85fce7 | 1530 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1531 | { |
5bae7f73 | 1532 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1533 | dev->tagset.ops = &nvme_mq_ops; |
1534 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1535 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1536 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1537 | dev->tagset.queue_depth = | |
a4aea562 | 1538 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1539 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1540 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1541 | dev->tagset.driver_data = dev; | |
b60503ba | 1542 | |
ffe7704d KB |
1543 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1544 | return 0; | |
5bae7f73 | 1545 | dev->ctrl.tagset = &dev->tagset; |
949928c1 KB |
1546 | } else { |
1547 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1548 | ||
1549 | /* Free previously allocated queues that are no longer usable */ | |
1550 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1551 | } |
949928c1 | 1552 | |
e1e5e564 | 1553 | return 0; |
b60503ba MW |
1554 | } |
1555 | ||
b00a726a | 1556 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1557 | { |
42f61420 | 1558 | u64 cap; |
b00a726a | 1559 | int result = -ENOMEM; |
e75ec752 | 1560 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1561 | |
1562 | if (pci_enable_device_mem(pdev)) | |
1563 | return result; | |
1564 | ||
0877cb0d | 1565 | pci_set_master(pdev); |
0877cb0d | 1566 | |
e75ec752 CH |
1567 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1568 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1569 | goto disable; |
0877cb0d | 1570 | |
7a67cbea | 1571 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1572 | result = -ENODEV; |
b00a726a | 1573 | goto disable; |
0e53d180 | 1574 | } |
e32efbfc JA |
1575 | |
1576 | /* | |
a5229050 KB |
1577 | * Some devices and/or platforms don't advertise or work with INTx |
1578 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1579 | * adjust this later. | |
e32efbfc | 1580 | */ |
dca51e78 CH |
1581 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
1582 | if (result < 0) | |
1583 | return result; | |
e32efbfc | 1584 | |
7a67cbea CH |
1585 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1586 | ||
42f61420 KB |
1587 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1588 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1589 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1590 | |
1591 | /* | |
1592 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1593 | * some MacBook7,1 to avoid controller resets and data loss. | |
1594 | */ | |
1595 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1596 | dev->q_depth = 2; | |
1597 | dev_warn(dev->dev, "detected Apple NVMe controller, set " | |
1598 | "queue depth=%u to work around controller resets\n", | |
1599 | dev->q_depth); | |
1600 | } | |
1601 | ||
202021c1 SB |
1602 | /* |
1603 | * CMBs can currently only exist on >=1.2 PCIe devices. We only | |
1604 | * populate sysfs if a CMB is implemented. Note that we add the | |
1605 | * CMB attribute to the nvme_ctrl kobj which removes the need to remove | |
1606 | * it on exit. Since nvme_dev_attrs_group has no name we can pass | |
1607 | * NULL as final argument to sysfs_add_file_to_group. | |
1608 | */ | |
1609 | ||
8ef2074d | 1610 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { |
8ffaadf7 | 1611 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1612 | |
202021c1 SB |
1613 | if (dev->cmbsz) { |
1614 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, | |
1615 | &dev_attr_cmb.attr, NULL)) | |
1616 | dev_warn(dev->dev, | |
1617 | "failed to add sysfs attribute for CMB\n"); | |
1618 | } | |
1619 | } | |
1620 | ||
a0a3408e KB |
1621 | pci_enable_pcie_error_reporting(pdev); |
1622 | pci_save_state(pdev); | |
0877cb0d KB |
1623 | return 0; |
1624 | ||
1625 | disable: | |
0877cb0d KB |
1626 | pci_disable_device(pdev); |
1627 | return result; | |
1628 | } | |
1629 | ||
1630 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1631 | { |
1632 | if (dev->bar) | |
1633 | iounmap(dev->bar); | |
a1f447b3 | 1634 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
1635 | } |
1636 | ||
1637 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1638 | { |
e75ec752 CH |
1639 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1640 | ||
dca51e78 | 1641 | pci_free_irq_vectors(pdev); |
0877cb0d | 1642 | |
a0a3408e KB |
1643 | if (pci_is_enabled(pdev)) { |
1644 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1645 | pci_disable_device(pdev); |
4d115420 | 1646 | } |
4d115420 KB |
1647 | } |
1648 | ||
a5cdb68c | 1649 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1650 | { |
70659060 | 1651 | int i, queues; |
302ad8cc KB |
1652 | bool dead = true; |
1653 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
22404274 | 1654 | |
2d55cd5f | 1655 | del_timer_sync(&dev->watchdog_timer); |
1fa6aead | 1656 | |
77bf25ea | 1657 | mutex_lock(&dev->shutdown_lock); |
302ad8cc KB |
1658 | if (pci_is_enabled(pdev)) { |
1659 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1660 | ||
1661 | if (dev->ctrl.state == NVME_CTRL_LIVE) | |
1662 | nvme_start_freeze(&dev->ctrl); | |
1663 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || | |
1664 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 1665 | } |
c21377f8 | 1666 | |
302ad8cc KB |
1667 | /* |
1668 | * Give the controller a chance to complete all entered requests if | |
1669 | * doing a safe shutdown. | |
1670 | */ | |
1671 | if (!dead && shutdown) | |
1672 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
1673 | nvme_stop_queues(&dev->ctrl); | |
1674 | ||
70659060 | 1675 | queues = dev->online_queues - 1; |
c21377f8 GKB |
1676 | for (i = dev->queue_count - 1; i > 0; i--) |
1677 | nvme_suspend_queue(dev->queues[i]); | |
1678 | ||
302ad8cc | 1679 | if (dead) { |
82469c59 GKB |
1680 | /* A device might become IO incapable very soon during |
1681 | * probe, before the admin queue is configured. Thus, | |
1682 | * queue_count can be 0 here. | |
1683 | */ | |
1684 | if (dev->queue_count) | |
1685 | nvme_suspend_queue(dev->queues[0]); | |
4d115420 | 1686 | } else { |
70659060 | 1687 | nvme_disable_io_queues(dev, queues); |
a5cdb68c | 1688 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1689 | } |
b00a726a | 1690 | nvme_pci_disable(dev); |
07836e65 | 1691 | |
e1958e65 ML |
1692 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
1693 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
302ad8cc KB |
1694 | |
1695 | /* | |
1696 | * The driver will not be starting up queues again if shutting down so | |
1697 | * must flush all entered requests to their failed completion to avoid | |
1698 | * deadlocking blk-mq hot-cpu notifier. | |
1699 | */ | |
1700 | if (shutdown) | |
1701 | nvme_start_queues(&dev->ctrl); | |
77bf25ea | 1702 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
1703 | } |
1704 | ||
091b6092 MW |
1705 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1706 | { | |
e75ec752 | 1707 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1708 | PAGE_SIZE, PAGE_SIZE, 0); |
1709 | if (!dev->prp_page_pool) | |
1710 | return -ENOMEM; | |
1711 | ||
99802a7a | 1712 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1713 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1714 | 256, 256, 0); |
1715 | if (!dev->prp_small_pool) { | |
1716 | dma_pool_destroy(dev->prp_page_pool); | |
1717 | return -ENOMEM; | |
1718 | } | |
091b6092 MW |
1719 | return 0; |
1720 | } | |
1721 | ||
1722 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1723 | { | |
1724 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1725 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1726 | } |
1727 | ||
1673f1f0 | 1728 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1729 | { |
1673f1f0 | 1730 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1731 | |
e75ec752 | 1732 | put_device(dev->dev); |
4af0e21c KB |
1733 | if (dev->tagset.tags) |
1734 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1735 | if (dev->ctrl.admin_q) |
1736 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 1737 | kfree(dev->queues); |
e286bcfc | 1738 | free_opal_dev(dev->ctrl.opal_dev); |
5e82e952 KB |
1739 | kfree(dev); |
1740 | } | |
1741 | ||
f58944e2 KB |
1742 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
1743 | { | |
237045fc | 1744 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
1745 | |
1746 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 1747 | nvme_dev_disable(dev, false); |
f58944e2 KB |
1748 | if (!schedule_work(&dev->remove_work)) |
1749 | nvme_put_ctrl(&dev->ctrl); | |
1750 | } | |
1751 | ||
fd634f41 | 1752 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 1753 | { |
fd634f41 | 1754 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
a98e58e5 | 1755 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
f58944e2 | 1756 | int result = -ENODEV; |
5e82e952 | 1757 | |
bb8d261e | 1758 | if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING)) |
fd634f41 | 1759 | goto out; |
5e82e952 | 1760 | |
fd634f41 CH |
1761 | /* |
1762 | * If we're called to reset a live controller first shut it down before | |
1763 | * moving on. | |
1764 | */ | |
b00a726a | 1765 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 1766 | nvme_dev_disable(dev, false); |
5e82e952 | 1767 | |
bb8d261e | 1768 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) |
9bf2b972 KB |
1769 | goto out; |
1770 | ||
b00a726a | 1771 | result = nvme_pci_enable(dev); |
f0b50732 | 1772 | if (result) |
3cf519b5 | 1773 | goto out; |
f0b50732 KB |
1774 | |
1775 | result = nvme_configure_admin_queue(dev); | |
1776 | if (result) | |
f58944e2 | 1777 | goto out; |
f0b50732 | 1778 | |
a4aea562 | 1779 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1780 | result = nvme_alloc_admin_tags(dev); |
1781 | if (result) | |
f58944e2 | 1782 | goto out; |
b9afca3e | 1783 | |
ce4541f4 CH |
1784 | result = nvme_init_identify(&dev->ctrl); |
1785 | if (result) | |
f58944e2 | 1786 | goto out; |
ce4541f4 | 1787 | |
e286bcfc SB |
1788 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
1789 | if (!dev->ctrl.opal_dev) | |
1790 | dev->ctrl.opal_dev = | |
1791 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); | |
1792 | else if (was_suspend) | |
1793 | opal_unlock_from_suspend(dev->ctrl.opal_dev); | |
1794 | } else { | |
1795 | free_opal_dev(dev->ctrl.opal_dev); | |
1796 | dev->ctrl.opal_dev = NULL; | |
4f1244c8 | 1797 | } |
a98e58e5 | 1798 | |
f0b50732 | 1799 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1800 | if (result) |
f58944e2 | 1801 | goto out; |
f0b50732 | 1802 | |
21f033f7 KB |
1803 | /* |
1804 | * A controller that can not execute IO typically requires user | |
1805 | * intervention to correct. For such degraded controllers, the driver | |
1806 | * should not submit commands the user did not request, so skip | |
1807 | * registering for asynchronous event notification on this condition. | |
1808 | */ | |
f866fc42 CH |
1809 | if (dev->online_queues > 1) |
1810 | nvme_queue_async_events(&dev->ctrl); | |
3cf519b5 | 1811 | |
2d55cd5f | 1812 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); |
3cf519b5 | 1813 | |
2659e57b CH |
1814 | /* |
1815 | * Keep the controller around but remove all namespaces if we don't have | |
1816 | * any working I/O queue. | |
1817 | */ | |
3cf519b5 | 1818 | if (dev->online_queues < 2) { |
1b3c47c1 | 1819 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 1820 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 1821 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1822 | } else { |
25646264 | 1823 | nvme_start_queues(&dev->ctrl); |
302ad8cc | 1824 | nvme_wait_freeze(&dev->ctrl); |
3cf519b5 | 1825 | nvme_dev_add(dev); |
302ad8cc | 1826 | nvme_unfreeze(&dev->ctrl); |
3cf519b5 CH |
1827 | } |
1828 | ||
bb8d261e CH |
1829 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
1830 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
1831 | goto out; | |
1832 | } | |
92911a55 CH |
1833 | |
1834 | if (dev->online_queues > 1) | |
5955be21 | 1835 | nvme_queue_scan(&dev->ctrl); |
3cf519b5 | 1836 | return; |
f0b50732 | 1837 | |
3cf519b5 | 1838 | out: |
f58944e2 | 1839 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
1840 | } |
1841 | ||
5c8809e6 | 1842 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1843 | { |
5c8809e6 | 1844 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1845 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 1846 | |
69d9a99c | 1847 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 1848 | if (pci_get_drvdata(pdev)) |
921920ab | 1849 | device_release_driver(&pdev->dev); |
1673f1f0 | 1850 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
1851 | } |
1852 | ||
4cc06521 | 1853 | static int nvme_reset(struct nvme_dev *dev) |
9a6b9458 | 1854 | { |
1c63dc66 | 1855 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 | 1856 | return -ENODEV; |
c5f6ce97 KB |
1857 | if (work_busy(&dev->reset_work)) |
1858 | return -ENODEV; | |
846cc05f CH |
1859 | if (!queue_work(nvme_workq, &dev->reset_work)) |
1860 | return -EBUSY; | |
846cc05f | 1861 | return 0; |
9a6b9458 KB |
1862 | } |
1863 | ||
1c63dc66 | 1864 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 1865 | { |
1c63dc66 | 1866 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 1867 | return 0; |
9ca97374 TH |
1868 | } |
1869 | ||
5fd4ce1b | 1870 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 1871 | { |
5fd4ce1b CH |
1872 | writel(val, to_nvme_dev(ctrl)->bar + off); |
1873 | return 0; | |
1874 | } | |
4cc06521 | 1875 | |
7fd8930f CH |
1876 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
1877 | { | |
1878 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
1879 | return 0; | |
4cc06521 KB |
1880 | } |
1881 | ||
f3ca80fc CH |
1882 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
1883 | { | |
c5f6ce97 KB |
1884 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
1885 | int ret = nvme_reset(dev); | |
1886 | ||
1887 | if (!ret) | |
1888 | flush_work(&dev->reset_work); | |
1889 | return ret; | |
4cc06521 | 1890 | } |
f3ca80fc | 1891 | |
1c63dc66 | 1892 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 1893 | .name = "pcie", |
e439bb12 | 1894 | .module = THIS_MODULE, |
1c63dc66 | 1895 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 1896 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 1897 | .reg_read64 = nvme_pci_reg_read64, |
f3ca80fc | 1898 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 1899 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 1900 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 1901 | }; |
4cc06521 | 1902 | |
b00a726a KB |
1903 | static int nvme_dev_map(struct nvme_dev *dev) |
1904 | { | |
b00a726a KB |
1905 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1906 | ||
a1f447b3 | 1907 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
1908 | return -ENODEV; |
1909 | ||
1910 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
1911 | if (!dev->bar) | |
1912 | goto release; | |
1913 | ||
9fa196e7 | 1914 | return 0; |
b00a726a | 1915 | release: |
9fa196e7 MG |
1916 | pci_release_mem_regions(pdev); |
1917 | return -ENODEV; | |
b00a726a KB |
1918 | } |
1919 | ||
8d85fce7 | 1920 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 1921 | { |
a4aea562 | 1922 | int node, result = -ENOMEM; |
b60503ba MW |
1923 | struct nvme_dev *dev; |
1924 | ||
a4aea562 MB |
1925 | node = dev_to_node(&pdev->dev); |
1926 | if (node == NUMA_NO_NODE) | |
2fa84351 | 1927 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
1928 | |
1929 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
1930 | if (!dev) |
1931 | return -ENOMEM; | |
a4aea562 MB |
1932 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
1933 | GFP_KERNEL, node); | |
b60503ba MW |
1934 | if (!dev->queues) |
1935 | goto free; | |
1936 | ||
e75ec752 | 1937 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 1938 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 1939 | |
b00a726a KB |
1940 | result = nvme_dev_map(dev); |
1941 | if (result) | |
1942 | goto free; | |
1943 | ||
f3ca80fc | 1944 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 1945 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
2d55cd5f CH |
1946 | setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, |
1947 | (unsigned long)dev); | |
77bf25ea | 1948 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 1949 | init_completion(&dev->ioq_wait); |
b60503ba | 1950 | |
091b6092 MW |
1951 | result = nvme_setup_prp_pools(dev); |
1952 | if (result) | |
a96d4f5c | 1953 | goto put_pci; |
4cc06521 | 1954 | |
f3ca80fc CH |
1955 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
1956 | id->driver_data); | |
4cc06521 | 1957 | if (result) |
2e1d8448 | 1958 | goto release_pools; |
740216fc | 1959 | |
1b3c47c1 SG |
1960 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
1961 | ||
92f7a162 | 1962 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
1963 | return 0; |
1964 | ||
0877cb0d | 1965 | release_pools: |
091b6092 | 1966 | nvme_release_prp_pools(dev); |
a96d4f5c | 1967 | put_pci: |
e75ec752 | 1968 | put_device(dev->dev); |
b00a726a | 1969 | nvme_dev_unmap(dev); |
b60503ba MW |
1970 | free: |
1971 | kfree(dev->queues); | |
b60503ba MW |
1972 | kfree(dev); |
1973 | return result; | |
1974 | } | |
1975 | ||
f0d54a54 KB |
1976 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
1977 | { | |
a6739479 | 1978 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 1979 | |
a6739479 | 1980 | if (prepare) |
a5cdb68c | 1981 | nvme_dev_disable(dev, false); |
a6739479 | 1982 | else |
c5f6ce97 | 1983 | nvme_reset(dev); |
f0d54a54 KB |
1984 | } |
1985 | ||
09ece142 KB |
1986 | static void nvme_shutdown(struct pci_dev *pdev) |
1987 | { | |
1988 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 1989 | nvme_dev_disable(dev, true); |
09ece142 KB |
1990 | } |
1991 | ||
f58944e2 KB |
1992 | /* |
1993 | * The driver's remove may be called on a device in a partially initialized | |
1994 | * state. This function must not have any dependencies on the device state in | |
1995 | * order to proceed. | |
1996 | */ | |
8d85fce7 | 1997 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
1998 | { |
1999 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2000 | |
bb8d261e CH |
2001 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2002 | ||
9a6b9458 | 2003 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 2004 | |
6db28eda | 2005 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 2006 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
6db28eda KB |
2007 | nvme_dev_disable(dev, false); |
2008 | } | |
0ff9d4e1 | 2009 | |
9bf2b972 | 2010 | flush_work(&dev->reset_work); |
53029b04 | 2011 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 2012 | nvme_dev_disable(dev, true); |
a4aea562 | 2013 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2014 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2015 | nvme_release_cmb(dev); |
9a6b9458 | 2016 | nvme_release_prp_pools(dev); |
b00a726a | 2017 | nvme_dev_unmap(dev); |
1673f1f0 | 2018 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2019 | } |
2020 | ||
13880f5b KB |
2021 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2022 | { | |
2023 | int ret = 0; | |
2024 | ||
2025 | if (numvfs == 0) { | |
2026 | if (pci_vfs_assigned(pdev)) { | |
2027 | dev_warn(&pdev->dev, | |
2028 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2029 | return -EPERM; | |
2030 | } | |
2031 | pci_disable_sriov(pdev); | |
2032 | return 0; | |
2033 | } | |
2034 | ||
2035 | ret = pci_enable_sriov(pdev, numvfs); | |
2036 | return ret ? ret : numvfs; | |
2037 | } | |
2038 | ||
671a6018 | 2039 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2040 | static int nvme_suspend(struct device *dev) |
2041 | { | |
2042 | struct pci_dev *pdev = to_pci_dev(dev); | |
2043 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2044 | ||
a5cdb68c | 2045 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2046 | return 0; |
2047 | } | |
2048 | ||
2049 | static int nvme_resume(struct device *dev) | |
2050 | { | |
2051 | struct pci_dev *pdev = to_pci_dev(dev); | |
2052 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2053 | |
c5f6ce97 | 2054 | nvme_reset(ndev); |
9a6b9458 | 2055 | return 0; |
cd638946 | 2056 | } |
671a6018 | 2057 | #endif |
cd638946 KB |
2058 | |
2059 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2060 | |
a0a3408e KB |
2061 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2062 | pci_channel_state_t state) | |
2063 | { | |
2064 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2065 | ||
2066 | /* | |
2067 | * A frozen channel requires a reset. When detected, this method will | |
2068 | * shutdown the controller to quiesce. The controller will be restarted | |
2069 | * after the slot reset through driver's slot_reset callback. | |
2070 | */ | |
a0a3408e KB |
2071 | switch (state) { |
2072 | case pci_channel_io_normal: | |
2073 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2074 | case pci_channel_io_frozen: | |
d011fb31 KB |
2075 | dev_warn(dev->ctrl.device, |
2076 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2077 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2078 | return PCI_ERS_RESULT_NEED_RESET; |
2079 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2080 | dev_warn(dev->ctrl.device, |
2081 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2082 | return PCI_ERS_RESULT_DISCONNECT; |
2083 | } | |
2084 | return PCI_ERS_RESULT_NEED_RESET; | |
2085 | } | |
2086 | ||
2087 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2088 | { | |
2089 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2090 | ||
1b3c47c1 | 2091 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2092 | pci_restore_state(pdev); |
c5f6ce97 | 2093 | nvme_reset(dev); |
a0a3408e KB |
2094 | return PCI_ERS_RESULT_RECOVERED; |
2095 | } | |
2096 | ||
2097 | static void nvme_error_resume(struct pci_dev *pdev) | |
2098 | { | |
2099 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2100 | } | |
2101 | ||
1d352035 | 2102 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2103 | .error_detected = nvme_error_detected, |
b60503ba MW |
2104 | .slot_reset = nvme_slot_reset, |
2105 | .resume = nvme_error_resume, | |
f0d54a54 | 2106 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2107 | }; |
2108 | ||
6eb0d698 | 2109 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2110 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 KB |
2111 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
2112 | NVME_QUIRK_DISCARD_ZEROES, }, | |
99466e70 KB |
2113 | { PCI_VDEVICE(INTEL, 0x0a53), |
2114 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2115 | NVME_QUIRK_DISCARD_ZEROES, }, | |
2116 | { PCI_VDEVICE(INTEL, 0x0a54), | |
2117 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2118 | NVME_QUIRK_DISCARD_ZEROES, }, | |
540c801c KB |
2119 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2120 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
54adc010 GP |
2121 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2122 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2123 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2124 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
b60503ba | 2125 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2126 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
124298bd | 2127 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
b60503ba MW |
2128 | { 0, } |
2129 | }; | |
2130 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2131 | ||
2132 | static struct pci_driver nvme_driver = { | |
2133 | .name = "nvme", | |
2134 | .id_table = nvme_id_table, | |
2135 | .probe = nvme_probe, | |
8d85fce7 | 2136 | .remove = nvme_remove, |
09ece142 | 2137 | .shutdown = nvme_shutdown, |
cd638946 KB |
2138 | .driver = { |
2139 | .pm = &nvme_dev_pm_ops, | |
2140 | }, | |
13880f5b | 2141 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2142 | .err_handler = &nvme_err_handler, |
2143 | }; | |
2144 | ||
2145 | static int __init nvme_init(void) | |
2146 | { | |
0ac13140 | 2147 | int result; |
1fa6aead | 2148 | |
92f7a162 | 2149 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2150 | if (!nvme_workq) |
b9afca3e | 2151 | return -ENOMEM; |
9a6b9458 | 2152 | |
f3db22fe KB |
2153 | result = pci_register_driver(&nvme_driver); |
2154 | if (result) | |
576d55d6 | 2155 | destroy_workqueue(nvme_workq); |
b60503ba MW |
2156 | return result; |
2157 | } | |
2158 | ||
2159 | static void __exit nvme_exit(void) | |
2160 | { | |
2161 | pci_unregister_driver(&nvme_driver); | |
9a6b9458 | 2162 | destroy_workqueue(nvme_workq); |
21bd78bc | 2163 | _nvme_check_size(); |
b60503ba MW |
2164 | } |
2165 | ||
2166 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2167 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2168 | MODULE_VERSION("1.0"); |
b60503ba MW |
2169 | module_init(nvme_init); |
2170 | module_exit(nvme_exit); |