gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004\r
gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
\r
- #\r
- # ARM PL180 MCI\r
- #\r
- gArmTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000006\r
- gArmTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000007\r
-\r
#\r
# ARM PL390 General Interrupt Controller\r
#\r
ArmTrustZoneLib|ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
ArmMPCoreMailBoxLib|ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBoxLib.inf
- PL354SmcLib|ArmPkg/Drivers/PL35xSmc/PL354SmcSec.inf
- PL341DmcLib|ArmPkg/Drivers/PL34xDmc/PL341Dmc.inf
- PL301AxiLib|ArmPkg/Drivers/PL301Axi/PL301Axi.inf
- PL310L2CacheSecLib|ArmPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf
-
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
- ArmPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
ArmPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf
ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf
- ArmPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
- ArmPkg/Drivers/PL301Axi/PL301Axi.inf
- ArmPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf
- ArmPkg/Drivers/PL34xDmc/PL341Dmc.inf
- ArmPkg/Drivers/PL35xSmc/PL354SmcSec.inf
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
-
-
+++ /dev/null
-/** @file\r
- This file implement the MMC Host Protocol for the ARM PrimeCell PL180.\r
-\r
- Copyright (c) 2011, ARM Limited. All rights reserved.\r
- \r
- This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-**/\r
-\r
-#include "PL180Mci.h"\r
-\r
-#include <Library/DevicePathLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-\r
-EFI_MMC_HOST_PROTOCOL *gpMmcHost;\r
-\r
-// Untested ...\r
-//#define USE_STREAM\r
-\r
-#define MMCI0_BLOCKLEN 512\r
-#define MMCI0_POW2_BLOCKLEN 9\r
-#define MMCI0_TIMEOUT 1000\r
-\r
-BOOLEAN\r
-MciIsPowerOn (\r
- VOID\r
- )\r
-{\r
- return ((MmioRead32(MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON);\r
-}\r
-\r
-EFI_STATUS\r
-MciInitialize (\r
- VOID\r
- )\r
-{\r
- MCI_TRACE("MciInitialize()");\r
- return EFI_SUCCESS;\r
-}\r
-\r
-BOOLEAN\r
-MciIsCardPresent (\r
- VOID\r
- )\r
-{\r
- return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress)) & 1);\r
-}\r
-\r
-BOOLEAN\r
-MciIsReadOnly (\r
- VOID\r
- )\r
-{\r
- return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress)) & 2);\r
-}\r
-\r
-#if 0\r
-//Note: This function has been commented out because it is not used yet.\r
-// This function could be used to remove the hardcoded BlockLen used\r
-// in MciPrepareDataPath\r
-\r
-// Convert block size to 2^n\r
-STATIC\r
-UINT32\r
-GetPow2BlockLen (\r
- IN UINT32 BlockLen\r
- )\r
-{\r
- UINTN Loop;\r
- UINTN Pow2BlockLen;\r
-\r
- Loop = 0x8000;\r
- Pow2BlockLen = 15;\r
- do {\r
- Loop = (Loop >> 1) & 0xFFFF;\r
- Pow2BlockLen--;\r
- } while (Pow2BlockLen && (!(Loop & BlockLen)));\r
-\r
- return Pow2BlockLen;\r
-}\r
-#endif\r
-\r
-VOID\r
-MciPrepareDataPath (\r
- IN UINTN TransferDirection\r
- )\r
-{\r
- // Set Data Length & Data Timer\r
- MmioWrite32(MCI_DATA_TIMER_REG,0xFFFFFFF);\r
- MmioWrite32(MCI_DATA_LENGTH_REG,MMCI0_BLOCKLEN);\r
-\r
-#ifndef USE_STREAM\r
- //Note: we are using a hardcoded BlockLen (=512). If we decide to use a variable size, we could\r
- // compute the pow2 of BlockLen with the above function GetPow2BlockLen()\r
- MmioWrite32(MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4));\r
-#else\r
- MmioWrite32(MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | MCI_DATACTL_STREAM_TRANS);\r
-#endif\r
-}\r
-\r
-EFI_STATUS\r
-MciSendCommand (\r
- IN MMC_CMD MmcCmd,\r
- IN UINT32 Argument\r
- )\r
-{\r
- UINT32 Status;\r
- UINT32 Cmd;\r
- UINTN RetVal;\r
- UINTN CmdCtrlReg;\r
-\r
- RetVal = EFI_SUCCESS;\r
-\r
- if ((MmcCmd == MMC_CMD17) || (MmcCmd == MMC_CMD11)) {\r
- MciPrepareDataPath(MCI_DATACTL_CARD_TO_CONT);\r
- } else if ((MmcCmd == MMC_CMD24) || (MmcCmd == MMC_CMD20)) {\r
- MciPrepareDataPath(MCI_DATACTL_CONT_TO_CARD);\r
- }\r
-\r
- // Create Command for PL180\r
- Cmd = (MMC_GET_INDX(MmcCmd) & INDX_MASK) | MCI_CPSM_ENABLED;\r
- if (MmcCmd & MMC_CMD_WAIT_RESPONSE) {\r
- Cmd |= MCI_CPSM_WAIT_RESPONSE;\r
- }\r
-\r
- if (MmcCmd & MMC_CMD_LONG_RESPONSE) {\r
- Cmd |= MCI_CPSM_LONG_RESPONSE;\r
- }\r
-\r
- // Clear Status register static flags\r
- MmioWrite32(MCI_CLEAR_STATUS_REG,0x7FF);\r
-\r
- //Write to command argument register\r
- MmioWrite32(MCI_ARGUMENT_REG,Argument);\r
-\r
- //Write to command register\r
- MmioWrite32(MCI_COMMAND_REG,Cmd);\r
-\r
- if (Cmd & MCI_CPSM_WAIT_RESPONSE) {\r
- Status = MmioRead32(MCI_STATUS_REG);\r
- while (!(Status & (MCI_STATUS_CMD_RESPEND | MCI_STATUS_CMD_CMDCRCFAIL | MCI_STATUS_CMD_CMDTIMEOUT | MCI_STATUS_CMD_START_BIT_ERROR))) {\r
- Status = MmioRead32(MCI_STATUS_REG);\r
- }\r
-\r
- if ((Status & MCI_STATUS_CMD_START_BIT_ERROR)) {\r
- DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));\r
- RetVal = EFI_NO_RESPONSE;\r
- goto Exit;\r
- } else if ((Status & MCI_STATUS_CMD_CMDTIMEOUT)) {\r
- //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));\r
- RetVal = EFI_TIMEOUT;\r
- goto Exit;\r
- } else if ((!(MmcCmd & MMC_CMD_NO_CRC_RESPONSE)) && (Status & MCI_STATUS_CMD_CMDCRCFAIL)) {\r
- // The CMD1 and response type R3 do not contain CRC. We should ignore the CRC failed Status.\r
- RetVal = EFI_CRC_ERROR;\r
- goto Exit;\r
- } else {\r
- RetVal = EFI_SUCCESS;\r
- goto Exit;\r
- }\r
- } else {\r
- Status = MmioRead32(MCI_STATUS_REG);\r
- while (!(Status & (MCI_STATUS_CMD_SENT | MCI_STATUS_CMD_CMDCRCFAIL | MCI_STATUS_CMD_CMDTIMEOUT| MCI_STATUS_CMD_START_BIT_ERROR))) {\r
- Status = MmioRead32(MCI_STATUS_REG);\r
- }\r
-\r
- if ((Status & MCI_STATUS_CMD_START_BIT_ERROR)) {\r
- DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));\r
- RetVal = EFI_NO_RESPONSE;\r
- goto Exit;\r
- } else if ((Status & MCI_STATUS_CMD_CMDTIMEOUT)) {\r
- //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));\r
- RetVal = EFI_TIMEOUT;\r
- goto Exit;\r
- } else\r
- if ((!(MmcCmd & MMC_CMD_NO_CRC_RESPONSE)) && (Status & MCI_STATUS_CMD_CMDCRCFAIL)) {\r
- // The CMD1 does not contain CRC. We should ignore the CRC failed Status.\r
- RetVal = EFI_CRC_ERROR;\r
- goto Exit;\r
- } else {\r
- RetVal = EFI_SUCCESS;\r
- goto Exit;\r
- }\r
- }\r
-\r
-Exit:\r
- //Disable Command Path\r
- CmdCtrlReg = MmioRead32(MCI_COMMAND_REG);\r
- MmioWrite32(MCI_COMMAND_REG, (CmdCtrlReg & ~MCI_CPSM_ENABLED));\r
- return RetVal;\r
-}\r
-\r
-EFI_STATUS\r
-MciReceiveResponse (\r
- IN MMC_RESPONSE_TYPE Type,\r
- IN UINT32* Buffer\r
- )\r
-{\r
- if (Buffer == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if ((Type == MMC_RESPONSE_TYPE_R1) || (Type == MMC_RESPONSE_TYPE_R1b) ||\r
- (Type == MMC_RESPONSE_TYPE_R3) || (Type == MMC_RESPONSE_TYPE_R6) ||\r
- (Type == MMC_RESPONSE_TYPE_R7))\r
- {\r
- Buffer[0] = MmioRead32(MCI_RESPONSE0_REG);\r
- Buffer[1] = MmioRead32(MCI_RESPONSE1_REG);\r
- } else if (Type == MMC_RESPONSE_TYPE_R2) {\r
- Buffer[0] = MmioRead32(MCI_RESPONSE0_REG);\r
- Buffer[1] = MmioRead32(MCI_RESPONSE1_REG);\r
- Buffer[2] = MmioRead32(MCI_RESPONSE2_REG);\r
- Buffer[3] = MmioRead32(MCI_RESPONSE3_REG);\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-MciReadBlockData (\r
- IN EFI_LBA Lba,\r
- IN UINTN Length,\r
- IN UINT32* Buffer\r
- )\r
-{\r
- UINTN Loop;\r
- UINTN Finish;\r
- UINTN Status;\r
- EFI_STATUS RetVal;\r
- UINTN DataCtrlReg;\r
-\r
- RetVal = EFI_SUCCESS;\r
-\r
- // Read data from the RX FIFO\r
- Loop = 0;\r
- Finish = MMCI0_BLOCKLEN / 4;\r
- do {\r
- // Read the Status flags\r
- Status = MmioRead32(MCI_STATUS_REG);\r
-\r
- // Do eight reads if possible else a single read\r
- if (Status & MCI_STATUS_CMD_RXFIFOHALFFULL) {\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- } else if (Status & MCI_STATUS_CMD_RXDATAAVAILBL) {\r
- Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
- Loop++;\r
- } else {\r
- //Check for error conditions and timeouts\r
- if(Status & MCI_STATUS_CMD_DATATIMEOUT) {\r
- DEBUG ((EFI_D_ERROR, "MciReadBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
- RetVal = EFI_TIMEOUT;\r
- break;\r
- } else if(Status & MCI_STATUS_CMD_DATACRCFAIL) {\r
- DEBUG ((EFI_D_ERROR, "MciReadBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
- RetVal = EFI_CRC_ERROR;\r
- break;\r
- } else if(Status & MCI_STATUS_CMD_START_BIT_ERROR) {\r
- DEBUG ((EFI_D_ERROR, "MciReadBlockData(): Start-bit Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
- RetVal = EFI_NO_RESPONSE;\r
- break;\r
- }\r
- }\r
- //clear RX over run flag\r
- if(Status & MCI_STATUS_CMD_RXOVERRUN) {\r
- MmioWrite32(MCI_CLEAR_STATUS_REG, MCI_STATUS_CMD_RXOVERRUN);\r
- }\r
- } while ((Loop < Finish));\r
-\r
- //Clear Status flags\r
- MmioWrite32(MCI_CLEAR_STATUS_REG, 0x7FF);\r
-\r
- //Disable Data path\r
- DataCtrlReg = MmioRead32(MCI_DATA_CTL_REG);\r
- MmioWrite32(MCI_DATA_CTL_REG, (DataCtrlReg & 0xFE));\r
-\r
- return RetVal;\r
-}\r
-\r
-EFI_STATUS\r
-MciWriteBlockData (\r
- IN EFI_LBA Lba,\r
- IN UINTN Length,\r
- IN UINT32* Buffer\r
- )\r
-{\r
- UINTN Loop;\r
- UINTN Finish;\r
- UINTN Timer;\r
- UINTN Status;\r
- EFI_STATUS RetVal;\r
- UINTN DataCtrlReg;\r
-\r
- RetVal = EFI_SUCCESS;\r
-\r
- // Write the data to the TX FIFO\r
- Loop = 0;\r
- Finish = MMCI0_BLOCKLEN / 4;\r
- Timer = MMCI0_TIMEOUT * 100;\r
- do {\r
- // Read the Status flags\r
- Status = MmioRead32(MCI_STATUS_REG);\r
-\r
- // Do eight writes if possible else a single write\r
- if (Status & MCI_STATUS_CMD_TXFIFOHALFEMPTY) {\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- } else if ((Status & MCI_STATUS_CMD_TXFIFOEMPTY)) {\r
- MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
- Loop++;\r
- } else {\r
- //Check for error conditions and timeouts\r
- if(Status & MCI_STATUS_CMD_DATATIMEOUT) {\r
- DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
- RetVal = EFI_TIMEOUT;\r
- goto Exit;\r
- } else if(Status & MCI_STATUS_CMD_DATACRCFAIL) {\r
- DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
- RetVal = EFI_CRC_ERROR;\r
- goto Exit;\r
- } else if(Status & MCI_STATUS_CMD_TX_UNDERRUN) {\r
- DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TX buffer Underrun! Response:0x%X Status:0x%x, Number of bytes written 0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status, Loop));\r
- RetVal = EFI_BUFFER_TOO_SMALL;\r
- ASSERT(0);\r
- goto Exit;\r
- }\r
- }\r
- } while (Loop < Finish);\r
-\r
- // Wait for FIFO to drain\r
- Timer = MMCI0_TIMEOUT * 60;\r
- Status = MmioRead32(MCI_STATUS_REG);\r
-#ifndef USE_STREAM\r
- // Single block\r
- while (((Status & MCI_STATUS_CMD_TXDONE) != MCI_STATUS_CMD_TXDONE) && Timer) {\r
-#else\r
- // Stream\r
- while (((Status & MCI_STATUS_CMD_DATAEND) != MCI_STATUS_CMD_DATAEND) && Timer) {\r
-#endif\r
- NanoSecondDelay(10);\r
- Status = MmioRead32(MCI_STATUS_REG);\r
- Timer--;\r
- }\r
-\r
- if(Timer == 0) {\r
- DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): Data End timeout Number of bytes written 0x%x\n",Loop));\r
- ASSERT(Timer > 0);\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- //Clear Status flags\r
- MmioWrite32(MCI_CLEAR_STATUS_REG, 0x7FF);\r
- if (Timer == 0) {\r
- RetVal = EFI_TIMEOUT;\r
- }\r
-\r
-Exit:\r
- //Disable Data path\r
- DataCtrlReg = MmioRead32(MCI_DATA_CTL_REG);\r
- MmioWrite32(MCI_DATA_CTL_REG, (DataCtrlReg & 0xFE));\r
- return RetVal;\r
-}\r
-\r
-EFI_STATUS\r
-MciNotifyState (\r
- IN MMC_STATE State\r
- )\r
-{\r
- UINT32 Data32;\r
-\r
- switch(State) {\r
- case MmcInvalidState:\r
- ASSERT(0);\r
- break;\r
- case MmcHwInitializationState:\r
- // If device already turn on then restart it\r
- Data32 = MmioRead32(MCI_POWER_CONTROL_REG);\r
- if ((Data32 & 0x2) == MCI_POWER_UP) {\r
- MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOff MCI");\r
-\r
- // Turn off\r
- MmioWrite32(MCI_CLOCK_CONTROL_REG, 0);\r
- MmioWrite32(MCI_POWER_CONTROL_REG, 0);\r
- MicroSecondDelay(100);\r
- }\r
-\r
- MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOn MCI");\r
- // Setup clock\r
- // - 0x1D = 29 => should be the clock divider to be less than 400kHz at MCLK = 24Mhz\r
- MmioWrite32(MCI_CLOCK_CONTROL_REG,0x1D | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE);\r
- //MmioWrite32(MCI_CLOCK_CONTROL_REG,0x1D | MCI_CLOCK_ENABLE);\r
-\r
- // Set the voltage\r
- MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_OPENDRAIN | (15<<2));\r
- MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_UP);\r
- MicroSecondDelay(10);\r
- MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_ON);\r
- MicroSecondDelay(100);\r
-\r
- // Set Data Length & Data Timer\r
- MmioWrite32(MCI_DATA_TIMER_REG,0xFFFFF);\r
- MmioWrite32(MCI_DATA_LENGTH_REG,8);\r
-\r
- ASSERT((MmioRead32(MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON);\r
- break;\r
- case MmcIdleState:\r
- MCI_TRACE("MciNotifyState(MmcIdleState)");\r
- break;\r
- case MmcReadyState:\r
- MCI_TRACE("MciNotifyState(MmcReadyState)");\r
- break;\r
- case MmcIdentificationState:\r
- MCI_TRACE("MciNotifyState(MmcIdentificationState)");\r
- break;\r
- case MmcStandByState:{\r
- volatile UINT32 PwrCtrlReg;\r
- MCI_TRACE("MciNotifyState(MmcStandByState)");\r
-\r
- // Enable MCICMD push-pull drive\r
- PwrCtrlReg = MmioRead32(MCI_POWER_CONTROL_REG);\r
- //Disable Open Drain output\r
- PwrCtrlReg &=~(MCI_POWER_OPENDRAIN);\r
- MmioWrite32(MCI_POWER_CONTROL_REG,PwrCtrlReg);\r
-\r
- // Set MMCI0 clock to 4MHz (24MHz may be possible with cache enabled)\r
- //\r
- // Note: Increasing clock speed causes TX FIFO under-run errors.\r
- // So careful when optimising this driver for higher performance.\r
- //\r
- MmioWrite32(MCI_CLOCK_CONTROL_REG,0x02 | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE);\r
- // Set MMCI0 clock to 24MHz (by bypassing the divider)\r
- //MmioWrite32(MCI_CLOCK_CONTROL_REG,MCI_CLOCK_BYPASS | MCI_CLOCK_ENABLE);\r
- break;\r
- }\r
- case MmcTransferState:\r
- //MCI_TRACE("MciNotifyState(MmcTransferState)");\r
- break;\r
- case MmcSendingDataState:\r
- MCI_TRACE("MciNotifyState(MmcSendingDataState)");\r
- break;\r
- case MmcReceiveDataState:\r
- MCI_TRACE("MciNotifyState(MmcReceiveDataState)");\r
- break;\r
- case MmcProgrammingState:\r
- MCI_TRACE("MciNotifyState(MmcProgrammingState)");\r
- break;\r
- case MmcDisconnectState:\r
- MCI_TRACE("MciNotifyState(MmcDisconnectState)");\r
- break;\r
- default:\r
- ASSERT(0);\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_GUID mPL180MciDevicePathGuid = EFI_CALLER_ID_GUID;\r
-\r
-EFI_STATUS\r
-MciBuildDevicePath (\r
- IN EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
- )\r
-{\r
- EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;\r
-\r
- NewDevicePathNode = CreateDeviceNode(HARDWARE_DEVICE_PATH,HW_VENDOR_DP,sizeof(VENDOR_DEVICE_PATH));\r
- CopyGuid(&((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid,&mPL180MciDevicePathGuid);\r
-\r
- *DevicePath = NewDevicePathNode;\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_MMC_HOST_PROTOCOL gMciHost = {\r
- MciIsCardPresent,\r
- MciIsReadOnly,\r
- MciBuildDevicePath,\r
- MciNotifyState,\r
- MciSendCommand,\r
- MciReceiveResponse,\r
- MciReadBlockData,\r
- MciWriteBlockData\r
-};\r
-\r
-EFI_STATUS\r
-PL180MciDxeInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_HANDLE Handle = NULL;\r
-\r
- MCI_TRACE("PL180MciDxeInitialize()");\r
-\r
- //Publish Component Name, BlockIO protocol interfaces\r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
- &Handle, \r
- &gEfiMmcHostProtocolGuid, &gMciHost,\r
- NULL\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-/** @file\r
- Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.\r
-\r
- Copyright (c) 2011, ARM Limited. All rights reserved.\r
- \r
- This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-**/\r
-\r
-#ifndef __PL180_MCI_H\r
-#define __PL180_MCI_H\r
-\r
-#include <Uefi.h>\r
-\r
-#include <Protocol/MmcHost.h>\r
-\r
-#include <Library/UefiLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/TimerLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#define PL180_MCI_DXE_VERSION 0x10\r
-\r
-#define MCI_SYSCTL FixedPcdGet32(PcdPL180MciBaseAddress)\r
-\r
-#define MCI_POWER_CONTROL_REG (MCI_SYSCTL+0x000)\r
-#define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL+0x004)\r
-#define MCI_ARGUMENT_REG (MCI_SYSCTL+0x008)\r
-#define MCI_COMMAND_REG (MCI_SYSCTL+0x00C)\r
-#define MCI_RESPCMD_REG (MCI_SYSCTL+0x010)\r
-#define MCI_RESPONSE0_REG (MCI_SYSCTL+0x014)\r
-#define MCI_RESPONSE1_REG (MCI_SYSCTL+0x018)\r
-#define MCI_RESPONSE2_REG (MCI_SYSCTL+0x01C)\r
-#define MCI_RESPONSE3_REG (MCI_SYSCTL+0x020)\r
-#define MCI_DATA_TIMER_REG (MCI_SYSCTL+0x024)\r
-#define MCI_DATA_LENGTH_REG (MCI_SYSCTL+0x028)\r
-#define MCI_DATA_CTL_REG (MCI_SYSCTL+0x02C)\r
-#define MCI_DATA_COUNTER (MCI_SYSCTL+0x030)\r
-#define MCI_STATUS_REG (MCI_SYSCTL+0x034)\r
-#define MCI_CLEAR_STATUS_REG (MCI_SYSCTL+0x038)\r
-#define MCI_INT0_MASK_REG (MCI_SYSCTL+0x03C)\r
-#define MCI_INT1_MASK_REG (MCI_SYSCTL+0x040)\r
-#define MCI_FIFOCOUNT_REG (MCI_SYSCTL+0x048)\r
-#define MCI_FIFO_REG (MCI_SYSCTL+0x080)\r
-\r
-#define MCI_POWER_UP 0x2\r
-#define MCI_POWER_ON 0x3\r
-#define MCI_POWER_OPENDRAIN (1 << 6)\r
-#define MCI_POWER_ROD (1 << 7)\r
-\r
-#define MCI_CLOCK_ENABLE 0x100\r
-#define MCI_CLOCK_POWERSAVE 0x200\r
-#define MCI_CLOCK_BYPASS 0x400\r
-\r
-#define MCI_STATUS_CMD_CMDCRCFAIL 0x1\r
-#define MCI_STATUS_CMD_DATACRCFAIL 0x2\r
-#define MCI_STATUS_CMD_CMDTIMEOUT 0x4\r
-#define MCI_STATUS_CMD_DATATIMEOUT 0x8\r
-#define MCI_STATUS_CMD_TX_UNDERRUN 0x10\r
-#define MCI_STATUS_CMD_RXOVERRUN 0x20\r
-#define MCI_STATUS_CMD_RESPEND 0x40\r
-#define MCI_STATUS_CMD_SENT 0x80\r
-#define MCI_STATUS_CMD_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)\r
-#define MCI_STATUS_CMD_DATAEND 0x000100 // Command Status - Data end\r
-#define MCI_STATUS_CMD_START_BIT_ERROR 0x000200\r
-#define MCI_STATUS_CMD_DATABLOCKEND 0x000400 // Command Status - Data end\r
-#define MCI_STATUS_CMD_ACTIVE 0x800\r
-#define MCI_STATUS_CMD_RXACTIVE (1 << 13)\r
-#define MCI_STATUS_CMD_RXFIFOHALFFULL 0x008000\r
-#define MCI_STATUS_CMD_RXFIFOEMPTY 0x080000\r
-#define MCI_STATUS_CMD_RXDATAAVAILBL (1 << 21)\r
-#define MCI_STATUS_CMD_TXACTIVE (1 << 12)\r
-#define MCI_STATUS_CMD_TXFIFOFULL (1 << 16)\r
-#define MCI_STATUS_CMD_TXFIFOHALFEMPTY (1 << 14)\r
-#define MCI_STATUS_CMD_TXFIFOEMPTY (1 << 18)\r
-#define MCI_STATUS_CMD_TXDATAAVAILBL (1 << 20)\r
-\r
-#define MCI_DATACTL_ENABLE 1\r
-#define MCI_DATACTL_CONT_TO_CARD 0\r
-#define MCI_DATACTL_CARD_TO_CONT 2\r
-#define MCI_DATACTL_BLOCK_TRANS 0\r
-#define MCI_DATACTL_STREAM_TRANS 4\r
-#define MCI_DATACTL_DMA_ENABLE (1 << 3)\r
-\r
-#define INDX_MASK 0x3F\r
-\r
-#define MCI_CPSM_ENABLED (1 << 10)\r
-#define MCI_CPSM_WAIT_RESPONSE (1 << 6)\r
-#define MCI_CPSM_LONG_RESPONSE (1 << 7)\r
-\r
-#define MCI_TRACE(txt) DEBUG((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-MciGetDriverName (\r
- IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
- IN CHAR8 *Language,\r
- OUT CHAR16 **DriverName\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-MciGetControllerName (\r
- IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
- IN EFI_HANDLE ControllerHandle,\r
- IN EFI_HANDLE ChildHandle OPTIONAL,\r
- IN CHAR8 *Language,\r
- OUT CHAR16 **ControllerName\r
- );\r
-\r
-#endif\r
+++ /dev/null
-#/** @file\r
-# INF file for the MMC Host Protocol implementation for the ARM PrimeCell PL180.\r
-#\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL180MciDxe\r
- FILE_GUID = 09831032-6fa3-4484-af4f-0a000a8d3a82\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
-\r
- ENTRY_POINT = PL180MciDxeInitialize\r
-\r
-[Sources.common]\r
- PL180Mci.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- UefiLib\r
- UefiDriverEntryPoint\r
- BaseMemoryLib\r
- ArmLib\r
- IoLib\r
- TimerLib\r
-\r
-[Protocols]\r
- gEfiCpuArchProtocolGuid\r
- gEfiDevicePathProtocolGuid\r
- gEfiMmcHostProtocolGuid\r
- \r
-[Pcd]\r
- gArmTokenSpaceGuid.PcdPL180SysMciRegAddress\r
- gArmTokenSpaceGuid.PcdPL180MciBaseAddress\r
- \r
-[Depex]\r
- TRUE\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-*\r
-**/\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-#define PL301_QOS_TIDEMARK_MI_0 0x400\r
-#define PL301_QOS_ACCESSCONTROL_MI_0 0x404\r
-\r
-#define PL301_QOS_TIDEMARK_MI_1 0x420\r
-#define PL301_QOS_ACCESSCONTROL_MI_1 0x424\r
-\r
-#define PL301_QOS_TIDEMARK_MI_2 0x440\r
-#define PL301_QOS_ACCESSCONTROL_MI_2 0x444\r
-\r
-#define PL301_AR_ARB_MI_0 0x408\r
-#define PL301_AW_ARB_MI_0 0x40C\r
-\r
-#define PL301_AR_ARB_MI_1 0x428\r
-#define PL301_AW_ARB_MI_1 0x42C\r
-\r
-#define PL301_AR_ARB_MI_2 0x448\r
-#define PL301_AW_ARB_MI_2 0x44C\r
-\r
-#define PL301_MI_1_OFFSET 0x20\r
-#define PL301_MI_2_OFFSET 0x40\r
-#define PL301_MI_3_OFFSET 0x60\r
-#define PL301_MI_4_OFFSET 0x80\r
-#define PL301_MI_5_OFFSET 0xa0\r
-\r
-#define V2P_CA9_FAXI_MI0_TIDEMARK_VAL 0x6\r
-#define V2P_CA9_FAXI_MI0_ACCESSCNTRL_VAL 0x1\r
-\r
-#define V2P_CA9_FAXI_MI1_TIDEMARK_VAL 0x6\r
-#define V2P_CA9_FAXI_MI1_ACCESSCNTRL_VAL 0x1\r
-\r
-#define V2P_CA9_FAXI_MI2_TIDEMARK_VAL 0x6\r
-#define V2P_CA9_FAXI_MI2_ACCESSCNTRL_VAL 0x1\r
-\r
-\r
-#define FAxiWriteReg(reg,val) MmioWrite32(FAxiBase + reg, val)\r
-#define FAxiReadReg(reg) MmioRead32(FAxiBase + reg)\r
-\r
-// IN FAxiBase\r
-// Initialize PL301 Dynamic Memory Controller\r
-VOID PL301AxiInit(UINTN FAxiBase) {\r
- // Configure Tidemark Register for Master Port 0 (MI 0)\r
- FAxiWriteReg(PL301_QOS_TIDEMARK_MI_0, V2P_CA9_FAXI_MI0_TIDEMARK_VAL);\r
-\r
- // Configure the Access Control Register (MI 0)\r
- FAxiWriteReg(PL301_QOS_ACCESSCONTROL_MI_0, V2P_CA9_FAXI_MI0_ACCESSCNTRL_VAL);\r
-\r
- // MP0 \r
- // Set priority for Read\r
- FAxiWriteReg(PL301_AR_ARB_MI_0, 0x00000100);\r
- FAxiWriteReg(PL301_AR_ARB_MI_0, 0x01000200);\r
- FAxiWriteReg(PL301_AR_ARB_MI_0, 0x02000200);\r
- FAxiWriteReg(PL301_AR_ARB_MI_0, 0x03000200);\r
- FAxiWriteReg(PL301_AR_ARB_MI_0, 0x04000200);\r
- \r
- // Set priority for Write\r
- FAxiWriteReg(PL301_AW_ARB_MI_0, 0x00000100);\r
- FAxiWriteReg(PL301_AW_ARB_MI_0, 0x01000200);\r
- FAxiWriteReg(PL301_AW_ARB_MI_0, 0x02000200);\r
- FAxiWriteReg(PL301_AW_ARB_MI_0, 0x03000200);\r
- FAxiWriteReg(PL301_AW_ARB_MI_0, 0x04000200);\r
-\r
- // MP1\r
- // Set priority for Read\r
- FAxiWriteReg(PL301_AR_ARB_MI_1, 0x00000100);\r
- FAxiWriteReg(PL301_AR_ARB_MI_1, 0x01000200);\r
- FAxiWriteReg(PL301_AR_ARB_MI_1, 0x02000200);\r
- FAxiWriteReg(PL301_AR_ARB_MI_1, 0x03000200);\r
- FAxiWriteReg(PL301_AR_ARB_MI_1, 0x04000200);\r
-\r
- // Set priority for Write\r
- FAxiWriteReg(PL301_AW_ARB_MI_1, 0x00000100);\r
- FAxiWriteReg(PL301_AW_ARB_MI_1, 0x01000200);\r
- FAxiWriteReg(PL301_AW_ARB_MI_1, 0x02000200);\r
- FAxiWriteReg(PL301_AW_ARB_MI_1, 0x03000200);\r
- FAxiWriteReg(PL301_AW_ARB_MI_1, 0x04000200);\r
-\r
- // MP2\r
- // Set priority for Read\r
- FAxiWriteReg(PL301_AR_ARB_MI_2, 0x00000100);\r
- FAxiWriteReg(PL301_AR_ARB_MI_2, 0x01000100);\r
- FAxiWriteReg(PL301_AR_ARB_MI_2, 0x02000100);\r
- FAxiWriteReg(PL301_AR_ARB_MI_2, 0x03000100);\r
- FAxiWriteReg(PL301_AR_ARB_MI_2, 0x04000100);\r
- \r
- // Set priority for Write\r
- FAxiWriteReg(PL301_AW_ARB_MI_2, 0x00000100);\r
- FAxiWriteReg(PL301_AW_ARB_MI_2, 0x01000200);\r
- FAxiWriteReg(PL301_AW_ARB_MI_2, 0x02000200);\r
- FAxiWriteReg(PL301_AW_ARB_MI_2, 0x03000200);\r
- FAxiWriteReg(PL301_AW_ARB_MI_2, 0x04000200);\r
-}\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL301AxiSec\r
- FILE_GUID = 2ea84160-aba0-11df-9896-0002a5d5c51b\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PL301AxiLib\r
-\r
-[Sources]\r
- PL301Axi.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[FixedPcd]\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-*\r
-**/\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/ArmLib.h>\r
-#include <Drivers/PL310L2Cache.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#define L2x0WriteReg(reg,val) MmioWrite32(PcdGet32(PcdL2x0ControllerBase) + reg, val)\r
-#define L2x0ReadReg(reg) MmioRead32(PcdGet32(PcdL2x0ControllerBase) + reg)\r
-\r
-// Initialize PL320 L2 Cache Controller\r
-VOID\r
-L2x0CacheInit (\r
- IN UINTN L2x0Base,\r
- IN UINT32 L2x0TagLatencies,\r
- IN UINT32 L2x0DataLatencies,\r
- IN UINT32 L2x0AuxValue,\r
- IN UINT32 L2x0AuxMask,\r
- IN BOOLEAN CacheEnabled\r
- )\r
-{\r
- UINT32 Data;\r
- UINT32 Revision;\r
- UINT32 Aux;\r
- UINT32 PfCtl;\r
- UINT32 PwrCtl;\r
-\r
- // Check if L2x0 is present and is an ARM implementation\r
- Data = L2x0ReadReg(L2X0_CACHEID);\r
- if ((Data >> 24) != L2X0_CACHEID_IMPLEMENTER_ARM) {\r
- ASSERT(0);\r
- return;\r
- }\r
-\r
- // Check if L2x0 is PL310\r
- if (((Data >> 6) & 0xF) != L2X0_CACHEID_PARTNUM_PL310) {\r
- ASSERT(0);\r
- return;\r
- }\r
-\r
- // RTL release\r
- Revision = Data & 0x3F;\r
-\r
- // Check if L2x0 is already enabled then we disable it\r
- Data = L2x0ReadReg(L2X0_CTRL);\r
- if (Data & L2X0_CTRL_ENABLED) {\r
- L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_DISABLED);\r
- }\r
-\r
- //\r
- // Set up global configurations\r
- //\r
-\r
- // Auxiliary register: Non-secure interrupt access Control + Event monitor bus enable + SBO\r
- Aux = L2X0_AUXCTRL_NSAC | L2X0_AUXCTRL_EM | L2X0_AUXCTRL_SBO;\r
- // Use AWCACHE attributes for WA\r
- Aux |= L2x0_AUXCTRL_AW_AWCACHE;\r
- // Use default Size\r
- Data = L2x0ReadReg(L2X0_AUXCTRL);\r
- Aux |= Data & L2X0_AUXCTRL_WAYSIZE_MASK;\r
- // Use default associativity\r
- Aux |= Data & L2X0_AUXCTRL_ASSOCIATIVITY;\r
- // Enabled I & D Prefetch\r
- Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;\r
-\r
- if (Revision >= 5) {\r
- // Prefetch Offset Register\r
- PfCtl = L2x0ReadReg(L2X0_PFCTRL);\r
- // - Prefetch increment set to 0\r
- // - Prefetch dropping off\r
- // - Double linefills off\r
- L2x0WriteReg(L2X0_PFCTRL, PfCtl);\r
-\r
- // Power Control Register - L2X0_PWRCTRL\r
- PwrCtl = L2x0ReadReg(L2X0_PWRCTRL);\r
- // - Standby when idle off\r
- // - Dynamic clock gating off\r
- // - Nc,NC-shared dropping off\r
- L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);\r
- }\r
-\r
- if (Revision >= 2) {\r
- L2x0WriteReg(L230_TAG_LATENCY, L2x0TagLatencies);\r
- L2x0WriteReg(L230_DATA_LATENCY, L2x0DataLatencies);\r
- } else {\r
- // PL310 old style latency is not supported yet\r
- ASSERT(0);\r
- }\r
-\r
- // Set the platform specific values\r
- Aux = (Aux & L2x0AuxMask) | L2x0AuxValue;\r
-\r
- // Write Auxiliary value\r
- L2x0WriteReg(L2X0_AUXCTRL, Aux);\r
-\r
- //\r
- // Invalidate all entries in cache\r
- //\r
- L2x0WriteReg(L2X0_INVWAY, 0xffff);\r
- // Poll cache maintenance register until invalidate operation is complete\r
- while(L2x0ReadReg(L2X0_INVWAY) & 0xffff);\r
-\r
- // Write to the Lockdown D and Lockdown I Register 9 if required\r
- // - Not required\r
-\r
- // Clear any residual raw interrupts\r
- L2x0WriteReg(L2X0_INTCLEAR, 0x1FF);\r
-\r
- // Enable the cache\r
- if (CacheEnabled) {\r
- L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_ENABLED);\r
- }\r
-}\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL310L2Cache\r
- FILE_GUID = 16ad4fe0-b5b1-11df-8cbf-0002a5d5c51b\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = L2X0CacheLib\r
-\r
-[Sources]\r
- PL310L2Cache.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdL2x0ControllerBase\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-*\r
-**/\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Drivers/PL341Dmc.h>\r
-\r
-// Macros for writing to DDR2 controller.\r
-#define DmcWriteReg(reg,val) MmioWrite32(DmcBase + reg, val)\r
-#define DmcReadReg(reg) MmioRead32(DmcBase + reg)\r
-\r
-// Macros for writing/reading to DDR2 PHY controller\r
-#define DmcPhyWriteReg(reg,val) MmioWrite32(DmcPhyBase + reg, val)\r
-#define DmcPhyReadReg(reg) MmioRead32(DmcPhyBase + reg)\r
-\r
-// Initialise PL341 Dynamic Memory Controller\r
-VOID\r
-PL341DmcInit (\r
- IN PL341_DMC_CONFIG *DmcConfig\r
- )\r
-{\r
- UINTN DmcBase;\r
- UINTN Index;\r
- UINT32 Chip;\r
-\r
- DmcBase = DmcConfig->base;\r
-\r
- // Set config mode\r
- DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_CONFIGURE);\r
-\r
- //\r
- // Setup the QoS AXI ID bits\r
- //\r
- if (DmcConfig->HasQos) {\r
- // CLCD AXIID = 000\r
- DmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);\r
-\r
- // Default disable QoS\r
- DmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- DmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
- }\r
-\r
- //\r
- // Initialise memory controlller\r
- //\r
- DmcWriteReg(DMC_REFRESH_PRD_REG, DmcConfig->refresh_prd);\r
- DmcWriteReg(DMC_CAS_LATENCY_REG, DmcConfig->cas_latency);\r
- DmcWriteReg(DMC_WRITE_LATENCY_REG, DmcConfig->write_latency);\r
- DmcWriteReg(DMC_T_MRD_REG, DmcConfig->t_mrd);\r
- DmcWriteReg(DMC_T_RAS_REG, DmcConfig->t_ras);\r
- DmcWriteReg(DMC_T_RC_REG, DmcConfig->t_rc);\r
- DmcWriteReg(DMC_T_RCD_REG, DmcConfig->t_rcd);\r
- DmcWriteReg(DMC_T_RFC_REG, DmcConfig->t_rfc);\r
- DmcWriteReg(DMC_T_RP_REG, DmcConfig->t_rp);\r
- DmcWriteReg(DMC_T_RRD_REG, DmcConfig->t_rrd);\r
- DmcWriteReg(DMC_T_WR_REG, DmcConfig->t_wr);\r
- DmcWriteReg(DMC_T_WTR_REG, DmcConfig->t_wtr);\r
- DmcWriteReg(DMC_T_XP_REG, DmcConfig->t_xp);\r
- DmcWriteReg(DMC_T_XSR_REG, DmcConfig->t_xsr);\r
- DmcWriteReg(DMC_T_ESR_REG, DmcConfig->t_esr);\r
- DmcWriteReg(DMC_T_FAW_REG, DmcConfig->t_faw);\r
- DmcWriteReg(DMC_T_WRLAT_DIFF, DmcConfig->t_wdata_en);\r
- DmcWriteReg(DMC_T_RDATA_EN, DmcConfig->t_data_en);\r
-\r
- //\r
- // Initialise PL341 Mem Config Registers\r
- //\r
-\r
- // Set PL341 Memory Config\r
- DmcWriteReg(DMC_MEMORY_CONFIG_REG, DmcConfig->MemoryCfg);\r
-\r
- // Set PL341 Memory Config 2\r
- DmcWriteReg(DMC_MEMORY_CFG2_REG, DmcConfig->MemoryCfg2);\r
-\r
- // Set PL341 Chip Select <n>\r
- DmcWriteReg(DMC_CHIP_0_CFG_REG, DmcConfig->ChipCfg0);\r
- DmcWriteReg(DMC_CHIP_1_CFG_REG, DmcConfig->ChipCfg1);\r
- DmcWriteReg(DMC_CHIP_2_CFG_REG, DmcConfig->ChipCfg2);\r
- DmcWriteReg(DMC_CHIP_3_CFG_REG, DmcConfig->ChipCfg3);\r
-\r
- // Delay\r
- for (Index = 0; Index < 10; Index++) {\r
- DmcReadReg(DMC_STATUS_REG);\r
- }\r
-\r
- // Set PL341 Memory Config 3\r
- DmcWriteReg(DMC_MEMORY_CFG3_REG, DmcConfig->MemoryCfg3);\r
-\r
- if (DmcConfig->IsUserCfg) {\r
- //\r
- // Set Test Chip PHY Registers via PL341 User Config Reg\r
- // Note that user_cfgX registers are Write Only\r
- //\r
- // DLL Freq set = 250MHz - 266MHz\r
- //\r
- DmcWriteReg(DMC_USER_0_CFG_REG, DmcConfig->User0Cfg);\r
-\r
- // user_config2\r
- // ------------\r
- // Set defaults before calibrating the DDR2 buffer impendence\r
- // - Disable ODT\r
- // - Default drive strengths\r
- DmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);\r
-\r
- //\r
- // Auto calibrate the DDR2 buffers impendence\r
- //\r
- while (!(DmcReadReg(DMC_USER_STATUS_REG) & 0x100));\r
-\r
- // Set the output driven strength\r
- DmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 | DmcConfig->User2Cfg);\r
-\r
- //\r
- // Set PL341 Feature Control Register\r
- //\r
- // Disable early BRESP - use to optimise CLCD performance\r
- DmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);\r
- }\r
-\r
- //\r
- // Config memories\r
- //\r
- for (Chip = 0; Chip < DmcConfig->MaxChip; Chip++) {\r
- // Send nop\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_NOP);\r
-\r
- // Pre-charge all\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
-\r
- // Delay\r
- for (Index = 0; Index < 10; Index++) {\r
- DmcReadReg(DMC_STATUS_REG);\r
- }\r
-\r
- // Set (EMR2) extended mode register 2\r
- DmcWriteReg(DMC_DIRECT_CMD_REG,\r
- DMC_DIRECT_CMD_CHIP_ADDR(Chip) |\r
- DMC_DIRECT_CMD_BANKADDR(2) |\r
- DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
-\r
- // Set (EMR3) extended mode register 3\r
- DmcWriteReg(DMC_DIRECT_CMD_REG,\r
- DMC_DIRECT_CMD_CHIP_ADDR(Chip) |\r
- DMC_DIRECT_CMD_BANKADDR(3) |\r
- DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
-\r
- //\r
- // Set (EMR) Extended Mode Register\r
- //\r
- // Put into OCD default state\r
- DmcWriteReg(DMC_DIRECT_CMD_REG,DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_BANKADDR(1) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
-\r
- //\r
- // Set (MR) mode register - With DLL reset\r
- //\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg | DDR2_MR_DLL_RESET);\r
-\r
- // Pre-charge all\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
- // Auto-refresh\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
- // Auto-refresh\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
-\r
- //\r
- // Set (MR) mode register - Without DLL reset\r
- //\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg);\r
-\r
- // Delay\r
- for (Index = 0; Index < 10; Index++) {\r
- DmcReadReg(DMC_STATUS_REG);\r
- }\r
-\r
- //\r
- // Set (EMR) extended mode register - Enable OCD defaults\r
- //\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |\r
- (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);\r
-\r
- // Delay\r
- for (Index = 0; Index < 10; Index++) {\r
- DmcReadReg(DMC_STATUS_REG);\r
- }\r
-\r
- // Set (EMR) extended mode register - OCD Exit\r
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |\r
- (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);\r
- }\r
-\r
- // Move DDR2 Controller to Ready state by issueing GO command\r
- DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_GO);\r
-\r
- // wait for ready\r
- while (!(DmcReadReg(DMC_STATUS_REG) & DMC_STATUS_READY));\r
-\r
-}\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL341Dmc\r
- FILE_GUID = edf8da40-aad1-11df-a1f4-0002a5d5c51b\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PL341DmcLib\r
-\r
-[Sources]\r
- PL341Dmc.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[FixedPcd]\r
+++ /dev/null
-#\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http:#opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-#include <Drivers/PL354Smc.h>\r
-\r
-#Start of the code section\r
-.text\r
-\r
-#Maintain 8 byte alignment\r
-.align 3\r
-\r
-\r
-GCC_ASM_EXPORT(SMCInitializeNOR)\r
-GCC_ASM_EXPORT(SMCInitializeSRAM)\r
-GCC_ASM_EXPORT(SMCInitializePeripherals)\r
-GCC_ASM_EXPORT(SMCInitializeVRAM)\r
-\r
-\r
-# CS0 CS0-Interf0 NOR1 flash on the motherboard\r
-# CS1 CS1-Interf0 Reserved for the motherboard\r
-# CS2 CS2-Interf0 SRAM on the motherboard\r
-# CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard\r
-# CS4 CS0-Interf1 NOR2 flash on the motherboard\r
-# CS5 CS1-Interf1 memory-mapped peripherals\r
-# CS6 CS2-Interf1 memory-mapped peripherals\r
-# CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r
-\r
-// IN r1 SmcBase\r
-// IN r2 ChipSelect\r
-// NOTE: This code is been called before any stack has been setup. It means some registers\r
-// could be overwritten (case of 'r0')\r
-ASM_PFX(SMCInitializeNOR):\r
-#\r
-# Setup NOR1 (CS0-Interface0)\r
-#\r
-\r
- # Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
- #Read cycle timeout = 0xA (0:3)\r
- #Write cycle timeout = 0x3(7:4)\r
- #OE Assertion Delay = 0x9(11:8)\r
- #WE Assertion delay = 0x3(15:12)\r
- #Page cycle timeout = 0x2(19:16) \r
- LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000028 = ReadMemoryBurstLength:continuous\r
- # 0x00000280 = WriteMemoryBurstLength:continuous\r
- # 0x00000800 = Set Address Valid\r
- LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
-\r
- # Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
- # 0x00000000 = ChipSelect0-Interface 0\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x00400000,r0) @ldr r0, = 0x00400000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
- bx lr\r
-\r
-ASM_PFX(SMCInitializeSRAM):\r
-#\r
-# Setup SRAM (CS2-Interface0)\r
-#\r
- LoadConstantToReg (0x00027158,r0) @ldr r0, = 0x00027158\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
-\r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000800 = Set Address Valid\r
- LoadConstantToReg (0x00000802,r0) @ldr r0, = 0x00000802\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x01000000 = ChipSelect2-Interface 0\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x01400000,r0) @ldr r0, = 0x01400000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
-\r
- bx lr\r
-\r
-ASM_PFX(SMCInitializePeripherals):\r
-#\r
-# USB/Eth/VRAM (CS3-Interface0)\r
-#\r
- LoadConstantToReg (0x000CD2AA,r0) @ldr r0, = 0x000CD2AA\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000004 = Memory reads are synchronous\r
- # 0x00000040 = Memory writes are synchronous\r
- LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x01800000 = ChipSelect3-Interface 0\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x01C00000,r0) @ldr r0, = 0x01C00000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
-\r
-#\r
-# Setup NOR3 (CS0-Interface1)\r
-#\r
- LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000028 = ReadMemoryBurstLength:continuous\r
- # 0x00000280 = WriteMemoryBurstLength:continuous\r
- # 0x00000800 = Set Address Valid\r
- LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x02000000 = ChipSelect0-Interface 1\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x02400000,r0) @ldr r0, = 0x02400000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
-#\r
-# Setup Peripherals (CS3-Interface1)\r
-#\r
- LoadConstantToReg (0x00025156,r0) @ldr r0, = 0x00025156\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000004 = Memory reads are synchronous\r
- # 0x00000040 = Memory writes are synchronous\r
- LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x03800000 = ChipSelect3-Interface 1\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x03C00000,r0) @ldr r0, = 0x03C00000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- bx lr\r
-\r
-// IN r1 SmcBase\r
-// IN r2 VideoSRamBase\r
-// NOTE: This code is been called before any stack has been setup. It means some registers\r
-// could be overwritten (case of 'r0')\r
-ASM_PFX(SMCInitializeVRAM):\r
-#\r
-# Setup VRAM (CS1-Interface0)\r
-#\r
- LoadConstantToReg (0x00049249,r0) @ldr r0, = 0x00049249\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000004 = Memory reads are synchronous\r
- # 0x00000040 = Memory writes are synchronous\r
- LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x00800000 = ChipSelect1-Interface 0\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x00C00000,r0) @ldr r0, = 0x00C00000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
-#\r
-# Page mode setup for VRAM\r
-#\r
- #read current state \r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
-\r
- #enable page mode \r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- LoadConstantToReg (0x00900090,r0) @ldr r0, = 0x00900090\r
- str r0, [r2, #0] \r
-\r
- #confirm page mode enabled\r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- \r
- bx lr\r
- \r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
\ No newline at end of file
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-// \r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Drivers/PL354Smc.h>\r
-#include <AutoGen.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
- \r
- EXPORT SMCInitializeNOR\r
- EXPORT SMCInitializeSRAM\r
- EXPORT SMCInitializePeripherals\r
- EXPORT SMCInitializeVRAM\r
-\r
- PRESERVE8\r
- AREA ModuleInitializeSMC, CODE, READONLY\r
- \r
-// CS0 CS0-Interf0 NOR1 flash on the motherboard\r
-// CS1 CS1-Interf0 Reserved for the motherboard\r
-// CS2 CS2-Interf0 SRAM on the motherboard\r
-// CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard\r
-// CS4 CS0-Interf1 NOR2 flash on the motherboard\r
-// CS5 CS1-Interf1 memory-mapped peripherals\r
-// CS6 CS2-Interf1 memory-mapped peripherals\r
-// CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r
-\r
-// IN r1 SmcBase\r
-// IN r2 ChipSelect\r
-// NOTE: This code is been called before any stack has been setup. It means some registers\r
-// could be overwritten (case of 'r0')\r
-SMCInitializeNOR\r
- // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
- // - Read cycle timeout = 0xA (0:3)\r
- // - Write cycle timeout = 0x3(7:4)\r
- // - OE Assertion Delay = 0x9(11:8)\r
- // - WE Assertion delay = 0x3(15:12)\r
- // - Page cycle timeout = 0x2(19:16)\r
- ldr r0, = 0x0002393A\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
- ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
-\r
- // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
- ldr r0, =PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
- orr r0, r0, r2\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
- bx lr\r
-\r
-\r
-//\r
-// Setup SRAM (CS2-Interface0)\r
-//\r
-SMCInitializeSRAM\r
- ldr r0, = 0x00027158\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
-\r
- ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,2))\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
-\r
- bx lr\r
-\r
-SMCInitializePeripherals\r
-//\r
-// USB/Eth/VRAM (CS3-Interface0)\r
-//\r
- ldr r0, = 0x000CD2AA\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,3))\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
-\r
-\r
-//\r
-// Setup Peripherals (CS3-Interface1)\r
-//\r
- ldr r0, = 0x00025156\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(1,3))\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
-\r
- bx lr\r
-\r
-\r
-// IN r1 SmcBase\r
-// IN r2 VideoSRamBase\r
-// NOTE: This code is been called before any stack has been setup. It means some registers\r
-// could be overwritten (case of 'r0')\r
-SMCInitializeVRAM\r
- //\r
- // Setup VRAM (CS1-Interface0)\r
- //\r
- ldr r0, = 0x00049249\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- ldr r0, = (PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,1))\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
- //\r
- // Page mode setup for VRAM\r
- //\r
-\r
- // Read current state\r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
-\r
- // Enable page mode\r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- ldr r0, = 0x00900090\r
- str r0, [r2, #0] \r
-\r
- // Confirm page mode enabled\r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- \r
- bx lr\r
- \r
- END\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL354SmcSec\r
- FILE_GUID = 10952220-aa32-11df-a438-0002a5d5c51b\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PL354SmcLib\r
-\r
-[Sources.common]\r
- InitializeSMC.asm | RVCT\r
- InitializeSMC.S | GCC\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[FixedPcd]\r
+++ /dev/null
-/** @file
-*
-* Copyright (c) 2011, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef PL301AXI_H_
-#define PL301AXI_H_
-
-VOID PL301AxiInit(UINTN FAxiBase);
-
-
-#endif /* PL301AXI_H_ */
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef L2CACHELIB_H_\r
-#define L2CACHELIB_H_\r
-\r
-#define L2X0_CACHEID 0x000\r
-#define L2X0_CTRL 0x100\r
-#define L2X0_AUXCTRL 0x104\r
-#define L230_TAG_LATENCY 0x108\r
-#define L230_DATA_LATENCY 0x10C\r
-#define L2X0_INTCLEAR 0x220\r
-#define L2X0_CACHE_SYNC 0x730\r
-#define L2X0_INVWAY 0x77C\r
-#define L2X0_CLEAN_WAY 0x7BC\r
-#define L2X0_PFCTRL 0xF60\r
-#define L2X0_PWRCTRL 0xF80\r
-\r
-#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41\r
-#define L2X0_CACHEID_PARTNUM_PL310 0x03\r
-\r
-#define L2X0_CTRL_ENABLED 0x1\r
-#define L2X0_CTRL_DISABLED 0x0\r
-\r
-#define L2X0_AUXCTRL_EXCLUSIVE (1 << 12)\r
-#define L2X0_AUXCTRL_ASSOCIATIVITY (1 << 16)\r
-#define L2X0_AUXCTRL_WAYSIZE_MASK (3 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_16KB (1 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_32KB (2 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_64KB (3 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_128KB (4 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_256KB (5 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_512KB (6 << 17)\r
-#define L2X0_AUXCTRL_EM (1 << 20)\r
-#define L2X0_AUXCTRL_SHARED_OVERRIDE (1 << 22)\r
-#define L2x0_AUXCTRL_AW_AWCACHE (0 << 23)\r
-#define L2x0_AUXCTRL_AW_NOALLOC (1 << 23)\r
-#define L2x0_AUXCTRL_AW_OVERRIDE (2 << 23)\r
-#define L2X0_AUXCTRL_SBO (1 << 25)\r
-#define L2X0_AUXCTRL_NSAC (1 << 27)\r
-#define L2x0_AUXCTRL_DPREFETCH (1 << 28)\r
-#define L2x0_AUXCTRL_IPREFETCH (1 << 29)\r
-#define L2x0_AUXCTRL_EARLY_BRESP (1 << 30)\r
-\r
-#define L2x0_LATENCY_1_CYCLE 0\r
-#define L2x0_LATENCY_2_CYCLES 1\r
-#define L2x0_LATENCY_3_CYCLES 2\r
-#define L2x0_LATENCY_4_CYCLES 3\r
-#define L2x0_LATENCY_5_CYCLES 4\r
-#define L2x0_LATENCY_6_CYCLES 5\r
-#define L2x0_LATENCY_7_CYCLES 6\r
-#define L2x0_LATENCY_8_CYCLES 7\r
-\r
-#define PL310_LATENCIES(Write,Read,Setup) (((Write) << 8) | ((Read) << 4) | (Setup))\r
-#define PL310_TAG_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)\r
-#define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)\r
-\r
-VOID\r
-L2x0CacheInit (\r
- IN UINTN L2x0Base,\r
- IN UINT32 L2x0TagLatencies,\r
- IN UINT32 L2x0DataLatencies,\r
- IN UINT32 L2x0AuxValue,\r
- IN UINT32 L2x0AuxMask,\r
- IN BOOLEAN CacheEnabled\r
- );\r
-\r
-#endif /* L2CACHELIB_H_ */\r
+++ /dev/null
-/** @file
-*
-* Copyright (c) 2011, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef _PL341DMC_H_
-#define _PL341DMC_H_
-
-
-typedef struct {
- UINTN base; // base address for the controller
- UINTN phy_ctrl_base; // DDR2 Phy control base
- UINTN HasQos; // has QoS registers
- UINTN MaxChip; // number of memory chips accessible
- BOOLEAN IsUserCfg;
- UINT32 User0Cfg;
- UINT32 User2Cfg;
- UINT32 refresh_prd;
- UINT32 cas_latency;
- UINT32 write_latency;
- UINT32 t_mrd;
- UINT32 t_ras;
- UINT32 t_rc;
- UINT32 t_rcd;
- UINT32 t_rfc;
- UINT32 t_rp;
- UINT32 t_rrd;
- UINT32 t_wr;
- UINT32 t_wtr;
- UINT32 t_xp;
- UINT32 t_xsr;
- UINT32 t_esr;
- UINT32 MemoryCfg;
- UINT32 MemoryCfg2;
- UINT32 MemoryCfg3;
- UINT32 ChipCfg0;
- UINT32 ChipCfg1;
- UINT32 ChipCfg2;
- UINT32 ChipCfg3;
- UINT32 t_faw;
- UINT32 t_data_en;
- UINT32 t_wdata_en;
- UINT32 ModeReg;
- UINT32 ExtModeReg;
-} PL341_DMC_CONFIG;
-
-/* Memory config bit fields */
-#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9 0x1
-#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10 0x2
-#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11 0x3
-#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12 0x4
-#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11 (0x0 << 3)
-#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12 (0x1 << 3)
-#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13 (0x2 << 3)
-#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14 (0x3 << 3)
-#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15 (0x4 << 3)
-#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16 (0x5 << 3)
-#define DMC_MEMORY_CONFIG_BURST_2 (0x1 << 15)
-#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15)
-#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15)
-#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15)
-#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21)
-#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21)
-#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21)
-#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21)
-
-#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0)
-#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0)
-#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2)
-#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3)
-#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4)
-#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4)
-#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6)
-#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6)
-#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6)
-#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6)
-
-//
-// DMC Configuration Register Map
-//
-#define DMC_STATUS_REG 0x00
-#define DMC_COMMAND_REG 0x04
-#define DMC_DIRECT_CMD_REG 0x08
-#define DMC_MEMORY_CONFIG_REG 0x0C
-#define DMC_REFRESH_PRD_REG 0x10
-#define DMC_CAS_LATENCY_REG 0x14
-#define DMC_WRITE_LATENCY_REG 0x18
-#define DMC_T_MRD_REG 0x1C
-#define DMC_T_RAS_REG 0x20
-#define DMC_T_RC_REG 0x24
-#define DMC_T_RCD_REG 0x28
-#define DMC_T_RFC_REG 0x2C
-#define DMC_T_RP_REG 0x30
-#define DMC_T_RRD_REG 0x34
-#define DMC_T_WR_REG 0x38
-#define DMC_T_WTR_REG 0x3C
-#define DMC_T_XP_REG 0x40
-#define DMC_T_XSR_REG 0x44
-#define DMC_T_ESR_REG 0x48
-#define DMC_MEMORY_CFG2_REG 0x4C
-#define DMC_MEMORY_CFG3_REG 0x50
-#define DMC_T_FAW_REG 0x54
-#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */
-#define DMC_T_WRLAT_DIFF 0x60 /* DFI write data enable register */
-
-// Returns the state of the memory controller:
-#define DMC_STATUS_CONFIG 0x0
-#define DMC_STATUS_READY 0x1
-#define DMC_STATUS_PAUSED 0x2
-#define DMC_STATUS_LOWPOWER 0x3
-
-// Changes the state of the memory controller:
-#define DMC_COMMAND_GO 0x0
-#define DMC_COMMAND_SLEEP 0x1
-#define DMC_COMMAND_WAKEUP 0x2
-#define DMC_COMMAND_PAUSE 0x3
-#define DMC_COMMAND_CONFIGURE 0x4
-#define DMC_COMMAND_ACTIVEPAUSE 0x7
-
-// Determines the command required
-#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL 0x0
-#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH (0x1 << 18)
-#define DMC_DIRECT_CMD_MEMCMD_MODEREG (0x2 << 18)
-#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG (0x2 << 18)
-#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18)
-#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22)
-#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16)
-#define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20)
-
-
-//
-// AXI ID configuration register map
-//
-#define DMC_ID_0_CFG_REG 0x100
-#define DMC_ID_1_CFG_REG 0x104
-#define DMC_ID_2_CFG_REG 0x108
-#define DMC_ID_3_CFG_REG 0x10C
-#define DMC_ID_4_CFG_REG 0x110
-#define DMC_ID_5_CFG_REG 0x114
-#define DMC_ID_6_CFG_REG 0x118
-#define DMC_ID_7_CFG_REG 0x11C
-#define DMC_ID_8_CFG_REG 0x120
-#define DMC_ID_9_CFG_REG 0x124
-#define DMC_ID_10_CFG_REG 0x128
-#define DMC_ID_11_CFG_REG 0x12C
-#define DMC_ID_12_CFG_REG 0x130
-#define DMC_ID_13_CFG_REG 0x134
-#define DMC_ID_14_CFG_REG 0x138
-#define DMC_ID_15_CFG_REG 0x13C
-
-// Set the QoS
-#define DMC_ID_CFG_QOS_DISABLE 0
-#define DMC_ID_CFG_QOS_ENABLE 1
-#define DMC_ID_CFG_QOS_MIN 2
-
-
-//
-// Chip configuration register map
-//
-#define DMC_CHIP_0_CFG_REG 0x200
-#define DMC_CHIP_1_CFG_REG 0x204
-#define DMC_CHIP_2_CFG_REG 0x208
-#define DMC_CHIP_3_CFG_REG 0x20C
-
-//
-// User Defined Pins
-//
-#define DMC_USER_STATUS_REG 0x300
-#define DMC_USER_0_CFG_REG 0x304
-#define DMC_USER_1_CFG_REG 0x308
-#define DMC_FEATURE_CRTL_REG 0x30C
-#define DMC_USER_2_CFG_REG 0x310
-
-
-//
-// PHY Register Settings
-//
-#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset
-#define PHY_PTM_IOTERM 0xE04
-#define PHY_PTM_PLL_EN 0xe0c
-#define PHY_PTM_PLL_RANGE 0xe18
-#define PHY_PTM_FEEBACK_DIV 0xe1c
-#define PHY_PTM_RCLK_DIV 0xe20
-#define PHY_PTM_LOCK_STATUS 0xe28
-#define PHY_PTM_INIT_DONE 0xe34
-#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8
-#define PHY_PTM_SQU_TRAINING 0xee8
-#define PHY_PTM_SQU_STAT 0xeec
-
-// ==============================================================================
-// PIPD 40G DDR2/DDR3 PHY Register definitions
-//
-// Offsets from APB Base Address
-// ==============================================================================
-#define PHY_BYTE0_OFFSET 0x000
-#define PHY_BYTE1_OFFSET 0x200
-#define PHY_BYTE2_OFFSET 0x400
-#define PHY_BYTE3_OFFSET 0x600
-
-#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust
-#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust
-#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust
-#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust
-
-#define PHY_BYTE0_IOSTR_OFFSET 0x004
-#define PHY_BYTE1_IOSTR_OFFSET 0x204
-#define PHY_BYTE2_IOSTR_OFFSET 0x404
-#define PHY_BYTE3_IOSTR_OFFSET 0x604
-
-
-;//--------------------------------------------------------------------------
-
-// DFI Clock ranges:
-
-#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0
-#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1
-#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2
-#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3
-#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4
-#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5
-#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6
-
-
-
-#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz
-
-//--------------------------------------------------------------------------
-
-
-// PLL Range
-
-#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
-#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
-#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
-#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
-#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0
-#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1
-
-
-// PHY Reset in SCC
-
-#define SCC_PHY_RST_REG_OFF 0xA0
-#define SCC_REMAP_REG_OFF 0x00
-#define SCC_PHY_RST0_MASK 1 // Active LOW PHY0 reset
-#define SCC_PHY_RST0_SHFT 0 // Active LOW PHY0 reset
-#define SCC_PHY_RST1_MASK 0x100 // Active LOW PHY1 reset
-#define SCC_PHY_RST1_SHFT 8 // Active LOW PHY1 reset
-
-#define TC_UIOLHNC_MASK 0x000003C0
-#define TC_UIOLHNC_SHIFT 0x6
-#define TC_UIOLHPC_MASK 0x0000003F
-#define TC_UIOLHPC_SHIFT 0x2
-#define TC_UIOHOCT_MASK 0x2
-#define TC_UIOHOCT_SHIFT 0x1
-#define TC_UIOHSTOP_SHIFT 0x0
-#define TC_UIOLHXC_VALUE 0x4
-
-#define PHY_PTM_SQU_TRAINING_ENABLE 0x1
-#define PHY_PTM_SQU_TRAINING_DISABLE 0x0
-
-
-//--------------------------------------
-// JEDEC DDR2 Device Register definitions and settings
-//--------------------------------------
-#define DDR_MODESET_SHFT 14
-#define DDR_MODESET_MR 0x0 ;// Mode register
-#define DDR_MODESET_EMR 0x1 ;// Extended Mode register
-#define DDR_MODESET_EMR2 0x2
-#define DDR_MODESET_EMR3 0x3
-
-//
-// Extended Mode Register settings
-//
-#define DDR_EMR_OCD_MASK 0x0000380
-#define DDR_EMR_OCD_SHIFT 0x7
-#define DDR_EMR_RTT_MASK 0x00000044 // DDR2 Device RTT (ODT) settings
-#define DDR_EMR_RTT_SHIFT 0x2
-#define DDR_EMR_ODS_MASK 0x00000002 // DDR2 Output Drive Strength
-#define DDR_EMR_ODS_SHIFT 0x0001
-
-// Termination Values:
-#define DDR_EMR_RTT_50R 0x00000044 // DDR2 50 Ohm termination
-#define DDR_EMR_RTT_75R 0x00000004 // DDR2 75 Ohm termination
-#define DDR_EMR_RTT_150 0x00000040 // DDR2 150 Ohm termination
-
-// Output Drive Strength Values:
-#define DDR_EMR_ODS_FULL 0x0 // DDR2 Full Drive Strength
-#define DDR_EMR_ODS_HALF 0x1 // DDR2 Half Drive Strength
-
-// OCD values
-#define DDR_EMR_OCD_DEFAULT 0x7
-#define DDR_EMR_OCD_NS 0x0
-
-#define DDR_EMR_ODS_VAL DDR_EMR_ODS_FULL
-
-#define DDR_SDRAM_START_ADDR 0x10000000
-
-
-// ----------------------------------------
-// PHY IOTERM values
-// ----------------------------------------
-#define PHY_PTM_IOTERM_OFF 0x0
-#define PHY_PTM_IOTERM_150R 0x1
-#define PHY_PTM_IOTERM_75R 0x2
-#define PHY_PTM_IOTERM_50R 0x3
-
-#define PHY_BYTE_IOSTR_60OHM 0x0
-#define PHY_BYTE_IOSTR_40OHM 0x1
-#define PHY_BYTE_IOSTR_30OHM 0x2
-#define PHY_BYTE_IOSTR_30AOHM 0x3
-
-#define DDR2_MR_BURST_LENGTH_4 (2)
-#define DDR2_MR_BURST_LENGTH_8 (3)
-#define DDR2_MR_DLL_RESET (1 << 8)
-#define DDR2_MR_CAS_LATENCY_4 (4 << 4)
-#define DDR2_MR_CAS_LATENCY_5 (5 << 4)
-#define DDR2_MR_CAS_LATENCY_6 (6 << 4)
-#define DDR2_MR_WR_CYCLES_2 (1 << 9)
-#define DDR2_MR_WR_CYCLES_3 (2 << 9)
-#define DDR2_MR_WR_CYCLES_4 (3 << 9)
-#define DDR2_MR_WR_CYCLES_5 (4 << 9)
-#define DDR2_MR_WR_CYCLES_6 (5 << 9)
-
-
-VOID PL341DmcInit (
- IN PL341_DMC_CONFIG *config
- );
-
-VOID PL341DmcPhyInit (
- IN UINTN DmcPhyBase
- );
-
-VOID PL341DmcTrainPHY (
- IN UINTN DmcPhyBase
- );
-
-#endif /* _PL341DMC_H_ */
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef PL354SMC_H_\r
-#define PL354SMC_H_\r
-\r
-#define PL354_SMC_DIRECT_CMD_OFFSET 0x10\r
-#define PL354_SMC_SET_CYCLES_OFFSET 0x14\r
-#define PL354_SMC_SET_OPMODE_OFFSET 0x18\r
-\r
-#define PL354_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CS(interf,chip) (((interf) << 25) | ((chip) << 23))\r
-\r
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)\r
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)\r
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_BAA (1 << 10)\r
-#define PL354_SMC_SET_OPMODE_SET_ADV (1 << 11)\r
-#define PL354_SMC_SET_OPMODE_SET_BLS (1 << 12)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)\r
-\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-*\r
-**/\r
-\r
-#include <Uefi.h>\r
-#include <Drivers/PL310L2Cache.h>\r
-\r
-// Initialize L2X0 Cache Controller\r
-VOID\r
-L2x0CacheInit (\r
- IN UINTN L2x0Base,\r
- IN UINT32 L2x0TagLatencies,\r
- IN UINT32 L2x0DataLatencies,\r
- IN UINT32 L2x0AuxValue,\r
- IN UINT32 L2x0AuxMask,\r
- IN BOOLEAN CacheEnabled\r
- )\r
-{\r
- //No implementation\r
-}\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = L2X0CacheLibNull\r
- FILE_GUID = 9c76c900-1e8c-11e0-8766-0002a5d5c51b\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = L2X0CacheLib\r
-\r
-[Sources]\r
- L2X0Cache.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- ArmPkg/ArmPkg.dec\r
#
# ARM Primecells
#
- gArmPlatformTokenSpaceGuid.PcdSP804FrequencyInMHz|1|UINT32|0x0000001D
- gArmPlatformTokenSpaceGuid.PcdSP804Timer0InterruptNum|0|UINT32|0x0000001E
+
+ ## SP804 DualTimer
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C
+
+ ## SP805 Watchdog
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
+
+ ## PL011 UART
+ gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0x00000000|UINT32|0x0000001F
+ gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout|0x00000000|UINT32|0x00000020
+
+ ## PL031 RealTimeClock
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
+
+ ## PL061 GPIO
+ gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
+
+ ## PL111 Lcd
+ gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026
+ gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027
+
+ ## PL180 MCI
+ gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028
+ gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029
#
# BDS - Boot Manager
#DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf\r
\r
# L2 Cache Driver\r
- L2X0CacheLib|ArmPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf\r
+ L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf\r
# ARM PL390 General Interrupt Driver in Secure and Non-secure\r
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf\r
\r
\r
# Size of the region used by UEFI in permanent memory (Reserved 64MB)\r
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000\r
- \r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000\r
- gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms\r
- gArmPlatformTokenSpaceGuid.PcdSP804Timer0InterruptNum|36\r
- \r
+ \r
#\r
# ARM Pcds\r
#\r
#\r
gArmRealViewEbPkgTokenSpaceGuid.PcdGdbUartBase|0x1000a000\r
\r
+ #\r
+ # ARM PrimeCells\r
+ #\r
+ \r
+ ## SP804 Timer\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000\r
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms\r
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|36\r
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x10011000\r
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x10012020\r
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x10012000\r
+ \r
+ ## PL031 RealTimeClock\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x10017000\r
+ \r
+ ## PL111 Lcd\r
+ gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x10020000\r
+ \r
#\r
# ARM PL011 - Serial Terminal\r
#\r
#DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
# L2 Cache Driver
- L2X0CacheLib|ArmPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
+ L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
# Size of the region used by UEFI in permanent memory (Reserved 64MB)
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
-
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000
- gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
- gArmPlatformTokenSpaceGuid.PcdSP804Timer0InterruptNum|33
-
+
#
# ARM Pcds
#
#
gArmRealViewEbPkgTokenSpaceGuid.PcdGdbUartBase|0x1000a000
+ #
+ # ARM PrimeCells
+ #
+
+ ## SP804 Timer
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|33
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x10011000
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x10012020
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x10012000
+
+ ## PL031 RealTimeClock
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x10017000
+
#
# ARM PL011 - Serial Terminal
#
//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/\r
\r
\r
-// PL031 RTC - Other settings\r
-#define PL031_PPM_ACCURACY 300000000\r
-\r
-\r
/*******************************************\r
// EFI Memory Map in Permanent Memory (DRAM)\r
*******************************************/\r
#include <Drivers/PL341Dmc.h>
#include <Drivers/SP804Timer.h>
+#include <ArmPlatform.h>
+
/**
Return if Trustzone is supported by your platform
/**
Initialize controllers that must setup in the normal world
- This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
in the PEI phase.
**/
#include <Library/MemoryAllocationLib.h>\r
#include <Library/IoLib.h>\r
\r
+#include <ArmPlatform.h>\r
+\r
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6\r
\r
// DDR attributes\r
UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
# ARM PL310 L2 Cache Driver
- L2X0CacheLib|ArmPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf
+ L2X0CacheLib|ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf
# ARM PL354 SMC Driver
- PL354SmcLib|ArmPkg/Drivers/PL35xSmc/PL354SmcSec.inf
+ PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf
# ARM PL341 DMC Driver
- PL341DmcLib|ArmPkg/Drivers/PL34xDmc/PL341Dmc.inf
+ PL341DmcLib|ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.inf
# ARM PL301 Axi Driver
- PL301AxiLib|ArmPkg/Drivers/PL301Axi/PL301Axi.inf
+ PL301AxiLib|ArmPlatformPkg/Drivers/PL301Axi/PL301Axi.inf
# ARM PL011 UART Driver
PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
# System Memory (1GB)
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x60000000
gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
-
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000
- gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
- gArmPlatformTokenSpaceGuid.PcdSP804Timer0InterruptNum|34
-
+
#
# ARM Pcds
#
gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
-
+
#
# ARM PrimeCell
#
- gArmTokenSpaceGuid.PcdPL180SysMciRegAddress|0x10000048
- gArmTokenSpaceGuid.PcdPL180MciBaseAddress|0x10005000
- #
- # ARM PL011 - Serial Terminal
- #
+ ## SP804 Timer
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|34
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x10011000
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x10012020
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x10012000
+
+ ## SP805 Watchdog - Motherboard Watchdog
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1000F000
+ ## SP805 Watchdog - CoreTile Watchdog
+ #gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x100E5000
+
+ ## PL011 - Serial Terminal
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x10009000
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400
+
+ ## PL031 RealTimeClock
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x10017000
+
+ ## PL111 Lcd
+ # PL111 CoreTile or Tuscan Standalone controller
+ gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x10020000
+ # PL111 Versatile Express Motherboard controller
+ #gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1001F000
+
+ ## PL180 MMC/SD card controller
+ gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x10000048
+ gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x10005000
#
# ARM PL390 General Interrupt Controller
# Multimedia Card Interface
#
EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
- ArmPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+ ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
#
# FAT filesystem + GPT/MBR partitioning
# Multimedia Card Interface
#
INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
- INF ArmPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+ INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
#
# UEFI application (Shell Embedded Boot Loader)
#
# For a list of mode numbers look in LcdArmVExpress.c
#
- gArmVExpressTokenSpaceGuid.PcdPL111MaxMode|3|UINT32|0x00000003
+ gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode|3|UINT32|0x00000003
+ gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId|1|UINT32|0x00000004
#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB\r
\r
// DRAM\r
-#define ARM_VE_DRAM_BASE 0x60000000\r
-#define ARM_VE_DRAM_SZ 0x40000000\r
+#define ARM_VE_DRAM_BASE PcdGet32 (PcdSystemMemoryBase)\r
+#define ARM_VE_DRAM_SZ PcdGet32 (PcdSystemMemorySize)\r
// Inside the DRAM we allocate a section for the VRAM (Video RAM)\r
-#define LCD_VRAM_CORE_TILE_BASE 0x64000000\r
+#define LCD_VRAM_CORE_TILE_BASE 0x64000000\r
\r
// External AXI between daughterboards (Logic Tile)\r
#define ARM_VE_EXT_AXI_BASE 0xE0000000\r
// PL310 L2x0 Cache Controller Base Address\r
//#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000\r
\r
-/***********************************************************************************\r
- Select between Motherboard and Core Tile peripherals\r
-************************************************************************************/\r
-\r
-// Specify which PL111 to use\r
-//#define PL111_CLCD_BASE PL111_CLCD_MOTHERBOARD_BASE\r
-#define PL111_CLCD_BASE PL111_CLCD_CORE_TILE_BASE\r
-\r
-// Specify which Watchdog to use\r
-#define SP805_WDOG_BASE SP805_WDOG_MOTHERBOARD_BASE\r
-//#define SP805_WDOG_BASE SP805_WDOG_CORE_TILE_BASE\r
-\r
/***********************************************************************************\r
Peripherals' misc settings\r
************************************************************************************/\r
#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK (1 << 4)\r
#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)\r
\r
-// PL031 RTC - Other settings\r
-#define PL031_PPM_ACCURACY 300000000\r
-\r
-// SP805 Watchdog - Other settings\r
-#define SP805_CLOCK_FREQUENCY 32000\r
-#define SP805_MAX_TICKS 0xFFFFFFFF\r
-\r
-// PL111 Lcd\r
-#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1\r
-\r
/***********************************************************************************\r
// EFI Memory Map in Permanent Memory (DRAM)\r
************************************************************************************/\r
[FixedPcd]
gArmPlatformTokenSpaceGuid.PcdStandalone
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
gArmTokenSpaceGuid.PcdL2x0ControllerBase
#include <Drivers/PL301Axi.h>
#include <Drivers/SP804Timer.h>
+#include <ArmPlatform.h>
+
#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);
// DDR2 timings
/**
Initialize controllers that must setup in the normal world
- This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
in the PEI phase.
**/
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
\r
+#include <ArmPlatform.h>\r
+\r
// Number of Virtual Memory Map Descriptors without a Logic Tile\r
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6\r
\r
#include <Drivers/PL310L2Cache.h>
+#include <ArmPlatform.h>
+
/**
Initialize the Secure peripherals and memory regions
[LibraryClasses]
BaseLib
+ IoLib
[Guids]
// This could be because the specific implementation of PL111 has certain limitations.\r
\r
// Set the maximum mode allowed\r
- return (PcdGet32(PcdPL111MaxMode));\r
+ return (PcdGet32(PcdPL111LcdMaxMode));\r
}\r
\r
EFI_STATUS\r
break;\r
case ARM_VE_DAUGHTERBOARD_1_SITE:\r
Function = SYS_CFG_OSC_SITE1;\r
- OscillatorId = PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID;\r
+ OscillatorId = (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId);\r
break;\r
default:\r
return EFI_UNSUPPORTED;\r
BaseLib
ArmPlatformSysConfigLib
-[Guids]
-
-[Protocols]
-
-[FeaturePcd]
-
-[FixedPcd.common]
- gArmVExpressTokenSpaceGuid.PcdPL111MaxMode
-
-[Pcd.common]
-
-[Depex]
+[Pcd]
+ gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode
+ gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId
#include <Guid/GlobalVariable.h>
-#include <ArmPlatform.h>
#include "LcdGraphicsOutputDxe.h"
extern BOOLEAN mDisplayInitialized;
#include <PiDxe.h>
#include <Library/PcdLib.h>
-#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DevicePathLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Guid/GlobalVariable.h>
-#include <ArmPlatform.h>
#include "LcdGraphicsOutputDxe.h"
/**********************************************************************
BaseMemoryLib
LcdPlatformLib
-[Guids]
-
[Protocols]
gEfiDevicePathProtocolGuid
gEfiGraphicsOutputProtocolGuid
-[FixedPcd.common]
-
-[Pcd.common]
-
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdPL111LcdBase
[Depex]
gEfiCpuArchProtocolGuid
#include <Library/NorFlashPlatformLib.h>
#include <Library/UefiLib.h>
-#include <ArmPlatform.h>
-
#define HIGH_16_BITS 0xFFFF0000
#define LOW_16_BITS 0x0000FFFF
#define LOW_8_BITS 0x000000FF
**/
-#include <Base.h>
#include <PiDxe.h>
#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/UefiLib.h>
-#include <Library/IoLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
#include <Protocol/EmbeddedGpio.h>
-#include <ArmPlatform.h>
#include <Drivers/PL061Gpio.h>
-#define LOW_4_BITS 0x0000000F
-
BOOLEAN mPL061Initialized = FALSE;
/**
)
{
// Check if this is a PrimeCell Peripheral
- if( ( MmioRead8( PL061_GPIO_PCELL_ID0 ) != 0x0D )
- || ( MmioRead8( PL061_GPIO_PCELL_ID1 ) != 0xF0 )
- || ( MmioRead8( PL061_GPIO_PCELL_ID2 ) != 0x05 )
- || ( MmioRead8( PL061_GPIO_PCELL_ID3 ) != 0xB1 ) ) {
+ if ( (MmioRead8 (PL061_GPIO_PCELL_ID0) != 0x0D)
+ || (MmioRead8 (PL061_GPIO_PCELL_ID1) != 0xF0)
+ || (MmioRead8 (PL061_GPIO_PCELL_ID2) != 0x05)
+ || (MmioRead8 (PL061_GPIO_PCELL_ID3) != 0xB1)) {
return EFI_NOT_FOUND;
}
// Check if this PrimeCell Peripheral is the PL061 GPIO
- if( ( MmioRead8( PL061_GPIO_PERIPH_ID0 ) != 0x61 )
- || ( MmioRead8( PL061_GPIO_PERIPH_ID1 ) != 0x10 )
- || ( ( MmioRead8( PL061_GPIO_PERIPH_ID2 ) & LOW_4_BITS ) != 0x04 )
- || ( MmioRead8( PL061_GPIO_PERIPH_ID3 ) != 0x00 ) ) {
+ if ( (MmioRead8 (PL061_GPIO_PERIPH_ID0) != 0x61)
+ || (MmioRead8 (PL061_GPIO_PERIPH_ID1) != 0x10)
+ || ((MmioRead8 (PL061_GPIO_PERIPH_ID2) & 0xF) != 0x04)
+ || (MmioRead8 (PL061_GPIO_PERIPH_ID3) != 0x00)) {
return EFI_NOT_FOUND;
}
EFI_STATUS
PL061Initialize (
-VOID
+ VOID
)
{
EFI_STATUS Status;
// Check if the PL061 GPIO module exists on board
Status = PL061Identify();
- if (EFI_ERROR( Status )) {
+ if (EFI_ERROR (Status)) {
Status = EFI_DEVICE_ERROR;
goto EXIT;
}
// Do other hardware initialisation things here as required
// Disable Interrupts
- //if( MmioRead8( PL061_GPIO_IE_REG ) != 0 ) {
+ //if (MmioRead8 (PL061_GPIO_IE_REG) != 0) {
// // Ensure interrupts are disabled
//}
{
EFI_STATUS Status = EFI_SUCCESS;
- if( ( Value == NULL )
- || ( Gpio > LAST_GPIO_PIN ) )
+ if ( (Value == NULL)
+ || (Gpio > LAST_GPIO_PIN))
{
return EFI_INVALID_PARAMETER;
}
// Initialize the hardware if not already done
- if( !mPL061Initialized ) {
+ if (!mPL061Initialized) {
Status = PL061Initialize();
- if( EFI_ERROR(Status) ) {
+ if (EFI_ERROR(Status)) {
goto EXIT;
}
}
- if( MmioRead8( PL061_GPIO_DATA_REG ) & GPIO_PIN_MASK_HIGH_8BIT(Gpio) ) {
+ if (MmioRead8 (PL061_GPIO_DATA_REG) & GPIO_PIN_MASK_HIGH_8BIT(Gpio)) {
*Value = 1;
} else {
*Value = 0;
EFI_STATUS Status = EFI_SUCCESS;
// Check for errors
- if( Gpio > LAST_GPIO_PIN ) {
+ if (Gpio > LAST_GPIO_PIN) {
Status = EFI_INVALID_PARAMETER;
goto EXIT;
}
// Initialize the hardware if not already done
- if( !mPL061Initialized ) {
+ if (!mPL061Initialized) {
Status = PL061Initialize();
- if( EFI_ERROR(Status) ) {
+ if (EFI_ERROR(Status)) {
goto EXIT;
}
}
{
case GPIO_MODE_INPUT:
// Set the corresponding direction bit to LOW for input
- MmioAnd8( PL061_GPIO_DIR_REG, GPIO_PIN_MASK_LOW_8BIT(Gpio) );
+ MmioAnd8 (PL061_GPIO_DIR_REG, GPIO_PIN_MASK_LOW_8BIT(Gpio));
break;
case GPIO_MODE_OUTPUT_0:
// Set the corresponding data bit to LOW for 0
- MmioAnd8( PL061_GPIO_DATA_REG, GPIO_PIN_MASK_LOW_8BIT(Gpio) );
+ MmioAnd8 (PL061_GPIO_DATA_REG, GPIO_PIN_MASK_LOW_8BIT(Gpio));
// Set the corresponding direction bit to HIGH for output
- MmioOr8( PL061_GPIO_DIR_REG, GPIO_PIN_MASK_HIGH_8BIT(Gpio) );
+ MmioOr8 (PL061_GPIO_DIR_REG, GPIO_PIN_MASK_HIGH_8BIT(Gpio));
break;
case GPIO_MODE_OUTPUT_1:
// Set the corresponding data bit to HIGH for 1
- MmioOr8( PL061_GPIO_DATA_REG, GPIO_PIN_MASK_HIGH_8BIT(Gpio) );
+ MmioOr8 (PL061_GPIO_DATA_REG, GPIO_PIN_MASK_HIGH_8BIT(Gpio));
// Set the corresponding direction bit to HIGH for output
- MmioOr8( PL061_GPIO_DIR_REG, GPIO_PIN_MASK_HIGH_8BIT(Gpio) );
+ MmioOr8 (PL061_GPIO_DIR_REG, GPIO_PIN_MASK_HIGH_8BIT(Gpio));
break;
default:
EFI_STATUS Status;
// Check for errors
- if( ( Mode == NULL )
- || ( Gpio > LAST_GPIO_PIN ) ) {
+ if ( (Mode == NULL)
+ || (Gpio > LAST_GPIO_PIN)) {
return EFI_INVALID_PARAMETER;
}
// Initialize the hardware if not already done
- if( !mPL061Initialized ) {
+ if (!mPL061Initialized) {
Status = PL061Initialize();
- if( EFI_ERROR(Status) ) {
+ if (EFI_ERROR(Status)) {
return Status;
}
}
// Check if it is input or output
- if( MmioRead8( PL061_GPIO_DIR_REG ) & GPIO_PIN_MASK_HIGH_8BIT(Gpio) ) {
+ if (MmioRead8 (PL061_GPIO_DIR_REG) & GPIO_PIN_MASK_HIGH_8BIT(Gpio)) {
// Pin set to output
- if( MmioRead8( PL061_GPIO_DATA_REG ) & GPIO_PIN_MASK_HIGH_8BIT(Gpio) ) {
+ if (MmioRead8 (PL061_GPIO_DATA_REG) & GPIO_PIN_MASK_HIGH_8BIT(Gpio)) {
*Mode = GPIO_MODE_OUTPUT_1;
} else {
*Mode = GPIO_MODE_OUTPUT_0;
&Handle,
&gEmbeddedGpioProtocolGuid, &gGpio,
NULL
- );
+ );
if (EFI_ERROR(Status)) {
Status = EFI_OUT_OF_RESOURCES;
}
[LibraryClasses]
BaseLib
- UefiRuntimeServicesTableLib
- UefiLib
- UefiBootServicesTableLib
BaseMemoryLib
DebugLib
- UefiDriverEntryPoint
IoLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+ UefiRuntimeServicesTableLib
-[Guids]
+[Pcd]
+ gArmPlatformTokenSpaceGuid.PcdPL061GpioBase
[Protocols]
gEmbeddedGpioProtocolGuid
-
[Depex]
-TRUE
+ TRUE
#include <Protocol/HardwareInterrupt.h>
#include <Drivers/SP804Timer.h>
-#include <ArmPlatform.h>
+
+#define SP804_TIMER_PERIODIC_BASE (UINTN)PcdGet32 (PcdSP804TimerPeriodicBase)
+#define SP804_TIMER_METRONOME_BASE (UINTN)PcdGet32 (PcdSP804TimerMetronomeBase)
+#define SP804_TIMER_PERFORMANCE_BASE (UINTN)PcdGet32 (PcdSP804TimerPerformanceBase)
// The notification function to call on every timer interrupt.
volatile EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
// Cached interrupt vector
UINTN gVector;
-UINT32 mLastTickCount;
/**
OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
// If the interrupt is shared then we must check if this interrupt source is the one associated to this Timer
- if (MmioRead32 (SP804_TIMER0_BASE + SP804_TIMER_MSK_INT_STS_REG) != 0) {
+ if (MmioRead32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_MSK_INT_STS_REG) != 0) {
// clear the periodic interrupt
- MmioWrite32 (SP804_TIMER0_BASE + SP804_TIMER_INT_CLR_REG, 0);
+ MmioWrite32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_INT_CLR_REG, 0);
// signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
gInterrupt->EndOfInterrupt (gInterrupt, Source);
}
/**
- Make sure all ArrmVe Timers are disabled
+ Make sure all Dual Timers are disabled
**/
VOID
EFIAPI
IN VOID *Context
)
{
- // Disable timer 0 if enabled
- if (MmioRead32(SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
- MmioAnd32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, 0);
- }
-
- // Disable timer 1 if enabled
- if (MmioRead32(SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
- MmioAnd32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, 0);
- }
+ // Disable 'Periodic Operation' timer if enabled
+ if (MmioRead32(SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
+ MmioAnd32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, 0);
+ }
- // Disable timer 2 if enabled
- if (MmioRead32(SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
- MmioAnd32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, 0);
- }
+ // Disable 'Metronome/Delay' timer if enabled
+ if (MmioRead32(SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
+ MmioAnd32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, 0);
+ }
- // Disable timer 3 if enabled
- if (MmioRead32(SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
- MmioAnd32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, 0);
- }
+ // Disable 'Performance' timer if enabled
+ if (MmioRead32(SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
+ MmioAnd32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, 0);
+ }
}
/**
UINT64 TimerTicks;
// always disable the timer
- MmioAnd32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, ~SP804_TIMER_CTRL_ENABLE);
+ MmioAnd32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, ~SP804_TIMER_CTRL_ENABLE);
if (TimerPeriod == 0) {
// Leave timer disabled from above, and...
} else {
// Convert TimerPeriod into 1MHz clock counts (us units = 100ns units / 10)
TimerTicks = DivU64x32 (TimerPeriod, 10);
- TimerTicks = MultU64x32 (TimerTicks, PcdGet32(PcdSP804FrequencyInMHz));
+ TimerTicks = MultU64x32 (TimerTicks, PcdGet32(PcdSP804TimerFrequencyInMHz));
// if it's larger than 32-bits, pin to highest value
if (TimerTicks > 0xffffffff) {
}
// Program the SP804 timer with the new count value
- MmioWrite32 (SP804_TIMER0_BASE + SP804_TIMER_LOAD_REG, TimerTicks);
+ MmioWrite32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_LOAD_REG, TimerTicks);
// enable the timer
- MmioOr32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
+ MmioOr32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
// enable timer 0/1 interrupts
Status = gInterrupt->EnableInterruptSource (gInterrupt, gVector);
Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
ASSERT_EFI_ERROR (Status);
- // Configure timer 1 for free running operation, 32 bits, no prescaler, interrupt disabled
- MmioWrite32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
-
- // Enable the free running timer
- MmioOr32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
-
- // Record free running tick value (should be close to 0xffffffff)
- mLastTickCount = MmioRead32 (SP804_TIMER1_BASE + SP804_TIMER_CURRENT_REG);
-
// Disable the timer
Status = TimerDriverSetTimerPeriod (&gTimer, 0);
ASSERT_EFI_ERROR (Status);
// Install interrupt handler
- gVector = PcdGet32(PcdSP804Timer0InterruptNum);
+ gVector = PcdGet32(PcdSP804TimerPeriodicInterruptNum);
Status = gInterrupt->RegisterInterruptSource (gInterrupt, gVector, TimerInterruptHandler);
ASSERT_EFI_ERROR (Status);
// configure timer 0 for periodic operation, 32 bits, no prescaler, and interrupt enabled
- MmioWrite32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_PERIODIC | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1 | SP804_TIMER_CTRL_INT_ENABLE);
+ MmioWrite32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_PERIODIC | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1 | SP804_TIMER_CTRL_INT_ENABLE);
// Set up default timer
Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
gHardwareInterruptProtocolGuid
[Pcd.common]
- gArmPlatformTokenSpaceGuid.PcdSP804FrequencyInMHz
- gArmPlatformTokenSpaceGuid.PcdSP804Timer0InterruptNum
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase
gEmbeddedTokenSpaceGuid.PcdTimerPeriod
[Depex]
#include <PiDxe.h>
#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/UefiLib.h>
-#include <Library/IoLib.h>
#include <Protocol/WatchdogTimer.h>
-#include <ArmPlatform.h>
#include <Drivers/SP805Watchdog.h>
/**
)
{
// Check if this is a PrimeCell Peripheral
- if( ( MmioRead8( SP805_WDOG_PCELL_ID0 ) != 0x0D )
- || ( MmioRead8( SP805_WDOG_PCELL_ID1 ) != 0xF0 )
- || ( MmioRead8( SP805_WDOG_PCELL_ID2 ) != 0x05 )
- || ( MmioRead8( SP805_WDOG_PCELL_ID3 ) != 0xB1 ) ) {
+ if ( (MmioRead8 (SP805_WDOG_PCELL_ID0) != 0x0D)
+ || (MmioRead8 (SP805_WDOG_PCELL_ID1) != 0xF0)
+ || (MmioRead8 (SP805_WDOG_PCELL_ID2) != 0x05)
+ || (MmioRead8 (SP805_WDOG_PCELL_ID3) != 0xB1)) {
return EFI_NOT_FOUND;
}
// Check if this PrimeCell Peripheral is the SP805 Watchdog Timer
- if( ( MmioRead8( SP805_WDOG_PERIPH_ID0 ) != 0x05 )
- || ( MmioRead8( SP805_WDOG_PERIPH_ID1 ) != 0x18 )
- || (( MmioRead8( SP805_WDOG_PERIPH_ID2 ) & 0x0000000F) != 0x04 )
- || ( MmioRead8( SP805_WDOG_PERIPH_ID3 ) != 0x00 ) ) {
+ if ( (MmioRead8 (SP805_WDOG_PERIPH_ID0) != 0x05)
+ || (MmioRead8 (SP805_WDOG_PERIPH_ID1) != 0x18)
+ || ((MmioRead8 (SP805_WDOG_PERIPH_ID2) & 0x0000000F) != 0x04)
+ || (MmioRead8 (SP805_WDOG_PERIPH_ID3) != 0x00)) {
return EFI_NOT_FOUND;
}
[LibraryClasses]
BaseLib
- UefiRuntimeServicesTableLib
- UefiLib
- UefiBootServicesTableLib
BaseMemoryLib
DebugLib
- UefiDriverEntryPoint
IoLib
+ PcdLib
+ UefiLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
-[Guids]
+[Pcd]
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz
[Protocols]
gEfiWatchdogTimerArchProtocolGuid
-
[Depex]
-TRUE
+ TRUE
#ifndef __PL031_REAL_TIME_CLOCK_H__\r
#define __PL031_REAL_TIME_CLOCK_H__\r
\r
-#include <Base.h>\r
-#include <ArmPlatform.h>\r
-\r
// PL031 Registers\r
-#define PL031_RTC_DR_DATA_REGISTER (PL031_RTC_BASE + 0x000)\r
-#define PL031_RTC_MR_MATCH_REGISTER (PL031_RTC_BASE + 0x004)\r
-#define PL031_RTC_LR_LOAD_REGISTER (PL031_RTC_BASE + 0x008)\r
-#define PL031_RTC_CR_CONTROL_REGISTER (PL031_RTC_BASE + 0x00C)\r
-#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER (PL031_RTC_BASE + 0x010)\r
-#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER (PL031_RTC_BASE + 0x014)\r
-#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER (PL031_RTC_BASE + 0x018)\r
-#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER (PL031_RTC_BASE + 0x01C)\r
-#define PL031_RTC_PERIPH_ID0 (PL031_RTC_BASE + 0xFE0)\r
-#define PL031_RTC_PERIPH_ID1 (PL031_RTC_BASE + 0xFE4)\r
-#define PL031_RTC_PERIPH_ID2 (PL031_RTC_BASE + 0xFE8)\r
-#define PL031_RTC_PERIPH_ID3 (PL031_RTC_BASE + 0xFEC)\r
-#define PL031_RTC_PCELL_ID0 (PL031_RTC_BASE + 0xFF0)\r
-#define PL031_RTC_PCELL_ID1 (PL031_RTC_BASE + 0xFF4)\r
-#define PL031_RTC_PCELL_ID2 (PL031_RTC_BASE + 0xFF8)\r
-#define PL031_RTC_PCELL_ID3 (PL031_RTC_BASE + 0xFFC)\r
+#define PL031_RTC_DR_DATA_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x000)\r
+#define PL031_RTC_MR_MATCH_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x004)\r
+#define PL031_RTC_LR_LOAD_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x008)\r
+#define PL031_RTC_CR_CONTROL_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x00C)\r
+#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x010)\r
+#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x014)\r
+#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x018)\r
+#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x01C)\r
+#define PL031_RTC_PERIPH_ID0 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE0)\r
+#define PL031_RTC_PERIPH_ID1 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE4)\r
+#define PL031_RTC_PERIPH_ID2 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE8)\r
+#define PL031_RTC_PERIPH_ID3 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFEC)\r
+#define PL031_RTC_PCELL_ID0 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF0)\r
+#define PL031_RTC_PCELL_ID1 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF4)\r
+#define PL031_RTC_PCELL_ID2 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF8)\r
+#define PL031_RTC_PCELL_ID3 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFFC)\r
\r
// PL031 Values\r
#define PL031_RTC_ENABLED 0x00000001\r
#ifndef __PL061_GPIO_H__\r
#define __PL061_GPIO_H__\r
\r
-#include <Base.h>\r
#include <Protocol/EmbeddedGpio.h>\r
-#include <ArmPlatform.h>\r
\r
// SP805 Watchdog Registers\r
-#define PL061_GPIO_DATA_REG (PL061_GPIO_BASE + 0x000)\r
-#define PL061_GPIO_DIR_REG (PL061_GPIO_BASE + 0x400)\r
-#define PL061_GPIO_IS_REG (PL061_GPIO_BASE + 0x404)\r
-#define PL061_GPIO_IBE_REG (PL061_GPIO_BASE + 0x408)\r
-#define PL061_GPIO_IEV_REG (PL061_GPIO_BASE + 0x40C)\r
-#define PL061_GPIO_IE_REG (PL061_GPIO_BASE + 0x410)\r
-#define PL061_GPIO_RIS_REG (PL061_GPIO_BASE + 0x414)\r
-#define PL061_GPIO_MIS_REG (PL061_GPIO_BASE + 0x410)\r
-#define PL061_GPIO_IC_REG (PL061_GPIO_BASE + 0x41C)\r
-#define PL061_GPIO_AFSEL_REG (PL061_GPIO_BASE + 0x420)\r
-\r
-#define PL061_GPIO_PERIPH_ID0 (PL061_GPIO_BASE + 0xFE0)\r
-#define PL061_GPIO_PERIPH_ID1 (PL061_GPIO_BASE + 0xFE4)\r
-#define PL061_GPIO_PERIPH_ID2 (PL061_GPIO_BASE + 0xFE8)\r
-#define PL061_GPIO_PERIPH_ID3 (PL061_GPIO_BASE + 0xFEC)\r
-\r
-#define PL061_GPIO_PCELL_ID0 (PL061_GPIO_BASE + 0xFF0)\r
-#define PL061_GPIO_PCELL_ID1 (PL061_GPIO_BASE + 0xFF4)\r
-#define PL061_GPIO_PCELL_ID2 (PL061_GPIO_BASE + 0xFF8)\r
-#define PL061_GPIO_PCELL_ID3 (PL061_GPIO_BASE + 0xFFC)\r
+#define PL061_GPIO_DATA_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x000)\r
+#define PL061_GPIO_DIR_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x400)\r
+#define PL061_GPIO_IS_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x404)\r
+#define PL061_GPIO_IBE_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x408)\r
+#define PL061_GPIO_IEV_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x40C)\r
+#define PL061_GPIO_IE_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x410)\r
+#define PL061_GPIO_RIS_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x414)\r
+#define PL061_GPIO_MIS_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x410)\r
+#define PL061_GPIO_IC_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x41C)\r
+#define PL061_GPIO_AFSEL_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x420)\r
+\r
+#define PL061_GPIO_PERIPH_ID0 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE0)\r
+#define PL061_GPIO_PERIPH_ID1 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE4)\r
+#define PL061_GPIO_PERIPH_ID2 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE8)\r
+#define PL061_GPIO_PERIPH_ID3 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFEC)\r
+\r
+#define PL061_GPIO_PCELL_ID0 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF0)\r
+#define PL061_GPIO_PCELL_ID1 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF4)\r
+#define PL061_GPIO_PCELL_ID2 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF8)\r
+#define PL061_GPIO_PCELL_ID3 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFFC)\r
\r
\r
// GPIO pins are numbered 0..7\r
#ifndef _PL111LCD_H__
#define _PL111LCD_H__
-#include <ArmPlatform.h>
-
/**********************************************************************
*
* This header file contains all the bits of the PL111 that are
**********************************************************************/
// Controller Register Offsets
-#define PL111_REG_LCD_TIMING_0 (PL111_CLCD_BASE + 0x000)
-#define PL111_REG_LCD_TIMING_1 (PL111_CLCD_BASE + 0x004)
-#define PL111_REG_LCD_TIMING_2 (PL111_CLCD_BASE + 0x008)
-#define PL111_REG_LCD_TIMING_3 (PL111_CLCD_BASE + 0x00C)
-#define PL111_REG_LCD_UP_BASE (PL111_CLCD_BASE + 0x010)
-#define PL111_REG_LCD_LP_BASE (PL111_CLCD_BASE + 0x014)
-#define PL111_REG_LCD_CONTROL (PL111_CLCD_BASE + 0x018)
-#define PL111_REG_LCD_IMSC (PL111_CLCD_BASE + 0x01C)
-#define PL111_REG_LCD_RIS (PL111_CLCD_BASE + 0x020)
-#define PL111_REG_LCD_MIS (PL111_CLCD_BASE + 0x024)
-#define PL111_REG_LCD_ICR (PL111_CLCD_BASE + 0x028)
-#define PL111_REG_LCD_UP_CURR (PL111_CLCD_BASE + 0x02C)
-#define PL111_REG_LCD_LP_CURR (PL111_CLCD_BASE + 0x030)
-#define PL111_REG_LCD_PALETTE (PL111_CLCD_BASE + 0x200)
+#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)
+#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)
+#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)
+#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)
+#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)
+#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)
+#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)
+#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)
+#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)
+#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)
+#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)
+#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)
+#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)
+#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)
// Identification Register Offsets
-#define PL111_REG_CLCD_PERIPH_ID_0 (PL111_CLCD_BASE + 0xFE0)
-#define PL111_REG_CLCD_PERIPH_ID_1 (PL111_CLCD_BASE + 0xFE4)
-#define PL111_REG_CLCD_PERIPH_ID_2 (PL111_CLCD_BASE + 0xFE8)
-#define PL111_REG_CLCD_PERIPH_ID_3 (PL111_CLCD_BASE + 0xFEC)
-#define PL111_REG_CLCD_P_CELL_ID_0 (PL111_CLCD_BASE + 0xFF0)
-#define PL111_REG_CLCD_P_CELL_ID_1 (PL111_CLCD_BASE + 0xFF4)
-#define PL111_REG_CLCD_P_CELL_ID_2 (PL111_CLCD_BASE + 0xFF8)
-#define PL111_REG_CLCD_P_CELL_ID_3 (PL111_CLCD_BASE + 0xFFC)
+#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)
+#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)
+#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)
+#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)
+#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)
+#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)
+#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)
+#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)
/**********************************************************************/
--- /dev/null
+/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef PL301AXI_H_
+#define PL301AXI_H_
+
+VOID PL301AxiInit(UINTN FAxiBase);
+
+
+#endif /* PL301AXI_H_ */
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef L2CACHELIB_H_\r
+#define L2CACHELIB_H_\r
+\r
+#define L2X0_CACHEID 0x000\r
+#define L2X0_CTRL 0x100\r
+#define L2X0_AUXCTRL 0x104\r
+#define L230_TAG_LATENCY 0x108\r
+#define L230_DATA_LATENCY 0x10C\r
+#define L2X0_INTCLEAR 0x220\r
+#define L2X0_CACHE_SYNC 0x730\r
+#define L2X0_INVWAY 0x77C\r
+#define L2X0_CLEAN_WAY 0x7BC\r
+#define L2X0_PFCTRL 0xF60\r
+#define L2X0_PWRCTRL 0xF80\r
+\r
+#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41\r
+#define L2X0_CACHEID_PARTNUM_PL310 0x03\r
+\r
+#define L2X0_CTRL_ENABLED 0x1\r
+#define L2X0_CTRL_DISABLED 0x0\r
+\r
+#define L2X0_AUXCTRL_EXCLUSIVE (1 << 12)\r
+#define L2X0_AUXCTRL_ASSOCIATIVITY (1 << 16)\r
+#define L2X0_AUXCTRL_WAYSIZE_MASK (3 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_16KB (1 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_32KB (2 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_64KB (3 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_128KB (4 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_256KB (5 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_512KB (6 << 17)\r
+#define L2X0_AUXCTRL_EM (1 << 20)\r
+#define L2X0_AUXCTRL_SHARED_OVERRIDE (1 << 22)\r
+#define L2x0_AUXCTRL_AW_AWCACHE (0 << 23)\r
+#define L2x0_AUXCTRL_AW_NOALLOC (1 << 23)\r
+#define L2x0_AUXCTRL_AW_OVERRIDE (2 << 23)\r
+#define L2X0_AUXCTRL_SBO (1 << 25)\r
+#define L2X0_AUXCTRL_NSAC (1 << 27)\r
+#define L2x0_AUXCTRL_DPREFETCH (1 << 28)\r
+#define L2x0_AUXCTRL_IPREFETCH (1 << 29)\r
+#define L2x0_AUXCTRL_EARLY_BRESP (1 << 30)\r
+\r
+#define L2x0_LATENCY_1_CYCLE 0\r
+#define L2x0_LATENCY_2_CYCLES 1\r
+#define L2x0_LATENCY_3_CYCLES 2\r
+#define L2x0_LATENCY_4_CYCLES 3\r
+#define L2x0_LATENCY_5_CYCLES 4\r
+#define L2x0_LATENCY_6_CYCLES 5\r
+#define L2x0_LATENCY_7_CYCLES 6\r
+#define L2x0_LATENCY_8_CYCLES 7\r
+\r
+#define PL310_LATENCIES(Write,Read,Setup) (((Write) << 8) | ((Read) << 4) | (Setup))\r
+#define PL310_TAG_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)\r
+#define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)\r
+\r
+VOID\r
+L2x0CacheInit (\r
+ IN UINTN L2x0Base,\r
+ IN UINT32 L2x0TagLatencies,\r
+ IN UINT32 L2x0DataLatencies,\r
+ IN UINT32 L2x0AuxValue,\r
+ IN UINT32 L2x0AuxMask,\r
+ IN BOOLEAN CacheEnabled\r
+ );\r
+\r
+#endif /* L2CACHELIB_H_ */\r
--- /dev/null
+/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PL341DMC_H_
+#define _PL341DMC_H_
+
+
+typedef struct {
+ UINTN base; // base address for the controller
+ UINTN phy_ctrl_base; // DDR2 Phy control base
+ UINTN HasQos; // has QoS registers
+ UINTN MaxChip; // number of memory chips accessible
+ BOOLEAN IsUserCfg;
+ UINT32 User0Cfg;
+ UINT32 User2Cfg;
+ UINT32 refresh_prd;
+ UINT32 cas_latency;
+ UINT32 write_latency;
+ UINT32 t_mrd;
+ UINT32 t_ras;
+ UINT32 t_rc;
+ UINT32 t_rcd;
+ UINT32 t_rfc;
+ UINT32 t_rp;
+ UINT32 t_rrd;
+ UINT32 t_wr;
+ UINT32 t_wtr;
+ UINT32 t_xp;
+ UINT32 t_xsr;
+ UINT32 t_esr;
+ UINT32 MemoryCfg;
+ UINT32 MemoryCfg2;
+ UINT32 MemoryCfg3;
+ UINT32 ChipCfg0;
+ UINT32 ChipCfg1;
+ UINT32 ChipCfg2;
+ UINT32 ChipCfg3;
+ UINT32 t_faw;
+ UINT32 t_data_en;
+ UINT32 t_wdata_en;
+ UINT32 ModeReg;
+ UINT32 ExtModeReg;
+} PL341_DMC_CONFIG;
+
+/* Memory config bit fields */
+#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9 0x1
+#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10 0x2
+#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11 0x3
+#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12 0x4
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11 (0x0 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12 (0x1 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13 (0x2 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14 (0x3 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15 (0x4 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16 (0x5 << 3)
+#define DMC_MEMORY_CONFIG_BURST_2 (0x1 << 15)
+#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15)
+#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15)
+#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21)
+
+#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0)
+#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0)
+#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2)
+#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3)
+#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4)
+#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6)
+
+//
+// DMC Configuration Register Map
+//
+#define DMC_STATUS_REG 0x00
+#define DMC_COMMAND_REG 0x04
+#define DMC_DIRECT_CMD_REG 0x08
+#define DMC_MEMORY_CONFIG_REG 0x0C
+#define DMC_REFRESH_PRD_REG 0x10
+#define DMC_CAS_LATENCY_REG 0x14
+#define DMC_WRITE_LATENCY_REG 0x18
+#define DMC_T_MRD_REG 0x1C
+#define DMC_T_RAS_REG 0x20
+#define DMC_T_RC_REG 0x24
+#define DMC_T_RCD_REG 0x28
+#define DMC_T_RFC_REG 0x2C
+#define DMC_T_RP_REG 0x30
+#define DMC_T_RRD_REG 0x34
+#define DMC_T_WR_REG 0x38
+#define DMC_T_WTR_REG 0x3C
+#define DMC_T_XP_REG 0x40
+#define DMC_T_XSR_REG 0x44
+#define DMC_T_ESR_REG 0x48
+#define DMC_MEMORY_CFG2_REG 0x4C
+#define DMC_MEMORY_CFG3_REG 0x50
+#define DMC_T_FAW_REG 0x54
+#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */
+#define DMC_T_WRLAT_DIFF 0x60 /* DFI write data enable register */
+
+// Returns the state of the memory controller:
+#define DMC_STATUS_CONFIG 0x0
+#define DMC_STATUS_READY 0x1
+#define DMC_STATUS_PAUSED 0x2
+#define DMC_STATUS_LOWPOWER 0x3
+
+// Changes the state of the memory controller:
+#define DMC_COMMAND_GO 0x0
+#define DMC_COMMAND_SLEEP 0x1
+#define DMC_COMMAND_WAKEUP 0x2
+#define DMC_COMMAND_PAUSE 0x3
+#define DMC_COMMAND_CONFIGURE 0x4
+#define DMC_COMMAND_ACTIVEPAUSE 0x7
+
+// Determines the command required
+#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL 0x0
+#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH (0x1 << 18)
+#define DMC_DIRECT_CMD_MEMCMD_MODEREG (0x2 << 18)
+#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG (0x2 << 18)
+#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18)
+#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22)
+#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16)
+#define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20)
+
+
+//
+// AXI ID configuration register map
+//
+#define DMC_ID_0_CFG_REG 0x100
+#define DMC_ID_1_CFG_REG 0x104
+#define DMC_ID_2_CFG_REG 0x108
+#define DMC_ID_3_CFG_REG 0x10C
+#define DMC_ID_4_CFG_REG 0x110
+#define DMC_ID_5_CFG_REG 0x114
+#define DMC_ID_6_CFG_REG 0x118
+#define DMC_ID_7_CFG_REG 0x11C
+#define DMC_ID_8_CFG_REG 0x120
+#define DMC_ID_9_CFG_REG 0x124
+#define DMC_ID_10_CFG_REG 0x128
+#define DMC_ID_11_CFG_REG 0x12C
+#define DMC_ID_12_CFG_REG 0x130
+#define DMC_ID_13_CFG_REG 0x134
+#define DMC_ID_14_CFG_REG 0x138
+#define DMC_ID_15_CFG_REG 0x13C
+
+// Set the QoS
+#define DMC_ID_CFG_QOS_DISABLE 0
+#define DMC_ID_CFG_QOS_ENABLE 1
+#define DMC_ID_CFG_QOS_MIN 2
+
+
+//
+// Chip configuration register map
+//
+#define DMC_CHIP_0_CFG_REG 0x200
+#define DMC_CHIP_1_CFG_REG 0x204
+#define DMC_CHIP_2_CFG_REG 0x208
+#define DMC_CHIP_3_CFG_REG 0x20C
+
+//
+// User Defined Pins
+//
+#define DMC_USER_STATUS_REG 0x300
+#define DMC_USER_0_CFG_REG 0x304
+#define DMC_USER_1_CFG_REG 0x308
+#define DMC_FEATURE_CRTL_REG 0x30C
+#define DMC_USER_2_CFG_REG 0x310
+
+
+//
+// PHY Register Settings
+//
+#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset
+#define PHY_PTM_IOTERM 0xE04
+#define PHY_PTM_PLL_EN 0xe0c
+#define PHY_PTM_PLL_RANGE 0xe18
+#define PHY_PTM_FEEBACK_DIV 0xe1c
+#define PHY_PTM_RCLK_DIV 0xe20
+#define PHY_PTM_LOCK_STATUS 0xe28
+#define PHY_PTM_INIT_DONE 0xe34
+#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8
+#define PHY_PTM_SQU_TRAINING 0xee8
+#define PHY_PTM_SQU_STAT 0xeec
+
+// ==============================================================================
+// PIPD 40G DDR2/DDR3 PHY Register definitions
+//
+// Offsets from APB Base Address
+// ==============================================================================
+#define PHY_BYTE0_OFFSET 0x000
+#define PHY_BYTE1_OFFSET 0x200
+#define PHY_BYTE2_OFFSET 0x400
+#define PHY_BYTE3_OFFSET 0x600
+
+#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust
+#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust
+#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust
+#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust
+
+#define PHY_BYTE0_IOSTR_OFFSET 0x004
+#define PHY_BYTE1_IOSTR_OFFSET 0x204
+#define PHY_BYTE2_IOSTR_OFFSET 0x404
+#define PHY_BYTE3_IOSTR_OFFSET 0x604
+
+
+;//--------------------------------------------------------------------------
+
+// DFI Clock ranges:
+
+#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0
+#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1
+#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2
+#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3
+#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4
+#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5
+#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6
+
+
+
+#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz
+
+//--------------------------------------------------------------------------
+
+
+// PLL Range
+
+#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
+#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
+#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
+#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
+#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0
+#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1
+
+
+// PHY Reset in SCC
+
+#define SCC_PHY_RST_REG_OFF 0xA0
+#define SCC_REMAP_REG_OFF 0x00
+#define SCC_PHY_RST0_MASK 1 // Active LOW PHY0 reset
+#define SCC_PHY_RST0_SHFT 0 // Active LOW PHY0 reset
+#define SCC_PHY_RST1_MASK 0x100 // Active LOW PHY1 reset
+#define SCC_PHY_RST1_SHFT 8 // Active LOW PHY1 reset
+
+#define TC_UIOLHNC_MASK 0x000003C0
+#define TC_UIOLHNC_SHIFT 0x6
+#define TC_UIOLHPC_MASK 0x0000003F
+#define TC_UIOLHPC_SHIFT 0x2
+#define TC_UIOHOCT_MASK 0x2
+#define TC_UIOHOCT_SHIFT 0x1
+#define TC_UIOHSTOP_SHIFT 0x0
+#define TC_UIOLHXC_VALUE 0x4
+
+#define PHY_PTM_SQU_TRAINING_ENABLE 0x1
+#define PHY_PTM_SQU_TRAINING_DISABLE 0x0
+
+
+//--------------------------------------
+// JEDEC DDR2 Device Register definitions and settings
+//--------------------------------------
+#define DDR_MODESET_SHFT 14
+#define DDR_MODESET_MR 0x0 ;// Mode register
+#define DDR_MODESET_EMR 0x1 ;// Extended Mode register
+#define DDR_MODESET_EMR2 0x2
+#define DDR_MODESET_EMR3 0x3
+
+//
+// Extended Mode Register settings
+//
+#define DDR_EMR_OCD_MASK 0x0000380
+#define DDR_EMR_OCD_SHIFT 0x7
+#define DDR_EMR_RTT_MASK 0x00000044 // DDR2 Device RTT (ODT) settings
+#define DDR_EMR_RTT_SHIFT 0x2
+#define DDR_EMR_ODS_MASK 0x00000002 // DDR2 Output Drive Strength
+#define DDR_EMR_ODS_SHIFT 0x0001
+
+// Termination Values:
+#define DDR_EMR_RTT_50R 0x00000044 // DDR2 50 Ohm termination
+#define DDR_EMR_RTT_75R 0x00000004 // DDR2 75 Ohm termination
+#define DDR_EMR_RTT_150 0x00000040 // DDR2 150 Ohm termination
+
+// Output Drive Strength Values:
+#define DDR_EMR_ODS_FULL 0x0 // DDR2 Full Drive Strength
+#define DDR_EMR_ODS_HALF 0x1 // DDR2 Half Drive Strength
+
+// OCD values
+#define DDR_EMR_OCD_DEFAULT 0x7
+#define DDR_EMR_OCD_NS 0x0
+
+#define DDR_EMR_ODS_VAL DDR_EMR_ODS_FULL
+
+#define DDR_SDRAM_START_ADDR 0x10000000
+
+
+// ----------------------------------------
+// PHY IOTERM values
+// ----------------------------------------
+#define PHY_PTM_IOTERM_OFF 0x0
+#define PHY_PTM_IOTERM_150R 0x1
+#define PHY_PTM_IOTERM_75R 0x2
+#define PHY_PTM_IOTERM_50R 0x3
+
+#define PHY_BYTE_IOSTR_60OHM 0x0
+#define PHY_BYTE_IOSTR_40OHM 0x1
+#define PHY_BYTE_IOSTR_30OHM 0x2
+#define PHY_BYTE_IOSTR_30AOHM 0x3
+
+#define DDR2_MR_BURST_LENGTH_4 (2)
+#define DDR2_MR_BURST_LENGTH_8 (3)
+#define DDR2_MR_DLL_RESET (1 << 8)
+#define DDR2_MR_CAS_LATENCY_4 (4 << 4)
+#define DDR2_MR_CAS_LATENCY_5 (5 << 4)
+#define DDR2_MR_CAS_LATENCY_6 (6 << 4)
+#define DDR2_MR_WR_CYCLES_2 (1 << 9)
+#define DDR2_MR_WR_CYCLES_3 (2 << 9)
+#define DDR2_MR_WR_CYCLES_4 (3 << 9)
+#define DDR2_MR_WR_CYCLES_5 (4 << 9)
+#define DDR2_MR_WR_CYCLES_6 (5 << 9)
+
+
+VOID PL341DmcInit (
+ IN PL341_DMC_CONFIG *config
+ );
+
+VOID PL341DmcPhyInit (
+ IN UINTN DmcPhyBase
+ );
+
+VOID PL341DmcTrainPHY (
+ IN UINTN DmcPhyBase
+ );
+
+#endif /* _PL341DMC_H_ */
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef PL354SMC_H_\r
+#define PL354SMC_H_\r
+\r
+#define PL354_SMC_DIRECT_CMD_OFFSET 0x10\r
+#define PL354_SMC_SET_CYCLES_OFFSET 0x14\r
+#define PL354_SMC_SET_OPMODE_OFFSET 0x18\r
+\r
+#define PL354_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)\r
+#define PL354_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)\r
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)\r
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)\r
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)\r
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)\r
+#define PL354_SMC_DIRECT_CMD_ADDR_CS(interf,chip) (((interf) << 25) | ((chip) << 23))\r
+\r
+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)\r
+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)\r
+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)\r
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)\r
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)\r
+#define PL354_SMC_SET_OPMODE_SET_BAA (1 << 10)\r
+#define PL354_SMC_SET_OPMODE_SET_ADV (1 << 11)\r
+#define PL354_SMC_SET_OPMODE_SET_BLS (1 << 12)\r
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)\r
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)\r
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)\r
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)\r
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)\r
+\r
+\r
+#endif\r
#ifndef __SP805_WATCHDOG_H__\r
#define __SP805_WATCHDOG_H__\r
\r
-#include <Base.h>\r
-#include <ArmPlatform.h>\r
-\r
// SP805 Watchdog Registers\r
-#define SP805_WDOG_LOAD_REG (SP805_WDOG_BASE + 0x000)\r
-#define SP805_WDOG_CURRENT_REG (SP805_WDOG_BASE + 0x004)\r
-#define SP805_WDOG_CONTROL_REG (SP805_WDOG_BASE + 0x008)\r
-#define SP805_WDOG_INT_CLR_REG (SP805_WDOG_BASE + 0x00C)\r
-#define SP805_WDOG_RAW_INT_STS_REG (SP805_WDOG_BASE + 0x010)\r
-#define SP805_WDOG_MSK_INT_STS_REG (SP805_WDOG_BASE + 0x014)\r
-#define SP805_WDOG_LOCK_REG (SP805_WDOG_BASE + 0xC00)\r
-\r
-#define SP805_WDOG_PERIPH_ID0 (SP805_WDOG_BASE + 0xFE0)\r
-#define SP805_WDOG_PERIPH_ID1 (SP805_WDOG_BASE + 0xFE4)\r
-#define SP805_WDOG_PERIPH_ID2 (SP805_WDOG_BASE + 0xFE8)\r
-#define SP805_WDOG_PERIPH_ID3 (SP805_WDOG_BASE + 0xFEC)\r
-\r
-#define SP805_WDOG_PCELL_ID0 (SP805_WDOG_BASE + 0xFF0)\r
-#define SP805_WDOG_PCELL_ID1 (SP805_WDOG_BASE + 0xFF4)\r
-#define SP805_WDOG_PCELL_ID2 (SP805_WDOG_BASE + 0xFF8)\r
-#define SP805_WDOG_PCELL_ID3 (SP805_WDOG_BASE + 0xFFC)\r
+#define SP805_WDOG_LOAD_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x000)\r
+#define SP805_WDOG_CURRENT_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x004)\r
+#define SP805_WDOG_CONTROL_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x008)\r
+#define SP805_WDOG_INT_CLR_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x00C)\r
+#define SP805_WDOG_RAW_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x010)\r
+#define SP805_WDOG_MSK_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x014)\r
+#define SP805_WDOG_LOCK_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xC00)\r
+\r
+#define SP805_WDOG_PERIPH_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE0)\r
+#define SP805_WDOG_PERIPH_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE4)\r
+#define SP805_WDOG_PERIPH_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE8)\r
+#define SP805_WDOG_PERIPH_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFEC)\r
+\r
+#define SP805_WDOG_PCELL_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF0)\r
+#define SP805_WDOG_PCELL_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF4)\r
+#define SP805_WDOG_PCELL_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF8)\r
+#define SP805_WDOG_PCELL_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFFC)\r
\r
// Timer control register bit definitions\r
#define SP805_WDOG_CTRL_INTEN BIT0\r
#include <Guid/MemoryTypeInformation.h>
#include <Library/ArmLib.h>
-#include <ArmPlatform.h>
/**
This structure is used by ArmVExpressGetEfiMemoryMap to describes a region of the EFI memory map
/**
Initialize controllers that must setup in the normal world
- This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
in the PEI phase.
**/
#include <Drivers/PL011Uart.h>
-#include <ArmPlatform.h>
/*
\r
**/\r
\r
-#include <Base.h>\r
#include <Uefi.h>\r
#include <PiDxe.h>\r
#include <Library/BaseLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/RealTimeClockLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PcdLib.h>\r
#include <Library/ArmPlatformSysConfigLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/UefiRuntimeServicesTableLib.h>\r
#include <Protocol/RealTimeClock.h>\r
#include <Guid/GlobalVariable.h>\r
-#include <ArmPlatform.h>\r
#include <Drivers/PL031RealTimeClock.h>\r
\r
+#include <ArmPlatform.h>\r
+\r
CHAR16 mTimeZoneVariableName[] = L"PL031_TimeZone";\r
CHAR16 mDaylightVariableName[] = L"PL031_Daylight";\r
BOOLEAN mPL031Initialized = FALSE;\r
EFI_STATUS Status;\r
\r
// Check if this is a PrimeCell Peripheral\r
- if( ( MmioRead8( PL031_RTC_PCELL_ID0 ) != 0x0D )\r
- || ( MmioRead8( PL031_RTC_PCELL_ID1 ) != 0xF0 )\r
- || ( MmioRead8( PL031_RTC_PCELL_ID2 ) != 0x05 )\r
- || ( MmioRead8( PL031_RTC_PCELL_ID3 ) != 0xB1 ) ) {\r
+ if ( (MmioRead8 (PL031_RTC_PCELL_ID0) != 0x0D)\r
+ || (MmioRead8 (PL031_RTC_PCELL_ID1) != 0xF0)\r
+ || (MmioRead8 (PL031_RTC_PCELL_ID2) != 0x05)\r
+ || (MmioRead8 (PL031_RTC_PCELL_ID3) != 0xB1)) {\r
Status = EFI_NOT_FOUND;\r
goto EXIT;\r
}\r
\r
// Check if this PrimeCell Peripheral is the SP805 Watchdog Timer\r
- if( ( MmioRead8( PL031_RTC_PERIPH_ID0 ) != 0x31 )\r
- || ( MmioRead8( PL031_RTC_PERIPH_ID1 ) != 0x10 )\r
- || (( MmioRead8( PL031_RTC_PERIPH_ID2 ) & 0xF) != 0x04 )\r
- || ( MmioRead8( PL031_RTC_PERIPH_ID3 ) != 0x00 ) ) {\r
+ if ( (MmioRead8 (PL031_RTC_PERIPH_ID0) != 0x31)\r
+ || (MmioRead8 (PL031_RTC_PERIPH_ID1) != 0x10)\r
+ || ((MmioRead8 (PL031_RTC_PERIPH_ID2) & 0xF) != 0x04)\r
+ || (MmioRead8 (PL031_RTC_PERIPH_ID3) != 0x00)) {\r
Status = EFI_NOT_FOUND;\r
goto EXIT;\r
}\r
}\r
\r
// Ensure interrupts are masked. We do not want RTC interrupts in UEFI\r
- if ( (MmioRead32( PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER ) & PL031_SET_IRQ_MASK) != PL031_SET_IRQ_MASK ) {\r
- MmioOr32( PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, PL031_SET_IRQ_MASK);\r
+ if ((MmioRead32 (PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER) & PL031_SET_IRQ_MASK) != PL031_SET_IRQ_MASK) {\r
+ MmioOr32 (PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, PL031_SET_IRQ_MASK);\r
}\r
\r
// Clear any existing interrupts\r
- if ( (MmioRead32( PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER ) & PL031_IRQ_TRIGGERED) == PL031_IRQ_TRIGGERED ) {\r
- MmioOr32( PL031_RTC_ICR_IRQ_CLEAR_REGISTER, PL031_CLEAR_IRQ);\r
+ if ((MmioRead32 (PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER) & PL031_IRQ_TRIGGERED) == PL031_IRQ_TRIGGERED) {\r
+ MmioOr32 (PL031_RTC_ICR_IRQ_CLEAR_REGISTER, PL031_CLEAR_IRQ);\r
}\r
\r
// Start the clock counter\r
- if ( (MmioRead32( PL031_RTC_CR_CONTROL_REGISTER ) & PL031_RTC_ENABLED) != PL031_RTC_ENABLED ) {\r
- MmioOr32( PL031_RTC_CR_CONTROL_REGISTER, PL031_RTC_ENABLED);\r
+ if ((MmioRead32 (PL031_RTC_CR_CONTROL_REGISTER) & PL031_RTC_ENABLED) != PL031_RTC_ENABLED) {\r
+ MmioOr32 (PL031_RTC_CR_CONTROL_REGISTER, PL031_RTC_ENABLED);\r
}\r
\r
mPL031Initialized = TRUE;\r
UINTN ss;\r
UINTN J;\r
\r
- if( Time->Daylight == TRUE) {\r
+ if (Time->Daylight == TRUE) {\r
\r
}\r
\r
\r
JulianDate = Time->Day + ((153*m + 2)/5) + (365*y) + (y/4) - (y/100) + (y/400) - 32045;\r
\r
- ASSERT( JulianDate > EPOCH_JULIAN_DATE );\r
+ ASSERT(JulianDate > EPOCH_JULIAN_DATE);\r
EpochDays = JulianDate - EPOCH_JULIAN_DATE;\r
\r
EpochSeconds = (EpochDays * SEC_PER_DAY) + ((UINTN)Time->Hour * SEC_PER_HOUR) + (Time->Minute * SEC_PER_MIN) + Time->Second;\r
if (Time->Day < 1 ||\r
Time->Day > DayOfMonth[Time->Month - 1] ||\r
(Time->Month == 2 && (!IsLeapYear (Time) && Time->Day > 28))\r
- ) {\r
+ ) {\r
return FALSE;\r
}\r
\r
UINTN *Daylight = 0;\r
\r
// Initialize the hardware if not already done\r
- if( !mPL031Initialized ) {\r
- Status = InitializePL031();\r
+ if (!mPL031Initialized) {\r
+ Status = InitializePL031 ();\r
if (EFI_ERROR (Status)) {\r
goto EXIT;\r
}\r
Status = ArmPlatformSysConfigGet (SYS_CFG_RTC, &EpochSeconds);\r
if (Status == EFI_UNSUPPORTED) {\r
// Battery backed up hardware RTC does not exist, revert to PL031\r
- EpochSeconds = MmioRead32( PL031_RTC_DR_DATA_REGISTER );\r
+ EpochSeconds = MmioRead32 (PL031_RTC_DR_DATA_REGISTER);\r
Status = EFI_SUCCESS;\r
} else if (EFI_ERROR (Status)) {\r
// Battery backed up hardware RTC exists but could not be read due to error. Abort.\r
} else {\r
// Battery backed up hardware RTC exists and we read the time correctly from it.\r
// Now sync the PL031 to the new time.\r
- MmioWrite32( PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);\r
+ MmioWrite32 (PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);\r
}\r
\r
// Ensure Time is a valid pointer\r
- if( Time == NULL ) {\r
+ if (Time == NULL) {\r
Status = EFI_INVALID_PARAMETER;\r
goto EXIT;\r
}\r
// Get the current time zone information from non-volatile storage\r
TimeZone = (INT16 *)GetVariable(mTimeZoneVariableName, &gEfiGlobalVariableGuid);\r
\r
- if( TimeZone == NULL ) {\r
+ if (TimeZone == NULL) {\r
// The time zone variable does not exist in non-volatile storage, so create it.\r
Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;\r
// Store it\r
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
sizeof(Time->TimeZone),\r
&(Time->TimeZone)\r
- );\r
+ );\r
if (EFI_ERROR (Status)) {\r
DEBUG((EFI_D_ERROR,"LibGetTime: ERROR: TimeZone\n"));\r
goto EXIT;\r
FreePool(TimeZone);\r
\r
// Check TimeZone bounds: -1440 to 1440 or 2047\r
- if( (( Time->TimeZone < -1440 ) || ( Time->TimeZone > 1440 ))\r
- && ( Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) ) {\r
+ if (((Time->TimeZone < -1440) || (Time->TimeZone > 1440))\r
+ && (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE)) {\r
Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;\r
}\r
\r
// Adjust for the correct time zone\r
- if( Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE ) {\r
+ if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) {\r
EpochSeconds += Time->TimeZone * SEC_PER_MIN;\r
}\r
}\r
// Get the current daylight information from non-volatile storage\r
Daylight = (UINTN *)GetVariable(mDaylightVariableName, &gEfiGlobalVariableGuid);\r
\r
- if( Daylight == NULL ) {\r
+ if (Daylight == NULL) {\r
// The daylight variable does not exist in non-volatile storage, so create it.\r
Time->Daylight = 0;\r
// Store it\r
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
sizeof(Time->Daylight),\r
&(Time->Daylight)\r
- );\r
+ );\r
if (EFI_ERROR (Status)) {\r
DEBUG((EFI_D_ERROR,"LibGetTime: ERROR: Daylight\n"));\r
goto EXIT;\r
FreePool(Daylight);\r
\r
// Adjust for the correct period\r
- if( (Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT ) {\r
+ if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) {\r
// Convert to adjusted time, i.e. spring forwards one hour\r
EpochSeconds += SEC_PER_HOUR;\r
}\r
}\r
\r
// Convert from internal 32-bit time to UEFI time\r
- EpochToEfiTime( EpochSeconds, Time );\r
+ EpochToEfiTime (EpochSeconds, Time);\r
\r
// Update the Capabilities info\r
- if( Capabilities != NULL ) {\r
- Capabilities->Resolution = PL031_COUNTS_PER_SECOND; /* PL031 runs at frequency 1Hz */\r
- Capabilities->Accuracy = PL031_PPM_ACCURACY; /* Accuracy in ppm multiplied by 1,000,000, e.g. for 50ppm set 50,000,000 */\r
- Capabilities->SetsToZero = FALSE; /* FALSE: Setting the time does not clear the values below the resolution level */\r
+ if (Capabilities != NULL) {\r
+ // PL031 runs at frequency 1Hz\r
+ Capabilities->Resolution = PL031_COUNTS_PER_SECOND;\r
+ // Accuracy in ppm multiplied by 1,000,000, e.g. for 50ppm set 50,000,000\r
+ Capabilities->Accuracy = (UINT32)PcdGet32 (PcdPL031RtcPpmAccuracy);\r
+ // FALSE: Setting the time does not clear the values below the resolution level\r
+ Capabilities->SetsToZero = FALSE;\r
}\r
\r
EXIT:\r
// to the range 1998 .. 2011\r
\r
// Check the input parameters' range.\r
- if ( ( Time->Year < 1998 ) ||\r
- ( Time->Year > 2099 ) ||\r
- ( Time->Month < 1 ) ||\r
- ( Time->Month > 12 ) ||\r
- (!DayValid (Time) ) ||\r
- ( Time->Hour > 23 ) ||\r
- ( Time->Minute > 59 ) ||\r
- ( Time->Second > 59 ) ||\r
- ( Time->Nanosecond > 999999999 ) ||\r
- ( !((Time->TimeZone == EFI_UNSPECIFIED_TIMEZONE) || ((Time->TimeZone >= -1440) && (Time->TimeZone <= 1440))) ) ||\r
- ( Time->Daylight & (~(EFI_TIME_ADJUST_DAYLIGHT | EFI_TIME_IN_DAYLIGHT)) )\r
- ) {\r
+ if ((Time->Year < 1998) ||\r
+ (Time->Year > 2099) ||\r
+ (Time->Month < 1 ) ||\r
+ (Time->Month > 12 ) ||\r
+ (!DayValid (Time) ) ||\r
+ (Time->Hour > 23 ) ||\r
+ (Time->Minute > 59 ) ||\r
+ (Time->Second > 59 ) ||\r
+ (Time->Nanosecond > 999999999) ||\r
+ (!((Time->TimeZone == EFI_UNSPECIFIED_TIMEZONE) || ((Time->TimeZone >= -1440) && (Time->TimeZone <= 1440)))) ||\r
+ (Time->Daylight & (~(EFI_TIME_ADJUST_DAYLIGHT | EFI_TIME_IN_DAYLIGHT)))\r
+ ) {\r
Status = EFI_INVALID_PARAMETER;\r
goto EXIT;\r
}\r
\r
// Initialize the hardware if not already done\r
- if( !mPL031Initialized ) {\r
- Status = InitializePL031();\r
+ if (!mPL031Initialized) {\r
+ Status = InitializePL031 ();\r
if (EFI_ERROR (Status)) {\r
goto EXIT;\r
}\r
}\r
\r
- EpochSeconds = EfiTimeToEpoch( Time );\r
+ EpochSeconds = EfiTimeToEpoch (Time);\r
\r
// Adjust for the correct time zone, i.e. convert to UTC time zone\r
- if( Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE ) {\r
+ if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) {\r
EpochSeconds -= Time->TimeZone * SEC_PER_MIN;\r
}\r
\r
// TODO: Automatic Daylight activation\r
\r
// Adjust for the correct period\r
- if( (Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT ) {\r
+ if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) {\r
// Convert to un-adjusted time, i.e. fall back one hour\r
EpochSeconds -= SEC_PER_HOUR;\r
}\r
\r
\r
// Set the PL031\r
- MmioWrite32( PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);\r
+ MmioWrite32 (PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);\r
\r
// The accesses to Variable Services can be very slow, because we may be writing to Flash.\r
// Do this after having set the RTC.\r
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
sizeof(Time->TimeZone),\r
&(Time->TimeZone)\r
- );\r
+ );\r
if (EFI_ERROR (Status)) {\r
DEBUG((EFI_D_ERROR,"LibSetTime: ERROR: TimeZone\n"));\r
goto EXIT;\r
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
sizeof(Time->Daylight),\r
&(Time->Daylight)\r
- );\r
+ );\r
if (EFI_ERROR (Status)) {\r
DEBUG((EFI_D_ERROR,"LibSetTime: ERROR: Daylight\n"));\r
goto EXIT;\r
&Handle,\r
&gEfiRealTimeClockArchProtocolGuid, NULL,\r
NULL\r
- );\r
+ );\r
\r
return Status;\r
}\r
IoLib\r
UefiLib\r
DebugLib\r
+ PcdLib\r
ArmPlatformSysConfigLib\r
+ \r
+[Pcd]\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy\r
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Drivers/SP804Timer.h>
-#include <ArmPlatform.h>
+
+#define SP804_TIMER_METRONOME_BASE (UINTN)PcdGet32 (PcdSP804TimerPerformanceBase)
+#define SP804_TIMER_PERFORMANCE_BASE (UINTN)PcdGet32 (PcdSP804TimerMetronomeBase)
// Setup SP810's Timer2 for managing delay functions. And Timer3 for Performance counter
// Note: ArmVE's Timer0 and Timer1 are used by TimerDxe.
)
{
// Check if Timer 2 is already initialized
- if (MmioRead32(SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
+ if (MmioRead32(SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
return RETURN_SUCCESS;
} else {
// Configure timer 2 for one shot operation, 32 bits, no prescaler, and interrupt disabled
- MmioOr32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
+ MmioOr32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
// Preload the timer count register
- MmioWrite32 (SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, 1);
+ MmioWrite32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_LOAD_REG, 1);
// Enable the timer
- MmioOr32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
+ MmioOr32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
}
// Check if Timer 3 is already initialized
- if (MmioRead32(SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
+ if (MmioRead32(SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
return RETURN_SUCCESS;
} else {
// Configure timer 3 for free running operation, 32 bits, no prescaler, interrupt disabled
- MmioOr32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
+ MmioOr32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
// Enable the timer
- MmioOr32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
+ MmioOr32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
}
return RETURN_SUCCESS;
UINTN Index;
// Reload the counter for each 1Mhz to avoid an overflow in the load value
- for (Index = 0; Index < (UINTN)PcdGet32(PcdSP804FrequencyInMHz); Index++) {
+ for (Index = 0; Index < (UINTN)PcdGet32(PcdSP804TimerFrequencyInMHz); Index++) {
// load the timer count register
- MmioWrite32 (SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, MicroSeconds);
+ MmioWrite32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_LOAD_REG, MicroSeconds);
- while (MmioRead32 (SP804_TIMER2_BASE + SP804_TIMER_CURRENT_REG) > 0) {
+ while (MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG) > 0) {
;
}
}
MicroSeconds += ((UINT32)NanoSeconds % 1000) == 0 ? 0 : 1;
// Reload the counter for each 1Mhz to avoid an overflow in the load value
- for (Index = 0; Index < (UINTN)PcdGet32(PcdSP804FrequencyInMHz); Index++) {
+ for (Index = 0; Index < (UINTN)PcdGet32(PcdSP804TimerFrequencyInMHz); Index++) {
// load the timer count register
- MmioWrite32 (SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, MicroSeconds);
+ MmioWrite32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_LOAD_REG, MicroSeconds);
- while (MmioRead32 (SP804_TIMER2_BASE + SP804_TIMER_CURRENT_REG) > 0) {
+ while (MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG) > 0) {
;
}
}
// Free running 64-bit/32-bit counter is needed here.
// Don't think we need this to boot, just to do performance profile
UINT64 Value;
- Value = MmioRead32 (SP804_TIMER3_BASE + SP804_TIMER_CURRENT_REG);
+ Value = MmioRead32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CURRENT_REG);
ASSERT(Value > 0);
return Value;
}
BaseLib
[Pcd]
- gArmPlatformTokenSpaceGuid.PcdSP804FrequencyInMHz
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase
gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz
)\r
{\r
EFI_STATUS Status;\r
- EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;\r
- ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR* EfiMemoryMap;\r
- UINTN Index;\r
UINTN SystemMemoryTop;\r
UINTN UefiMemoryBase;\r
- UINTN UefiMemorySize;\r
\r
DEBUG ((EFI_D_ERROR, "Memory Init PEIM Loaded\n"));\r
\r
*\r
**/\r
\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
#include <Library/ArmMPCoreMailBoxLib.h>\r
#include <Chipset/ArmV7.h>\r
#include <Drivers/PL390Gic.h>\r
*\r
**/\r
\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
#include <Chipset/ArmV7.h>\r
\r
#include "PrePeiCore.h"\r
*\r
**/\r
\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#ifndef __PREPEICORE_H_\r
#define __PREPEICORE_H_\r
\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
#include <PiPei.h>\r
#include <Ppi/TemporaryRamSupport.h>\r
\r
\r
gArmTokenSpaceGuid.PcdGicDistributorBase\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
+\r
+ gArmTokenSpaceGuid.PcdNormalFvBaseAddress\r
+ gArmTokenSpaceGuid.PcdNormalFvSize\r
//Default Exception Handlers
//============================================================
-
ASM_PFX(PrePiVectorTable):
b _DefaultResetHandler
b _DefaultUndefined