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c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf
EH		 26#include "sysemu/cpus.h"
27#include "topology.h"
c6dc6f63 28
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
53a89e26 44#include "hw/qdev-properties.h"
62fc403f 45#include "hw/cpu/icc_bus.h"
bdeec802 46#ifndef CONFIG_USER_ONLY
0d09e41a 47#include "hw/xen/xen.h"
0d09e41a 48#include "hw/i386/apic_internal.h"
bdeec802
IM		 49#endif
50
5e891bf8
EH		 51
52/* Cache topology CPUID constants: */
53
54/* CPUID Leaf 2 Descriptors */
55
56#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57#define CPUID_2_L1I_32KB_8WAY_64B 0x30
58#define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61/* CPUID Leaf 4 constants: */
62
63/* EAX: */
64#define CPUID_4_TYPE_DCACHE 1
65#define CPUID_4_TYPE_ICACHE 2
66#define CPUID_4_TYPE_UNIFIED 3
67
68#define CPUID_4_LEVEL(l) ((l) << 5)
69
70#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71#define CPUID_4_FULLY_ASSOC (1 << 9)
72
73/* EDX: */
74#define CPUID_4_NO_INVD_SHARING (1 << 0)
75#define CPUID_4_INCLUSIVE (1 << 1)
76#define CPUID_4_COMPLEX_IDX (1 << 2)
77
78#define ASSOC_FULL 0xFF
79
80/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95/* Definitions of the hardcoded cache entries we expose: */
96
97/* L1 data cache: */
98#define L1D_LINE_SIZE 64
99#define L1D_ASSOCIATIVITY 8
100#define L1D_SETS 64
101#define L1D_PARTITIONS 1
102/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105#define L1D_LINES_PER_TAG 1
106#define L1D_SIZE_KB_AMD 64
107#define L1D_ASSOCIATIVITY_AMD 2
108
109/* L1 instruction cache: */
110#define L1I_LINE_SIZE 64
111#define L1I_ASSOCIATIVITY 8
112#define L1I_SETS 64
113#define L1I_PARTITIONS 1
114/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117#define L1I_LINES_PER_TAG 1
118#define L1I_SIZE_KB_AMD 64
119#define L1I_ASSOCIATIVITY_AMD 2
120
121/* Level 2 unified cache: */
122#define L2_LINE_SIZE 64
123#define L2_ASSOCIATIVITY 16
124#define L2_SETS 4096
125#define L2_PARTITIONS 1
126/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130#define L2_LINES_PER_TAG 1
131#define L2_SIZE_KB_AMD 512
132
133/* No L3 cache: */
134#define L3_SIZE_KB 0 /* disabled */
135#define L3_ASSOCIATIVITY 0 /* disabled */
136#define L3_LINES_PER_TAG 0 /* disabled */
137#define L3_LINE_SIZE 0 /* disabled */
138
139/* TLB definitions: */
140
141#define L1_DTLB_2M_ASSOC 1
142#define L1_DTLB_2M_ENTRIES 255
143#define L1_DTLB_4K_ASSOC 1
144#define L1_DTLB_4K_ENTRIES 255
145
146#define L1_ITLB_2M_ASSOC 1
147#define L1_ITLB_2M_ENTRIES 255
148#define L1_ITLB_4K_ASSOC 1
149#define L1_ITLB_4K_ENTRIES 255
150
151#define L2_DTLB_2M_ASSOC 0 /* disabled */
152#define L2_DTLB_2M_ENTRIES 0 /* disabled */
153#define L2_DTLB_4K_ASSOC 4
154#define L2_DTLB_4K_ENTRIES 512
155
156#define L2_ITLB_2M_ASSOC 0 /* disabled */
157#define L2_ITLB_2M_ENTRIES 0 /* disabled */
158#define L2_ITLB_4K_ASSOC 4
159#define L2_ITLB_4K_ENTRIES 512
160
161
162
99b88a17
IM		 163static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165{
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173}
174
c6dc6f63
AP		 175/* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188};
189static const char *ext_feature_name[] = {
f370be3c 190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 191 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 192 "tm2", "ssse3", "cid", NULL,
e117f772 193 "fma", "cx16", "xtpr", "pdcm",
434acb81 194 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 196 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 197 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 198};
3b671a40
EH		 199/* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
c6dc6f63 204static const char *ext2_feature_name[] = {
3b671a40
EH		 205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 212 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 213};
214static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 217 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 222 NULL, NULL, NULL, NULL,
223};
224
89e49c8b
EH		 225static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234};
235
c6dc6f63 236static const char *kvm_feature_name[] = {
c3d39807
DS		 237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 245};
246
296acb64
JR		 247static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256};
257
a9321a4d 258static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263};
264
5ef57876
EH		 265typedef struct FeatureWordInfo {
266 const char **feat_names;
04d104b6
EH		 267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
5ef57876
EH		 271} FeatureWordInfo;
272
273static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
89e49c8b
EH		 290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
bffd67b0
EH		 294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
bffd67b0 307 },
5ef57876
EH		 308};
309
8e8aba50
EH		 310typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315} X86RegisterInfo32;
316
317#define REGISTER(reg) \
318 [R_##reg] = { .name = #reg, .qapi_enum = X86_C_P_U_REGISTER32_##reg }
319X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328};
329#undef REGISTER
330
331
8b4beddc
EH		 332const char *get_register_name_32(unsigned int reg)
333{
31ccdde2 334 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 335 return NULL;
336 }
8e8aba50 337 return x86_reg_info_32[reg].name;
8b4beddc
EH		 338}
339
c6dc6f63
AP		 340/* collects per-function cpuid data
341 */
342typedef struct model_features_t {
343 uint32_t *guest_feat;
344 uint32_t *host_feat;
bffd67b0 345 FeatureWord feat_word;
8b4beddc 346} model_features_t;
c6dc6f63
AP		 347
348int check_cpuid = 0;
349int enforce_cpuid = 0;
350
dc59944b
MT		 351static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
352 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 353 (1 << KVM_FEATURE_CLOCKSOURCE2) |
354 (1 << KVM_FEATURE_ASYNC_PF) |
355 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 356 (1 << KVM_FEATURE_PV_EOI) |
dc59944b 357 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
dc59944b 358
29694758 359void disable_kvm_pv_eoi(void)
dc59944b 360{
29694758 361 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
dc59944b
MT		 362}
363
bb44e0d1
JK		 364void host_cpuid(uint32_t function, uint32_t count,
365 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 366{
367#if defined(CONFIG_KVM)
a1fd24af
AL		 368 uint32_t vec[4];
369
370#ifdef __x86_64__
371 asm volatile("cpuid"
372 : "=a"(vec[0]), "=b"(vec[1]),
373 "=c"(vec[2]), "=d"(vec[3])
374 : "0"(function), "c"(count) : "cc");
375#else
376 asm volatile("pusha \n\t"
377 "cpuid \n\t"
378 "mov %%eax, 0(%2) \n\t"
379 "mov %%ebx, 4(%2) \n\t"
380 "mov %%ecx, 8(%2) \n\t"
381 "mov %%edx, 12(%2) \n\t"
382 "popa"
383 : : "a"(function), "c"(count), "S"(vec)
384 : "memory", "cc");
385#endif
386
bdde476a 387 if (eax)
a1fd24af 388 *eax = vec[0];
bdde476a 389 if (ebx)
a1fd24af 390 *ebx = vec[1];
bdde476a 391 if (ecx)
a1fd24af 392 *ecx = vec[2];
bdde476a 393 if (edx)
a1fd24af 394 *edx = vec[3];
bdde476a
AP		 395#endif
396}
c6dc6f63
AP		 397
398#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
399
400/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
401 * a substring. ex if !NULL points to the first char after a substring,
402 * otherwise the string is assumed to sized by a terminating nul.
403 * Return lexical ordering of *s1:*s2.
404 */
405static int sstrcmp(const char *s1, const char *e1, const char *s2,
406 const char *e2)
407{
408 for (;;) {
409 if (!*s1 || !*s2 || *s1 != *s2)
410 return (*s1 - *s2);
411 ++s1, ++s2;
412 if (s1 == e1 && s2 == e2)
413 return (0);
414 else if (s1 == e1)
415 return (*s2);
416 else if (s2 == e2)
417 return (*s1);
418 }
419}
420
421/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
422 * '|' delimited (possibly empty) strings in which case search for a match
423 * within the alternatives proceeds left to right. Return 0 for success,
424 * non-zero otherwise.
425 */
426static int altcmp(const char *s, const char *e, const char *altstr)
427{
428 const char *p, *q;
429
430 for (q = p = altstr; ; ) {
431 while (*p && *p != '|')
432 ++p;
433 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
434 return (0);
435 if (!*p)
436 return (1);
437 else
438 q = ++p;
439 }
440}
441
442/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 443 * *pval and return true, otherwise return false
c6dc6f63 444 */
e41e0fc6
JK		 445static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
446 const char **featureset)
c6dc6f63
AP		 447{
448 uint32_t mask;
449 const char **ppc;
e41e0fc6 450 bool found = false;
c6dc6f63 451
e41e0fc6 452 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 453 if (*ppc && !altcmp(s, e, *ppc)) {
454 *pval |= mask;
e41e0fc6 455 found = true;
c6dc6f63 456 }
e41e0fc6
JK		 457 }
458 return found;
c6dc6f63
AP		 459}
460
5ef57876
EH		 461static void add_flagname_to_bitmaps(const char *flagname,
462 FeatureWordArray words)
c6dc6f63 463{
5ef57876
EH		 464 FeatureWord w;
465 for (w = 0; w < FEATURE_WORDS; w++) {
466 FeatureWordInfo *wi = &feature_word_info[w];
467 if (wi->feat_names &&
468 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
469 break;
470 }
471 }
472 if (w == FEATURE_WORDS) {
473 fprintf(stderr, "CPU feature %s not found\n", flagname);
474 }
c6dc6f63
AP		 475}
476
477typedef struct x86_def_t {
c6dc6f63
AP		 478 const char *name;
479 uint32_t level;
90e4b0c3
EH		 480 uint32_t xlevel;
481 uint32_t xlevel2;
99b88a17
IM		 482 /* vendor is zero-terminated, 12 character ASCII string */
483 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 484 int family;
485 int model;
486 int stepping;
0514ef2f 487 FeatureWordArray features;
c6dc6f63 488 char model_id[48];
c6dc6f63
AP		 489} x86_def_t;
490
491#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
492#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
493 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
494#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
495 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
496 CPUID_PSE36 | CPUID_FXSR)
497#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
498#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
499 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
500 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
501 CPUID_PAE | CPUID_SEP | CPUID_APIC)
502
551a2dec
AP		 503#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
504 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
505 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
506 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
507 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 508 /* partly implemented:
509 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
510 CPUID_PSE36 (needed for Solaris) */
511 /* missing:
512 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
e71827bc
AJ		 513#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
514 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
515 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
d640045a 516 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
8560efed 517 /* missing:
e71827bc
AJ		 518 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
519 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
520 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
d640045a
AJ		 521 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
522 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
83f7dc28 523 CPUID_EXT_RDRAND */
60032ac0 524#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 525 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
526 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 527 /* missing:
528 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 529#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
530 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 531#define TCG_SVM_FEATURES 0
7073fbad 532#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
cd7f97ca 533 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
111994ee 534 /* missing:
7073fbad
RH		 535 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
536 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
cd7f97ca 537 CPUID_7_0_EBX_RDSEED */
551a2dec 538
7fc9b714 539/* built-in CPU model definitions
c6dc6f63
AP		 540 */
541static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 542 {
543 .name = "qemu64",
544 .level = 4,
99b88a17 545 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 546 .family = 6,
547 .model = 2,
548 .stepping = 3,
0514ef2f 549 .features[FEAT_1_EDX] =
27861ecc 550 PPRO_FEATURES |
c6dc6f63 551 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 552 CPUID_PSE36,
0514ef2f 553 .features[FEAT_1_ECX] =
27861ecc 554 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 555 .features[FEAT_8000_0001_EDX] =
27861ecc 556 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 557 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 558 .features[FEAT_8000_0001_ECX] =
27861ecc 559 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 560 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
561 .xlevel = 0x8000000A,
c6dc6f63
AP		 562 },
563 {
564 .name = "phenom",
565 .level = 5,
99b88a17 566 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 567 .family = 16,
568 .model = 2,
569 .stepping = 3,
0514ef2f 570 .features[FEAT_1_EDX] =
27861ecc 571 PPRO_FEATURES |
c6dc6f63 572 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 573 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 574 .features[FEAT_1_ECX] =
27861ecc 575 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 576 CPUID_EXT_POPCNT,
0514ef2f 577 .features[FEAT_8000_0001_EDX] =
27861ecc 578 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 579 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
580 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 581 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 582 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
583 CPUID_EXT3_CR8LEG,
584 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
585 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 586 .features[FEAT_8000_0001_ECX] =
27861ecc 587 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 588 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 589 .features[FEAT_SVM] =
27861ecc 590 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 591 .xlevel = 0x8000001A,
592 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
593 },
594 {
595 .name = "core2duo",
596 .level = 10,
99b88a17 597 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 598 .family = 6,
599 .model = 15,
600 .stepping = 11,
0514ef2f 601 .features[FEAT_1_EDX] =
27861ecc 602 PPRO_FEATURES |
c6dc6f63 603 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 604 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
605 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 606 .features[FEAT_1_ECX] =
27861ecc 607 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 608 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
609 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 610 .features[FEAT_8000_0001_EDX] =
27861ecc 611 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 612 .features[FEAT_8000_0001_ECX] =
27861ecc 613 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 614 .xlevel = 0x80000008,
615 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
616 },
617 {
618 .name = "kvm64",
619 .level = 5,
99b88a17 620 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 621 .family = 15,
622 .model = 6,
623 .stepping = 1,
624 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 625 .features[FEAT_1_EDX] =
27861ecc 626 PPRO_FEATURES |
c6dc6f63
AP		 627 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
628 CPUID_PSE36,
629 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 630 .features[FEAT_1_ECX] =
27861ecc 631 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 632 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 633 .features[FEAT_8000_0001_EDX] =
27861ecc 634 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 635 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
636 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
637 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
638 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
639 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 640 .features[FEAT_8000_0001_ECX] =
27861ecc 641 0,
c6dc6f63
AP		 642 .xlevel = 0x80000008,
643 .model_id = "Common KVM processor"
644 },
c6dc6f63
AP		 645 {
646 .name = "qemu32",
647 .level = 4,
99b88a17 648 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 649 .family = 6,
650 .model = 3,
651 .stepping = 3,
0514ef2f 652 .features[FEAT_1_EDX] =
27861ecc 653 PPRO_FEATURES,
0514ef2f 654 .features[FEAT_1_ECX] =
27861ecc 655 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 656 .xlevel = 0x80000004,
c6dc6f63 657 },
eafaf1e5
AP		 658 {
659 .name = "kvm32",
660 .level = 5,
99b88a17 661 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 662 .family = 15,
663 .model = 6,
664 .stepping = 1,
0514ef2f 665 .features[FEAT_1_EDX] =
27861ecc 666 PPRO_FEATURES |
eafaf1e5 667 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 668 .features[FEAT_1_ECX] =
27861ecc 669 CPUID_EXT_SSE3,
0514ef2f 670 .features[FEAT_8000_0001_EDX] =
27861ecc 671 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 672 .features[FEAT_8000_0001_ECX] =
27861ecc 673 0,
eafaf1e5
AP		 674 .xlevel = 0x80000008,
675 .model_id = "Common 32-bit KVM processor"
676 },
c6dc6f63
AP		 677 {
678 .name = "coreduo",
679 .level = 10,
99b88a17 680 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 681 .family = 6,
682 .model = 14,
683 .stepping = 8,
0514ef2f 684 .features[FEAT_1_EDX] =
27861ecc 685 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 686 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
687 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 688 .features[FEAT_1_ECX] =
27861ecc 689 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 690 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 691 .features[FEAT_8000_0001_EDX] =
27861ecc 692 CPUID_EXT2_NX,
c6dc6f63
AP		 693 .xlevel = 0x80000008,
694 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
695 },
696 {
697 .name = "486",
58012d66 698 .level = 1,
99b88a17 699 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 700 .family = 4,
b2a856d9 701 .model = 8,
c6dc6f63 702 .stepping = 0,
0514ef2f 703 .features[FEAT_1_EDX] =
27861ecc 704 I486_FEATURES,
c6dc6f63
AP		 705 .xlevel = 0,
706 },
707 {
708 .name = "pentium",
709 .level = 1,
99b88a17 710 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 711 .family = 5,
712 .model = 4,
713 .stepping = 3,
0514ef2f 714 .features[FEAT_1_EDX] =
27861ecc 715 PENTIUM_FEATURES,
c6dc6f63
AP		 716 .xlevel = 0,
717 },
718 {
719 .name = "pentium2",
720 .level = 2,
99b88a17 721 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 722 .family = 6,
723 .model = 5,
724 .stepping = 2,
0514ef2f 725 .features[FEAT_1_EDX] =
27861ecc 726 PENTIUM2_FEATURES,
c6dc6f63
AP		 727 .xlevel = 0,
728 },
729 {
730 .name = "pentium3",
731 .level = 2,
99b88a17 732 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 733 .family = 6,
734 .model = 7,
735 .stepping = 3,
0514ef2f 736 .features[FEAT_1_EDX] =
27861ecc 737 PENTIUM3_FEATURES,
c6dc6f63
AP		 738 .xlevel = 0,
739 },
740 {
741 .name = "athlon",
742 .level = 2,
99b88a17 743 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 744 .family = 6,
745 .model = 2,
746 .stepping = 3,
0514ef2f 747 .features[FEAT_1_EDX] =
27861ecc 748 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 749 CPUID_MCA,
0514ef2f 750 .features[FEAT_8000_0001_EDX] =
27861ecc 751 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 752 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 753 .xlevel = 0x80000008,
c6dc6f63
AP		 754 },
755 {
756 .name = "n270",
757 /* original is on level 10 */
758 .level = 5,
99b88a17 759 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 760 .family = 6,
761 .model = 28,
762 .stepping = 2,
0514ef2f 763 .features[FEAT_1_EDX] =
27861ecc 764 PPRO_FEATURES |
8560efed
AJ		 765 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
766 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 767 /* Some CPUs got no CPUID_SEP */
0514ef2f 768 .features[FEAT_1_ECX] =
27861ecc 769 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 770 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
771 CPUID_EXT_MOVBE,
0514ef2f 772 .features[FEAT_8000_0001_EDX] =
27861ecc 773 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 774 CPUID_EXT2_NX,
0514ef2f 775 .features[FEAT_8000_0001_ECX] =
27861ecc 776 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 777 .xlevel = 0x8000000A,
778 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
779 },
3eca4642
EH		 780 {
781 .name = "Conroe",
6b11322e 782 .level = 4,
99b88a17 783 .vendor = CPUID_VENDOR_INTEL,
3eca4642 784 .family = 6,
ffce9ebb 785 .model = 15,
3eca4642 786 .stepping = 3,
0514ef2f 787 .features[FEAT_1_EDX] =
27861ecc 788 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 789 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
790 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
791 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
792 CPUID_DE | CPUID_FP87,
0514ef2f 793 .features[FEAT_1_ECX] =
27861ecc 794 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 795 .features[FEAT_8000_0001_EDX] =
27861ecc 796 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 797 .features[FEAT_8000_0001_ECX] =
27861ecc 798 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 799 .xlevel = 0x8000000A,
800 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
801 },
802 {
803 .name = "Penryn",
6b11322e 804 .level = 4,
99b88a17 805 .vendor = CPUID_VENDOR_INTEL,
3eca4642 806 .family = 6,
ffce9ebb 807 .model = 23,
3eca4642 808 .stepping = 3,
0514ef2f 809 .features[FEAT_1_EDX] =
27861ecc 810 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 811 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
812 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
813 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
814 CPUID_DE | CPUID_FP87,
0514ef2f 815 .features[FEAT_1_ECX] =
27861ecc 816 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 817 CPUID_EXT_SSE3,
0514ef2f 818 .features[FEAT_8000_0001_EDX] =
27861ecc 819 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 820 .features[FEAT_8000_0001_ECX] =
27861ecc 821 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 822 .xlevel = 0x8000000A,
823 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
824 },
825 {
826 .name = "Nehalem",
6b11322e 827 .level = 4,
99b88a17 828 .vendor = CPUID_VENDOR_INTEL,
3eca4642 829 .family = 6,
ffce9ebb 830 .model = 26,
3eca4642 831 .stepping = 3,
0514ef2f 832 .features[FEAT_1_EDX] =
27861ecc 833 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 834 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
835 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
836 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
837 CPUID_DE | CPUID_FP87,
0514ef2f 838 .features[FEAT_1_ECX] =
27861ecc 839 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 840 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 841 .features[FEAT_8000_0001_EDX] =
27861ecc 842 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 843 .features[FEAT_8000_0001_ECX] =
27861ecc 844 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 845 .xlevel = 0x8000000A,
846 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
847 },
848 {
849 .name = "Westmere",
850 .level = 11,
99b88a17 851 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 852 .family = 6,
853 .model = 44,
854 .stepping = 1,
0514ef2f 855 .features[FEAT_1_EDX] =
27861ecc 856 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 857 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
858 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
859 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
860 CPUID_DE | CPUID_FP87,
0514ef2f 861 .features[FEAT_1_ECX] =
27861ecc 862 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 863 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 864 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 865 .features[FEAT_8000_0001_EDX] =
27861ecc 866 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 867 .features[FEAT_8000_0001_ECX] =
27861ecc 868 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 869 .xlevel = 0x8000000A,
870 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
871 },
872 {
873 .name = "SandyBridge",
874 .level = 0xd,
99b88a17 875 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 876 .family = 6,
877 .model = 42,
878 .stepping = 1,
0514ef2f 879 .features[FEAT_1_EDX] =
27861ecc 880 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 881 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
882 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
883 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
884 CPUID_DE | CPUID_FP87,
0514ef2f 885 .features[FEAT_1_ECX] =
27861ecc 886 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 887 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
888 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
889 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
890 CPUID_EXT_SSE3,
0514ef2f 891 .features[FEAT_8000_0001_EDX] =
27861ecc 892 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 893 CPUID_EXT2_SYSCALL,
0514ef2f 894 .features[FEAT_8000_0001_ECX] =
27861ecc 895 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 896 .xlevel = 0x8000000A,
897 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
898 },
37507094
EH		 899 {
900 .name = "Haswell",
901 .level = 0xd,
99b88a17 902 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 903 .family = 6,
904 .model = 60,
905 .stepping = 1,
0514ef2f 906 .features[FEAT_1_EDX] =
27861ecc 907 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 908 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 909 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 910 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
911 CPUID_DE | CPUID_FP87,
0514ef2f 912 .features[FEAT_1_ECX] =
27861ecc 913 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH		 914 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
915 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
916 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
917 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
918 CPUID_EXT_PCID,
0514ef2f 919 .features[FEAT_8000_0001_EDX] =
27861ecc 920 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 921 CPUID_EXT2_SYSCALL,
0514ef2f 922 .features[FEAT_8000_0001_ECX] =
27861ecc 923 CPUID_EXT3_LAHF_LM,
0514ef2f 924 .features[FEAT_7_0_EBX] =
27861ecc 925 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 926 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
927 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
928 CPUID_7_0_EBX_RTM,
929 .xlevel = 0x8000000A,
930 .model_id = "Intel Core Processor (Haswell)",
931 },
3eca4642
EH		 932 {
933 .name = "Opteron_G1",
934 .level = 5,
99b88a17 935 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 936 .family = 15,
937 .model = 6,
938 .stepping = 1,
0514ef2f 939 .features[FEAT_1_EDX] =
27861ecc 940 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 941 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
942 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
943 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
944 CPUID_DE | CPUID_FP87,
0514ef2f 945 .features[FEAT_1_ECX] =
27861ecc 946 CPUID_EXT_SSE3,
0514ef2f 947 .features[FEAT_8000_0001_EDX] =
27861ecc 948 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH		 949 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
950 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
951 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
952 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
953 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
954 .xlevel = 0x80000008,
955 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
956 },
957 {
958 .name = "Opteron_G2",
959 .level = 5,
99b88a17 960 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 961 .family = 15,
962 .model = 6,
963 .stepping = 1,
0514ef2f 964 .features[FEAT_1_EDX] =
27861ecc 965 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 966 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
967 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
968 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
969 CPUID_DE | CPUID_FP87,
0514ef2f 970 .features[FEAT_1_ECX] =
27861ecc 971 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 972 .features[FEAT_8000_0001_EDX] =
27861ecc 973 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 974 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
975 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
976 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
977 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
978 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
979 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 980 .features[FEAT_8000_0001_ECX] =
27861ecc 981 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 982 .xlevel = 0x80000008,
983 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
984 },
985 {
986 .name = "Opteron_G3",
987 .level = 5,
99b88a17 988 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 989 .family = 15,
990 .model = 6,
991 .stepping = 1,
0514ef2f 992 .features[FEAT_1_EDX] =
27861ecc 993 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 994 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
995 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
996 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
997 CPUID_DE | CPUID_FP87,
0514ef2f 998 .features[FEAT_1_ECX] =
27861ecc 999 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1000 CPUID_EXT_SSE3,
0514ef2f 1001 .features[FEAT_8000_0001_EDX] =
27861ecc 1002 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1003 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1004 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1005 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1006 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1007 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1008 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1009 .features[FEAT_8000_0001_ECX] =
27861ecc 1010 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH		 1011 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1012 .xlevel = 0x80000008,
1013 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1014 },
1015 {
1016 .name = "Opteron_G4",
1017 .level = 0xd,
99b88a17 1018 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1019 .family = 21,
1020 .model = 1,
1021 .stepping = 2,
0514ef2f 1022 .features[FEAT_1_EDX] =
27861ecc 1023 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1024 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1025 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1026 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1027 CPUID_DE | CPUID_FP87,
0514ef2f 1028 .features[FEAT_1_ECX] =
27861ecc 1029 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 1030 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1031 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1032 CPUID_EXT_SSE3,
0514ef2f 1033 .features[FEAT_8000_0001_EDX] =
27861ecc 1034 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH		 1035 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1036 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1037 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1038 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1039 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1040 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1041 .features[FEAT_8000_0001_ECX] =
27861ecc 1042 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH		 1043 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1044 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1045 CPUID_EXT3_LAHF_LM,
1046 .xlevel = 0x8000001A,
1047 .model_id = "AMD Opteron 62xx class CPU",
1048 },
021941b9
AP		 1049 {
1050 .name = "Opteron_G5",
1051 .level = 0xd,
99b88a17 1052 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1053 .family = 21,
1054 .model = 2,
1055 .stepping = 0,
0514ef2f 1056 .features[FEAT_1_EDX] =
27861ecc 1057 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP		 1058 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1059 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1060 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1061 CPUID_DE | CPUID_FP87,
0514ef2f 1062 .features[FEAT_1_ECX] =
27861ecc 1063 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP		 1064 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1065 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1066 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1067 .features[FEAT_8000_0001_EDX] =
27861ecc 1068 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP		 1069 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1070 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1071 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1072 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1073 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1074 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1075 .features[FEAT_8000_0001_ECX] =
27861ecc 1076 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP		 1077 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1078 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1079 CPUID_EXT3_LAHF_LM,
1080 .xlevel = 0x8000001A,
1081 .model_id = "AMD Opteron 63xx class CPU",
1082 },
c6dc6f63
AP		 1083};
1084
0668af54
EH		 1085/**
1086 * x86_cpu_compat_set_features:
1087 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1088 * @w: Identifies the feature word to be changed.
1089 * @feat_add: Feature bits to be added to feature word
1090 * @feat_remove: Feature bits to be removed from feature word
1091 *
1092 * Change CPU model feature bits for compatibility.
1093 *
1094 * This function may be used by machine-type compatibility functions
1095 * to enable or disable feature bits on specific CPU models.
1096 */
1097void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1098 uint32_t feat_add, uint32_t feat_remove)
1099{
1100 x86_def_t *def;
1101 int i;
1102 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1103 def = &builtin_x86_defs[i];
1104 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1105 def->features[w] |= feat_add;
1106 def->features[w] &= ~feat_remove;
1107 }
1108 }
1109}
1110
e4ab0d6b 1111#ifdef CONFIG_KVM
c6dc6f63
AP		 1112static int cpu_x86_fill_model_id(char *str)
1113{
1114 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1115 int i;
1116
1117 for (i = 0; i < 3; i++) {
1118 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1119 memcpy(str + i * 16 + 0, &eax, 4);
1120 memcpy(str + i * 16 + 4, &ebx, 4);
1121 memcpy(str + i * 16 + 8, &ecx, 4);
1122 memcpy(str + i * 16 + 12, &edx, 4);
1123 }
1124 return 0;
1125}
e4ab0d6b 1126#endif
c6dc6f63 1127
6e746f30
EH		 1128/* Fill a x86_def_t struct with information about the host CPU, and
1129 * the CPU features supported by the host hardware + host kernel
1130 *
1131 * This function may be called only if KVM is enabled.
1132 */
1133static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 1134{
e4ab0d6b 1135#ifdef CONFIG_KVM
12869995 1136 KVMState *s = kvm_state;
c6dc6f63
AP		 1137 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1138
6e746f30
EH		 1139 assert(kvm_enabled());
1140
c6dc6f63
AP		 1141 x86_cpu_def->name = "host";
1142 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
99b88a17 1143 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
c6dc6f63
AP		 1144
1145 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1146 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1147 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1148 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 1149
12869995 1150 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
0514ef2f 1151 x86_cpu_def->features[FEAT_1_EDX] =
27861ecc 1152 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
0514ef2f 1153 x86_cpu_def->features[FEAT_1_ECX] =
27861ecc 1154 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 1155
6e746f30 1156 if (x86_cpu_def->level >= 7) {
0514ef2f 1157 x86_cpu_def->features[FEAT_7_0_EBX] =
12869995 1158 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728 1159 } else {
0514ef2f 1160 x86_cpu_def->features[FEAT_7_0_EBX] = 0;
13526728
EH		 1161 }
1162
12869995 1163 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
0514ef2f 1164 x86_cpu_def->features[FEAT_8000_0001_EDX] =
12869995 1165 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
0514ef2f 1166 x86_cpu_def->features[FEAT_8000_0001_ECX] =
12869995 1167 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 1168
c6dc6f63 1169 cpu_x86_fill_model_id(x86_cpu_def->model_id);
c6dc6f63 1170
b3baa152 1171 /* Call Centaur's CPUID instruction. */
99b88a17 1172 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
b3baa152 1173 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
12869995 1174 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
b3baa152
BW		 1175 if (eax >= 0xC0000001) {
1176 /* Support VIA max extended level */
1177 x86_cpu_def->xlevel2 = eax;
1178 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
0514ef2f 1179 x86_cpu_def->features[FEAT_C000_0001_EDX] =
12869995 1180 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
b3baa152
BW		 1181 }
1182 }
296acb64 1183
fcb93c03 1184 /* Other KVM-specific feature fields: */
0514ef2f 1185 x86_cpu_def->features[FEAT_SVM] =
fcb93c03 1186 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
0514ef2f 1187 x86_cpu_def->features[FEAT_KVM] =
bd004bef 1188 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 1189
e4ab0d6b 1190#endif /* CONFIG_KVM */
c6dc6f63
AP		 1191}
1192
bffd67b0 1193static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 1194{
1195 int i;
1196
1197 for (i = 0; i < 32; ++i)
1198 if (1 << i & mask) {
bffd67b0 1199 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1200 assert(reg);
1201 fprintf(stderr, "warning: host doesn't support requested feature: "
1202 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1203 f->cpuid_eax, reg,
1204 f->feat_names[i] ? "." : "",
1205 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 1206 break;
1207 }
1208 return 0;
1209}
1210
07ca5945
EH		 1211/* Check if all requested cpu flags are making their way to the guest
1212 *
1213 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 1214 *
1215 * This function may be called only if KVM is enabled.
c6dc6f63 1216 */
5ec01c2e 1217static int kvm_check_features_against_host(X86CPU *cpu)
c6dc6f63 1218{
5ec01c2e 1219 CPUX86State *env = &cpu->env;
c6dc6f63
AP		 1220 x86_def_t host_def;
1221 uint32_t mask;
1222 int rv, i;
1223 struct model_features_t ft[] = {
0514ef2f
EH		 1224 {&env->features[FEAT_1_EDX],
1225 &host_def.features[FEAT_1_EDX],
bffd67b0 1226 FEAT_1_EDX },
0514ef2f
EH		 1227 {&env->features[FEAT_1_ECX],
1228 &host_def.features[FEAT_1_ECX],
bffd67b0 1229 FEAT_1_ECX },
0514ef2f
EH		 1230 {&env->features[FEAT_8000_0001_EDX],
1231 &host_def.features[FEAT_8000_0001_EDX],
bffd67b0 1232 FEAT_8000_0001_EDX },
0514ef2f
EH		 1233 {&env->features[FEAT_8000_0001_ECX],
1234 &host_def.features[FEAT_8000_0001_ECX],
bffd67b0 1235 FEAT_8000_0001_ECX },
0514ef2f
EH		 1236 {&env->features[FEAT_C000_0001_EDX],
1237 &host_def.features[FEAT_C000_0001_EDX],
07ca5945 1238 FEAT_C000_0001_EDX },
0514ef2f
EH		 1239 {&env->features[FEAT_7_0_EBX],
1240 &host_def.features[FEAT_7_0_EBX],
07ca5945 1241 FEAT_7_0_EBX },
0514ef2f
EH		 1242 {&env->features[FEAT_SVM],
1243 &host_def.features[FEAT_SVM],
07ca5945 1244 FEAT_SVM },
0514ef2f
EH		 1245 {&env->features[FEAT_KVM],
1246 &host_def.features[FEAT_KVM],
07ca5945 1247 FEAT_KVM },
8b4beddc 1248 };
c6dc6f63 1249
6e746f30
EH		 1250 assert(kvm_enabled());
1251
1252 kvm_cpu_fill_host(&host_def);
bffd67b0
EH		 1253 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1254 FeatureWord w = ft[i].feat_word;
1255 FeatureWordInfo *wi = &feature_word_info[w];
1256 for (mask = 1; mask; mask <<= 1) {
e8beac00 1257 if (*ft[i].guest_feat & mask &&
c6dc6f63 1258 !(*ft[i].host_feat & mask)) {
bffd67b0
EH		 1259 unavailable_host_feature(wi, mask);
1260 rv = 1;
1261 }
1262 }
1263 }
c6dc6f63
AP		 1264 return rv;
1265}
1266
95b8519d
AF		 1267static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1268 const char *name, Error **errp)
1269{
1270 X86CPU *cpu = X86_CPU(obj);
1271 CPUX86State *env = &cpu->env;
1272 int64_t value;
1273
1274 value = (env->cpuid_version >> 8) & 0xf;
1275 if (value == 0xf) {
1276 value += (env->cpuid_version >> 20) & 0xff;
1277 }
1278 visit_type_int(v, &value, name, errp);
1279}
1280
71ad61d3
AF		 1281static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1282 const char *name, Error **errp)
ed5e1ec3 1283{
71ad61d3
AF		 1284 X86CPU *cpu = X86_CPU(obj);
1285 CPUX86State *env = &cpu->env;
1286 const int64_t min = 0;
1287 const int64_t max = 0xff + 0xf;
1288 int64_t value;
1289
1290 visit_type_int(v, &value, name, errp);
1291 if (error_is_set(errp)) {
1292 return;
1293 }
1294 if (value < min || value > max) {
1295 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1296 name ? name : "null", value, min, max);
1297 return;
1298 }
1299
ed5e1ec3 1300 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1301 if (value > 0x0f) {
1302 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1303 } else {
71ad61d3 1304 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1305 }
1306}
1307
67e30c83
AF		 1308static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1309 const char *name, Error **errp)
1310{
1311 X86CPU *cpu = X86_CPU(obj);
1312 CPUX86State *env = &cpu->env;
1313 int64_t value;
1314
1315 value = (env->cpuid_version >> 4) & 0xf;
1316 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1317 visit_type_int(v, &value, name, errp);
1318}
1319
c5291a4f
AF		 1320static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1321 const char *name, Error **errp)
b0704cbd 1322{
c5291a4f
AF		 1323 X86CPU *cpu = X86_CPU(obj);
1324 CPUX86State *env = &cpu->env;
1325 const int64_t min = 0;
1326 const int64_t max = 0xff;
1327 int64_t value;
1328
1329 visit_type_int(v, &value, name, errp);
1330 if (error_is_set(errp)) {
1331 return;
1332 }
1333 if (value < min || value > max) {
1334 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1335 name ? name : "null", value, min, max);
1336 return;
1337 }
1338
b0704cbd 1339 env->cpuid_version &= ~0xf00f0;
c5291a4f 1340 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1341}
1342
35112e41
AF		 1343static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1344 void *opaque, const char *name,
1345 Error **errp)
1346{
1347 X86CPU *cpu = X86_CPU(obj);
1348 CPUX86State *env = &cpu->env;
1349 int64_t value;
1350
1351 value = env->cpuid_version & 0xf;
1352 visit_type_int(v, &value, name, errp);
1353}
1354
036e2222
AF		 1355static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1356 void *opaque, const char *name,
1357 Error **errp)
38c3dc46 1358{
036e2222
AF		 1359 X86CPU *cpu = X86_CPU(obj);
1360 CPUX86State *env = &cpu->env;
1361 const int64_t min = 0;
1362 const int64_t max = 0xf;
1363 int64_t value;
1364
1365 visit_type_int(v, &value, name, errp);
1366 if (error_is_set(errp)) {
1367 return;
1368 }
1369 if (value < min || value > max) {
1370 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1371 name ? name : "null", value, min, max);
1372 return;
1373 }
1374
38c3dc46 1375 env->cpuid_version &= ~0xf;
036e2222 1376 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1377}
1378
8e1898bf
AF		 1379static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1380 const char *name, Error **errp)
1381{
1382 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1383
fa029887 1384 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1385}
1386
1387static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1388 const char *name, Error **errp)
1389{
1390 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1391
fa029887 1392 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1393}
1394
16b93aa8
AF		 1395static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1396 const char *name, Error **errp)
1397{
1398 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1399
fa029887 1400 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1401}
1402
1403static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1404 const char *name, Error **errp)
1405{
1406 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1407
fa029887 1408 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1409}
1410
d480e1af
AF		 1411static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1412{
1413 X86CPU *cpu = X86_CPU(obj);
1414 CPUX86State *env = &cpu->env;
1415 char *value;
d480e1af 1416
9df694ee 1417 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1418 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1419 env->cpuid_vendor3);
d480e1af
AF		 1420 return value;
1421}
1422
1423static void x86_cpuid_set_vendor(Object *obj, const char *value,
1424 Error **errp)
1425{
1426 X86CPU *cpu = X86_CPU(obj);
1427 CPUX86State *env = &cpu->env;
1428 int i;
1429
9df694ee 1430 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1431 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1432 "vendor", value);
1433 return;
1434 }
1435
1436 env->cpuid_vendor1 = 0;
1437 env->cpuid_vendor2 = 0;
1438 env->cpuid_vendor3 = 0;
1439 for (i = 0; i < 4; i++) {
1440 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1441 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1442 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1443 }
d480e1af
AF		 1444}
1445
63e886eb
AF		 1446static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1447{
1448 X86CPU *cpu = X86_CPU(obj);
1449 CPUX86State *env = &cpu->env;
1450 char *value;
1451 int i;
1452
1453 value = g_malloc(48 + 1);
1454 for (i = 0; i < 48; i++) {
1455 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1456 }
1457 value[48] = '\0';
1458 return value;
1459}
1460
938d4c25
AF		 1461static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1462 Error **errp)
dcce6675 1463{
938d4c25
AF		 1464 X86CPU *cpu = X86_CPU(obj);
1465 CPUX86State *env = &cpu->env;
dcce6675
AF		 1466 int c, len, i;
1467
1468 if (model_id == NULL) {
1469 model_id = "";
1470 }
1471 len = strlen(model_id);
d0a6acf4 1472 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1473 for (i = 0; i < 48; i++) {
1474 if (i >= len) {
1475 c = '\0';
1476 } else {
1477 c = (uint8_t)model_id[i];
1478 }
1479 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1480 }
1481}
1482
89e48965
AF		 1483static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1484 const char *name, Error **errp)
1485{
1486 X86CPU *cpu = X86_CPU(obj);
1487 int64_t value;
1488
1489 value = cpu->env.tsc_khz * 1000;
1490 visit_type_int(v, &value, name, errp);
1491}
1492
1493static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1494 const char *name, Error **errp)
1495{
1496 X86CPU *cpu = X86_CPU(obj);
1497 const int64_t min = 0;
2e84849a 1498 const int64_t max = INT64_MAX;
89e48965
AF		 1499 int64_t value;
1500
1501 visit_type_int(v, &value, name, errp);
1502 if (error_is_set(errp)) {
1503 return;
1504 }
1505 if (value < min || value > max) {
1506 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1507 name ? name : "null", value, min, max);
1508 return;
1509 }
1510
1511 cpu->env.tsc_khz = value / 1000;
1512}
1513
31050930
IM		 1514static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1515 const char *name, Error **errp)
1516{
1517 X86CPU *cpu = X86_CPU(obj);
1518 int64_t value = cpu->env.cpuid_apic_id;
1519
1520 visit_type_int(v, &value, name, errp);
1521}
1522
1523static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1524 const char *name, Error **errp)
1525{
1526 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1527 DeviceState *dev = DEVICE(obj);
31050930
IM		 1528 const int64_t min = 0;
1529 const int64_t max = UINT32_MAX;
1530 Error *error = NULL;
1531 int64_t value;
1532
8d6d4980
IM		 1533 if (dev->realized) {
1534 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1535 "it was realized", name, object_get_typename(obj));
1536 return;
1537 }
1538
31050930
IM		 1539 visit_type_int(v, &value, name, &error);
1540 if (error) {
1541 error_propagate(errp, error);
1542 return;
1543 }
1544 if (value < min || value > max) {
1545 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1546 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1547 object_get_typename(obj), name, value, min, max);
1548 return;
1549 }
1550
1551 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1552 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1553 return;
1554 }
1555 cpu->env.cpuid_apic_id = value;
1556}
1557
7e5292b5 1558/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1559static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1560 const char *name, Error **errp)
1561{
7e5292b5 1562 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1563 FeatureWord w;
1564 Error *err = NULL;
1565 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1566 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1567 X86CPUFeatureWordInfoList *list = NULL;
1568
1569 for (w = 0; w < FEATURE_WORDS; w++) {
1570 FeatureWordInfo *wi = &feature_word_info[w];
1571 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1572 qwi->cpuid_input_eax = wi->cpuid_eax;
1573 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1574 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1575 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1576 qwi->features = array[w];
8e8aba50
EH		 1577
1578 /* List will be in reverse order, but order shouldn't matter */
1579 list_entries[w].next = list;
1580 list_entries[w].value = &word_infos[w];
1581 list = &list_entries[w];
1582 }
1583
1584 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1585 error_propagate(errp, err);
1586}
1587
c1399112
EH		 1588static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def,
1589 const char *name)
c6dc6f63 1590{
c6dc6f63 1591 x86_def_t *def;
9337e3b6 1592 Error *err = NULL;
7fc9b714 1593 int i;
c6dc6f63 1594
4bfe910d
AF		 1595 if (name == NULL) {
1596 return -1;
9f3fb565 1597 }
4bfe910d 1598 if (kvm_enabled() && strcmp(name, "host") == 0) {
6e746f30 1599 kvm_cpu_fill_host(x86_cpu_def);
9337e3b6
EH		 1600 object_property_set_bool(OBJECT(cpu), true, "pmu", &err);
1601 assert_no_error(err);
4bfe910d 1602 return 0;
c6dc6f63
AP		 1603 }
1604
7fc9b714
AF		 1605 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1606 def = &builtin_x86_defs[i];
4bfe910d
AF		 1607 if (strcmp(name, def->name) == 0) {
1608 memcpy(x86_cpu_def, def, sizeof(*def));
11acfdd5
IM		 1609 /* sysenter isn't supported in compatibility mode on AMD,
1610 * syscall isn't supported in compatibility mode on Intel.
1611 * Normally we advertise the actual CPU vendor, but you can
1612 * override this using the 'vendor' property if you want to use
1613 * KVM's sysenter/syscall emulation in compatibility mode and
1614 * when doing cross vendor migration
1615 */
1616 if (kvm_enabled()) {
1617 uint32_t ebx = 0, ecx = 0, edx = 0;
1618 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1619 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1620 }
4bfe910d
AF		 1621 return 0;
1622 }
1623 }
1624
1625 return -1;
8f961357
EH		 1626}
1627
72ac2e87
IM		 1628/* Convert all '_' in a feature string option name to '-', to make feature
1629 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1630 */
1631static inline void feat2prop(char *s)
1632{
1633 while ((s = strchr(s, '_'))) {
1634 *s = '-';
1635 }
1636}
1637
8f961357
EH		 1638/* Parse "+feature,-feature,feature=foo" CPU feature string
1639 */
a91987c2 1640static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
8f961357 1641{
8f961357
EH		 1642 char *featurestr; /* Single 'key=value" string being parsed */
1643 /* Features to be added */
077c68c3 1644 FeatureWordArray plus_features = { 0 };
8f961357 1645 /* Features to be removed */
5ef57876 1646 FeatureWordArray minus_features = { 0 };
8f961357 1647 uint32_t numvalue;
a91987c2 1648 CPUX86State *env = &cpu->env;
8f961357 1649
8f961357 1650 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1651
1652 while (featurestr) {
1653 char *val;
1654 if (featurestr[0] == '+') {
5ef57876 1655 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1656 } else if (featurestr[0] == '-') {
5ef57876 1657 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1658 } else if ((val = strchr(featurestr, '='))) {
1659 *val = 0; val++;
72ac2e87 1660 feat2prop(featurestr);
c6dc6f63 1661 if (!strcmp(featurestr, "family")) {
a91987c2 1662 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1663 } else if (!strcmp(featurestr, "model")) {
a91987c2 1664 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1665 } else if (!strcmp(featurestr, "stepping")) {
a91987c2 1666 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1667 } else if (!strcmp(featurestr, "level")) {
a91987c2 1668 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63
AP		 1669 } else if (!strcmp(featurestr, "xlevel")) {
1670 char *err;
a91987c2
IM		 1671 char num[32];
1672
c6dc6f63
AP		 1673 numvalue = strtoul(val, &err, 0);
1674 if (!*val || *err) {
312fd5f2 1675 error_setg(errp, "bad numerical value %s", val);
a91987c2 1676 goto out;
c6dc6f63
AP		 1677 }
1678 if (numvalue < 0x80000000) {
8ba8a698
IM		 1679 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1680 ", fixup will be removed in future versions\n");
2f7a21c4 1681 numvalue += 0x80000000;
c6dc6f63 1682 }
a91987c2
IM		 1683 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1684 object_property_parse(OBJECT(cpu), num, featurestr, errp);
c6dc6f63 1685 } else if (!strcmp(featurestr, "vendor")) {
a91987c2 1686 object_property_parse(OBJECT(cpu), val, featurestr, errp);
72ac2e87
IM		 1687 } else if (!strcmp(featurestr, "model-id")) {
1688 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1689 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1690 int64_t tsc_freq;
1691 char *err;
a91987c2 1692 char num[32];
b862d1fe
JR		 1693
1694 tsc_freq = strtosz_suffix_unit(val, &err,
1695 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1696 if (tsc_freq < 0 || *err) {
312fd5f2 1697 error_setg(errp, "bad numerical value %s", val);
a91987c2 1698 goto out;
b862d1fe 1699 }
a91987c2
IM		 1700 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1701 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
72ac2e87 1702 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1703 char *err;
92067bf4 1704 const int min = 0xFFF;
28f52cc0
VR		 1705 numvalue = strtoul(val, &err, 0);
1706 if (!*val || *err) {
312fd5f2 1707 error_setg(errp, "bad numerical value %s", val);
a91987c2 1708 goto out;
28f52cc0 1709 }
92067bf4
IM		 1710 if (numvalue < min) {
1711 fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1712 ", fixup will be removed in future versions\n",
1713 min);
1714 numvalue = min;
1715 }
1716 cpu->hyperv_spinlock_attempts = numvalue;
c6dc6f63 1717 } else {
312fd5f2 1718 error_setg(errp, "unrecognized feature %s", featurestr);
a91987c2 1719 goto out;
c6dc6f63
AP		 1720 }
1721 } else if (!strcmp(featurestr, "check")) {
1722 check_cpuid = 1;
1723 } else if (!strcmp(featurestr, "enforce")) {
1724 check_cpuid = enforce_cpuid = 1;
28f52cc0 1725 } else if (!strcmp(featurestr, "hv_relaxed")) {
92067bf4 1726 cpu->hyperv_relaxed_timing = true;
28f52cc0 1727 } else if (!strcmp(featurestr, "hv_vapic")) {
92067bf4 1728 cpu->hyperv_vapic = true;
c6dc6f63 1729 } else {
a91987c2 1730 error_setg(errp, "feature string `%s' not in format (+feature|"
312fd5f2 1731 "-feature|feature=xyz)", featurestr);
a91987c2
IM		 1732 goto out;
1733 }
1734 if (error_is_set(errp)) {
1735 goto out;
c6dc6f63
AP		 1736 }
1737 featurestr = strtok(NULL, ",");
1738 }
0514ef2f
EH		 1739 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1740 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1741 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1742 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1743 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1744 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1745 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1746 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1747 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1748 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1749 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1750 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1751 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1752 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1753 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1754 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63 1755
a91987c2
IM		 1756out:
1757 return;
c6dc6f63
AP		 1758}
1759
1760/* generate a composite string into buf of all cpuid names in featureset
1761 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1762 * if flags, suppress names undefined in featureset.
1763 */
1764static void listflags(char *buf, int bufsize, uint32_t fbits,
1765 const char **featureset, uint32_t flags)
1766{
1767 const char **p = &featureset[31];
1768 char *q, *b, bit;
1769 int nc;
1770
1771 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1772 *buf = '\0';
1773 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1774 if (fbits & 1 << bit && (*p || !flags)) {
1775 if (*p)
1776 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1777 else
1778 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1779 if (bufsize <= nc) {
1780 if (b) {
1781 memcpy(b, "...", sizeof("..."));
1782 }
1783 return;
1784 }
1785 q += nc;
1786 bufsize -= nc;
1787 }
1788}
1789
e916cbf8
PM		 1790/* generate CPU information. */
1791void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1792{
c6dc6f63
AP		 1793 x86_def_t *def;
1794 char buf[256];
7fc9b714 1795 int i;
c6dc6f63 1796
7fc9b714
AF		 1797 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1798 def = &builtin_x86_defs[i];
c04321b3 1799 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1800 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1801 }
21ad7789
JK		 1802#ifdef CONFIG_KVM
1803 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1804 "KVM processor with all supported host features "
1805 "(only available in KVM mode)");
1806#endif
1807
6cdf8854 1808 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1809 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1810 FeatureWordInfo *fw = &feature_word_info[i];
1811
1812 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1813 (*cpu_fprintf)(f, " %s\n", buf);
1814 }
c6dc6f63
AP		 1815}
1816
76b64a7a 1817CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1818{
1819 CpuDefinitionInfoList *cpu_list = NULL;
1820 x86_def_t *def;
7fc9b714 1821 int i;
e3966126 1822
7fc9b714 1823 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1824 CpuDefinitionInfoList *entry;
1825 CpuDefinitionInfo *info;
1826
7fc9b714 1827 def = &builtin_x86_defs[i];
e3966126
AL		 1828 info = g_malloc0(sizeof(*info));
1829 info->name = g_strdup(def->name);
1830
1831 entry = g_malloc0(sizeof(*entry));
1832 entry->value = info;
1833 entry->next = cpu_list;
1834 cpu_list = entry;
1835 }
1836
1837 return cpu_list;
1838}
1839
bc74b7db
EH		 1840#ifdef CONFIG_KVM
1841static void filter_features_for_kvm(X86CPU *cpu)
1842{
1843 CPUX86State *env = &cpu->env;
1844 KVMState *s = kvm_state;
bd87d2a2 1845 FeatureWord w;
bc74b7db 1846
bd87d2a2
EH		 1847 for (w = 0; w < FEATURE_WORDS; w++) {
1848 FeatureWordInfo *wi = &feature_word_info[w];
034acf4a
EH		 1849 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1850 wi->cpuid_ecx,
1851 wi->cpuid_reg);
1852 uint32_t requested_features = env->features[w];
1853 env->features[w] &= host_feat;
1854 cpu->filtered_features[w] = requested_features & ~env->features[w];
bd87d2a2 1855 }
bc74b7db
EH		 1856}
1857#endif
1858
2d64255b 1859static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
c6dc6f63 1860{
61dcd775 1861 CPUX86State *env = &cpu->env;
c6dc6f63
AP		 1862 x86_def_t def1, *def = &def1;
1863
db0ad1ba
JR		 1864 memset(def, 0, sizeof(*def));
1865
c1399112 1866 if (cpu_x86_find_by_name(cpu, def, name) < 0) {
2d64255b
AF		 1867 error_setg(errp, "Unable to find CPU definition: %s", name);
1868 return;
8f961357
EH		 1869 }
1870
aa87d458 1871 if (kvm_enabled()) {
0514ef2f 1872 def->features[FEAT_KVM] |= kvm_default_features;
aa87d458 1873 }
0514ef2f 1874 def->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
077c68c3 1875
2d64255b
AF		 1876 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1877 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1878 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1879 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1880 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
0514ef2f
EH		 1881 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1882 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1883 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1884 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
2d64255b 1885 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
0514ef2f
EH		 1886 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1887 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1888 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1889 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
b3baa152 1890 env->cpuid_xlevel2 = def->xlevel2;
3b671a40 1891
2d64255b 1892 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
c6dc6f63
AP		 1893}
1894
62fc403f
IM		 1895X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1896 Error **errp)
5c3c6a68 1897{
2d64255b 1898 X86CPU *cpu = NULL;
5c3c6a68 1899 CPUX86State *env;
2d64255b
AF		 1900 gchar **model_pieces;
1901 char *name, *features;
ba2bc7a4 1902 char *typename;
5c3c6a68
AF		 1903 Error *error = NULL;
1904
2d64255b
AF		 1905 model_pieces = g_strsplit(cpu_model, ",", 2);
1906 if (!model_pieces[0]) {
1907 error_setg(&error, "Invalid/empty CPU model name");
1908 goto out;
1909 }
1910 name = model_pieces[0];
1911 features = model_pieces[1];
1912
5c3c6a68 1913 cpu = X86_CPU(object_new(TYPE_X86_CPU));
62fc403f
IM		 1914#ifndef CONFIG_USER_ONLY
1915 if (icc_bridge == NULL) {
1916 error_setg(&error, "Invalid icc-bridge value");
1917 goto out;
1918 }
1919 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1920 object_unref(OBJECT(cpu));
1921#endif
5c3c6a68
AF		 1922 env = &cpu->env;
1923 env->cpu_model_str = cpu_model;
1924
2d64255b
AF		 1925 cpu_x86_register(cpu, name, &error);
1926 if (error) {
1927 goto out;
1928 }
1929
ba2bc7a4
AF		 1930 /* Emulate per-model subclasses for global properties */
1931 typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1932 qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1933 g_free(typename);
1934 if (error) {
1935 goto out;
1936 }
1937
2d64255b
AF		 1938 cpu_x86_parse_featurestr(cpu, features, &error);
1939 if (error) {
1940 goto out;
5c3c6a68
AF		 1941 }
1942
7f833247 1943out:
cd7b87ff
AF		 1944 if (error != NULL) {
1945 error_propagate(errp, error);
1946 object_unref(OBJECT(cpu));
1947 cpu = NULL;
1948 }
7f833247
IM		 1949 g_strfreev(model_pieces);
1950 return cpu;
1951}
1952
1953X86CPU *cpu_x86_init(const char *cpu_model)
1954{
1955 Error *error = NULL;
1956 X86CPU *cpu;
1957
62fc403f 1958 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1959 if (error) {
2d64255b
AF		 1960 goto out;
1961 }
1962
7f833247
IM		 1963 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1964
2d64255b 1965out:
2d64255b 1966 if (error) {
4a44d85e 1967 error_report("%s", error_get_pretty(error));
5c3c6a68 1968 error_free(error);
2d64255b
AF		 1969 if (cpu != NULL) {
1970 object_unref(OBJECT(cpu));
1971 cpu = NULL;
1972 }
5c3c6a68
AF		 1973 }
1974 return cpu;
1975}
1976
c6dc6f63 1977#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1978
0e26b7b8
BS		 1979void cpu_clear_apic_feature(CPUX86State *env)
1980{
0514ef2f 1981 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 1982}
1983
c6dc6f63
AP		 1984#endif /* !CONFIG_USER_ONLY */
1985
c04321b3 1986/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1987 */
1988void x86_cpudef_setup(void)
1989{
93bfef4c
CV		 1990 int i, j;
1991 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1992
1993 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291 1994 x86_def_t *def = &builtin_x86_defs[i];
93bfef4c
CV		 1995
1996 /* Look for specific "cpudef" models that */
09faecf2 1997 /* have the QEMU version in .model_id */
93bfef4c 1998 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1999 if (strcmp(model_with_versions[j], def->name) == 0) {
2000 pstrcpy(def->model_id, sizeof(def->model_id),
2001 "QEMU Virtual CPU version ");
2002 pstrcat(def->model_id, sizeof(def->model_id),
2003 qemu_get_version());
93bfef4c
CV		 2004 break;
2005 }
2006 }
c6dc6f63 2007 }
c6dc6f63
AP		 2008}
2009
c6dc6f63
AP		 2010static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2011 uint32_t *ecx, uint32_t *edx)
2012{
2013 *ebx = env->cpuid_vendor1;
2014 *edx = env->cpuid_vendor2;
2015 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2016}
2017
2018void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2019 uint32_t *eax, uint32_t *ebx,
2020 uint32_t *ecx, uint32_t *edx)
2021{
a60f24b5
AF		 2022 X86CPU *cpu = x86_env_get_cpu(env);
2023 CPUState *cs = CPU(cpu);
2024
c6dc6f63
AP		 2025 /* test if maximum index reached */
2026 if (index & 0x80000000) {
b3baa152
BW		 2027 if (index > env->cpuid_xlevel) {
2028 if (env->cpuid_xlevel2 > 0) {
2029 /* Handle the Centaur's CPUID instruction. */
2030 if (index > env->cpuid_xlevel2) {
2031 index = env->cpuid_xlevel2;
2032 } else if (index < 0xC0000000) {
2033 index = env->cpuid_xlevel;
2034 }
2035 } else {
57f26ae7
EH		 2036 /* Intel documentation states that invalid EAX input will
2037 * return the same information as EAX=cpuid_level
2038 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2039 */
2040 index = env->cpuid_level;
b3baa152
BW		 2041 }
2042 }
c6dc6f63
AP		 2043 } else {
2044 if (index > env->cpuid_level)
2045 index = env->cpuid_level;
2046 }
2047
2048 switch(index) {
2049 case 0:
2050 *eax = env->cpuid_level;
2051 get_cpuid_vendor(env, ebx, ecx, edx);
2052 break;
2053 case 1:
2054 *eax = env->cpuid_version;
2055 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2056 *ecx = env->features[FEAT_1_ECX];
2057 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2058 if (cs->nr_cores * cs->nr_threads > 1) {
2059 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2060 *edx |= 1 << 28; /* HTT bit */
2061 }
2062 break;
2063 case 2:
2064 /* cache info: needed for Pentium Pro compatibility */
5e891bf8 2065 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2066 *ebx = 0;
2067 *ecx = 0;
5e891bf8
EH		 2068 *edx = (L1D_DESCRIPTOR << 16) | \
2069 (L1I_DESCRIPTOR << 8) | \
2070 (L2_DESCRIPTOR);
c6dc6f63
AP		 2071 break;
2072 case 4:
2073 /* cache info: needed for Core compatibility */
ce3960eb
AF		 2074 if (cs->nr_cores > 1) {
2075 *eax = (cs->nr_cores - 1) << 26;
c6dc6f63 2076 } else {
2f7a21c4 2077 *eax = 0;
c6dc6f63
AP		 2078 }
2079 switch (count) {
2080 case 0: /* L1 dcache info */
5e891bf8
EH		 2081 *eax |= CPUID_4_TYPE_DCACHE | \
2082 CPUID_4_LEVEL(1) | \
2083 CPUID_4_SELF_INIT_LEVEL;
2084 *ebx = (L1D_LINE_SIZE - 1) | \
2085 ((L1D_PARTITIONS - 1) << 12) | \
2086 ((L1D_ASSOCIATIVITY - 1) << 22);
2087 *ecx = L1D_SETS - 1;
2088 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2089 break;
2090 case 1: /* L1 icache info */
5e891bf8
EH		 2091 *eax |= CPUID_4_TYPE_ICACHE | \
2092 CPUID_4_LEVEL(1) | \
2093 CPUID_4_SELF_INIT_LEVEL;
2094 *ebx = (L1I_LINE_SIZE - 1) | \
2095 ((L1I_PARTITIONS - 1) << 12) | \
2096 ((L1I_ASSOCIATIVITY - 1) << 22);
2097 *ecx = L1I_SETS - 1;
2098 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2099 break;
2100 case 2: /* L2 cache info */
5e891bf8
EH		 2101 *eax |= CPUID_4_TYPE_UNIFIED | \
2102 CPUID_4_LEVEL(2) | \
2103 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2104 if (cs->nr_threads > 1) {
2105 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2106 }
5e891bf8
EH		 2107 *ebx = (L2_LINE_SIZE - 1) | \
2108 ((L2_PARTITIONS - 1) << 12) | \
2109 ((L2_ASSOCIATIVITY - 1) << 22);
2110 *ecx = L2_SETS - 1;
2111 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2112 break;
2113 default: /* end of info */
2114 *eax = 0;
2115 *ebx = 0;
2116 *ecx = 0;
2117 *edx = 0;
2118 break;
2119 }
2120 break;
2121 case 5:
2122 /* mwait info: needed for Core compatibility */
2123 *eax = 0; /* Smallest monitor-line size in bytes */
2124 *ebx = 0; /* Largest monitor-line size in bytes */
2125 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2126 *edx = 0;
2127 break;
2128 case 6:
2129 /* Thermal and Power Leaf */
2130 *eax = 0;
2131 *ebx = 0;
2132 *ecx = 0;
2133 *edx = 0;
2134 break;
f7911686 2135 case 7:
13526728
EH		 2136 /* Structured Extended Feature Flags Enumeration Leaf */
2137 if (count == 0) {
2138 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2139 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2140 *ecx = 0; /* Reserved */
2141 *edx = 0; /* Reserved */
f7911686
YW		 2142 } else {
2143 *eax = 0;
2144 *ebx = 0;
2145 *ecx = 0;
2146 *edx = 0;
2147 }
2148 break;
c6dc6f63
AP		 2149 case 9:
2150 /* Direct Cache Access Information Leaf */
2151 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2152 *ebx = 0;
2153 *ecx = 0;
2154 *edx = 0;
2155 break;
2156 case 0xA:
2157 /* Architectural Performance Monitoring Leaf */
9337e3b6 2158 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2159 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2160
2161 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2162 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2163 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2164 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2165 } else {
2166 *eax = 0;
2167 *ebx = 0;
2168 *ecx = 0;
2169 *edx = 0;
2170 }
c6dc6f63 2171 break;
51e49430
SY		 2172 case 0xD:
2173 /* Processor Extended State */
0514ef2f 2174 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2175 *eax = 0;
2176 *ebx = 0;
2177 *ecx = 0;
2178 *edx = 0;
2179 break;
2180 }
2181 if (kvm_enabled()) {
a60f24b5 2182 KVMState *s = cs->kvm_state;
ba9bc59e
JK		 2183
2184 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
2185 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
2186 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
2187 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 2188 } else {
2189 *eax = 0;
2190 *ebx = 0;
2191 *ecx = 0;
2192 *edx = 0;
2193 }
2194 break;
c6dc6f63
AP		 2195 case 0x80000000:
2196 *eax = env->cpuid_xlevel;
2197 *ebx = env->cpuid_vendor1;
2198 *edx = env->cpuid_vendor2;
2199 *ecx = env->cpuid_vendor3;
2200 break;
2201 case 0x80000001:
2202 *eax = env->cpuid_version;
2203 *ebx = 0;
0514ef2f
EH		 2204 *ecx = env->features[FEAT_8000_0001_ECX];
2205 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2206
2207 /* The Linux kernel checks for the CMPLegacy bit and
2208 * discards multiple thread information if it is set.
2209 * So dont set it here for Intel to make Linux guests happy.
2210 */
ce3960eb 2211 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2212 uint32_t tebx, tecx, tedx;
2213 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2214 if (tebx != CPUID_VENDOR_INTEL_1 ||
2215 tedx != CPUID_VENDOR_INTEL_2 ||
2216 tecx != CPUID_VENDOR_INTEL_3) {
2217 *ecx |= 1 << 1; /* CmpLegacy bit */
2218 }
2219 }
c6dc6f63
AP		 2220 break;
2221 case 0x80000002:
2222 case 0x80000003:
2223 case 0x80000004:
2224 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2225 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2226 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2227 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2228 break;
2229 case 0x80000005:
2230 /* cache info (L1 cache) */
5e891bf8
EH		 2231 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2232 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2233 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2234 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2235 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2236 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2237 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2238 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2239 break;
2240 case 0x80000006:
2241 /* cache info (L2 cache) */
5e891bf8
EH		 2242 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2243 (L2_DTLB_2M_ENTRIES << 16) | \
2244 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2245 (L2_ITLB_2M_ENTRIES);
2246 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2247 (L2_DTLB_4K_ENTRIES << 16) | \
2248 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2249 (L2_ITLB_4K_ENTRIES);
2250 *ecx = (L2_SIZE_KB_AMD << 16) | \
2251 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2252 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2253 *edx = ((L3_SIZE_KB/512) << 18) | \
2254 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2255 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP		 2256 break;
2257 case 0x80000008:
2258 /* virtual & phys address size in low 2 bytes. */
2259/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2260 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2261 /* 64 bit processor */
2262/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2263 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2264 } else {
0514ef2f 2265 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2266 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2267 } else {
c6dc6f63 2268 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2269 }
c6dc6f63
AP		 2270 }
2271 *ebx = 0;
2272 *ecx = 0;
2273 *edx = 0;
ce3960eb
AF		 2274 if (cs->nr_cores * cs->nr_threads > 1) {
2275 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2276 }
2277 break;
2278 case 0x8000000A:
0514ef2f 2279 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2280 *eax = 0x00000001; /* SVM Revision */
2281 *ebx = 0x00000010; /* nr of ASIDs */
2282 *ecx = 0;
0514ef2f 2283 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2284 } else {
2285 *eax = 0;
2286 *ebx = 0;
2287 *ecx = 0;
2288 *edx = 0;
2289 }
c6dc6f63 2290 break;
b3baa152
BW		 2291 case 0xC0000000:
2292 *eax = env->cpuid_xlevel2;
2293 *ebx = 0;
2294 *ecx = 0;
2295 *edx = 0;
2296 break;
2297 case 0xC0000001:
2298 /* Support for VIA CPU's CPUID instruction */
2299 *eax = env->cpuid_version;
2300 *ebx = 0;
2301 *ecx = 0;
0514ef2f 2302 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2303 break;
2304 case 0xC0000002:
2305 case 0xC0000003:
2306 case 0xC0000004:
2307 /* Reserved for the future, and now filled with zero */
2308 *eax = 0;
2309 *ebx = 0;
2310 *ecx = 0;
2311 *edx = 0;
2312 break;
c6dc6f63
AP		 2313 default:
2314 /* reserved values: zero */
2315 *eax = 0;
2316 *ebx = 0;
2317 *ecx = 0;
2318 *edx = 0;
2319 break;
2320 }
2321}
5fd2087a
AF		 2322
2323/* CPUClass::reset() */
2324static void x86_cpu_reset(CPUState *s)
2325{
2326 X86CPU *cpu = X86_CPU(s);
2327 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2328 CPUX86State *env = &cpu->env;
c1958aea
AF		 2329 int i;
2330
5fd2087a
AF		 2331 xcc->parent_reset(s);
2332
c1958aea
AF		 2333
2334 memset(env, 0, offsetof(CPUX86State, breakpoints));
2335
2336 tlb_flush(env, 1);
2337
2338 env->old_exception = -1;
2339
2340 /* init to reset state */
2341
2342#ifdef CONFIG_SOFTMMU
2343 env->hflags |= HF_SOFTMMU_MASK;
2344#endif
2345 env->hflags2 |= HF2_GIF_MASK;
2346
2347 cpu_x86_update_cr0(env, 0x60000010);
2348 env->a20_mask = ~0x0;
2349 env->smbase = 0x30000;
2350
2351 env->idt.limit = 0xffff;
2352 env->gdt.limit = 0xffff;
2353 env->ldt.limit = 0xffff;
2354 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2355 env->tr.limit = 0xffff;
2356 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2357
2358 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2359 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2360 DESC_R_MASK | DESC_A_MASK);
2361 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2362 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2363 DESC_A_MASK);
2364 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2365 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2366 DESC_A_MASK);
2367 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2368 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2369 DESC_A_MASK);
2370 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2371 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2372 DESC_A_MASK);
2373 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2374 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2375 DESC_A_MASK);
2376
2377 env->eip = 0xfff0;
2378 env->regs[R_EDX] = env->cpuid_version;
2379
2380 env->eflags = 0x2;
2381
2382 /* FPU init */
2383 for (i = 0; i < 8; i++) {
2384 env->fptags[i] = 1;
2385 }
2386 env->fpuc = 0x37f;
2387
2388 env->mxcsr = 0x1f80;
2389
2390 env->pat = 0x0007040600070406ULL;
2391 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2392
2393 memset(env->dr, 0, sizeof(env->dr));
2394 env->dr[6] = DR6_FIXED_1;
2395 env->dr[7] = DR7_FIXED_1;
2396 cpu_breakpoint_remove_all(env, BP_CPU);
2397 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 2398
2399#if !defined(CONFIG_USER_ONLY)
2400 /* We hard-wire the BSP to the first CPU. */
55e5c285 2401 if (s->cpu_index == 0) {
dd673288
IM		 2402 apic_designate_bsp(env->apic_state);
2403 }
2404
259186a7 2405 s->halted = !cpu_is_bsp(cpu);
dd673288 2406#endif
5fd2087a
AF		 2407}
2408
dd673288
IM		 2409#ifndef CONFIG_USER_ONLY
2410bool cpu_is_bsp(X86CPU *cpu)
2411{
2412 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2413}
65dee380
IM		 2414
2415/* TODO: remove me, when reset over QOM tree is implemented */
2416static void x86_cpu_machine_reset_cb(void *opaque)
2417{
2418 X86CPU *cpu = opaque;
2419 cpu_reset(CPU(cpu));
2420}
dd673288
IM		 2421#endif
2422
de024815
AF		 2423static void mce_init(X86CPU *cpu)
2424{
2425 CPUX86State *cenv = &cpu->env;
2426 unsigned int bank;
2427
2428 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2429 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2430 (CPUID_MCE | CPUID_MCA)) {
2431 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2432 cenv->mcg_ctl = ~(uint64_t)0;
2433 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2434 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2435 }
2436 }
2437}
2438
bdeec802 2439#ifndef CONFIG_USER_ONLY
d3c64d6a 2440static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2441{
bdeec802 2442 CPUX86State *env = &cpu->env;
53a89e26 2443 DeviceState *dev = DEVICE(cpu);
449994eb 2444 APICCommonState *apic;
bdeec802
IM		 2445 const char *apic_type = "apic";
2446
2447 if (kvm_irqchip_in_kernel()) {
2448 apic_type = "kvm-apic";
2449 } else if (xen_enabled()) {
2450 apic_type = "xen-apic";
2451 }
2452
53a89e26 2453 env->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
bdeec802
IM		 2454 if (env->apic_state == NULL) {
2455 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2456 return;
2457 }
2458
2459 object_property_add_child(OBJECT(cpu), "apic",
2460 OBJECT(env->apic_state), NULL);
2461 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2462 /* TODO: convert to link<> */
449994eb 2463 apic = APIC_COMMON(env->apic_state);
60671e58 2464 apic->cpu = cpu;
d3c64d6a
IM		 2465}
2466
2467static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2468{
2469 CPUX86State *env = &cpu->env;
d3c64d6a
IM		 2470
2471 if (env->apic_state == NULL) {
2472 return;
2473 }
bdeec802
IM		 2474
2475 if (qdev_init(env->apic_state)) {
2476 error_setg(errp, "APIC device '%s' could not be initialized",
2477 object_get_typename(OBJECT(env->apic_state)));
2478 return;
2479 }
bdeec802 2480}
d3c64d6a
IM		 2481#else
2482static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2483{
2484}
bdeec802
IM		 2485#endif
2486
2b6f294c 2487static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2488{
14a10fc3 2489 CPUState *cs = CPU(dev);
2b6f294c
AF		 2490 X86CPU *cpu = X86_CPU(dev);
2491 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2492 CPUX86State *env = &cpu->env;
2b6f294c 2493 Error *local_err = NULL;
b34d12d1 2494
0514ef2f 2495 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2496 env->cpuid_level = 7;
2497 }
7a059953 2498
9b15cd9e
IM		 2499 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2500 * CPUID[1].EDX.
2501 */
2502 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2503 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2504 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2505 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2506 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2507 & CPUID_EXT2_AMD_ALIASES);
2508 }
2509
4586f157 2510 if (!kvm_enabled()) {
0514ef2f
EH		 2511 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2512 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2513 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
4586f157
IM		 2514#ifdef TARGET_X86_64
2515 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2516#endif
2517 );
0514ef2f
EH		 2518 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2519 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
4586f157 2520 } else {
5ec01c2e
IM		 2521 if (check_cpuid && kvm_check_features_against_host(cpu)
2522 && enforce_cpuid) {
4dc1f449
IM		 2523 error_setg(&local_err,
2524 "Host's CPU doesn't support requested features");
2525 goto out;
5ec01c2e 2526 }
a509d632
EH		 2527#ifdef CONFIG_KVM
2528 filter_features_for_kvm(cpu);
2529#endif
4586f157
IM		 2530 }
2531
65dee380
IM		 2532#ifndef CONFIG_USER_ONLY
2533 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2534
0514ef2f 2535 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2536 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2537 if (local_err != NULL) {
4dc1f449 2538 goto out;
bdeec802
IM		 2539 }
2540 }
65dee380
IM		 2541#endif
2542
7a059953 2543 mce_init(cpu);
14a10fc3 2544 qemu_init_vcpu(cs);
d3c64d6a
IM		 2545
2546 x86_cpu_apic_realize(cpu, &local_err);
2547 if (local_err != NULL) {
2548 goto out;
2549 }
14a10fc3 2550 cpu_reset(cs);
2b6f294c 2551
4dc1f449
IM		 2552 xcc->parent_realize(dev, &local_err);
2553out:
2554 if (local_err != NULL) {
2555 error_propagate(errp, local_err);
2556 return;
2557 }
7a059953
AF		 2558}
2559
8932cfdf
EH		 2560/* Enables contiguous-apic-ID mode, for compatibility */
2561static bool compat_apic_id_mode;
2562
2563void enable_compat_apic_id_mode(void)
2564{
2565 compat_apic_id_mode = true;
2566}
2567
cb41bad3
EH		 2568/* Calculates initial APIC ID for a specific CPU index
2569 *
2570 * Currently we need to be able to calculate the APIC ID from the CPU index
2571 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2572 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2573 * all CPUs up to max_cpus.
2574 */
2575uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2576{
8932cfdf
EH		 2577 uint32_t correct_id;
2578 static bool warned;
2579
2580 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2581 if (compat_apic_id_mode) {
2582 if (cpu_index != correct_id && !warned) {
2583 error_report("APIC IDs set in compatibility mode, "
2584 "CPU topology won't match the configuration");
2585 warned = true;
2586 }
2587 return cpu_index;
2588 } else {
2589 return correct_id;
2590 }
cb41bad3
EH		 2591}
2592
de024815
AF		 2593static void x86_cpu_initfn(Object *obj)
2594{
55e5c285 2595 CPUState *cs = CPU(obj);
de024815
AF		 2596 X86CPU *cpu = X86_CPU(obj);
2597 CPUX86State *env = &cpu->env;
d65e9815 2598 static int inited;
de024815 2599
c05efcb1 2600 cs->env_ptr = env;
de024815 2601 cpu_exec_init(env);
71ad61d3
AF		 2602
2603 object_property_add(obj, "family", "int",
95b8519d 2604 x86_cpuid_version_get_family,
71ad61d3 2605 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2606 object_property_add(obj, "model", "int",
67e30c83 2607 x86_cpuid_version_get_model,
c5291a4f 2608 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2609 object_property_add(obj, "stepping", "int",
35112e41 2610 x86_cpuid_version_get_stepping,
036e2222 2611 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2612 object_property_add(obj, "level", "int",
2613 x86_cpuid_get_level,
2614 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2615 object_property_add(obj, "xlevel", "int",
2616 x86_cpuid_get_xlevel,
2617 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2618 object_property_add_str(obj, "vendor",
2619 x86_cpuid_get_vendor,
2620 x86_cpuid_set_vendor, NULL);
938d4c25 2621 object_property_add_str(obj, "model-id",
63e886eb 2622 x86_cpuid_get_model_id,
938d4c25 2623 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2624 object_property_add(obj, "tsc-frequency", "int",
2625 x86_cpuid_get_tsc_freq,
2626 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2627 object_property_add(obj, "apic-id", "int",
2628 x86_cpuid_get_apic_id,
2629 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2630 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2631 x86_cpu_get_feature_words,
7e5292b5
EH		 2632 NULL, NULL, (void *)env->features, NULL);
2633 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2634 x86_cpu_get_feature_words,
2635 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2636
92067bf4 2637 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2638 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815
IM		 2639
2640 /* init various static tables used in TCG mode */
2641 if (tcg_enabled() && !inited) {
2642 inited = 1;
2643 optimize_flags_init();
2644#ifndef CONFIG_USER_ONLY
2645 cpu_set_debug_excp_handler(breakpoint_handler);
2646#endif
2647 }
de024815
AF		 2648}
2649
997395d3
IM		 2650static int64_t x86_cpu_get_arch_id(CPUState *cs)
2651{
2652 X86CPU *cpu = X86_CPU(cs);
2653 CPUX86State *env = &cpu->env;
2654
2655 return env->cpuid_apic_id;
2656}
2657
444d5590
AF		 2658static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2659{
2660 X86CPU *cpu = X86_CPU(cs);
2661
2662 return cpu->env.cr[0] & CR0_PG_MASK;
2663}
2664
f45748f1
AF		 2665static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2666{
2667 X86CPU *cpu = X86_CPU(cs);
2668
2669 cpu->env.eip = value;
2670}
2671
bdf7ae5b
AF		 2672static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2673{
2674 X86CPU *cpu = X86_CPU(cs);
2675
2676 cpu->env.eip = tb->pc - tb->cs_base;
2677}
2678
9337e3b6
EH		 2679static Property x86_cpu_properties[] = {
2680 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2681 DEFINE_PROP_END_OF_LIST()
2682};
2683
5fd2087a
AF		 2684static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2685{
2686 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2687 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2688 DeviceClass *dc = DEVICE_CLASS(oc);
2689
2690 xcc->parent_realize = dc->realize;
2691 dc->realize = x86_cpu_realizefn;
62fc403f 2692 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2693 dc->props = x86_cpu_properties;
5fd2087a
AF		 2694
2695 xcc->parent_reset = cc->reset;
2696 cc->reset = x86_cpu_reset;
91b1df8c 2697 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2698
97a8ea5a 2699 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2700 cc->dump_state = x86_cpu_dump_state;
f45748f1 2701 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2702 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2703 cc->gdb_read_register = x86_cpu_gdb_read_register;
2704 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2705 cc->get_arch_id = x86_cpu_get_arch_id;
2706 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
c72bf468 2707#ifndef CONFIG_USER_ONLY
a23bbfda 2708 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2709 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2710 cc->write_elf64_note = x86_cpu_write_elf64_note;
2711 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2712 cc->write_elf32_note = x86_cpu_write_elf32_note;
2713 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2714 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2715#endif
a0e372f0 2716 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2717}
2718
2719static const TypeInfo x86_cpu_type_info = {
2720 .name = TYPE_X86_CPU,
2721 .parent = TYPE_CPU,
2722 .instance_size = sizeof(X86CPU),
de024815 2723 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2724 .abstract = false,
2725 .class_size = sizeof(X86CPUClass),
2726 .class_init = x86_cpu_common_class_init,
2727};
2728
2729static void x86_cpu_register_types(void)
2730{
2731 type_register_static(&x86_cpu_type_info);
2732}
2733
2734type_init(x86_cpu_register_types)
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