]>
Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
e495606d | 23 | |
6aa8b732 | 24 | #include <linux/module.h> |
9d8f549d | 25 | #include <linux/kernel.h> |
6aa8b732 AK |
26 | #include <linux/vmalloc.h> |
27 | #include <linux/highmem.h> | |
e8edc6e0 | 28 | #include <linux/sched.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
6aa8b732 | 31 | |
67ec6607 | 32 | #include <asm/tlbflush.h> |
e495606d | 33 | #include <asm/desc.h> |
631bc487 | 34 | #include <asm/kvm_para.h> |
6aa8b732 | 35 | |
63d1142f | 36 | #include <asm/virtext.h> |
229456fc | 37 | #include "trace.h" |
63d1142f | 38 | |
4ecac3fd AK |
39 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
40 | ||
6aa8b732 AK |
41 | MODULE_AUTHOR("Qumranet"); |
42 | MODULE_LICENSE("GPL"); | |
43 | ||
44 | #define IOPM_ALLOC_ORDER 2 | |
45 | #define MSRPM_ALLOC_ORDER 1 | |
46 | ||
6aa8b732 AK |
47 | #define SEG_TYPE_LDT 2 |
48 | #define SEG_TYPE_BUSY_TSS16 3 | |
49 | ||
6bc31bdc AP |
50 | #define SVM_FEATURE_NPT (1 << 0) |
51 | #define SVM_FEATURE_LBRV (1 << 1) | |
52 | #define SVM_FEATURE_SVML (1 << 2) | |
53 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
54 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
55 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
56 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
57 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 58 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 59 | |
410e4d57 JR |
60 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
61 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
62 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
63 | ||
24e09cbf JR |
64 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
65 | ||
67ec6607 JR |
66 | static bool erratum_383_found __read_mostly; |
67 | ||
6c8166a7 AK |
68 | static const u32 host_save_user_msrs[] = { |
69 | #ifdef CONFIG_X86_64 | |
70 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
71 | MSR_FS_BASE, | |
72 | #endif | |
73 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
74 | }; | |
75 | ||
76 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
77 | ||
78 | struct kvm_vcpu; | |
79 | ||
e6aa9abd JR |
80 | struct nested_state { |
81 | struct vmcb *hsave; | |
82 | u64 hsave_msr; | |
4a810181 | 83 | u64 vm_cr_msr; |
e6aa9abd JR |
84 | u64 vmcb; |
85 | ||
86 | /* These are the merged vectors */ | |
87 | u32 *msrpm; | |
88 | ||
89 | /* gpa pointers to the real vectors */ | |
90 | u64 vmcb_msrpm; | |
ce2ac085 | 91 | u64 vmcb_iopm; |
aad42c64 | 92 | |
cd3ff653 JR |
93 | /* A VMEXIT is required but not yet emulated */ |
94 | bool exit_required; | |
95 | ||
aad42c64 | 96 | /* cache for intercepts of the guest */ |
4ee546b4 | 97 | u32 intercept_cr; |
3aed041a | 98 | u32 intercept_dr; |
aad42c64 JR |
99 | u32 intercept_exceptions; |
100 | u64 intercept; | |
101 | ||
5bd2edc3 JR |
102 | /* Nested Paging related state */ |
103 | u64 nested_cr3; | |
e6aa9abd JR |
104 | }; |
105 | ||
323c3d80 JR |
106 | #define MSRPM_OFFSETS 16 |
107 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
108 | ||
6c8166a7 AK |
109 | struct vcpu_svm { |
110 | struct kvm_vcpu vcpu; | |
111 | struct vmcb *vmcb; | |
112 | unsigned long vmcb_pa; | |
113 | struct svm_cpu_data *svm_data; | |
114 | uint64_t asid_generation; | |
115 | uint64_t sysenter_esp; | |
116 | uint64_t sysenter_eip; | |
117 | ||
118 | u64 next_rip; | |
119 | ||
120 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 121 | struct { |
dacccfdd AK |
122 | u16 fs; |
123 | u16 gs; | |
124 | u16 ldt; | |
afe9e66f AK |
125 | u64 gs_base; |
126 | } host; | |
6c8166a7 AK |
127 | |
128 | u32 *msrpm; | |
6c8166a7 | 129 | |
bd3d1ec3 AK |
130 | ulong nmi_iret_rip; |
131 | ||
e6aa9abd | 132 | struct nested_state nested; |
6be7d306 JK |
133 | |
134 | bool nmi_singlestep; | |
66b7138f JK |
135 | |
136 | unsigned int3_injected; | |
137 | unsigned long int3_rip; | |
631bc487 | 138 | u32 apf_reason; |
6c8166a7 AK |
139 | }; |
140 | ||
455716fa JR |
141 | #define MSR_INVALID 0xffffffffU |
142 | ||
ac72a9b7 JR |
143 | static struct svm_direct_access_msrs { |
144 | u32 index; /* Index of the MSR */ | |
145 | bool always; /* True if intercept is always on */ | |
146 | } direct_access_msrs[] = { | |
8c06585d | 147 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
148 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
149 | #ifdef CONFIG_X86_64 | |
150 | { .index = MSR_GS_BASE, .always = true }, | |
151 | { .index = MSR_FS_BASE, .always = true }, | |
152 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
153 | { .index = MSR_LSTAR, .always = true }, | |
154 | { .index = MSR_CSTAR, .always = true }, | |
155 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
156 | #endif | |
157 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
158 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
159 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
160 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
161 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
162 | }; |
163 | ||
709ddebf JR |
164 | /* enable NPT for AMD64 and X86 with PAE */ |
165 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
166 | static bool npt_enabled = true; | |
167 | #else | |
e0231715 | 168 | static bool npt_enabled; |
709ddebf | 169 | #endif |
6c7dac72 JR |
170 | static int npt = 1; |
171 | ||
172 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 173 | |
4b6e4dca | 174 | static int nested = 1; |
236de055 AG |
175 | module_param(nested, int, S_IRUGO); |
176 | ||
44874f84 | 177 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 178 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 179 | |
410e4d57 | 180 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 181 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 182 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
183 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
184 | bool has_error_code, u32 error_code); | |
185 | ||
8d28fec4 | 186 | enum { |
116a0a23 JR |
187 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
188 | pause filter count */ | |
f56838e4 | 189 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 190 | VMCB_ASID, /* ASID */ |
decdbf6a | 191 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 192 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 193 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 194 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 195 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 196 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 197 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 198 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
8d28fec4 RJ |
199 | VMCB_DIRTY_MAX, |
200 | }; | |
201 | ||
0574dec0 JR |
202 | /* TPR and CR2 are always written before VMRUN */ |
203 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 RJ |
204 | |
205 | static inline void mark_all_dirty(struct vmcb *vmcb) | |
206 | { | |
207 | vmcb->control.clean = 0; | |
208 | } | |
209 | ||
210 | static inline void mark_all_clean(struct vmcb *vmcb) | |
211 | { | |
212 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
213 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
214 | } | |
215 | ||
216 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
217 | { | |
218 | vmcb->control.clean &= ~(1 << bit); | |
219 | } | |
220 | ||
a2fa3e9f GH |
221 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
222 | { | |
fb3f0f51 | 223 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
224 | } |
225 | ||
384c6368 JR |
226 | static void recalc_intercepts(struct vcpu_svm *svm) |
227 | { | |
228 | struct vmcb_control_area *c, *h; | |
229 | struct nested_state *g; | |
230 | ||
116a0a23 JR |
231 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
232 | ||
384c6368 JR |
233 | if (!is_guest_mode(&svm->vcpu)) |
234 | return; | |
235 | ||
236 | c = &svm->vmcb->control; | |
237 | h = &svm->nested.hsave->control; | |
238 | g = &svm->nested; | |
239 | ||
4ee546b4 | 240 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 241 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
242 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
243 | c->intercept = h->intercept | g->intercept; | |
244 | } | |
245 | ||
4ee546b4 RJ |
246 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
247 | { | |
248 | if (is_guest_mode(&svm->vcpu)) | |
249 | return svm->nested.hsave; | |
250 | else | |
251 | return svm->vmcb; | |
252 | } | |
253 | ||
254 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
255 | { | |
256 | struct vmcb *vmcb = get_host_vmcb(svm); | |
257 | ||
258 | vmcb->control.intercept_cr |= (1U << bit); | |
259 | ||
260 | recalc_intercepts(svm); | |
261 | } | |
262 | ||
263 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
264 | { | |
265 | struct vmcb *vmcb = get_host_vmcb(svm); | |
266 | ||
267 | vmcb->control.intercept_cr &= ~(1U << bit); | |
268 | ||
269 | recalc_intercepts(svm); | |
270 | } | |
271 | ||
272 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
273 | { | |
274 | struct vmcb *vmcb = get_host_vmcb(svm); | |
275 | ||
276 | return vmcb->control.intercept_cr & (1U << bit); | |
277 | } | |
278 | ||
3aed041a JR |
279 | static inline void set_dr_intercept(struct vcpu_svm *svm, int bit) |
280 | { | |
281 | struct vmcb *vmcb = get_host_vmcb(svm); | |
282 | ||
283 | vmcb->control.intercept_dr |= (1U << bit); | |
284 | ||
285 | recalc_intercepts(svm); | |
286 | } | |
287 | ||
288 | static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit) | |
289 | { | |
290 | struct vmcb *vmcb = get_host_vmcb(svm); | |
291 | ||
292 | vmcb->control.intercept_dr &= ~(1U << bit); | |
293 | ||
294 | recalc_intercepts(svm); | |
295 | } | |
296 | ||
18c918c5 JR |
297 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
298 | { | |
299 | struct vmcb *vmcb = get_host_vmcb(svm); | |
300 | ||
301 | vmcb->control.intercept_exceptions |= (1U << bit); | |
302 | ||
303 | recalc_intercepts(svm); | |
304 | } | |
305 | ||
306 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
307 | { | |
308 | struct vmcb *vmcb = get_host_vmcb(svm); | |
309 | ||
310 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
311 | ||
312 | recalc_intercepts(svm); | |
313 | } | |
314 | ||
8a05a1b8 JR |
315 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
316 | { | |
317 | struct vmcb *vmcb = get_host_vmcb(svm); | |
318 | ||
319 | vmcb->control.intercept |= (1ULL << bit); | |
320 | ||
321 | recalc_intercepts(svm); | |
322 | } | |
323 | ||
324 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
325 | { | |
326 | struct vmcb *vmcb = get_host_vmcb(svm); | |
327 | ||
328 | vmcb->control.intercept &= ~(1ULL << bit); | |
329 | ||
330 | recalc_intercepts(svm); | |
331 | } | |
332 | ||
2af9194d JR |
333 | static inline void enable_gif(struct vcpu_svm *svm) |
334 | { | |
335 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
336 | } | |
337 | ||
338 | static inline void disable_gif(struct vcpu_svm *svm) | |
339 | { | |
340 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
341 | } | |
342 | ||
343 | static inline bool gif_set(struct vcpu_svm *svm) | |
344 | { | |
345 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
346 | } | |
347 | ||
4866d5e3 | 348 | static unsigned long iopm_base; |
6aa8b732 AK |
349 | |
350 | struct kvm_ldttss_desc { | |
351 | u16 limit0; | |
352 | u16 base0; | |
e0231715 JR |
353 | unsigned base1:8, type:5, dpl:2, p:1; |
354 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
355 | u32 base3; |
356 | u32 zero1; | |
357 | } __attribute__((packed)); | |
358 | ||
359 | struct svm_cpu_data { | |
360 | int cpu; | |
361 | ||
5008fdf5 AK |
362 | u64 asid_generation; |
363 | u32 max_asid; | |
364 | u32 next_asid; | |
6aa8b732 AK |
365 | struct kvm_ldttss_desc *tss_desc; |
366 | ||
367 | struct page *save_area; | |
368 | }; | |
369 | ||
370 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
371 | ||
372 | struct svm_init_data { | |
373 | int cpu; | |
374 | int r; | |
375 | }; | |
376 | ||
377 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
378 | ||
9d8f549d | 379 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
380 | #define MSRS_RANGE_SIZE 2048 |
381 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
382 | ||
455716fa JR |
383 | static u32 svm_msrpm_offset(u32 msr) |
384 | { | |
385 | u32 offset; | |
386 | int i; | |
387 | ||
388 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
389 | if (msr < msrpm_ranges[i] || | |
390 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
391 | continue; | |
392 | ||
393 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
394 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
395 | ||
396 | /* Now we have the u8 offset - but need the u32 offset */ | |
397 | return offset / 4; | |
398 | } | |
399 | ||
400 | /* MSR not in any range */ | |
401 | return MSR_INVALID; | |
402 | } | |
403 | ||
6aa8b732 AK |
404 | #define MAX_INST_SIZE 15 |
405 | ||
6aa8b732 AK |
406 | static inline void clgi(void) |
407 | { | |
4ecac3fd | 408 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
409 | } |
410 | ||
411 | static inline void stgi(void) | |
412 | { | |
4ecac3fd | 413 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
414 | } |
415 | ||
416 | static inline void invlpga(unsigned long addr, u32 asid) | |
417 | { | |
e0231715 | 418 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
419 | } |
420 | ||
4b16184c JR |
421 | static int get_npt_level(void) |
422 | { | |
423 | #ifdef CONFIG_X86_64 | |
424 | return PT64_ROOT_LEVEL; | |
425 | #else | |
426 | return PT32E_ROOT_LEVEL; | |
427 | #endif | |
428 | } | |
429 | ||
6aa8b732 AK |
430 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
431 | { | |
6dc696d4 | 432 | vcpu->arch.efer = efer; |
709ddebf | 433 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 434 | efer &= ~EFER_LME; |
6aa8b732 | 435 | |
9962d032 | 436 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 437 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
438 | } |
439 | ||
6aa8b732 AK |
440 | static int is_external_interrupt(u32 info) |
441 | { | |
442 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
443 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
444 | } | |
445 | ||
2809f5d2 GC |
446 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
447 | { | |
448 | struct vcpu_svm *svm = to_svm(vcpu); | |
449 | u32 ret = 0; | |
450 | ||
451 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 452 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
453 | return ret & mask; |
454 | } | |
455 | ||
456 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
457 | { | |
458 | struct vcpu_svm *svm = to_svm(vcpu); | |
459 | ||
460 | if (mask == 0) | |
461 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
462 | else | |
463 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
464 | ||
465 | } | |
466 | ||
6aa8b732 AK |
467 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
468 | { | |
a2fa3e9f GH |
469 | struct vcpu_svm *svm = to_svm(vcpu); |
470 | ||
6bc31bdc AP |
471 | if (svm->vmcb->control.next_rip != 0) |
472 | svm->next_rip = svm->vmcb->control.next_rip; | |
473 | ||
a2fa3e9f | 474 | if (!svm->next_rip) { |
51d8b661 | 475 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
476 | EMULATE_DONE) |
477 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
478 | return; |
479 | } | |
5fdbf976 MT |
480 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
481 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
482 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 483 | |
5fdbf976 | 484 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 485 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
486 | } |
487 | ||
116a4752 | 488 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
489 | bool has_error_code, u32 error_code, |
490 | bool reinject) | |
116a4752 JK |
491 | { |
492 | struct vcpu_svm *svm = to_svm(vcpu); | |
493 | ||
e0231715 JR |
494 | /* |
495 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
496 | * handle the exception | |
497 | */ | |
ce7ddec4 JR |
498 | if (!reinject && |
499 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
500 | return; |
501 | ||
2a6b20b8 | 502 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
503 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
504 | ||
505 | /* | |
506 | * For guest debugging where we have to reinject #BP if some | |
507 | * INT3 is guest-owned: | |
508 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
509 | * raises a fault that is not intercepted. Still better than | |
510 | * failing in all cases. | |
511 | */ | |
512 | skip_emulated_instruction(&svm->vcpu); | |
513 | rip = kvm_rip_read(&svm->vcpu); | |
514 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
515 | svm->int3_injected = rip - old_rip; | |
516 | } | |
517 | ||
116a4752 JK |
518 | svm->vmcb->control.event_inj = nr |
519 | | SVM_EVTINJ_VALID | |
520 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
521 | | SVM_EVTINJ_TYPE_EXEPT; | |
522 | svm->vmcb->control.event_inj_err = error_code; | |
523 | } | |
524 | ||
67ec6607 JR |
525 | static void svm_init_erratum_383(void) |
526 | { | |
527 | u32 low, high; | |
528 | int err; | |
529 | u64 val; | |
530 | ||
1be85a6d | 531 | if (!cpu_has_amd_erratum(amd_erratum_383)) |
67ec6607 JR |
532 | return; |
533 | ||
534 | /* Use _safe variants to not break nested virtualization */ | |
535 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
536 | if (err) | |
537 | return; | |
538 | ||
539 | val |= (1ULL << 47); | |
540 | ||
541 | low = lower_32_bits(val); | |
542 | high = upper_32_bits(val); | |
543 | ||
544 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
545 | ||
546 | erratum_383_found = true; | |
547 | } | |
548 | ||
6aa8b732 AK |
549 | static int has_svm(void) |
550 | { | |
63d1142f | 551 | const char *msg; |
6aa8b732 | 552 | |
63d1142f | 553 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 554 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
555 | return 0; |
556 | } | |
557 | ||
6aa8b732 AK |
558 | return 1; |
559 | } | |
560 | ||
561 | static void svm_hardware_disable(void *garbage) | |
562 | { | |
2c8dceeb | 563 | cpu_svm_disable(); |
6aa8b732 AK |
564 | } |
565 | ||
10474ae8 | 566 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
567 | { |
568 | ||
0fe1e009 | 569 | struct svm_cpu_data *sd; |
6aa8b732 | 570 | uint64_t efer; |
89a27f4d | 571 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
572 | struct desc_struct *gdt; |
573 | int me = raw_smp_processor_id(); | |
574 | ||
10474ae8 AG |
575 | rdmsrl(MSR_EFER, efer); |
576 | if (efer & EFER_SVME) | |
577 | return -EBUSY; | |
578 | ||
6aa8b732 | 579 | if (!has_svm()) { |
e6732a5a ZA |
580 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", |
581 | me); | |
10474ae8 | 582 | return -EINVAL; |
6aa8b732 | 583 | } |
0fe1e009 | 584 | sd = per_cpu(svm_data, me); |
6aa8b732 | 585 | |
0fe1e009 | 586 | if (!sd) { |
e6732a5a | 587 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", |
6aa8b732 | 588 | me); |
10474ae8 | 589 | return -EINVAL; |
6aa8b732 AK |
590 | } |
591 | ||
0fe1e009 TH |
592 | sd->asid_generation = 1; |
593 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
594 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 595 | |
d6ab1ed4 | 596 | native_store_gdt(&gdt_descr); |
89a27f4d | 597 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 598 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 599 | |
9962d032 | 600 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 601 | |
d0316554 | 602 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 603 | |
67ec6607 JR |
604 | svm_init_erratum_383(); |
605 | ||
10474ae8 | 606 | return 0; |
6aa8b732 AK |
607 | } |
608 | ||
0da1db75 JR |
609 | static void svm_cpu_uninit(int cpu) |
610 | { | |
0fe1e009 | 611 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 612 | |
0fe1e009 | 613 | if (!sd) |
0da1db75 JR |
614 | return; |
615 | ||
616 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
617 | __free_page(sd->save_area); |
618 | kfree(sd); | |
0da1db75 JR |
619 | } |
620 | ||
6aa8b732 AK |
621 | static int svm_cpu_init(int cpu) |
622 | { | |
0fe1e009 | 623 | struct svm_cpu_data *sd; |
6aa8b732 AK |
624 | int r; |
625 | ||
0fe1e009 TH |
626 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
627 | if (!sd) | |
6aa8b732 | 628 | return -ENOMEM; |
0fe1e009 TH |
629 | sd->cpu = cpu; |
630 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 631 | r = -ENOMEM; |
0fe1e009 | 632 | if (!sd->save_area) |
6aa8b732 AK |
633 | goto err_1; |
634 | ||
0fe1e009 | 635 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
636 | |
637 | return 0; | |
638 | ||
639 | err_1: | |
0fe1e009 | 640 | kfree(sd); |
6aa8b732 AK |
641 | return r; |
642 | ||
643 | } | |
644 | ||
ac72a9b7 JR |
645 | static bool valid_msr_intercept(u32 index) |
646 | { | |
647 | int i; | |
648 | ||
649 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
650 | if (direct_access_msrs[i].index == index) | |
651 | return true; | |
652 | ||
653 | return false; | |
654 | } | |
655 | ||
bfc733a7 RR |
656 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
657 | int read, int write) | |
6aa8b732 | 658 | { |
455716fa JR |
659 | u8 bit_read, bit_write; |
660 | unsigned long tmp; | |
661 | u32 offset; | |
6aa8b732 | 662 | |
ac72a9b7 JR |
663 | /* |
664 | * If this warning triggers extend the direct_access_msrs list at the | |
665 | * beginning of the file | |
666 | */ | |
667 | WARN_ON(!valid_msr_intercept(msr)); | |
668 | ||
455716fa JR |
669 | offset = svm_msrpm_offset(msr); |
670 | bit_read = 2 * (msr & 0x0f); | |
671 | bit_write = 2 * (msr & 0x0f) + 1; | |
672 | tmp = msrpm[offset]; | |
673 | ||
674 | BUG_ON(offset == MSR_INVALID); | |
675 | ||
676 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
677 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
678 | ||
679 | msrpm[offset] = tmp; | |
6aa8b732 AK |
680 | } |
681 | ||
f65c229c | 682 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
683 | { |
684 | int i; | |
685 | ||
f65c229c JR |
686 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
687 | ||
ac72a9b7 JR |
688 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
689 | if (!direct_access_msrs[i].always) | |
690 | continue; | |
691 | ||
692 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
693 | } | |
f65c229c JR |
694 | } |
695 | ||
323c3d80 JR |
696 | static void add_msr_offset(u32 offset) |
697 | { | |
698 | int i; | |
699 | ||
700 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
701 | ||
702 | /* Offset already in list? */ | |
703 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 704 | return; |
323c3d80 JR |
705 | |
706 | /* Slot used by another offset? */ | |
707 | if (msrpm_offsets[i] != MSR_INVALID) | |
708 | continue; | |
709 | ||
710 | /* Add offset to list */ | |
711 | msrpm_offsets[i] = offset; | |
712 | ||
713 | return; | |
6aa8b732 | 714 | } |
323c3d80 JR |
715 | |
716 | /* | |
717 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
718 | * increase MSRPM_OFFSETS in this case. | |
719 | */ | |
bfc733a7 | 720 | BUG(); |
6aa8b732 AK |
721 | } |
722 | ||
323c3d80 | 723 | static void init_msrpm_offsets(void) |
f65c229c | 724 | { |
323c3d80 | 725 | int i; |
f65c229c | 726 | |
323c3d80 JR |
727 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
728 | ||
729 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
730 | u32 offset; | |
731 | ||
732 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
733 | BUG_ON(offset == MSR_INVALID); | |
734 | ||
735 | add_msr_offset(offset); | |
736 | } | |
f65c229c JR |
737 | } |
738 | ||
24e09cbf JR |
739 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
740 | { | |
741 | u32 *msrpm = svm->msrpm; | |
742 | ||
743 | svm->vmcb->control.lbr_ctl = 1; | |
744 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
745 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
746 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
747 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
748 | } | |
749 | ||
750 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
751 | { | |
752 | u32 *msrpm = svm->msrpm; | |
753 | ||
754 | svm->vmcb->control.lbr_ctl = 0; | |
755 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
756 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
757 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
758 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
759 | } | |
760 | ||
6aa8b732 AK |
761 | static __init int svm_hardware_setup(void) |
762 | { | |
763 | int cpu; | |
764 | struct page *iopm_pages; | |
f65c229c | 765 | void *iopm_va; |
6aa8b732 AK |
766 | int r; |
767 | ||
6aa8b732 AK |
768 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
769 | ||
770 | if (!iopm_pages) | |
771 | return -ENOMEM; | |
c8681339 AL |
772 | |
773 | iopm_va = page_address(iopm_pages); | |
774 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
775 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
776 | ||
323c3d80 JR |
777 | init_msrpm_offsets(); |
778 | ||
50a37eb4 JR |
779 | if (boot_cpu_has(X86_FEATURE_NX)) |
780 | kvm_enable_efer_bits(EFER_NX); | |
781 | ||
1b2fd70c AG |
782 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
783 | kvm_enable_efer_bits(EFER_FFXSR); | |
784 | ||
236de055 AG |
785 | if (nested) { |
786 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 787 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
788 | } |
789 | ||
3230bb47 | 790 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
791 | r = svm_cpu_init(cpu); |
792 | if (r) | |
f65c229c | 793 | goto err; |
6aa8b732 | 794 | } |
33bd6a0b | 795 | |
2a6b20b8 | 796 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
797 | npt_enabled = false; |
798 | ||
6c7dac72 JR |
799 | if (npt_enabled && !npt) { |
800 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
801 | npt_enabled = false; | |
802 | } | |
803 | ||
18552672 | 804 | if (npt_enabled) { |
e3da3acd | 805 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 806 | kvm_enable_tdp(); |
5f4cb662 JR |
807 | } else |
808 | kvm_disable_tdp(); | |
e3da3acd | 809 | |
6aa8b732 AK |
810 | return 0; |
811 | ||
f65c229c | 812 | err: |
6aa8b732 AK |
813 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
814 | iopm_base = 0; | |
815 | return r; | |
816 | } | |
817 | ||
818 | static __exit void svm_hardware_unsetup(void) | |
819 | { | |
0da1db75 JR |
820 | int cpu; |
821 | ||
3230bb47 | 822 | for_each_possible_cpu(cpu) |
0da1db75 JR |
823 | svm_cpu_uninit(cpu); |
824 | ||
6aa8b732 | 825 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 826 | iopm_base = 0; |
6aa8b732 AK |
827 | } |
828 | ||
829 | static void init_seg(struct vmcb_seg *seg) | |
830 | { | |
831 | seg->selector = 0; | |
832 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 833 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
834 | seg->limit = 0xffff; |
835 | seg->base = 0; | |
836 | } | |
837 | ||
838 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
839 | { | |
840 | seg->selector = 0; | |
841 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
842 | seg->limit = 0xffff; | |
843 | seg->base = 0; | |
844 | } | |
845 | ||
f4e1b3c8 ZA |
846 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
847 | { | |
848 | struct vcpu_svm *svm = to_svm(vcpu); | |
849 | u64 g_tsc_offset = 0; | |
850 | ||
2030753d | 851 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
852 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
853 | svm->nested.hsave->control.tsc_offset; | |
854 | svm->nested.hsave->control.tsc_offset = offset; | |
855 | } | |
856 | ||
857 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
858 | |
859 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
860 | } |
861 | ||
e48672fa ZA |
862 | static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) |
863 | { | |
864 | struct vcpu_svm *svm = to_svm(vcpu); | |
865 | ||
866 | svm->vmcb->control.tsc_offset += adjustment; | |
2030753d | 867 | if (is_guest_mode(vcpu)) |
e48672fa | 868 | svm->nested.hsave->control.tsc_offset += adjustment; |
116a0a23 | 869 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
e48672fa ZA |
870 | } |
871 | ||
e6101a96 | 872 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 873 | { |
e6101a96 JR |
874 | struct vmcb_control_area *control = &svm->vmcb->control; |
875 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 876 | |
bff78274 | 877 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 878 | svm->vcpu.arch.hflags = 0; |
bff78274 | 879 | |
4ee546b4 RJ |
880 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
881 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
882 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
883 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
884 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
885 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
886 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 887 | |
3aed041a JR |
888 | set_dr_intercept(svm, INTERCEPT_DR0_READ); |
889 | set_dr_intercept(svm, INTERCEPT_DR1_READ); | |
890 | set_dr_intercept(svm, INTERCEPT_DR2_READ); | |
891 | set_dr_intercept(svm, INTERCEPT_DR3_READ); | |
892 | set_dr_intercept(svm, INTERCEPT_DR4_READ); | |
893 | set_dr_intercept(svm, INTERCEPT_DR5_READ); | |
894 | set_dr_intercept(svm, INTERCEPT_DR6_READ); | |
895 | set_dr_intercept(svm, INTERCEPT_DR7_READ); | |
896 | ||
897 | set_dr_intercept(svm, INTERCEPT_DR0_WRITE); | |
898 | set_dr_intercept(svm, INTERCEPT_DR1_WRITE); | |
899 | set_dr_intercept(svm, INTERCEPT_DR2_WRITE); | |
900 | set_dr_intercept(svm, INTERCEPT_DR3_WRITE); | |
901 | set_dr_intercept(svm, INTERCEPT_DR4_WRITE); | |
902 | set_dr_intercept(svm, INTERCEPT_DR5_WRITE); | |
903 | set_dr_intercept(svm, INTERCEPT_DR6_WRITE); | |
904 | set_dr_intercept(svm, INTERCEPT_DR7_WRITE); | |
6aa8b732 | 905 | |
18c918c5 JR |
906 | set_exception_intercept(svm, PF_VECTOR); |
907 | set_exception_intercept(svm, UD_VECTOR); | |
908 | set_exception_intercept(svm, MC_VECTOR); | |
6aa8b732 | 909 | |
8a05a1b8 JR |
910 | set_intercept(svm, INTERCEPT_INTR); |
911 | set_intercept(svm, INTERCEPT_NMI); | |
912 | set_intercept(svm, INTERCEPT_SMI); | |
913 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
914 | set_intercept(svm, INTERCEPT_CPUID); | |
915 | set_intercept(svm, INTERCEPT_INVD); | |
916 | set_intercept(svm, INTERCEPT_HLT); | |
917 | set_intercept(svm, INTERCEPT_INVLPG); | |
918 | set_intercept(svm, INTERCEPT_INVLPGA); | |
919 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
920 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
921 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
922 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
923 | set_intercept(svm, INTERCEPT_VMRUN); | |
924 | set_intercept(svm, INTERCEPT_VMMCALL); | |
925 | set_intercept(svm, INTERCEPT_VMLOAD); | |
926 | set_intercept(svm, INTERCEPT_VMSAVE); | |
927 | set_intercept(svm, INTERCEPT_STGI); | |
928 | set_intercept(svm, INTERCEPT_CLGI); | |
929 | set_intercept(svm, INTERCEPT_SKINIT); | |
930 | set_intercept(svm, INTERCEPT_WBINVD); | |
931 | set_intercept(svm, INTERCEPT_MONITOR); | |
932 | set_intercept(svm, INTERCEPT_MWAIT); | |
81dd35d4 | 933 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 AK |
934 | |
935 | control->iopm_base_pa = iopm_base; | |
f65c229c | 936 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
937 | control->int_ctl = V_INTR_MASKING_MASK; |
938 | ||
939 | init_seg(&save->es); | |
940 | init_seg(&save->ss); | |
941 | init_seg(&save->ds); | |
942 | init_seg(&save->fs); | |
943 | init_seg(&save->gs); | |
944 | ||
945 | save->cs.selector = 0xf000; | |
946 | /* Executable/Readable Code Segment */ | |
947 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
948 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
949 | save->cs.limit = 0xffff; | |
d92899a0 AK |
950 | /* |
951 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
952 | * be consistent with it. | |
953 | * | |
954 | * Replace when we have real mode working for vmx. | |
955 | */ | |
956 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
957 | |
958 | save->gdtr.limit = 0xffff; | |
959 | save->idtr.limit = 0xffff; | |
960 | ||
961 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
962 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
963 | ||
eaa48512 | 964 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 965 | save->dr6 = 0xffff0ff0; |
6aa8b732 | 966 | save->dr7 = 0x400; |
f6e78475 | 967 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 968 | save->rip = 0x0000fff0; |
5fdbf976 | 969 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 970 | |
e0231715 JR |
971 | /* |
972 | * This is the guest-visible cr0 value. | |
18fa000a | 973 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 974 | */ |
678041ad MT |
975 | svm->vcpu.arch.cr0 = 0; |
976 | (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); | |
18fa000a | 977 | |
66aee91a | 978 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 979 | /* rdx = ?? */ |
709ddebf JR |
980 | |
981 | if (npt_enabled) { | |
982 | /* Setup VMCB for Nested Paging */ | |
983 | control->nested_ctl = 1; | |
8a05a1b8 JR |
984 | clr_intercept(svm, INTERCEPT_TASK_SWITCH); |
985 | clr_intercept(svm, INTERCEPT_INVLPG); | |
18c918c5 | 986 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
987 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
988 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
709ddebf | 989 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
990 | save->cr3 = 0; |
991 | save->cr4 = 0; | |
992 | } | |
f40f6a45 | 993 | svm->asid_generation = 0; |
1371d904 | 994 | |
e6aa9abd | 995 | svm->nested.vmcb = 0; |
2af9194d JR |
996 | svm->vcpu.arch.hflags = 0; |
997 | ||
2a6b20b8 | 998 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 999 | control->pause_filter_count = 3000; |
8a05a1b8 | 1000 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1001 | } |
1002 | ||
8d28fec4 RJ |
1003 | mark_all_dirty(svm->vmcb); |
1004 | ||
2af9194d | 1005 | enable_gif(svm); |
6aa8b732 AK |
1006 | } |
1007 | ||
e00c8cf2 | 1008 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
1009 | { |
1010 | struct vcpu_svm *svm = to_svm(vcpu); | |
1011 | ||
e6101a96 | 1012 | init_vmcb(svm); |
70433389 | 1013 | |
c5af89b6 | 1014 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 1015 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
1016 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
1017 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 1018 | } |
5fdbf976 MT |
1019 | vcpu->arch.regs_avail = ~0; |
1020 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
1021 | |
1022 | return 0; | |
04d2cc77 AK |
1023 | } |
1024 | ||
fb3f0f51 | 1025 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1026 | { |
a2fa3e9f | 1027 | struct vcpu_svm *svm; |
6aa8b732 | 1028 | struct page *page; |
f65c229c | 1029 | struct page *msrpm_pages; |
b286d5d8 | 1030 | struct page *hsave_page; |
3d6368ef | 1031 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1032 | int err; |
6aa8b732 | 1033 | |
c16f862d | 1034 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1035 | if (!svm) { |
1036 | err = -ENOMEM; | |
1037 | goto out; | |
1038 | } | |
1039 | ||
1040 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
1041 | if (err) | |
1042 | goto free_svm; | |
1043 | ||
b7af4043 | 1044 | err = -ENOMEM; |
6aa8b732 | 1045 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1046 | if (!page) |
fb3f0f51 | 1047 | goto uninit; |
6aa8b732 | 1048 | |
f65c229c JR |
1049 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1050 | if (!msrpm_pages) | |
b7af4043 | 1051 | goto free_page1; |
3d6368ef AG |
1052 | |
1053 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1054 | if (!nested_msrpm_pages) | |
b7af4043 | 1055 | goto free_page2; |
f65c229c | 1056 | |
b286d5d8 AG |
1057 | hsave_page = alloc_page(GFP_KERNEL); |
1058 | if (!hsave_page) | |
b7af4043 TY |
1059 | goto free_page3; |
1060 | ||
e6aa9abd | 1061 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1062 | |
b7af4043 TY |
1063 | svm->msrpm = page_address(msrpm_pages); |
1064 | svm_vcpu_init_msrpm(svm->msrpm); | |
1065 | ||
e6aa9abd | 1066 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1067 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1068 | |
a2fa3e9f GH |
1069 | svm->vmcb = page_address(page); |
1070 | clear_page(svm->vmcb); | |
1071 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1072 | svm->asid_generation = 0; | |
e6101a96 | 1073 | init_vmcb(svm); |
99e3e30a | 1074 | kvm_write_tsc(&svm->vcpu, 0); |
a2fa3e9f | 1075 | |
10ab25cd JK |
1076 | err = fx_init(&svm->vcpu); |
1077 | if (err) | |
1078 | goto free_page4; | |
1079 | ||
ad312c7c | 1080 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 1081 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 1082 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 1083 | |
fb3f0f51 | 1084 | return &svm->vcpu; |
36241b8c | 1085 | |
10ab25cd JK |
1086 | free_page4: |
1087 | __free_page(hsave_page); | |
b7af4043 TY |
1088 | free_page3: |
1089 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1090 | free_page2: | |
1091 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1092 | free_page1: | |
1093 | __free_page(page); | |
fb3f0f51 RR |
1094 | uninit: |
1095 | kvm_vcpu_uninit(&svm->vcpu); | |
1096 | free_svm: | |
a4770347 | 1097 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1098 | out: |
1099 | return ERR_PTR(err); | |
6aa8b732 AK |
1100 | } |
1101 | ||
1102 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1103 | { | |
a2fa3e9f GH |
1104 | struct vcpu_svm *svm = to_svm(vcpu); |
1105 | ||
fb3f0f51 | 1106 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1107 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1108 | __free_page(virt_to_page(svm->nested.hsave)); |
1109 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1110 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1111 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1112 | } |
1113 | ||
15ad7146 | 1114 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1115 | { |
a2fa3e9f | 1116 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1117 | int i; |
0cc5064d | 1118 | |
0cc5064d | 1119 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1120 | svm->asid_generation = 0; |
8d28fec4 | 1121 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1122 | } |
94dfbdb3 | 1123 | |
82ca2d10 AK |
1124 | #ifdef CONFIG_X86_64 |
1125 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1126 | #endif | |
dacccfdd AK |
1127 | savesegment(fs, svm->host.fs); |
1128 | savesegment(gs, svm->host.gs); | |
1129 | svm->host.ldt = kvm_read_ldt(); | |
1130 | ||
94dfbdb3 | 1131 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1132 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1133 | } |
1134 | ||
1135 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1136 | { | |
a2fa3e9f | 1137 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1138 | int i; |
1139 | ||
e1beb1d3 | 1140 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1141 | kvm_load_ldt(svm->host.ldt); |
1142 | #ifdef CONFIG_X86_64 | |
1143 | loadsegment(fs, svm->host.fs); | |
dacccfdd | 1144 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); |
893a5ab6 | 1145 | load_gs_index(svm->host.gs); |
dacccfdd | 1146 | #else |
831ca609 | 1147 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1148 | loadsegment(gs, svm->host.gs); |
831ca609 | 1149 | #endif |
dacccfdd | 1150 | #endif |
94dfbdb3 | 1151 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1152 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1153 | } |
1154 | ||
6aa8b732 AK |
1155 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1156 | { | |
a2fa3e9f | 1157 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1158 | } |
1159 | ||
1160 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1161 | { | |
a2fa3e9f | 1162 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1163 | } |
1164 | ||
6de4f3ad AK |
1165 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1166 | { | |
1167 | switch (reg) { | |
1168 | case VCPU_EXREG_PDPTR: | |
1169 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1170 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1171 | break; |
1172 | default: | |
1173 | BUG(); | |
1174 | } | |
1175 | } | |
1176 | ||
f0b85051 AG |
1177 | static void svm_set_vintr(struct vcpu_svm *svm) |
1178 | { | |
8a05a1b8 | 1179 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1180 | } |
1181 | ||
1182 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1183 | { | |
8a05a1b8 | 1184 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1185 | } |
1186 | ||
6aa8b732 AK |
1187 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1188 | { | |
a2fa3e9f | 1189 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1190 | |
1191 | switch (seg) { | |
1192 | case VCPU_SREG_CS: return &save->cs; | |
1193 | case VCPU_SREG_DS: return &save->ds; | |
1194 | case VCPU_SREG_ES: return &save->es; | |
1195 | case VCPU_SREG_FS: return &save->fs; | |
1196 | case VCPU_SREG_GS: return &save->gs; | |
1197 | case VCPU_SREG_SS: return &save->ss; | |
1198 | case VCPU_SREG_TR: return &save->tr; | |
1199 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1200 | } | |
1201 | BUG(); | |
8b6d44c7 | 1202 | return NULL; |
6aa8b732 AK |
1203 | } |
1204 | ||
1205 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1206 | { | |
1207 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1208 | ||
1209 | return s->base; | |
1210 | } | |
1211 | ||
1212 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1213 | struct kvm_segment *var, int seg) | |
1214 | { | |
1215 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1216 | ||
1217 | var->base = s->base; | |
1218 | var->limit = s->limit; | |
1219 | var->selector = s->selector; | |
1220 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1221 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1222 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1223 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1224 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1225 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1226 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1227 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1228 | |
e0231715 JR |
1229 | /* |
1230 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1231 | * for cross vendor migration purposes by "not present" |
1232 | */ | |
1233 | var->unusable = !var->present || (var->type == 0); | |
1234 | ||
1fbdc7a5 AP |
1235 | switch (seg) { |
1236 | case VCPU_SREG_CS: | |
1237 | /* | |
1238 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1239 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1240 | * Intel's VMENTRY has a check on the 'G' bit. | |
1241 | */ | |
25022acc | 1242 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1243 | break; |
1244 | case VCPU_SREG_TR: | |
1245 | /* | |
1246 | * Work around a bug where the busy flag in the tr selector | |
1247 | * isn't exposed | |
1248 | */ | |
c0d09828 | 1249 | var->type |= 0x2; |
1fbdc7a5 AP |
1250 | break; |
1251 | case VCPU_SREG_DS: | |
1252 | case VCPU_SREG_ES: | |
1253 | case VCPU_SREG_FS: | |
1254 | case VCPU_SREG_GS: | |
1255 | /* | |
1256 | * The accessed bit must always be set in the segment | |
1257 | * descriptor cache, although it can be cleared in the | |
1258 | * descriptor, the cached bit always remains at 1. Since | |
1259 | * Intel has a check on this, set it here to support | |
1260 | * cross-vendor migration. | |
1261 | */ | |
1262 | if (!var->unusable) | |
1263 | var->type |= 0x1; | |
1264 | break; | |
b586eb02 | 1265 | case VCPU_SREG_SS: |
e0231715 JR |
1266 | /* |
1267 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1268 | * descriptor is left as 1, although the whole segment has |
1269 | * been made unusable. Clear it here to pass an Intel VMX | |
1270 | * entry check when cross vendor migrating. | |
1271 | */ | |
1272 | if (var->unusable) | |
1273 | var->db = 0; | |
1274 | break; | |
1fbdc7a5 | 1275 | } |
6aa8b732 AK |
1276 | } |
1277 | ||
2e4d2653 IE |
1278 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1279 | { | |
1280 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1281 | ||
1282 | return save->cpl; | |
1283 | } | |
1284 | ||
89a27f4d | 1285 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1286 | { |
a2fa3e9f GH |
1287 | struct vcpu_svm *svm = to_svm(vcpu); |
1288 | ||
89a27f4d GN |
1289 | dt->size = svm->vmcb->save.idtr.limit; |
1290 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1291 | } |
1292 | ||
89a27f4d | 1293 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1294 | { |
a2fa3e9f GH |
1295 | struct vcpu_svm *svm = to_svm(vcpu); |
1296 | ||
89a27f4d GN |
1297 | svm->vmcb->save.idtr.limit = dt->size; |
1298 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1299 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1300 | } |
1301 | ||
89a27f4d | 1302 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1303 | { |
a2fa3e9f GH |
1304 | struct vcpu_svm *svm = to_svm(vcpu); |
1305 | ||
89a27f4d GN |
1306 | dt->size = svm->vmcb->save.gdtr.limit; |
1307 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1308 | } |
1309 | ||
89a27f4d | 1310 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1311 | { |
a2fa3e9f GH |
1312 | struct vcpu_svm *svm = to_svm(vcpu); |
1313 | ||
89a27f4d GN |
1314 | svm->vmcb->save.gdtr.limit = dt->size; |
1315 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1316 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1317 | } |
1318 | ||
e8467fda AK |
1319 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1320 | { | |
1321 | } | |
1322 | ||
aff48baa AK |
1323 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1324 | { | |
1325 | } | |
1326 | ||
25c4c276 | 1327 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1328 | { |
1329 | } | |
1330 | ||
d225157b AK |
1331 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1332 | { | |
1333 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1334 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1335 | ||
1336 | if (!svm->vcpu.fpu_active) | |
1337 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1338 | else | |
1339 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1340 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1341 | ||
dcca1a65 | 1342 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b AK |
1343 | |
1344 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1345 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1346 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1347 | } else { |
4ee546b4 RJ |
1348 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1349 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1350 | } |
1351 | } | |
1352 | ||
6aa8b732 AK |
1353 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1354 | { | |
a2fa3e9f GH |
1355 | struct vcpu_svm *svm = to_svm(vcpu); |
1356 | ||
05b3e0c2 | 1357 | #ifdef CONFIG_X86_64 |
f6801dff | 1358 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1359 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1360 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1361 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1362 | } |
1363 | ||
d77c26fc | 1364 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1365 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1366 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1367 | } |
1368 | } | |
1369 | #endif | |
ad312c7c | 1370 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1371 | |
1372 | if (!npt_enabled) | |
1373 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1374 | |
1375 | if (!vcpu->fpu_active) | |
334df50a | 1376 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1377 | /* |
1378 | * re-enable caching here because the QEMU bios | |
1379 | * does not do it - this results in some delay at | |
1380 | * reboot | |
1381 | */ | |
1382 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1383 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1384 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1385 | update_cr0_intercept(svm); |
6aa8b732 AK |
1386 | } |
1387 | ||
1388 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1389 | { | |
6394b649 | 1390 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1391 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1392 | ||
1393 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
f40f6a45 | 1394 | svm_flush_tlb(vcpu); |
6394b649 | 1395 | |
ec077263 JR |
1396 | vcpu->arch.cr4 = cr4; |
1397 | if (!npt_enabled) | |
1398 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1399 | cr4 |= host_cr4_mce; |
ec077263 | 1400 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1401 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
1402 | } |
1403 | ||
1404 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1405 | struct kvm_segment *var, int seg) | |
1406 | { | |
a2fa3e9f | 1407 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1408 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1409 | ||
1410 | s->base = var->base; | |
1411 | s->limit = var->limit; | |
1412 | s->selector = var->selector; | |
1413 | if (var->unusable) | |
1414 | s->attrib = 0; | |
1415 | else { | |
1416 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1417 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1418 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1419 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1420 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1421 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1422 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1423 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1424 | } | |
1425 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1426 | svm->vmcb->save.cpl |
1427 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1428 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1429 | ||
060d0c9a | 1430 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
1431 | } |
1432 | ||
44c11430 | 1433 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1434 | { |
d0bfb940 JK |
1435 | struct vcpu_svm *svm = to_svm(vcpu); |
1436 | ||
18c918c5 JR |
1437 | clr_exception_intercept(svm, DB_VECTOR); |
1438 | clr_exception_intercept(svm, BP_VECTOR); | |
44c11430 | 1439 | |
6be7d306 | 1440 | if (svm->nmi_singlestep) |
18c918c5 | 1441 | set_exception_intercept(svm, DB_VECTOR); |
44c11430 | 1442 | |
d0bfb940 JK |
1443 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1444 | if (vcpu->guest_debug & | |
1445 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
18c918c5 | 1446 | set_exception_intercept(svm, DB_VECTOR); |
d0bfb940 | 1447 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1448 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1449 | } else |
1450 | vcpu->guest_debug = 0; | |
44c11430 GN |
1451 | } |
1452 | ||
355be0b9 | 1453 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
44c11430 | 1454 | { |
44c11430 GN |
1455 | struct vcpu_svm *svm = to_svm(vcpu); |
1456 | ||
ae675ef0 JK |
1457 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1458 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1459 | else | |
1460 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1461 | ||
72214b96 JR |
1462 | mark_dirty(svm->vmcb, VMCB_DR); |
1463 | ||
355be0b9 | 1464 | update_db_intercept(vcpu); |
6aa8b732 AK |
1465 | } |
1466 | ||
0fe1e009 | 1467 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1468 | { |
0fe1e009 TH |
1469 | if (sd->next_asid > sd->max_asid) { |
1470 | ++sd->asid_generation; | |
1471 | sd->next_asid = 1; | |
a2fa3e9f | 1472 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1473 | } |
1474 | ||
0fe1e009 TH |
1475 | svm->asid_generation = sd->asid_generation; |
1476 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
1477 | |
1478 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
1479 | } |
1480 | ||
020df079 | 1481 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1482 | { |
42dbaa5a | 1483 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1484 | |
020df079 | 1485 | svm->vmcb->save.dr7 = value; |
72214b96 | 1486 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
1487 | } |
1488 | ||
851ba692 | 1489 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1490 | { |
631bc487 | 1491 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1492 | u32 error_code; |
631bc487 | 1493 | int r = 1; |
6aa8b732 | 1494 | |
631bc487 GN |
1495 | switch (svm->apf_reason) { |
1496 | default: | |
1497 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1498 | |
631bc487 GN |
1499 | trace_kvm_page_fault(fault_address, error_code); |
1500 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1501 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
1502 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
1503 | svm->vmcb->control.insn_bytes, | |
1504 | svm->vmcb->control.insn_len); | |
631bc487 GN |
1505 | break; |
1506 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1507 | svm->apf_reason = 0; | |
1508 | local_irq_disable(); | |
1509 | kvm_async_pf_task_wait(fault_address); | |
1510 | local_irq_enable(); | |
1511 | break; | |
1512 | case KVM_PV_REASON_PAGE_READY: | |
1513 | svm->apf_reason = 0; | |
1514 | local_irq_disable(); | |
1515 | kvm_async_pf_task_wake(fault_address); | |
1516 | local_irq_enable(); | |
1517 | break; | |
1518 | } | |
1519 | return r; | |
6aa8b732 AK |
1520 | } |
1521 | ||
851ba692 | 1522 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1523 | { |
851ba692 AK |
1524 | struct kvm_run *kvm_run = svm->vcpu.run; |
1525 | ||
d0bfb940 | 1526 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1527 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1528 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1529 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1530 | return 1; | |
1531 | } | |
44c11430 | 1532 | |
6be7d306 JK |
1533 | if (svm->nmi_singlestep) { |
1534 | svm->nmi_singlestep = false; | |
44c11430 GN |
1535 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1536 | svm->vmcb->save.rflags &= | |
1537 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1538 | update_db_intercept(&svm->vcpu); | |
1539 | } | |
1540 | ||
1541 | if (svm->vcpu.guest_debug & | |
e0231715 | 1542 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1543 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1544 | kvm_run->debug.arch.pc = | |
1545 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1546 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1547 | return 0; | |
1548 | } | |
1549 | ||
1550 | return 1; | |
d0bfb940 JK |
1551 | } |
1552 | ||
851ba692 | 1553 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1554 | { |
851ba692 AK |
1555 | struct kvm_run *kvm_run = svm->vcpu.run; |
1556 | ||
d0bfb940 JK |
1557 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1558 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1559 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1560 | return 0; | |
1561 | } | |
1562 | ||
851ba692 | 1563 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1564 | { |
1565 | int er; | |
1566 | ||
51d8b661 | 1567 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1568 | if (er != EMULATE_DONE) |
7ee5d940 | 1569 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1570 | return 1; |
1571 | } | |
1572 | ||
6b52d186 | 1573 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1574 | { |
6b52d186 | 1575 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1576 | |
18c918c5 | 1577 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1578 | |
e756fc62 | 1579 | svm->vcpu.fpu_active = 1; |
d225157b | 1580 | update_cr0_intercept(svm); |
6b52d186 | 1581 | } |
a2fa3e9f | 1582 | |
6b52d186 AK |
1583 | static int nm_interception(struct vcpu_svm *svm) |
1584 | { | |
1585 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1586 | return 1; |
7807fa6c AL |
1587 | } |
1588 | ||
67ec6607 JR |
1589 | static bool is_erratum_383(void) |
1590 | { | |
1591 | int err, i; | |
1592 | u64 value; | |
1593 | ||
1594 | if (!erratum_383_found) | |
1595 | return false; | |
1596 | ||
1597 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1598 | if (err) | |
1599 | return false; | |
1600 | ||
1601 | /* Bit 62 may or may not be set for this mce */ | |
1602 | value &= ~(1ULL << 62); | |
1603 | ||
1604 | if (value != 0xb600000000010015ULL) | |
1605 | return false; | |
1606 | ||
1607 | /* Clear MCi_STATUS registers */ | |
1608 | for (i = 0; i < 6; ++i) | |
1609 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1610 | ||
1611 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1612 | if (!err) { | |
1613 | u32 low, high; | |
1614 | ||
1615 | value &= ~(1ULL << 2); | |
1616 | low = lower_32_bits(value); | |
1617 | high = upper_32_bits(value); | |
1618 | ||
1619 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1620 | } | |
1621 | ||
1622 | /* Flush tlb to evict multi-match entries */ | |
1623 | __flush_tlb_all(); | |
1624 | ||
1625 | return true; | |
1626 | } | |
1627 | ||
fe5913e4 | 1628 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1629 | { |
67ec6607 JR |
1630 | if (is_erratum_383()) { |
1631 | /* | |
1632 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1633 | * guest. | |
1634 | */ | |
1635 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1636 | ||
a8eeb04a | 1637 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1638 | |
1639 | return; | |
1640 | } | |
1641 | ||
53371b50 JR |
1642 | /* |
1643 | * On an #MC intercept the MCE handler is not called automatically in | |
1644 | * the host. So do it by hand here. | |
1645 | */ | |
1646 | asm volatile ( | |
1647 | "int $0x12\n"); | |
1648 | /* not sure if we ever come back to this point */ | |
1649 | ||
fe5913e4 JR |
1650 | return; |
1651 | } | |
1652 | ||
1653 | static int mc_interception(struct vcpu_svm *svm) | |
1654 | { | |
53371b50 JR |
1655 | return 1; |
1656 | } | |
1657 | ||
851ba692 | 1658 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1659 | { |
851ba692 AK |
1660 | struct kvm_run *kvm_run = svm->vcpu.run; |
1661 | ||
46fe4ddd JR |
1662 | /* |
1663 | * VMCB is undefined after a SHUTDOWN intercept | |
1664 | * so reinitialize it. | |
1665 | */ | |
a2fa3e9f | 1666 | clear_page(svm->vmcb); |
e6101a96 | 1667 | init_vmcb(svm); |
46fe4ddd JR |
1668 | |
1669 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1670 | return 0; | |
1671 | } | |
1672 | ||
851ba692 | 1673 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1674 | { |
cf8f70bf | 1675 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1676 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1677 | int size, in, string; |
039576c0 | 1678 | unsigned port; |
6aa8b732 | 1679 | |
e756fc62 | 1680 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1681 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1682 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1683 | if (string || in) |
51d8b661 | 1684 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 1685 | |
039576c0 AK |
1686 | port = io_info >> 16; |
1687 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1688 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1689 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1690 | |
1691 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1692 | } |
1693 | ||
851ba692 | 1694 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1695 | { |
1696 | return 1; | |
1697 | } | |
1698 | ||
851ba692 | 1699 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1700 | { |
1701 | ++svm->vcpu.stat.irq_exits; | |
1702 | return 1; | |
1703 | } | |
1704 | ||
851ba692 | 1705 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1706 | { |
1707 | return 1; | |
1708 | } | |
1709 | ||
851ba692 | 1710 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1711 | { |
5fdbf976 | 1712 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1713 | skip_emulated_instruction(&svm->vcpu); |
1714 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1715 | } |
1716 | ||
851ba692 | 1717 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1718 | { |
5fdbf976 | 1719 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1720 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1721 | kvm_emulate_hypercall(&svm->vcpu); |
1722 | return 1; | |
02e235bc AK |
1723 | } |
1724 | ||
5bd2edc3 JR |
1725 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1726 | { | |
1727 | struct vcpu_svm *svm = to_svm(vcpu); | |
1728 | ||
1729 | return svm->nested.nested_cr3; | |
1730 | } | |
1731 | ||
1732 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, | |
1733 | unsigned long root) | |
1734 | { | |
1735 | struct vcpu_svm *svm = to_svm(vcpu); | |
1736 | ||
1737 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 1738 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 1739 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
1740 | } |
1741 | ||
6389ee94 AK |
1742 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
1743 | struct x86_exception *fault) | |
5bd2edc3 JR |
1744 | { |
1745 | struct vcpu_svm *svm = to_svm(vcpu); | |
1746 | ||
1747 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1748 | svm->vmcb->control.exit_code_hi = 0; | |
6389ee94 AK |
1749 | svm->vmcb->control.exit_info_1 = fault->error_code; |
1750 | svm->vmcb->control.exit_info_2 = fault->address; | |
5bd2edc3 JR |
1751 | |
1752 | nested_svm_vmexit(svm); | |
1753 | } | |
1754 | ||
4b16184c JR |
1755 | static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
1756 | { | |
1757 | int r; | |
1758 | ||
1759 | r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); | |
1760 | ||
1761 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; | |
1762 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
1763 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; | |
1764 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
1765 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
1766 | ||
1767 | return r; | |
1768 | } | |
1769 | ||
1770 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1771 | { | |
1772 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1773 | } | |
1774 | ||
c0725420 AG |
1775 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1776 | { | |
f6801dff | 1777 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1778 | || !is_paging(&svm->vcpu)) { |
1779 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1780 | return 1; | |
1781 | } | |
1782 | ||
1783 | if (svm->vmcb->save.cpl) { | |
1784 | kvm_inject_gp(&svm->vcpu, 0); | |
1785 | return 1; | |
1786 | } | |
1787 | ||
1788 | return 0; | |
1789 | } | |
1790 | ||
cf74a78b AG |
1791 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1792 | bool has_error_code, u32 error_code) | |
1793 | { | |
b8e88bc8 JR |
1794 | int vmexit; |
1795 | ||
2030753d | 1796 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 1797 | return 0; |
cf74a78b | 1798 | |
0295ad7d JR |
1799 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1800 | svm->vmcb->control.exit_code_hi = 0; | |
1801 | svm->vmcb->control.exit_info_1 = error_code; | |
1802 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1803 | ||
b8e88bc8 JR |
1804 | vmexit = nested_svm_intercept(svm); |
1805 | if (vmexit == NESTED_EXIT_DONE) | |
1806 | svm->nested.exit_required = true; | |
1807 | ||
1808 | return vmexit; | |
cf74a78b AG |
1809 | } |
1810 | ||
8fe54654 JR |
1811 | /* This function returns true if it is save to enable the irq window */ |
1812 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 1813 | { |
2030753d | 1814 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 1815 | return true; |
cf74a78b | 1816 | |
26666957 | 1817 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 1818 | return true; |
cf74a78b | 1819 | |
26666957 | 1820 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 1821 | return false; |
cf74a78b | 1822 | |
a0a07cd2 GN |
1823 | /* |
1824 | * if vmexit was already requested (by intercepted exception | |
1825 | * for instance) do not overwrite it with "external interrupt" | |
1826 | * vmexit. | |
1827 | */ | |
1828 | if (svm->nested.exit_required) | |
1829 | return false; | |
1830 | ||
197717d5 JR |
1831 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1832 | svm->vmcb->control.exit_info_1 = 0; | |
1833 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 1834 | |
cd3ff653 JR |
1835 | if (svm->nested.intercept & 1ULL) { |
1836 | /* | |
1837 | * The #vmexit can't be emulated here directly because this | |
1838 | * code path runs with irqs and preemtion disabled. A | |
1839 | * #vmexit emulation might sleep. Only signal request for | |
1840 | * the #vmexit here. | |
1841 | */ | |
1842 | svm->nested.exit_required = true; | |
236649de | 1843 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 1844 | return false; |
cf74a78b AG |
1845 | } |
1846 | ||
8fe54654 | 1847 | return true; |
cf74a78b AG |
1848 | } |
1849 | ||
887f500c JR |
1850 | /* This function returns true if it is save to enable the nmi window */ |
1851 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
1852 | { | |
2030753d | 1853 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
1854 | return true; |
1855 | ||
1856 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
1857 | return true; | |
1858 | ||
1859 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
1860 | svm->nested.exit_required = true; | |
1861 | ||
1862 | return false; | |
cf74a78b AG |
1863 | } |
1864 | ||
7597f129 | 1865 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
1866 | { |
1867 | struct page *page; | |
1868 | ||
6c3bd3d7 JR |
1869 | might_sleep(); |
1870 | ||
34f80cfa | 1871 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
1872 | if (is_error_page(page)) |
1873 | goto error; | |
1874 | ||
7597f129 JR |
1875 | *_page = page; |
1876 | ||
1877 | return kmap(page); | |
34f80cfa JR |
1878 | |
1879 | error: | |
1880 | kvm_release_page_clean(page); | |
1881 | kvm_inject_gp(&svm->vcpu, 0); | |
1882 | ||
1883 | return NULL; | |
1884 | } | |
1885 | ||
7597f129 | 1886 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 1887 | { |
7597f129 | 1888 | kunmap(page); |
34f80cfa JR |
1889 | kvm_release_page_dirty(page); |
1890 | } | |
34f80cfa | 1891 | |
ce2ac085 JR |
1892 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
1893 | { | |
1894 | unsigned port; | |
1895 | u8 val, bit; | |
1896 | u64 gpa; | |
34f80cfa | 1897 | |
ce2ac085 JR |
1898 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
1899 | return NESTED_EXIT_HOST; | |
34f80cfa | 1900 | |
ce2ac085 JR |
1901 | port = svm->vmcb->control.exit_info_1 >> 16; |
1902 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
1903 | bit = port % 8; | |
1904 | val = 0; | |
1905 | ||
1906 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
1907 | val &= (1 << bit); | |
1908 | ||
1909 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
1910 | } |
1911 | ||
d2477826 | 1912 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 1913 | { |
0d6b3537 JR |
1914 | u32 offset, msr, value; |
1915 | int write, mask; | |
4c2161ae | 1916 | |
3d62d9aa | 1917 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 1918 | return NESTED_EXIT_HOST; |
3d62d9aa | 1919 | |
0d6b3537 JR |
1920 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
1921 | offset = svm_msrpm_offset(msr); | |
1922 | write = svm->vmcb->control.exit_info_1 & 1; | |
1923 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 1924 | |
0d6b3537 JR |
1925 | if (offset == MSR_INVALID) |
1926 | return NESTED_EXIT_DONE; | |
4c2161ae | 1927 | |
0d6b3537 JR |
1928 | /* Offset is in 32 bit units but need in 8 bit units */ |
1929 | offset *= 4; | |
4c2161ae | 1930 | |
0d6b3537 JR |
1931 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
1932 | return NESTED_EXIT_DONE; | |
3d62d9aa | 1933 | |
0d6b3537 | 1934 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
1935 | } |
1936 | ||
410e4d57 | 1937 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 1938 | { |
cf74a78b | 1939 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 1940 | |
410e4d57 JR |
1941 | switch (exit_code) { |
1942 | case SVM_EXIT_INTR: | |
1943 | case SVM_EXIT_NMI: | |
ff47a49b | 1944 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 1945 | return NESTED_EXIT_HOST; |
410e4d57 | 1946 | case SVM_EXIT_NPF: |
e0231715 | 1947 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
1948 | if (npt_enabled) |
1949 | return NESTED_EXIT_HOST; | |
1950 | break; | |
410e4d57 | 1951 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
1952 | /* When we're shadowing, trap PFs, but not async PF */ |
1953 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
1954 | return NESTED_EXIT_HOST; |
1955 | break; | |
66a562f7 JR |
1956 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
1957 | nm_interception(svm); | |
1958 | break; | |
410e4d57 JR |
1959 | default: |
1960 | break; | |
cf74a78b AG |
1961 | } |
1962 | ||
410e4d57 JR |
1963 | return NESTED_EXIT_CONTINUE; |
1964 | } | |
1965 | ||
1966 | /* | |
1967 | * If this function returns true, this #vmexit was already handled | |
1968 | */ | |
b8e88bc8 | 1969 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
1970 | { |
1971 | u32 exit_code = svm->vmcb->control.exit_code; | |
1972 | int vmexit = NESTED_EXIT_HOST; | |
1973 | ||
cf74a78b | 1974 | switch (exit_code) { |
9c4e40b9 | 1975 | case SVM_EXIT_MSR: |
3d62d9aa | 1976 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 1977 | break; |
ce2ac085 JR |
1978 | case SVM_EXIT_IOIO: |
1979 | vmexit = nested_svm_intercept_ioio(svm); | |
1980 | break; | |
4ee546b4 RJ |
1981 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
1982 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
1983 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 1984 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1985 | break; |
1986 | } | |
3aed041a JR |
1987 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
1988 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
1989 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 1990 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1991 | break; |
1992 | } | |
1993 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
1994 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 1995 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 1996 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
1997 | /* async page fault always cause vmexit */ |
1998 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
1999 | svm->apf_reason != 0) | |
2000 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2001 | break; |
2002 | } | |
228070b1 JR |
2003 | case SVM_EXIT_ERR: { |
2004 | vmexit = NESTED_EXIT_DONE; | |
2005 | break; | |
2006 | } | |
cf74a78b AG |
2007 | default: { |
2008 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2009 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2010 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2011 | } |
2012 | } | |
2013 | ||
b8e88bc8 JR |
2014 | return vmexit; |
2015 | } | |
2016 | ||
2017 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2018 | { | |
2019 | int vmexit; | |
2020 | ||
2021 | vmexit = nested_svm_intercept(svm); | |
2022 | ||
2023 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2024 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2025 | |
2026 | return vmexit; | |
cf74a78b AG |
2027 | } |
2028 | ||
0460a979 JR |
2029 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2030 | { | |
2031 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2032 | struct vmcb_control_area *from = &from_vmcb->control; | |
2033 | ||
4ee546b4 | 2034 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2035 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2036 | dst->intercept_exceptions = from->intercept_exceptions; |
2037 | dst->intercept = from->intercept; | |
2038 | dst->iopm_base_pa = from->iopm_base_pa; | |
2039 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2040 | dst->tsc_offset = from->tsc_offset; | |
2041 | dst->asid = from->asid; | |
2042 | dst->tlb_ctl = from->tlb_ctl; | |
2043 | dst->int_ctl = from->int_ctl; | |
2044 | dst->int_vector = from->int_vector; | |
2045 | dst->int_state = from->int_state; | |
2046 | dst->exit_code = from->exit_code; | |
2047 | dst->exit_code_hi = from->exit_code_hi; | |
2048 | dst->exit_info_1 = from->exit_info_1; | |
2049 | dst->exit_info_2 = from->exit_info_2; | |
2050 | dst->exit_int_info = from->exit_int_info; | |
2051 | dst->exit_int_info_err = from->exit_int_info_err; | |
2052 | dst->nested_ctl = from->nested_ctl; | |
2053 | dst->event_inj = from->event_inj; | |
2054 | dst->event_inj_err = from->event_inj_err; | |
2055 | dst->nested_cr3 = from->nested_cr3; | |
2056 | dst->lbr_ctl = from->lbr_ctl; | |
2057 | } | |
2058 | ||
34f80cfa | 2059 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2060 | { |
34f80cfa | 2061 | struct vmcb *nested_vmcb; |
e6aa9abd | 2062 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2063 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2064 | struct page *page; |
cf74a78b | 2065 | |
17897f36 JR |
2066 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2067 | vmcb->control.exit_info_1, | |
2068 | vmcb->control.exit_info_2, | |
2069 | vmcb->control.exit_int_info, | |
2070 | vmcb->control.exit_int_info_err); | |
2071 | ||
7597f129 | 2072 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2073 | if (!nested_vmcb) |
2074 | return 1; | |
2075 | ||
2030753d JR |
2076 | /* Exit Guest-Mode */ |
2077 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2078 | svm->nested.vmcb = 0; |
2079 | ||
cf74a78b | 2080 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2081 | disable_gif(svm); |
2082 | ||
2083 | nested_vmcb->save.es = vmcb->save.es; | |
2084 | nested_vmcb->save.cs = vmcb->save.cs; | |
2085 | nested_vmcb->save.ss = vmcb->save.ss; | |
2086 | nested_vmcb->save.ds = vmcb->save.ds; | |
2087 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2088 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2089 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2090 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2091 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2092 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2093 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2094 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2095 | nested_vmcb->save.rip = vmcb->save.rip; |
2096 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2097 | nested_vmcb->save.rax = vmcb->save.rax; | |
2098 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2099 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2100 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2101 | ||
2102 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2103 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2104 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2105 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2106 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2107 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2108 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2109 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2110 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
7a190667 | 2111 | nested_vmcb->control.next_rip = vmcb->control.next_rip; |
8d23c466 AG |
2112 | |
2113 | /* | |
2114 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2115 | * to make sure that we do not lose injected events. So check event_inj | |
2116 | * here and copy it to exit_int_info if it is valid. | |
2117 | * Exit_int_info and event_inj can't be both valid because the case | |
2118 | * below only happens on a VMRUN instruction intercept which has | |
2119 | * no valid exit_int_info set. | |
2120 | */ | |
2121 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2122 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2123 | ||
2124 | nc->exit_int_info = vmcb->control.event_inj; | |
2125 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2126 | } | |
2127 | ||
33740e40 JR |
2128 | nested_vmcb->control.tlb_ctl = 0; |
2129 | nested_vmcb->control.event_inj = 0; | |
2130 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2131 | |
2132 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2133 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2134 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2135 | ||
cf74a78b | 2136 | /* Restore the original control entries */ |
0460a979 | 2137 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2138 | |
219b65dc AG |
2139 | kvm_clear_exception_queue(&svm->vcpu); |
2140 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2141 | |
4b16184c JR |
2142 | svm->nested.nested_cr3 = 0; |
2143 | ||
cf74a78b AG |
2144 | /* Restore selected save entries */ |
2145 | svm->vmcb->save.es = hsave->save.es; | |
2146 | svm->vmcb->save.cs = hsave->save.cs; | |
2147 | svm->vmcb->save.ss = hsave->save.ss; | |
2148 | svm->vmcb->save.ds = hsave->save.ds; | |
2149 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2150 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2151 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2152 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2153 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2154 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2155 | if (npt_enabled) { | |
2156 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2157 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2158 | } else { | |
2390218b | 2159 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2160 | } |
2161 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2162 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2163 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2164 | svm->vmcb->save.dr7 = 0; | |
2165 | svm->vmcb->save.cpl = 0; | |
2166 | svm->vmcb->control.exit_int_info = 0; | |
2167 | ||
8d28fec4 RJ |
2168 | mark_all_dirty(svm->vmcb); |
2169 | ||
7597f129 | 2170 | nested_svm_unmap(page); |
cf74a78b | 2171 | |
4b16184c | 2172 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2173 | kvm_mmu_reset_context(&svm->vcpu); |
2174 | kvm_mmu_load(&svm->vcpu); | |
2175 | ||
2176 | return 0; | |
2177 | } | |
3d6368ef | 2178 | |
9738b2c9 | 2179 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2180 | { |
323c3d80 JR |
2181 | /* |
2182 | * This function merges the msr permission bitmaps of kvm and the | |
2183 | * nested vmcb. It is omptimized in that it only merges the parts where | |
2184 | * the kvm msr permission bitmap may contain zero bits | |
2185 | */ | |
3d6368ef | 2186 | int i; |
9738b2c9 | 2187 | |
323c3d80 JR |
2188 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2189 | return true; | |
9738b2c9 | 2190 | |
323c3d80 JR |
2191 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2192 | u32 value, p; | |
2193 | u64 offset; | |
9738b2c9 | 2194 | |
323c3d80 JR |
2195 | if (msrpm_offsets[i] == 0xffffffff) |
2196 | break; | |
3d6368ef | 2197 | |
0d6b3537 JR |
2198 | p = msrpm_offsets[i]; |
2199 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2200 | |
2201 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2202 | return false; | |
2203 | ||
2204 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2205 | } | |
3d6368ef | 2206 | |
323c3d80 | 2207 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2208 | |
2209 | return true; | |
3d6368ef AG |
2210 | } |
2211 | ||
52c65a30 JR |
2212 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2213 | { | |
2214 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2215 | return false; | |
2216 | ||
dbe77584 JR |
2217 | if (vmcb->control.asid == 0) |
2218 | return false; | |
2219 | ||
4b16184c JR |
2220 | if (vmcb->control.nested_ctl && !npt_enabled) |
2221 | return false; | |
2222 | ||
52c65a30 JR |
2223 | return true; |
2224 | } | |
2225 | ||
9738b2c9 | 2226 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2227 | { |
9738b2c9 | 2228 | struct vmcb *nested_vmcb; |
e6aa9abd | 2229 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2230 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2231 | struct page *page; |
06fc7772 | 2232 | u64 vmcb_gpa; |
3d6368ef | 2233 | |
06fc7772 | 2234 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2235 | |
7597f129 | 2236 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2237 | if (!nested_vmcb) |
2238 | return false; | |
2239 | ||
52c65a30 JR |
2240 | if (!nested_vmcb_checks(nested_vmcb)) { |
2241 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2242 | nested_vmcb->control.exit_code_hi = 0; | |
2243 | nested_vmcb->control.exit_info_1 = 0; | |
2244 | nested_vmcb->control.exit_info_2 = 0; | |
2245 | ||
2246 | nested_svm_unmap(page); | |
2247 | ||
2248 | return false; | |
2249 | } | |
2250 | ||
b75f4eb3 | 2251 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2252 | nested_vmcb->save.rip, |
2253 | nested_vmcb->control.int_ctl, | |
2254 | nested_vmcb->control.event_inj, | |
2255 | nested_vmcb->control.nested_ctl); | |
2256 | ||
4ee546b4 RJ |
2257 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2258 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2259 | nested_vmcb->control.intercept_exceptions, |
2260 | nested_vmcb->control.intercept); | |
2261 | ||
3d6368ef | 2262 | /* Clear internal status */ |
219b65dc AG |
2263 | kvm_clear_exception_queue(&svm->vcpu); |
2264 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2265 | |
e0231715 JR |
2266 | /* |
2267 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2268 | * restore everything when a VMEXIT occurs | |
2269 | */ | |
defbba56 JR |
2270 | hsave->save.es = vmcb->save.es; |
2271 | hsave->save.cs = vmcb->save.cs; | |
2272 | hsave->save.ss = vmcb->save.ss; | |
2273 | hsave->save.ds = vmcb->save.ds; | |
2274 | hsave->save.gdtr = vmcb->save.gdtr; | |
2275 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2276 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2277 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 | 2278 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2279 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); |
b75f4eb3 | 2280 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2281 | hsave->save.rsp = vmcb->save.rsp; |
2282 | hsave->save.rax = vmcb->save.rax; | |
2283 | if (npt_enabled) | |
2284 | hsave->save.cr3 = vmcb->save.cr3; | |
2285 | else | |
9f8fe504 | 2286 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2287 | |
0460a979 | 2288 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef | 2289 | |
f6e78475 | 2290 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2291 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2292 | else | |
2293 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2294 | ||
4b16184c JR |
2295 | if (nested_vmcb->control.nested_ctl) { |
2296 | kvm_mmu_unload(&svm->vcpu); | |
2297 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2298 | nested_svm_init_mmu_context(&svm->vcpu); | |
2299 | } | |
2300 | ||
3d6368ef AG |
2301 | /* Load the nested guest state */ |
2302 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2303 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2304 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2305 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2306 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2307 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2308 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2309 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
2310 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2311 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2312 | if (npt_enabled) { | |
2313 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2314 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2315 | } else |
2390218b | 2316 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2317 | |
2318 | /* Guest paging mode is active - reset mmu */ | |
2319 | kvm_mmu_reset_context(&svm->vcpu); | |
2320 | ||
defbba56 | 2321 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2322 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2323 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2324 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2325 | |
3d6368ef AG |
2326 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2327 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2328 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2329 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2330 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2331 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2332 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2333 | ||
f7138538 | 2334 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2335 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2336 | |
aad42c64 | 2337 | /* cache intercepts */ |
4ee546b4 | 2338 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2339 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2340 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2341 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2342 | ||
f40f6a45 | 2343 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2344 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2345 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2346 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2347 | else | |
2348 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2349 | ||
88ab24ad JR |
2350 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2351 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2352 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2353 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2354 | } |
2355 | ||
0d945bd9 | 2356 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2357 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2358 | |
88ab24ad | 2359 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2360 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2361 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2362 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2363 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2364 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2365 | ||
7597f129 | 2366 | nested_svm_unmap(page); |
9738b2c9 | 2367 | |
2030753d JR |
2368 | /* Enter Guest-Mode */ |
2369 | enter_guest_mode(&svm->vcpu); | |
2370 | ||
384c6368 JR |
2371 | /* |
2372 | * Merge guest and host intercepts - must be called with vcpu in | |
2373 | * guest-mode to take affect here | |
2374 | */ | |
2375 | recalc_intercepts(svm); | |
2376 | ||
06fc7772 | 2377 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2378 | |
2af9194d | 2379 | enable_gif(svm); |
3d6368ef | 2380 | |
8d28fec4 RJ |
2381 | mark_all_dirty(svm->vmcb); |
2382 | ||
9738b2c9 | 2383 | return true; |
3d6368ef AG |
2384 | } |
2385 | ||
9966bf68 | 2386 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2387 | { |
2388 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2389 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2390 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2391 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2392 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2393 | to_vmcb->save.star = from_vmcb->save.star; | |
2394 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2395 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2396 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2397 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2398 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2399 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2400 | } |
2401 | ||
851ba692 | 2402 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2403 | { |
9966bf68 | 2404 | struct vmcb *nested_vmcb; |
7597f129 | 2405 | struct page *page; |
9966bf68 | 2406 | |
5542675b AG |
2407 | if (nested_svm_check_permissions(svm)) |
2408 | return 1; | |
2409 | ||
2410 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2411 | skip_emulated_instruction(&svm->vcpu); | |
2412 | ||
7597f129 | 2413 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2414 | if (!nested_vmcb) |
2415 | return 1; | |
2416 | ||
2417 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
7597f129 | 2418 | nested_svm_unmap(page); |
5542675b AG |
2419 | |
2420 | return 1; | |
2421 | } | |
2422 | ||
851ba692 | 2423 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2424 | { |
9966bf68 | 2425 | struct vmcb *nested_vmcb; |
7597f129 | 2426 | struct page *page; |
9966bf68 | 2427 | |
5542675b AG |
2428 | if (nested_svm_check_permissions(svm)) |
2429 | return 1; | |
2430 | ||
2431 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2432 | skip_emulated_instruction(&svm->vcpu); | |
2433 | ||
7597f129 | 2434 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2435 | if (!nested_vmcb) |
2436 | return 1; | |
2437 | ||
2438 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
7597f129 | 2439 | nested_svm_unmap(page); |
5542675b AG |
2440 | |
2441 | return 1; | |
2442 | } | |
2443 | ||
851ba692 | 2444 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2445 | { |
3d6368ef AG |
2446 | if (nested_svm_check_permissions(svm)) |
2447 | return 1; | |
2448 | ||
b75f4eb3 RJ |
2449 | /* Save rip after vmrun instruction */ |
2450 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2451 | |
9738b2c9 | 2452 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2453 | return 1; |
2454 | ||
9738b2c9 | 2455 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2456 | goto failed; |
2457 | ||
2458 | return 1; | |
2459 | ||
2460 | failed: | |
2461 | ||
2462 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2463 | svm->vmcb->control.exit_code_hi = 0; | |
2464 | svm->vmcb->control.exit_info_1 = 0; | |
2465 | svm->vmcb->control.exit_info_2 = 0; | |
2466 | ||
2467 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2468 | |
2469 | return 1; | |
2470 | } | |
2471 | ||
851ba692 | 2472 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2473 | { |
2474 | if (nested_svm_check_permissions(svm)) | |
2475 | return 1; | |
2476 | ||
2477 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2478 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2479 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2480 | |
2af9194d | 2481 | enable_gif(svm); |
1371d904 AG |
2482 | |
2483 | return 1; | |
2484 | } | |
2485 | ||
851ba692 | 2486 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2487 | { |
2488 | if (nested_svm_check_permissions(svm)) | |
2489 | return 1; | |
2490 | ||
2491 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2492 | skip_emulated_instruction(&svm->vcpu); | |
2493 | ||
2af9194d | 2494 | disable_gif(svm); |
1371d904 AG |
2495 | |
2496 | /* After a CLGI no interrupts should come */ | |
2497 | svm_clear_vintr(svm); | |
2498 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2499 | ||
decdbf6a JR |
2500 | mark_dirty(svm->vmcb, VMCB_INTR); |
2501 | ||
1371d904 AG |
2502 | return 1; |
2503 | } | |
2504 | ||
851ba692 | 2505 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2506 | { |
2507 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2508 | |
ec1ff790 JR |
2509 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2510 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2511 | ||
ff092385 AG |
2512 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2513 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2514 | ||
2515 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2516 | skip_emulated_instruction(&svm->vcpu); | |
2517 | return 1; | |
2518 | } | |
2519 | ||
532a46b9 JR |
2520 | static int skinit_interception(struct vcpu_svm *svm) |
2521 | { | |
2522 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2523 | ||
2524 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2525 | return 1; | |
2526 | } | |
2527 | ||
81dd35d4 JR |
2528 | static int xsetbv_interception(struct vcpu_svm *svm) |
2529 | { | |
2530 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
2531 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
2532 | ||
2533 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
2534 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2535 | skip_emulated_instruction(&svm->vcpu); | |
2536 | } | |
2537 | ||
2538 | return 1; | |
2539 | } | |
2540 | ||
851ba692 | 2541 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2542 | { |
7ee5d940 | 2543 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2544 | return 1; |
2545 | } | |
2546 | ||
851ba692 | 2547 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2548 | { |
37817f29 | 2549 | u16 tss_selector; |
64a7ec06 GN |
2550 | int reason; |
2551 | int int_type = svm->vmcb->control.exit_int_info & | |
2552 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2553 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2554 | uint32_t type = |
2555 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2556 | uint32_t idt_v = | |
2557 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2558 | bool has_error_code = false; |
2559 | u32 error_code = 0; | |
37817f29 IE |
2560 | |
2561 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2562 | |
37817f29 IE |
2563 | if (svm->vmcb->control.exit_info_2 & |
2564 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2565 | reason = TASK_SWITCH_IRET; |
2566 | else if (svm->vmcb->control.exit_info_2 & | |
2567 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2568 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2569 | else if (idt_v) |
64a7ec06 GN |
2570 | reason = TASK_SWITCH_GATE; |
2571 | else | |
2572 | reason = TASK_SWITCH_CALL; | |
2573 | ||
fe8e7f83 GN |
2574 | if (reason == TASK_SWITCH_GATE) { |
2575 | switch (type) { | |
2576 | case SVM_EXITINTINFO_TYPE_NMI: | |
2577 | svm->vcpu.arch.nmi_injected = false; | |
2578 | break; | |
2579 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2580 | if (svm->vmcb->control.exit_info_2 & |
2581 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2582 | has_error_code = true; | |
2583 | error_code = | |
2584 | (u32)svm->vmcb->control.exit_info_2; | |
2585 | } | |
fe8e7f83 GN |
2586 | kvm_clear_exception_queue(&svm->vcpu); |
2587 | break; | |
2588 | case SVM_EXITINTINFO_TYPE_INTR: | |
2589 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2590 | break; | |
2591 | default: | |
2592 | break; | |
2593 | } | |
2594 | } | |
64a7ec06 | 2595 | |
8317c298 GN |
2596 | if (reason != TASK_SWITCH_GATE || |
2597 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2598 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2599 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2600 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2601 | |
acb54517 GN |
2602 | if (kvm_task_switch(&svm->vcpu, tss_selector, reason, |
2603 | has_error_code, error_code) == EMULATE_FAIL) { | |
2604 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2605 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2606 | svm->vcpu.run->internal.ndata = 0; | |
2607 | return 0; | |
2608 | } | |
2609 | return 1; | |
6aa8b732 AK |
2610 | } |
2611 | ||
851ba692 | 2612 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2613 | { |
5fdbf976 | 2614 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2615 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2616 | return 1; |
6aa8b732 AK |
2617 | } |
2618 | ||
851ba692 | 2619 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2620 | { |
2621 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 2622 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 2623 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 2624 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
95ba8273 GN |
2625 | return 1; |
2626 | } | |
2627 | ||
851ba692 | 2628 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2629 | { |
df4f3108 AP |
2630 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
2631 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
2632 | ||
2633 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
2634 | skip_emulated_instruction(&svm->vcpu); | |
2635 | return 1; | |
a7052897 MT |
2636 | } |
2637 | ||
851ba692 | 2638 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2639 | { |
51d8b661 | 2640 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
2641 | } |
2642 | ||
628afd2a JR |
2643 | bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val) |
2644 | { | |
2645 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
2646 | bool ret = false; | |
2647 | u64 intercept; | |
2648 | ||
2649 | intercept = svm->nested.intercept; | |
2650 | ||
2651 | if (!is_guest_mode(&svm->vcpu) || | |
2652 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
2653 | return false; | |
2654 | ||
2655 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
2656 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
2657 | ||
2658 | if (cr0 ^ val) { | |
2659 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
2660 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
2661 | } | |
2662 | ||
2663 | return ret; | |
2664 | } | |
2665 | ||
7ff76d58 AP |
2666 | #define CR_VALID (1ULL << 63) |
2667 | ||
2668 | static int cr_interception(struct vcpu_svm *svm) | |
2669 | { | |
2670 | int reg, cr; | |
2671 | unsigned long val; | |
2672 | int err; | |
2673 | ||
2674 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2675 | return emulate_on_interception(svm); | |
2676 | ||
2677 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
2678 | return emulate_on_interception(svm); | |
2679 | ||
2680 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2681 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
2682 | ||
2683 | err = 0; | |
2684 | if (cr >= 16) { /* mov to cr */ | |
2685 | cr -= 16; | |
2686 | val = kvm_register_read(&svm->vcpu, reg); | |
2687 | switch (cr) { | |
2688 | case 0: | |
628afd2a JR |
2689 | if (!check_selective_cr0_intercepted(svm, val)) |
2690 | err = kvm_set_cr0(&svm->vcpu, val); | |
7ff76d58 AP |
2691 | break; |
2692 | case 3: | |
2693 | err = kvm_set_cr3(&svm->vcpu, val); | |
2694 | break; | |
2695 | case 4: | |
2696 | err = kvm_set_cr4(&svm->vcpu, val); | |
2697 | break; | |
2698 | case 8: | |
2699 | err = kvm_set_cr8(&svm->vcpu, val); | |
2700 | break; | |
2701 | default: | |
2702 | WARN(1, "unhandled write to CR%d", cr); | |
2703 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2704 | return 1; | |
2705 | } | |
2706 | } else { /* mov from cr */ | |
2707 | switch (cr) { | |
2708 | case 0: | |
2709 | val = kvm_read_cr0(&svm->vcpu); | |
2710 | break; | |
2711 | case 2: | |
2712 | val = svm->vcpu.arch.cr2; | |
2713 | break; | |
2714 | case 3: | |
9f8fe504 | 2715 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
2716 | break; |
2717 | case 4: | |
2718 | val = kvm_read_cr4(&svm->vcpu); | |
2719 | break; | |
2720 | case 8: | |
2721 | val = kvm_get_cr8(&svm->vcpu); | |
2722 | break; | |
2723 | default: | |
2724 | WARN(1, "unhandled read from CR%d", cr); | |
2725 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2726 | return 1; | |
2727 | } | |
2728 | kvm_register_write(&svm->vcpu, reg, val); | |
2729 | } | |
2730 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2731 | ||
2732 | return 1; | |
2733 | } | |
2734 | ||
cae3797a AP |
2735 | static int dr_interception(struct vcpu_svm *svm) |
2736 | { | |
2737 | int reg, dr; | |
2738 | unsigned long val; | |
2739 | int err; | |
2740 | ||
2741 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2742 | return emulate_on_interception(svm); | |
2743 | ||
2744 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2745 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
2746 | ||
2747 | if (dr >= 16) { /* mov to DRn */ | |
2748 | val = kvm_register_read(&svm->vcpu, reg); | |
2749 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
2750 | } else { | |
2751 | err = kvm_get_dr(&svm->vcpu, dr, &val); | |
2752 | if (!err) | |
2753 | kvm_register_write(&svm->vcpu, reg, val); | |
2754 | } | |
2755 | ||
2c46d2ae JR |
2756 | skip_emulated_instruction(&svm->vcpu); |
2757 | ||
cae3797a AP |
2758 | return 1; |
2759 | } | |
2760 | ||
851ba692 | 2761 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2762 | { |
851ba692 | 2763 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 2764 | int r; |
851ba692 | 2765 | |
0a5fff19 GN |
2766 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2767 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 2768 | r = cr_interception(svm); |
95ba8273 | 2769 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
4ee546b4 | 2770 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
7ff76d58 | 2771 | return r; |
95ba8273 | 2772 | } |
0a5fff19 | 2773 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 2774 | return r; |
1d075434 JR |
2775 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2776 | return 0; | |
2777 | } | |
2778 | ||
6aa8b732 AK |
2779 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
2780 | { | |
a2fa3e9f GH |
2781 | struct vcpu_svm *svm = to_svm(vcpu); |
2782 | ||
6aa8b732 | 2783 | switch (ecx) { |
af24a4e4 | 2784 | case MSR_IA32_TSC: { |
4cc70310 | 2785 | struct vmcb *vmcb = get_host_vmcb(svm); |
6aa8b732 | 2786 | |
4cc70310 | 2787 | *data = vmcb->control.tsc_offset + native_read_tsc(); |
6aa8b732 AK |
2788 | break; |
2789 | } | |
8c06585d | 2790 | case MSR_STAR: |
a2fa3e9f | 2791 | *data = svm->vmcb->save.star; |
6aa8b732 | 2792 | break; |
0e859cac | 2793 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2794 | case MSR_LSTAR: |
a2fa3e9f | 2795 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
2796 | break; |
2797 | case MSR_CSTAR: | |
a2fa3e9f | 2798 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
2799 | break; |
2800 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2801 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
2802 | break; |
2803 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2804 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
2805 | break; |
2806 | #endif | |
2807 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2808 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
2809 | break; |
2810 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2811 | *data = svm->sysenter_eip; |
6aa8b732 AK |
2812 | break; |
2813 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2814 | *data = svm->sysenter_esp; |
6aa8b732 | 2815 | break; |
e0231715 JR |
2816 | /* |
2817 | * Nobody will change the following 5 values in the VMCB so we can | |
2818 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
2819 | * implemented. | |
2820 | */ | |
a2938c80 JR |
2821 | case MSR_IA32_DEBUGCTLMSR: |
2822 | *data = svm->vmcb->save.dbgctl; | |
2823 | break; | |
2824 | case MSR_IA32_LASTBRANCHFROMIP: | |
2825 | *data = svm->vmcb->save.br_from; | |
2826 | break; | |
2827 | case MSR_IA32_LASTBRANCHTOIP: | |
2828 | *data = svm->vmcb->save.br_to; | |
2829 | break; | |
2830 | case MSR_IA32_LASTINTFROMIP: | |
2831 | *data = svm->vmcb->save.last_excp_from; | |
2832 | break; | |
2833 | case MSR_IA32_LASTINTTOIP: | |
2834 | *data = svm->vmcb->save.last_excp_to; | |
2835 | break; | |
b286d5d8 | 2836 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2837 | *data = svm->nested.hsave_msr; |
b286d5d8 | 2838 | break; |
eb6f302e | 2839 | case MSR_VM_CR: |
4a810181 | 2840 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 2841 | break; |
c8a73f18 AG |
2842 | case MSR_IA32_UCODE_REV: |
2843 | *data = 0x01000065; | |
2844 | break; | |
6aa8b732 | 2845 | default: |
3bab1f5d | 2846 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2847 | } |
2848 | return 0; | |
2849 | } | |
2850 | ||
851ba692 | 2851 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2852 | { |
ad312c7c | 2853 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2854 | u64 data; |
2855 | ||
59200273 AK |
2856 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
2857 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 2858 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 2859 | } else { |
229456fc | 2860 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 2861 | |
5fdbf976 | 2862 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 2863 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 2864 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2865 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2866 | } |
2867 | return 1; | |
2868 | } | |
2869 | ||
4a810181 JR |
2870 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
2871 | { | |
2872 | struct vcpu_svm *svm = to_svm(vcpu); | |
2873 | int svm_dis, chg_mask; | |
2874 | ||
2875 | if (data & ~SVM_VM_CR_VALID_MASK) | |
2876 | return 1; | |
2877 | ||
2878 | chg_mask = SVM_VM_CR_VALID_MASK; | |
2879 | ||
2880 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
2881 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
2882 | ||
2883 | svm->nested.vm_cr_msr &= ~chg_mask; | |
2884 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
2885 | ||
2886 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
2887 | ||
2888 | /* check for svm_disable while efer.svme is set */ | |
2889 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
2890 | return 1; | |
2891 | ||
2892 | return 0; | |
2893 | } | |
2894 | ||
6aa8b732 AK |
2895 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) |
2896 | { | |
a2fa3e9f GH |
2897 | struct vcpu_svm *svm = to_svm(vcpu); |
2898 | ||
6aa8b732 | 2899 | switch (ecx) { |
f4e1b3c8 | 2900 | case MSR_IA32_TSC: |
99e3e30a | 2901 | kvm_write_tsc(vcpu, data); |
6aa8b732 | 2902 | break; |
8c06585d | 2903 | case MSR_STAR: |
a2fa3e9f | 2904 | svm->vmcb->save.star = data; |
6aa8b732 | 2905 | break; |
49b14f24 | 2906 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2907 | case MSR_LSTAR: |
a2fa3e9f | 2908 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
2909 | break; |
2910 | case MSR_CSTAR: | |
a2fa3e9f | 2911 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
2912 | break; |
2913 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2914 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
2915 | break; |
2916 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2917 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
2918 | break; |
2919 | #endif | |
2920 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2921 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
2922 | break; |
2923 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2924 | svm->sysenter_eip = data; |
a2fa3e9f | 2925 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
2926 | break; |
2927 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2928 | svm->sysenter_esp = data; |
a2fa3e9f | 2929 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 2930 | break; |
a2938c80 | 2931 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 2932 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
24e09cbf | 2933 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
b8688d51 | 2934 | __func__, data); |
24e09cbf JR |
2935 | break; |
2936 | } | |
2937 | if (data & DEBUGCTL_RESERVED_BITS) | |
2938 | return 1; | |
2939 | ||
2940 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 2941 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
2942 | if (data & (1ULL<<0)) |
2943 | svm_enable_lbrv(svm); | |
2944 | else | |
2945 | svm_disable_lbrv(svm); | |
a2938c80 | 2946 | break; |
b286d5d8 | 2947 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2948 | svm->nested.hsave_msr = data; |
62b9abaa | 2949 | break; |
3c5d0a44 | 2950 | case MSR_VM_CR: |
4a810181 | 2951 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 2952 | case MSR_VM_IGNNE: |
3c5d0a44 AG |
2953 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
2954 | break; | |
6aa8b732 | 2955 | default: |
3bab1f5d | 2956 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2957 | } |
2958 | return 0; | |
2959 | } | |
2960 | ||
851ba692 | 2961 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2962 | { |
ad312c7c | 2963 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 2964 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 2965 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 2966 | |
af9ca2d7 | 2967 | |
5fdbf976 | 2968 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
59200273 AK |
2969 | if (svm_set_msr(&svm->vcpu, ecx, data)) { |
2970 | trace_kvm_msr_write_ex(ecx, data); | |
c1a5d4f9 | 2971 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
2972 | } else { |
2973 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 2974 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 2975 | } |
6aa8b732 AK |
2976 | return 1; |
2977 | } | |
2978 | ||
851ba692 | 2979 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2980 | { |
e756fc62 | 2981 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 2982 | return wrmsr_interception(svm); |
6aa8b732 | 2983 | else |
851ba692 | 2984 | return rdmsr_interception(svm); |
6aa8b732 AK |
2985 | } |
2986 | ||
851ba692 | 2987 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 2988 | { |
851ba692 AK |
2989 | struct kvm_run *kvm_run = svm->vcpu.run; |
2990 | ||
3842d135 | 2991 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 2992 | svm_clear_vintr(svm); |
85f455f7 | 2993 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 2994 | mark_dirty(svm->vmcb, VMCB_INTR); |
c1150d8c DL |
2995 | /* |
2996 | * If the user space waits to inject interrupts, exit as soon as | |
2997 | * possible | |
2998 | */ | |
8061823a GN |
2999 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
3000 | kvm_run->request_interrupt_window && | |
3001 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 3002 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3003 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
3004 | return 0; | |
3005 | } | |
3006 | ||
3007 | return 1; | |
3008 | } | |
3009 | ||
565d0998 ML |
3010 | static int pause_interception(struct vcpu_svm *svm) |
3011 | { | |
3012 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3013 | return 1; | |
3014 | } | |
3015 | ||
851ba692 | 3016 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
3017 | [SVM_EXIT_READ_CR0] = cr_interception, |
3018 | [SVM_EXIT_READ_CR3] = cr_interception, | |
3019 | [SVM_EXIT_READ_CR4] = cr_interception, | |
3020 | [SVM_EXIT_READ_CR8] = cr_interception, | |
d225157b | 3021 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
628afd2a | 3022 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
3023 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
3024 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 3025 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
3026 | [SVM_EXIT_READ_DR0] = dr_interception, |
3027 | [SVM_EXIT_READ_DR1] = dr_interception, | |
3028 | [SVM_EXIT_READ_DR2] = dr_interception, | |
3029 | [SVM_EXIT_READ_DR3] = dr_interception, | |
3030 | [SVM_EXIT_READ_DR4] = dr_interception, | |
3031 | [SVM_EXIT_READ_DR5] = dr_interception, | |
3032 | [SVM_EXIT_READ_DR6] = dr_interception, | |
3033 | [SVM_EXIT_READ_DR7] = dr_interception, | |
3034 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
3035 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
3036 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
3037 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
3038 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
3039 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
3040 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
3041 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
3042 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
3043 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 3044 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
3045 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
3046 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
3047 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
3048 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 3049 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
3050 | [SVM_EXIT_SMI] = nop_on_interception, |
3051 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 3052 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 | 3053 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 3054 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 3055 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 3056 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 3057 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 3058 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 3059 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 3060 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
3061 | [SVM_EXIT_MSR] = msr_interception, |
3062 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 3063 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 3064 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 3065 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
3066 | [SVM_EXIT_VMLOAD] = vmload_interception, |
3067 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
3068 | [SVM_EXIT_STGI] = stgi_interception, |
3069 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 3070 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 3071 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
3072 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
3073 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
81dd35d4 | 3074 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 3075 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
3076 | }; |
3077 | ||
3f10c846 JR |
3078 | void dump_vmcb(struct kvm_vcpu *vcpu) |
3079 | { | |
3080 | struct vcpu_svm *svm = to_svm(vcpu); | |
3081 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3082 | struct vmcb_save_area *save = &svm->vmcb->save; | |
3083 | ||
3084 | pr_err("VMCB Control Area:\n"); | |
4ee546b4 RJ |
3085 | pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff); |
3086 | pr_err("cr_write: %04x\n", control->intercept_cr >> 16); | |
3aed041a JR |
3087 | pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff); |
3088 | pr_err("dr_write: %04x\n", control->intercept_dr >> 16); | |
3f10c846 JR |
3089 | pr_err("exceptions: %08x\n", control->intercept_exceptions); |
3090 | pr_err("intercepts: %016llx\n", control->intercept); | |
3091 | pr_err("pause filter count: %d\n", control->pause_filter_count); | |
3092 | pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa); | |
3093 | pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa); | |
3094 | pr_err("tsc_offset: %016llx\n", control->tsc_offset); | |
3095 | pr_err("asid: %d\n", control->asid); | |
3096 | pr_err("tlb_ctl: %d\n", control->tlb_ctl); | |
3097 | pr_err("int_ctl: %08x\n", control->int_ctl); | |
3098 | pr_err("int_vector: %08x\n", control->int_vector); | |
3099 | pr_err("int_state: %08x\n", control->int_state); | |
3100 | pr_err("exit_code: %08x\n", control->exit_code); | |
3101 | pr_err("exit_info1: %016llx\n", control->exit_info_1); | |
3102 | pr_err("exit_info2: %016llx\n", control->exit_info_2); | |
3103 | pr_err("exit_int_info: %08x\n", control->exit_int_info); | |
3104 | pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err); | |
3105 | pr_err("nested_ctl: %lld\n", control->nested_ctl); | |
3106 | pr_err("nested_cr3: %016llx\n", control->nested_cr3); | |
3107 | pr_err("event_inj: %08x\n", control->event_inj); | |
3108 | pr_err("event_inj_err: %08x\n", control->event_inj_err); | |
3109 | pr_err("lbr_ctl: %lld\n", control->lbr_ctl); | |
3110 | pr_err("next_rip: %016llx\n", control->next_rip); | |
3111 | pr_err("VMCB State Save Area:\n"); | |
3112 | pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n", | |
3113 | save->es.selector, save->es.attrib, | |
3114 | save->es.limit, save->es.base); | |
3115 | pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n", | |
3116 | save->cs.selector, save->cs.attrib, | |
3117 | save->cs.limit, save->cs.base); | |
3118 | pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n", | |
3119 | save->ss.selector, save->ss.attrib, | |
3120 | save->ss.limit, save->ss.base); | |
3121 | pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n", | |
3122 | save->ds.selector, save->ds.attrib, | |
3123 | save->ds.limit, save->ds.base); | |
3124 | pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n", | |
3125 | save->fs.selector, save->fs.attrib, | |
3126 | save->fs.limit, save->fs.base); | |
3127 | pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n", | |
3128 | save->gs.selector, save->gs.attrib, | |
3129 | save->gs.limit, save->gs.base); | |
3130 | pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3131 | save->gdtr.selector, save->gdtr.attrib, | |
3132 | save->gdtr.limit, save->gdtr.base); | |
3133 | pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3134 | save->ldtr.selector, save->ldtr.attrib, | |
3135 | save->ldtr.limit, save->ldtr.base); | |
3136 | pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3137 | save->idtr.selector, save->idtr.attrib, | |
3138 | save->idtr.limit, save->idtr.base); | |
3139 | pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n", | |
3140 | save->tr.selector, save->tr.attrib, | |
3141 | save->tr.limit, save->tr.base); | |
3142 | pr_err("cpl: %d efer: %016llx\n", | |
3143 | save->cpl, save->efer); | |
3144 | pr_err("cr0: %016llx cr2: %016llx\n", | |
3145 | save->cr0, save->cr2); | |
3146 | pr_err("cr3: %016llx cr4: %016llx\n", | |
3147 | save->cr3, save->cr4); | |
3148 | pr_err("dr6: %016llx dr7: %016llx\n", | |
3149 | save->dr6, save->dr7); | |
3150 | pr_err("rip: %016llx rflags: %016llx\n", | |
3151 | save->rip, save->rflags); | |
3152 | pr_err("rsp: %016llx rax: %016llx\n", | |
3153 | save->rsp, save->rax); | |
3154 | pr_err("star: %016llx lstar: %016llx\n", | |
3155 | save->star, save->lstar); | |
3156 | pr_err("cstar: %016llx sfmask: %016llx\n", | |
3157 | save->cstar, save->sfmask); | |
3158 | pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n", | |
3159 | save->kernel_gs_base, save->sysenter_cs); | |
3160 | pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n", | |
3161 | save->sysenter_esp, save->sysenter_eip); | |
3162 | pr_err("gpat: %016llx dbgctl: %016llx\n", | |
3163 | save->g_pat, save->dbgctl); | |
3164 | pr_err("br_from: %016llx br_to: %016llx\n", | |
3165 | save->br_from, save->br_to); | |
3166 | pr_err("excp_from: %016llx excp_to: %016llx\n", | |
3167 | save->last_excp_from, save->last_excp_to); | |
3168 | ||
3169 | } | |
3170 | ||
586f9607 AK |
3171 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3172 | { | |
3173 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3174 | ||
3175 | *info1 = control->exit_info_1; | |
3176 | *info2 = control->exit_info_2; | |
3177 | } | |
3178 | ||
851ba692 | 3179 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3180 | { |
04d2cc77 | 3181 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3182 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3183 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3184 | |
aa17911e | 3185 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
af9ca2d7 | 3186 | |
4ee546b4 | 3187 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3188 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3189 | if (npt_enabled) | |
3190 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3191 | |
cd3ff653 JR |
3192 | if (unlikely(svm->nested.exit_required)) { |
3193 | nested_svm_vmexit(svm); | |
3194 | svm->nested.exit_required = false; | |
3195 | ||
3196 | return 1; | |
3197 | } | |
3198 | ||
2030753d | 3199 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3200 | int vmexit; |
3201 | ||
d8cabddf JR |
3202 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3203 | svm->vmcb->control.exit_info_1, | |
3204 | svm->vmcb->control.exit_info_2, | |
3205 | svm->vmcb->control.exit_int_info, | |
3206 | svm->vmcb->control.exit_int_info_err); | |
3207 | ||
410e4d57 JR |
3208 | vmexit = nested_svm_exit_special(svm); |
3209 | ||
3210 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3211 | vmexit = nested_svm_exit_handled(svm); | |
3212 | ||
3213 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3214 | return 1; |
cf74a78b AG |
3215 | } |
3216 | ||
a5c3832d JR |
3217 | svm_complete_interrupts(svm); |
3218 | ||
04d2cc77 AK |
3219 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3220 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3221 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3222 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3223 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3224 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3225 | return 0; |
3226 | } | |
3227 | ||
a2fa3e9f | 3228 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3229 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3230 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3231 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6aa8b732 AK |
3232 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
3233 | "exit_code 0x%x\n", | |
b8688d51 | 3234 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3235 | exit_code); |
3236 | ||
9d8f549d | 3237 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3238 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 3239 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 3240 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
3241 | return 0; |
3242 | } | |
3243 | ||
851ba692 | 3244 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3245 | } |
3246 | ||
3247 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3248 | { | |
3249 | int cpu = raw_smp_processor_id(); | |
3250 | ||
0fe1e009 TH |
3251 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3252 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3253 | load_TR_desc(); |
3254 | } | |
3255 | ||
e756fc62 | 3256 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3257 | { |
3258 | int cpu = raw_smp_processor_id(); | |
3259 | ||
0fe1e009 | 3260 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3261 | |
4b656b12 | 3262 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3263 | if (svm->asid_generation != sd->asid_generation) |
3264 | new_asid(svm, sd); | |
6aa8b732 AK |
3265 | } |
3266 | ||
95ba8273 GN |
3267 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3268 | { | |
3269 | struct vcpu_svm *svm = to_svm(vcpu); | |
3270 | ||
3271 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3272 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3273 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
3274 | ++vcpu->stat.nmi_injections; |
3275 | } | |
6aa8b732 | 3276 | |
85f455f7 | 3277 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3278 | { |
3279 | struct vmcb_control_area *control; | |
3280 | ||
e756fc62 | 3281 | control = &svm->vmcb->control; |
85f455f7 | 3282 | control->int_vector = irq; |
6aa8b732 AK |
3283 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3284 | control->int_ctl |= V_IRQ_MASK | | |
3285 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 3286 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
3287 | } |
3288 | ||
66fd3f7f | 3289 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3290 | { |
3291 | struct vcpu_svm *svm = to_svm(vcpu); | |
3292 | ||
2af9194d | 3293 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3294 | |
9fb2d2b4 GN |
3295 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3296 | ++vcpu->stat.irq_injections; | |
3297 | ||
219b65dc AG |
3298 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3299 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3300 | } |
3301 | ||
95ba8273 | 3302 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3303 | { |
3304 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3305 | |
2030753d | 3306 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3307 | return; |
3308 | ||
95ba8273 | 3309 | if (irr == -1) |
aaacfc9a JR |
3310 | return; |
3311 | ||
95ba8273 | 3312 | if (tpr >= irr) |
4ee546b4 | 3313 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3314 | } |
aaacfc9a | 3315 | |
95ba8273 GN |
3316 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3317 | { | |
3318 | struct vcpu_svm *svm = to_svm(vcpu); | |
3319 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3320 | int ret; |
3321 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3322 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3323 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3324 | ||
3325 | return ret; | |
aaacfc9a JR |
3326 | } |
3327 | ||
3cfc3092 JK |
3328 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3329 | { | |
3330 | struct vcpu_svm *svm = to_svm(vcpu); | |
3331 | ||
3332 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3333 | } | |
3334 | ||
3335 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3336 | { | |
3337 | struct vcpu_svm *svm = to_svm(vcpu); | |
3338 | ||
3339 | if (masked) { | |
3340 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3341 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3342 | } else { |
3343 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 3344 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3345 | } |
3346 | } | |
3347 | ||
78646121 GN |
3348 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3349 | { | |
3350 | struct vcpu_svm *svm = to_svm(vcpu); | |
3351 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3352 | int ret; |
3353 | ||
3354 | if (!gif_set(svm) || | |
3355 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3356 | return 0; | |
3357 | ||
f6e78475 | 3358 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 3359 | |
2030753d | 3360 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3361 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3362 | ||
3363 | return ret; | |
78646121 GN |
3364 | } |
3365 | ||
9222be18 | 3366 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3367 | { |
219b65dc | 3368 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3369 | |
e0231715 JR |
3370 | /* |
3371 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3372 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3373 | * get that intercept, this function will be called again though and | |
3374 | * we'll get the vintr intercept. | |
3375 | */ | |
8fe54654 | 3376 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3377 | svm_set_vintr(svm); |
3378 | svm_inject_irq(svm, 0x0); | |
3379 | } | |
85f455f7 ED |
3380 | } |
3381 | ||
95ba8273 | 3382 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3383 | { |
04d2cc77 | 3384 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3385 | |
44c11430 GN |
3386 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3387 | == HF_NMI_MASK) | |
3388 | return; /* IRET will cause a vm exit */ | |
3389 | ||
e0231715 JR |
3390 | /* |
3391 | * Something prevents NMI from been injected. Single step over possible | |
3392 | * problem (IRET or exception injection or interrupt shadow) | |
3393 | */ | |
6be7d306 | 3394 | svm->nmi_singlestep = true; |
44c11430 GN |
3395 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
3396 | update_db_intercept(vcpu); | |
c1150d8c DL |
3397 | } |
3398 | ||
cbc94022 IE |
3399 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3400 | { | |
3401 | return 0; | |
3402 | } | |
3403 | ||
d9e368d6 AK |
3404 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3405 | { | |
38e5e92f JR |
3406 | struct vcpu_svm *svm = to_svm(vcpu); |
3407 | ||
3408 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
3409 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
3410 | else | |
3411 | svm->asid_generation--; | |
d9e368d6 AK |
3412 | } |
3413 | ||
04d2cc77 AK |
3414 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3415 | { | |
3416 | } | |
3417 | ||
d7bf8221 JR |
3418 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3419 | { | |
3420 | struct vcpu_svm *svm = to_svm(vcpu); | |
3421 | ||
2030753d | 3422 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3423 | return; |
3424 | ||
4ee546b4 | 3425 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3426 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3427 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3428 | } |
3429 | } | |
3430 | ||
649d6864 JR |
3431 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3432 | { | |
3433 | struct vcpu_svm *svm = to_svm(vcpu); | |
3434 | u64 cr8; | |
3435 | ||
2030753d | 3436 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3437 | return; |
3438 | ||
649d6864 JR |
3439 | cr8 = kvm_get_cr8(vcpu); |
3440 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3441 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3442 | } | |
3443 | ||
9222be18 GN |
3444 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3445 | { | |
3446 | u8 vector; | |
3447 | int type; | |
3448 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3449 | unsigned int3_injected = svm->int3_injected; |
3450 | ||
3451 | svm->int3_injected = 0; | |
9222be18 | 3452 | |
bd3d1ec3 AK |
3453 | /* |
3454 | * If we've made progress since setting HF_IRET_MASK, we've | |
3455 | * executed an IRET and can allow NMI injection. | |
3456 | */ | |
3457 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
3458 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 3459 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3460 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3461 | } | |
44c11430 | 3462 | |
9222be18 GN |
3463 | svm->vcpu.arch.nmi_injected = false; |
3464 | kvm_clear_exception_queue(&svm->vcpu); | |
3465 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3466 | ||
3467 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3468 | return; | |
3469 | ||
3842d135 AK |
3470 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3471 | ||
9222be18 GN |
3472 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3473 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3474 | ||
3475 | switch (type) { | |
3476 | case SVM_EXITINTINFO_TYPE_NMI: | |
3477 | svm->vcpu.arch.nmi_injected = true; | |
3478 | break; | |
3479 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3480 | /* |
3481 | * In case of software exceptions, do not reinject the vector, | |
3482 | * but re-execute the instruction instead. Rewind RIP first | |
3483 | * if we emulated INT3 before. | |
3484 | */ | |
3485 | if (kvm_exception_is_soft(vector)) { | |
3486 | if (vector == BP_VECTOR && int3_injected && | |
3487 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3488 | kvm_rip_write(&svm->vcpu, | |
3489 | kvm_rip_read(&svm->vcpu) - | |
3490 | int3_injected); | |
9222be18 | 3491 | break; |
66b7138f | 3492 | } |
9222be18 GN |
3493 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3494 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3495 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3496 | |
3497 | } else | |
ce7ddec4 | 3498 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3499 | break; |
3500 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3501 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3502 | break; |
3503 | default: | |
3504 | break; | |
3505 | } | |
3506 | } | |
3507 | ||
b463a6f7 AK |
3508 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3509 | { | |
3510 | struct vcpu_svm *svm = to_svm(vcpu); | |
3511 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3512 | ||
3513 | control->exit_int_info = control->event_inj; | |
3514 | control->exit_int_info_err = control->event_inj_err; | |
3515 | control->event_inj = 0; | |
3516 | svm_complete_interrupts(svm); | |
3517 | } | |
3518 | ||
80e31d4f AK |
3519 | #ifdef CONFIG_X86_64 |
3520 | #define R "r" | |
3521 | #else | |
3522 | #define R "e" | |
3523 | #endif | |
3524 | ||
851ba692 | 3525 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3526 | { |
a2fa3e9f | 3527 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3528 | |
2041a06a JR |
3529 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3530 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3531 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3532 | ||
cd3ff653 JR |
3533 | /* |
3534 | * A vmexit emulation is required before the vcpu can be executed | |
3535 | * again. | |
3536 | */ | |
3537 | if (unlikely(svm->nested.exit_required)) | |
3538 | return; | |
3539 | ||
e756fc62 | 3540 | pre_svm_run(svm); |
6aa8b732 | 3541 | |
649d6864 JR |
3542 | sync_lapic_to_cr8(vcpu); |
3543 | ||
cda0ffdd | 3544 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3545 | |
04d2cc77 AK |
3546 | clgi(); |
3547 | ||
3548 | local_irq_enable(); | |
36241b8c | 3549 | |
6aa8b732 | 3550 | asm volatile ( |
80e31d4f AK |
3551 | "push %%"R"bp; \n\t" |
3552 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
3553 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
3554 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
3555 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
3556 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
3557 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 3558 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3559 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3560 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3561 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3562 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3563 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3564 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3565 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3566 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3567 | #endif |
3568 | ||
6aa8b732 | 3569 | /* Enter guest mode */ |
80e31d4f AK |
3570 | "push %%"R"ax \n\t" |
3571 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
3572 | __ex(SVM_VMLOAD) "\n\t" |
3573 | __ex(SVM_VMRUN) "\n\t" | |
3574 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 3575 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
3576 | |
3577 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
3578 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
3579 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
3580 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
3581 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
3582 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
3583 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3584 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3585 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3586 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3587 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3588 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3589 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3590 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3591 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3592 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3593 | #endif |
80e31d4f | 3594 | "pop %%"R"bp" |
6aa8b732 | 3595 | : |
fb3f0f51 | 3596 | : [svm]"a"(svm), |
6aa8b732 | 3597 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3598 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3599 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3600 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3601 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3602 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3603 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3604 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3605 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3606 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3607 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3608 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3609 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3610 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3611 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3612 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3613 | #endif |
54a08c04 | 3614 | : "cc", "memory" |
80e31d4f | 3615 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 3616 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
3617 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
3618 | #endif | |
3619 | ); | |
6aa8b732 | 3620 | |
82ca2d10 AK |
3621 | #ifdef CONFIG_X86_64 |
3622 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3623 | #else | |
dacccfdd | 3624 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
3625 | #ifndef CONFIG_X86_32_LAZY_GS |
3626 | loadsegment(gs, svm->host.gs); | |
3627 | #endif | |
9581d442 | 3628 | #endif |
6aa8b732 AK |
3629 | |
3630 | reload_tss(vcpu); | |
3631 | ||
56ba47dd AK |
3632 | local_irq_disable(); |
3633 | ||
13c34e07 AK |
3634 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3635 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3636 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3637 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3638 | ||
3781c01c JR |
3639 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
3640 | kvm_before_handle_nmi(&svm->vcpu); | |
3641 | ||
3642 | stgi(); | |
3643 | ||
3644 | /* Any pending NMI will happen here */ | |
3645 | ||
3646 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
3647 | kvm_after_handle_nmi(&svm->vcpu); | |
3648 | ||
d7bf8221 JR |
3649 | sync_cr8_to_lapic(vcpu); |
3650 | ||
a2fa3e9f | 3651 | svm->next_rip = 0; |
9222be18 | 3652 | |
38e5e92f JR |
3653 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
3654 | ||
631bc487 GN |
3655 | /* if exit due to PF check for async PF */ |
3656 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3657 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3658 | ||
6de4f3ad AK |
3659 | if (npt_enabled) { |
3660 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3661 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3662 | } | |
fe5913e4 JR |
3663 | |
3664 | /* | |
3665 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3666 | * change the physical cpu | |
3667 | */ | |
3668 | if (unlikely(svm->vmcb->control.exit_code == | |
3669 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3670 | svm_handle_mce(svm); | |
8d28fec4 RJ |
3671 | |
3672 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
3673 | } |
3674 | ||
80e31d4f AK |
3675 | #undef R |
3676 | ||
6aa8b732 AK |
3677 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3678 | { | |
a2fa3e9f GH |
3679 | struct vcpu_svm *svm = to_svm(vcpu); |
3680 | ||
3681 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 3682 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 3683 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
3684 | } |
3685 | ||
1c97f0a0 JR |
3686 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3687 | { | |
3688 | struct vcpu_svm *svm = to_svm(vcpu); | |
3689 | ||
3690 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 3691 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
3692 | |
3693 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 3694 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 3695 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 3696 | |
f40f6a45 | 3697 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
3698 | } |
3699 | ||
6aa8b732 AK |
3700 | static int is_disabled(void) |
3701 | { | |
6031a61c JR |
3702 | u64 vm_cr; |
3703 | ||
3704 | rdmsrl(MSR_VM_CR, vm_cr); | |
3705 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3706 | return 1; | |
3707 | ||
6aa8b732 AK |
3708 | return 0; |
3709 | } | |
3710 | ||
102d8325 IM |
3711 | static void |
3712 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3713 | { | |
3714 | /* | |
3715 | * Patch in the VMMCALL instruction: | |
3716 | */ | |
3717 | hypercall[0] = 0x0f; | |
3718 | hypercall[1] = 0x01; | |
3719 | hypercall[2] = 0xd9; | |
102d8325 IM |
3720 | } |
3721 | ||
002c7f7c YS |
3722 | static void svm_check_processor_compat(void *rtn) |
3723 | { | |
3724 | *(int *)rtn = 0; | |
3725 | } | |
3726 | ||
774ead3a AK |
3727 | static bool svm_cpu_has_accelerated_tpr(void) |
3728 | { | |
3729 | return false; | |
3730 | } | |
3731 | ||
4b12f0de | 3732 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
3733 | { |
3734 | return 0; | |
3735 | } | |
3736 | ||
0e851880 SY |
3737 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
3738 | { | |
3739 | } | |
3740 | ||
d4330ef2 JR |
3741 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
3742 | { | |
c2c63a49 | 3743 | switch (func) { |
4c62a2dc JR |
3744 | case 0x80000001: |
3745 | if (nested) | |
3746 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
3747 | break; | |
c2c63a49 JR |
3748 | case 0x8000000A: |
3749 | entry->eax = 1; /* SVM revision 1 */ | |
3750 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
3751 | ASID emulation to nested SVM */ | |
3752 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
3753 | entry->edx = 0; /* Per default do not support any |
3754 | additional features */ | |
3755 | ||
3756 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 3757 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 3758 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 3759 | |
3d4aeaad JR |
3760 | /* Support NPT for the guest if enabled */ |
3761 | if (npt_enabled) | |
3762 | entry->edx |= SVM_FEATURE_NPT; | |
3763 | ||
c2c63a49 JR |
3764 | break; |
3765 | } | |
d4330ef2 JR |
3766 | } |
3767 | ||
229456fc | 3768 | static const struct trace_print_flags svm_exit_reasons_str[] = { |
e0231715 JR |
3769 | { SVM_EXIT_READ_CR0, "read_cr0" }, |
3770 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
3771 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
3772 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
3773 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
3774 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
3775 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
3776 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
3777 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
3778 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
3779 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
3780 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
3781 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
3782 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
3783 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
3784 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
3785 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
3786 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
229456fc MT |
3787 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, |
3788 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
3789 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
3790 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
3791 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
3792 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
3793 | { SVM_EXIT_INTR, "interrupt" }, | |
3794 | { SVM_EXIT_NMI, "nmi" }, | |
3795 | { SVM_EXIT_SMI, "smi" }, | |
3796 | { SVM_EXIT_INIT, "init" }, | |
3797 | { SVM_EXIT_VINTR, "vintr" }, | |
3798 | { SVM_EXIT_CPUID, "cpuid" }, | |
3799 | { SVM_EXIT_INVD, "invd" }, | |
3800 | { SVM_EXIT_HLT, "hlt" }, | |
3801 | { SVM_EXIT_INVLPG, "invlpg" }, | |
3802 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
3803 | { SVM_EXIT_IOIO, "io" }, | |
3804 | { SVM_EXIT_MSR, "msr" }, | |
3805 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
3806 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
3807 | { SVM_EXIT_VMRUN, "vmrun" }, | |
3808 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
3809 | { SVM_EXIT_VMLOAD, "vmload" }, | |
3810 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
3811 | { SVM_EXIT_STGI, "stgi" }, | |
3812 | { SVM_EXIT_CLGI, "clgi" }, | |
3813 | { SVM_EXIT_SKINIT, "skinit" }, | |
3814 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
3815 | { SVM_EXIT_MONITOR, "monitor" }, | |
3816 | { SVM_EXIT_MWAIT, "mwait" }, | |
81dd35d4 | 3817 | { SVM_EXIT_XSETBV, "xsetbv" }, |
229456fc MT |
3818 | { SVM_EXIT_NPF, "npf" }, |
3819 | { -1, NULL } | |
3820 | }; | |
3821 | ||
17cc3935 | 3822 | static int svm_get_lpage_level(void) |
344f414f | 3823 | { |
17cc3935 | 3824 | return PT_PDPE_LEVEL; |
344f414f JR |
3825 | } |
3826 | ||
4e47c7a6 SY |
3827 | static bool svm_rdtscp_supported(void) |
3828 | { | |
3829 | return false; | |
3830 | } | |
3831 | ||
f5f48ee1 SY |
3832 | static bool svm_has_wbinvd_exit(void) |
3833 | { | |
3834 | return true; | |
3835 | } | |
3836 | ||
02daab21 AK |
3837 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
3838 | { | |
3839 | struct vcpu_svm *svm = to_svm(vcpu); | |
3840 | ||
18c918c5 | 3841 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 3842 | update_cr0_intercept(svm); |
02daab21 AK |
3843 | } |
3844 | ||
8061252e JR |
3845 | #define PRE_EX(exit) { .exit_code = (exit), \ |
3846 | .stage = X86_ICPT_PRE_EXCEPT, \ | |
3847 | .valid = true } | |
cfec82cb JR |
3848 | #define POST_EX(exit) { .exit_code = (exit), \ |
3849 | .stage = X86_ICPT_POST_EXCEPT, \ | |
3850 | .valid = true } | |
d7eb8203 JR |
3851 | #define POST_MEM(exit) { .exit_code = (exit), \ |
3852 | .stage = X86_ICPT_POST_MEMACCESS, \ | |
3853 | .valid = true } | |
cfec82cb JR |
3854 | |
3855 | static struct __x86_intercept { | |
3856 | u32 exit_code; | |
3857 | enum x86_intercept_stage stage; | |
3858 | bool valid; | |
3859 | } x86_intercept_map[] = { | |
3860 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
3861 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
3862 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
3863 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
3864 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
3865 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
3866 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
3867 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
3868 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
3869 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
3870 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
3871 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
3872 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
3873 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
3874 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
3875 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
3876 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
3877 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
3878 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
3879 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
3880 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
3881 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
3882 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
3883 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
3884 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
3885 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
3886 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
3887 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
3888 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
3889 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
3890 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
3891 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
3892 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
3893 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
3894 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
3895 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
3896 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
3897 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
3898 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
3899 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
3900 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
3901 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
3902 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
3903 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
3904 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
3905 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
3906 | }; |
3907 | ||
8061252e | 3908 | #undef PRE_EX |
cfec82cb | 3909 | #undef POST_EX |
d7eb8203 | 3910 | #undef POST_MEM |
cfec82cb | 3911 | |
8a76d7f2 JR |
3912 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
3913 | struct x86_instruction_info *info, | |
3914 | enum x86_intercept_stage stage) | |
3915 | { | |
cfec82cb JR |
3916 | struct vcpu_svm *svm = to_svm(vcpu); |
3917 | int vmexit, ret = X86EMUL_CONTINUE; | |
3918 | struct __x86_intercept icpt_info; | |
3919 | struct vmcb *vmcb = svm->vmcb; | |
3920 | ||
3921 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
3922 | goto out; | |
3923 | ||
3924 | icpt_info = x86_intercept_map[info->intercept]; | |
3925 | ||
3926 | if (!icpt_info.valid || stage != icpt_info.stage) | |
3927 | goto out; | |
3928 | ||
3929 | switch (icpt_info.exit_code) { | |
3930 | case SVM_EXIT_READ_CR0: | |
3931 | if (info->intercept == x86_intercept_cr_read) | |
3932 | icpt_info.exit_code += info->modrm_reg; | |
3933 | break; | |
3934 | case SVM_EXIT_WRITE_CR0: { | |
3935 | unsigned long cr0, val; | |
3936 | u64 intercept; | |
3937 | ||
3938 | if (info->intercept == x86_intercept_cr_write) | |
3939 | icpt_info.exit_code += info->modrm_reg; | |
3940 | ||
3941 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0) | |
3942 | break; | |
3943 | ||
3944 | intercept = svm->nested.intercept; | |
3945 | ||
3946 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
3947 | break; | |
3948 | ||
3949 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
3950 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
3951 | ||
3952 | if (info->intercept == x86_intercept_lmsw) { | |
3953 | cr0 &= 0xfUL; | |
3954 | val &= 0xfUL; | |
3955 | /* lmsw can't clear PE - catch this here */ | |
3956 | if (cr0 & X86_CR0_PE) | |
3957 | val |= X86_CR0_PE; | |
3958 | } | |
3959 | ||
3960 | if (cr0 ^ val) | |
3961 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
3962 | ||
3963 | break; | |
3964 | } | |
3b88e41a JR |
3965 | case SVM_EXIT_READ_DR0: |
3966 | case SVM_EXIT_WRITE_DR0: | |
3967 | icpt_info.exit_code += info->modrm_reg; | |
3968 | break; | |
8061252e JR |
3969 | case SVM_EXIT_MSR: |
3970 | if (info->intercept == x86_intercept_wrmsr) | |
3971 | vmcb->control.exit_info_1 = 1; | |
3972 | else | |
3973 | vmcb->control.exit_info_1 = 0; | |
3974 | break; | |
bf608f88 JR |
3975 | case SVM_EXIT_PAUSE: |
3976 | /* | |
3977 | * We get this for NOP only, but pause | |
3978 | * is rep not, check this here | |
3979 | */ | |
3980 | if (info->rep_prefix != REPE_PREFIX) | |
3981 | goto out; | |
f6511935 JR |
3982 | case SVM_EXIT_IOIO: { |
3983 | u64 exit_info; | |
3984 | u32 bytes; | |
3985 | ||
3986 | exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16; | |
3987 | ||
3988 | if (info->intercept == x86_intercept_in || | |
3989 | info->intercept == x86_intercept_ins) { | |
3990 | exit_info |= SVM_IOIO_TYPE_MASK; | |
3991 | bytes = info->src_bytes; | |
3992 | } else { | |
3993 | bytes = info->dst_bytes; | |
3994 | } | |
3995 | ||
3996 | if (info->intercept == x86_intercept_outs || | |
3997 | info->intercept == x86_intercept_ins) | |
3998 | exit_info |= SVM_IOIO_STR_MASK; | |
3999 | ||
4000 | if (info->rep_prefix) | |
4001 | exit_info |= SVM_IOIO_REP_MASK; | |
4002 | ||
4003 | bytes = min(bytes, 4u); | |
4004 | ||
4005 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
4006 | ||
4007 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
4008 | ||
4009 | vmcb->control.exit_info_1 = exit_info; | |
4010 | vmcb->control.exit_info_2 = info->next_rip; | |
4011 | ||
4012 | break; | |
4013 | } | |
cfec82cb JR |
4014 | default: |
4015 | break; | |
4016 | } | |
4017 | ||
4018 | vmcb->control.next_rip = info->next_rip; | |
4019 | vmcb->control.exit_code = icpt_info.exit_code; | |
4020 | vmexit = nested_svm_exit_handled(svm); | |
4021 | ||
4022 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
4023 | : X86EMUL_CONTINUE; | |
4024 | ||
4025 | out: | |
4026 | return ret; | |
8a76d7f2 JR |
4027 | } |
4028 | ||
cbdd1bea | 4029 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
4030 | .cpu_has_kvm_support = has_svm, |
4031 | .disabled_by_bios = is_disabled, | |
4032 | .hardware_setup = svm_hardware_setup, | |
4033 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 4034 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
4035 | .hardware_enable = svm_hardware_enable, |
4036 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 4037 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
4038 | |
4039 | .vcpu_create = svm_create_vcpu, | |
4040 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 4041 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 4042 | |
04d2cc77 | 4043 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
4044 | .vcpu_load = svm_vcpu_load, |
4045 | .vcpu_put = svm_vcpu_put, | |
4046 | ||
4047 | .set_guest_debug = svm_guest_debug, | |
4048 | .get_msr = svm_get_msr, | |
4049 | .set_msr = svm_set_msr, | |
4050 | .get_segment_base = svm_get_segment_base, | |
4051 | .get_segment = svm_get_segment, | |
4052 | .set_segment = svm_set_segment, | |
2e4d2653 | 4053 | .get_cpl = svm_get_cpl, |
1747fb71 | 4054 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 4055 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 4056 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 4057 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 4058 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
4059 | .set_cr3 = svm_set_cr3, |
4060 | .set_cr4 = svm_set_cr4, | |
4061 | .set_efer = svm_set_efer, | |
4062 | .get_idt = svm_get_idt, | |
4063 | .set_idt = svm_set_idt, | |
4064 | .get_gdt = svm_get_gdt, | |
4065 | .set_gdt = svm_set_gdt, | |
020df079 | 4066 | .set_dr7 = svm_set_dr7, |
6de4f3ad | 4067 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
4068 | .get_rflags = svm_get_rflags, |
4069 | .set_rflags = svm_set_rflags, | |
6b52d186 | 4070 | .fpu_activate = svm_fpu_activate, |
02daab21 | 4071 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 4072 | |
6aa8b732 | 4073 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 4074 | |
6aa8b732 | 4075 | .run = svm_vcpu_run, |
04d2cc77 | 4076 | .handle_exit = handle_exit, |
6aa8b732 | 4077 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4078 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
4079 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 4080 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 4081 | .set_irq = svm_set_irq, |
95ba8273 | 4082 | .set_nmi = svm_inject_nmi, |
298101da | 4083 | .queue_exception = svm_queue_exception, |
b463a6f7 | 4084 | .cancel_injection = svm_cancel_injection, |
78646121 | 4085 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 4086 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
4087 | .get_nmi_mask = svm_get_nmi_mask, |
4088 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
4089 | .enable_nmi_window = enable_nmi_window, |
4090 | .enable_irq_window = enable_irq_window, | |
4091 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
4092 | |
4093 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 4094 | .get_tdp_level = get_npt_level, |
4b12f0de | 4095 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 4096 | |
586f9607 | 4097 | .get_exit_info = svm_get_exit_info, |
229456fc | 4098 | .exit_reasons_str = svm_exit_reasons_str, |
586f9607 | 4099 | |
17cc3935 | 4100 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
4101 | |
4102 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
4103 | |
4104 | .rdtscp_supported = svm_rdtscp_supported, | |
d4330ef2 JR |
4105 | |
4106 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
4107 | |
4108 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a ZA |
4109 | |
4110 | .write_tsc_offset = svm_write_tsc_offset, | |
e48672fa | 4111 | .adjust_tsc_offset = svm_adjust_tsc_offset, |
1c97f0a0 JR |
4112 | |
4113 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
4114 | |
4115 | .check_intercept = svm_check_intercept, | |
6aa8b732 AK |
4116 | }; |
4117 | ||
4118 | static int __init svm_init(void) | |
4119 | { | |
cb498ea2 | 4120 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 4121 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
4122 | } |
4123 | ||
4124 | static void __exit svm_exit(void) | |
4125 | { | |
cb498ea2 | 4126 | kvm_exit(); |
6aa8b732 AK |
4127 | } |
4128 | ||
4129 | module_init(svm_init) | |
4130 | module_exit(svm_exit) |