]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/x86/kvm/vmx.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: SVM: Implement Flush-By-Asid feature
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
cdc0e244
AK		 72#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74#define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 77 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 78#define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 80#define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
82 | X86_CR4_OSXMMEXCPT)
83
cdc0e244
AK		 84#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
86
78ac8b47
AK		 87#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
88
4b8d54f9
ZE		 89/*
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
99 */
100#define KVM_VMX_DEFAULT_PLE_GAP 41
101#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103module_param(ple_gap, int, S_IRUGO);
104
105static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106module_param(ple_window, int, S_IRUGO);
107
61d2ef2c
AK		 108#define NR_AUTOLOAD_MSRS 1
109
a2fa3e9f
GH		 110struct vmcs {
111 u32 revision_id;
112 u32 abort;
113 char data[0];
114};
115
26bb0981
AK		 116struct shared_msr_entry {
117 unsigned index;
118 u64 data;
d5696725 119 u64 mask;
26bb0981
AK		 120};
121
a2fa3e9f 122struct vcpu_vmx {
fb3f0f51 123 struct kvm_vcpu vcpu;
543e4243 124 struct list_head local_vcpus_link;
313dbd49 125 unsigned long host_rsp;
a2fa3e9f 126 int launched;
29bd8a78 127 u8 fail;
51aa01d1 128 u32 exit_intr_info;
1155f76a 129 u32 idt_vectoring_info;
26bb0981 130 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 131 int nmsrs;
132 int save_nmsrs;
a2fa3e9f 133#ifdef CONFIG_X86_64
44ea2b17
AK		 134 u64 msr_host_kernel_gs_base;
135 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 136#endif
137 struct vmcs *vmcs;
61d2ef2c
AK		 138 struct msr_autoload {
139 unsigned nr;
140 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
141 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
142 } msr_autoload;
a2fa3e9f
GH		 143 struct {
144 int loaded;
145 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 146 int gs_ldt_reload_needed;
147 int fs_reload_needed;
d77c26fc 148 } host_state;
9c8cba37 149 struct {
7ffd92c5 150 int vm86_active;
78ac8b47 151 ulong save_rflags;
7ffd92c5
AK		 152 struct kvm_save_segment {
153 u16 selector;
154 unsigned long base;
155 u32 limit;
156 u32 ar;
157 } tr, es, ds, fs, gs;
9c8cba37 158 } rmode;
2384d2b3 159 int vpid;
04fa4d32 160 bool emulation_required;
3b86cd99
JK		 161
162 /* Support for vnmi-less CPUs */
163 int soft_vnmi_blocked;
164 ktime_t entry_time;
165 s64 vnmi_blocked_time;
a0861c02 166 u32 exit_reason;
4e47c7a6
SY		 167
168 bool rdtscp_enabled;
a2fa3e9f
GH		 169};
170
171static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
172{
fb3f0f51 173 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 174}
175
b7ebfb05 176static int init_rmode(struct kvm *kvm);
4e1096d2 177static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 178static void kvm_cpu_vmxon(u64 addr);
179static void kvm_cpu_vmxoff(void);
75880a01 180
6aa8b732
AK		 181static DEFINE_PER_CPU(struct vmcs *, vmxarea);
182static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 183static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
3444d7da 184static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 185
3e7c73e9
AK		 186static unsigned long *vmx_io_bitmap_a;
187static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 188static unsigned long *vmx_msr_bitmap_legacy;
189static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 190
2384d2b3
SY		 191static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
192static DEFINE_SPINLOCK(vmx_vpid_lock);
193
1c3d14fe 194static struct vmcs_config {
6aa8b732
AK		 195 int size;
196 int order;
197 u32 revision_id;
1c3d14fe
YS		 198 u32 pin_based_exec_ctrl;
199 u32 cpu_based_exec_ctrl;
f78e0e2e 200 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 201 u32 vmexit_ctrl;
202 u32 vmentry_ctrl;
203} vmcs_config;
6aa8b732 204
efff9e53 205static struct vmx_capability {
d56f546d
SY		 206 u32 ept;
207 u32 vpid;
208} vmx_capability;
209
6aa8b732
AK		 210#define VMX_SEGMENT_FIELD(seg) \
211 [VCPU_SREG_##seg] = { \
212 .selector = GUEST_##seg##_SELECTOR, \
213 .base = GUEST_##seg##_BASE, \
214 .limit = GUEST_##seg##_LIMIT, \
215 .ar_bytes = GUEST_##seg##_AR_BYTES, \
216 }
217
218static struct kvm_vmx_segment_field {
219 unsigned selector;
220 unsigned base;
221 unsigned limit;
222 unsigned ar_bytes;
223} kvm_vmx_segment_fields[] = {
224 VMX_SEGMENT_FIELD(CS),
225 VMX_SEGMENT_FIELD(DS),
226 VMX_SEGMENT_FIELD(ES),
227 VMX_SEGMENT_FIELD(FS),
228 VMX_SEGMENT_FIELD(GS),
229 VMX_SEGMENT_FIELD(SS),
230 VMX_SEGMENT_FIELD(TR),
231 VMX_SEGMENT_FIELD(LDTR),
232};
233
26bb0981
AK		 234static u64 host_efer;
235
6de4f3ad
AK		 236static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
237
4d56c8a7 238/*
8c06585d 239 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 240 * away by decrementing the array size.
241 */
6aa8b732 242static const u32 vmx_msr_index[] = {
05b3e0c2 243#ifdef CONFIG_X86_64
44ea2b17 244 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 245#endif
8c06585d 246 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 247};
9d8f549d 248#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 249
31299944 250static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 251{
252 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
253 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 254 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 255}
256
31299944 257static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 258{
259 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
260 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 261 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 262}
263
31299944 264static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 265{
266 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
267 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 268 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 269}
270
31299944 271static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 272{
273 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
274 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
275}
276
31299944 277static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 278{
279 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
280 INTR_INFO_VALID_MASK)) ==
281 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
282}
283
31299944 284static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 285{
04547156 286 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 287}
288
31299944 289static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 290{
04547156 291 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 292}
293
31299944 294static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 295{
04547156 296 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 297}
298
31299944 299static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 300{
04547156
SY		 301 return vmcs_config.cpu_based_exec_ctrl &
302 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 303}
304
774ead3a 305static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 306{
04547156
SY		 307 return vmcs_config.cpu_based_2nd_exec_ctrl &
308 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
309}
310
311static inline bool cpu_has_vmx_flexpriority(void)
312{
313 return cpu_has_vmx_tpr_shadow() &&
314 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 315}
316
e799794e
MT		 317static inline bool cpu_has_vmx_ept_execute_only(void)
318{
31299944 319 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 320}
321
322static inline bool cpu_has_vmx_eptp_uncacheable(void)
323{
31299944 324 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 325}
326
327static inline bool cpu_has_vmx_eptp_writeback(void)
328{
31299944 329 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 330}
331
332static inline bool cpu_has_vmx_ept_2m_page(void)
333{
31299944 334 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 335}
336
878403b7
SY		 337static inline bool cpu_has_vmx_ept_1g_page(void)
338{
31299944 339 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 340}
341
4bc9b982
SY		 342static inline bool cpu_has_vmx_ept_4levels(void)
343{
344 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
345}
346
31299944 347static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 348{
31299944 349 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 350}
351
31299944 352static inline bool cpu_has_vmx_invept_context(void)
d56f546d 353{
31299944 354 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 355}
356
31299944 357static inline bool cpu_has_vmx_invept_global(void)
d56f546d 358{
31299944 359 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 360}
361
518c8aee
GJ		 362static inline bool cpu_has_vmx_invvpid_single(void)
363{
364 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
365}
366
b9d762fa
GJ		 367static inline bool cpu_has_vmx_invvpid_global(void)
368{
369 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
370}
371
31299944 372static inline bool cpu_has_vmx_ept(void)
d56f546d 373{
04547156
SY		 374 return vmcs_config.cpu_based_2nd_exec_ctrl &
375 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 376}
377
31299944 378static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 379{
380 return vmcs_config.cpu_based_2nd_exec_ctrl &
381 SECONDARY_EXEC_UNRESTRICTED_GUEST;
382}
383
31299944 384static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 385{
386 return vmcs_config.cpu_based_2nd_exec_ctrl &
387 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
388}
389
31299944 390static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 391{
6d3e435e 392 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 393}
394
31299944 395static inline bool cpu_has_vmx_vpid(void)
2384d2b3 396{
04547156
SY		 397 return vmcs_config.cpu_based_2nd_exec_ctrl &
398 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 399}
400
31299944 401static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 402{
403 return vmcs_config.cpu_based_2nd_exec_ctrl &
404 SECONDARY_EXEC_RDTSCP;
405}
406
31299944 407static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 408{
409 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
410}
411
f5f48ee1
SY		 412static inline bool cpu_has_vmx_wbinvd_exit(void)
413{
414 return vmcs_config.cpu_based_2nd_exec_ctrl &
415 SECONDARY_EXEC_WBINVD_EXITING;
416}
417
04547156
SY		 418static inline bool report_flexpriority(void)
419{
420 return flexpriority_enabled;
421}
422
8b9cf98c 423static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 424{
425 int i;
426
a2fa3e9f 427 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 428 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 429 return i;
430 return -1;
431}
432
2384d2b3
SY		 433static inline void __invvpid(int ext, u16 vpid, gva_t gva)
434{
435 struct {
436 u64 vpid : 16;
437 u64 rsvd : 48;
438 u64 gva;
439 } operand = { vpid, 0, gva };
440
4ecac3fd 441 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 442 /* CF==1 or ZF==1 --> rc = -1 */
443 "; ja 1f ; ud2 ; 1:"
444 : : "a"(&operand), "c"(ext) : "cc", "memory");
445}
446
1439442c
SY		 447static inline void __invept(int ext, u64 eptp, gpa_t gpa)
448{
449 struct {
450 u64 eptp, gpa;
451 } operand = {eptp, gpa};
452
4ecac3fd 453 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 454 /* CF==1 or ZF==1 --> rc = -1 */
455 "; ja 1f ; ud2 ; 1:\n"
456 : : "a" (&operand), "c" (ext) : "cc", "memory");
457}
458
26bb0981 459static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 460{
461 int i;
462
8b9cf98c 463 i = __find_msr_index(vmx, msr);
a75beee6 464 if (i >= 0)
a2fa3e9f 465 return &vmx->guest_msrs[i];
8b6d44c7 466 return NULL;
7725f0ba
AK		 467}
468
6aa8b732
AK		 469static void vmcs_clear(struct vmcs *vmcs)
470{
471 u64 phys_addr = __pa(vmcs);
472 u8 error;
473
4ecac3fd 474 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 475 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
476 : "cc", "memory");
477 if (error)
478 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
479 vmcs, phys_addr);
480}
481
7725b894
DX		 482static void vmcs_load(struct vmcs *vmcs)
483{
484 u64 phys_addr = __pa(vmcs);
485 u8 error;
486
487 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
488 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
489 : "cc", "memory");
490 if (error)
491 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
492 vmcs, phys_addr);
493}
494
6aa8b732
AK		 495static void __vcpu_clear(void *arg)
496{
8b9cf98c 497 struct vcpu_vmx *vmx = arg;
d3b2c338 498 int cpu = raw_smp_processor_id();
6aa8b732 499
8b9cf98c 500 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 501 vmcs_clear(vmx->vmcs);
502 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 503 per_cpu(current_vmcs, cpu) = NULL;
543e4243
AK		 504 list_del(&vmx->local_vcpus_link);
505 vmx->vcpu.cpu = -1;
506 vmx->launched = 0;
6aa8b732
AK		 507}
508
8b9cf98c 509static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 510{
eae5ecb5
AK		 511 if (vmx->vcpu.cpu == -1)
512 return;
8691e5a8 513 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 514}
515
1760dd49 516static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 517{
518 if (vmx->vpid == 0)
519 return;
520
518c8aee
GJ		 521 if (cpu_has_vmx_invvpid_single())
522 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 523}
524
b9d762fa
GJ		 525static inline void vpid_sync_vcpu_global(void)
526{
527 if (cpu_has_vmx_invvpid_global())
528 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
529}
530
531static inline void vpid_sync_context(struct vcpu_vmx *vmx)
532{
533 if (cpu_has_vmx_invvpid_single())
1760dd49 534 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 535 else
536 vpid_sync_vcpu_global();
537}
538
1439442c
SY		 539static inline void ept_sync_global(void)
540{
541 if (cpu_has_vmx_invept_global())
542 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
543}
544
545static inline void ept_sync_context(u64 eptp)
546{
089d034e 547 if (enable_ept) {
1439442c
SY		 548 if (cpu_has_vmx_invept_context())
549 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
550 else
551 ept_sync_global();
552 }
553}
554
555static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
556{
089d034e 557 if (enable_ept) {
1439442c
SY		 558 if (cpu_has_vmx_invept_individual_addr())
559 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
560 eptp, gpa);
561 else
562 ept_sync_context(eptp);
563 }
564}
565
6aa8b732
AK		 566static unsigned long vmcs_readl(unsigned long field)
567{
a295673a 568 unsigned long value = 0;
6aa8b732 569
4ecac3fd 570 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
a295673a 571 : "+a"(value) : "d"(field) : "cc");
6aa8b732
AK		 572 return value;
573}
574
575static u16 vmcs_read16(unsigned long field)
576{
577 return vmcs_readl(field);
578}
579
580static u32 vmcs_read32(unsigned long field)
581{
582 return vmcs_readl(field);
583}
584
585static u64 vmcs_read64(unsigned long field)
586{
05b3e0c2 587#ifdef CONFIG_X86_64
6aa8b732
AK		 588 return vmcs_readl(field);
589#else
590 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
591#endif
592}
593
e52de1b8
AK		 594static noinline void vmwrite_error(unsigned long field, unsigned long value)
595{
596 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
597 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
598 dump_stack();
599}
600
6aa8b732
AK		 601static void vmcs_writel(unsigned long field, unsigned long value)
602{
603 u8 error;
604
4ecac3fd 605 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 606 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 607 if (unlikely(error))
608 vmwrite_error(field, value);
6aa8b732
AK		 609}
610
611static void vmcs_write16(unsigned long field, u16 value)
612{
613 vmcs_writel(field, value);
614}
615
616static void vmcs_write32(unsigned long field, u32 value)
617{
618 vmcs_writel(field, value);
619}
620
621static void vmcs_write64(unsigned long field, u64 value)
622{
6aa8b732 623 vmcs_writel(field, value);
7682f2d0 624#ifndef CONFIG_X86_64
6aa8b732
AK		 625 asm volatile ("");
626 vmcs_writel(field+1, value >> 32);
627#endif
628}
629
2ab455cc
AL		 630static void vmcs_clear_bits(unsigned long field, u32 mask)
631{
632 vmcs_writel(field, vmcs_readl(field) & ~mask);
633}
634
635static void vmcs_set_bits(unsigned long field, u32 mask)
636{
637 vmcs_writel(field, vmcs_readl(field) | mask);
638}
639
abd3f2d6
AK		 640static void update_exception_bitmap(struct kvm_vcpu *vcpu)
641{
642 u32 eb;
643
fd7373cc
JK		 644 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
645 (1u << NM_VECTOR) | (1u << DB_VECTOR);
646 if ((vcpu->guest_debug &
647 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
648 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
649 eb |= 1u << BP_VECTOR;
7ffd92c5 650 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 651 eb = ~0;
089d034e 652 if (enable_ept)
1439442c 653 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 654 if (vcpu->fpu_active)
655 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 656 vmcs_write32(EXCEPTION_BITMAP, eb);
657}
658
61d2ef2c
AK		 659static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
660{
661 unsigned i;
662 struct msr_autoload *m = &vmx->msr_autoload;
663
664 for (i = 0; i < m->nr; ++i)
665 if (m->guest[i].index == msr)
666 break;
667
668 if (i == m->nr)
669 return;
670 --m->nr;
671 m->guest[i] = m->guest[m->nr];
672 m->host[i] = m->host[m->nr];
673 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
674 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
675}
676
677static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
678 u64 guest_val, u64 host_val)
679{
680 unsigned i;
681 struct msr_autoload *m = &vmx->msr_autoload;
682
683 for (i = 0; i < m->nr; ++i)
684 if (m->guest[i].index == msr)
685 break;
686
687 if (i == m->nr) {
688 ++m->nr;
689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
691 }
692
693 m->guest[i].index = msr;
694 m->guest[i].value = guest_val;
695 m->host[i].index = msr;
696 m->host[i].value = host_val;
697}
698
33ed6329
AK		 699static void reload_tss(void)
700{
33ed6329
AK		 701 /*
702 * VT restores TR but not its size. Useless.
703 */
d359192f 704 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 705 struct desc_struct *descs;
33ed6329 706
d359192f 707 descs = (void *)gdt->address;
33ed6329
AK		 708 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
709 load_TR_desc();
33ed6329
AK		 710}
711
92c0d900 712static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 713{
3a34a881 714 u64 guest_efer;
51c6cf66
AK		 715 u64 ignore_bits;
716
f6801dff 717 guest_efer = vmx->vcpu.arch.efer;
3a34a881 718
51c6cf66
AK		 719 /*
720 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
721 * outside long mode
722 */
723 ignore_bits = EFER_NX | EFER_SCE;
724#ifdef CONFIG_X86_64
725 ignore_bits |= EFER_LMA | EFER_LME;
726 /* SCE is meaningful only in long mode on Intel */
727 if (guest_efer & EFER_LMA)
728 ignore_bits &= ~(u64)EFER_SCE;
729#endif
51c6cf66
AK		 730 guest_efer &= ~ignore_bits;
731 guest_efer |= host_efer & ignore_bits;
26bb0981 732 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 733 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 734
735 clear_atomic_switch_msr(vmx, MSR_EFER);
736 /* On ept, can't emulate nx, and must switch nx atomically */
737 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
738 guest_efer = vmx->vcpu.arch.efer;
739 if (!(guest_efer & EFER_LMA))
740 guest_efer &= ~EFER_LME;
741 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
742 return false;
743 }
744
26bb0981 745 return true;
51c6cf66
AK		 746}
747
2d49ec72
GN		 748static unsigned long segment_base(u16 selector)
749{
d359192f 750 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 751 struct desc_struct *d;
752 unsigned long table_base;
753 unsigned long v;
754
755 if (!(selector & ~3))
756 return 0;
757
d359192f 758 table_base = gdt->address;
2d49ec72
GN		 759
760 if (selector & 4) { /* from ldt */
761 u16 ldt_selector = kvm_read_ldt();
762
763 if (!(ldt_selector & ~3))
764 return 0;
765
766 table_base = segment_base(ldt_selector);
767 }
768 d = (struct desc_struct *)(table_base + (selector & ~7));
769 v = get_desc_base(d);
770#ifdef CONFIG_X86_64
771 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
772 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
773#endif
774 return v;
775}
776
777static inline unsigned long kvm_read_tr_base(void)
778{
779 u16 tr;
780 asm("str %0" : "=g"(tr));
781 return segment_base(tr);
782}
783
04d2cc77 784static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 785{
04d2cc77 786 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 787 int i;
04d2cc77 788
a2fa3e9f 789 if (vmx->host_state.loaded)
33ed6329
AK		 790 return;
791
a2fa3e9f 792 vmx->host_state.loaded = 1;
33ed6329
AK		 793 /*
794 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
795 * allow segment selectors with cpl > 0 or ti == 1.
796 */
d6e88aec 797 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 798 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 799 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 800 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 801 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 802 vmx->host_state.fs_reload_needed = 0;
803 } else {
33ed6329 804 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 805 vmx->host_state.fs_reload_needed = 1;
33ed6329 806 }
9581d442 807 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 808 if (!(vmx->host_state.gs_sel & 7))
809 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 810 else {
811 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 812 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 813 }
814
815#ifdef CONFIG_X86_64
816 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
817 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
818#else
a2fa3e9f
GH		 819 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
820 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 821#endif
707c0874
AK		 822
823#ifdef CONFIG_X86_64
c8770e7b
AK		 824 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
825 if (is_long_mode(&vmx->vcpu))
44ea2b17 826 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 827#endif
26bb0981
AK		 828 for (i = 0; i < vmx->save_nmsrs; ++i)
829 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 830 vmx->guest_msrs[i].data,
831 vmx->guest_msrs[i].mask);
33ed6329
AK		 832}
833
a9b21b62 834static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 835{
a2fa3e9f 836 if (!vmx->host_state.loaded)
33ed6329
AK		 837 return;
838
e1beb1d3 839 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 840 vmx->host_state.loaded = 0;
c8770e7b
AK		 841#ifdef CONFIG_X86_64
842 if (is_long_mode(&vmx->vcpu))
843 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
844#endif
152d3f2f 845 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 846 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 847#ifdef CONFIG_X86_64
9581d442 848 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 849#else
850 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 851#endif
33ed6329 852 }
0a77fe4c
AK		 853 if (vmx->host_state.fs_reload_needed)
854 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 855 reload_tss();
44ea2b17 856#ifdef CONFIG_X86_64
c8770e7b 857 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 858#endif
1c11e713
AK		 859 if (current_thread_info()->status & TS_USEDFPU)
860 clts();
3444d7da 861 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 862}
863
a9b21b62
AK		 864static void vmx_load_host_state(struct vcpu_vmx *vmx)
865{
866 preempt_disable();
867 __vmx_load_host_state(vmx);
868 preempt_enable();
869}
870
6aa8b732
AK		 871/*
872 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
873 * vcpu mutex is already taken.
874 */
15ad7146 875static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 876{
a2fa3e9f 877 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 878 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 879
4610c9cc
DX		 880 if (!vmm_exclusive)
881 kvm_cpu_vmxon(phys_addr);
882 else if (vcpu->cpu != cpu)
8b9cf98c 883 vcpu_clear(vmx);
6aa8b732 884
a2fa3e9f 885 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 886 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 887 vmcs_load(vmx->vmcs);
6aa8b732
AK		 888 }
889
890 if (vcpu->cpu != cpu) {
d359192f 891 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 892 unsigned long sysenter_esp;
893
a8eeb04a 894 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be
DX		 895 local_irq_disable();
896 list_add(&vmx->local_vcpus_link,
897 &per_cpu(vcpus_on_cpu, cpu));
898 local_irq_enable();
899
6aa8b732
AK		 900 /*
901 * Linux uses per-cpu TSS and GDT, so set these when switching
902 * processors.
903 */
d6e88aec 904 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 905 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 906
907 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
908 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
909 }
6aa8b732
AK		 910}
911
912static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
913{
a9b21b62 914 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 915 if (!vmm_exclusive) {
b923e62e 916 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 917 kvm_cpu_vmxoff();
918 }
6aa8b732
AK		 919}
920
5fd86fcf
AK		 921static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
922{
81231c69
AK		 923 ulong cr0;
924
5fd86fcf
AK		 925 if (vcpu->fpu_active)
926 return;
927 vcpu->fpu_active = 1;
81231c69
AK		 928 cr0 = vmcs_readl(GUEST_CR0);
929 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
930 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
931 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 932 update_exception_bitmap(vcpu);
edcafe3c
AK		 933 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
934 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 935}
936
edcafe3c
AK		 937static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
938
5fd86fcf
AK		 939static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
940{
edcafe3c 941 vmx_decache_cr0_guest_bits(vcpu);
81231c69 942 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 943 update_exception_bitmap(vcpu);
edcafe3c
AK		 944 vcpu->arch.cr0_guest_owned_bits = 0;
945 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
946 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 947}
948
6aa8b732
AK		 949static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
950{
78ac8b47 951 unsigned long rflags, save_rflags;
345dcaa8
AK		 952
953 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 954 if (to_vmx(vcpu)->rmode.vm86_active) {
955 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
956 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
957 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
958 }
345dcaa8 959 return rflags;
6aa8b732
AK		 960}
961
962static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
963{
78ac8b47
AK		 964 if (to_vmx(vcpu)->rmode.vm86_active) {
965 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 966 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 967 }
6aa8b732
AK		 968 vmcs_writel(GUEST_RFLAGS, rflags);
969}
970
2809f5d2
GC		 971static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
972{
973 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
974 int ret = 0;
975
976 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 977 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 978 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 979 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 980
981 return ret & mask;
982}
983
984static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
985{
986 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
987 u32 interruptibility = interruptibility_old;
988
989 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
990
48005f64 991 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 992 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 993 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 994 interruptibility |= GUEST_INTR_STATE_STI;
995
996 if ((interruptibility != interruptibility_old))
997 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
998}
999
6aa8b732
AK		 1000static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1001{
1002 unsigned long rip;
6aa8b732 1003
5fdbf976 1004 rip = kvm_rip_read(vcpu);
6aa8b732 1005 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1006 kvm_rip_write(vcpu, rip);
6aa8b732 1007
2809f5d2
GC		 1008 /* skipping an emulated instruction also counts */
1009 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1010}
1011
298101da 1012static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1013 bool has_error_code, u32 error_code,
1014 bool reinject)
298101da 1015{
77ab6db0 1016 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1017 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1018
8ab2d2e2 1019 if (has_error_code) {
77ab6db0 1020 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1021 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1022 }
77ab6db0 1023
7ffd92c5 1024 if (vmx->rmode.vm86_active) {
a92601bb
MG		 1025 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1026 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1027 return;
1028 }
1029
66fd3f7f
GN		 1030 if (kvm_exception_is_soft(nr)) {
1031 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1032 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1033 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1034 } else
1035 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1036
1037 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1038}
1039
4e47c7a6
SY		 1040static bool vmx_rdtscp_supported(void)
1041{
1042 return cpu_has_vmx_rdtscp();
1043}
1044
a75beee6
ED		 1045/*
1046 * Swap MSR entry in host/guest MSR entry array.
1047 */
8b9cf98c 1048static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1049{
26bb0981 1050 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1051
1052 tmp = vmx->guest_msrs[to];
1053 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1054 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1055}
1056
e38aea3e
AK		 1057/*
1058 * Set up the vmcs to automatically save and restore system
1059 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1060 * mode, as fiddling with msrs is very expensive.
1061 */
8b9cf98c 1062static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1063{
26bb0981 1064 int save_nmsrs, index;
5897297b 1065 unsigned long *msr_bitmap;
e38aea3e 1066
33f9c505 1067 vmx_load_host_state(vmx);
a75beee6
ED		 1068 save_nmsrs = 0;
1069#ifdef CONFIG_X86_64
8b9cf98c 1070 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1071 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1072 if (index >= 0)
8b9cf98c
RR		 1073 move_msr_up(vmx, index, save_nmsrs++);
1074 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1075 if (index >= 0)
8b9cf98c
RR		 1076 move_msr_up(vmx, index, save_nmsrs++);
1077 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1078 if (index >= 0)
8b9cf98c 1079 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1080 index = __find_msr_index(vmx, MSR_TSC_AUX);
1081 if (index >= 0 && vmx->rdtscp_enabled)
1082 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1083 /*
8c06585d 1084 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1085 * if efer.sce is enabled.
1086 */
8c06585d 1087 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1088 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1089 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1090 }
1091#endif
92c0d900
AK		 1092 index = __find_msr_index(vmx, MSR_EFER);
1093 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1094 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1095
26bb0981 1096 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1097
1098 if (cpu_has_vmx_msr_bitmap()) {
1099 if (is_long_mode(&vmx->vcpu))
1100 msr_bitmap = vmx_msr_bitmap_longmode;
1101 else
1102 msr_bitmap = vmx_msr_bitmap_legacy;
1103
1104 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1105 }
e38aea3e
AK		 1106}
1107
6aa8b732
AK		 1108/*
1109 * reads and returns guest's timestamp counter "register"
1110 * guest_tsc = host_tsc + tsc_offset -- 21.3
1111 */
1112static u64 guest_read_tsc(void)
1113{
1114 u64 host_tsc, tsc_offset;
1115
1116 rdtscll(host_tsc);
1117 tsc_offset = vmcs_read64(TSC_OFFSET);
1118 return host_tsc + tsc_offset;
1119}
1120
1121/*
99e3e30a 1122 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1123 */
99e3e30a 1124static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1125{
f4e1b3c8 1126 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1127}
1128
e48672fa
ZA		 1129static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1130{
1131 u64 offset = vmcs_read64(TSC_OFFSET);
1132 vmcs_write64(TSC_OFFSET, offset + adjustment);
1133}
1134
6aa8b732
AK		 1135/*
1136 * Reads an msr value (of 'msr_index') into 'pdata'.
1137 * Returns 0 on success, non-0 otherwise.
1138 * Assumes vcpu_load() was already called.
1139 */
1140static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1141{
1142 u64 data;
26bb0981 1143 struct shared_msr_entry *msr;
6aa8b732
AK		 1144
1145 if (!pdata) {
1146 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1147 return -EINVAL;
1148 }
1149
1150 switch (msr_index) {
05b3e0c2 1151#ifdef CONFIG_X86_64
6aa8b732
AK		 1152 case MSR_FS_BASE:
1153 data = vmcs_readl(GUEST_FS_BASE);
1154 break;
1155 case MSR_GS_BASE:
1156 data = vmcs_readl(GUEST_GS_BASE);
1157 break;
44ea2b17
AK		 1158 case MSR_KERNEL_GS_BASE:
1159 vmx_load_host_state(to_vmx(vcpu));
1160 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1161 break;
26bb0981 1162#endif
6aa8b732 1163 case MSR_EFER:
3bab1f5d 1164 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1165 case MSR_IA32_TSC:
6aa8b732
AK		 1166 data = guest_read_tsc();
1167 break;
1168 case MSR_IA32_SYSENTER_CS:
1169 data = vmcs_read32(GUEST_SYSENTER_CS);
1170 break;
1171 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1172 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1173 break;
1174 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1175 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1176 break;
4e47c7a6
SY		 1177 case MSR_TSC_AUX:
1178 if (!to_vmx(vcpu)->rdtscp_enabled)
1179 return 1;
1180 /* Otherwise falls through */
6aa8b732 1181 default:
26bb0981 1182 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1183 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1184 if (msr) {
542423b0 1185 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1186 data = msr->data;
1187 break;
6aa8b732 1188 }
3bab1f5d 1189 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1190 }
1191
1192 *pdata = data;
1193 return 0;
1194}
1195
1196/*
1197 * Writes msr value into into the appropriate "register".
1198 * Returns 0 on success, non-0 otherwise.
1199 * Assumes vcpu_load() was already called.
1200 */
1201static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1202{
a2fa3e9f 1203 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1204 struct shared_msr_entry *msr;
2cc51560
ED		 1205 int ret = 0;
1206
6aa8b732 1207 switch (msr_index) {
3bab1f5d 1208 case MSR_EFER:
a9b21b62 1209 vmx_load_host_state(vmx);
2cc51560 1210 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1211 break;
16175a79 1212#ifdef CONFIG_X86_64
6aa8b732
AK		 1213 case MSR_FS_BASE:
1214 vmcs_writel(GUEST_FS_BASE, data);
1215 break;
1216 case MSR_GS_BASE:
1217 vmcs_writel(GUEST_GS_BASE, data);
1218 break;
44ea2b17
AK		 1219 case MSR_KERNEL_GS_BASE:
1220 vmx_load_host_state(vmx);
1221 vmx->msr_guest_kernel_gs_base = data;
1222 break;
6aa8b732
AK		 1223#endif
1224 case MSR_IA32_SYSENTER_CS:
1225 vmcs_write32(GUEST_SYSENTER_CS, data);
1226 break;
1227 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1228 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1229 break;
1230 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1231 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1232 break;
af24a4e4 1233 case MSR_IA32_TSC:
99e3e30a 1234 kvm_write_tsc(vcpu, data);
6aa8b732 1235 break;
468d472f
SY		 1236 case MSR_IA32_CR_PAT:
1237 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1238 vmcs_write64(GUEST_IA32_PAT, data);
1239 vcpu->arch.pat = data;
1240 break;
1241 }
4e47c7a6
SY		 1242 ret = kvm_set_msr_common(vcpu, msr_index, data);
1243 break;
1244 case MSR_TSC_AUX:
1245 if (!vmx->rdtscp_enabled)
1246 return 1;
1247 /* Check reserved bit, higher 32 bits should be zero */
1248 if ((data >> 32) != 0)
1249 return 1;
1250 /* Otherwise falls through */
6aa8b732 1251 default:
8b9cf98c 1252 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1253 if (msr) {
542423b0 1254 vmx_load_host_state(vmx);
3bab1f5d
AK		 1255 msr->data = data;
1256 break;
6aa8b732 1257 }
2cc51560 1258 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1259 }
1260
2cc51560 1261 return ret;
6aa8b732
AK		 1262}
1263
5fdbf976 1264static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1265{
5fdbf976
MT		 1266 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1267 switch (reg) {
1268 case VCPU_REGS_RSP:
1269 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1270 break;
1271 case VCPU_REGS_RIP:
1272 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1273 break;
6de4f3ad
AK		 1274 case VCPU_EXREG_PDPTR:
1275 if (enable_ept)
1276 ept_save_pdptrs(vcpu);
1277 break;
5fdbf976
MT		 1278 default:
1279 break;
1280 }
6aa8b732
AK		 1281}
1282
355be0b9 1283static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1284{
ae675ef0
JK		 1285 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1286 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1287 else
1288 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1289
abd3f2d6 1290 update_exception_bitmap(vcpu);
6aa8b732
AK		 1291}
1292
1293static __init int cpu_has_kvm_support(void)
1294{
6210e37b 1295 return cpu_has_vmx();
6aa8b732
AK		 1296}
1297
1298static __init int vmx_disabled_by_bios(void)
1299{
1300 u64 msr;
1301
1302 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1303 if (msr & FEATURE_CONTROL_LOCKED) {
1304 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1305 && tboot_enabled())
1306 return 1;
1307 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
f9335afe
SW		 1308 && !tboot_enabled()) {
1309 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1310 " activate TXT before enabling KVM\n");
cafd6659 1311 return 1;
f9335afe 1312 }
cafd6659
SW		 1313 }
1314
1315 return 0;
62b3ffb8 1316 /* locked but not enabled */
6aa8b732
AK		 1317}
1318
7725b894
DX		 1319static void kvm_cpu_vmxon(u64 addr)
1320{
1321 asm volatile (ASM_VMX_VMXON_RAX
1322 : : "a"(&addr), "m"(addr)
1323 : "memory", "cc");
1324}
1325
10474ae8 1326static int hardware_enable(void *garbage)
6aa8b732
AK		 1327{
1328 int cpu = raw_smp_processor_id();
1329 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1330 u64 old, test_bits;
6aa8b732 1331
10474ae8
AG		 1332 if (read_cr4() & X86_CR4_VMXE)
1333 return -EBUSY;
1334
543e4243 1335 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1336 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1337
1338 test_bits = FEATURE_CONTROL_LOCKED;
1339 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1340 if (tboot_enabled())
1341 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1342
1343 if ((old & test_bits) != test_bits) {
6aa8b732 1344 /* enable and lock */
cafd6659
SW		 1345 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1346 }
66aee91a 1347 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1348
4610c9cc
DX		 1349 if (vmm_exclusive) {
1350 kvm_cpu_vmxon(phys_addr);
1351 ept_sync_global();
1352 }
10474ae8 1353
3444d7da
AK		 1354 store_gdt(&__get_cpu_var(host_gdt));
1355
10474ae8 1356 return 0;
6aa8b732
AK		 1357}
1358
543e4243
AK		 1359static void vmclear_local_vcpus(void)
1360{
1361 int cpu = raw_smp_processor_id();
1362 struct vcpu_vmx *vmx, *n;
1363
1364 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1365 local_vcpus_link)
1366 __vcpu_clear(vmx);
1367}
1368
710ff4a8
EH		 1369
1370/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1371 * tricks.
1372 */
1373static void kvm_cpu_vmxoff(void)
6aa8b732 1374{
4ecac3fd 1375 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1376}
1377
710ff4a8
EH		 1378static void hardware_disable(void *garbage)
1379{
4610c9cc
DX		 1380 if (vmm_exclusive) {
1381 vmclear_local_vcpus();
1382 kvm_cpu_vmxoff();
1383 }
7725b894 1384 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1385}
1386
1c3d14fe 1387static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1388 u32 msr, u32 *result)
1c3d14fe
YS		 1389{
1390 u32 vmx_msr_low, vmx_msr_high;
1391 u32 ctl = ctl_min | ctl_opt;
1392
1393 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1394
1395 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1396 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1397
1398 /* Ensure minimum (required) set of control bits are supported. */
1399 if (ctl_min & ~ctl)
002c7f7c 1400 return -EIO;
1c3d14fe
YS		 1401
1402 *result = ctl;
1403 return 0;
1404}
1405
002c7f7c 1406static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1407{
1408 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1409 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1410 u32 _pin_based_exec_control = 0;
1411 u32 _cpu_based_exec_control = 0;
f78e0e2e 1412 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1413 u32 _vmexit_control = 0;
1414 u32 _vmentry_control = 0;
1415
1416 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1417 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1418 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1419 &_pin_based_exec_control) < 0)
002c7f7c 1420 return -EIO;
1c3d14fe
YS		 1421
1422 min = CPU_BASED_HLT_EXITING |
1423#ifdef CONFIG_X86_64
1424 CPU_BASED_CR8_LOAD_EXITING |
1425 CPU_BASED_CR8_STORE_EXITING |
1426#endif
d56f546d
SY		 1427 CPU_BASED_CR3_LOAD_EXITING |
1428 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1429 CPU_BASED_USE_IO_BITMAPS |
1430 CPU_BASED_MOV_DR_EXITING |
a7052897 1431 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1432 CPU_BASED_MWAIT_EXITING |
1433 CPU_BASED_MONITOR_EXITING |
a7052897 1434 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1435 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1436 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1437 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1438 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1439 &_cpu_based_exec_control) < 0)
002c7f7c 1440 return -EIO;
6e5d865c
YS		 1441#ifdef CONFIG_X86_64
1442 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1443 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1444 ~CPU_BASED_CR8_STORE_EXITING;
1445#endif
f78e0e2e 1446 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1447 min2 = 0;
1448 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1449 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1450 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1451 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1452 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1453 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1454 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1455 if (adjust_vmx_controls(min2, opt2,
1456 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1457 &_cpu_based_2nd_exec_control) < 0)
1458 return -EIO;
1459 }
1460#ifndef CONFIG_X86_64
1461 if (!(_cpu_based_2nd_exec_control &
1462 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1463 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1464#endif
d56f546d 1465 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1466 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1467 enabled */
5fff7d27
GN		 1468 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1469 CPU_BASED_CR3_STORE_EXITING |
1470 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1471 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1472 vmx_capability.ept, vmx_capability.vpid);
1473 }
1c3d14fe
YS		 1474
1475 min = 0;
1476#ifdef CONFIG_X86_64
1477 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1478#endif
468d472f 1479 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1480 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1481 &_vmexit_control) < 0)
002c7f7c 1482 return -EIO;
1c3d14fe 1483
468d472f
SY		 1484 min = 0;
1485 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1486 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1487 &_vmentry_control) < 0)
002c7f7c 1488 return -EIO;
6aa8b732 1489
c68876fd 1490 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1491
1492 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1493 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1494 return -EIO;
1c3d14fe
YS		 1495
1496#ifdef CONFIG_X86_64
1497 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1498 if (vmx_msr_high & (1u<<16))
002c7f7c 1499 return -EIO;
1c3d14fe
YS		 1500#endif
1501
1502 /* Require Write-Back (WB) memory type for VMCS accesses. */
1503 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1504 return -EIO;
1c3d14fe 1505
002c7f7c
YS		 1506 vmcs_conf->size = vmx_msr_high & 0x1fff;
1507 vmcs_conf->order = get_order(vmcs_config.size);
1508 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1509
002c7f7c
YS		 1510 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1511 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1512 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1513 vmcs_conf->vmexit_ctrl = _vmexit_control;
1514 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1515
1516 return 0;
c68876fd 1517}
6aa8b732
AK		 1518
1519static struct vmcs *alloc_vmcs_cpu(int cpu)
1520{
1521 int node = cpu_to_node(cpu);
1522 struct page *pages;
1523 struct vmcs *vmcs;
1524
6484eb3e 1525 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1526 if (!pages)
1527 return NULL;
1528 vmcs = page_address(pages);
1c3d14fe
YS		 1529 memset(vmcs, 0, vmcs_config.size);
1530 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1531 return vmcs;
1532}
1533
1534static struct vmcs *alloc_vmcs(void)
1535{
d3b2c338 1536 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1537}
1538
1539static void free_vmcs(struct vmcs *vmcs)
1540{
1c3d14fe 1541 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1542}
1543
39959588 1544static void free_kvm_area(void)
6aa8b732
AK		 1545{
1546 int cpu;
1547
3230bb47 1548 for_each_possible_cpu(cpu) {
6aa8b732 1549 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1550 per_cpu(vmxarea, cpu) = NULL;
1551 }
6aa8b732
AK		 1552}
1553
6aa8b732
AK		 1554static __init int alloc_kvm_area(void)
1555{
1556 int cpu;
1557
3230bb47 1558 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1559 struct vmcs *vmcs;
1560
1561 vmcs = alloc_vmcs_cpu(cpu);
1562 if (!vmcs) {
1563 free_kvm_area();
1564 return -ENOMEM;
1565 }
1566
1567 per_cpu(vmxarea, cpu) = vmcs;
1568 }
1569 return 0;
1570}
1571
1572static __init int hardware_setup(void)
1573{
002c7f7c
YS		 1574 if (setup_vmcs_config(&vmcs_config) < 0)
1575 return -EIO;
50a37eb4
JR		 1576
1577 if (boot_cpu_has(X86_FEATURE_NX))
1578 kvm_enable_efer_bits(EFER_NX);
1579
93ba03c2
SY		 1580 if (!cpu_has_vmx_vpid())
1581 enable_vpid = 0;
1582
4bc9b982
SY		 1583 if (!cpu_has_vmx_ept() ||
1584 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1585 enable_ept = 0;
3a624e29
NK		 1586 enable_unrestricted_guest = 0;
1587 }
1588
1589 if (!cpu_has_vmx_unrestricted_guest())
1590 enable_unrestricted_guest = 0;
93ba03c2
SY		 1591
1592 if (!cpu_has_vmx_flexpriority())
1593 flexpriority_enabled = 0;
1594
95ba8273
GN		 1595 if (!cpu_has_vmx_tpr_shadow())
1596 kvm_x86_ops->update_cr8_intercept = NULL;
1597
54dee993
MT		 1598 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1599 kvm_disable_largepages();
1600
4b8d54f9
ZE		 1601 if (!cpu_has_vmx_ple())
1602 ple_gap = 0;
1603
6aa8b732
AK		 1604 return alloc_kvm_area();
1605}
1606
1607static __exit void hardware_unsetup(void)
1608{
1609 free_kvm_area();
1610}
1611
6aa8b732
AK		 1612static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1613{
1614 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1615
6af11b9e 1616 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1617 vmcs_write16(sf->selector, save->selector);
1618 vmcs_writel(sf->base, save->base);
1619 vmcs_write32(sf->limit, save->limit);
1620 vmcs_write32(sf->ar_bytes, save->ar);
1621 } else {
1622 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1623 << AR_DPL_SHIFT;
1624 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1625 }
1626}
1627
1628static void enter_pmode(struct kvm_vcpu *vcpu)
1629{
1630 unsigned long flags;
a89a8fb9 1631 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1632
a89a8fb9 1633 vmx->emulation_required = 1;
7ffd92c5 1634 vmx->rmode.vm86_active = 0;
6aa8b732 1635
7ffd92c5
AK		 1636 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1637 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1638 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1639
1640 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1641 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1642 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1643 vmcs_writel(GUEST_RFLAGS, flags);
1644
66aee91a
RR		 1645 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1646 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1647
1648 update_exception_bitmap(vcpu);
1649
a89a8fb9
MG		 1650 if (emulate_invalid_guest_state)
1651 return;
1652
7ffd92c5
AK		 1653 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1654 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1655 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1656 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1657
1658 vmcs_write16(GUEST_SS_SELECTOR, 0);
1659 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1660
1661 vmcs_write16(GUEST_CS_SELECTOR,
1662 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1663 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1664}
1665
d77c26fc 1666static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1667{
bfc6d222 1668 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1669 struct kvm_memslots *slots;
1670 gfn_t base_gfn;
1671
90d83dc3 1672 slots = kvm_memslots(kvm);
f495c6e5 1673 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1674 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1675 return base_gfn << PAGE_SHIFT;
1676 }
bfc6d222 1677 return kvm->arch.tss_addr;
6aa8b732
AK		 1678}
1679
1680static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1681{
1682 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1683
1684 save->selector = vmcs_read16(sf->selector);
1685 save->base = vmcs_readl(sf->base);
1686 save->limit = vmcs_read32(sf->limit);
1687 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1688 vmcs_write16(sf->selector, save->base >> 4);
1689 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1690 vmcs_write32(sf->limit, 0xffff);
1691 vmcs_write32(sf->ar_bytes, 0xf3);
1692}
1693
1694static void enter_rmode(struct kvm_vcpu *vcpu)
1695{
1696 unsigned long flags;
a89a8fb9 1697 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1698
3a624e29
NK		 1699 if (enable_unrestricted_guest)
1700 return;
1701
a89a8fb9 1702 vmx->emulation_required = 1;
7ffd92c5 1703 vmx->rmode.vm86_active = 1;
6aa8b732 1704
7ffd92c5 1705 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1706 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1707
7ffd92c5 1708 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1709 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1710
7ffd92c5 1711 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1712 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1713
1714 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1715 vmx->rmode.save_rflags = flags;
6aa8b732 1716
053de044 1717 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1718
1719 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1720 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1721 update_exception_bitmap(vcpu);
1722
a89a8fb9
MG		 1723 if (emulate_invalid_guest_state)
1724 goto continue_rmode;
1725
6aa8b732
AK		 1726 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1727 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1728 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1729
1730 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1731 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1732 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1733 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1734 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1735
7ffd92c5
AK		 1736 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1737 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1738 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1739 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1740
a89a8fb9 1741continue_rmode:
8668a3c4 1742 kvm_mmu_reset_context(vcpu);
b7ebfb05 1743 init_rmode(vcpu->kvm);
6aa8b732
AK		 1744}
1745
401d10de
AS		 1746static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1747{
1748 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1749 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1750
1751 if (!msr)
1752 return;
401d10de 1753
44ea2b17
AK		 1754 /*
1755 * Force kernel_gs_base reloading before EFER changes, as control
1756 * of this msr depends on is_long_mode().
1757 */
1758 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1759 vcpu->arch.efer = efer;
401d10de
AS		 1760 if (efer & EFER_LMA) {
1761 vmcs_write32(VM_ENTRY_CONTROLS,
1762 vmcs_read32(VM_ENTRY_CONTROLS) |
1763 VM_ENTRY_IA32E_MODE);
1764 msr->data = efer;
1765 } else {
1766 vmcs_write32(VM_ENTRY_CONTROLS,
1767 vmcs_read32(VM_ENTRY_CONTROLS) &
1768 ~VM_ENTRY_IA32E_MODE);
1769
1770 msr->data = efer & ~EFER_LME;
1771 }
1772 setup_msrs(vmx);
1773}
1774
05b3e0c2 1775#ifdef CONFIG_X86_64
6aa8b732
AK		 1776
1777static void enter_lmode(struct kvm_vcpu *vcpu)
1778{
1779 u32 guest_tr_ar;
1780
1781 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1782 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1783 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1784 __func__);
6aa8b732
AK		 1785 vmcs_write32(GUEST_TR_AR_BYTES,
1786 (guest_tr_ar & ~AR_TYPE_MASK)
1787 | AR_TYPE_BUSY_64_TSS);
1788 }
da38f438 1789 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1790}
1791
1792static void exit_lmode(struct kvm_vcpu *vcpu)
1793{
6aa8b732
AK		 1794 vmcs_write32(VM_ENTRY_CONTROLS,
1795 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1796 & ~VM_ENTRY_IA32E_MODE);
da38f438 1797 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1798}
1799
1800#endif
1801
2384d2b3
SY		 1802static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1803{
b9d762fa 1804 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 1805 if (enable_ept) {
1806 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1807 return;
4e1096d2 1808 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 1809 }
2384d2b3
SY		 1810}
1811
e8467fda
AK		 1812static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1813{
1814 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1815
1816 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1817 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1818}
1819
25c4c276 1820static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1821{
fc78f519
AK		 1822 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1823
1824 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1825 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1826}
1827
1439442c
SY		 1828static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1829{
6de4f3ad
AK		 1830 if (!test_bit(VCPU_EXREG_PDPTR,
1831 (unsigned long *)&vcpu->arch.regs_dirty))
1832 return;
1833
1439442c 1834 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1835 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1836 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1837 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1838 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 1839 }
1840}
1841
8f5d549f
AK		 1842static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1843{
1844 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1845 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1846 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1847 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1848 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 1849 }
6de4f3ad
AK		 1850
1851 __set_bit(VCPU_EXREG_PDPTR,
1852 (unsigned long *)&vcpu->arch.regs_avail);
1853 __set_bit(VCPU_EXREG_PDPTR,
1854 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1855}
1856
1439442c
SY		 1857static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1858
1859static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1860 unsigned long cr0,
1861 struct kvm_vcpu *vcpu)
1862{
1863 if (!(cr0 & X86_CR0_PG)) {
1864 /* From paging/starting to nonpaging */
1865 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1866 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1867 (CPU_BASED_CR3_LOAD_EXITING |
1868 CPU_BASED_CR3_STORE_EXITING));
1869 vcpu->arch.cr0 = cr0;
fc78f519 1870 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1871 } else if (!is_paging(vcpu)) {
1872 /* From nonpaging to paging */
1873 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1874 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1875 ~(CPU_BASED_CR3_LOAD_EXITING |
1876 CPU_BASED_CR3_STORE_EXITING));
1877 vcpu->arch.cr0 = cr0;
fc78f519 1878 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1879 }
95eb84a7
SY		 1880
1881 if (!(cr0 & X86_CR0_WP))
1882 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1883}
1884
6aa8b732
AK		 1885static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1886{
7ffd92c5 1887 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1888 unsigned long hw_cr0;
1889
1890 if (enable_unrestricted_guest)
1891 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1892 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1893 else
1894 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1895
7ffd92c5 1896 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1897 enter_pmode(vcpu);
1898
7ffd92c5 1899 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1900 enter_rmode(vcpu);
1901
05b3e0c2 1902#ifdef CONFIG_X86_64
f6801dff 1903 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1904 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1905 enter_lmode(vcpu);
707d92fa 1906 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1907 exit_lmode(vcpu);
1908 }
1909#endif
1910
089d034e 1911 if (enable_ept)
1439442c
SY		 1912 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1913
02daab21 1914 if (!vcpu->fpu_active)
81231c69 1915 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1916
6aa8b732 1917 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1918 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1919 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1920}
1921
1439442c
SY		 1922static u64 construct_eptp(unsigned long root_hpa)
1923{
1924 u64 eptp;
1925
1926 /* TODO write the value reading from MSR */
1927 eptp = VMX_EPT_DEFAULT_MT |
1928 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1929 eptp |= (root_hpa & PAGE_MASK);
1930
1931 return eptp;
1932}
1933
6aa8b732
AK		 1934static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1935{
1439442c
SY		 1936 unsigned long guest_cr3;
1937 u64 eptp;
1938
1939 guest_cr3 = cr3;
089d034e 1940 if (enable_ept) {
1439442c
SY		 1941 eptp = construct_eptp(cr3);
1942 vmcs_write64(EPT_POINTER, eptp);
1439442c 1943 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1944 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1945 ept_load_pdptrs(vcpu);
1439442c
SY		 1946 }
1947
2384d2b3 1948 vmx_flush_tlb(vcpu);
1439442c 1949 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1950}
1951
1952static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1953{
7ffd92c5 1954 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1955 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1956
ad312c7c 1957 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1958 if (enable_ept) {
1959 if (!is_paging(vcpu)) {
1960 hw_cr4 &= ~X86_CR4_PAE;
1961 hw_cr4 |= X86_CR4_PSE;
1962 } else if (!(cr4 & X86_CR4_PAE)) {
1963 hw_cr4 &= ~X86_CR4_PAE;
1964 }
1965 }
1439442c
SY		 1966
1967 vmcs_writel(CR4_READ_SHADOW, cr4);
1968 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1969}
1970
6aa8b732
AK		 1971static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1972{
1973 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1974
1975 return vmcs_readl(sf->base);
1976}
1977
1978static void vmx_get_segment(struct kvm_vcpu *vcpu,
1979 struct kvm_segment *var, int seg)
1980{
1981 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1982 u32 ar;
1983
1984 var->base = vmcs_readl(sf->base);
1985 var->limit = vmcs_read32(sf->limit);
1986 var->selector = vmcs_read16(sf->selector);
1987 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1988 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1989 ar = 0;
1990 var->type = ar & 15;
1991 var->s = (ar >> 4) & 1;
1992 var->dpl = (ar >> 5) & 3;
1993 var->present = (ar >> 7) & 1;
1994 var->avl = (ar >> 12) & 1;
1995 var->l = (ar >> 13) & 1;
1996 var->db = (ar >> 14) & 1;
1997 var->g = (ar >> 15) & 1;
1998 var->unusable = (ar >> 16) & 1;
1999}
2000
2e4d2653
IE		 2001static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2002{
3eeb3288 2003 if (!is_protmode(vcpu))
2e4d2653
IE		 2004 return 0;
2005
2006 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2007 return 3;
2008
eab4b8aa 2009 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2010}
2011
653e3108 2012static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2013{
6aa8b732
AK		 2014 u32 ar;
2015
653e3108 2016 if (var->unusable)
6aa8b732
AK		 2017 ar = 1 << 16;
2018 else {
2019 ar = var->type & 15;
2020 ar |= (var->s & 1) << 4;
2021 ar |= (var->dpl & 3) << 5;
2022 ar |= (var->present & 1) << 7;
2023 ar |= (var->avl & 1) << 12;
2024 ar |= (var->l & 1) << 13;
2025 ar |= (var->db & 1) << 14;
2026 ar |= (var->g & 1) << 15;
2027 }
f7fbf1fd
UL		 2028 if (ar == 0) /* a 0 value means unusable */
2029 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2030
2031 return ar;
2032}
2033
2034static void vmx_set_segment(struct kvm_vcpu *vcpu,
2035 struct kvm_segment *var, int seg)
2036{
7ffd92c5 2037 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2038 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2039 u32 ar;
2040
7ffd92c5
AK		 2041 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2042 vmx->rmode.tr.selector = var->selector;
2043 vmx->rmode.tr.base = var->base;
2044 vmx->rmode.tr.limit = var->limit;
2045 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2046 return;
2047 }
2048 vmcs_writel(sf->base, var->base);
2049 vmcs_write32(sf->limit, var->limit);
2050 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2051 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2052 /*
2053 * Hack real-mode segments into vm86 compatibility.
2054 */
2055 if (var->base == 0xffff0000 && var->selector == 0xf000)
2056 vmcs_writel(sf->base, 0xf0000);
2057 ar = 0xf3;
2058 } else
2059 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2060
2061 /*
2062 * Fix the "Accessed" bit in AR field of segment registers for older
2063 * qemu binaries.
2064 * IA32 arch specifies that at the time of processor reset the
2065 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2066 * is setting it to 0 in the usedland code. This causes invalid guest
2067 * state vmexit when "unrestricted guest" mode is turned on.
2068 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2069 * tree. Newer qemu binaries with that qemu fix would not need this
2070 * kvm hack.
2071 */
2072 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2073 ar |= 0x1; /* Accessed */
2074
6aa8b732
AK		 2075 vmcs_write32(sf->ar_bytes, ar);
2076}
2077
6aa8b732
AK		 2078static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2079{
2080 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2081
2082 *db = (ar >> 14) & 1;
2083 *l = (ar >> 13) & 1;
2084}
2085
89a27f4d 2086static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2087{
89a27f4d
GN		 2088 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2089 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2090}
2091
89a27f4d 2092static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2093{
89a27f4d
GN		 2094 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2095 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2096}
2097
89a27f4d 2098static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2099{
89a27f4d
GN		 2100 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2101 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2102}
2103
89a27f4d 2104static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2105{
89a27f4d
GN		 2106 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2107 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2108}
2109
648dfaa7
MG		 2110static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2111{
2112 struct kvm_segment var;
2113 u32 ar;
2114
2115 vmx_get_segment(vcpu, &var, seg);
2116 ar = vmx_segment_access_rights(&var);
2117
2118 if (var.base != (var.selector << 4))
2119 return false;
2120 if (var.limit != 0xffff)
2121 return false;
2122 if (ar != 0xf3)
2123 return false;
2124
2125 return true;
2126}
2127
2128static bool code_segment_valid(struct kvm_vcpu *vcpu)
2129{
2130 struct kvm_segment cs;
2131 unsigned int cs_rpl;
2132
2133 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2134 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2135
1872a3f4
AK		 2136 if (cs.unusable)
2137 return false;
648dfaa7
MG		 2138 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2139 return false;
2140 if (!cs.s)
2141 return false;
1872a3f4 2142 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2143 if (cs.dpl > cs_rpl)
2144 return false;
1872a3f4 2145 } else {
648dfaa7
MG		 2146 if (cs.dpl != cs_rpl)
2147 return false;
2148 }
2149 if (!cs.present)
2150 return false;
2151
2152 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2153 return true;
2154}
2155
2156static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2157{
2158 struct kvm_segment ss;
2159 unsigned int ss_rpl;
2160
2161 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2162 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2163
1872a3f4
AK		 2164 if (ss.unusable)
2165 return true;
2166 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2167 return false;
2168 if (!ss.s)
2169 return false;
2170 if (ss.dpl != ss_rpl) /* DPL != RPL */
2171 return false;
2172 if (!ss.present)
2173 return false;
2174
2175 return true;
2176}
2177
2178static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2179{
2180 struct kvm_segment var;
2181 unsigned int rpl;
2182
2183 vmx_get_segment(vcpu, &var, seg);
2184 rpl = var.selector & SELECTOR_RPL_MASK;
2185
1872a3f4
AK		 2186 if (var.unusable)
2187 return true;
648dfaa7
MG		 2188 if (!var.s)
2189 return false;
2190 if (!var.present)
2191 return false;
2192 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2193 if (var.dpl < rpl) /* DPL < RPL */
2194 return false;
2195 }
2196
2197 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2198 * rights flags
2199 */
2200 return true;
2201}
2202
2203static bool tr_valid(struct kvm_vcpu *vcpu)
2204{
2205 struct kvm_segment tr;
2206
2207 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2208
1872a3f4
AK		 2209 if (tr.unusable)
2210 return false;
648dfaa7
MG		 2211 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2212 return false;
1872a3f4 2213 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2214 return false;
2215 if (!tr.present)
2216 return false;
2217
2218 return true;
2219}
2220
2221static bool ldtr_valid(struct kvm_vcpu *vcpu)
2222{
2223 struct kvm_segment ldtr;
2224
2225 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2226
1872a3f4
AK		 2227 if (ldtr.unusable)
2228 return true;
648dfaa7
MG		 2229 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2230 return false;
2231 if (ldtr.type != 2)
2232 return false;
2233 if (!ldtr.present)
2234 return false;
2235
2236 return true;
2237}
2238
2239static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2240{
2241 struct kvm_segment cs, ss;
2242
2243 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2244 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2245
2246 return ((cs.selector & SELECTOR_RPL_MASK) ==
2247 (ss.selector & SELECTOR_RPL_MASK));
2248}
2249
2250/*
2251 * Check if guest state is valid. Returns true if valid, false if
2252 * not.
2253 * We assume that registers are always usable
2254 */
2255static bool guest_state_valid(struct kvm_vcpu *vcpu)
2256{
2257 /* real mode guest state checks */
3eeb3288 2258 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2259 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2260 return false;
2261 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2262 return false;
2263 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2264 return false;
2265 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2266 return false;
2267 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2268 return false;
2269 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2270 return false;
2271 } else {
2272 /* protected mode guest state checks */
2273 if (!cs_ss_rpl_check(vcpu))
2274 return false;
2275 if (!code_segment_valid(vcpu))
2276 return false;
2277 if (!stack_segment_valid(vcpu))
2278 return false;
2279 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2280 return false;
2281 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2282 return false;
2283 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2284 return false;
2285 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2286 return false;
2287 if (!tr_valid(vcpu))
2288 return false;
2289 if (!ldtr_valid(vcpu))
2290 return false;
2291 }
2292 /* TODO:
2293 * - Add checks on RIP
2294 * - Add checks on RFLAGS
2295 */
2296
2297 return true;
2298}
2299
d77c26fc 2300static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2301{
6aa8b732 2302 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2303 u16 data = 0;
10589a46 2304 int ret = 0;
195aefde 2305 int r;
6aa8b732 2306
195aefde
IE		 2307 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2308 if (r < 0)
10589a46 2309 goto out;
195aefde 2310 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2311 r = kvm_write_guest_page(kvm, fn++, &data,
2312 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2313 if (r < 0)
10589a46 2314 goto out;
195aefde
IE		 2315 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2316 if (r < 0)
10589a46 2317 goto out;
195aefde
IE		 2318 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2319 if (r < 0)
10589a46 2320 goto out;
195aefde 2321 data = ~0;
10589a46
MT		 2322 r = kvm_write_guest_page(kvm, fn, &data,
2323 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2324 sizeof(u8));
195aefde 2325 if (r < 0)
10589a46
MT		 2326 goto out;
2327
2328 ret = 1;
2329out:
10589a46 2330 return ret;
6aa8b732
AK		 2331}
2332
b7ebfb05
SY		 2333static int init_rmode_identity_map(struct kvm *kvm)
2334{
2335 int i, r, ret;
2336 pfn_t identity_map_pfn;
2337 u32 tmp;
2338
089d034e 2339 if (!enable_ept)
b7ebfb05
SY		 2340 return 1;
2341 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2342 printk(KERN_ERR "EPT: identity-mapping pagetable "
2343 "haven't been allocated!\n");
2344 return 0;
2345 }
2346 if (likely(kvm->arch.ept_identity_pagetable_done))
2347 return 1;
2348 ret = 0;
b927a3ce 2349 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2350 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2351 if (r < 0)
2352 goto out;
2353 /* Set up identity-mapping pagetable for EPT in real mode */
2354 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2355 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2356 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2357 r = kvm_write_guest_page(kvm, identity_map_pfn,
2358 &tmp, i * sizeof(tmp), sizeof(tmp));
2359 if (r < 0)
2360 goto out;
2361 }
2362 kvm->arch.ept_identity_pagetable_done = true;
2363 ret = 1;
2364out:
2365 return ret;
2366}
2367
6aa8b732
AK		 2368static void seg_setup(int seg)
2369{
2370 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2371 unsigned int ar;
6aa8b732
AK		 2372
2373 vmcs_write16(sf->selector, 0);
2374 vmcs_writel(sf->base, 0);
2375 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2376 if (enable_unrestricted_guest) {
2377 ar = 0x93;
2378 if (seg == VCPU_SREG_CS)
2379 ar |= 0x08; /* code segment */
2380 } else
2381 ar = 0xf3;
2382
2383 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2384}
2385
f78e0e2e
SY		 2386static int alloc_apic_access_page(struct kvm *kvm)
2387{
2388 struct kvm_userspace_memory_region kvm_userspace_mem;
2389 int r = 0;
2390
79fac95e 2391 mutex_lock(&kvm->slots_lock);
bfc6d222 2392 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2393 goto out;
2394 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2395 kvm_userspace_mem.flags = 0;
2396 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2397 kvm_userspace_mem.memory_size = PAGE_SIZE;
2398 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2399 if (r)
2400 goto out;
72dc67a6 2401
bfc6d222 2402 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2403out:
79fac95e 2404 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2405 return r;
2406}
2407
b7ebfb05
SY		 2408static int alloc_identity_pagetable(struct kvm *kvm)
2409{
2410 struct kvm_userspace_memory_region kvm_userspace_mem;
2411 int r = 0;
2412
79fac95e 2413 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2414 if (kvm->arch.ept_identity_pagetable)
2415 goto out;
2416 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2417 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2418 kvm_userspace_mem.guest_phys_addr =
2419 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2420 kvm_userspace_mem.memory_size = PAGE_SIZE;
2421 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2422 if (r)
2423 goto out;
2424
b7ebfb05 2425 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2426 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2427out:
79fac95e 2428 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2429 return r;
2430}
2431
2384d2b3
SY		 2432static void allocate_vpid(struct vcpu_vmx *vmx)
2433{
2434 int vpid;
2435
2436 vmx->vpid = 0;
919818ab 2437 if (!enable_vpid)
2384d2b3
SY		 2438 return;
2439 spin_lock(&vmx_vpid_lock);
2440 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2441 if (vpid < VMX_NR_VPIDS) {
2442 vmx->vpid = vpid;
2443 __set_bit(vpid, vmx_vpid_bitmap);
2444 }
2445 spin_unlock(&vmx_vpid_lock);
2446}
2447
cdbecfc3
LJ		 2448static void free_vpid(struct vcpu_vmx *vmx)
2449{
2450 if (!enable_vpid)
2451 return;
2452 spin_lock(&vmx_vpid_lock);
2453 if (vmx->vpid != 0)
2454 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2455 spin_unlock(&vmx_vpid_lock);
2456}
2457
5897297b 2458static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2459{
3e7c73e9 2460 int f = sizeof(unsigned long);
25c5f225
SY		 2461
2462 if (!cpu_has_vmx_msr_bitmap())
2463 return;
2464
2465 /*
2466 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2467 * have the write-low and read-high bitmap offsets the wrong way round.
2468 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2469 */
25c5f225 2470 if (msr <= 0x1fff) {
3e7c73e9
AK		 2471 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2472 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2473 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2474 msr &= 0x1fff;
3e7c73e9
AK		 2475 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2476 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2477 }
25c5f225
SY		 2478}
2479
5897297b
AK		 2480static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2481{
2482 if (!longmode_only)
2483 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2484 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2485}
2486
6aa8b732
AK		 2487/*
2488 * Sets up the vmcs for emulated real mode.
2489 */
8b9cf98c 2490static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2491{
468d472f 2492 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2493 u32 junk;
f4e1b3c8 2494 u64 host_pat;
6aa8b732 2495 unsigned long a;
89a27f4d 2496 struct desc_ptr dt;
6aa8b732 2497 int i;
cd2276a7 2498 unsigned long kvm_vmx_return;
6e5d865c 2499 u32 exec_control;
6aa8b732 2500
6aa8b732 2501 /* I/O */
3e7c73e9
AK		 2502 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2503 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2504
25c5f225 2505 if (cpu_has_vmx_msr_bitmap())
5897297b 2506 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2507
6aa8b732
AK		 2508 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2509
6aa8b732 2510 /* Control */
1c3d14fe
YS		 2511 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2512 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2513
2514 exec_control = vmcs_config.cpu_based_exec_ctrl;
2515 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2516 exec_control &= ~CPU_BASED_TPR_SHADOW;
2517#ifdef CONFIG_X86_64
2518 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2519 CPU_BASED_CR8_LOAD_EXITING;
2520#endif
2521 }
089d034e 2522 if (!enable_ept)
d56f546d 2523 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2524 CPU_BASED_CR3_LOAD_EXITING |
2525 CPU_BASED_INVLPG_EXITING;
6e5d865c 2526 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2527
83ff3b9d
SY		 2528 if (cpu_has_secondary_exec_ctrls()) {
2529 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2530 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2531 exec_control &=
2532 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2533 if (vmx->vpid == 0)
2534 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2535 if (!enable_ept) {
d56f546d 2536 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2537 enable_unrestricted_guest = 0;
2538 }
3a624e29
NK		 2539 if (!enable_unrestricted_guest)
2540 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2541 if (!ple_gap)
2542 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2543 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2544 }
f78e0e2e 2545
4b8d54f9
ZE		 2546 if (ple_gap) {
2547 vmcs_write32(PLE_GAP, ple_gap);
2548 vmcs_write32(PLE_WINDOW, ple_window);
2549 }
2550
c7addb90
AK		 2551 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2552 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2553 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2554
1c11e713 2555 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2556 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2557 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2558
2559 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2560 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2561 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
9581d442
AK		 2562 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2563 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6aa8b732 2564 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2565#ifdef CONFIG_X86_64
6aa8b732
AK		 2566 rdmsrl(MSR_FS_BASE, a);
2567 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2568 rdmsrl(MSR_GS_BASE, a);
2569 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2570#else
2571 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2572 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2573#endif
2574
2575 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2576
ec68798c 2577 native_store_idt(&dt);
89a27f4d 2578 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2579
d77c26fc 2580 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2581 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2582 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2583 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2584 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2585 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2586 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2587
2588 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2589 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2590 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2591 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2592 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2593 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2594
468d472f
SY		 2595 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2596 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2597 host_pat = msr_low | ((u64) msr_high << 32);
2598 vmcs_write64(HOST_IA32_PAT, host_pat);
2599 }
2600 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2601 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2602 host_pat = msr_low | ((u64) msr_high << 32);
2603 /* Write the default value follow host pat */
2604 vmcs_write64(GUEST_IA32_PAT, host_pat);
2605 /* Keep arch.pat sync with GUEST_IA32_PAT */
2606 vmx->vcpu.arch.pat = host_pat;
2607 }
2608
6aa8b732
AK		 2609 for (i = 0; i < NR_VMX_MSR; ++i) {
2610 u32 index = vmx_msr_index[i];
2611 u32 data_low, data_high;
a2fa3e9f 2612 int j = vmx->nmsrs;
6aa8b732
AK		 2613
2614 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2615 continue;
432bd6cb
AK		 2616 if (wrmsr_safe(index, data_low, data_high) < 0)
2617 continue;
26bb0981
AK		 2618 vmx->guest_msrs[j].index = i;
2619 vmx->guest_msrs[j].data = 0;
d5696725 2620 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2621 ++vmx->nmsrs;
6aa8b732 2622 }
6aa8b732 2623
1c3d14fe 2624 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2625
2626 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2627 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2628
e00c8cf2 2629 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2630 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2631 if (enable_ept)
2632 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2633 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2634
99e3e30a 2635 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 2636
e00c8cf2
AK		 2637 return 0;
2638}
2639
b7ebfb05
SY		 2640static int init_rmode(struct kvm *kvm)
2641{
4b9d3a04
XG		 2642 int idx, ret = 0;
2643
2644 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05 2645 if (!init_rmode_tss(kvm))
4b9d3a04 2646 goto exit;
b7ebfb05 2647 if (!init_rmode_identity_map(kvm))
4b9d3a04
XG		 2648 goto exit;
2649
2650 ret = 1;
2651exit:
2652 srcu_read_unlock(&kvm->srcu, idx);
2653 return ret;
b7ebfb05
SY		 2654}
2655
e00c8cf2
AK		 2656static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2657{
2658 struct vcpu_vmx *vmx = to_vmx(vcpu);
2659 u64 msr;
4b9d3a04 2660 int ret;
e00c8cf2 2661
5fdbf976 2662 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
b7ebfb05 2663 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2664 ret = -ENOMEM;
2665 goto out;
2666 }
2667
7ffd92c5 2668 vmx->rmode.vm86_active = 0;
e00c8cf2 2669
3b86cd99
JK		 2670 vmx->soft_vnmi_blocked = 0;
2671
ad312c7c 2672 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2673 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2674 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2675 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2676 msr |= MSR_IA32_APICBASE_BSP;
2677 kvm_set_apic_base(&vmx->vcpu, msr);
2678
10ab25cd
JK		 2679 ret = fx_init(&vmx->vcpu);
2680 if (ret != 0)
2681 goto out;
e00c8cf2 2682
5706be0d 2683 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2684 /*
2685 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2686 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2687 */
c5af89b6 2688 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2689 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2690 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2691 } else {
ad312c7c
ZX		 2692 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2693 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2694 }
e00c8cf2
AK		 2695
2696 seg_setup(VCPU_SREG_DS);
2697 seg_setup(VCPU_SREG_ES);
2698 seg_setup(VCPU_SREG_FS);
2699 seg_setup(VCPU_SREG_GS);
2700 seg_setup(VCPU_SREG_SS);
2701
2702 vmcs_write16(GUEST_TR_SELECTOR, 0);
2703 vmcs_writel(GUEST_TR_BASE, 0);
2704 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2705 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2706
2707 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2708 vmcs_writel(GUEST_LDTR_BASE, 0);
2709 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2710 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2711
2712 vmcs_write32(GUEST_SYSENTER_CS, 0);
2713 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2714 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2715
2716 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2717 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2718 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2719 else
5fdbf976
MT		 2720 kvm_rip_write(vcpu, 0);
2721 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2722
e00c8cf2
AK		 2723 vmcs_writel(GUEST_DR7, 0x400);
2724
2725 vmcs_writel(GUEST_GDTR_BASE, 0);
2726 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2727
2728 vmcs_writel(GUEST_IDTR_BASE, 0);
2729 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2730
2731 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2732 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2733 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2734
e00c8cf2
AK		 2735 /* Special registers */
2736 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2737
2738 setup_msrs(vmx);
2739
6aa8b732
AK		 2740 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2741
f78e0e2e
SY		 2742 if (cpu_has_vmx_tpr_shadow()) {
2743 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2744 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2745 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2746 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2747 vmcs_write32(TPR_THRESHOLD, 0);
2748 }
2749
2750 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2751 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2752 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2753
2384d2b3
SY		 2754 if (vmx->vpid != 0)
2755 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2756
fa40052c 2757 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2758 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2759 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2760 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2761 vmx_fpu_activate(&vmx->vcpu);
2762 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2763
b9d762fa 2764 vpid_sync_context(vmx);
2384d2b3 2765
3200f405 2766 ret = 0;
6aa8b732 2767
a89a8fb9
MG		 2768 /* HACK: Don't enable emulation on guest boot/reset */
2769 vmx->emulation_required = 0;
2770
6aa8b732
AK		 2771out:
2772 return ret;
2773}
2774
3b86cd99
JK		 2775static void enable_irq_window(struct kvm_vcpu *vcpu)
2776{
2777 u32 cpu_based_vm_exec_control;
2778
2779 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2780 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2781 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2782}
2783
2784static void enable_nmi_window(struct kvm_vcpu *vcpu)
2785{
2786 u32 cpu_based_vm_exec_control;
2787
2788 if (!cpu_has_virtual_nmis()) {
2789 enable_irq_window(vcpu);
2790 return;
2791 }
2792
30bd0c4c
AK		 2793 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2794 enable_irq_window(vcpu);
2795 return;
2796 }
3b86cd99
JK		 2797 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2798 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2799 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2800}
2801
66fd3f7f 2802static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2803{
9c8cba37 2804 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2805 uint32_t intr;
2806 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2807
229456fc 2808 trace_kvm_inj_virq(irq);
2714d1d3 2809
fa89a817 2810 ++vcpu->stat.irq_injections;
7ffd92c5 2811 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2812 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2813 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 2814 return;
2815 }
66fd3f7f
GN		 2816 intr = irq | INTR_INFO_VALID_MASK;
2817 if (vcpu->arch.interrupt.soft) {
2818 intr |= INTR_TYPE_SOFT_INTR;
2819 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2820 vmx->vcpu.arch.event_exit_inst_len);
2821 } else
2822 intr |= INTR_TYPE_EXT_INTR;
2823 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2824}
2825
f08864b4
SY		 2826static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2827{
66a5a347
JK		 2828 struct vcpu_vmx *vmx = to_vmx(vcpu);
2829
3b86cd99
JK		 2830 if (!cpu_has_virtual_nmis()) {
2831 /*
2832 * Tracking the NMI-blocked state in software is built upon
2833 * finding the next open IRQ window. This, in turn, depends on
2834 * well-behaving guests: They have to keep IRQs disabled at
2835 * least as long as the NMI handler runs. Otherwise we may
2836 * cause NMI nesting, maybe breaking the guest. But as this is
2837 * highly unlikely, we can live with the residual risk.
2838 */
2839 vmx->soft_vnmi_blocked = 1;
2840 vmx->vnmi_blocked_time = 0;
2841 }
2842
487b391d 2843 ++vcpu->stat.nmi_injections;
7ffd92c5 2844 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2845 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2846 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 2847 return;
2848 }
f08864b4
SY		 2849 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2850 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2851}
2852
c4282df9 2853static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2854{
3b86cd99 2855 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2856 return 0;
33f089ca 2857
c4282df9 2858 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 2859 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2860 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2861}
2862
3cfc3092
JK		 2863static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2864{
2865 if (!cpu_has_virtual_nmis())
2866 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2867 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2868}
2869
2870static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2871{
2872 struct vcpu_vmx *vmx = to_vmx(vcpu);
2873
2874 if (!cpu_has_virtual_nmis()) {
2875 if (vmx->soft_vnmi_blocked != masked) {
2876 vmx->soft_vnmi_blocked = masked;
2877 vmx->vnmi_blocked_time = 0;
2878 }
2879 } else {
2880 if (masked)
2881 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2882 GUEST_INTR_STATE_NMI);
2883 else
2884 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2885 GUEST_INTR_STATE_NMI);
2886 }
2887}
2888
78646121
GN		 2889static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2890{
c4282df9
GN		 2891 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2892 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2893 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2894}
2895
cbc94022
IE		 2896static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2897{
2898 int ret;
2899 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2900 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2901 .guest_phys_addr = addr,
2902 .memory_size = PAGE_SIZE * 3,
2903 .flags = 0,
2904 };
2905
2906 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2907 if (ret)
2908 return ret;
bfc6d222 2909 kvm->arch.tss_addr = addr;
cbc94022
IE		 2910 return 0;
2911}
2912
6aa8b732
AK		 2913static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2914 int vec, u32 err_code)
2915{
b3f37707
NK		 2916 /*
2917 * Instruction with address size override prefix opcode 0x67
2918 * Cause the #SS fault with 0 error code in VM86 mode.
2919 */
2920 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2921 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2922 return 1;
77ab6db0
JK		 2923 /*
2924 * Forward all other exceptions that are valid in real mode.
2925 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2926 * the required debugging infrastructure rework.
2927 */
2928 switch (vec) {
77ab6db0 2929 case DB_VECTOR:
d0bfb940
JK		 2930 if (vcpu->guest_debug &
2931 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2932 return 0;
2933 kvm_queue_exception(vcpu, vec);
2934 return 1;
77ab6db0 2935 case BP_VECTOR:
c573cd22
JK		 2936 /*
2937 * Update instruction length as we may reinject the exception
2938 * from user space while in guest debugging mode.
2939 */
2940 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2941 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2942 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2943 return 0;
2944 /* fall through */
2945 case DE_VECTOR:
77ab6db0
JK		 2946 case OF_VECTOR:
2947 case BR_VECTOR:
2948 case UD_VECTOR:
2949 case DF_VECTOR:
2950 case SS_VECTOR:
2951 case GP_VECTOR:
2952 case MF_VECTOR:
2953 kvm_queue_exception(vcpu, vec);
2954 return 1;
2955 }
6aa8b732
AK		 2956 return 0;
2957}
2958
a0861c02
AK		 2959/*
2960 * Trigger machine check on the host. We assume all the MSRs are already set up
2961 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2962 * We pass a fake environment to the machine check handler because we want
2963 * the guest to be always treated like user space, no matter what context
2964 * it used internally.
2965 */
2966static void kvm_machine_check(void)
2967{
2968#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2969 struct pt_regs regs = {
2970 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2971 .flags = X86_EFLAGS_IF,
2972 };
2973
2974 do_machine_check(&regs, 0);
2975#endif
2976}
2977
851ba692 2978static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2979{
2980 /* already handled by vcpu_run */
2981 return 1;
2982}
2983
851ba692 2984static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2985{
1155f76a 2986 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2987 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2988 u32 intr_info, ex_no, error_code;
42dbaa5a 2989 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2990 u32 vect_info;
2991 enum emulation_result er;
2992
1155f76a 2993 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2994 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2995
a0861c02 2996 if (is_machine_check(intr_info))
851ba692 2997 return handle_machine_check(vcpu);
a0861c02 2998
6aa8b732 2999 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3000 !is_page_fault(intr_info)) {
3001 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3002 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3003 vcpu->run->internal.ndata = 2;
3004 vcpu->run->internal.data[0] = vect_info;
3005 vcpu->run->internal.data[1] = intr_info;
3006 return 0;
3007 }
6aa8b732 3008
e4a41889 3009 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3010 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3011
3012 if (is_no_device(intr_info)) {
5fd86fcf 3013 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3014 return 1;
3015 }
3016
7aa81cc0 3017 if (is_invalid_opcode(intr_info)) {
851ba692 3018 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 3019 if (er != EMULATE_DONE)
7ee5d940 3020 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3021 return 1;
3022 }
3023
6aa8b732 3024 error_code = 0;
5fdbf976 3025 rip = kvm_rip_read(vcpu);
2e11384c 3026 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3027 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3028 if (is_page_fault(intr_info)) {
1439442c 3029 /* EPT won't cause page fault directly */
089d034e 3030 if (enable_ept)
1439442c 3031 BUG();
6aa8b732 3032 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3033 trace_kvm_page_fault(cr2, error_code);
3034
3298b75c 3035 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3036 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 3037 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 3038 }
3039
7ffd92c5 3040 if (vmx->rmode.vm86_active &&
6aa8b732 3041 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3042 error_code)) {
ad312c7c
ZX		 3043 if (vcpu->arch.halt_request) {
3044 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3045 return kvm_emulate_halt(vcpu);
3046 }
6aa8b732 3047 return 1;
72d6e5a0 3048 }
6aa8b732 3049
d0bfb940 3050 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3051 switch (ex_no) {
3052 case DB_VECTOR:
3053 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3054 if (!(vcpu->guest_debug &
3055 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3056 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3057 kvm_queue_exception(vcpu, DB_VECTOR);
3058 return 1;
3059 }
3060 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3061 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3062 /* fall through */
3063 case BP_VECTOR:
c573cd22
JK		 3064 /*
3065 * Update instruction length as we may reinject #BP from
3066 * user space while in guest debugging mode. Reading it for
3067 * #DB as well causes no harm, it is not used in that case.
3068 */
3069 vmx->vcpu.arch.event_exit_inst_len =
3070 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3071 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3072 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3073 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3074 break;
3075 default:
d0bfb940
JK		 3076 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3077 kvm_run->ex.exception = ex_no;
3078 kvm_run->ex.error_code = error_code;
42dbaa5a 3079 break;
6aa8b732 3080 }
6aa8b732
AK		 3081 return 0;
3082}
3083
851ba692 3084static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3085{
1165f5fe 3086 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3087 return 1;
3088}
3089
851ba692 3090static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3091{
851ba692 3092 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3093 return 0;
3094}
6aa8b732 3095
851ba692 3096static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3097{
bfdaab09 3098 unsigned long exit_qualification;
34c33d16 3099 int size, in, string;
039576c0 3100 unsigned port;
6aa8b732 3101
bfdaab09 3102 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3103 string = (exit_qualification & 16) != 0;
cf8f70bf 3104 in = (exit_qualification & 8) != 0;
e70669ab 3105
cf8f70bf 3106 ++vcpu->stat.io_exits;
e70669ab 3107
cf8f70bf 3108 if (string || in)
6d77dbfc 3109 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
e70669ab 3110
cf8f70bf
GN		 3111 port = exit_qualification >> 16;
3112 size = (exit_qualification & 7) + 1;
e93f36bc 3113 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3114
3115 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3116}
3117
102d8325
IM		 3118static void
3119vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3120{
3121 /*
3122 * Patch in the VMCALL instruction:
3123 */
3124 hypercall[0] = 0x0f;
3125 hypercall[1] = 0x01;
3126 hypercall[2] = 0xc1;
102d8325
IM		 3127}
3128
49a9b07e
AK		 3129static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3130{
3131 if (err)
3132 kvm_inject_gp(vcpu, 0);
3133 else
3134 skip_emulated_instruction(vcpu);
3135}
3136
851ba692 3137static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3138{
229456fc 3139 unsigned long exit_qualification, val;
6aa8b732
AK		 3140 int cr;
3141 int reg;
49a9b07e 3142 int err;
6aa8b732 3143
bfdaab09 3144 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3145 cr = exit_qualification & 15;
3146 reg = (exit_qualification >> 8) & 15;
3147 switch ((exit_qualification >> 4) & 3) {
3148 case 0: /* mov to cr */
229456fc
MT		 3149 val = kvm_register_read(vcpu, reg);
3150 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3151 switch (cr) {
3152 case 0:
49a9b07e
AK		 3153 err = kvm_set_cr0(vcpu, val);
3154 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3155 return 1;
3156 case 3:
2390218b
AK		 3157 err = kvm_set_cr3(vcpu, val);
3158 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3159 return 1;
3160 case 4:
a83b29c6
AK		 3161 err = kvm_set_cr4(vcpu, val);
3162 complete_insn_gp(vcpu, err);
6aa8b732 3163 return 1;
0a5fff19
GN		 3164 case 8: {
3165 u8 cr8_prev = kvm_get_cr8(vcpu);
3166 u8 cr8 = kvm_register_read(vcpu, reg);
3167 kvm_set_cr8(vcpu, cr8);
3168 skip_emulated_instruction(vcpu);
3169 if (irqchip_in_kernel(vcpu->kvm))
3170 return 1;
3171 if (cr8_prev <= cr8)
3172 return 1;
851ba692 3173 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3174 return 0;
3175 }
6aa8b732
AK		 3176 };
3177 break;
25c4c276 3178 case 2: /* clts */
edcafe3c 3179 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3180 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3181 skip_emulated_instruction(vcpu);
6b52d186 3182 vmx_fpu_activate(vcpu);
25c4c276 3183 return 1;
6aa8b732
AK		 3184 case 1: /*mov from cr*/
3185 switch (cr) {
3186 case 3:
5fdbf976 3187 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3188 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3189 skip_emulated_instruction(vcpu);
3190 return 1;
3191 case 8:
229456fc
MT		 3192 val = kvm_get_cr8(vcpu);
3193 kvm_register_write(vcpu, reg, val);
3194 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3195 skip_emulated_instruction(vcpu);
3196 return 1;
3197 }
3198 break;
3199 case 3: /* lmsw */
a1f83a74 3200 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3201 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3202 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3203
3204 skip_emulated_instruction(vcpu);
3205 return 1;
3206 default:
3207 break;
3208 }
851ba692 3209 vcpu->run->exit_reason = 0;
f0242478 3210 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3211 (int)(exit_qualification >> 4) & 3, cr);
3212 return 0;
3213}
3214
851ba692 3215static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3216{
bfdaab09 3217 unsigned long exit_qualification;
6aa8b732
AK		 3218 int dr, reg;
3219
f2483415 3220 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3221 if (!kvm_require_cpl(vcpu, 0))
3222 return 1;
42dbaa5a
JK		 3223 dr = vmcs_readl(GUEST_DR7);
3224 if (dr & DR7_GD) {
3225 /*
3226 * As the vm-exit takes precedence over the debug trap, we
3227 * need to emulate the latter, either for the host or the
3228 * guest debugging itself.
3229 */
3230 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3231 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3232 vcpu->run->debug.arch.dr7 = dr;
3233 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3234 vmcs_readl(GUEST_CS_BASE) +
3235 vmcs_readl(GUEST_RIP);
851ba692
AK		 3236 vcpu->run->debug.arch.exception = DB_VECTOR;
3237 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3238 return 0;
3239 } else {
3240 vcpu->arch.dr7 &= ~DR7_GD;
3241 vcpu->arch.dr6 |= DR6_BD;
3242 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3243 kvm_queue_exception(vcpu, DB_VECTOR);
3244 return 1;
3245 }
3246 }
3247
bfdaab09 3248 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3249 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3250 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3251 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3252 unsigned long val;
3253 if (!kvm_get_dr(vcpu, dr, &val))
3254 kvm_register_write(vcpu, reg, val);
3255 } else
3256 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3257 skip_emulated_instruction(vcpu);
3258 return 1;
3259}
3260
020df079
GN		 3261static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3262{
3263 vmcs_writel(GUEST_DR7, val);
3264}
3265
851ba692 3266static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3267{
06465c5a
AK		 3268 kvm_emulate_cpuid(vcpu);
3269 return 1;
6aa8b732
AK		 3270}
3271
851ba692 3272static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3273{
ad312c7c 3274 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3275 u64 data;
3276
3277 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3278 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3279 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3280 return 1;
3281 }
3282
229456fc 3283 trace_kvm_msr_read(ecx, data);
2714d1d3 3284
6aa8b732 3285 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3286 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3287 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3288 skip_emulated_instruction(vcpu);
3289 return 1;
3290}
3291
851ba692 3292static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3293{
ad312c7c
ZX		 3294 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3295 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3296 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3297
3298 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3299 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3300 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3301 return 1;
3302 }
3303
59200273 3304 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3305 skip_emulated_instruction(vcpu);
3306 return 1;
3307}
3308
851ba692 3309static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 3310{
3842d135 3311 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 3312 return 1;
3313}
3314
851ba692 3315static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3316{
85f455f7
ED		 3317 u32 cpu_based_vm_exec_control;
3318
3319 /* clear pending irq */
3320 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3321 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3322 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3323
3842d135
AK		 3324 kvm_make_request(KVM_REQ_EVENT, vcpu);
3325
a26bf12a 3326 ++vcpu->stat.irq_window_exits;
2714d1d3 3327
c1150d8c
DL		 3328 /*
3329 * If the user space waits to inject interrupts, exit as soon as
3330 * possible
3331 */
8061823a 3332 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3333 vcpu->run->request_interrupt_window &&
8061823a 3334 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3335 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3336 return 0;
3337 }
6aa8b732
AK		 3338 return 1;
3339}
3340
851ba692 3341static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3342{
3343 skip_emulated_instruction(vcpu);
d3bef15f 3344 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3345}
3346
851ba692 3347static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3348{
510043da 3349 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3350 kvm_emulate_hypercall(vcpu);
3351 return 1;
c21415e8
IM		 3352}
3353
851ba692 3354static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3355{
3356 kvm_queue_exception(vcpu, UD_VECTOR);
3357 return 1;
3358}
3359
ec25d5e6
GN		 3360static int handle_invd(struct kvm_vcpu *vcpu)
3361{
3362 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3363}
3364
851ba692 3365static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3366{
f9c617f6 3367 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3368
3369 kvm_mmu_invlpg(vcpu, exit_qualification);
3370 skip_emulated_instruction(vcpu);
3371 return 1;
3372}
3373
851ba692 3374static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3375{
3376 skip_emulated_instruction(vcpu);
f5f48ee1 3377 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3378 return 1;
3379}
3380
2acf923e
DC		 3381static int handle_xsetbv(struct kvm_vcpu *vcpu)
3382{
3383 u64 new_bv = kvm_read_edx_eax(vcpu);
3384 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3385
3386 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3387 skip_emulated_instruction(vcpu);
3388 return 1;
3389}
3390
851ba692 3391static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3392{
6d77dbfc 3393 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
f78e0e2e
SY		 3394}
3395
851ba692 3396static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3397{
60637aac 3398 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3399 unsigned long exit_qualification;
e269fb21
JK		 3400 bool has_error_code = false;
3401 u32 error_code = 0;
37817f29 3402 u16 tss_selector;
64a7ec06
GN		 3403 int reason, type, idt_v;
3404
3405 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3406 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3407
3408 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3409
3410 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3411 if (reason == TASK_SWITCH_GATE && idt_v) {
3412 switch (type) {
3413 case INTR_TYPE_NMI_INTR:
3414 vcpu->arch.nmi_injected = false;
3415 if (cpu_has_virtual_nmis())
3416 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3417 GUEST_INTR_STATE_NMI);
3418 break;
3419 case INTR_TYPE_EXT_INTR:
66fd3f7f 3420 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3421 kvm_clear_interrupt_queue(vcpu);
3422 break;
3423 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3424 if (vmx->idt_vectoring_info &
3425 VECTORING_INFO_DELIVER_CODE_MASK) {
3426 has_error_code = true;
3427 error_code =
3428 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3429 }
3430 /* fall through */
64a7ec06
GN		 3431 case INTR_TYPE_SOFT_EXCEPTION:
3432 kvm_clear_exception_queue(vcpu);
3433 break;
3434 default:
3435 break;
3436 }
60637aac 3437 }
37817f29
IE		 3438 tss_selector = exit_qualification;
3439
64a7ec06
GN		 3440 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3441 type != INTR_TYPE_EXT_INTR &&
3442 type != INTR_TYPE_NMI_INTR))
3443 skip_emulated_instruction(vcpu);
3444
acb54517
GN		 3445 if (kvm_task_switch(vcpu, tss_selector, reason,
3446 has_error_code, error_code) == EMULATE_FAIL) {
3447 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3448 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3449 vcpu->run->internal.ndata = 0;
42dbaa5a 3450 return 0;
acb54517 3451 }
42dbaa5a
JK		 3452
3453 /* clear all local breakpoint enable flags */
3454 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3455
3456 /*
3457 * TODO: What about debug traps on tss switch?
3458 * Are we supposed to inject them and update dr6?
3459 */
3460
3461 return 1;
37817f29
IE		 3462}
3463
851ba692 3464static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3465{
f9c617f6 3466 unsigned long exit_qualification;
1439442c 3467 gpa_t gpa;
1439442c 3468 int gla_validity;
1439442c 3469
f9c617f6 3470 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3471
3472 if (exit_qualification & (1 << 6)) {
3473 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3474 return -EINVAL;
1439442c
SY		 3475 }
3476
3477 gla_validity = (exit_qualification >> 7) & 0x3;
3478 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3479 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3480 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3481 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3482 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3483 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3484 (long unsigned int)exit_qualification);
851ba692
AK		 3485 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3486 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3487 return 0;
1439442c
SY		 3488 }
3489
3490 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3491 trace_kvm_page_fault(gpa, exit_qualification);
ff1fcb9e 3492 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3);
1439442c
SY		 3493}
3494
68f89400
MT		 3495static u64 ept_rsvd_mask(u64 spte, int level)
3496{
3497 int i;
3498 u64 mask = 0;
3499
3500 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3501 mask |= (1ULL << i);
3502
3503 if (level > 2)
3504 /* bits 7:3 reserved */
3505 mask |= 0xf8;
3506 else if (level == 2) {
3507 if (spte & (1ULL << 7))
3508 /* 2MB ref, bits 20:12 reserved */
3509 mask |= 0x1ff000;
3510 else
3511 /* bits 6:3 reserved */
3512 mask |= 0x78;
3513 }
3514
3515 return mask;
3516}
3517
3518static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3519 int level)
3520{
3521 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3522
3523 /* 010b (write-only) */
3524 WARN_ON((spte & 0x7) == 0x2);
3525
3526 /* 110b (write/execute) */
3527 WARN_ON((spte & 0x7) == 0x6);
3528
3529 /* 100b (execute-only) and value not supported by logical processor */
3530 if (!cpu_has_vmx_ept_execute_only())
3531 WARN_ON((spte & 0x7) == 0x4);
3532
3533 /* not 000b */
3534 if ((spte & 0x7)) {
3535 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3536
3537 if (rsvd_bits != 0) {
3538 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3539 __func__, rsvd_bits);
3540 WARN_ON(1);
3541 }
3542
3543 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3544 u64 ept_mem_type = (spte & 0x38) >> 3;
3545
3546 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3547 ept_mem_type == 7) {
3548 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3549 __func__, ept_mem_type);
3550 WARN_ON(1);
3551 }
3552 }
3553 }
3554}
3555
851ba692 3556static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3557{
3558 u64 sptes[4];
3559 int nr_sptes, i;
3560 gpa_t gpa;
3561
3562 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3563
3564 printk(KERN_ERR "EPT: Misconfiguration.\n");
3565 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3566
3567 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3568
3569 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3570 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3571
851ba692
AK		 3572 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3573 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3574
3575 return 0;
3576}
3577
851ba692 3578static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3579{
3580 u32 cpu_based_vm_exec_control;
3581
3582 /* clear pending NMI */
3583 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3584 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3585 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3586 ++vcpu->stat.nmi_window_exits;
3842d135 3587 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 3588
3589 return 1;
3590}
3591
80ced186 3592static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3593{
8b3079a5
AK		 3594 struct vcpu_vmx *vmx = to_vmx(vcpu);
3595 enum emulation_result err = EMULATE_DONE;
80ced186 3596 int ret = 1;
49e9d557
AK		 3597 u32 cpu_exec_ctrl;
3598 bool intr_window_requested;
3599
3600 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3601 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 3602
3603 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 3604 if (intr_window_requested
3605 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3606 return handle_interrupt_window(&vmx->vcpu);
3607
851ba692 3608 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3609
80ced186
MG		 3610 if (err == EMULATE_DO_MMIO) {
3611 ret = 0;
3612 goto out;
3613 }
1d5a4d9b 3614
6d77dbfc
GN		 3615 if (err != EMULATE_DONE)
3616 return 0;
ea953ef0
MG		 3617
3618 if (signal_pending(current))
80ced186 3619 goto out;
ea953ef0
MG		 3620 if (need_resched())
3621 schedule();
3622 }
3623
80ced186
MG		 3624 vmx->emulation_required = 0;
3625out:
3626 return ret;
ea953ef0
MG		 3627}
3628
4b8d54f9
ZE		 3629/*
3630 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3631 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3632 */
9fb41ba8 3633static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3634{
3635 skip_emulated_instruction(vcpu);
3636 kvm_vcpu_on_spin(vcpu);
3637
3638 return 1;
3639}
3640
59708670
SY		 3641static int handle_invalid_op(struct kvm_vcpu *vcpu)
3642{
3643 kvm_queue_exception(vcpu, UD_VECTOR);
3644 return 1;
3645}
3646
6aa8b732
AK		 3647/*
3648 * The exit handlers return 1 if the exit was handled fully and guest execution
3649 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3650 * to be done to userspace and return 0.
3651 */
851ba692 3652static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3653 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3654 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3655 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3656 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3657 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3658 [EXIT_REASON_CR_ACCESS] = handle_cr,
3659 [EXIT_REASON_DR_ACCESS] = handle_dr,
3660 [EXIT_REASON_CPUID] = handle_cpuid,
3661 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3662 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3663 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3664 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 3665 [EXIT_REASON_INVD] = handle_invd,
a7052897 3666 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3667 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3668 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3669 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3670 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3671 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3672 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3673 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3674 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3675 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3676 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3677 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3678 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3679 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3680 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3681 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3682 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3683 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3684 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3685 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3686 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3687 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3688};
3689
3690static const int kvm_vmx_max_exit_handlers =
50a3485c 3691 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 3692
586f9607
AK		 3693static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3694{
3695 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3696 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3697}
3698
6aa8b732
AK		 3699/*
3700 * The guest has exited. See if we can fix it or if we need userspace
3701 * assistance.
3702 */
851ba692 3703static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3704{
29bd8a78 3705 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3706 u32 exit_reason = vmx->exit_reason;
1155f76a 3707 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3708
aa17911e 3709 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 3710
80ced186
MG		 3711 /* If guest state is invalid, start emulating */
3712 if (vmx->emulation_required && emulate_invalid_guest_state)
3713 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3714
1439442c
SY		 3715 /* Access CR3 don't cause VMExit in paging mode, so we need
3716 * to sync with guest real CR3. */
6de4f3ad 3717 if (enable_ept && is_paging(vcpu))
1439442c 3718 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3719
5120702e
MG		 3720 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3721 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3722 vcpu->run->fail_entry.hardware_entry_failure_reason
3723 = exit_reason;
3724 return 0;
3725 }
3726
29bd8a78 3727 if (unlikely(vmx->fail)) {
851ba692
AK		 3728 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3729 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3730 = vmcs_read32(VM_INSTRUCTION_ERROR);
3731 return 0;
3732 }
6aa8b732 3733
d77c26fc 3734 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3735 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3736 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3737 exit_reason != EXIT_REASON_TASK_SWITCH))
3738 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3739 "(0x%x) and exit reason is 0x%x\n",
3740 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3741
3742 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3743 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3744 vmx->soft_vnmi_blocked = 0;
3b86cd99 3745 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3746 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3747 /*
3748 * This CPU don't support us in finding the end of an
3749 * NMI-blocked window if the guest runs with IRQs
3750 * disabled. So we pull the trigger after 1 s of
3751 * futile waiting, but inform the user about this.
3752 */
3753 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3754 "state on VCPU %d after 1 s timeout\n",
3755 __func__, vcpu->vcpu_id);
3756 vmx->soft_vnmi_blocked = 0;
3b86cd99 3757 }
3b86cd99
JK		 3758 }
3759
6aa8b732
AK		 3760 if (exit_reason < kvm_vmx_max_exit_handlers
3761 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3762 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3763 else {
851ba692
AK		 3764 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3765 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3766 }
3767 return 0;
3768}
3769
95ba8273 3770static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3771{
95ba8273 3772 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3773 vmcs_write32(TPR_THRESHOLD, 0);
3774 return;
3775 }
3776
95ba8273 3777 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3778}
3779
51aa01d1 3780static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 3781{
51aa01d1 3782 u32 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 3783
3784 /* Handle machine checks before interrupts are enabled */
3785 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3786 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3787 && is_machine_check(exit_intr_info)))
3788 kvm_machine_check();
3789
20f65983
GN		 3790 /* We need to handle NMIs before interrupts are enabled */
3791 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3792 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3793 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3794 asm("int $2");
ff9d07a0
ZY		 3795 kvm_after_handle_nmi(&vmx->vcpu);
3796 }
51aa01d1 3797}
20f65983 3798
51aa01d1
AK		 3799static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3800{
3801 u32 exit_intr_info = vmx->exit_intr_info;
3802 bool unblock_nmi;
3803 u8 vector;
3804 bool idtv_info_valid;
3805
3806 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 3807
cf393f75
AK		 3808 if (cpu_has_virtual_nmis()) {
3809 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3810 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3811 /*
7b4a25cb 3812 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3813 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3814 * a guest IRET fault.
7b4a25cb
GN		 3815 * SDM 3: 23.2.2 (September 2008)
3816 * Bit 12 is undefined in any of the following cases:
3817 * If the VM exit sets the valid bit in the IDT-vectoring
3818 * information field.
3819 * If the VM exit is due to a double fault.
cf393f75 3820 */
7b4a25cb
GN		 3821 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3822 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3823 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3824 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3825 } else if (unlikely(vmx->soft_vnmi_blocked))
3826 vmx->vnmi_blocked_time +=
3827 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 3828}
3829
83422e17
AK		 3830static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3831 u32 idt_vectoring_info,
3832 int instr_len_field,
3833 int error_code_field)
51aa01d1 3834{
51aa01d1
AK		 3835 u8 vector;
3836 int type;
3837 bool idtv_info_valid;
3838
3839 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 3840
37b96e98
GN		 3841 vmx->vcpu.arch.nmi_injected = false;
3842 kvm_clear_exception_queue(&vmx->vcpu);
3843 kvm_clear_interrupt_queue(&vmx->vcpu);
3844
3845 if (!idtv_info_valid)
3846 return;
3847
3842d135
AK		 3848 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3849
668f612f
AK		 3850 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3851 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3852
64a7ec06 3853 switch (type) {
37b96e98
GN		 3854 case INTR_TYPE_NMI_INTR:
3855 vmx->vcpu.arch.nmi_injected = true;
668f612f 3856 /*
7b4a25cb 3857 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3858 * Clear bit "block by NMI" before VM entry if a NMI
3859 * delivery faulted.
668f612f 3860 */
37b96e98
GN		 3861 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3862 GUEST_INTR_STATE_NMI);
3863 break;
37b96e98 3864 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 3865 vmx->vcpu.arch.event_exit_inst_len =
83422e17 3866 vmcs_read32(instr_len_field);
66fd3f7f
GN		 3867 /* fall through */
3868 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3869 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 3870 u32 err = vmcs_read32(error_code_field);
37b96e98 3871 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3872 } else
3873 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3874 break;
66fd3f7f
GN		 3875 case INTR_TYPE_SOFT_INTR:
3876 vmx->vcpu.arch.event_exit_inst_len =
83422e17 3877 vmcs_read32(instr_len_field);
66fd3f7f 3878 /* fall through */
37b96e98 3879 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3880 kvm_queue_interrupt(&vmx->vcpu, vector,
3881 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3882 break;
3883 default:
3884 break;
f7d9238f 3885 }
cf393f75
AK		 3886}
3887
83422e17
AK		 3888static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3889{
3890 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3891 VM_EXIT_INSTRUCTION_LEN,
3892 IDT_VECTORING_ERROR_CODE);
3893}
3894
b463a6f7
AK		 3895static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3896{
3897 __vmx_complete_interrupts(to_vmx(vcpu),
3898 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3899 VM_ENTRY_INSTRUCTION_LEN,
3900 VM_ENTRY_EXCEPTION_ERROR_CODE);
3901
3902 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3903}
3904
c801949d
AK		 3905#ifdef CONFIG_X86_64
3906#define R "r"
3907#define Q "q"
3908#else
3909#define R "e"
3910#define Q "l"
3911#endif
3912
104f226b 3913static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3914{
a2fa3e9f 3915 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b
AK		 3916
3917 /* Record the guest's net vcpu time for enforced NMI injections. */
3918 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3919 vmx->entry_time = ktime_get();
3920
3921 /* Don't enter VMX if guest state is invalid, let the exit handler
3922 start emulation until we arrive back to a valid state */
3923 if (vmx->emulation_required && emulate_invalid_guest_state)
3924 return;
3925
3926 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3927 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3928 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3929 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3930
3931 /* When single-stepping over STI and MOV SS, we must clear the
3932 * corresponding interruptibility bits in the guest state. Otherwise
3933 * vmentry fails as it then expects bit 14 (BS) in pending debug
3934 * exceptions being set, but that's not correct for the guest debugging
3935 * case. */
3936 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3937 vmx_set_interrupt_shadow(vcpu, 0);
3938
3939 asm(
6aa8b732 3940 /* Store host registers */
c801949d
AK		 3941 "push %%"R"dx; push %%"R"bp;"
3942 "push %%"R"cx \n\t"
313dbd49
AK		 3943 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3944 "je 1f \n\t"
3945 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3946 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3947 "1: \n\t"
d3edefc0
AK		 3948 /* Reload cr2 if changed */
3949 "mov %c[cr2](%0), %%"R"ax \n\t"
3950 "mov %%cr2, %%"R"dx \n\t"
3951 "cmp %%"R"ax, %%"R"dx \n\t"
3952 "je 2f \n\t"
3953 "mov %%"R"ax, %%cr2 \n\t"
3954 "2: \n\t"
6aa8b732 3955 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3956 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3957 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3958 "mov %c[rax](%0), %%"R"ax \n\t"
3959 "mov %c[rbx](%0), %%"R"bx \n\t"
3960 "mov %c[rdx](%0), %%"R"dx \n\t"
3961 "mov %c[rsi](%0), %%"R"si \n\t"
3962 "mov %c[rdi](%0), %%"R"di \n\t"
3963 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3964#ifdef CONFIG_X86_64
e08aa78a
AK		 3965 "mov %c[r8](%0), %%r8 \n\t"
3966 "mov %c[r9](%0), %%r9 \n\t"
3967 "mov %c[r10](%0), %%r10 \n\t"
3968 "mov %c[r11](%0), %%r11 \n\t"
3969 "mov %c[r12](%0), %%r12 \n\t"
3970 "mov %c[r13](%0), %%r13 \n\t"
3971 "mov %c[r14](%0), %%r14 \n\t"
3972 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3973#endif
c801949d
AK		 3974 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3975
6aa8b732 3976 /* Enter guest mode */
cd2276a7 3977 "jne .Llaunched \n\t"
4ecac3fd 3978 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3979 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3980 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3981 ".Lkvm_vmx_return: "
6aa8b732 3982 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3983 "xchg %0, (%%"R"sp) \n\t"
3984 "mov %%"R"ax, %c[rax](%0) \n\t"
3985 "mov %%"R"bx, %c[rbx](%0) \n\t"
3986 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3987 "mov %%"R"dx, %c[rdx](%0) \n\t"
3988 "mov %%"R"si, %c[rsi](%0) \n\t"
3989 "mov %%"R"di, %c[rdi](%0) \n\t"
3990 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3991#ifdef CONFIG_X86_64
e08aa78a
AK		 3992 "mov %%r8, %c[r8](%0) \n\t"
3993 "mov %%r9, %c[r9](%0) \n\t"
3994 "mov %%r10, %c[r10](%0) \n\t"
3995 "mov %%r11, %c[r11](%0) \n\t"
3996 "mov %%r12, %c[r12](%0) \n\t"
3997 "mov %%r13, %c[r13](%0) \n\t"
3998 "mov %%r14, %c[r14](%0) \n\t"
3999 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 4000#endif
c801949d
AK		 4001 "mov %%cr2, %%"R"ax \n\t"
4002 "mov %%"R"ax, %c[cr2](%0) \n\t"
4003
4004 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 4005 "setbe %c[fail](%0) \n\t"
4006 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4007 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4008 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 4009 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 4010 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4011 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4012 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4013 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4014 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4015 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4016 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4017#ifdef CONFIG_X86_64
ad312c7c
ZX		 4018 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4019 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4020 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4021 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4022 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4023 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4024 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4025 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4026#endif
ad312c7c 4027 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 4028 : "cc", "memory"
07d6f555 4029 , R"ax", R"bx", R"di", R"si"
c2036300 4030#ifdef CONFIG_X86_64
c2036300
LV		 4031 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4032#endif
4033 );
6aa8b732 4034
6de4f3ad
AK		 4035 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4036 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 4037 vcpu->arch.regs_dirty = 0;
4038
1155f76a
AK		 4039 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4040
d77c26fc 4041 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4042 vmx->launched = 1;
1b6269db 4043
51aa01d1
AK		 4044 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4045 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4046
4047 vmx_complete_atomic_exit(vmx);
4048 vmx_recover_nmi_blocking(vmx);
cf393f75 4049 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4050}
4051
c801949d
AK		 4052#undef R
4053#undef Q
4054
6aa8b732
AK		 4055static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4056{
a2fa3e9f
GH		 4057 struct vcpu_vmx *vmx = to_vmx(vcpu);
4058
4059 if (vmx->vmcs) {
543e4243 4060 vcpu_clear(vmx);
a2fa3e9f
GH		 4061 free_vmcs(vmx->vmcs);
4062 vmx->vmcs = NULL;
6aa8b732
AK		 4063 }
4064}
4065
4066static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4067{
fb3f0f51
RR		 4068 struct vcpu_vmx *vmx = to_vmx(vcpu);
4069
cdbecfc3 4070 free_vpid(vmx);
6aa8b732 4071 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4072 kfree(vmx->guest_msrs);
4073 kvm_vcpu_uninit(vcpu);
a4770347 4074 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4075}
4076
4610c9cc
DX		 4077static inline void vmcs_init(struct vmcs *vmcs)
4078{
4079 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4080
4081 if (!vmm_exclusive)
4082 kvm_cpu_vmxon(phys_addr);
4083
4084 vmcs_clear(vmcs);
4085
4086 if (!vmm_exclusive)
4087 kvm_cpu_vmxoff();
4088}
4089
fb3f0f51 4090static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4091{
fb3f0f51 4092 int err;
c16f862d 4093 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4094 int cpu;
6aa8b732 4095
a2fa3e9f 4096 if (!vmx)
fb3f0f51
RR		 4097 return ERR_PTR(-ENOMEM);
4098
2384d2b3
SY		 4099 allocate_vpid(vmx);
4100
fb3f0f51
RR		 4101 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4102 if (err)
4103 goto free_vcpu;
965b58a5 4104
a2fa3e9f 4105 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4106 if (!vmx->guest_msrs) {
4107 err = -ENOMEM;
4108 goto uninit_vcpu;
4109 }
965b58a5 4110
a2fa3e9f
GH		 4111 vmx->vmcs = alloc_vmcs();
4112 if (!vmx->vmcs)
fb3f0f51 4113 goto free_msrs;
a2fa3e9f 4114
4610c9cc 4115 vmcs_init(vmx->vmcs);
a2fa3e9f 4116
15ad7146
AK		 4117 cpu = get_cpu();
4118 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 4119 vmx->vcpu.cpu = cpu;
8b9cf98c 4120 err = vmx_vcpu_setup(vmx);
fb3f0f51 4121 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4122 put_cpu();
fb3f0f51
RR		 4123 if (err)
4124 goto free_vmcs;
5e4a0b3c
MT		 4125 if (vm_need_virtualize_apic_accesses(kvm))
4126 if (alloc_apic_access_page(kvm) != 0)
4127 goto free_vmcs;
fb3f0f51 4128
b927a3ce
SY		 4129 if (enable_ept) {
4130 if (!kvm->arch.ept_identity_map_addr)
4131 kvm->arch.ept_identity_map_addr =
4132 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4133 if (alloc_identity_pagetable(kvm) != 0)
4134 goto free_vmcs;
b927a3ce 4135 }
b7ebfb05 4136
fb3f0f51
RR		 4137 return &vmx->vcpu;
4138
4139free_vmcs:
4140 free_vmcs(vmx->vmcs);
4141free_msrs:
fb3f0f51
RR		 4142 kfree(vmx->guest_msrs);
4143uninit_vcpu:
4144 kvm_vcpu_uninit(&vmx->vcpu);
4145free_vcpu:
cdbecfc3 4146 free_vpid(vmx);
a4770347 4147 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4148 return ERR_PTR(err);
6aa8b732
AK		 4149}
4150
002c7f7c
YS		 4151static void __init vmx_check_processor_compat(void *rtn)
4152{
4153 struct vmcs_config vmcs_conf;
4154
4155 *(int *)rtn = 0;
4156 if (setup_vmcs_config(&vmcs_conf) < 0)
4157 *(int *)rtn = -EIO;
4158 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4159 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4160 smp_processor_id());
4161 *(int *)rtn = -EIO;
4162 }
4163}
4164
67253af5
SY		 4165static int get_ept_level(void)
4166{
4167 return VMX_EPT_DEFAULT_GAW + 1;
4168}
4169
4b12f0de 4170static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4171{
4b12f0de
SY		 4172 u64 ret;
4173
522c68c4
SY		 4174 /* For VT-d and EPT combination
4175 * 1. MMIO: always map as UC
4176 * 2. EPT with VT-d:
4177 * a. VT-d without snooping control feature: can't guarantee the
4178 * result, try to trust guest.
4179 * b. VT-d with snooping control feature: snooping control feature of
4180 * VT-d engine can guarantee the cache correctness. Just set it
4181 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4182 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4183 * consistent with host MTRR
4184 */
4b12f0de
SY		 4185 if (is_mmio)
4186 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4187 else if (vcpu->kvm->arch.iommu_domain &&
4188 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4189 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4190 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4191 else
522c68c4 4192 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4193 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4194
4195 return ret;
64d4d521
SY		 4196}
4197
f4c9e87c
AK		 4198#define _ER(x) { EXIT_REASON_##x, #x }
4199
229456fc 4200static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4201 _ER(EXCEPTION_NMI),
4202 _ER(EXTERNAL_INTERRUPT),
4203 _ER(TRIPLE_FAULT),
4204 _ER(PENDING_INTERRUPT),
4205 _ER(NMI_WINDOW),
4206 _ER(TASK_SWITCH),
4207 _ER(CPUID),
4208 _ER(HLT),
4209 _ER(INVLPG),
4210 _ER(RDPMC),
4211 _ER(RDTSC),
4212 _ER(VMCALL),
4213 _ER(VMCLEAR),
4214 _ER(VMLAUNCH),
4215 _ER(VMPTRLD),
4216 _ER(VMPTRST),
4217 _ER(VMREAD),
4218 _ER(VMRESUME),
4219 _ER(VMWRITE),
4220 _ER(VMOFF),
4221 _ER(VMON),
4222 _ER(CR_ACCESS),
4223 _ER(DR_ACCESS),
4224 _ER(IO_INSTRUCTION),
4225 _ER(MSR_READ),
4226 _ER(MSR_WRITE),
4227 _ER(MWAIT_INSTRUCTION),
4228 _ER(MONITOR_INSTRUCTION),
4229 _ER(PAUSE_INSTRUCTION),
4230 _ER(MCE_DURING_VMENTRY),
4231 _ER(TPR_BELOW_THRESHOLD),
4232 _ER(APIC_ACCESS),
4233 _ER(EPT_VIOLATION),
4234 _ER(EPT_MISCONFIG),
4235 _ER(WBINVD),
229456fc
MT		 4236 { -1, NULL }
4237};
4238
f4c9e87c
AK		 4239#undef _ER
4240
17cc3935 4241static int vmx_get_lpage_level(void)
344f414f 4242{
878403b7
SY		 4243 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4244 return PT_DIRECTORY_LEVEL;
4245 else
4246 /* For shadow and EPT supported 1GB page */
4247 return PT_PDPE_LEVEL;
344f414f
JR		 4248}
4249
0e851880
SY		 4250static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4251{
4e47c7a6
SY		 4252 struct kvm_cpuid_entry2 *best;
4253 struct vcpu_vmx *vmx = to_vmx(vcpu);
4254 u32 exec_control;
4255
4256 vmx->rdtscp_enabled = false;
4257 if (vmx_rdtscp_supported()) {
4258 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4259 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4260 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4261 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4262 vmx->rdtscp_enabled = true;
4263 else {
4264 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4265 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4266 exec_control);
4267 }
4268 }
4269 }
0e851880
SY		 4270}
4271
d4330ef2
JR		 4272static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4273{
4274}
4275
cbdd1bea 4276static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4277 .cpu_has_kvm_support = cpu_has_kvm_support,
4278 .disabled_by_bios = vmx_disabled_by_bios,
4279 .hardware_setup = hardware_setup,
4280 .hardware_unsetup = hardware_unsetup,
002c7f7c 4281 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4282 .hardware_enable = hardware_enable,
4283 .hardware_disable = hardware_disable,
04547156 4284 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4285
4286 .vcpu_create = vmx_create_vcpu,
4287 .vcpu_free = vmx_free_vcpu,
04d2cc77 4288 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4289
04d2cc77 4290 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4291 .vcpu_load = vmx_vcpu_load,
4292 .vcpu_put = vmx_vcpu_put,
4293
4294 .set_guest_debug = set_guest_debug,
4295 .get_msr = vmx_get_msr,
4296 .set_msr = vmx_set_msr,
4297 .get_segment_base = vmx_get_segment_base,
4298 .get_segment = vmx_get_segment,
4299 .set_segment = vmx_set_segment,
2e4d2653 4300 .get_cpl = vmx_get_cpl,
6aa8b732 4301 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4302 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4303 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4304 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4305 .set_cr3 = vmx_set_cr3,
4306 .set_cr4 = vmx_set_cr4,
6aa8b732 4307 .set_efer = vmx_set_efer,
6aa8b732
AK		 4308 .get_idt = vmx_get_idt,
4309 .set_idt = vmx_set_idt,
4310 .get_gdt = vmx_get_gdt,
4311 .set_gdt = vmx_set_gdt,
020df079 4312 .set_dr7 = vmx_set_dr7,
5fdbf976 4313 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4314 .get_rflags = vmx_get_rflags,
4315 .set_rflags = vmx_set_rflags,
ebcbab4c 4316 .fpu_activate = vmx_fpu_activate,
02daab21 4317 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4318
4319 .tlb_flush = vmx_flush_tlb,
6aa8b732 4320
6aa8b732 4321 .run = vmx_vcpu_run,
6062d012 4322 .handle_exit = vmx_handle_exit,
6aa8b732 4323 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4324 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4325 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4326 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4327 .set_irq = vmx_inject_irq,
95ba8273 4328 .set_nmi = vmx_inject_nmi,
298101da 4329 .queue_exception = vmx_queue_exception,
b463a6f7 4330 .cancel_injection = vmx_cancel_injection,
78646121 4331 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4332 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4333 .get_nmi_mask = vmx_get_nmi_mask,
4334 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4335 .enable_nmi_window = enable_nmi_window,
4336 .enable_irq_window = enable_irq_window,
4337 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4338
cbc94022 4339 .set_tss_addr = vmx_set_tss_addr,
67253af5 4340 .get_tdp_level = get_ept_level,
4b12f0de 4341 .get_mt_mask = vmx_get_mt_mask,
229456fc 4342
586f9607 4343 .get_exit_info = vmx_get_exit_info,
229456fc 4344 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 4345
17cc3935 4346 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4347
4348 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4349
4350 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4351
4352 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4353
4354 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA		 4355
4356 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 4357 .adjust_tsc_offset = vmx_adjust_tsc_offset,
1c97f0a0
JR		 4358
4359 .set_tdp_cr3 = vmx_set_cr3,
6aa8b732
AK		 4360};
4361
4362static int __init vmx_init(void)
4363{
26bb0981
AK		 4364 int r, i;
4365
4366 rdmsrl_safe(MSR_EFER, &host_efer);
4367
4368 for (i = 0; i < NR_VMX_MSR; ++i)
4369 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4370
3e7c73e9 4371 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4372 if (!vmx_io_bitmap_a)
4373 return -ENOMEM;
4374
3e7c73e9 4375 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4376 if (!vmx_io_bitmap_b) {
4377 r = -ENOMEM;
4378 goto out;
4379 }
4380
5897297b
AK		 4381 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4382 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4383 r = -ENOMEM;
4384 goto out1;
4385 }
4386
5897297b
AK		 4387 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4388 if (!vmx_msr_bitmap_longmode) {
4389 r = -ENOMEM;
4390 goto out2;
4391 }
4392
fdef3ad1
HQ		 4393 /*
4394 * Allow direct access to the PC debug port (it is often used for I/O
4395 * delays, but the vmexits simply slow things down).
4396 */
3e7c73e9
AK		 4397 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4398 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4399
3e7c73e9 4400 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4401
5897297b
AK		 4402 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4403 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4404
2384d2b3
SY		 4405 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4406
0ee75bea
AK		 4407 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4408 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4409 if (r)
5897297b 4410 goto out3;
25c5f225 4411
5897297b
AK		 4412 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4413 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4414 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4415 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4416 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4417 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4418
089d034e 4419 if (enable_ept) {
1439442c 4420 bypass_guest_pf = 0;
534e38b4 4421 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4422 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4423 kvm_enable_tdp();
4424 } else
4425 kvm_disable_tdp();
1439442c 4426
c7addb90
AK		 4427 if (bypass_guest_pf)
4428 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4429
fdef3ad1
HQ		 4430 return 0;
4431
5897297b
AK		 4432out3:
4433 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4434out2:
5897297b 4435 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4436out1:
3e7c73e9 4437 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4438out:
3e7c73e9 4439 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4440 return r;
6aa8b732
AK		 4441}
4442
4443static void __exit vmx_exit(void)
4444{
5897297b
AK		 4445 free_page((unsigned long)vmx_msr_bitmap_legacy);
4446 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4447 free_page((unsigned long)vmx_io_bitmap_b);
4448 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4449
cb498ea2 4450 kvm_exit();
6aa8b732
AK		 4451}
4452
4453module_init(vmx_init)
4454module_exit(vmx_exit)
Ubuntu Artful kernel mirror