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nvme: Don't allow to reset a reconnecting controller
[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
dca51e78 19#include <linux/blk-mq-pci.h>
42f61420 20#include <linux/cpu.h>
fd63e9ce 21#include <linux/delay.h>
ff5350a8 22#include <linux/dmi.h>
b60503ba
MW		 23#include <linux/errno.h>
24#include <linux/fs.h>
25#include <linux/genhd.h>
4cc09e2d 26#include <linux/hdreg.h>
5aff9382 27#include <linux/idr.h>
b60503ba
MW		 28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/kdev_t.h>
32#include <linux/kernel.h>
33#include <linux/mm.h>
34#include <linux/module.h>
35#include <linux/moduleparam.h>
77bf25ea 36#include <linux/mutex.h>
b60503ba 37#include <linux/pci.h>
be7b6275 38#include <linux/poison.h>
c3bfe717 39#include <linux/ptrace.h>
b60503ba
MW		 40#include <linux/sched.h>
41#include <linux/slab.h>
e1e5e564 42#include <linux/t10-pi.h>
2d55cd5f 43#include <linux/timer.h>
b60503ba 44#include <linux/types.h>
2f8e2c87 45#include <linux/io-64-nonatomic-lo-hi.h>
1d277a63 46#include <asm/unaligned.h>
a98e58e5 47#include <linux/sed-opal.h>
797a796a 48
f11bb3e2
CH		 49#include "nvme.h"
50
9d43cf64 51#define NVME_Q_DEPTH 1024
d31af0a3 52#define NVME_AQ_DEPTH 256
b60503ba
MW		 53#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 55
adf68f21
CH		 56/*
57 * We handle AEN commands ourselves and don't even let the
58 * block layer know about them.
59 */
f866fc42 60#define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
9d43cf64 61
58ffacb5
MW		 62static int use_threaded_interrupts;
63module_param(use_threaded_interrupts, int, 0);
64
8ffaadf7
JD		 65static bool use_cmb_sqes = true;
66module_param(use_cmb_sqes, bool, 0644);
67MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
68
87ad72a5
CH		 69static unsigned int max_host_mem_size_mb = 128;
70module_param(max_host_mem_size_mb, uint, 0444);
71MODULE_PARM_DESC(max_host_mem_size_mb,
72 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
73
9a6b9458 74static struct workqueue_struct *nvme_workq;
1fa6aead 75
1c63dc66
CH		 76struct nvme_dev;
77struct nvme_queue;
b3fffdef 78
4cc06521 79static int nvme_reset(struct nvme_dev *dev);
a0fa9647 80static void nvme_process_cq(struct nvme_queue *nvmeq);
a5cdb68c 81static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 82
1c63dc66
CH		 83/*
84 * Represents an NVM Express device. Each nvme_dev is a PCI function.
85 */
86struct nvme_dev {
1c63dc66
CH		 87 struct nvme_queue **queues;
88 struct blk_mq_tag_set tagset;
89 struct blk_mq_tag_set admin_tagset;
90 u32 __iomem *dbs;
91 struct device *dev;
92 struct dma_pool *prp_page_pool;
93 struct dma_pool *prp_small_pool;
94 unsigned queue_count;
95 unsigned online_queues;
96 unsigned max_qid;
97 int q_depth;
98 u32 db_stride;
1c63dc66 99 void __iomem *bar;
1c63dc66 100 struct work_struct reset_work;
5c8809e6 101 struct work_struct remove_work;
2d55cd5f 102 struct timer_list watchdog_timer;
77bf25ea 103 struct mutex shutdown_lock;
1c63dc66 104 bool subsystem;
1c63dc66
CH		 105 void __iomem *cmb;
106 dma_addr_t cmb_dma_addr;
107 u64 cmb_size;
108 u32 cmbsz;
202021c1 109 u32 cmbloc;
1c63dc66 110 struct nvme_ctrl ctrl;
db3cbfff 111 struct completion ioq_wait;
87ad72a5
CH		 112
113 /* shadow doorbell buffer support: */
f9f38e33
HK		 114 u32 *dbbuf_dbs;
115 dma_addr_t dbbuf_dbs_dma_addr;
116 u32 *dbbuf_eis;
117 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 118
119 /* host memory buffer support: */
120 u64 host_mem_size;
121 u32 nr_host_mem_descs;
122 struct nvme_host_mem_buf_desc *host_mem_descs;
123 void **host_mem_desc_bufs;
4d115420 124};
1fa6aead 125
f9f38e33
HK		 126static inline unsigned int sq_idx(unsigned int qid, u32 stride)
127{
128 return qid * 2 * stride;
129}
130
131static inline unsigned int cq_idx(unsigned int qid, u32 stride)
132{
133 return (qid * 2 + 1) * stride;
134}
135
1c63dc66
CH		 136static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
137{
138 return container_of(ctrl, struct nvme_dev, ctrl);
139}
140
b60503ba
MW		 141/*
142 * An NVM Express queue. Each device has at least two (one for admin
143 * commands and one for I/O commands).
144 */
145struct nvme_queue {
146 struct device *q_dmadev;
091b6092 147 struct nvme_dev *dev;
b60503ba
MW		 148 spinlock_t q_lock;
149 struct nvme_command *sq_cmds;
8ffaadf7 150 struct nvme_command __iomem *sq_cmds_io;
b60503ba 151 volatile struct nvme_completion *cqes;
42483228 152 struct blk_mq_tags **tags;
b60503ba
MW		 153 dma_addr_t sq_dma_addr;
154 dma_addr_t cq_dma_addr;
b60503ba
MW		 155 u32 __iomem *q_db;
156 u16 q_depth;
6222d172 157 s16 cq_vector;
b60503ba
MW		 158 u16 sq_tail;
159 u16 cq_head;
c30341dc 160 u16 qid;
e9539f47
MW		 161 u8 cq_phase;
162 u8 cqe_seen;
f9f38e33
HK		 163 u32 *dbbuf_sq_db;
164 u32 *dbbuf_cq_db;
165 u32 *dbbuf_sq_ei;
166 u32 *dbbuf_cq_ei;
b60503ba
MW		 167};
168
71bd150c
CH		 169/*
170 * The nvme_iod describes the data in an I/O, including the list of PRP
171 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 172 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 173 * allocated to store the PRP list.
174 */
175struct nvme_iod {
d49187e9 176 struct nvme_request req;
f4800d6d
CH		 177 struct nvme_queue *nvmeq;
178 int aborted;
71bd150c 179 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 180 int nents; /* Used in scatterlist */
181 int length; /* Of data, in bytes */
182 dma_addr_t first_dma;
bf684057 183 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 184 struct scatterlist *sg;
185 struct scatterlist inline_sg[0];
b60503ba
MW		 186};
187
188/*
189 * Check we didin't inadvertently grow the command struct
190 */
191static inline void _nvme_check_size(void)
192{
193 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
194 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
195 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 198 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 199 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 200 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
202 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
203 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 204 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 205 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
206}
207
208static inline unsigned int nvme_dbbuf_size(u32 stride)
209{
210 return ((num_possible_cpus() + 1) * 8 * stride);
211}
212
213static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
214{
215 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
216
217 if (dev->dbbuf_dbs)
218 return 0;
219
220 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
221 &dev->dbbuf_dbs_dma_addr,
222 GFP_KERNEL);
223 if (!dev->dbbuf_dbs)
224 return -ENOMEM;
225 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
226 &dev->dbbuf_eis_dma_addr,
227 GFP_KERNEL);
228 if (!dev->dbbuf_eis) {
229 dma_free_coherent(dev->dev, mem_size,
230 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
231 dev->dbbuf_dbs = NULL;
232 return -ENOMEM;
233 }
234
235 return 0;
236}
237
238static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
239{
240 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
241
242 if (dev->dbbuf_dbs) {
243 dma_free_coherent(dev->dev, mem_size,
244 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
245 dev->dbbuf_dbs = NULL;
246 }
247 if (dev->dbbuf_eis) {
248 dma_free_coherent(dev->dev, mem_size,
249 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
250 dev->dbbuf_eis = NULL;
251 }
252}
253
254static void nvme_dbbuf_init(struct nvme_dev *dev,
255 struct nvme_queue *nvmeq, int qid)
256{
257 if (!dev->dbbuf_dbs || !qid)
258 return;
259
260 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
261 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
262 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
263 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
264}
265
266static void nvme_dbbuf_set(struct nvme_dev *dev)
267{
268 struct nvme_command c;
269
270 if (!dev->dbbuf_dbs)
271 return;
272
273 memset(&c, 0, sizeof(c));
274 c.dbbuf.opcode = nvme_admin_dbbuf;
275 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
276 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
277
278 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 279 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 280 /* Free memory and continue on */
281 nvme_dbbuf_dma_free(dev);
282 }
283}
284
285static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
286{
287 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
288}
289
290/* Update dbbuf and return true if an MMIO is required */
291static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
292 volatile u32 *dbbuf_ei)
293{
294 if (dbbuf_db) {
295 u16 old_value;
296
297 /*
298 * Ensure that the queue is written before updating
299 * the doorbell in memory
300 */
301 wmb();
302
303 old_value = *dbbuf_db;
304 *dbbuf_db = value;
305
306 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
307 return false;
308 }
309
310 return true;
b60503ba
MW		 311}
312
ac3dd5bd
JA		 313/*
314 * Max size of iod being embedded in the request payload
315 */
316#define NVME_INT_PAGES 2
5fd4ce1b 317#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 318
319/*
320 * Will slightly overestimate the number of pages needed. This is OK
321 * as it only leads to a small amount of wasted memory for the lifetime of
322 * the I/O.
323 */
324static int nvme_npages(unsigned size, struct nvme_dev *dev)
325{
5fd4ce1b
CH		 326 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
327 dev->ctrl.page_size);
ac3dd5bd
JA		 328 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
329}
330
f4800d6d
CH		 331static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
332 unsigned int size, unsigned int nseg)
ac3dd5bd 333{
f4800d6d
CH		 334 return sizeof(__le64 *) * nvme_npages(size, dev) +
335 sizeof(struct scatterlist) * nseg;
336}
ac3dd5bd 337
f4800d6d
CH		 338static unsigned int nvme_cmd_size(struct nvme_dev *dev)
339{
340 return sizeof(struct nvme_iod) +
341 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
ac3dd5bd
JA		 342}
343
a4aea562
MB		 344static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
345 unsigned int hctx_idx)
e85248e5 346{
a4aea562
MB		 347 struct nvme_dev *dev = data;
348 struct nvme_queue *nvmeq = dev->queues[0];
349
42483228
KB		 350 WARN_ON(hctx_idx != 0);
351 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
352 WARN_ON(nvmeq->tags);
353
a4aea562 354 hctx->driver_data = nvmeq;
42483228 355 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 356 return 0;
e85248e5
MW		 357}
358
4af0e21c
KB		 359static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
360{
361 struct nvme_queue *nvmeq = hctx->driver_data;
362
363 nvmeq->tags = NULL;
364}
365
d6296d39
CH		 366static int nvme_admin_init_request(struct blk_mq_tag_set *set,
367 struct request *req, unsigned int hctx_idx,
368 unsigned int numa_node)
22404274 369{
d6296d39 370 struct nvme_dev *dev = set->driver_data;
f4800d6d 371 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562
MB		 372 struct nvme_queue *nvmeq = dev->queues[0];
373
374 BUG_ON(!nvmeq);
f4800d6d 375 iod->nvmeq = nvmeq;
a4aea562 376 return 0;
22404274
KB		 377}
378
a4aea562
MB		 379static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
380 unsigned int hctx_idx)
b60503ba 381{
a4aea562 382 struct nvme_dev *dev = data;
42483228 383 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 384
42483228
KB		 385 if (!nvmeq->tags)
386 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 387
42483228 388 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 389 hctx->driver_data = nvmeq;
390 return 0;
b60503ba
MW		 391}
392
d6296d39
CH		 393static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
394 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 395{
d6296d39 396 struct nvme_dev *dev = set->driver_data;
f4800d6d 397 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562
MB		 398 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
399
400 BUG_ON(!nvmeq);
f4800d6d 401 iod->nvmeq = nvmeq;
a4aea562
MB		 402 return 0;
403}
404
dca51e78
CH		 405static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
406{
407 struct nvme_dev *dev = set->driver_data;
408
409 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
410}
411
b60503ba 412/**
adf68f21 413 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 414 * @nvmeq: The queue to use
415 * @cmd: The command to send
416 *
417 * Safe to use from interrupt context
418 */
e3f879bf
SB		 419static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
420 struct nvme_command *cmd)
b60503ba 421{
a4aea562
MB		 422 u16 tail = nvmeq->sq_tail;
423
8ffaadf7
JD		 424 if (nvmeq->sq_cmds_io)
425 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
426 else
427 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
428
b60503ba
MW		 429 if (++tail == nvmeq->q_depth)
430 tail = 0;
f9f38e33
HK		 431 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
432 nvmeq->dbbuf_sq_ei))
433 writel(tail, nvmeq->q_db);
b60503ba 434 nvmeq->sq_tail = tail;
b60503ba
MW		 435}
436
f4800d6d 437static __le64 **iod_list(struct request *req)
b60503ba 438{
f4800d6d 439 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
f9d03f96 440 return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 441}
442
fc17b653 443static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 444{
f4800d6d 445 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 446 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 447 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 448
f4800d6d
CH		 449 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
450 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
451 if (!iod->sg)
fc17b653 452 return BLK_STS_RESOURCE;
f4800d6d
CH		 453 } else {
454 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 455 }
456
f4800d6d
CH		 457 iod->aborted = 0;
458 iod->npages = -1;
459 iod->nents = 0;
460 iod->length = size;
f80ec966 461
fc17b653 462 return BLK_STS_OK;
ac3dd5bd
JA		 463}
464
f4800d6d 465static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 466{
f4800d6d 467 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
5fd4ce1b 468 const int last_prp = dev->ctrl.page_size / 8 - 1;
eca18b23 469 int i;
f4800d6d 470 __le64 **list = iod_list(req);
eca18b23
MW		 471 dma_addr_t prp_dma = iod->first_dma;
472
473 if (iod->npages == 0)
474 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
475 for (i = 0; i < iod->npages; i++) {
476 __le64 *prp_list = list[i];
477 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
478 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
479 prp_dma = next_prp_dma;
480 }
ac3dd5bd 481
f4800d6d
CH		 482 if (iod->sg != iod->inline_sg)
483 kfree(iod->sg);
b4ff9c8d
KB		 484}
485
52b68d7e 486#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 487static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
488{
489 if (be32_to_cpu(pi->ref_tag) == v)
490 pi->ref_tag = cpu_to_be32(p);
491}
492
493static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
494{
495 if (be32_to_cpu(pi->ref_tag) == p)
496 pi->ref_tag = cpu_to_be32(v);
497}
498
499/**
500 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
501 *
502 * The virtual start sector is the one that was originally submitted by the
503 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
504 * start sector may be different. Remap protection information to match the
505 * physical LBA on writes, and back to the original seed on reads.
506 *
507 * Type 0 and 3 do not have a ref tag, so no remapping required.
508 */
509static void nvme_dif_remap(struct request *req,
510 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
511{
512 struct nvme_ns *ns = req->rq_disk->private_data;
513 struct bio_integrity_payload *bip;
514 struct t10_pi_tuple *pi;
515 void *p, *pmap;
516 u32 i, nlb, ts, phys, virt;
517
518 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
519 return;
520
521 bip = bio_integrity(req->bio);
522 if (!bip)
523 return;
524
525 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 526
527 p = pmap;
528 virt = bip_get_seed(bip);
529 phys = nvme_block_nr(ns, blk_rq_pos(req));
530 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
ac6fc48c 531 ts = ns->disk->queue->integrity.tuple_size;
e1e5e564
KB		 532
533 for (i = 0; i < nlb; i++, virt++, phys++) {
534 pi = (struct t10_pi_tuple *)p;
535 dif_swap(phys, virt, pi);
536 p += ts;
537 }
538 kunmap_atomic(pmap);
539}
52b68d7e
KB		 540#else /* CONFIG_BLK_DEV_INTEGRITY */
541static void nvme_dif_remap(struct request *req,
542 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
543{
544}
545static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
546{
547}
548static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
549{
550}
52b68d7e
KB		 551#endif
552
b131c61d 553static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req)
ff22b54f 554{
f4800d6d 555 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 556 struct dma_pool *pool;
b131c61d 557 int length = blk_rq_payload_bytes(req);
eca18b23 558 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 559 int dma_len = sg_dma_len(sg);
560 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 561 u32 page_size = dev->ctrl.page_size;
f137e0f1 562 int offset = dma_addr & (page_size - 1);
e025344c 563 __le64 *prp_list;
f4800d6d 564 __le64 **list = iod_list(req);
e025344c 565 dma_addr_t prp_dma;
eca18b23 566 int nprps, i;
ff22b54f 567
1d090624 568 length -= (page_size - offset);
ff22b54f 569 if (length <= 0)
69d2b571 570 return true;
ff22b54f 571
1d090624 572 dma_len -= (page_size - offset);
ff22b54f 573 if (dma_len) {
1d090624 574 dma_addr += (page_size - offset);
ff22b54f
MW		 575 } else {
576 sg = sg_next(sg);
577 dma_addr = sg_dma_address(sg);
578 dma_len = sg_dma_len(sg);
579 }
580
1d090624 581 if (length <= page_size) {
edd10d33 582 iod->first_dma = dma_addr;
69d2b571 583 return true;
e025344c
SMM		 584 }
585
1d090624 586 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 587 if (nprps <= (256 / 8)) {
588 pool = dev->prp_small_pool;
eca18b23 589 iod->npages = 0;
99802a7a
MW		 590 } else {
591 pool = dev->prp_page_pool;
eca18b23 592 iod->npages = 1;
99802a7a
MW		 593 }
594
69d2b571 595 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 596 if (!prp_list) {
edd10d33 597 iod->first_dma = dma_addr;
eca18b23 598 iod->npages = -1;
69d2b571 599 return false;
b77954cb 600 }
eca18b23
MW		 601 list[0] = prp_list;
602 iod->first_dma = prp_dma;
e025344c
SMM		 603 i = 0;
604 for (;;) {
1d090624 605 if (i == page_size >> 3) {
e025344c 606 __le64 *old_prp_list = prp_list;
69d2b571 607 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 608 if (!prp_list)
69d2b571 609 return false;
eca18b23 610 list[iod->npages++] = prp_list;
7523d834
MW		 611 prp_list[0] = old_prp_list[i - 1];
612 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
613 i = 1;
e025344c
SMM		 614 }
615 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 616 dma_len -= page_size;
617 dma_addr += page_size;
618 length -= page_size;
e025344c
SMM		 619 if (length <= 0)
620 break;
621 if (dma_len > 0)
622 continue;
623 BUG_ON(dma_len < 0);
624 sg = sg_next(sg);
625 dma_addr = sg_dma_address(sg);
626 dma_len = sg_dma_len(sg);
ff22b54f
MW		 627 }
628
69d2b571 629 return true;
ff22b54f
MW		 630}
631
fc17b653 632static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 633 struct nvme_command *cmnd)
d29ec824 634{
f4800d6d 635 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 636 struct request_queue *q = req->q;
637 enum dma_data_direction dma_dir = rq_data_dir(req) ?
638 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 639 blk_status_t ret = BLK_STS_IOERR;
d29ec824 640
f9d03f96 641 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 642 iod->nents = blk_rq_map_sg(q, req, iod->sg);
643 if (!iod->nents)
644 goto out;
d29ec824 645
fc17b653 646 ret = BLK_STS_RESOURCE;
2b6b535d
MFO		 647 if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
648 DMA_ATTR_NO_WARN))
ba1ca37e 649 goto out;
d29ec824 650
b131c61d 651 if (!nvme_setup_prps(dev, req))
ba1ca37e 652 goto out_unmap;
0e5e4f0e 653
fc17b653 654 ret = BLK_STS_IOERR;
ba1ca37e
CH		 655 if (blk_integrity_rq(req)) {
656 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
657 goto out_unmap;
0e5e4f0e 658
bf684057
CH		 659 sg_init_table(&iod->meta_sg, 1);
660 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 661 goto out_unmap;
0e5e4f0e 662
ba1ca37e
CH		 663 if (rq_data_dir(req))
664 nvme_dif_remap(req, nvme_dif_prep);
0e5e4f0e 665
bf684057 666 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 667 goto out_unmap;
d29ec824 668 }
00df5cb4 669
eb793e2c
CH		 670 cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
671 cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
ba1ca37e 672 if (blk_integrity_rq(req))
bf684057 673 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
fc17b653 674 return BLK_STS_OK;
00df5cb4 675
ba1ca37e
CH		 676out_unmap:
677 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
678out:
679 return ret;
00df5cb4
MW		 680}
681
f4800d6d 682static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 683{
f4800d6d 684 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 685 enum dma_data_direction dma_dir = rq_data_dir(req) ?
686 DMA_TO_DEVICE : DMA_FROM_DEVICE;
687
688 if (iod->nents) {
689 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
690 if (blk_integrity_rq(req)) {
691 if (!rq_data_dir(req))
692 nvme_dif_remap(req, nvme_dif_complete);
bf684057 693 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e1e5e564 694 }
e19b127f 695 }
e1e5e564 696
f9d03f96 697 nvme_cleanup_cmd(req);
f4800d6d 698 nvme_free_iod(dev, req);
d4f6c3ab 699}
b60503ba 700
d29ec824
CH		 701/*
702 * NOTE: ns is NULL when called on the admin queue.
703 */
fc17b653 704static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 705 const struct blk_mq_queue_data *bd)
edd10d33 706{
a4aea562
MB		 707 struct nvme_ns *ns = hctx->queue->queuedata;
708 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 709 struct nvme_dev *dev = nvmeq->dev;
a4aea562 710 struct request *req = bd->rq;
ba1ca37e 711 struct nvme_command cmnd;
fc17b653 712 blk_status_t ret = BLK_STS_OK;
edd10d33 713
e1e5e564
KB		 714 /*
715 * If formated with metadata, require the block layer provide a buffer
716 * unless this namespace is formated such that the metadata can be
717 * stripped/generated by the controller with PRACT=1.
718 */
d29ec824 719 if (ns && ns->ms && !blk_integrity_rq(req)) {
71feb364 720 if (!(ns->pi_type && ns->ms == 8) &&
fc17b653
CH		 721 !blk_rq_is_passthrough(req))
722 return BLK_STS_NOTSUPP;
e1e5e564
KB		 723 }
724
f9d03f96 725 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 726 if (ret)
f4800d6d 727 return ret;
a4aea562 728
b131c61d 729 ret = nvme_init_iod(req, dev);
fc17b653 730 if (ret)
f9d03f96 731 goto out_free_cmd;
a4aea562 732
fc17b653 733 if (blk_rq_nr_phys_segments(req)) {
b131c61d 734 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 735 if (ret)
736 goto out_cleanup_iod;
737 }
a4aea562 738
aae239e1 739 blk_mq_start_request(req);
a4aea562 740
ba1ca37e 741 spin_lock_irq(&nvmeq->q_lock);
ae1fba20 742 if (unlikely(nvmeq->cq_vector < 0)) {
fc17b653 743 ret = BLK_STS_IOERR;
ae1fba20 744 spin_unlock_irq(&nvmeq->q_lock);
f9d03f96 745 goto out_cleanup_iod;
ae1fba20 746 }
ba1ca37e 747 __nvme_submit_cmd(nvmeq, &cmnd);
a4aea562
MB		 748 nvme_process_cq(nvmeq);
749 spin_unlock_irq(&nvmeq->q_lock);
fc17b653 750 return BLK_STS_OK;
f9d03f96 751out_cleanup_iod:
f4800d6d 752 nvme_free_iod(dev, req);
f9d03f96
CH		 753out_free_cmd:
754 nvme_cleanup_cmd(req);
ba1ca37e 755 return ret;
b60503ba 756}
e1e5e564 757
77f02a7a 758static void nvme_pci_complete_rq(struct request *req)
eee417b0 759{
f4800d6d 760 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 761
77f02a7a
CH		 762 nvme_unmap_data(iod->nvmeq->dev, req);
763 nvme_complete_rq(req);
b60503ba
MW		 764}
765
d783e0bd
MR		 766/* We read the CQE phase first to check if the rest of the entry is valid */
767static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
768 u16 phase)
769{
770 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
771}
772
a0fa9647 773static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
b60503ba 774{
82123460 775 u16 head, phase;
b60503ba 776
b60503ba 777 head = nvmeq->cq_head;
82123460 778 phase = nvmeq->cq_phase;
b60503ba 779
d783e0bd 780 while (nvme_cqe_valid(nvmeq, head, phase)) {
b60503ba 781 struct nvme_completion cqe = nvmeq->cqes[head];
eee417b0 782 struct request *req;
adf68f21 783
b60503ba
MW		 784 if (++head == nvmeq->q_depth) {
785 head = 0;
82123460 786 phase = !phase;
b60503ba 787 }
adf68f21 788
a0fa9647
JA		 789 if (tag && *tag == cqe.command_id)
790 *tag = -1;
adf68f21 791
aae239e1 792 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
1b3c47c1 793 dev_warn(nvmeq->dev->ctrl.device,
aae239e1
CH		 794 "invalid id %d completed on queue %d\n",
795 cqe.command_id, le16_to_cpu(cqe.sq_id));
796 continue;
797 }
798
adf68f21
CH		 799 /*
800 * AEN requests are special as they don't time out and can
801 * survive any kind of queue freeze and often don't respond to
802 * aborts. We don't even bother to allocate a struct request
803 * for them but rather special case them here.
804 */
805 if (unlikely(nvmeq->qid == 0 &&
806 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
7bf58533
CH		 807 nvme_complete_async_event(&nvmeq->dev->ctrl,
808 cqe.status, &cqe.result);
adf68f21
CH		 809 continue;
810 }
811
eee417b0 812 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
27fa9bc5 813 nvme_end_request(req, cqe.status, cqe.result);
b60503ba
MW		 814 }
815
82123460 816 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
a0fa9647 817 return;
b60503ba 818
604e8c8d 819 if (likely(nvmeq->cq_vector >= 0))
f9f38e33
HK		 820 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
821 nvmeq->dbbuf_cq_ei))
822 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 823 nvmeq->cq_head = head;
82123460 824 nvmeq->cq_phase = phase;
b60503ba 825
e9539f47 826 nvmeq->cqe_seen = 1;
a0fa9647
JA		 827}
828
829static void nvme_process_cq(struct nvme_queue *nvmeq)
830{
831 __nvme_process_cq(nvmeq, NULL);
b60503ba
MW		 832}
833
834static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 835{
836 irqreturn_t result;
837 struct nvme_queue *nvmeq = data;
838 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 839 nvme_process_cq(nvmeq);
840 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
841 nvmeq->cqe_seen = 0;
58ffacb5
MW		 842 spin_unlock(&nvmeq->q_lock);
843 return result;
844}
845
846static irqreturn_t nvme_irq_check(int irq, void *data)
847{
848 struct nvme_queue *nvmeq = data;
d783e0bd
MR		 849 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
850 return IRQ_WAKE_THREAD;
851 return IRQ_NONE;
58ffacb5
MW		 852}
853
7776db1c 854static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 855{
d783e0bd 856 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
a0fa9647
JA		 857 spin_lock_irq(&nvmeq->q_lock);
858 __nvme_process_cq(nvmeq, &tag);
859 spin_unlock_irq(&nvmeq->q_lock);
860
861 if (tag == -1)
862 return 1;
863 }
864
865 return 0;
866}
867
7776db1c
KB		 868static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
869{
870 struct nvme_queue *nvmeq = hctx->driver_data;
871
872 return __nvme_poll(nvmeq, tag);
873}
874
f866fc42 875static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
b60503ba 876{
f866fc42 877 struct nvme_dev *dev = to_nvme_dev(ctrl);
9396dec9 878 struct nvme_queue *nvmeq = dev->queues[0];
a4aea562 879 struct nvme_command c;
b60503ba 880
a4aea562
MB		 881 memset(&c, 0, sizeof(c));
882 c.common.opcode = nvme_admin_async_event;
f866fc42 883 c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
3c0cf138 884
9396dec9 885 spin_lock_irq(&nvmeq->q_lock);
f866fc42 886 __nvme_submit_cmd(nvmeq, &c);
9396dec9 887 spin_unlock_irq(&nvmeq->q_lock);
f705f837
CH		 888}
889
b60503ba 890static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 891{
b60503ba
MW		 892 struct nvme_command c;
893
894 memset(&c, 0, sizeof(c));
895 c.delete_queue.opcode = opcode;
896 c.delete_queue.qid = cpu_to_le16(id);
897
1c63dc66 898 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 899}
900
b60503ba
MW		 901static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
902 struct nvme_queue *nvmeq)
903{
b60503ba
MW		 904 struct nvme_command c;
905 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
906
d29ec824
CH		 907 /*
908 * Note: we (ab)use the fact the the prp fields survive if no data
909 * is attached to the request.
910 */
b60503ba
MW		 911 memset(&c, 0, sizeof(c));
912 c.create_cq.opcode = nvme_admin_create_cq;
913 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
914 c.create_cq.cqid = cpu_to_le16(qid);
915 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
916 c.create_cq.cq_flags = cpu_to_le16(flags);
917 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
918
1c63dc66 919 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 920}
921
922static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
923 struct nvme_queue *nvmeq)
924{
b60503ba 925 struct nvme_command c;
81c1cd98 926 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 927
d29ec824
CH		 928 /*
929 * Note: we (ab)use the fact the the prp fields survive if no data
930 * is attached to the request.
931 */
b60503ba
MW		 932 memset(&c, 0, sizeof(c));
933 c.create_sq.opcode = nvme_admin_create_sq;
934 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
935 c.create_sq.sqid = cpu_to_le16(qid);
936 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
937 c.create_sq.sq_flags = cpu_to_le16(flags);
938 c.create_sq.cqid = cpu_to_le16(qid);
939
1c63dc66 940 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 941}
942
943static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
944{
945 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
946}
947
948static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
949{
950 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
951}
952
2a842aca 953static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 954{
f4800d6d
CH		 955 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
956 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 957
27fa9bc5
CH		 958 dev_warn(nvmeq->dev->ctrl.device,
959 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 960 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 961 blk_mq_free_request(req);
bc5fc7e4
MW		 962}
963
31c7c7d2 964static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 965{
f4800d6d
CH		 966 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
967 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 968 struct nvme_dev *dev = nvmeq->dev;
a4aea562 969 struct request *abort_req;
a4aea562 970 struct nvme_command cmd;
c30341dc 971
7776db1c
KB		 972 /*
973 * Did we miss an interrupt?
974 */
975 if (__nvme_poll(nvmeq, req->tag)) {
976 dev_warn(dev->ctrl.device,
977 "I/O %d QID %d timeout, completion polled\n",
978 req->tag, nvmeq->qid);
979 return BLK_EH_HANDLED;
980 }
981
31c7c7d2 982 /*
fd634f41
CH		 983 * Shutdown immediately if controller times out while starting. The
984 * reset work will see the pci device disabled when it gets the forced
985 * cancellation error. All outstanding requests are completed on
986 * shutdown, so we return BLK_EH_HANDLED.
987 */
bb8d261e 988 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1b3c47c1 989 dev_warn(dev->ctrl.device,
fd634f41
CH		 990 "I/O %d QID %d timeout, disable controller\n",
991 req->tag, nvmeq->qid);
a5cdb68c 992 nvme_dev_disable(dev, false);
27fa9bc5 993 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
fd634f41 994 return BLK_EH_HANDLED;
c30341dc
KB		 995 }
996
fd634f41
CH		 997 /*
998 * Shutdown the controller immediately and schedule a reset if the
999 * command was already aborted once before and still hasn't been
1000 * returned to the driver, or if this is the admin queue.
31c7c7d2 1001 */
f4800d6d 1002 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1003 dev_warn(dev->ctrl.device,
e1569a16
KB		 1004 "I/O %d QID %d timeout, reset controller\n",
1005 req->tag, nvmeq->qid);
a5cdb68c 1006 nvme_dev_disable(dev, false);
c5f6ce97 1007 nvme_reset(dev);
c30341dc 1008
e1569a16
KB		 1009 /*
1010 * Mark the request as handled, since the inline shutdown
1011 * forces all outstanding requests to complete.
1012 */
27fa9bc5 1013 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
e1569a16 1014 return BLK_EH_HANDLED;
c30341dc 1015 }
c30341dc 1016
e7a2a87d 1017 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1018 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1019 return BLK_EH_RESET_TIMER;
6bf25d16 1020 }
7bf7d778 1021 iod->aborted = 1;
a4aea562 1022
c30341dc
KB		 1023 memset(&cmd, 0, sizeof(cmd));
1024 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1025 cmd.abort.cid = req->tag;
c30341dc 1026 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1027
1b3c47c1
SG		 1028 dev_warn(nvmeq->dev->ctrl.device,
1029 "I/O %d QID %d timeout, aborting\n",
1030 req->tag, nvmeq->qid);
e7a2a87d
CH		 1031
1032 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1033 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1034 if (IS_ERR(abort_req)) {
1035 atomic_inc(&dev->ctrl.abort_limit);
1036 return BLK_EH_RESET_TIMER;
1037 }
1038
1039 abort_req->timeout = ADMIN_TIMEOUT;
1040 abort_req->end_io_data = NULL;
1041 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1042
31c7c7d2
CH		 1043 /*
1044 * The aborted req will be completed on receiving the abort req.
1045 * We enable the timer again. If hit twice, it'll cause a device reset,
1046 * as the device then is in a faulty state.
1047 */
1048 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1049}
1050
a4aea562
MB		 1051static void nvme_free_queue(struct nvme_queue *nvmeq)
1052{
9e866774
MW		 1053 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1054 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1055 if (nvmeq->sq_cmds)
1056 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774
MW		 1057 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1058 kfree(nvmeq);
1059}
1060
a1a5ef99 1061static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1062{
1063 int i;
1064
a1a5ef99 1065 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1066 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1067 dev->queue_count--;
a4aea562 1068 dev->queues[i] = NULL;
f435c282 1069 nvme_free_queue(nvmeq);
121c7ad4 1070 }
22404274
KB		 1071}
1072
4d115420
KB		 1073/**
1074 * nvme_suspend_queue - put queue into suspended state
1075 * @nvmeq - queue to suspend
4d115420
KB		 1076 */
1077static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1078{
2b25d981 1079 int vector;
b60503ba 1080
a09115b2 1081 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1082 if (nvmeq->cq_vector == -1) {
1083 spin_unlock_irq(&nvmeq->q_lock);
1084 return 1;
1085 }
0ff199cb 1086 vector = nvmeq->cq_vector;
42f61420 1087 nvmeq->dev->online_queues--;
2b25d981 1088 nvmeq->cq_vector = -1;
a09115b2
MW		 1089 spin_unlock_irq(&nvmeq->q_lock);
1090
1c63dc66 1091 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
25646264 1092 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
6df3dbc8 1093
0ff199cb 1094 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
b60503ba 1095
4d115420
KB		 1096 return 0;
1097}
b60503ba 1098
a5cdb68c 1099static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1100{
a5cdb68c 1101 struct nvme_queue *nvmeq = dev->queues[0];
4d115420
KB		 1102
1103 if (!nvmeq)
1104 return;
1105 if (nvme_suspend_queue(nvmeq))
1106 return;
1107
a5cdb68c
KB		 1108 if (shutdown)
1109 nvme_shutdown_ctrl(&dev->ctrl);
1110 else
1111 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1112 dev->bar + NVME_REG_CAP));
07836e65
KB		 1113
1114 spin_lock_irq(&nvmeq->q_lock);
1115 nvme_process_cq(nvmeq);
1116 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1117}
1118
8ffaadf7
JD		 1119static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1120 int entry_size)
1121{
1122 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1123 unsigned q_size_aligned = roundup(q_depth * entry_size,
1124 dev->ctrl.page_size);
8ffaadf7
JD		 1125
1126 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1127 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1128 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1129 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1130
1131 /*
1132 * Ensure the reduced q_depth is above some threshold where it
1133 * would be better to map queues in system memory with the
1134 * original depth
1135 */
1136 if (q_depth < 64)
1137 return -ENOMEM;
1138 }
1139
1140 return q_depth;
1141}
1142
1143static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1144 int qid, int depth)
1145{
1146 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
5fd4ce1b
CH		 1147 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1148 dev->ctrl.page_size);
8ffaadf7
JD		 1149 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1150 nvmeq->sq_cmds_io = dev->cmb + offset;
1151 } else {
1152 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1153 &nvmeq->sq_dma_addr, GFP_KERNEL);
1154 if (!nvmeq->sq_cmds)
1155 return -ENOMEM;
1156 }
1157
1158 return 0;
1159}
1160
b60503ba 1161static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
d3af3ecd 1162 int depth, int node)
b60503ba 1163{
d3af3ecd
SL		 1164 struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1165 node);
b60503ba
MW		 1166 if (!nvmeq)
1167 return NULL;
1168
e75ec752 1169 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1170 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1171 if (!nvmeq->cqes)
1172 goto free_nvmeq;
b60503ba 1173
8ffaadf7 1174 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1175 goto free_cqdma;
1176
e75ec752 1177 nvmeq->q_dmadev = dev->dev;
091b6092 1178 nvmeq->dev = dev;
b60503ba
MW		 1179 spin_lock_init(&nvmeq->q_lock);
1180 nvmeq->cq_head = 0;
82123460 1181 nvmeq->cq_phase = 1;
b80d5ccc 1182 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1183 nvmeq->q_depth = depth;
c30341dc 1184 nvmeq->qid = qid;
758dd7fd 1185 nvmeq->cq_vector = -1;
a4aea562 1186 dev->queues[qid] = nvmeq;
36a7e993
JD		 1187 dev->queue_count++;
1188
b60503ba
MW		 1189 return nvmeq;
1190
1191 free_cqdma:
e75ec752 1192 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1193 nvmeq->cq_dma_addr);
1194 free_nvmeq:
1195 kfree(nvmeq);
1196 return NULL;
1197}
1198
dca51e78 1199static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1200{
0ff199cb
CH		 1201 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1202 int nr = nvmeq->dev->ctrl.instance;
1203
1204 if (use_threaded_interrupts) {
1205 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1206 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1207 } else {
1208 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1209 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1210 }
3001082c
MW		 1211}
1212
22404274 1213static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1214{
22404274 1215 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1216
7be50e93 1217 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1218 nvmeq->sq_tail = 0;
1219 nvmeq->cq_head = 0;
1220 nvmeq->cq_phase = 1;
b80d5ccc 1221 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1222 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1223 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1224 dev->online_queues++;
7be50e93 1225 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1226}
1227
1228static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1229{
1230 struct nvme_dev *dev = nvmeq->dev;
1231 int result;
3f85d50b 1232
2b25d981 1233 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1234 result = adapter_alloc_cq(dev, qid, nvmeq);
1235 if (result < 0)
22404274 1236 return result;
b60503ba
MW		 1237
1238 result = adapter_alloc_sq(dev, qid, nvmeq);
1239 if (result < 0)
1240 goto release_cq;
1241
dca51e78 1242 result = queue_request_irq(nvmeq);
b60503ba
MW		 1243 if (result < 0)
1244 goto release_sq;
1245
22404274 1246 nvme_init_queue(nvmeq, qid);
22404274 1247 return result;
b60503ba
MW		 1248
1249 release_sq:
1250 adapter_delete_sq(dev, qid);
1251 release_cq:
1252 adapter_delete_cq(dev, qid);
22404274 1253 return result;
b60503ba
MW		 1254}
1255
f363b089 1256static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1257 .queue_rq = nvme_queue_rq,
77f02a7a 1258 .complete = nvme_pci_complete_rq,
a4aea562 1259 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1260 .exit_hctx = nvme_admin_exit_hctx,
a4aea562
MB		 1261 .init_request = nvme_admin_init_request,
1262 .timeout = nvme_timeout,
1263};
1264
f363b089 1265static const struct blk_mq_ops nvme_mq_ops = {
a4aea562 1266 .queue_rq = nvme_queue_rq,
77f02a7a 1267 .complete = nvme_pci_complete_rq,
a4aea562
MB		 1268 .init_hctx = nvme_init_hctx,
1269 .init_request = nvme_init_request,
dca51e78 1270 .map_queues = nvme_pci_map_queues,
a4aea562 1271 .timeout = nvme_timeout,
a0fa9647 1272 .poll = nvme_poll,
a4aea562
MB		 1273};
1274
ea191d2f
KB		 1275static void nvme_dev_remove_admin(struct nvme_dev *dev)
1276{
1c63dc66 1277 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1278 /*
1279 * If the controller was reset during removal, it's possible
1280 * user requests may be waiting on a stopped queue. Start the
1281 * queue to flush these to completion.
1282 */
1283 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1c63dc66 1284 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1285 blk_mq_free_tag_set(&dev->admin_tagset);
1286 }
1287}
1288
a4aea562
MB		 1289static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1290{
1c63dc66 1291 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1292 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1293 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c
KB		 1294
1295 /*
1296 * Subtract one to leave an empty queue entry for 'Full Queue'
1297 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1298 */
1299 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
a4aea562 1300 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1301 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
ac3dd5bd 1302 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
d3484991 1303 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1304 dev->admin_tagset.driver_data = dev;
1305
1306 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1307 return -ENOMEM;
1308
1c63dc66
CH		 1309 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1310 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1311 blk_mq_free_tag_set(&dev->admin_tagset);
1312 return -ENOMEM;
1313 }
1c63dc66 1314 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1315 nvme_dev_remove_admin(dev);
1c63dc66 1316 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1317 return -ENODEV;
1318 }
0fb59cbc 1319 } else
25646264 1320 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
a4aea562
MB		 1321
1322 return 0;
1323}
1324
8d85fce7 1325static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1326{
ba47e386 1327 int result;
b60503ba 1328 u32 aqa;
7a67cbea 1329 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
b60503ba
MW		 1330 struct nvme_queue *nvmeq;
1331
8ef2074d 1332 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
dfbac8c7
KB		 1333 NVME_CAP_NSSRC(cap) : 0;
1334
7a67cbea
CH		 1335 if (dev->subsystem &&
1336 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1337 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1338
5fd4ce1b 1339 result = nvme_disable_ctrl(&dev->ctrl, cap);
ba47e386
MW		 1340 if (result < 0)
1341 return result;
b60503ba 1342
a4aea562 1343 nvmeq = dev->queues[0];
cd638946 1344 if (!nvmeq) {
d3af3ecd
SL		 1345 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1346 dev_to_node(dev->dev));
cd638946
KB		 1347 if (!nvmeq)
1348 return -ENOMEM;
cd638946 1349 }
b60503ba
MW		 1350
1351 aqa = nvmeq->q_depth - 1;
1352 aqa |= aqa << 16;
1353
7a67cbea
CH		 1354 writel(aqa, dev->bar + NVME_REG_AQA);
1355 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1356 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1357
5fd4ce1b 1358 result = nvme_enable_ctrl(&dev->ctrl, cap);
025c557a 1359 if (result)
d4875622 1360 return result;
a4aea562 1361
2b25d981 1362 nvmeq->cq_vector = 0;
dca51e78 1363 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1364 if (result) {
1365 nvmeq->cq_vector = -1;
d4875622 1366 return result;
758dd7fd 1367 }
025c557a 1368
b60503ba
MW		 1369 return result;
1370}
1371
c875a709
GP		 1372static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1373{
1374
1375 /* If true, indicates loss of adapter communication, possibly by a
1376 * NVMe Subsystem reset.
1377 */
1378 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1379
1380 /* If there is a reset ongoing, we shouldn't reset again. */
82b057ca 1381 if (dev->ctrl.state == NVME_CTRL_RESETTING)
c875a709
GP		 1382 return false;
1383
1384 /* We shouldn't reset unless the controller is on fatal error state
1385 * _or_ if we lost the communication with it.
1386 */
1387 if (!(csts & NVME_CSTS_CFS) && !nssro)
1388 return false;
1389
1390 /* If PCI error recovery process is happening, we cannot reset or
1391 * the recovery mechanism will surely fail.
1392 */
1393 if (pci_channel_offline(to_pci_dev(dev->dev)))
1394 return false;
1395
1396 return true;
1397}
1398
d2a61918
AL		 1399static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1400{
1401 /* Read a config register to help see what died. */
1402 u16 pci_status;
1403 int result;
1404
1405 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1406 &pci_status);
1407 if (result == PCIBIOS_SUCCESSFUL)
9bdcfb10 1408 dev_warn(dev->ctrl.device,
d2a61918
AL		 1409 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1410 csts, pci_status);
1411 else
9bdcfb10 1412 dev_warn(dev->ctrl.device,
d2a61918
AL		 1413 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1414 csts, result);
1415}
1416
2d55cd5f 1417static void nvme_watchdog_timer(unsigned long data)
1fa6aead 1418{
2d55cd5f
CH		 1419 struct nvme_dev *dev = (struct nvme_dev *)data;
1420 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1fa6aead 1421
c875a709
GP		 1422 /* Skip controllers under certain specific conditions. */
1423 if (nvme_should_reset(dev, csts)) {
c5f6ce97 1424 if (!nvme_reset(dev))
d2a61918 1425 nvme_warn_reset(dev, csts);
2d55cd5f 1426 return;
1fa6aead 1427 }
2d55cd5f
CH		 1428
1429 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1fa6aead
MW		 1430}
1431
749941f2 1432static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1433{
949928c1 1434 unsigned i, max;
749941f2 1435 int ret = 0;
42f61420 1436
749941f2 1437 for (i = dev->queue_count; i <= dev->max_qid; i++) {
d3af3ecd
SL		 1438 /* vector == qid - 1, match nvme_create_queue */
1439 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1440 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
749941f2 1441 ret = -ENOMEM;
42f61420 1442 break;
749941f2
CH		 1443 }
1444 }
42f61420 1445
949928c1
KB		 1446 max = min(dev->max_qid, dev->queue_count - 1);
1447 for (i = dev->online_queues; i <= max; i++) {
749941f2 1448 ret = nvme_create_queue(dev->queues[i], i);
d4875622 1449 if (ret)
42f61420 1450 break;
27e8166c 1451 }
749941f2
CH		 1452
1453 /*
1454 * Ignore failing Create SQ/CQ commands, we can continue with less
1455 * than the desired aount of queues, and even a controller without
1456 * I/O queues an still be used to issue admin commands. This might
1457 * be useful to upgrade a buggy firmware for example.
1458 */
1459 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1460}
1461
202021c1
SB		 1462static ssize_t nvme_cmb_show(struct device *dev,
1463 struct device_attribute *attr,
1464 char *buf)
1465{
1466 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1467
c965809c 1468 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1469 ndev->cmbloc, ndev->cmbsz);
1470}
1471static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1472
8ffaadf7
JD		 1473static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1474{
1475 u64 szu, size, offset;
8ffaadf7
JD		 1476 resource_size_t bar_size;
1477 struct pci_dev *pdev = to_pci_dev(dev->dev);
1478 void __iomem *cmb;
1479 dma_addr_t dma_addr;
1480
7a67cbea 1481 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
8ffaadf7
JD		 1482 if (!(NVME_CMB_SZ(dev->cmbsz)))
1483 return NULL;
202021c1 1484 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1485
202021c1
SB		 1486 if (!use_cmb_sqes)
1487 return NULL;
8ffaadf7
JD		 1488
1489 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1490 size = szu * NVME_CMB_SZ(dev->cmbsz);
202021c1
SB		 1491 offset = szu * NVME_CMB_OFST(dev->cmbloc);
1492 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
8ffaadf7
JD		 1493
1494 if (offset > bar_size)
1495 return NULL;
1496
1497 /*
1498 * Controllers may support a CMB size larger than their BAR,
1499 * for example, due to being behind a bridge. Reduce the CMB to
1500 * the reported size of the BAR
1501 */
1502 if (size > bar_size - offset)
1503 size = bar_size - offset;
1504
202021c1 1505 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
8ffaadf7
JD		 1506 cmb = ioremap_wc(dma_addr, size);
1507 if (!cmb)
1508 return NULL;
1509
1510 dev->cmb_dma_addr = dma_addr;
1511 dev->cmb_size = size;
1512 return cmb;
1513}
1514
1515static inline void nvme_release_cmb(struct nvme_dev *dev)
1516{
1517 if (dev->cmb) {
1518 iounmap(dev->cmb);
1519 dev->cmb = NULL;
f63572df
JD		 1520 if (dev->cmbsz) {
1521 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1522 &dev_attr_cmb.attr, NULL);
1523 dev->cmbsz = 0;
1524 }
8ffaadf7
JD		 1525 }
1526}
1527
87ad72a5
CH		 1528static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1529{
1530 size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs);
1531 struct nvme_command c;
1532 u64 dma_addr;
1533 int ret;
1534
1535 dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len,
1536 DMA_TO_DEVICE);
1537 if (dma_mapping_error(dev->dev, dma_addr))
1538 return -ENOMEM;
1539
1540 memset(&c, 0, sizeof(c));
1541 c.features.opcode = nvme_admin_set_features;
1542 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1543 c.features.dword11 = cpu_to_le32(bits);
1544 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1545 ilog2(dev->ctrl.page_size));
1546 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1547 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1548 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1549
1550 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1551 if (ret) {
1552 dev_warn(dev->ctrl.device,
1553 "failed to set host mem (err %d, flags %#x).\n",
1554 ret, bits);
1555 }
1556 dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE);
1557 return ret;
1558}
1559
1560static void nvme_free_host_mem(struct nvme_dev *dev)
1561{
1562 int i;
1563
1564 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1565 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1566 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1567
1568 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1569 le64_to_cpu(desc->addr));
1570 }
1571
1572 kfree(dev->host_mem_desc_bufs);
1573 dev->host_mem_desc_bufs = NULL;
1574 kfree(dev->host_mem_descs);
1575 dev->host_mem_descs = NULL;
1576}
1577
1578static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1579{
1580 struct nvme_host_mem_buf_desc *descs;
1581 u32 chunk_size, max_entries, i = 0;
1582 void **bufs;
1583 u64 size, tmp;
1584
1585 /* start big and work our way down */
1586 chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER);
1587retry:
1588 tmp = (preferred + chunk_size - 1);
1589 do_div(tmp, chunk_size);
1590 max_entries = tmp;
1591 descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL);
1592 if (!descs)
1593 goto out;
1594
1595 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1596 if (!bufs)
1597 goto out_free_descs;
1598
1599 for (size = 0; size < preferred; size += chunk_size) {
1600 u32 len = min_t(u64, chunk_size, preferred - size);
1601 dma_addr_t dma_addr;
1602
1603 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1604 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1605 if (!bufs[i])
1606 break;
1607
1608 descs[i].addr = cpu_to_le64(dma_addr);
1609 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1610 i++;
1611 }
1612
1613 if (!size || (min && size < min)) {
1614 dev_warn(dev->ctrl.device,
1615 "failed to allocate host memory buffer.\n");
1616 goto out_free_bufs;
1617 }
1618
1619 dev_info(dev->ctrl.device,
1620 "allocated %lld MiB host memory buffer.\n",
1621 size >> ilog2(SZ_1M));
1622 dev->nr_host_mem_descs = i;
1623 dev->host_mem_size = size;
1624 dev->host_mem_descs = descs;
1625 dev->host_mem_desc_bufs = bufs;
1626 return 0;
1627
1628out_free_bufs:
1629 while (--i >= 0) {
1630 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1631
1632 dma_free_coherent(dev->dev, size, bufs[i],
1633 le64_to_cpu(descs[i].addr));
1634 }
1635
1636 kfree(bufs);
1637out_free_descs:
1638 kfree(descs);
1639out:
1640 /* try a smaller chunk size if we failed early */
1641 if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) {
1642 chunk_size /= 2;
1643 goto retry;
1644 }
1645 dev->host_mem_descs = NULL;
1646 return -ENOMEM;
1647}
1648
1649static void nvme_setup_host_mem(struct nvme_dev *dev)
1650{
1651 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1652 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1653 u64 min = (u64)dev->ctrl.hmmin * 4096;
1654 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1655
1656 preferred = min(preferred, max);
1657 if (min > max) {
1658 dev_warn(dev->ctrl.device,
1659 "min host memory (%lld MiB) above limit (%d MiB).\n",
1660 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1661 nvme_free_host_mem(dev);
1662 return;
1663 }
1664
1665 /*
1666 * If we already have a buffer allocated check if we can reuse it.
1667 */
1668 if (dev->host_mem_descs) {
1669 if (dev->host_mem_size >= min)
1670 enable_bits |= NVME_HOST_MEM_RETURN;
1671 else
1672 nvme_free_host_mem(dev);
1673 }
1674
1675 if (!dev->host_mem_descs) {
1676 if (nvme_alloc_host_mem(dev, min, preferred))
1677 return;
1678 }
1679
1680 if (nvme_set_host_mem(dev, enable_bits))
1681 nvme_free_host_mem(dev);
1682}
1683
9d713c2b
KB		 1684static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1685{
b80d5ccc 1686 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 1687}
1688
8d85fce7 1689static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1690{
a4aea562 1691 struct nvme_queue *adminq = dev->queues[0];
e75ec752 1692 struct pci_dev *pdev = to_pci_dev(dev->dev);
dca51e78 1693 int result, nr_io_queues, size;
b60503ba 1694
2800b8e7 1695 nr_io_queues = num_online_cpus();
9a0be7ab
CH		 1696 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1697 if (result < 0)
1b23484b 1698 return result;
9a0be7ab 1699
f5fa90dc 1700 if (nr_io_queues == 0)
a5229050 1701 return 0;
b60503ba 1702
8ffaadf7
JD		 1703 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1704 result = nvme_cmb_qdepth(dev, nr_io_queues,
1705 sizeof(struct nvme_command));
1706 if (result > 0)
1707 dev->q_depth = result;
1708 else
1709 nvme_release_cmb(dev);
1710 }
1711
9d713c2b
KB		 1712 size = db_bar_size(dev, nr_io_queues);
1713 if (size > 8192) {
f1938f6e 1714 iounmap(dev->bar);
9d713c2b
KB		 1715 do {
1716 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1717 if (dev->bar)
1718 break;
1719 if (!--nr_io_queues)
1720 return -ENOMEM;
1721 size = db_bar_size(dev, nr_io_queues);
1722 } while (1);
7a67cbea 1723 dev->dbs = dev->bar + 4096;
5a92e700 1724 adminq->q_db = dev->dbs;
f1938f6e
MW		 1725 }
1726
9d713c2b 1727 /* Deregister the admin queue's interrupt */
0ff199cb 1728 pci_free_irq(pdev, 0, adminq);
9d713c2b 1729
e32efbfc
JA		 1730 /*
1731 * If we enable msix early due to not intx, disable it again before
1732 * setting up the full range we need.
1733 */
dca51e78
CH		 1734 pci_free_irq_vectors(pdev);
1735 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1736 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1737 if (nr_io_queues <= 0)
1738 return -EIO;
1739 dev->max_qid = nr_io_queues;
fa08a396 1740
063a8096
MW		 1741 /*
1742 * Should investigate if there's a performance win from allocating
1743 * more queues than interrupt vectors; it might allow the submission
1744 * path to scale better, even if the receive path is limited by the
1745 * number of interrupts.
1746 */
063a8096 1747
dca51e78 1748 result = queue_request_irq(adminq);
758dd7fd
JD		 1749 if (result) {
1750 adminq->cq_vector = -1;
d4875622 1751 return result;
758dd7fd 1752 }
749941f2 1753 return nvme_create_io_queues(dev);
b60503ba
MW		 1754}
1755
2a842aca 1756static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 1757{
db3cbfff 1758 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 1759
db3cbfff
KB		 1760 blk_mq_free_request(req);
1761 complete(&nvmeq->dev->ioq_wait);
a5768aa8
KB		 1762}
1763
2a842aca 1764static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 1765{
db3cbfff 1766 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 1767
db3cbfff
KB		 1768 if (!error) {
1769 unsigned long flags;
1770
2e39e0f6
ML		 1771 /*
1772 * We might be called with the AQ q_lock held
1773 * and the I/O queue q_lock should always
1774 * nest inside the AQ one.
1775 */
1776 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1777 SINGLE_DEPTH_NESTING);
db3cbfff
KB		 1778 nvme_process_cq(nvmeq);
1779 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a5768aa8 1780 }
db3cbfff
KB		 1781
1782 nvme_del_queue_end(req, error);
a5768aa8
KB		 1783}
1784
db3cbfff 1785static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 1786{
db3cbfff
KB		 1787 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1788 struct request *req;
1789 struct nvme_command cmd;
bda4e0fb 1790
db3cbfff
KB		 1791 memset(&cmd, 0, sizeof(cmd));
1792 cmd.delete_queue.opcode = opcode;
1793 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 1794
eb71f435 1795 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 1796 if (IS_ERR(req))
1797 return PTR_ERR(req);
bda4e0fb 1798
db3cbfff
KB		 1799 req->timeout = ADMIN_TIMEOUT;
1800 req->end_io_data = nvmeq;
1801
1802 blk_execute_rq_nowait(q, NULL, req, false,
1803 opcode == nvme_admin_delete_cq ?
1804 nvme_del_cq_end : nvme_del_queue_end);
1805 return 0;
bda4e0fb
KB		 1806}
1807
70659060 1808static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
a5768aa8 1809{
70659060 1810 int pass;
db3cbfff
KB		 1811 unsigned long timeout;
1812 u8 opcode = nvme_admin_delete_sq;
a5768aa8 1813
db3cbfff 1814 for (pass = 0; pass < 2; pass++) {
014a0d60 1815 int sent = 0, i = queues;
db3cbfff
KB		 1816
1817 reinit_completion(&dev->ioq_wait);
1818 retry:
1819 timeout = ADMIN_TIMEOUT;
c21377f8
GKB		 1820 for (; i > 0; i--, sent++)
1821 if (nvme_delete_queue(dev->queues[i], opcode))
db3cbfff 1822 break;
c21377f8 1823
db3cbfff
KB		 1824 while (sent--) {
1825 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1826 if (timeout == 0)
1827 return;
1828 if (i)
1829 goto retry;
1830 }
1831 opcode = nvme_admin_delete_cq;
1832 }
a5768aa8
KB		 1833}
1834
422ef0c7
MW		 1835/*
1836 * Return: error value if an error occurred setting up the queues or calling
1837 * Identify Device. 0 if these succeeded, even if adding some of the
1838 * namespaces failed. At the moment, these failures are silent. TBD which
1839 * failures should be reported.
1840 */
8d85fce7 1841static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 1842{
5bae7f73 1843 if (!dev->ctrl.tagset) {
ffe7704d
KB		 1844 dev->tagset.ops = &nvme_mq_ops;
1845 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1846 dev->tagset.timeout = NVME_IO_TIMEOUT;
1847 dev->tagset.numa_node = dev_to_node(dev->dev);
1848 dev->tagset.queue_depth =
a4aea562 1849 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ffe7704d
KB		 1850 dev->tagset.cmd_size = nvme_cmd_size(dev);
1851 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1852 dev->tagset.driver_data = dev;
b60503ba 1853
ffe7704d
KB		 1854 if (blk_mq_alloc_tag_set(&dev->tagset))
1855 return 0;
5bae7f73 1856 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 1857
1858 nvme_dbbuf_set(dev);
949928c1
KB		 1859 } else {
1860 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1861
1862 /* Free previously allocated queues that are no longer usable */
1863 nvme_free_queues(dev, dev->online_queues);
ffe7704d 1864 }
949928c1 1865
e1e5e564 1866 return 0;
b60503ba
MW		 1867}
1868
b00a726a 1869static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 1870{
42f61420 1871 u64 cap;
b00a726a 1872 int result = -ENOMEM;
e75ec752 1873 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 1874
1875 if (pci_enable_device_mem(pdev))
1876 return result;
1877
0877cb0d 1878 pci_set_master(pdev);
0877cb0d 1879
e75ec752
CH		 1880 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1881 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 1882 goto disable;
0877cb0d 1883
7a67cbea 1884 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 1885 result = -ENODEV;
b00a726a 1886 goto disable;
0e53d180 1887 }
e32efbfc
JA		 1888
1889 /*
a5229050
KB		 1890 * Some devices and/or platforms don't advertise or work with INTx
1891 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1892 * adjust this later.
e32efbfc 1893 */
dca51e78
CH		 1894 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1895 if (result < 0)
1896 return result;
e32efbfc 1897
7a67cbea
CH		 1898 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1899
42f61420
KB		 1900 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1901 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
7a67cbea 1902 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 1903
1904 /*
1905 * Temporary fix for the Apple controller found in the MacBook8,1 and
1906 * some MacBook7,1 to avoid controller resets and data loss.
1907 */
1908 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1909 dev->q_depth = 2;
9bdcfb10
CH		 1910 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
1911 "set queue depth=%u to work around controller resets\n",
1f390c1f
SG		 1912 dev->q_depth);
1913 }
1914
202021c1
SB		 1915 /*
1916 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1917 * populate sysfs if a CMB is implemented. Note that we add the
1918 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1919 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1920 * NULL as final argument to sysfs_add_file_to_group.
1921 */
1922
8ef2074d 1923 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
8ffaadf7 1924 dev->cmb = nvme_map_cmb(dev);
0877cb0d 1925
202021c1
SB		 1926 if (dev->cmbsz) {
1927 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1928 &dev_attr_cmb.attr, NULL))
9bdcfb10 1929 dev_warn(dev->ctrl.device,
202021c1
SB		 1930 "failed to add sysfs attribute for CMB\n");
1931 }
1932 }
1933
a0a3408e
KB		 1934 pci_enable_pcie_error_reporting(pdev);
1935 pci_save_state(pdev);
0877cb0d
KB		 1936 return 0;
1937
1938 disable:
0877cb0d
KB		 1939 pci_disable_device(pdev);
1940 return result;
1941}
1942
1943static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 1944{
1945 if (dev->bar)
1946 iounmap(dev->bar);
a1f447b3 1947 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 1948}
1949
1950static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 1951{
e75ec752
CH		 1952 struct pci_dev *pdev = to_pci_dev(dev->dev);
1953
f63572df 1954 nvme_release_cmb(dev);
dca51e78 1955 pci_free_irq_vectors(pdev);
0877cb0d 1956
a0a3408e
KB		 1957 if (pci_is_enabled(pdev)) {
1958 pci_disable_pcie_error_reporting(pdev);
e75ec752 1959 pci_disable_device(pdev);
4d115420 1960 }
4d115420
KB		 1961}
1962
a5cdb68c 1963static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 1964{
70659060 1965 int i, queues;
302ad8cc
KB		 1966 bool dead = true;
1967 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 1968
2d55cd5f 1969 del_timer_sync(&dev->watchdog_timer);
1fa6aead 1970
77bf25ea 1971 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 1972 if (pci_is_enabled(pdev)) {
1973 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1974
1975 if (dev->ctrl.state == NVME_CTRL_LIVE)
1976 nvme_start_freeze(&dev->ctrl);
1977 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
1978 pdev->error_state != pci_channel_io_normal);
c9d3bf88 1979 }
c21377f8 1980
302ad8cc
KB		 1981 /*
1982 * Give the controller a chance to complete all entered requests if
1983 * doing a safe shutdown.
1984 */
87ad72a5
CH		 1985 if (!dead) {
1986 if (shutdown)
1987 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
1988
1989 /*
1990 * If the controller is still alive tell it to stop using the
1991 * host memory buffer. In theory the shutdown / reset should
1992 * make sure that it doesn't access the host memoery anymore,
1993 * but I'd rather be safe than sorry..
1994 */
1995 if (dev->host_mem_descs)
1996 nvme_set_host_mem(dev, 0);
1997
1998 }
302ad8cc
KB		 1999 nvme_stop_queues(&dev->ctrl);
2000
70659060 2001 queues = dev->online_queues - 1;
c21377f8
GKB		 2002 for (i = dev->queue_count - 1; i > 0; i--)
2003 nvme_suspend_queue(dev->queues[i]);
2004
302ad8cc 2005 if (dead) {
82469c59
GKB		 2006 /* A device might become IO incapable very soon during
2007 * probe, before the admin queue is configured. Thus,
2008 * queue_count can be 0 here.
2009 */
2010 if (dev->queue_count)
2011 nvme_suspend_queue(dev->queues[0]);
4d115420 2012 } else {
70659060 2013 nvme_disable_io_queues(dev, queues);
a5cdb68c 2014 nvme_disable_admin_queue(dev, shutdown);
4d115420 2015 }
b00a726a 2016 nvme_pci_disable(dev);
07836e65 2017
e1958e65
ML		 2018 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2019 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2020
2021 /*
2022 * The driver will not be starting up queues again if shutting down so
2023 * must flush all entered requests to their failed completion to avoid
2024 * deadlocking blk-mq hot-cpu notifier.
2025 */
2026 if (shutdown)
2027 nvme_start_queues(&dev->ctrl);
77bf25ea 2028 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2029}
2030
091b6092
MW		 2031static int nvme_setup_prp_pools(struct nvme_dev *dev)
2032{
e75ec752 2033 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2034 PAGE_SIZE, PAGE_SIZE, 0);
2035 if (!dev->prp_page_pool)
2036 return -ENOMEM;
2037
99802a7a 2038 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2039 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2040 256, 256, 0);
2041 if (!dev->prp_small_pool) {
2042 dma_pool_destroy(dev->prp_page_pool);
2043 return -ENOMEM;
2044 }
091b6092
MW		 2045 return 0;
2046}
2047
2048static void nvme_release_prp_pools(struct nvme_dev *dev)
2049{
2050 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2051 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2052}
2053
1673f1f0 2054static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2055{
1673f1f0 2056 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2057
f9f38e33 2058 nvme_dbbuf_dma_free(dev);
e75ec752 2059 put_device(dev->dev);
4af0e21c
KB		 2060 if (dev->tagset.tags)
2061 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2062 if (dev->ctrl.admin_q)
2063 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2064 kfree(dev->queues);
e286bcfc 2065 free_opal_dev(dev->ctrl.opal_dev);
5e82e952
KB		 2066 kfree(dev);
2067}
2068
f58944e2
KB		 2069static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2070{
237045fc 2071 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2
KB		 2072
2073 kref_get(&dev->ctrl.kref);
69d9a99c 2074 nvme_dev_disable(dev, false);
f58944e2
KB		 2075 if (!schedule_work(&dev->remove_work))
2076 nvme_put_ctrl(&dev->ctrl);
2077}
2078
fd634f41 2079static void nvme_reset_work(struct work_struct *work)
5e82e952 2080{
fd634f41 2081 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
a98e58e5 2082 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2083 int result = -ENODEV;
5e82e952 2084
82b057ca 2085 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2086 goto out;
5e82e952 2087
fd634f41
CH		 2088 /*
2089 * If we're called to reset a live controller first shut it down before
2090 * moving on.
2091 */
b00a726a 2092 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2093 nvme_dev_disable(dev, false);
5e82e952 2094
b00a726a 2095 result = nvme_pci_enable(dev);
f0b50732 2096 if (result)
3cf519b5 2097 goto out;
f0b50732
KB		 2098
2099 result = nvme_configure_admin_queue(dev);
2100 if (result)
f58944e2 2101 goto out;
f0b50732 2102
a4aea562 2103 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2104 result = nvme_alloc_admin_tags(dev);
2105 if (result)
f58944e2 2106 goto out;
b9afca3e 2107
ce4541f4
CH		 2108 result = nvme_init_identify(&dev->ctrl);
2109 if (result)
f58944e2 2110 goto out;
ce4541f4 2111
e286bcfc
SB		 2112 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2113 if (!dev->ctrl.opal_dev)
2114 dev->ctrl.opal_dev =
2115 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2116 else if (was_suspend)
2117 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2118 } else {
2119 free_opal_dev(dev->ctrl.opal_dev);
2120 dev->ctrl.opal_dev = NULL;
4f1244c8 2121 }
a98e58e5 2122
f9f38e33
HK		 2123 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2124 result = nvme_dbbuf_dma_alloc(dev);
2125 if (result)
2126 dev_warn(dev->dev,
2127 "unable to allocate dma for dbbuf\n");
2128 }
2129
87ad72a5
CH		 2130 if (dev->ctrl.hmpre)
2131 nvme_setup_host_mem(dev);
2132
f0b50732 2133 result = nvme_setup_io_queues(dev);
badc34d4 2134 if (result)
f58944e2 2135 goto out;
f0b50732 2136
21f033f7
KB		 2137 /*
2138 * A controller that can not execute IO typically requires user
2139 * intervention to correct. For such degraded controllers, the driver
2140 * should not submit commands the user did not request, so skip
2141 * registering for asynchronous event notification on this condition.
2142 */
f866fc42
CH		 2143 if (dev->online_queues > 1)
2144 nvme_queue_async_events(&dev->ctrl);
3cf519b5 2145
2d55cd5f 2146 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
3cf519b5 2147
2659e57b
CH		 2148 /*
2149 * Keep the controller around but remove all namespaces if we don't have
2150 * any working I/O queue.
2151 */
3cf519b5 2152 if (dev->online_queues < 2) {
1b3c47c1 2153 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2154 nvme_kill_queues(&dev->ctrl);
5bae7f73 2155 nvme_remove_namespaces(&dev->ctrl);
3cf519b5 2156 } else {
25646264 2157 nvme_start_queues(&dev->ctrl);
302ad8cc 2158 nvme_wait_freeze(&dev->ctrl);
3cf519b5 2159 nvme_dev_add(dev);
302ad8cc 2160 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2161 }
2162
bb8d261e
CH		 2163 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2164 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2165 goto out;
2166 }
92911a55
CH		 2167
2168 if (dev->online_queues > 1)
5955be21 2169 nvme_queue_scan(&dev->ctrl);
3cf519b5 2170 return;
f0b50732 2171
3cf519b5 2172 out:
f58944e2 2173 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2174}
2175
5c8809e6 2176static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2177{
5c8809e6 2178 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2179 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458 2180
69d9a99c 2181 nvme_kill_queues(&dev->ctrl);
9a6b9458 2182 if (pci_get_drvdata(pdev))
921920ab 2183 device_release_driver(&pdev->dev);
1673f1f0 2184 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2185}
2186
4cc06521 2187static int nvme_reset(struct nvme_dev *dev)
9a6b9458 2188{
1c63dc66 2189 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
4cc06521 2190 return -ENODEV;
82b057ca
RP		 2191 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
2192 return -EBUSY;
846cc05f
CH		 2193 if (!queue_work(nvme_workq, &dev->reset_work))
2194 return -EBUSY;
846cc05f 2195 return 0;
9a6b9458
KB		 2196}
2197
1c63dc66 2198static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2199{
1c63dc66 2200 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2201 return 0;
9ca97374
TH		 2202}
2203
5fd4ce1b 2204static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2205{
5fd4ce1b
CH		 2206 writel(val, to_nvme_dev(ctrl)->bar + off);
2207 return 0;
2208}
4cc06521 2209
7fd8930f
CH		 2210static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2211{
2212 *val = readq(to_nvme_dev(ctrl)->bar + off);
2213 return 0;
4cc06521
KB		 2214}
2215
f3ca80fc
CH		 2216static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2217{
c5f6ce97
KB		 2218 struct nvme_dev *dev = to_nvme_dev(ctrl);
2219 int ret = nvme_reset(dev);
2220
2221 if (!ret)
2222 flush_work(&dev->reset_work);
2223 return ret;
4cc06521 2224}
f3ca80fc 2225
1c63dc66 2226static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2227 .name = "pcie",
e439bb12 2228 .module = THIS_MODULE,
c81bfba9 2229 .flags = NVME_F_METADATA_SUPPORTED,
1c63dc66 2230 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2231 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2232 .reg_read64 = nvme_pci_reg_read64,
f3ca80fc 2233 .reset_ctrl = nvme_pci_reset_ctrl,
1673f1f0 2234 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2235 .submit_async_event = nvme_pci_submit_async_event,
1c63dc66 2236};
4cc06521 2237
b00a726a
KB		 2238static int nvme_dev_map(struct nvme_dev *dev)
2239{
b00a726a
KB		 2240 struct pci_dev *pdev = to_pci_dev(dev->dev);
2241
a1f447b3 2242 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2243 return -ENODEV;
2244
2245 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2246 if (!dev->bar)
2247 goto release;
2248
9fa196e7 2249 return 0;
b00a726a 2250 release:
9fa196e7
MG		 2251 pci_release_mem_regions(pdev);
2252 return -ENODEV;
b00a726a
KB		 2253}
2254
ff5350a8
AL		 2255static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
2256{
2257 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2258 /*
2259 * Several Samsung devices seem to drop off the PCIe bus
2260 * randomly when APST is on and uses the deepest sleep state.
2261 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2262 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2263 * 950 PRO 256GB", but it seems to be restricted to two Dell
2264 * laptops.
2265 */
2266 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2267 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2268 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2269 return NVME_QUIRK_NO_DEEPEST_PS;
2270 }
2271
2272 return 0;
2273}
2274
8d85fce7 2275static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2276{
a4aea562 2277 int node, result = -ENOMEM;
b60503ba 2278 struct nvme_dev *dev;
ff5350a8 2279 unsigned long quirks = id->driver_data;
b60503ba 2280
a4aea562
MB		 2281 node = dev_to_node(&pdev->dev);
2282 if (node == NUMA_NO_NODE)
2fa84351 2283 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2284
2285 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2286 if (!dev)
2287 return -ENOMEM;
a4aea562
MB		 2288 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2289 GFP_KERNEL, node);
b60503ba
MW		 2290 if (!dev->queues)
2291 goto free;
2292
e75ec752 2293 dev->dev = get_device(&pdev->dev);
9a6b9458 2294 pci_set_drvdata(pdev, dev);
1c63dc66 2295
b00a726a
KB		 2296 result = nvme_dev_map(dev);
2297 if (result)
2298 goto free;
2299
f3ca80fc 2300 INIT_WORK(&dev->reset_work, nvme_reset_work);
5c8809e6 2301 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2d55cd5f
CH		 2302 setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
2303 (unsigned long)dev);
77bf25ea 2304 mutex_init(&dev->shutdown_lock);
db3cbfff 2305 init_completion(&dev->ioq_wait);
b60503ba 2306
091b6092
MW		 2307 result = nvme_setup_prp_pools(dev);
2308 if (result)
a96d4f5c 2309 goto put_pci;
4cc06521 2310
ff5350a8
AL		 2311 quirks |= check_dell_samsung_bug(pdev);
2312
f3ca80fc 2313 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
ff5350a8 2314 quirks);
4cc06521 2315 if (result)
2e1d8448 2316 goto release_pools;
740216fc 2317
82b057ca 2318 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
1b3c47c1
SG		 2319 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2320
92f7a162 2321 queue_work(nvme_workq, &dev->reset_work);
b60503ba
MW		 2322 return 0;
2323
0877cb0d 2324 release_pools:
091b6092 2325 nvme_release_prp_pools(dev);
a96d4f5c 2326 put_pci:
e75ec752 2327 put_device(dev->dev);
b00a726a 2328 nvme_dev_unmap(dev);
b60503ba
MW		 2329 free:
2330 kfree(dev->queues);
b60503ba
MW		 2331 kfree(dev);
2332 return result;
2333}
2334
f0d54a54
KB		 2335static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2336{
a6739479 2337 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 2338
a6739479 2339 if (prepare)
a5cdb68c 2340 nvme_dev_disable(dev, false);
a6739479 2341 else
c5f6ce97 2342 nvme_reset(dev);
f0d54a54
KB		 2343}
2344
09ece142
KB		 2345static void nvme_shutdown(struct pci_dev *pdev)
2346{
2347 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2348 nvme_dev_disable(dev, true);
09ece142
KB		 2349}
2350
f58944e2
KB		 2351/*
2352 * The driver's remove may be called on a device in a partially initialized
2353 * state. This function must not have any dependencies on the device state in
2354 * order to proceed.
2355 */
8d85fce7 2356static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2357{
2358 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2359
bb8d261e
CH		 2360 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2361
82b057ca 2362 cancel_work_sync(&dev->reset_work);
9a6b9458 2363 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2364
6db28eda 2365 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2366 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
6db28eda
KB		 2367 nvme_dev_disable(dev, false);
2368 }
0ff9d4e1 2369
9bf2b972 2370 flush_work(&dev->reset_work);
53029b04 2371 nvme_uninit_ctrl(&dev->ctrl);
a5cdb68c 2372 nvme_dev_disable(dev, true);
87ad72a5 2373 nvme_free_host_mem(dev);
a4aea562 2374 nvme_dev_remove_admin(dev);
a1a5ef99 2375 nvme_free_queues(dev, 0);
9a6b9458 2376 nvme_release_prp_pools(dev);
b00a726a 2377 nvme_dev_unmap(dev);
1673f1f0 2378 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2379}
2380
13880f5b
KB		 2381static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2382{
2383 int ret = 0;
2384
2385 if (numvfs == 0) {
2386 if (pci_vfs_assigned(pdev)) {
2387 dev_warn(&pdev->dev,
2388 "Cannot disable SR-IOV VFs while assigned\n");
2389 return -EPERM;
2390 }
2391 pci_disable_sriov(pdev);
2392 return 0;
2393 }
2394
2395 ret = pci_enable_sriov(pdev, numvfs);
2396 return ret ? ret : numvfs;
2397}
2398
671a6018 2399#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2400static int nvme_suspend(struct device *dev)
2401{
2402 struct pci_dev *pdev = to_pci_dev(dev);
2403 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2404
a5cdb68c 2405 nvme_dev_disable(ndev, true);
cd638946
KB		 2406 return 0;
2407}
2408
2409static int nvme_resume(struct device *dev)
2410{
2411 struct pci_dev *pdev = to_pci_dev(dev);
2412 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2413
c5f6ce97 2414 nvme_reset(ndev);
9a6b9458 2415 return 0;
cd638946 2416}
671a6018 2417#endif
cd638946
KB		 2418
2419static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2420
a0a3408e
KB		 2421static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2422 pci_channel_state_t state)
2423{
2424 struct nvme_dev *dev = pci_get_drvdata(pdev);
2425
2426 /*
2427 * A frozen channel requires a reset. When detected, this method will
2428 * shutdown the controller to quiesce. The controller will be restarted
2429 * after the slot reset through driver's slot_reset callback.
2430 */
a0a3408e
KB		 2431 switch (state) {
2432 case pci_channel_io_normal:
2433 return PCI_ERS_RESULT_CAN_RECOVER;
2434 case pci_channel_io_frozen:
d011fb31
KB		 2435 dev_warn(dev->ctrl.device,
2436 "frozen state error detected, reset controller\n");
a5cdb68c 2437 nvme_dev_disable(dev, false);
a0a3408e
KB		 2438 return PCI_ERS_RESULT_NEED_RESET;
2439 case pci_channel_io_perm_failure:
d011fb31
KB		 2440 dev_warn(dev->ctrl.device,
2441 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2442 return PCI_ERS_RESULT_DISCONNECT;
2443 }
2444 return PCI_ERS_RESULT_NEED_RESET;
2445}
2446
2447static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2448{
2449 struct nvme_dev *dev = pci_get_drvdata(pdev);
2450
1b3c47c1 2451 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2452 pci_restore_state(pdev);
c5f6ce97 2453 nvme_reset(dev);
a0a3408e
KB		 2454 return PCI_ERS_RESULT_RECOVERED;
2455}
2456
2457static void nvme_error_resume(struct pci_dev *pdev)
2458{
2459 pci_cleanup_aer_uncorrect_error_status(pdev);
2460}
2461
1d352035 2462static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2463 .error_detected = nvme_error_detected,
b60503ba
MW		 2464 .slot_reset = nvme_slot_reset,
2465 .resume = nvme_error_resume,
f0d54a54 2466 .reset_notify = nvme_reset_notify,
b60503ba
MW		 2467};
2468
6eb0d698 2469static const struct pci_device_id nvme_id_table[] = {
106198ed 2470 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2471 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2472 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2473 { PCI_VDEVICE(INTEL, 0x0a53),
2474 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2475 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2476 { PCI_VDEVICE(INTEL, 0x0a54),
2477 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2478 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0
AL		 2479 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2480 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
540c801c
KB		 2481 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2482 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
54adc010
GP		 2483 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2484 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2485 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2486 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
b60503ba 2487 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2488 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2489 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2490 { 0, }
2491};
2492MODULE_DEVICE_TABLE(pci, nvme_id_table);
2493
2494static struct pci_driver nvme_driver = {
2495 .name = "nvme",
2496 .id_table = nvme_id_table,
2497 .probe = nvme_probe,
8d85fce7 2498 .remove = nvme_remove,
09ece142 2499 .shutdown = nvme_shutdown,
cd638946
KB		 2500 .driver = {
2501 .pm = &nvme_dev_pm_ops,
2502 },
13880f5b 2503 .sriov_configure = nvme_pci_sriov_configure,
b60503ba
MW		 2504 .err_handler = &nvme_err_handler,
2505};
2506
2507static int __init nvme_init(void)
2508{
0ac13140 2509 int result;
1fa6aead 2510
92f7a162 2511 nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
9a6b9458 2512 if (!nvme_workq)
b9afca3e 2513 return -ENOMEM;
9a6b9458 2514
f3db22fe
KB		 2515 result = pci_register_driver(&nvme_driver);
2516 if (result)
576d55d6 2517 destroy_workqueue(nvme_workq);
b60503ba
MW		 2518 return result;
2519}
2520
2521static void __exit nvme_exit(void)
2522{
2523 pci_unregister_driver(&nvme_driver);
9a6b9458 2524 destroy_workqueue(nvme_workq);
21bd78bc 2525 _nvme_check_size();
b60503ba
MW		 2526}
2527
2528MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2529MODULE_LICENSE("GPL");
c78b4713 2530MODULE_VERSION("1.0");
b60503ba
MW		 2531module_init(nvme_init);
2532module_exit(nvme_exit);
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