Qin Long [Tue, 27 Sep 2016 08:54:04 +0000 (16:54 +0800)]
CryptoPkg/OpensslLib: Upgrade OpenSSL version to 1.0.2j
Two official releases (OpenSSL 1.0.2i and 1.0.2j) were available
with several severity fixes at 22-Sep-2016 and 26-Sep-2016.
Refer to
https://www.openssl.org/news/secadv/20160922.txt and
https://www.openssl.org/news/secadv/20160926.txt.
This patch is to upgrade the supported OpenSSL version in
CryptoPkg/OpensslLib to catch the latest release 1.0.2j.
Cc: Ting Ye <ting.ye@intel.com> Cc: David Woodhouse <David.Woodhouse@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Qin Long <qin.long@intel.com> Reviewed-by: Ting Ye <ting.ye@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
Ruiyu Ni [Thu, 29 Sep 2016 02:40:28 +0000 (10:40 +0800)]
MdeModulePkg: Remove ImageDecoderLib and BmpImageDecoderLib
The two libraries are created to support old BootLogoLib to
decode the images. Due to the new BootLogoLib starts using
HiiImageEx interfaces, the two libraries are not needed.
Several issues exist in TCG2 PP
1. TCG2 PP use NVS PPRQ/PPRM as PP parameter as well as current
PP state cache. But it doesn't handle PP set failure case
2. TCG2 PP Submit TPM Operation Request to Pre-OS Environment forgets
to clean PPRM
3. Potential alignment issue
Ruiyu Ni [Fri, 23 Sep 2016 08:03:47 +0000 (16:03 +0800)]
MdeModulePkg/Logo: Add LogoDxe module
LogoDxe embeds the image resource in the PE resource section, then
it produces Platform Logo protocol which can return the images
in pixel format.
HiiImageEx protocol is responsible to decode the JPEG/PNG images
to pixel format. LogoDxe driver uses HiiImageEx protocol.
Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Ruiyu Ni [Fri, 23 Sep 2016 07:54:01 +0000 (15:54 +0800)]
MdeModulePkg/BootLogoLib&PlatformLogo: Use HII data types in parameters
1. Change PlatformLogo protocol to return EFI_IMAGE_INPUT instead of
RAW image data. PlatformLogo implementation can use HiiImageEx to
decode the image if it's JPEG or PNG format.
2. Change BootLogoLib to consume the new PlatformLogo protocol.
3. Change BootLogoEnableLogo() to only use images returned from
PlatformLogo protocol.
Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
According to UEFI spec, NewImageEx()/SetImageEx()/DrawImageEx()
implicitly call the non-Ex version interface
of HiiImage protocol.
GetImageEx()/DrawImageIdEx() are the enhanced version of
GetImage()/DrawImageId(), which can support decoding JPEG/PNG
through the help of HiiImageDecoder protocol.
Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Ruiyu Ni [Wed, 21 Sep 2016 04:55:00 +0000 (12:55 +0800)]
MdeModulePkg/HiiDatabase: Update HiiImage to support PNG/JPEG
1. Update GetImageIdOrAddress() to recognize PNG/JPEG image block.
A offset calculation bug was fixed.
2. Update HiiGetImage() comments to say PNG/JPEG support is provided
by HiiImageEx
3. Update HiiSetImage() to support replacing a PNG/JPEG image block
with a new image
Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Ruiyu Ni [Mon, 26 Sep 2016 07:39:54 +0000 (15:39 +0800)]
MdePkg/HiiImage.h: Include GraphicsOutput.h
HiiImage.h uses EFI_GRAPHICS_OUTPUT_BLT_PIXEL which is defined in
GraphicsOutput.h. Include GraphicsOutput.h to avoid build failure
from consumer of HiiImage protocol.
MdePkg/BaseMemoryLibOptDxe: replace deprecated uses of IT blocks
The ARM architecture version 8 deprecates all uses of the IT instruction
except cases where it is followed by a single narrow instruction. So
replace any occurrences with equivalent sequences that adhere to the
new rules.
MdePkg/BaseMemoryLibOptDxe ARM: fix Thumb-2 bug in ScanMem()
The ARM ScanMem() in BaseMemoryLibOptDxe contains code from the open
source cortex-strings library, and inherited a bug from it where the
conditional execution of a sequence of instructions is erroneously
made dependent on the same condition. Since the final 'addeq' is
supposed to be dependent on the preceding 'tsteq' instruction, they
cannot be part of the same IT block.
BaseTools: support generating image package from BMP/JPEG/PNG files
BaseTools add support to generating image package from BMP/JPEG/PNG
files.
1) New file type *.idf Image definition file to describe HII image
resource. It is the ASCII text file, and includes one or more "#image
IMAGE_ID [TRANSPARENT] ImageFileName".
2) New IMAGE_TOKEN macro is used to refer to IMAGE_ID.
3) New AutoGen header file $(MODULE_NAME)ImgDefs.h to include the
generated ImageId definition.
4) New $(MODULE_NAME)Idf.hpk or $(MODULE_NAME)Images are generated
as the output binary HII image package.
SecurityPkg: Tcg: New field for User Confirmation Status
Add a new field in TcgNVS for PP operation user confirmation status,
instead of previous logic overriding Request. Previous logic causes
Get Pending TPM Operation Requested sub function return wrong value.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Long Qin <qin.long@intel.com>
Kurt Kennett [Mon, 26 Sep 2016 22:45:02 +0000 (22:45 +0000)]
ArmPkg/CpuDxe: Fix MMU initialization problem
During Mmu initialization in the CpuDxe, for a page table any bits set
in the 'NextSectionAttributes' are garbage and were set from bits that
are actually part of the pagetable address. We clear it out to zero
so that the SyncCacheConfigPage will use the page attributes instead
of trying to convert the (bogus) section attributes into page
attributes.
Tapan Shah [Fri, 23 Sep 2016 16:03:16 +0000 (09:03 -0700)]
ShellPkg: Enhance 'cls' command to change the background and foreground colors
As per ECR 1416 change in UEFI Shell Specification 2.2,
enhancing 'cls' command to change the background color as well as
foreground color. Also add support to display current settings
using 'cls -sfo' command.
NetworkPkg: Clean the previous address since the policy changed
The previous DNS server data will be retained after the policy
changes from Auto to Manual. This patch is used to clean the
previous dhcp configuration data.
Cc: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com> Cc: Subramanian Sriram <sriram-s@hpe.com> Cc: Ye Ting <ting.ye@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Sriram Subramanian <sriram-s@hpe.com> Reviewed-by: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com> Tested-by: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com>
MdeModulePkg: Clean the previous address since the policy changed
The previous DNS server data will be retained after the policy
changes from Dhcp to Static. This patch is used to clean the
previous dhcp configuration data.
Cc: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com> Cc: Subramanian Sriram <sriram-s@hpe.com> Cc: Ye Ting <ting.ye@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Sriram Subramanian <sriram-s@hpe.com> Reviewed-by: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com> Tested-by: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com>
MdeModulePkg/PciBusDxe: make OPROM BAR degradation configurable
The 'universal' PCI bus driver in MdeModulePkg contains a quirk to
degrade 64-bit PCI MMIO BARs to 32-bit in the presence of an option
ROM on the same PCI controller.
This quirk is highly specific to not just the X64 architecture in general,
but to the PC platform in particular, given that only X64 platforms that
require legacy PC BIOS compatibility require it. However, making the
quirk dependent on the presence of the legacy BIOS protocol met with
resistance, due to the fact that it introduces a dependency on the
IntelFrameworkModulePkg package.
So instead, make the quirk configurable, by introducing a feature flag PCD
'PcdPciDegradeResourceForOptionRom' which defaults to TRUE only for X64.
BaseTools: handling the case that map file is not exist
We meet a case that add the library inf file which has the uni file in
the [Sources] section, for this case there will no map file exist, it
cause build tools report Traceback error.
MdePkg/BaseMemoryLibOptDxe ARM AARCH64: fix thinko in SetMem##
The new InternalMemSetMem##() implementations for ARM and AARCH64 in
BaseMemoryLibOptDxe fail to take into account that the 'length' argument
is not in bytes, but in number of items to be copied. So multiply by the
item size before proceeding.
Tapan Shah [Wed, 21 Sep 2016 21:30:15 +0000 (14:30 -0700)]
ShellPkg: Remove current working dir path ".;" from 'path' variable
As per ECR 1349, latest UEFI Shell 2.2 specification has removed current working directory
path ".;" from a default 'path' environment variable as current working directory always
search first in system.
Tapan Shah [Thu, 22 Sep 2016 19:12:47 +0000 (12:12 -0700)]
ShellPkg: Expand special output file to include "NULL" and case insensitive
As per ECR 1349 change in UEFI Shell Specification 2.2, expanding
a special output file name to include "NULL". Previously it only
supported "NUL" as a special output file and it was case sensitive.
With this change both "NUL" and "NULL" are special output file and
checked as case insensitive.
Tapan Shah [Thu, 22 Sep 2016 19:49:12 +0000 (12:49 -0700)]
ShellPkg: Add '-nc' flag support in 'disconnect' command
As per ECR 1416, latest UEFI Shell 2.2 specification:
Define a behavior where 'disconnect -r' will disconnect drivers
from all devices but it will reconnect all consoles.
If -nc flag is used (e.g. 'disconnect -r -nc') then disconnect drivers
from all devices and don't reconnect consoles.
Jiewen Yao [Wed, 14 Sep 2016 08:54:50 +0000 (16:54 +0800)]
SecurityPkg/TPM2: Sync PcrAllocations and PcrMask
Current TCG2 implementation will set Tpm2HashMask PCD value according to TPM2
PCR bank. However, there might be misconfiguration in BIOS build phase.
The enhanced logic makes sure that the current PCR allocations, the TPM
supported PCRs, and the PcdTpm2HashMask are all in agreement.
Cc: Chao B Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Jiewen Yao [Wed, 14 Sep 2016 08:28:12 +0000 (16:28 +0800)]
SecurityPkg/TPM2: Extract GetSupportedAndActivePcrs to Tpm2CommandLib
This patch extracts function Tpm2GetCapabilitySupportedAndActivePcrs()
from drivers and also update Tcg2ExecutePhysicalPresence() to call
Tpm2GetCapabilitySupportedAndActivePcrs() instead of
Tcg2Protocol->GetCapability to query the TPM to determine which
hashing algorithms are supported.
Cc: Chao B Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Jiewen Yao [Wed, 14 Sep 2016 02:45:19 +0000 (10:45 +0800)]
SecurityPkg/TPM2: Move CopyDigestListToBuffer() to Tpm2CommandLib
This patch just moves function CopyDigestListToBuffer() from
drivers to library with HashAlgorithmMask parameter added to
make the interface more applicable.
The related function IsHashAlgSupportedInHashAlgorithmMask()
is also moved from drivers to library as internal function.
Cc: Chao B Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Jiewen Yao [Tue, 13 Sep 2016 10:43:30 +0000 (18:43 +0800)]
SecurityPkg/TPM2: Move Tpm2PcrAllocateBanks() to Tpm2CommandLib
This patch just moves function Tpm2CommandAllocPcr() from
DxeTcg2PhysicalPresenceLib.c to Tpm2CommandLib as Tpm2PcrAllocateBanks()
and no functionality change.
Cc: Chao B Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
ArmPkg/AsmMacroIoLib: force word alignment for functions
Without an explicit .align directive, the Clang assembler defaults to
no alignment, which may result in instructions appearing misaligned in
the final executable. So use word alignment in all cases.
ArmVirtPkg: move all platforms to MdePkg/ BaseMemoryLib implementations
The BaseMemoryLibStm implementation under ArmPkg/ is being deprecated,
in favor of the generic versions under MdePkg, now that ARM and AARCH64
support has been added to both the generic C version (BaseMemoryLib) and
the accelerated version (BaseMemoryLibOptDxe). The latter uses unaligned
accesses and special cache maintenance instructions, and can therefore
not be used when the MMU is off.
So move to BaseMemoryLibOptDxe for the DXE phase and later, and to the
generic BaseMemoryLib before that.
As reported by Vishal, CompareGuid() is a hotspot, and switching from
BaseMemoryLibStm in ArmPkg/ to BaseMemoryLibOptDxe causes a noticeable
performance regression due to the fact that BaseMemoryLibOptDxe uses
unaligned accessors explicitly to implement CompareGuid() and the related
functions.
Since BaseMemoryLibOptDxe on ARM and AARCH64 can only be used in contexts
where unaligned accesses are allowed, reimplement these functions for ARM
and AARCH64 specifically, using wide accessors that can tolerate any
misalignment.
MdePkg/BaseMemoryLibOptDxe ARM: fix arithmetic bugs in CompareMem()
Fix two bugs:
- Erroneous shift of 2 in a bytes to bits conversion.
- Use reverse subtract rather than negate for value that is subsequently
used as operand #2 in a shift operation.
Jeff Fan [Tue, 20 Sep 2016 08:17:26 +0000 (16:17 +0800)]
UefiCpuPkg/SecCore: SecPlatformInformation(2) are optional PPIs
Currently, this is ASSERT() if neither SecPlatformInformation2 nor
SecPlatformInformation PPIs are found. This is not correct. Per PI specification
both of them are optional PPI. Platform may not install them.
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Jeff Fan [Tue, 20 Sep 2016 08:03:18 +0000 (16:03 +0800)]
QuarkPlatformPkg/PlatformSecLib: Fix stack pointer issue in Flat32.S
ESP should be set to top of eSRAM range that aligns with Flat32.asm. Because CPU
BIST data will be located at top of STACK, this issue leads Platform Sec Lib
cannot get the correct CPU BIST information.
This fix is to address below issue:
https://tianocore.acgmultimedia.com/show_bug.cgi?id=123
Cc: Steven Shi <Steven.shi@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Kelly Steele <kelly.steele@intel.com> Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Star Zeng [Wed, 31 Aug 2016 06:47:36 +0000 (14:47 +0800)]
MdeModulePkg PCD: Update PCD database structure definition to match BaseTools
To follow PI1.4a, BaseTools has be updated to fix artificial limitation of
SkuId range.
This patch is to update PCD database structure definition to match BaseTools.
Note: The source code and BaseTools need to be upgraded at the same time,
and if they are not upgraded at the same time, build error like below will
be triggered to help user identify the problem.
"Please make sure the version of PCD PEIM Service and the generated
PCD PEI Database match."
BaseTools: Follow PI1.4a to fix artificial limitation of PCD SkuId range
Current BaseTools follow previous PI spec to use UINT8 for SkuId, to
follow PI1.4a, BaseTools need to be updated to fix artificial limitation
of PCD SkuId range.
This patch is to update BaseTools to use UINT64 for SkuId, since the
PCD database structure needs to be naturally aligned, the PCD database
structure layout is adjusted to keep the natural alignment and version
is updated to 6.
Note: As the PCD database structure layout is adjusted, the structure
definition in MdeModulePkg/Include/Guid/PcdDataBaseSignatureGuid.h and
PCD drivers also need to be updated. That means the source code and
BaseTools need to be upgraded at the same time, and if they are not
upgraded at the same time, build error like below will be triggered
to help user identify the problem.
"Please make sure the version of PCD PEIM Service and the generated
PCD PEI Database match."
IntelFsp2Pkg: Align #Pragma in UPD header files to rest of EDK2 Pkgs
Changed the GenCfgOpt.py script to insert pragma pack(1) instead of
pragma pack (push, 1) in the upd header files generated during fsp build.
This is to align with rest of the EDKII pkgs pragma pack usage.
Also, this scripts generates UnusedUpdSpace for UPD address gaps.
Currently it uses UIN16/UINT32/UINT64 for 2/4/8 bytes instead of UINT8[],
thus causing upd space waste to have Natural Alignment. Hence changed the
script to use UINT8[] for any unusedUpd fields above 1 byte.
Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
NetworkPkg: Correct the DNS token return status by RCODE
When HostNameToIp() and GeneralLookUp() are called with a invalid
host name, RCODE (4 bit field is set as part of responses) error
will returned in packet to identify the domain name referenced in
the query does not exist. So, EFI_NOT_FOUND should be returned
directly.
Current implementation only check the RCODE in successful condition.
Need update the code for more error check according to RFC 1035 4.1.1
section.
Cc: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Ye Ting <ting.ye@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Tested-by: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com> Reviewed-by: Sriram Subramanian <sriram-s@hpe.com>
ArmVirtPkg/HighMemDxe: move to FDT client protocol
Use the FDT client protocol rather than parsing the DT directly using
fdtlib. While we're at it, update the code so it deals correctly with
memory nodes that describe multiple disjoint regions in their "reg"
properties, and make the code work with #address-cells/#size-cells
properties of <1> as well as <2>.
ArmVirtPkg/FdtClientDxe: add methods to iterate over memory nodes
Add high level methods to iterate over all 'reg' properties of all DT
nodes whose device_type properties have the value "memory". Since we are
modifying the FdtClient protocol, update the protocol and the only existing
implementation at the same time.
ArmVirtPkg/FdtClientDxe: report address and size cell count directly
The FDT client protocol methods dealing with "reg" properties return
the size of a "reg" element. Currently, we have hardcoded this as '8',
since #address-cells == #size-cells == 2 in most cases. However, for
different values, have a single 'reg' element size is not unambiguous,
since - however unlikely - if #address-cells != #size-cells, we do not
know which is which.
So before adding more methods to the protocol, fix up this oversight.
ArmVirtPkg/FdtClientDxe: fix check for size of "reg" properties
Currently, the code in FdtClientDxe assumes #address-cells/#size-cells
values of <2>. Since DT "reg" properties always consist of <base, size>
tuples, this means the size of the entire property should always be a
multiple of 16 bytes (i.e, 4 * sizeof(UINT32), not 8. So fix this.
BaseTools: Fix the bug to handle the read-only file
change the 'r+b' to 'rb' for some file's open, since these files we only
read it and no need to write. It can fix the bug that the file's attribute
had been set to read-only.
Jeff Fan [Fri, 9 Sep 2016 07:14:32 +0000 (15:14 +0800)]
UefiCpuPkg/SecCore: Re-install SEC platform information(2) PPI
In SecTemporaryRamDone(), we will build one privated GUIDed-HOB to save CPU BIST
Data and re-install SEC platform information(2) PPI. Then other PEI drivers
could get CPU BIST data from the private GUIDed-HOB by new installed PPI.
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
Jeff Fan [Fri, 9 Sep 2016 07:08:56 +0000 (15:08 +0800)]
UefiCpuPkg/SecCore: Abstract worker function GetBistFromHob()
Abstract one worker function to get CPU BIST from the GUIDed-HOB. Add
SecPlatformInformationBist() and SecPlatformInformation2Bist() to invoke
GetBistFromHob(). Add in/out for parameter in function header.
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
Jeff Fan [Fri, 9 Sep 2016 07:00:30 +0000 (15:00 +0800)]
UefiCpuPkg/SecCore: Add SecBist.c
Add SecBist.c and copy GetBistInfoFromPpi() and SecPlatformInformation2() from
UefiCpuPkg/CpuMpPei/CpuBist.c. And update SecMain.c, SecMain.inf and
UefiCpuPkg.dsc accordinlgy to pass build.
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
Jeff Fan [Fri, 9 Sep 2016 06:36:39 +0000 (14:36 +0800)]
UefiCpuPkg/CpuMpPei: Build GUIDed-HOB to store all CPU BIST Data
Build gEfiSecPlatformInformation2PpiGuid GUIDed-HOB to store all CPU BIST data
that could be used not only by SecPlatformInformation2(), but also by CPU MP Dxe
driver to get CPU BIST data.
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
Jeff Fan [Fri, 9 Sep 2016 06:17:57 +0000 (14:17 +0800)]
UefiCpuPkg/CpuMpPei: Fix BistData ouput error
ProcessorInfo.ProcessorId is UINT64 type even it's valid value is UINT32. Use %x
only output the low 4 bytes and keep the high 4 bytes in stack that will be
output as the second parameter BistData. Typecast ProcessorInfo.ProcessorId to
UINT32 could make BistData output correctly.
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
Jeff Fan [Fri, 9 Sep 2016 05:39:50 +0000 (13:39 +0800)]
UefiCpuPkg/CpuDxe: Fix duplicated status code report
If CPU Bist data is not zero, we will report Status code. But there is one bug
that will report each processor's status code duplicated with NumberOfData
times. This fix is to exchange the loop order on NumberOfData and
mNumberOfProcessors. It could make sure the report status code only once for
each processor.
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
MdePkg/BaseMemoryLibOptDxe ARM|AARCH64: disallow use in SEC & PEI phases
The new accelerated ARM and AARCH64 implementations take advantage of
features that are only available when the MMU and Dcache are on. So
restrict the use of this library to the DXE phase or later.
This adds AARCH64 support to BaseMemoryLibOptDxe, based on the cortex-strings
library. All string routines are accelerated except ScanMem16, ScanMem32,
ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few
occurrences exist in the codebase)
MdePkg/BaseMemoryLibOptDxe: add accelerated ARM routines
This adds ARM support to BaseMemoryLibOptDxe, partially based on the
cortex-strings library (ScanMem) and the existing CopyMem() implementation
from BaseMemoryLibStm in ArmPkg.
All string routines are accelerated except ScanMem16, ScanMem32,
ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few
occurrences exist in the codebase)
MdePkg/BaseMemoryLib: widen aligned accesses to 32 or 64 bits
Since the default BaseMemoryLib should be callable from any context,
including ones where unaligned accesses are not allowed, it implements
InternalCopyMem() and InternalSetMem() using byte accesses only.
However, especially in a context where the MMU is off, such narrow
accesses may be disproportionately costly, and so if the size and
alignment of the access allow it, use 32-bit or even 64-bit loads and
stores (the latter may be beneficial even on a 32-bit architectures like
ARM, which has load pair/store pair instructions)
ArmVirtPkg/FdtParser: avoid unaligned accesses with the MMU off
When parsing the device tree to find the memory node, we are still running
with the MMU off, which means unaligned memory accesses are not allowed.
Since the FDT only mandates 32-bit alignment, 64-bit quantities are not
guaranteed to appear naturally aligned, and so should be accessed using
32-bit accesses instead.
ArmPkg/ArmMmuLib: base page table VA size on GCD memory map size
As reported by Eugene, the practice of sizing the address space in the
virtual memory system based on the maximum address in the table passed
to ArmConfigureMmu() is problematic, since it fails to take into account
the fact that the GCD memory space may be extended at a later time, both
for memory and for MMIO. So instead, choose the VA size identical to the
GCD memory map size, which is based on PcdPrePiCpuMemorySize on ARM
systems.
ArmPkg/ArmMmuLib: use a pool allocation for the root table
Currently, we allocate a full page for the root translation table, even
if the configured translation only requires two entries (16 bytes) for
the root level, which happens to be the case for a 40 bit VA. Likewise,
for a 36-bit VA space, the root table only needs 16 entries of 8 bytes
each, adding up to 128 bytes.
So switch to a pool allocation for the root table if we can, but take into
account that the architecture requires it to be naturally aligned to its
size, i.e., a 64 byte table requires 64 byte alignment, whereas pool
allocations in general are only guaranteed to be aligned to 8 bytes.