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Merge remote-tracking branch 'kraxel/seabios-1.7.3.2' into staging
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf
EH		 26#include "sysemu/cpus.h"
27#include "topology.h"
c6dc6f63 28
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
53a89e26 44#include "hw/qdev-properties.h"
62fc403f 45#include "hw/cpu/icc_bus.h"
bdeec802 46#ifndef CONFIG_USER_ONLY
0d09e41a 47#include "hw/xen/xen.h"
0d09e41a 48#include "hw/i386/apic_internal.h"
bdeec802
IM		 49#endif
50
5e891bf8
EH		 51
52/* Cache topology CPUID constants: */
53
54/* CPUID Leaf 2 Descriptors */
55
56#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57#define CPUID_2_L1I_32KB_8WAY_64B 0x30
58#define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61/* CPUID Leaf 4 constants: */
62
63/* EAX: */
64#define CPUID_4_TYPE_DCACHE 1
65#define CPUID_4_TYPE_ICACHE 2
66#define CPUID_4_TYPE_UNIFIED 3
67
68#define CPUID_4_LEVEL(l) ((l) << 5)
69
70#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71#define CPUID_4_FULLY_ASSOC (1 << 9)
72
73/* EDX: */
74#define CPUID_4_NO_INVD_SHARING (1 << 0)
75#define CPUID_4_INCLUSIVE (1 << 1)
76#define CPUID_4_COMPLEX_IDX (1 << 2)
77
78#define ASSOC_FULL 0xFF
79
80/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95/* Definitions of the hardcoded cache entries we expose: */
96
97/* L1 data cache: */
98#define L1D_LINE_SIZE 64
99#define L1D_ASSOCIATIVITY 8
100#define L1D_SETS 64
101#define L1D_PARTITIONS 1
102/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105#define L1D_LINES_PER_TAG 1
106#define L1D_SIZE_KB_AMD 64
107#define L1D_ASSOCIATIVITY_AMD 2
108
109/* L1 instruction cache: */
110#define L1I_LINE_SIZE 64
111#define L1I_ASSOCIATIVITY 8
112#define L1I_SETS 64
113#define L1I_PARTITIONS 1
114/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117#define L1I_LINES_PER_TAG 1
118#define L1I_SIZE_KB_AMD 64
119#define L1I_ASSOCIATIVITY_AMD 2
120
121/* Level 2 unified cache: */
122#define L2_LINE_SIZE 64
123#define L2_ASSOCIATIVITY 16
124#define L2_SETS 4096
125#define L2_PARTITIONS 1
126/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130#define L2_LINES_PER_TAG 1
131#define L2_SIZE_KB_AMD 512
132
133/* No L3 cache: */
134#define L3_SIZE_KB 0 /* disabled */
135#define L3_ASSOCIATIVITY 0 /* disabled */
136#define L3_LINES_PER_TAG 0 /* disabled */
137#define L3_LINE_SIZE 0 /* disabled */
138
139/* TLB definitions: */
140
141#define L1_DTLB_2M_ASSOC 1
142#define L1_DTLB_2M_ENTRIES 255
143#define L1_DTLB_4K_ASSOC 1
144#define L1_DTLB_4K_ENTRIES 255
145
146#define L1_ITLB_2M_ASSOC 1
147#define L1_ITLB_2M_ENTRIES 255
148#define L1_ITLB_4K_ASSOC 1
149#define L1_ITLB_4K_ENTRIES 255
150
151#define L2_DTLB_2M_ASSOC 0 /* disabled */
152#define L2_DTLB_2M_ENTRIES 0 /* disabled */
153#define L2_DTLB_4K_ASSOC 4
154#define L2_DTLB_4K_ENTRIES 512
155
156#define L2_ITLB_2M_ASSOC 0 /* disabled */
157#define L2_ITLB_2M_ENTRIES 0 /* disabled */
158#define L2_ITLB_4K_ASSOC 4
159#define L2_ITLB_4K_ENTRIES 512
160
161
162
99b88a17
IM		 163static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165{
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173}
174
c6dc6f63
AP		 175/* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188};
189static const char *ext_feature_name[] = {
f370be3c 190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 191 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 192 "tm2", "ssse3", "cid", NULL,
e117f772 193 "fma", "cx16", "xtpr", "pdcm",
434acb81 194 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 196 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 197 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 198};
3b671a40
EH		 199/* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
c6dc6f63 204static const char *ext2_feature_name[] = {
3b671a40
EH		 205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 212 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 213};
214static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 217 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 222 NULL, NULL, NULL, NULL,
223};
224
89e49c8b
EH		 225static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234};
235
c6dc6f63 236static const char *kvm_feature_name[] = {
c3d39807 237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 245};
246
296acb64
JR		 247static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256};
257
a9321a4d 258static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263};
264
5ef57876
EH		 265typedef struct FeatureWordInfo {
266 const char **feat_names;
04d104b6
EH		 267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
5ef57876
EH		 271} FeatureWordInfo;
272
273static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
89e49c8b
EH		 290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
bffd67b0
EH		 294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
bffd67b0 307 },
5ef57876
EH		 308};
309
8e8aba50
EH		 310typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315} X86RegisterInfo32;
316
317#define REGISTER(reg) \
318 [R_##reg] = { .name = #reg, .qapi_enum = X86_C_P_U_REGISTER32_##reg }
319X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328};
329#undef REGISTER
330
331
8b4beddc
EH		 332const char *get_register_name_32(unsigned int reg)
333{
31ccdde2 334 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 335 return NULL;
336 }
8e8aba50 337 return x86_reg_info_32[reg].name;
8b4beddc
EH		 338}
339
c6dc6f63
AP		 340/* collects per-function cpuid data
341 */
342typedef struct model_features_t {
343 uint32_t *guest_feat;
344 uint32_t *host_feat;
bffd67b0 345 FeatureWord feat_word;
8b4beddc 346} model_features_t;
c6dc6f63
AP		 347
348int check_cpuid = 0;
349int enforce_cpuid = 0;
350
dc59944b
MT		 351static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
352 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 353 (1 << KVM_FEATURE_CLOCKSOURCE2) |
354 (1 << KVM_FEATURE_ASYNC_PF) |
355 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 356 (1 << KVM_FEATURE_PV_EOI) |
dc59944b 357 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
dc59944b 358
29694758 359void disable_kvm_pv_eoi(void)
dc59944b 360{
29694758 361 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
dc59944b
MT		 362}
363
bb44e0d1
JK		 364void host_cpuid(uint32_t function, uint32_t count,
365 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 366{
367#if defined(CONFIG_KVM)
a1fd24af
AL		 368 uint32_t vec[4];
369
370#ifdef __x86_64__
371 asm volatile("cpuid"
372 : "=a"(vec[0]), "=b"(vec[1]),
373 "=c"(vec[2]), "=d"(vec[3])
374 : "0"(function), "c"(count) : "cc");
375#else
376 asm volatile("pusha \n\t"
377 "cpuid \n\t"
378 "mov %%eax, 0(%2) \n\t"
379 "mov %%ebx, 4(%2) \n\t"
380 "mov %%ecx, 8(%2) \n\t"
381 "mov %%edx, 12(%2) \n\t"
382 "popa"
383 : : "a"(function), "c"(count), "S"(vec)
384 : "memory", "cc");
385#endif
386
bdde476a 387 if (eax)
a1fd24af 388 *eax = vec[0];
bdde476a 389 if (ebx)
a1fd24af 390 *ebx = vec[1];
bdde476a 391 if (ecx)
a1fd24af 392 *ecx = vec[2];
bdde476a 393 if (edx)
a1fd24af 394 *edx = vec[3];
bdde476a
AP		 395#endif
396}
c6dc6f63
AP		 397
398#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
399
400/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
401 * a substring. ex if !NULL points to the first char after a substring,
402 * otherwise the string is assumed to sized by a terminating nul.
403 * Return lexical ordering of *s1:*s2.
404 */
405static int sstrcmp(const char *s1, const char *e1, const char *s2,
406 const char *e2)
407{
408 for (;;) {
409 if (!*s1 || !*s2 || *s1 != *s2)
410 return (*s1 - *s2);
411 ++s1, ++s2;
412 if (s1 == e1 && s2 == e2)
413 return (0);
414 else if (s1 == e1)
415 return (*s2);
416 else if (s2 == e2)
417 return (*s1);
418 }
419}
420
421/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
422 * '|' delimited (possibly empty) strings in which case search for a match
423 * within the alternatives proceeds left to right. Return 0 for success,
424 * non-zero otherwise.
425 */
426static int altcmp(const char *s, const char *e, const char *altstr)
427{
428 const char *p, *q;
429
430 for (q = p = altstr; ; ) {
431 while (*p && *p != '|')
432 ++p;
433 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
434 return (0);
435 if (!*p)
436 return (1);
437 else
438 q = ++p;
439 }
440}
441
442/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 443 * *pval and return true, otherwise return false
c6dc6f63 444 */
e41e0fc6
JK		 445static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
446 const char **featureset)
c6dc6f63
AP		 447{
448 uint32_t mask;
449 const char **ppc;
e41e0fc6 450 bool found = false;
c6dc6f63 451
e41e0fc6 452 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 453 if (*ppc && !altcmp(s, e, *ppc)) {
454 *pval |= mask;
e41e0fc6 455 found = true;
c6dc6f63 456 }
e41e0fc6
JK		 457 }
458 return found;
c6dc6f63
AP		 459}
460
5ef57876
EH		 461static void add_flagname_to_bitmaps(const char *flagname,
462 FeatureWordArray words)
c6dc6f63 463{
5ef57876
EH		 464 FeatureWord w;
465 for (w = 0; w < FEATURE_WORDS; w++) {
466 FeatureWordInfo *wi = &feature_word_info[w];
467 if (wi->feat_names &&
468 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
469 break;
470 }
471 }
472 if (w == FEATURE_WORDS) {
473 fprintf(stderr, "CPU feature %s not found\n", flagname);
474 }
c6dc6f63
AP		 475}
476
477typedef struct x86_def_t {
c6dc6f63
AP		 478 const char *name;
479 uint32_t level;
90e4b0c3
EH		 480 uint32_t xlevel;
481 uint32_t xlevel2;
99b88a17
IM		 482 /* vendor is zero-terminated, 12 character ASCII string */
483 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 484 int family;
485 int model;
486 int stepping;
0514ef2f 487 FeatureWordArray features;
c6dc6f63 488 char model_id[48];
787aaf57 489 bool cache_info_passthrough;
c6dc6f63
AP		 490} x86_def_t;
491
492#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
493#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
494 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
495#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
496 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
497 CPUID_PSE36 | CPUID_FXSR)
498#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
499#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
500 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
501 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
502 CPUID_PAE | CPUID_SEP | CPUID_APIC)
503
551a2dec
AP		 504#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
505 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
506 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
507 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
508 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 509 /* partly implemented:
510 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
511 CPUID_PSE36 (needed for Solaris) */
512 /* missing:
513 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
e71827bc
AJ		 514#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
515 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
516 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
d640045a 517 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
8560efed 518 /* missing:
e71827bc
AJ		 519 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
520 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
521 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
d640045a
AJ		 522 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
523 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
83f7dc28 524 CPUID_EXT_RDRAND */
60032ac0 525#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 526 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
527 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 528 /* missing:
529 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 530#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
531 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 532#define TCG_SVM_FEATURES 0
7073fbad 533#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
cd7f97ca 534 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
111994ee 535 /* missing:
7073fbad
RH		 536 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
537 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
cd7f97ca 538 CPUID_7_0_EBX_RDSEED */
551a2dec 539
7fc9b714 540/* built-in CPU model definitions
c6dc6f63
AP		 541 */
542static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 543 {
544 .name = "qemu64",
545 .level = 4,
99b88a17 546 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 547 .family = 6,
548 .model = 2,
549 .stepping = 3,
0514ef2f 550 .features[FEAT_1_EDX] =
27861ecc 551 PPRO_FEATURES |
c6dc6f63 552 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 553 CPUID_PSE36,
0514ef2f 554 .features[FEAT_1_ECX] =
27861ecc 555 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 556 .features[FEAT_8000_0001_EDX] =
27861ecc 557 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 558 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 559 .features[FEAT_8000_0001_ECX] =
27861ecc 560 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 561 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
562 .xlevel = 0x8000000A,
c6dc6f63
AP		 563 },
564 {
565 .name = "phenom",
566 .level = 5,
99b88a17 567 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 568 .family = 16,
569 .model = 2,
570 .stepping = 3,
0514ef2f 571 .features[FEAT_1_EDX] =
27861ecc 572 PPRO_FEATURES |
c6dc6f63 573 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 574 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 575 .features[FEAT_1_ECX] =
27861ecc 576 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 577 CPUID_EXT_POPCNT,
0514ef2f 578 .features[FEAT_8000_0001_EDX] =
27861ecc 579 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 580 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
581 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 582 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 583 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
584 CPUID_EXT3_CR8LEG,
585 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
586 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 587 .features[FEAT_8000_0001_ECX] =
27861ecc 588 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 589 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 590 .features[FEAT_SVM] =
27861ecc 591 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 592 .xlevel = 0x8000001A,
593 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
594 },
595 {
596 .name = "core2duo",
597 .level = 10,
99b88a17 598 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 599 .family = 6,
600 .model = 15,
601 .stepping = 11,
0514ef2f 602 .features[FEAT_1_EDX] =
27861ecc 603 PPRO_FEATURES |
c6dc6f63 604 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 605 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
606 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 607 .features[FEAT_1_ECX] =
27861ecc 608 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 609 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
610 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 611 .features[FEAT_8000_0001_EDX] =
27861ecc 612 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 613 .features[FEAT_8000_0001_ECX] =
27861ecc 614 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 615 .xlevel = 0x80000008,
616 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
617 },
618 {
619 .name = "kvm64",
620 .level = 5,
99b88a17 621 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 622 .family = 15,
623 .model = 6,
624 .stepping = 1,
625 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 626 .features[FEAT_1_EDX] =
27861ecc 627 PPRO_FEATURES |
c6dc6f63
AP		 628 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
629 CPUID_PSE36,
630 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 631 .features[FEAT_1_ECX] =
27861ecc 632 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 633 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 634 .features[FEAT_8000_0001_EDX] =
27861ecc 635 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 636 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
637 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
638 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
639 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
640 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 641 .features[FEAT_8000_0001_ECX] =
27861ecc 642 0,
c6dc6f63
AP		 643 .xlevel = 0x80000008,
644 .model_id = "Common KVM processor"
645 },
c6dc6f63
AP		 646 {
647 .name = "qemu32",
648 .level = 4,
99b88a17 649 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 650 .family = 6,
651 .model = 3,
652 .stepping = 3,
0514ef2f 653 .features[FEAT_1_EDX] =
27861ecc 654 PPRO_FEATURES,
0514ef2f 655 .features[FEAT_1_ECX] =
27861ecc 656 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 657 .xlevel = 0x80000004,
c6dc6f63 658 },
eafaf1e5
AP		 659 {
660 .name = "kvm32",
661 .level = 5,
99b88a17 662 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 663 .family = 15,
664 .model = 6,
665 .stepping = 1,
0514ef2f 666 .features[FEAT_1_EDX] =
27861ecc 667 PPRO_FEATURES |
eafaf1e5 668 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 669 .features[FEAT_1_ECX] =
27861ecc 670 CPUID_EXT_SSE3,
0514ef2f 671 .features[FEAT_8000_0001_EDX] =
27861ecc 672 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 673 .features[FEAT_8000_0001_ECX] =
27861ecc 674 0,
eafaf1e5
AP		 675 .xlevel = 0x80000008,
676 .model_id = "Common 32-bit KVM processor"
677 },
c6dc6f63
AP		 678 {
679 .name = "coreduo",
680 .level = 10,
99b88a17 681 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 682 .family = 6,
683 .model = 14,
684 .stepping = 8,
0514ef2f 685 .features[FEAT_1_EDX] =
27861ecc 686 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 687 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
688 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 689 .features[FEAT_1_ECX] =
27861ecc 690 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 691 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 692 .features[FEAT_8000_0001_EDX] =
27861ecc 693 CPUID_EXT2_NX,
c6dc6f63
AP		 694 .xlevel = 0x80000008,
695 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
696 },
697 {
698 .name = "486",
58012d66 699 .level = 1,
99b88a17 700 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 701 .family = 4,
b2a856d9 702 .model = 8,
c6dc6f63 703 .stepping = 0,
0514ef2f 704 .features[FEAT_1_EDX] =
27861ecc 705 I486_FEATURES,
c6dc6f63
AP		 706 .xlevel = 0,
707 },
708 {
709 .name = "pentium",
710 .level = 1,
99b88a17 711 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 712 .family = 5,
713 .model = 4,
714 .stepping = 3,
0514ef2f 715 .features[FEAT_1_EDX] =
27861ecc 716 PENTIUM_FEATURES,
c6dc6f63
AP		 717 .xlevel = 0,
718 },
719 {
720 .name = "pentium2",
721 .level = 2,
99b88a17 722 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 723 .family = 6,
724 .model = 5,
725 .stepping = 2,
0514ef2f 726 .features[FEAT_1_EDX] =
27861ecc 727 PENTIUM2_FEATURES,
c6dc6f63
AP		 728 .xlevel = 0,
729 },
730 {
731 .name = "pentium3",
732 .level = 2,
99b88a17 733 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 734 .family = 6,
735 .model = 7,
736 .stepping = 3,
0514ef2f 737 .features[FEAT_1_EDX] =
27861ecc 738 PENTIUM3_FEATURES,
c6dc6f63
AP		 739 .xlevel = 0,
740 },
741 {
742 .name = "athlon",
743 .level = 2,
99b88a17 744 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 745 .family = 6,
746 .model = 2,
747 .stepping = 3,
0514ef2f 748 .features[FEAT_1_EDX] =
27861ecc 749 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 750 CPUID_MCA,
0514ef2f 751 .features[FEAT_8000_0001_EDX] =
27861ecc 752 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 753 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 754 .xlevel = 0x80000008,
c6dc6f63
AP		 755 },
756 {
757 .name = "n270",
758 /* original is on level 10 */
759 .level = 5,
99b88a17 760 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 761 .family = 6,
762 .model = 28,
763 .stepping = 2,
0514ef2f 764 .features[FEAT_1_EDX] =
27861ecc 765 PPRO_FEATURES |
8560efed
AJ		 766 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
767 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 768 /* Some CPUs got no CPUID_SEP */
0514ef2f 769 .features[FEAT_1_ECX] =
27861ecc 770 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 771 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
772 CPUID_EXT_MOVBE,
0514ef2f 773 .features[FEAT_8000_0001_EDX] =
27861ecc 774 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 775 CPUID_EXT2_NX,
0514ef2f 776 .features[FEAT_8000_0001_ECX] =
27861ecc 777 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 778 .xlevel = 0x8000000A,
779 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
780 },
3eca4642
EH		 781 {
782 .name = "Conroe",
6b11322e 783 .level = 4,
99b88a17 784 .vendor = CPUID_VENDOR_INTEL,
3eca4642 785 .family = 6,
ffce9ebb 786 .model = 15,
3eca4642 787 .stepping = 3,
0514ef2f 788 .features[FEAT_1_EDX] =
27861ecc 789 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 790 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
791 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
792 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
793 CPUID_DE | CPUID_FP87,
0514ef2f 794 .features[FEAT_1_ECX] =
27861ecc 795 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 796 .features[FEAT_8000_0001_EDX] =
27861ecc 797 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 798 .features[FEAT_8000_0001_ECX] =
27861ecc 799 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 800 .xlevel = 0x8000000A,
801 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
802 },
803 {
804 .name = "Penryn",
6b11322e 805 .level = 4,
99b88a17 806 .vendor = CPUID_VENDOR_INTEL,
3eca4642 807 .family = 6,
ffce9ebb 808 .model = 23,
3eca4642 809 .stepping = 3,
0514ef2f 810 .features[FEAT_1_EDX] =
27861ecc 811 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 812 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
813 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
814 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
815 CPUID_DE | CPUID_FP87,
0514ef2f 816 .features[FEAT_1_ECX] =
27861ecc 817 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 818 CPUID_EXT_SSE3,
0514ef2f 819 .features[FEAT_8000_0001_EDX] =
27861ecc 820 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 821 .features[FEAT_8000_0001_ECX] =
27861ecc 822 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 823 .xlevel = 0x8000000A,
824 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
825 },
826 {
827 .name = "Nehalem",
6b11322e 828 .level = 4,
99b88a17 829 .vendor = CPUID_VENDOR_INTEL,
3eca4642 830 .family = 6,
ffce9ebb 831 .model = 26,
3eca4642 832 .stepping = 3,
0514ef2f 833 .features[FEAT_1_EDX] =
27861ecc 834 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 835 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
836 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
837 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
838 CPUID_DE | CPUID_FP87,
0514ef2f 839 .features[FEAT_1_ECX] =
27861ecc 840 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 841 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 842 .features[FEAT_8000_0001_EDX] =
27861ecc 843 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 844 .features[FEAT_8000_0001_ECX] =
27861ecc 845 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 846 .xlevel = 0x8000000A,
847 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
848 },
849 {
850 .name = "Westmere",
851 .level = 11,
99b88a17 852 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 853 .family = 6,
854 .model = 44,
855 .stepping = 1,
0514ef2f 856 .features[FEAT_1_EDX] =
27861ecc 857 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 858 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
859 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
860 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
861 CPUID_DE | CPUID_FP87,
0514ef2f 862 .features[FEAT_1_ECX] =
27861ecc 863 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 864 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 865 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 866 .features[FEAT_8000_0001_EDX] =
27861ecc 867 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 868 .features[FEAT_8000_0001_ECX] =
27861ecc 869 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 870 .xlevel = 0x8000000A,
871 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
872 },
873 {
874 .name = "SandyBridge",
875 .level = 0xd,
99b88a17 876 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 877 .family = 6,
878 .model = 42,
879 .stepping = 1,
0514ef2f 880 .features[FEAT_1_EDX] =
27861ecc 881 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 882 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
883 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
884 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
885 CPUID_DE | CPUID_FP87,
0514ef2f 886 .features[FEAT_1_ECX] =
27861ecc 887 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 888 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
889 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
890 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
891 CPUID_EXT_SSE3,
0514ef2f 892 .features[FEAT_8000_0001_EDX] =
27861ecc 893 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 894 CPUID_EXT2_SYSCALL,
0514ef2f 895 .features[FEAT_8000_0001_ECX] =
27861ecc 896 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 897 .xlevel = 0x8000000A,
898 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
899 },
37507094
EH		 900 {
901 .name = "Haswell",
902 .level = 0xd,
99b88a17 903 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 904 .family = 6,
905 .model = 60,
906 .stepping = 1,
0514ef2f 907 .features[FEAT_1_EDX] =
27861ecc 908 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 909 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 910 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 911 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
912 CPUID_DE | CPUID_FP87,
0514ef2f 913 .features[FEAT_1_ECX] =
27861ecc 914 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH		 915 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
916 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
917 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
918 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
919 CPUID_EXT_PCID,
0514ef2f 920 .features[FEAT_8000_0001_EDX] =
27861ecc 921 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 922 CPUID_EXT2_SYSCALL,
0514ef2f 923 .features[FEAT_8000_0001_ECX] =
27861ecc 924 CPUID_EXT3_LAHF_LM,
0514ef2f 925 .features[FEAT_7_0_EBX] =
27861ecc 926 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 927 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
928 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
929 CPUID_7_0_EBX_RTM,
930 .xlevel = 0x8000000A,
931 .model_id = "Intel Core Processor (Haswell)",
932 },
3eca4642
EH		 933 {
934 .name = "Opteron_G1",
935 .level = 5,
99b88a17 936 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 937 .family = 15,
938 .model = 6,
939 .stepping = 1,
0514ef2f 940 .features[FEAT_1_EDX] =
27861ecc 941 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 942 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
943 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
944 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
945 CPUID_DE | CPUID_FP87,
0514ef2f 946 .features[FEAT_1_ECX] =
27861ecc 947 CPUID_EXT_SSE3,
0514ef2f 948 .features[FEAT_8000_0001_EDX] =
27861ecc 949 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH		 950 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
951 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
952 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
953 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
954 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
955 .xlevel = 0x80000008,
956 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
957 },
958 {
959 .name = "Opteron_G2",
960 .level = 5,
99b88a17 961 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 962 .family = 15,
963 .model = 6,
964 .stepping = 1,
0514ef2f 965 .features[FEAT_1_EDX] =
27861ecc 966 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 967 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
968 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
969 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
970 CPUID_DE | CPUID_FP87,
0514ef2f 971 .features[FEAT_1_ECX] =
27861ecc 972 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 973 .features[FEAT_8000_0001_EDX] =
27861ecc 974 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 975 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
976 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
977 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
978 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
979 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
980 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 981 .features[FEAT_8000_0001_ECX] =
27861ecc 982 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 983 .xlevel = 0x80000008,
984 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
985 },
986 {
987 .name = "Opteron_G3",
988 .level = 5,
99b88a17 989 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 990 .family = 15,
991 .model = 6,
992 .stepping = 1,
0514ef2f 993 .features[FEAT_1_EDX] =
27861ecc 994 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 995 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
996 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
997 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
998 CPUID_DE | CPUID_FP87,
0514ef2f 999 .features[FEAT_1_ECX] =
27861ecc 1000 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1001 CPUID_EXT_SSE3,
0514ef2f 1002 .features[FEAT_8000_0001_EDX] =
27861ecc 1003 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1004 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1005 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1006 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1007 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1008 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1009 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1010 .features[FEAT_8000_0001_ECX] =
27861ecc 1011 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH		 1012 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1013 .xlevel = 0x80000008,
1014 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1015 },
1016 {
1017 .name = "Opteron_G4",
1018 .level = 0xd,
99b88a17 1019 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1020 .family = 21,
1021 .model = 1,
1022 .stepping = 2,
0514ef2f 1023 .features[FEAT_1_EDX] =
27861ecc 1024 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1025 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1026 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1027 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1028 CPUID_DE | CPUID_FP87,
0514ef2f 1029 .features[FEAT_1_ECX] =
27861ecc 1030 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 1031 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1032 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1033 CPUID_EXT_SSE3,
0514ef2f 1034 .features[FEAT_8000_0001_EDX] =
27861ecc 1035 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH		 1036 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1037 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1038 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1039 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1040 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1041 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1042 .features[FEAT_8000_0001_ECX] =
27861ecc 1043 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH		 1044 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1045 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1046 CPUID_EXT3_LAHF_LM,
1047 .xlevel = 0x8000001A,
1048 .model_id = "AMD Opteron 62xx class CPU",
1049 },
021941b9
AP		 1050 {
1051 .name = "Opteron_G5",
1052 .level = 0xd,
99b88a17 1053 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1054 .family = 21,
1055 .model = 2,
1056 .stepping = 0,
0514ef2f 1057 .features[FEAT_1_EDX] =
27861ecc 1058 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP		 1059 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1060 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1061 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1062 CPUID_DE | CPUID_FP87,
0514ef2f 1063 .features[FEAT_1_ECX] =
27861ecc 1064 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP		 1065 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1066 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1067 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1068 .features[FEAT_8000_0001_EDX] =
27861ecc 1069 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP		 1070 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1071 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1072 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1073 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1074 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1075 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1076 .features[FEAT_8000_0001_ECX] =
27861ecc 1077 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP		 1078 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1079 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1080 CPUID_EXT3_LAHF_LM,
1081 .xlevel = 0x8000001A,
1082 .model_id = "AMD Opteron 63xx class CPU",
1083 },
c6dc6f63
AP		 1084};
1085
0668af54
EH		 1086/**
1087 * x86_cpu_compat_set_features:
1088 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1089 * @w: Identifies the feature word to be changed.
1090 * @feat_add: Feature bits to be added to feature word
1091 * @feat_remove: Feature bits to be removed from feature word
1092 *
1093 * Change CPU model feature bits for compatibility.
1094 *
1095 * This function may be used by machine-type compatibility functions
1096 * to enable or disable feature bits on specific CPU models.
1097 */
1098void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1099 uint32_t feat_add, uint32_t feat_remove)
1100{
1101 x86_def_t *def;
1102 int i;
1103 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1104 def = &builtin_x86_defs[i];
1105 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1106 def->features[w] |= feat_add;
1107 def->features[w] &= ~feat_remove;
1108 }
1109 }
1110}
1111
e4ab0d6b 1112#ifdef CONFIG_KVM
c6dc6f63
AP		 1113static int cpu_x86_fill_model_id(char *str)
1114{
1115 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1116 int i;
1117
1118 for (i = 0; i < 3; i++) {
1119 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1120 memcpy(str + i * 16 + 0, &eax, 4);
1121 memcpy(str + i * 16 + 4, &ebx, 4);
1122 memcpy(str + i * 16 + 8, &ecx, 4);
1123 memcpy(str + i * 16 + 12, &edx, 4);
1124 }
1125 return 0;
1126}
e4ab0d6b 1127#endif
c6dc6f63 1128
6e746f30
EH		 1129/* Fill a x86_def_t struct with information about the host CPU, and
1130 * the CPU features supported by the host hardware + host kernel
1131 *
1132 * This function may be called only if KVM is enabled.
1133 */
1134static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 1135{
e4ab0d6b 1136#ifdef CONFIG_KVM
12869995 1137 KVMState *s = kvm_state;
c6dc6f63
AP		 1138 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1139
6e746f30
EH		 1140 assert(kvm_enabled());
1141
c6dc6f63 1142 x86_cpu_def->name = "host";
787aaf57 1143 x86_cpu_def->cache_info_passthrough = true;
c6dc6f63 1144 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
99b88a17 1145 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
c6dc6f63
AP		 1146
1147 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1148 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1149 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1150 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 1151
12869995 1152 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
0514ef2f 1153 x86_cpu_def->features[FEAT_1_EDX] =
27861ecc 1154 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
0514ef2f 1155 x86_cpu_def->features[FEAT_1_ECX] =
27861ecc 1156 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 1157
6e746f30 1158 if (x86_cpu_def->level >= 7) {
0514ef2f 1159 x86_cpu_def->features[FEAT_7_0_EBX] =
12869995 1160 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728 1161 } else {
0514ef2f 1162 x86_cpu_def->features[FEAT_7_0_EBX] = 0;
13526728
EH		 1163 }
1164
12869995 1165 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
0514ef2f 1166 x86_cpu_def->features[FEAT_8000_0001_EDX] =
12869995 1167 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
0514ef2f 1168 x86_cpu_def->features[FEAT_8000_0001_ECX] =
12869995 1169 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 1170
c6dc6f63 1171 cpu_x86_fill_model_id(x86_cpu_def->model_id);
c6dc6f63 1172
b3baa152 1173 /* Call Centaur's CPUID instruction. */
99b88a17 1174 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
b3baa152 1175 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
12869995 1176 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
b3baa152
BW		 1177 if (eax >= 0xC0000001) {
1178 /* Support VIA max extended level */
1179 x86_cpu_def->xlevel2 = eax;
1180 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
0514ef2f 1181 x86_cpu_def->features[FEAT_C000_0001_EDX] =
12869995 1182 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
b3baa152
BW		 1183 }
1184 }
296acb64 1185
fcb93c03 1186 /* Other KVM-specific feature fields: */
0514ef2f 1187 x86_cpu_def->features[FEAT_SVM] =
fcb93c03 1188 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
0514ef2f 1189 x86_cpu_def->features[FEAT_KVM] =
bd004bef 1190 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 1191
e4ab0d6b 1192#endif /* CONFIG_KVM */
c6dc6f63
AP		 1193}
1194
bffd67b0 1195static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 1196{
1197 int i;
1198
1199 for (i = 0; i < 32; ++i)
1200 if (1 << i & mask) {
bffd67b0 1201 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1202 assert(reg);
1203 fprintf(stderr, "warning: host doesn't support requested feature: "
1204 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1205 f->cpuid_eax, reg,
1206 f->feat_names[i] ? "." : "",
1207 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 1208 break;
1209 }
1210 return 0;
1211}
1212
07ca5945
EH		 1213/* Check if all requested cpu flags are making their way to the guest
1214 *
1215 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 1216 *
1217 * This function may be called only if KVM is enabled.
c6dc6f63 1218 */
5ec01c2e 1219static int kvm_check_features_against_host(X86CPU *cpu)
c6dc6f63 1220{
5ec01c2e 1221 CPUX86State *env = &cpu->env;
c6dc6f63
AP		 1222 x86_def_t host_def;
1223 uint32_t mask;
1224 int rv, i;
1225 struct model_features_t ft[] = {
0514ef2f
EH		 1226 {&env->features[FEAT_1_EDX],
1227 &host_def.features[FEAT_1_EDX],
bffd67b0 1228 FEAT_1_EDX },
0514ef2f
EH		 1229 {&env->features[FEAT_1_ECX],
1230 &host_def.features[FEAT_1_ECX],
bffd67b0 1231 FEAT_1_ECX },
0514ef2f
EH		 1232 {&env->features[FEAT_8000_0001_EDX],
1233 &host_def.features[FEAT_8000_0001_EDX],
bffd67b0 1234 FEAT_8000_0001_EDX },
0514ef2f
EH		 1235 {&env->features[FEAT_8000_0001_ECX],
1236 &host_def.features[FEAT_8000_0001_ECX],
bffd67b0 1237 FEAT_8000_0001_ECX },
0514ef2f
EH		 1238 {&env->features[FEAT_C000_0001_EDX],
1239 &host_def.features[FEAT_C000_0001_EDX],
07ca5945 1240 FEAT_C000_0001_EDX },
0514ef2f
EH		 1241 {&env->features[FEAT_7_0_EBX],
1242 &host_def.features[FEAT_7_0_EBX],
07ca5945 1243 FEAT_7_0_EBX },
0514ef2f
EH		 1244 {&env->features[FEAT_SVM],
1245 &host_def.features[FEAT_SVM],
07ca5945 1246 FEAT_SVM },
0514ef2f
EH		 1247 {&env->features[FEAT_KVM],
1248 &host_def.features[FEAT_KVM],
07ca5945 1249 FEAT_KVM },
8b4beddc 1250 };
c6dc6f63 1251
6e746f30
EH		 1252 assert(kvm_enabled());
1253
1254 kvm_cpu_fill_host(&host_def);
bffd67b0
EH		 1255 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1256 FeatureWord w = ft[i].feat_word;
1257 FeatureWordInfo *wi = &feature_word_info[w];
1258 for (mask = 1; mask; mask <<= 1) {
e8beac00 1259 if (*ft[i].guest_feat & mask &&
c6dc6f63 1260 !(*ft[i].host_feat & mask)) {
bffd67b0
EH		 1261 unavailable_host_feature(wi, mask);
1262 rv = 1;
1263 }
1264 }
1265 }
c6dc6f63
AP		 1266 return rv;
1267}
1268
95b8519d
AF		 1269static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1270 const char *name, Error **errp)
1271{
1272 X86CPU *cpu = X86_CPU(obj);
1273 CPUX86State *env = &cpu->env;
1274 int64_t value;
1275
1276 value = (env->cpuid_version >> 8) & 0xf;
1277 if (value == 0xf) {
1278 value += (env->cpuid_version >> 20) & 0xff;
1279 }
1280 visit_type_int(v, &value, name, errp);
1281}
1282
71ad61d3
AF		 1283static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1284 const char *name, Error **errp)
ed5e1ec3 1285{
71ad61d3
AF		 1286 X86CPU *cpu = X86_CPU(obj);
1287 CPUX86State *env = &cpu->env;
1288 const int64_t min = 0;
1289 const int64_t max = 0xff + 0xf;
1290 int64_t value;
1291
1292 visit_type_int(v, &value, name, errp);
1293 if (error_is_set(errp)) {
1294 return;
1295 }
1296 if (value < min || value > max) {
1297 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1298 name ? name : "null", value, min, max);
1299 return;
1300 }
1301
ed5e1ec3 1302 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1303 if (value > 0x0f) {
1304 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1305 } else {
71ad61d3 1306 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1307 }
1308}
1309
67e30c83
AF		 1310static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1311 const char *name, Error **errp)
1312{
1313 X86CPU *cpu = X86_CPU(obj);
1314 CPUX86State *env = &cpu->env;
1315 int64_t value;
1316
1317 value = (env->cpuid_version >> 4) & 0xf;
1318 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1319 visit_type_int(v, &value, name, errp);
1320}
1321
c5291a4f
AF		 1322static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1323 const char *name, Error **errp)
b0704cbd 1324{
c5291a4f
AF		 1325 X86CPU *cpu = X86_CPU(obj);
1326 CPUX86State *env = &cpu->env;
1327 const int64_t min = 0;
1328 const int64_t max = 0xff;
1329 int64_t value;
1330
1331 visit_type_int(v, &value, name, errp);
1332 if (error_is_set(errp)) {
1333 return;
1334 }
1335 if (value < min || value > max) {
1336 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1337 name ? name : "null", value, min, max);
1338 return;
1339 }
1340
b0704cbd 1341 env->cpuid_version &= ~0xf00f0;
c5291a4f 1342 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1343}
1344
35112e41
AF		 1345static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1346 void *opaque, const char *name,
1347 Error **errp)
1348{
1349 X86CPU *cpu = X86_CPU(obj);
1350 CPUX86State *env = &cpu->env;
1351 int64_t value;
1352
1353 value = env->cpuid_version & 0xf;
1354 visit_type_int(v, &value, name, errp);
1355}
1356
036e2222
AF		 1357static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1358 void *opaque, const char *name,
1359 Error **errp)
38c3dc46 1360{
036e2222
AF		 1361 X86CPU *cpu = X86_CPU(obj);
1362 CPUX86State *env = &cpu->env;
1363 const int64_t min = 0;
1364 const int64_t max = 0xf;
1365 int64_t value;
1366
1367 visit_type_int(v, &value, name, errp);
1368 if (error_is_set(errp)) {
1369 return;
1370 }
1371 if (value < min || value > max) {
1372 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1373 name ? name : "null", value, min, max);
1374 return;
1375 }
1376
38c3dc46 1377 env->cpuid_version &= ~0xf;
036e2222 1378 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1379}
1380
8e1898bf
AF		 1381static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1382 const char *name, Error **errp)
1383{
1384 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1385
fa029887 1386 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1387}
1388
1389static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1390 const char *name, Error **errp)
1391{
1392 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1393
fa029887 1394 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1395}
1396
16b93aa8
AF		 1397static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1398 const char *name, Error **errp)
1399{
1400 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1401
fa029887 1402 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1403}
1404
1405static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1406 const char *name, Error **errp)
1407{
1408 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1409
fa029887 1410 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1411}
1412
d480e1af
AF		 1413static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1414{
1415 X86CPU *cpu = X86_CPU(obj);
1416 CPUX86State *env = &cpu->env;
1417 char *value;
d480e1af 1418
9df694ee 1419 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1420 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1421 env->cpuid_vendor3);
d480e1af
AF		 1422 return value;
1423}
1424
1425static void x86_cpuid_set_vendor(Object *obj, const char *value,
1426 Error **errp)
1427{
1428 X86CPU *cpu = X86_CPU(obj);
1429 CPUX86State *env = &cpu->env;
1430 int i;
1431
9df694ee 1432 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1433 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1434 "vendor", value);
1435 return;
1436 }
1437
1438 env->cpuid_vendor1 = 0;
1439 env->cpuid_vendor2 = 0;
1440 env->cpuid_vendor3 = 0;
1441 for (i = 0; i < 4; i++) {
1442 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1443 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1444 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1445 }
d480e1af
AF		 1446}
1447
63e886eb
AF		 1448static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1449{
1450 X86CPU *cpu = X86_CPU(obj);
1451 CPUX86State *env = &cpu->env;
1452 char *value;
1453 int i;
1454
1455 value = g_malloc(48 + 1);
1456 for (i = 0; i < 48; i++) {
1457 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1458 }
1459 value[48] = '\0';
1460 return value;
1461}
1462
938d4c25
AF		 1463static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1464 Error **errp)
dcce6675 1465{
938d4c25
AF		 1466 X86CPU *cpu = X86_CPU(obj);
1467 CPUX86State *env = &cpu->env;
dcce6675
AF		 1468 int c, len, i;
1469
1470 if (model_id == NULL) {
1471 model_id = "";
1472 }
1473 len = strlen(model_id);
d0a6acf4 1474 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1475 for (i = 0; i < 48; i++) {
1476 if (i >= len) {
1477 c = '\0';
1478 } else {
1479 c = (uint8_t)model_id[i];
1480 }
1481 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1482 }
1483}
1484
89e48965
AF		 1485static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1486 const char *name, Error **errp)
1487{
1488 X86CPU *cpu = X86_CPU(obj);
1489 int64_t value;
1490
1491 value = cpu->env.tsc_khz * 1000;
1492 visit_type_int(v, &value, name, errp);
1493}
1494
1495static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1496 const char *name, Error **errp)
1497{
1498 X86CPU *cpu = X86_CPU(obj);
1499 const int64_t min = 0;
2e84849a 1500 const int64_t max = INT64_MAX;
89e48965
AF		 1501 int64_t value;
1502
1503 visit_type_int(v, &value, name, errp);
1504 if (error_is_set(errp)) {
1505 return;
1506 }
1507 if (value < min || value > max) {
1508 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1509 name ? name : "null", value, min, max);
1510 return;
1511 }
1512
1513 cpu->env.tsc_khz = value / 1000;
1514}
1515
31050930
IM		 1516static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1517 const char *name, Error **errp)
1518{
1519 X86CPU *cpu = X86_CPU(obj);
1520 int64_t value = cpu->env.cpuid_apic_id;
1521
1522 visit_type_int(v, &value, name, errp);
1523}
1524
1525static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1526 const char *name, Error **errp)
1527{
1528 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1529 DeviceState *dev = DEVICE(obj);
31050930
IM		 1530 const int64_t min = 0;
1531 const int64_t max = UINT32_MAX;
1532 Error *error = NULL;
1533 int64_t value;
1534
8d6d4980
IM		 1535 if (dev->realized) {
1536 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1537 "it was realized", name, object_get_typename(obj));
1538 return;
1539 }
1540
31050930
IM		 1541 visit_type_int(v, &value, name, &error);
1542 if (error) {
1543 error_propagate(errp, error);
1544 return;
1545 }
1546 if (value < min || value > max) {
1547 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1548 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1549 object_get_typename(obj), name, value, min, max);
1550 return;
1551 }
1552
1553 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1554 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1555 return;
1556 }
1557 cpu->env.cpuid_apic_id = value;
1558}
1559
7e5292b5 1560/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1561static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1562 const char *name, Error **errp)
1563{
7e5292b5 1564 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1565 FeatureWord w;
1566 Error *err = NULL;
1567 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1568 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1569 X86CPUFeatureWordInfoList *list = NULL;
1570
1571 for (w = 0; w < FEATURE_WORDS; w++) {
1572 FeatureWordInfo *wi = &feature_word_info[w];
1573 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1574 qwi->cpuid_input_eax = wi->cpuid_eax;
1575 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1576 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1577 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1578 qwi->features = array[w];
8e8aba50
EH		 1579
1580 /* List will be in reverse order, but order shouldn't matter */
1581 list_entries[w].next = list;
1582 list_entries[w].value = &word_infos[w];
1583 list = &list_entries[w];
1584 }
1585
1586 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1587 error_propagate(errp, err);
1588}
1589
c1399112
EH		 1590static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def,
1591 const char *name)
c6dc6f63 1592{
c6dc6f63 1593 x86_def_t *def;
9337e3b6 1594 Error *err = NULL;
7fc9b714 1595 int i;
c6dc6f63 1596
4bfe910d
AF		 1597 if (name == NULL) {
1598 return -1;
9f3fb565 1599 }
4bfe910d 1600 if (kvm_enabled() && strcmp(name, "host") == 0) {
6e746f30 1601 kvm_cpu_fill_host(x86_cpu_def);
9337e3b6
EH		 1602 object_property_set_bool(OBJECT(cpu), true, "pmu", &err);
1603 assert_no_error(err);
4bfe910d 1604 return 0;
c6dc6f63
AP		 1605 }
1606
7fc9b714
AF		 1607 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1608 def = &builtin_x86_defs[i];
4bfe910d
AF		 1609 if (strcmp(name, def->name) == 0) {
1610 memcpy(x86_cpu_def, def, sizeof(*def));
11acfdd5
IM		 1611 /* sysenter isn't supported in compatibility mode on AMD,
1612 * syscall isn't supported in compatibility mode on Intel.
1613 * Normally we advertise the actual CPU vendor, but you can
1614 * override this using the 'vendor' property if you want to use
1615 * KVM's sysenter/syscall emulation in compatibility mode and
1616 * when doing cross vendor migration
1617 */
1618 if (kvm_enabled()) {
1619 uint32_t ebx = 0, ecx = 0, edx = 0;
1620 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1621 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1622 }
4bfe910d
AF		 1623 return 0;
1624 }
1625 }
1626
1627 return -1;
8f961357
EH		 1628}
1629
72ac2e87
IM		 1630/* Convert all '_' in a feature string option name to '-', to make feature
1631 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1632 */
1633static inline void feat2prop(char *s)
1634{
1635 while ((s = strchr(s, '_'))) {
1636 *s = '-';
1637 }
1638}
1639
8f961357
EH		 1640/* Parse "+feature,-feature,feature=foo" CPU feature string
1641 */
a91987c2 1642static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
8f961357 1643{
8f961357
EH		 1644 char *featurestr; /* Single 'key=value" string being parsed */
1645 /* Features to be added */
077c68c3 1646 FeatureWordArray plus_features = { 0 };
8f961357 1647 /* Features to be removed */
5ef57876 1648 FeatureWordArray minus_features = { 0 };
8f961357 1649 uint32_t numvalue;
a91987c2 1650 CPUX86State *env = &cpu->env;
8f961357 1651
8f961357 1652 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1653
1654 while (featurestr) {
1655 char *val;
1656 if (featurestr[0] == '+') {
5ef57876 1657 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1658 } else if (featurestr[0] == '-') {
5ef57876 1659 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1660 } else if ((val = strchr(featurestr, '='))) {
1661 *val = 0; val++;
72ac2e87 1662 feat2prop(featurestr);
c6dc6f63 1663 if (!strcmp(featurestr, "family")) {
a91987c2 1664 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1665 } else if (!strcmp(featurestr, "model")) {
a91987c2 1666 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1667 } else if (!strcmp(featurestr, "stepping")) {
a91987c2 1668 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1669 } else if (!strcmp(featurestr, "level")) {
a91987c2 1670 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63
AP		 1671 } else if (!strcmp(featurestr, "xlevel")) {
1672 char *err;
a91987c2
IM		 1673 char num[32];
1674
c6dc6f63
AP		 1675 numvalue = strtoul(val, &err, 0);
1676 if (!*val || *err) {
312fd5f2 1677 error_setg(errp, "bad numerical value %s", val);
a91987c2 1678 goto out;
c6dc6f63
AP		 1679 }
1680 if (numvalue < 0x80000000) {
8ba8a698
IM		 1681 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1682 ", fixup will be removed in future versions\n");
2f7a21c4 1683 numvalue += 0x80000000;
c6dc6f63 1684 }
a91987c2
IM		 1685 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1686 object_property_parse(OBJECT(cpu), num, featurestr, errp);
c6dc6f63 1687 } else if (!strcmp(featurestr, "vendor")) {
a91987c2 1688 object_property_parse(OBJECT(cpu), val, featurestr, errp);
72ac2e87
IM		 1689 } else if (!strcmp(featurestr, "model-id")) {
1690 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1691 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1692 int64_t tsc_freq;
1693 char *err;
a91987c2 1694 char num[32];
b862d1fe
JR		 1695
1696 tsc_freq = strtosz_suffix_unit(val, &err,
1697 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1698 if (tsc_freq < 0 || *err) {
312fd5f2 1699 error_setg(errp, "bad numerical value %s", val);
a91987c2 1700 goto out;
b862d1fe 1701 }
a91987c2
IM		 1702 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1703 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
72ac2e87 1704 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1705 char *err;
92067bf4 1706 const int min = 0xFFF;
28f52cc0
VR		 1707 numvalue = strtoul(val, &err, 0);
1708 if (!*val || *err) {
312fd5f2 1709 error_setg(errp, "bad numerical value %s", val);
a91987c2 1710 goto out;
28f52cc0 1711 }
92067bf4
IM		 1712 if (numvalue < min) {
1713 fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1714 ", fixup will be removed in future versions\n",
1715 min);
1716 numvalue = min;
1717 }
1718 cpu->hyperv_spinlock_attempts = numvalue;
c6dc6f63 1719 } else {
312fd5f2 1720 error_setg(errp, "unrecognized feature %s", featurestr);
a91987c2 1721 goto out;
c6dc6f63
AP		 1722 }
1723 } else if (!strcmp(featurestr, "check")) {
1724 check_cpuid = 1;
1725 } else if (!strcmp(featurestr, "enforce")) {
1726 check_cpuid = enforce_cpuid = 1;
28f52cc0 1727 } else if (!strcmp(featurestr, "hv_relaxed")) {
92067bf4 1728 cpu->hyperv_relaxed_timing = true;
28f52cc0 1729 } else if (!strcmp(featurestr, "hv_vapic")) {
92067bf4 1730 cpu->hyperv_vapic = true;
c6dc6f63 1731 } else {
a91987c2 1732 error_setg(errp, "feature string `%s' not in format (+feature|"
312fd5f2 1733 "-feature|feature=xyz)", featurestr);
a91987c2
IM		 1734 goto out;
1735 }
1736 if (error_is_set(errp)) {
1737 goto out;
c6dc6f63
AP		 1738 }
1739 featurestr = strtok(NULL, ",");
1740 }
0514ef2f
EH		 1741 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1742 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1743 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1744 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1745 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1746 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1747 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1748 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1749 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1750 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1751 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1752 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1753 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1754 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1755 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1756 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63 1757
a91987c2
IM		 1758out:
1759 return;
c6dc6f63
AP		 1760}
1761
1762/* generate a composite string into buf of all cpuid names in featureset
1763 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1764 * if flags, suppress names undefined in featureset.
1765 */
1766static void listflags(char *buf, int bufsize, uint32_t fbits,
1767 const char **featureset, uint32_t flags)
1768{
1769 const char **p = &featureset[31];
1770 char *q, *b, bit;
1771 int nc;
1772
1773 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1774 *buf = '\0';
1775 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1776 if (fbits & 1 << bit && (*p || !flags)) {
1777 if (*p)
1778 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1779 else
1780 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1781 if (bufsize <= nc) {
1782 if (b) {
1783 memcpy(b, "...", sizeof("..."));
1784 }
1785 return;
1786 }
1787 q += nc;
1788 bufsize -= nc;
1789 }
1790}
1791
e916cbf8
PM		 1792/* generate CPU information. */
1793void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1794{
c6dc6f63
AP		 1795 x86_def_t *def;
1796 char buf[256];
7fc9b714 1797 int i;
c6dc6f63 1798
7fc9b714
AF		 1799 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1800 def = &builtin_x86_defs[i];
c04321b3 1801 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1802 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1803 }
21ad7789
JK		 1804#ifdef CONFIG_KVM
1805 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1806 "KVM processor with all supported host features "
1807 "(only available in KVM mode)");
1808#endif
1809
6cdf8854 1810 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1811 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1812 FeatureWordInfo *fw = &feature_word_info[i];
1813
1814 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1815 (*cpu_fprintf)(f, " %s\n", buf);
1816 }
c6dc6f63
AP		 1817}
1818
76b64a7a 1819CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1820{
1821 CpuDefinitionInfoList *cpu_list = NULL;
1822 x86_def_t *def;
7fc9b714 1823 int i;
e3966126 1824
7fc9b714 1825 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1826 CpuDefinitionInfoList *entry;
1827 CpuDefinitionInfo *info;
1828
7fc9b714 1829 def = &builtin_x86_defs[i];
e3966126
AL		 1830 info = g_malloc0(sizeof(*info));
1831 info->name = g_strdup(def->name);
1832
1833 entry = g_malloc0(sizeof(*entry));
1834 entry->value = info;
1835 entry->next = cpu_list;
1836 cpu_list = entry;
1837 }
1838
1839 return cpu_list;
1840}
1841
bc74b7db
EH		 1842#ifdef CONFIG_KVM
1843static void filter_features_for_kvm(X86CPU *cpu)
1844{
1845 CPUX86State *env = &cpu->env;
1846 KVMState *s = kvm_state;
bd87d2a2 1847 FeatureWord w;
bc74b7db 1848
bd87d2a2
EH		 1849 for (w = 0; w < FEATURE_WORDS; w++) {
1850 FeatureWordInfo *wi = &feature_word_info[w];
034acf4a
EH		 1851 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1852 wi->cpuid_ecx,
1853 wi->cpuid_reg);
1854 uint32_t requested_features = env->features[w];
1855 env->features[w] &= host_feat;
1856 cpu->filtered_features[w] = requested_features & ~env->features[w];
bd87d2a2 1857 }
bc74b7db
EH		 1858}
1859#endif
1860
2d64255b 1861static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
c6dc6f63 1862{
61dcd775 1863 CPUX86State *env = &cpu->env;
c6dc6f63
AP		 1864 x86_def_t def1, *def = &def1;
1865
db0ad1ba
JR		 1866 memset(def, 0, sizeof(*def));
1867
c1399112 1868 if (cpu_x86_find_by_name(cpu, def, name) < 0) {
2d64255b
AF		 1869 error_setg(errp, "Unable to find CPU definition: %s", name);
1870 return;
8f961357
EH		 1871 }
1872
aa87d458 1873 if (kvm_enabled()) {
0514ef2f 1874 def->features[FEAT_KVM] |= kvm_default_features;
aa87d458 1875 }
0514ef2f 1876 def->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
077c68c3 1877
2d64255b
AF		 1878 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1879 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1880 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1881 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1882 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
0514ef2f
EH		 1883 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1884 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1885 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1886 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
2d64255b 1887 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
0514ef2f
EH		 1888 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1889 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1890 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1891 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
b3baa152 1892 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1893 cpu->cache_info_passthrough = def->cache_info_passthrough;
3b671a40 1894
2d64255b 1895 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
c6dc6f63
AP		 1896}
1897
62fc403f
IM		 1898X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1899 Error **errp)
5c3c6a68 1900{
2d64255b 1901 X86CPU *cpu = NULL;
5c3c6a68 1902 CPUX86State *env;
2d64255b
AF		 1903 gchar **model_pieces;
1904 char *name, *features;
ba2bc7a4 1905 char *typename;
5c3c6a68
AF		 1906 Error *error = NULL;
1907
2d64255b
AF		 1908 model_pieces = g_strsplit(cpu_model, ",", 2);
1909 if (!model_pieces[0]) {
1910 error_setg(&error, "Invalid/empty CPU model name");
1911 goto out;
1912 }
1913 name = model_pieces[0];
1914 features = model_pieces[1];
1915
5c3c6a68 1916 cpu = X86_CPU(object_new(TYPE_X86_CPU));
62fc403f
IM		 1917#ifndef CONFIG_USER_ONLY
1918 if (icc_bridge == NULL) {
1919 error_setg(&error, "Invalid icc-bridge value");
1920 goto out;
1921 }
1922 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1923 object_unref(OBJECT(cpu));
1924#endif
5c3c6a68
AF		 1925 env = &cpu->env;
1926 env->cpu_model_str = cpu_model;
1927
2d64255b
AF		 1928 cpu_x86_register(cpu, name, &error);
1929 if (error) {
1930 goto out;
1931 }
1932
ba2bc7a4
AF		 1933 /* Emulate per-model subclasses for global properties */
1934 typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1935 qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1936 g_free(typename);
1937 if (error) {
1938 goto out;
1939 }
1940
2d64255b
AF		 1941 cpu_x86_parse_featurestr(cpu, features, &error);
1942 if (error) {
1943 goto out;
5c3c6a68
AF		 1944 }
1945
7f833247 1946out:
cd7b87ff
AF		 1947 if (error != NULL) {
1948 error_propagate(errp, error);
1949 object_unref(OBJECT(cpu));
1950 cpu = NULL;
1951 }
7f833247
IM		 1952 g_strfreev(model_pieces);
1953 return cpu;
1954}
1955
1956X86CPU *cpu_x86_init(const char *cpu_model)
1957{
1958 Error *error = NULL;
1959 X86CPU *cpu;
1960
62fc403f 1961 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1962 if (error) {
2d64255b
AF		 1963 goto out;
1964 }
1965
7f833247
IM		 1966 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1967
2d64255b 1968out:
2d64255b 1969 if (error) {
4a44d85e 1970 error_report("%s", error_get_pretty(error));
5c3c6a68 1971 error_free(error);
2d64255b
AF		 1972 if (cpu != NULL) {
1973 object_unref(OBJECT(cpu));
1974 cpu = NULL;
1975 }
5c3c6a68
AF		 1976 }
1977 return cpu;
1978}
1979
c6dc6f63 1980#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1981
0e26b7b8
BS		 1982void cpu_clear_apic_feature(CPUX86State *env)
1983{
0514ef2f 1984 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 1985}
1986
c6dc6f63
AP		 1987#endif /* !CONFIG_USER_ONLY */
1988
c04321b3 1989/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1990 */
1991void x86_cpudef_setup(void)
1992{
93bfef4c
CV		 1993 int i, j;
1994 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1995
1996 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291 1997 x86_def_t *def = &builtin_x86_defs[i];
93bfef4c
CV		 1998
1999 /* Look for specific "cpudef" models that */
09faecf2 2000 /* have the QEMU version in .model_id */
93bfef4c 2001 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2002 if (strcmp(model_with_versions[j], def->name) == 0) {
2003 pstrcpy(def->model_id, sizeof(def->model_id),
2004 "QEMU Virtual CPU version ");
2005 pstrcat(def->model_id, sizeof(def->model_id),
2006 qemu_get_version());
93bfef4c
CV		 2007 break;
2008 }
2009 }
c6dc6f63 2010 }
c6dc6f63
AP		 2011}
2012
c6dc6f63
AP		 2013static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2014 uint32_t *ecx, uint32_t *edx)
2015{
2016 *ebx = env->cpuid_vendor1;
2017 *edx = env->cpuid_vendor2;
2018 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2019}
2020
2021void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2022 uint32_t *eax, uint32_t *ebx,
2023 uint32_t *ecx, uint32_t *edx)
2024{
a60f24b5
AF		 2025 X86CPU *cpu = x86_env_get_cpu(env);
2026 CPUState *cs = CPU(cpu);
2027
c6dc6f63
AP		 2028 /* test if maximum index reached */
2029 if (index & 0x80000000) {
b3baa152
BW		 2030 if (index > env->cpuid_xlevel) {
2031 if (env->cpuid_xlevel2 > 0) {
2032 /* Handle the Centaur's CPUID instruction. */
2033 if (index > env->cpuid_xlevel2) {
2034 index = env->cpuid_xlevel2;
2035 } else if (index < 0xC0000000) {
2036 index = env->cpuid_xlevel;
2037 }
2038 } else {
57f26ae7
EH		 2039 /* Intel documentation states that invalid EAX input will
2040 * return the same information as EAX=cpuid_level
2041 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2042 */
2043 index = env->cpuid_level;
b3baa152
BW		 2044 }
2045 }
c6dc6f63
AP		 2046 } else {
2047 if (index > env->cpuid_level)
2048 index = env->cpuid_level;
2049 }
2050
2051 switch(index) {
2052 case 0:
2053 *eax = env->cpuid_level;
2054 get_cpuid_vendor(env, ebx, ecx, edx);
2055 break;
2056 case 1:
2057 *eax = env->cpuid_version;
2058 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2059 *ecx = env->features[FEAT_1_ECX];
2060 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2061 if (cs->nr_cores * cs->nr_threads > 1) {
2062 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2063 *edx |= 1 << 28; /* HTT bit */
2064 }
2065 break;
2066 case 2:
2067 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2068 if (cpu->cache_info_passthrough) {
2069 host_cpuid(index, 0, eax, ebx, ecx, edx);
2070 break;
2071 }
5e891bf8 2072 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2073 *ebx = 0;
2074 *ecx = 0;
5e891bf8
EH		 2075 *edx = (L1D_DESCRIPTOR << 16) | \
2076 (L1I_DESCRIPTOR << 8) | \
2077 (L2_DESCRIPTOR);
c6dc6f63
AP		 2078 break;
2079 case 4:
2080 /* cache info: needed for Core compatibility */
787aaf57
BC		 2081 if (cpu->cache_info_passthrough) {
2082 host_cpuid(index, count, eax, ebx, ecx, edx);
2083 break;
2084 }
ce3960eb
AF		 2085 if (cs->nr_cores > 1) {
2086 *eax = (cs->nr_cores - 1) << 26;
c6dc6f63 2087 } else {
2f7a21c4 2088 *eax = 0;
c6dc6f63
AP		 2089 }
2090 switch (count) {
2091 case 0: /* L1 dcache info */
5e891bf8
EH		 2092 *eax |= CPUID_4_TYPE_DCACHE | \
2093 CPUID_4_LEVEL(1) | \
2094 CPUID_4_SELF_INIT_LEVEL;
2095 *ebx = (L1D_LINE_SIZE - 1) | \
2096 ((L1D_PARTITIONS - 1) << 12) | \
2097 ((L1D_ASSOCIATIVITY - 1) << 22);
2098 *ecx = L1D_SETS - 1;
2099 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2100 break;
2101 case 1: /* L1 icache info */
5e891bf8
EH		 2102 *eax |= CPUID_4_TYPE_ICACHE | \
2103 CPUID_4_LEVEL(1) | \
2104 CPUID_4_SELF_INIT_LEVEL;
2105 *ebx = (L1I_LINE_SIZE - 1) | \
2106 ((L1I_PARTITIONS - 1) << 12) | \
2107 ((L1I_ASSOCIATIVITY - 1) << 22);
2108 *ecx = L1I_SETS - 1;
2109 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2110 break;
2111 case 2: /* L2 cache info */
5e891bf8
EH		 2112 *eax |= CPUID_4_TYPE_UNIFIED | \
2113 CPUID_4_LEVEL(2) | \
2114 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2115 if (cs->nr_threads > 1) {
2116 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2117 }
5e891bf8
EH		 2118 *ebx = (L2_LINE_SIZE - 1) | \
2119 ((L2_PARTITIONS - 1) << 12) | \
2120 ((L2_ASSOCIATIVITY - 1) << 22);
2121 *ecx = L2_SETS - 1;
2122 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2123 break;
2124 default: /* end of info */
2125 *eax = 0;
2126 *ebx = 0;
2127 *ecx = 0;
2128 *edx = 0;
2129 break;
2130 }
2131 break;
2132 case 5:
2133 /* mwait info: needed for Core compatibility */
2134 *eax = 0; /* Smallest monitor-line size in bytes */
2135 *ebx = 0; /* Largest monitor-line size in bytes */
2136 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2137 *edx = 0;
2138 break;
2139 case 6:
2140 /* Thermal and Power Leaf */
2141 *eax = 0;
2142 *ebx = 0;
2143 *ecx = 0;
2144 *edx = 0;
2145 break;
f7911686 2146 case 7:
13526728
EH		 2147 /* Structured Extended Feature Flags Enumeration Leaf */
2148 if (count == 0) {
2149 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2150 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2151 *ecx = 0; /* Reserved */
2152 *edx = 0; /* Reserved */
f7911686
YW		 2153 } else {
2154 *eax = 0;
2155 *ebx = 0;
2156 *ecx = 0;
2157 *edx = 0;
2158 }
2159 break;
c6dc6f63
AP		 2160 case 9:
2161 /* Direct Cache Access Information Leaf */
2162 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2163 *ebx = 0;
2164 *ecx = 0;
2165 *edx = 0;
2166 break;
2167 case 0xA:
2168 /* Architectural Performance Monitoring Leaf */
9337e3b6 2169 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2170 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2171
2172 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2173 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2174 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2175 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2176 } else {
2177 *eax = 0;
2178 *ebx = 0;
2179 *ecx = 0;
2180 *edx = 0;
2181 }
c6dc6f63 2182 break;
51e49430
SY		 2183 case 0xD:
2184 /* Processor Extended State */
0514ef2f 2185 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2186 *eax = 0;
2187 *ebx = 0;
2188 *ecx = 0;
2189 *edx = 0;
2190 break;
2191 }
2192 if (kvm_enabled()) {
a60f24b5 2193 KVMState *s = cs->kvm_state;
ba9bc59e
JK		 2194
2195 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
2196 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
2197 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
2198 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 2199 } else {
2200 *eax = 0;
2201 *ebx = 0;
2202 *ecx = 0;
2203 *edx = 0;
2204 }
2205 break;
c6dc6f63
AP		 2206 case 0x80000000:
2207 *eax = env->cpuid_xlevel;
2208 *ebx = env->cpuid_vendor1;
2209 *edx = env->cpuid_vendor2;
2210 *ecx = env->cpuid_vendor3;
2211 break;
2212 case 0x80000001:
2213 *eax = env->cpuid_version;
2214 *ebx = 0;
0514ef2f
EH		 2215 *ecx = env->features[FEAT_8000_0001_ECX];
2216 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2217
2218 /* The Linux kernel checks for the CMPLegacy bit and
2219 * discards multiple thread information if it is set.
2220 * So dont set it here for Intel to make Linux guests happy.
2221 */
ce3960eb 2222 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2223 uint32_t tebx, tecx, tedx;
2224 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2225 if (tebx != CPUID_VENDOR_INTEL_1 ||
2226 tedx != CPUID_VENDOR_INTEL_2 ||
2227 tecx != CPUID_VENDOR_INTEL_3) {
2228 *ecx |= 1 << 1; /* CmpLegacy bit */
2229 }
2230 }
c6dc6f63
AP		 2231 break;
2232 case 0x80000002:
2233 case 0x80000003:
2234 case 0x80000004:
2235 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2236 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2237 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2238 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2239 break;
2240 case 0x80000005:
2241 /* cache info (L1 cache) */
787aaf57
BC		 2242 if (cpu->cache_info_passthrough) {
2243 host_cpuid(index, 0, eax, ebx, ecx, edx);
2244 break;
2245 }
5e891bf8
EH		 2246 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2247 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2248 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2249 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2250 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2251 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2252 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2253 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2254 break;
2255 case 0x80000006:
2256 /* cache info (L2 cache) */
787aaf57
BC		 2257 if (cpu->cache_info_passthrough) {
2258 host_cpuid(index, 0, eax, ebx, ecx, edx);
2259 break;
2260 }
5e891bf8
EH		 2261 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2262 (L2_DTLB_2M_ENTRIES << 16) | \
2263 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2264 (L2_ITLB_2M_ENTRIES);
2265 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2266 (L2_DTLB_4K_ENTRIES << 16) | \
2267 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2268 (L2_ITLB_4K_ENTRIES);
2269 *ecx = (L2_SIZE_KB_AMD << 16) | \
2270 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2271 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2272 *edx = ((L3_SIZE_KB/512) << 18) | \
2273 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2274 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP		 2275 break;
2276 case 0x80000008:
2277 /* virtual & phys address size in low 2 bytes. */
2278/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2279 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2280 /* 64 bit processor */
2281/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2282 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2283 } else {
0514ef2f 2284 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2285 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2286 } else {
c6dc6f63 2287 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2288 }
c6dc6f63
AP		 2289 }
2290 *ebx = 0;
2291 *ecx = 0;
2292 *edx = 0;
ce3960eb
AF		 2293 if (cs->nr_cores * cs->nr_threads > 1) {
2294 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2295 }
2296 break;
2297 case 0x8000000A:
0514ef2f 2298 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2299 *eax = 0x00000001; /* SVM Revision */
2300 *ebx = 0x00000010; /* nr of ASIDs */
2301 *ecx = 0;
0514ef2f 2302 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2303 } else {
2304 *eax = 0;
2305 *ebx = 0;
2306 *ecx = 0;
2307 *edx = 0;
2308 }
c6dc6f63 2309 break;
b3baa152
BW		 2310 case 0xC0000000:
2311 *eax = env->cpuid_xlevel2;
2312 *ebx = 0;
2313 *ecx = 0;
2314 *edx = 0;
2315 break;
2316 case 0xC0000001:
2317 /* Support for VIA CPU's CPUID instruction */
2318 *eax = env->cpuid_version;
2319 *ebx = 0;
2320 *ecx = 0;
0514ef2f 2321 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2322 break;
2323 case 0xC0000002:
2324 case 0xC0000003:
2325 case 0xC0000004:
2326 /* Reserved for the future, and now filled with zero */
2327 *eax = 0;
2328 *ebx = 0;
2329 *ecx = 0;
2330 *edx = 0;
2331 break;
c6dc6f63
AP		 2332 default:
2333 /* reserved values: zero */
2334 *eax = 0;
2335 *ebx = 0;
2336 *ecx = 0;
2337 *edx = 0;
2338 break;
2339 }
2340}
5fd2087a
AF		 2341
2342/* CPUClass::reset() */
2343static void x86_cpu_reset(CPUState *s)
2344{
2345 X86CPU *cpu = X86_CPU(s);
2346 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2347 CPUX86State *env = &cpu->env;
c1958aea
AF		 2348 int i;
2349
5fd2087a
AF		 2350 xcc->parent_reset(s);
2351
c1958aea
AF		 2352
2353 memset(env, 0, offsetof(CPUX86State, breakpoints));
2354
2355 tlb_flush(env, 1);
2356
2357 env->old_exception = -1;
2358
2359 /* init to reset state */
2360
2361#ifdef CONFIG_SOFTMMU
2362 env->hflags |= HF_SOFTMMU_MASK;
2363#endif
2364 env->hflags2 |= HF2_GIF_MASK;
2365
2366 cpu_x86_update_cr0(env, 0x60000010);
2367 env->a20_mask = ~0x0;
2368 env->smbase = 0x30000;
2369
2370 env->idt.limit = 0xffff;
2371 env->gdt.limit = 0xffff;
2372 env->ldt.limit = 0xffff;
2373 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2374 env->tr.limit = 0xffff;
2375 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2376
2377 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2378 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2379 DESC_R_MASK | DESC_A_MASK);
2380 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2381 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2382 DESC_A_MASK);
2383 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2384 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2385 DESC_A_MASK);
2386 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2387 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2388 DESC_A_MASK);
2389 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2390 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2391 DESC_A_MASK);
2392 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2393 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2394 DESC_A_MASK);
2395
2396 env->eip = 0xfff0;
2397 env->regs[R_EDX] = env->cpuid_version;
2398
2399 env->eflags = 0x2;
2400
2401 /* FPU init */
2402 for (i = 0; i < 8; i++) {
2403 env->fptags[i] = 1;
2404 }
2405 env->fpuc = 0x37f;
2406
2407 env->mxcsr = 0x1f80;
2408
2409 env->pat = 0x0007040600070406ULL;
2410 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2411
2412 memset(env->dr, 0, sizeof(env->dr));
2413 env->dr[6] = DR6_FIXED_1;
2414 env->dr[7] = DR7_FIXED_1;
2415 cpu_breakpoint_remove_all(env, BP_CPU);
2416 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 2417
2418#if !defined(CONFIG_USER_ONLY)
2419 /* We hard-wire the BSP to the first CPU. */
55e5c285 2420 if (s->cpu_index == 0) {
dd673288
IM		 2421 apic_designate_bsp(env->apic_state);
2422 }
2423
259186a7 2424 s->halted = !cpu_is_bsp(cpu);
dd673288 2425#endif
5fd2087a
AF		 2426}
2427
dd673288
IM		 2428#ifndef CONFIG_USER_ONLY
2429bool cpu_is_bsp(X86CPU *cpu)
2430{
2431 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2432}
65dee380
IM		 2433
2434/* TODO: remove me, when reset over QOM tree is implemented */
2435static void x86_cpu_machine_reset_cb(void *opaque)
2436{
2437 X86CPU *cpu = opaque;
2438 cpu_reset(CPU(cpu));
2439}
dd673288
IM		 2440#endif
2441
de024815
AF		 2442static void mce_init(X86CPU *cpu)
2443{
2444 CPUX86State *cenv = &cpu->env;
2445 unsigned int bank;
2446
2447 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2448 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2449 (CPUID_MCE | CPUID_MCA)) {
2450 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2451 cenv->mcg_ctl = ~(uint64_t)0;
2452 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2453 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2454 }
2455 }
2456}
2457
bdeec802 2458#ifndef CONFIG_USER_ONLY
d3c64d6a 2459static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2460{
bdeec802 2461 CPUX86State *env = &cpu->env;
53a89e26 2462 DeviceState *dev = DEVICE(cpu);
449994eb 2463 APICCommonState *apic;
bdeec802
IM		 2464 const char *apic_type = "apic";
2465
2466 if (kvm_irqchip_in_kernel()) {
2467 apic_type = "kvm-apic";
2468 } else if (xen_enabled()) {
2469 apic_type = "xen-apic";
2470 }
2471
53a89e26 2472 env->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
bdeec802
IM		 2473 if (env->apic_state == NULL) {
2474 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2475 return;
2476 }
2477
2478 object_property_add_child(OBJECT(cpu), "apic",
2479 OBJECT(env->apic_state), NULL);
2480 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2481 /* TODO: convert to link<> */
449994eb 2482 apic = APIC_COMMON(env->apic_state);
60671e58 2483 apic->cpu = cpu;
d3c64d6a
IM		 2484}
2485
2486static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2487{
2488 CPUX86State *env = &cpu->env;
d3c64d6a
IM		 2489
2490 if (env->apic_state == NULL) {
2491 return;
2492 }
bdeec802
IM		 2493
2494 if (qdev_init(env->apic_state)) {
2495 error_setg(errp, "APIC device '%s' could not be initialized",
2496 object_get_typename(OBJECT(env->apic_state)));
2497 return;
2498 }
bdeec802 2499}
d3c64d6a
IM		 2500#else
2501static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2502{
2503}
bdeec802
IM		 2504#endif
2505
2b6f294c 2506static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2507{
14a10fc3 2508 CPUState *cs = CPU(dev);
2b6f294c
AF		 2509 X86CPU *cpu = X86_CPU(dev);
2510 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2511 CPUX86State *env = &cpu->env;
2b6f294c 2512 Error *local_err = NULL;
b34d12d1 2513
0514ef2f 2514 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2515 env->cpuid_level = 7;
2516 }
7a059953 2517
9b15cd9e
IM		 2518 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2519 * CPUID[1].EDX.
2520 */
2521 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2522 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2523 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2524 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2525 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2526 & CPUID_EXT2_AMD_ALIASES);
2527 }
2528
4586f157 2529 if (!kvm_enabled()) {
0514ef2f
EH		 2530 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2531 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2532 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
4586f157
IM		 2533#ifdef TARGET_X86_64
2534 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2535#endif
2536 );
0514ef2f
EH		 2537 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2538 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
4586f157 2539 } else {
5ec01c2e
IM		 2540 if (check_cpuid && kvm_check_features_against_host(cpu)
2541 && enforce_cpuid) {
4dc1f449
IM		 2542 error_setg(&local_err,
2543 "Host's CPU doesn't support requested features");
2544 goto out;
5ec01c2e 2545 }
a509d632
EH		 2546#ifdef CONFIG_KVM
2547 filter_features_for_kvm(cpu);
2548#endif
4586f157
IM		 2549 }
2550
65dee380
IM		 2551#ifndef CONFIG_USER_ONLY
2552 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2553
0514ef2f 2554 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2555 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2556 if (local_err != NULL) {
4dc1f449 2557 goto out;
bdeec802
IM		 2558 }
2559 }
65dee380
IM		 2560#endif
2561
7a059953 2562 mce_init(cpu);
14a10fc3 2563 qemu_init_vcpu(cs);
d3c64d6a
IM		 2564
2565 x86_cpu_apic_realize(cpu, &local_err);
2566 if (local_err != NULL) {
2567 goto out;
2568 }
14a10fc3 2569 cpu_reset(cs);
2b6f294c 2570
4dc1f449
IM		 2571 xcc->parent_realize(dev, &local_err);
2572out:
2573 if (local_err != NULL) {
2574 error_propagate(errp, local_err);
2575 return;
2576 }
7a059953
AF		 2577}
2578
8932cfdf
EH		 2579/* Enables contiguous-apic-ID mode, for compatibility */
2580static bool compat_apic_id_mode;
2581
2582void enable_compat_apic_id_mode(void)
2583{
2584 compat_apic_id_mode = true;
2585}
2586
cb41bad3
EH		 2587/* Calculates initial APIC ID for a specific CPU index
2588 *
2589 * Currently we need to be able to calculate the APIC ID from the CPU index
2590 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2591 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2592 * all CPUs up to max_cpus.
2593 */
2594uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2595{
8932cfdf
EH		 2596 uint32_t correct_id;
2597 static bool warned;
2598
2599 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2600 if (compat_apic_id_mode) {
2601 if (cpu_index != correct_id && !warned) {
2602 error_report("APIC IDs set in compatibility mode, "
2603 "CPU topology won't match the configuration");
2604 warned = true;
2605 }
2606 return cpu_index;
2607 } else {
2608 return correct_id;
2609 }
cb41bad3
EH		 2610}
2611
de024815
AF		 2612static void x86_cpu_initfn(Object *obj)
2613{
55e5c285 2614 CPUState *cs = CPU(obj);
de024815
AF		 2615 X86CPU *cpu = X86_CPU(obj);
2616 CPUX86State *env = &cpu->env;
d65e9815 2617 static int inited;
de024815 2618
c05efcb1 2619 cs->env_ptr = env;
de024815 2620 cpu_exec_init(env);
71ad61d3
AF		 2621
2622 object_property_add(obj, "family", "int",
95b8519d 2623 x86_cpuid_version_get_family,
71ad61d3 2624 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2625 object_property_add(obj, "model", "int",
67e30c83 2626 x86_cpuid_version_get_model,
c5291a4f 2627 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2628 object_property_add(obj, "stepping", "int",
35112e41 2629 x86_cpuid_version_get_stepping,
036e2222 2630 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2631 object_property_add(obj, "level", "int",
2632 x86_cpuid_get_level,
2633 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2634 object_property_add(obj, "xlevel", "int",
2635 x86_cpuid_get_xlevel,
2636 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2637 object_property_add_str(obj, "vendor",
2638 x86_cpuid_get_vendor,
2639 x86_cpuid_set_vendor, NULL);
938d4c25 2640 object_property_add_str(obj, "model-id",
63e886eb 2641 x86_cpuid_get_model_id,
938d4c25 2642 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2643 object_property_add(obj, "tsc-frequency", "int",
2644 x86_cpuid_get_tsc_freq,
2645 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2646 object_property_add(obj, "apic-id", "int",
2647 x86_cpuid_get_apic_id,
2648 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2649 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2650 x86_cpu_get_feature_words,
7e5292b5
EH		 2651 NULL, NULL, (void *)env->features, NULL);
2652 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2653 x86_cpu_get_feature_words,
2654 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2655
92067bf4 2656 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2657 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815
IM		 2658
2659 /* init various static tables used in TCG mode */
2660 if (tcg_enabled() && !inited) {
2661 inited = 1;
2662 optimize_flags_init();
2663#ifndef CONFIG_USER_ONLY
2664 cpu_set_debug_excp_handler(breakpoint_handler);
2665#endif
2666 }
de024815
AF		 2667}
2668
997395d3
IM		 2669static int64_t x86_cpu_get_arch_id(CPUState *cs)
2670{
2671 X86CPU *cpu = X86_CPU(cs);
2672 CPUX86State *env = &cpu->env;
2673
2674 return env->cpuid_apic_id;
2675}
2676
444d5590
AF		 2677static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2678{
2679 X86CPU *cpu = X86_CPU(cs);
2680
2681 return cpu->env.cr[0] & CR0_PG_MASK;
2682}
2683
f45748f1
AF		 2684static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2685{
2686 X86CPU *cpu = X86_CPU(cs);
2687
2688 cpu->env.eip = value;
2689}
2690
bdf7ae5b
AF		 2691static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2692{
2693 X86CPU *cpu = X86_CPU(cs);
2694
2695 cpu->env.eip = tb->pc - tb->cs_base;
2696}
2697
9337e3b6
EH		 2698static Property x86_cpu_properties[] = {
2699 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2700 DEFINE_PROP_END_OF_LIST()
2701};
2702
5fd2087a
AF		 2703static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2704{
2705 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2706 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2707 DeviceClass *dc = DEVICE_CLASS(oc);
2708
2709 xcc->parent_realize = dc->realize;
2710 dc->realize = x86_cpu_realizefn;
62fc403f 2711 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2712 dc->props = x86_cpu_properties;
5fd2087a
AF		 2713
2714 xcc->parent_reset = cc->reset;
2715 cc->reset = x86_cpu_reset;
91b1df8c 2716 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2717
97a8ea5a 2718 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2719 cc->dump_state = x86_cpu_dump_state;
f45748f1 2720 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2721 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2722 cc->gdb_read_register = x86_cpu_gdb_read_register;
2723 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2724 cc->get_arch_id = x86_cpu_get_arch_id;
2725 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
c72bf468 2726#ifndef CONFIG_USER_ONLY
a23bbfda 2727 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2728 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2729 cc->write_elf64_note = x86_cpu_write_elf64_note;
2730 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2731 cc->write_elf32_note = x86_cpu_write_elf32_note;
2732 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2733 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2734#endif
a0e372f0 2735 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2736}
2737
2738static const TypeInfo x86_cpu_type_info = {
2739 .name = TYPE_X86_CPU,
2740 .parent = TYPE_CPU,
2741 .instance_size = sizeof(X86CPU),
de024815 2742 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2743 .abstract = false,
2744 .class_size = sizeof(X86CPUClass),
2745 .class_init = x86_cpu_common_class_init,
2746};
2747
2748static void x86_cpu_register_types(void)
2749{
2750 type_register_static(&x86_cpu_type_info);
2751}
2752
2753type_init(x86_cpu_register_types)
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