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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
e495606d | 23 | |
6aa8b732 | 24 | #include <linux/module.h> |
9d8f549d | 25 | #include <linux/kernel.h> |
6aa8b732 AK |
26 | #include <linux/vmalloc.h> |
27 | #include <linux/highmem.h> | |
e8edc6e0 | 28 | #include <linux/sched.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
6aa8b732 | 31 | |
67ec6607 | 32 | #include <asm/tlbflush.h> |
e495606d | 33 | #include <asm/desc.h> |
631bc487 | 34 | #include <asm/kvm_para.h> |
6aa8b732 | 35 | |
63d1142f | 36 | #include <asm/virtext.h> |
229456fc | 37 | #include "trace.h" |
63d1142f | 38 | |
4ecac3fd AK |
39 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
40 | ||
6aa8b732 AK |
41 | MODULE_AUTHOR("Qumranet"); |
42 | MODULE_LICENSE("GPL"); | |
43 | ||
44 | #define IOPM_ALLOC_ORDER 2 | |
45 | #define MSRPM_ALLOC_ORDER 1 | |
46 | ||
6aa8b732 AK |
47 | #define SEG_TYPE_LDT 2 |
48 | #define SEG_TYPE_BUSY_TSS16 3 | |
49 | ||
6bc31bdc AP |
50 | #define SVM_FEATURE_NPT (1 << 0) |
51 | #define SVM_FEATURE_LBRV (1 << 1) | |
52 | #define SVM_FEATURE_SVML (1 << 2) | |
53 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
54 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
55 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
56 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
57 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 58 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 59 | |
410e4d57 JR |
60 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
61 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
62 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
63 | ||
24e09cbf JR |
64 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
65 | ||
fbc0db76 | 66 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
67 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
68 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 69 | |
67ec6607 JR |
70 | static bool erratum_383_found __read_mostly; |
71 | ||
6c8166a7 AK |
72 | static const u32 host_save_user_msrs[] = { |
73 | #ifdef CONFIG_X86_64 | |
74 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
75 | MSR_FS_BASE, | |
76 | #endif | |
77 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
78 | }; | |
79 | ||
80 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
81 | ||
82 | struct kvm_vcpu; | |
83 | ||
e6aa9abd JR |
84 | struct nested_state { |
85 | struct vmcb *hsave; | |
86 | u64 hsave_msr; | |
4a810181 | 87 | u64 vm_cr_msr; |
e6aa9abd JR |
88 | u64 vmcb; |
89 | ||
90 | /* These are the merged vectors */ | |
91 | u32 *msrpm; | |
92 | ||
93 | /* gpa pointers to the real vectors */ | |
94 | u64 vmcb_msrpm; | |
ce2ac085 | 95 | u64 vmcb_iopm; |
aad42c64 | 96 | |
cd3ff653 JR |
97 | /* A VMEXIT is required but not yet emulated */ |
98 | bool exit_required; | |
99 | ||
aad42c64 | 100 | /* cache for intercepts of the guest */ |
4ee546b4 | 101 | u32 intercept_cr; |
3aed041a | 102 | u32 intercept_dr; |
aad42c64 JR |
103 | u32 intercept_exceptions; |
104 | u64 intercept; | |
105 | ||
5bd2edc3 JR |
106 | /* Nested Paging related state */ |
107 | u64 nested_cr3; | |
e6aa9abd JR |
108 | }; |
109 | ||
323c3d80 JR |
110 | #define MSRPM_OFFSETS 16 |
111 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
112 | ||
2b036c6b BO |
113 | /* |
114 | * Set osvw_len to higher value when updated Revision Guides | |
115 | * are published and we know what the new status bits are | |
116 | */ | |
117 | static uint64_t osvw_len = 4, osvw_status; | |
118 | ||
6c8166a7 AK |
119 | struct vcpu_svm { |
120 | struct kvm_vcpu vcpu; | |
121 | struct vmcb *vmcb; | |
122 | unsigned long vmcb_pa; | |
123 | struct svm_cpu_data *svm_data; | |
124 | uint64_t asid_generation; | |
125 | uint64_t sysenter_esp; | |
126 | uint64_t sysenter_eip; | |
127 | ||
128 | u64 next_rip; | |
129 | ||
130 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 131 | struct { |
dacccfdd AK |
132 | u16 fs; |
133 | u16 gs; | |
134 | u16 ldt; | |
afe9e66f AK |
135 | u64 gs_base; |
136 | } host; | |
6c8166a7 AK |
137 | |
138 | u32 *msrpm; | |
6c8166a7 | 139 | |
bd3d1ec3 AK |
140 | ulong nmi_iret_rip; |
141 | ||
e6aa9abd | 142 | struct nested_state nested; |
6be7d306 JK |
143 | |
144 | bool nmi_singlestep; | |
66b7138f JK |
145 | |
146 | unsigned int3_injected; | |
147 | unsigned long int3_rip; | |
631bc487 | 148 | u32 apf_reason; |
fbc0db76 JR |
149 | |
150 | u64 tsc_ratio; | |
6c8166a7 AK |
151 | }; |
152 | ||
fbc0db76 JR |
153 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
154 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
155 | ||
455716fa JR |
156 | #define MSR_INVALID 0xffffffffU |
157 | ||
ac72a9b7 JR |
158 | static struct svm_direct_access_msrs { |
159 | u32 index; /* Index of the MSR */ | |
160 | bool always; /* True if intercept is always on */ | |
161 | } direct_access_msrs[] = { | |
8c06585d | 162 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
163 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
164 | #ifdef CONFIG_X86_64 | |
165 | { .index = MSR_GS_BASE, .always = true }, | |
166 | { .index = MSR_FS_BASE, .always = true }, | |
167 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
168 | { .index = MSR_LSTAR, .always = true }, | |
169 | { .index = MSR_CSTAR, .always = true }, | |
170 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
171 | #endif | |
172 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
173 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
174 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
175 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
176 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
177 | }; |
178 | ||
709ddebf JR |
179 | /* enable NPT for AMD64 and X86 with PAE */ |
180 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
181 | static bool npt_enabled = true; | |
182 | #else | |
e0231715 | 183 | static bool npt_enabled; |
709ddebf | 184 | #endif |
6c7dac72 | 185 | |
e2358851 DB |
186 | /* allow nested paging (virtualized MMU) for all guests */ |
187 | static int npt = true; | |
6c7dac72 | 188 | module_param(npt, int, S_IRUGO); |
e3da3acd | 189 | |
e2358851 DB |
190 | /* allow nested virtualization in KVM/SVM */ |
191 | static int nested = true; | |
236de055 AG |
192 | module_param(nested, int, S_IRUGO); |
193 | ||
44874f84 | 194 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 195 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 196 | |
410e4d57 | 197 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 198 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 199 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
200 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
201 | bool has_error_code, u32 error_code); | |
92a1f12d | 202 | static u64 __scale_tsc(u64 ratio, u64 tsc); |
cf74a78b | 203 | |
8d28fec4 | 204 | enum { |
116a0a23 JR |
205 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
206 | pause filter count */ | |
f56838e4 | 207 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 208 | VMCB_ASID, /* ASID */ |
decdbf6a | 209 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 210 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 211 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 212 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 213 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 214 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 215 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 216 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
8d28fec4 RJ |
217 | VMCB_DIRTY_MAX, |
218 | }; | |
219 | ||
0574dec0 JR |
220 | /* TPR and CR2 are always written before VMRUN */ |
221 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 RJ |
222 | |
223 | static inline void mark_all_dirty(struct vmcb *vmcb) | |
224 | { | |
225 | vmcb->control.clean = 0; | |
226 | } | |
227 | ||
228 | static inline void mark_all_clean(struct vmcb *vmcb) | |
229 | { | |
230 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
231 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
232 | } | |
233 | ||
234 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
235 | { | |
236 | vmcb->control.clean &= ~(1 << bit); | |
237 | } | |
238 | ||
a2fa3e9f GH |
239 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
240 | { | |
fb3f0f51 | 241 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
242 | } |
243 | ||
384c6368 JR |
244 | static void recalc_intercepts(struct vcpu_svm *svm) |
245 | { | |
246 | struct vmcb_control_area *c, *h; | |
247 | struct nested_state *g; | |
248 | ||
116a0a23 JR |
249 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
250 | ||
384c6368 JR |
251 | if (!is_guest_mode(&svm->vcpu)) |
252 | return; | |
253 | ||
254 | c = &svm->vmcb->control; | |
255 | h = &svm->nested.hsave->control; | |
256 | g = &svm->nested; | |
257 | ||
4ee546b4 | 258 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 259 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
260 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
261 | c->intercept = h->intercept | g->intercept; | |
262 | } | |
263 | ||
4ee546b4 RJ |
264 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
265 | { | |
266 | if (is_guest_mode(&svm->vcpu)) | |
267 | return svm->nested.hsave; | |
268 | else | |
269 | return svm->vmcb; | |
270 | } | |
271 | ||
272 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
273 | { | |
274 | struct vmcb *vmcb = get_host_vmcb(svm); | |
275 | ||
276 | vmcb->control.intercept_cr |= (1U << bit); | |
277 | ||
278 | recalc_intercepts(svm); | |
279 | } | |
280 | ||
281 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
282 | { | |
283 | struct vmcb *vmcb = get_host_vmcb(svm); | |
284 | ||
285 | vmcb->control.intercept_cr &= ~(1U << bit); | |
286 | ||
287 | recalc_intercepts(svm); | |
288 | } | |
289 | ||
290 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
291 | { | |
292 | struct vmcb *vmcb = get_host_vmcb(svm); | |
293 | ||
294 | return vmcb->control.intercept_cr & (1U << bit); | |
295 | } | |
296 | ||
3aed041a JR |
297 | static inline void set_dr_intercept(struct vcpu_svm *svm, int bit) |
298 | { | |
299 | struct vmcb *vmcb = get_host_vmcb(svm); | |
300 | ||
301 | vmcb->control.intercept_dr |= (1U << bit); | |
302 | ||
303 | recalc_intercepts(svm); | |
304 | } | |
305 | ||
306 | static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit) | |
307 | { | |
308 | struct vmcb *vmcb = get_host_vmcb(svm); | |
309 | ||
310 | vmcb->control.intercept_dr &= ~(1U << bit); | |
311 | ||
312 | recalc_intercepts(svm); | |
313 | } | |
314 | ||
18c918c5 JR |
315 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
316 | { | |
317 | struct vmcb *vmcb = get_host_vmcb(svm); | |
318 | ||
319 | vmcb->control.intercept_exceptions |= (1U << bit); | |
320 | ||
321 | recalc_intercepts(svm); | |
322 | } | |
323 | ||
324 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
325 | { | |
326 | struct vmcb *vmcb = get_host_vmcb(svm); | |
327 | ||
328 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
329 | ||
330 | recalc_intercepts(svm); | |
331 | } | |
332 | ||
8a05a1b8 JR |
333 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
334 | { | |
335 | struct vmcb *vmcb = get_host_vmcb(svm); | |
336 | ||
337 | vmcb->control.intercept |= (1ULL << bit); | |
338 | ||
339 | recalc_intercepts(svm); | |
340 | } | |
341 | ||
342 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
343 | { | |
344 | struct vmcb *vmcb = get_host_vmcb(svm); | |
345 | ||
346 | vmcb->control.intercept &= ~(1ULL << bit); | |
347 | ||
348 | recalc_intercepts(svm); | |
349 | } | |
350 | ||
2af9194d JR |
351 | static inline void enable_gif(struct vcpu_svm *svm) |
352 | { | |
353 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
354 | } | |
355 | ||
356 | static inline void disable_gif(struct vcpu_svm *svm) | |
357 | { | |
358 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
359 | } | |
360 | ||
361 | static inline bool gif_set(struct vcpu_svm *svm) | |
362 | { | |
363 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
364 | } | |
365 | ||
4866d5e3 | 366 | static unsigned long iopm_base; |
6aa8b732 AK |
367 | |
368 | struct kvm_ldttss_desc { | |
369 | u16 limit0; | |
370 | u16 base0; | |
e0231715 JR |
371 | unsigned base1:8, type:5, dpl:2, p:1; |
372 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
373 | u32 base3; |
374 | u32 zero1; | |
375 | } __attribute__((packed)); | |
376 | ||
377 | struct svm_cpu_data { | |
378 | int cpu; | |
379 | ||
5008fdf5 AK |
380 | u64 asid_generation; |
381 | u32 max_asid; | |
382 | u32 next_asid; | |
6aa8b732 AK |
383 | struct kvm_ldttss_desc *tss_desc; |
384 | ||
385 | struct page *save_area; | |
386 | }; | |
387 | ||
388 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
389 | ||
390 | struct svm_init_data { | |
391 | int cpu; | |
392 | int r; | |
393 | }; | |
394 | ||
395 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
396 | ||
9d8f549d | 397 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
398 | #define MSRS_RANGE_SIZE 2048 |
399 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
400 | ||
455716fa JR |
401 | static u32 svm_msrpm_offset(u32 msr) |
402 | { | |
403 | u32 offset; | |
404 | int i; | |
405 | ||
406 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
407 | if (msr < msrpm_ranges[i] || | |
408 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
409 | continue; | |
410 | ||
411 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
412 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
413 | ||
414 | /* Now we have the u8 offset - but need the u32 offset */ | |
415 | return offset / 4; | |
416 | } | |
417 | ||
418 | /* MSR not in any range */ | |
419 | return MSR_INVALID; | |
420 | } | |
421 | ||
6aa8b732 AK |
422 | #define MAX_INST_SIZE 15 |
423 | ||
6aa8b732 AK |
424 | static inline void clgi(void) |
425 | { | |
4ecac3fd | 426 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
427 | } |
428 | ||
429 | static inline void stgi(void) | |
430 | { | |
4ecac3fd | 431 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
432 | } |
433 | ||
434 | static inline void invlpga(unsigned long addr, u32 asid) | |
435 | { | |
e0231715 | 436 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
437 | } |
438 | ||
4b16184c JR |
439 | static int get_npt_level(void) |
440 | { | |
441 | #ifdef CONFIG_X86_64 | |
442 | return PT64_ROOT_LEVEL; | |
443 | #else | |
444 | return PT32E_ROOT_LEVEL; | |
445 | #endif | |
446 | } | |
447 | ||
6aa8b732 AK |
448 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
449 | { | |
6dc696d4 | 450 | vcpu->arch.efer = efer; |
709ddebf | 451 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 452 | efer &= ~EFER_LME; |
6aa8b732 | 453 | |
9962d032 | 454 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 455 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
456 | } |
457 | ||
6aa8b732 AK |
458 | static int is_external_interrupt(u32 info) |
459 | { | |
460 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
461 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
462 | } | |
463 | ||
2809f5d2 GC |
464 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
465 | { | |
466 | struct vcpu_svm *svm = to_svm(vcpu); | |
467 | u32 ret = 0; | |
468 | ||
469 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 470 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
471 | return ret & mask; |
472 | } | |
473 | ||
474 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
475 | { | |
476 | struct vcpu_svm *svm = to_svm(vcpu); | |
477 | ||
478 | if (mask == 0) | |
479 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
480 | else | |
481 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
482 | ||
483 | } | |
484 | ||
6aa8b732 AK |
485 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
486 | { | |
a2fa3e9f GH |
487 | struct vcpu_svm *svm = to_svm(vcpu); |
488 | ||
6bc31bdc AP |
489 | if (svm->vmcb->control.next_rip != 0) |
490 | svm->next_rip = svm->vmcb->control.next_rip; | |
491 | ||
a2fa3e9f | 492 | if (!svm->next_rip) { |
51d8b661 | 493 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
494 | EMULATE_DONE) |
495 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
496 | return; |
497 | } | |
5fdbf976 MT |
498 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
499 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
500 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 501 | |
5fdbf976 | 502 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 503 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
504 | } |
505 | ||
116a4752 | 506 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
507 | bool has_error_code, u32 error_code, |
508 | bool reinject) | |
116a4752 JK |
509 | { |
510 | struct vcpu_svm *svm = to_svm(vcpu); | |
511 | ||
e0231715 JR |
512 | /* |
513 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
514 | * handle the exception | |
515 | */ | |
ce7ddec4 JR |
516 | if (!reinject && |
517 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
518 | return; |
519 | ||
2a6b20b8 | 520 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
521 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
522 | ||
523 | /* | |
524 | * For guest debugging where we have to reinject #BP if some | |
525 | * INT3 is guest-owned: | |
526 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
527 | * raises a fault that is not intercepted. Still better than | |
528 | * failing in all cases. | |
529 | */ | |
530 | skip_emulated_instruction(&svm->vcpu); | |
531 | rip = kvm_rip_read(&svm->vcpu); | |
532 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
533 | svm->int3_injected = rip - old_rip; | |
534 | } | |
535 | ||
116a4752 JK |
536 | svm->vmcb->control.event_inj = nr |
537 | | SVM_EVTINJ_VALID | |
538 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
539 | | SVM_EVTINJ_TYPE_EXEPT; | |
540 | svm->vmcb->control.event_inj_err = error_code; | |
541 | } | |
542 | ||
67ec6607 JR |
543 | static void svm_init_erratum_383(void) |
544 | { | |
545 | u32 low, high; | |
546 | int err; | |
547 | u64 val; | |
548 | ||
1be85a6d | 549 | if (!cpu_has_amd_erratum(amd_erratum_383)) |
67ec6607 JR |
550 | return; |
551 | ||
552 | /* Use _safe variants to not break nested virtualization */ | |
553 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
554 | if (err) | |
555 | return; | |
556 | ||
557 | val |= (1ULL << 47); | |
558 | ||
559 | low = lower_32_bits(val); | |
560 | high = upper_32_bits(val); | |
561 | ||
562 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
563 | ||
564 | erratum_383_found = true; | |
565 | } | |
566 | ||
2b036c6b BO |
567 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
568 | { | |
569 | /* | |
570 | * Guests should see errata 400 and 415 as fixed (assuming that | |
571 | * HLT and IO instructions are intercepted). | |
572 | */ | |
573 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
574 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
575 | ||
576 | /* | |
577 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
578 | * all osvw.status bits inside that length, including bit 0 (which is | |
579 | * reserved for erratum 298), are valid. However, if host processor's | |
580 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
581 | * be conservative here and therefore we tell the guest that erratum 298 | |
582 | * is present (because we really don't know). | |
583 | */ | |
584 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
585 | vcpu->arch.osvw.status |= 1; | |
586 | } | |
587 | ||
6aa8b732 AK |
588 | static int has_svm(void) |
589 | { | |
63d1142f | 590 | const char *msg; |
6aa8b732 | 591 | |
63d1142f | 592 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 593 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
594 | return 0; |
595 | } | |
596 | ||
6aa8b732 AK |
597 | return 1; |
598 | } | |
599 | ||
600 | static void svm_hardware_disable(void *garbage) | |
601 | { | |
fbc0db76 JR |
602 | /* Make sure we clean up behind us */ |
603 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
604 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
605 | ||
2c8dceeb | 606 | cpu_svm_disable(); |
6aa8b732 AK |
607 | } |
608 | ||
10474ae8 | 609 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
610 | { |
611 | ||
0fe1e009 | 612 | struct svm_cpu_data *sd; |
6aa8b732 | 613 | uint64_t efer; |
89a27f4d | 614 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
615 | struct desc_struct *gdt; |
616 | int me = raw_smp_processor_id(); | |
617 | ||
10474ae8 AG |
618 | rdmsrl(MSR_EFER, efer); |
619 | if (efer & EFER_SVME) | |
620 | return -EBUSY; | |
621 | ||
6aa8b732 | 622 | if (!has_svm()) { |
e6732a5a ZA |
623 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", |
624 | me); | |
10474ae8 | 625 | return -EINVAL; |
6aa8b732 | 626 | } |
0fe1e009 | 627 | sd = per_cpu(svm_data, me); |
6aa8b732 | 628 | |
0fe1e009 | 629 | if (!sd) { |
e6732a5a | 630 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", |
6aa8b732 | 631 | me); |
10474ae8 | 632 | return -EINVAL; |
6aa8b732 AK |
633 | } |
634 | ||
0fe1e009 TH |
635 | sd->asid_generation = 1; |
636 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
637 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 638 | |
d6ab1ed4 | 639 | native_store_gdt(&gdt_descr); |
89a27f4d | 640 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 641 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 642 | |
9962d032 | 643 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 644 | |
d0316554 | 645 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 646 | |
fbc0db76 JR |
647 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
648 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
649 | __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT; | |
650 | } | |
651 | ||
2b036c6b BO |
652 | |
653 | /* | |
654 | * Get OSVW bits. | |
655 | * | |
656 | * Note that it is possible to have a system with mixed processor | |
657 | * revisions and therefore different OSVW bits. If bits are not the same | |
658 | * on different processors then choose the worst case (i.e. if erratum | |
659 | * is present on one processor and not on another then assume that the | |
660 | * erratum is present everywhere). | |
661 | */ | |
662 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
663 | uint64_t len, status = 0; | |
664 | int err; | |
665 | ||
666 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
667 | if (!err) | |
668 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
669 | &err); | |
670 | ||
671 | if (err) | |
672 | osvw_status = osvw_len = 0; | |
673 | else { | |
674 | if (len < osvw_len) | |
675 | osvw_len = len; | |
676 | osvw_status |= status; | |
677 | osvw_status &= (1ULL << osvw_len) - 1; | |
678 | } | |
679 | } else | |
680 | osvw_status = osvw_len = 0; | |
681 | ||
67ec6607 JR |
682 | svm_init_erratum_383(); |
683 | ||
10474ae8 | 684 | return 0; |
6aa8b732 AK |
685 | } |
686 | ||
0da1db75 JR |
687 | static void svm_cpu_uninit(int cpu) |
688 | { | |
0fe1e009 | 689 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 690 | |
0fe1e009 | 691 | if (!sd) |
0da1db75 JR |
692 | return; |
693 | ||
694 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
695 | __free_page(sd->save_area); |
696 | kfree(sd); | |
0da1db75 JR |
697 | } |
698 | ||
6aa8b732 AK |
699 | static int svm_cpu_init(int cpu) |
700 | { | |
0fe1e009 | 701 | struct svm_cpu_data *sd; |
6aa8b732 AK |
702 | int r; |
703 | ||
0fe1e009 TH |
704 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
705 | if (!sd) | |
6aa8b732 | 706 | return -ENOMEM; |
0fe1e009 TH |
707 | sd->cpu = cpu; |
708 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 709 | r = -ENOMEM; |
0fe1e009 | 710 | if (!sd->save_area) |
6aa8b732 AK |
711 | goto err_1; |
712 | ||
0fe1e009 | 713 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
714 | |
715 | return 0; | |
716 | ||
717 | err_1: | |
0fe1e009 | 718 | kfree(sd); |
6aa8b732 AK |
719 | return r; |
720 | ||
721 | } | |
722 | ||
ac72a9b7 JR |
723 | static bool valid_msr_intercept(u32 index) |
724 | { | |
725 | int i; | |
726 | ||
727 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
728 | if (direct_access_msrs[i].index == index) | |
729 | return true; | |
730 | ||
731 | return false; | |
732 | } | |
733 | ||
bfc733a7 RR |
734 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
735 | int read, int write) | |
6aa8b732 | 736 | { |
455716fa JR |
737 | u8 bit_read, bit_write; |
738 | unsigned long tmp; | |
739 | u32 offset; | |
6aa8b732 | 740 | |
ac72a9b7 JR |
741 | /* |
742 | * If this warning triggers extend the direct_access_msrs list at the | |
743 | * beginning of the file | |
744 | */ | |
745 | WARN_ON(!valid_msr_intercept(msr)); | |
746 | ||
455716fa JR |
747 | offset = svm_msrpm_offset(msr); |
748 | bit_read = 2 * (msr & 0x0f); | |
749 | bit_write = 2 * (msr & 0x0f) + 1; | |
750 | tmp = msrpm[offset]; | |
751 | ||
752 | BUG_ON(offset == MSR_INVALID); | |
753 | ||
754 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
755 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
756 | ||
757 | msrpm[offset] = tmp; | |
6aa8b732 AK |
758 | } |
759 | ||
f65c229c | 760 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
761 | { |
762 | int i; | |
763 | ||
f65c229c JR |
764 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
765 | ||
ac72a9b7 JR |
766 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
767 | if (!direct_access_msrs[i].always) | |
768 | continue; | |
769 | ||
770 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
771 | } | |
f65c229c JR |
772 | } |
773 | ||
323c3d80 JR |
774 | static void add_msr_offset(u32 offset) |
775 | { | |
776 | int i; | |
777 | ||
778 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
779 | ||
780 | /* Offset already in list? */ | |
781 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 782 | return; |
323c3d80 JR |
783 | |
784 | /* Slot used by another offset? */ | |
785 | if (msrpm_offsets[i] != MSR_INVALID) | |
786 | continue; | |
787 | ||
788 | /* Add offset to list */ | |
789 | msrpm_offsets[i] = offset; | |
790 | ||
791 | return; | |
6aa8b732 | 792 | } |
323c3d80 JR |
793 | |
794 | /* | |
795 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
796 | * increase MSRPM_OFFSETS in this case. | |
797 | */ | |
bfc733a7 | 798 | BUG(); |
6aa8b732 AK |
799 | } |
800 | ||
323c3d80 | 801 | static void init_msrpm_offsets(void) |
f65c229c | 802 | { |
323c3d80 | 803 | int i; |
f65c229c | 804 | |
323c3d80 JR |
805 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
806 | ||
807 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
808 | u32 offset; | |
809 | ||
810 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
811 | BUG_ON(offset == MSR_INVALID); | |
812 | ||
813 | add_msr_offset(offset); | |
814 | } | |
f65c229c JR |
815 | } |
816 | ||
24e09cbf JR |
817 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
818 | { | |
819 | u32 *msrpm = svm->msrpm; | |
820 | ||
821 | svm->vmcb->control.lbr_ctl = 1; | |
822 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
823 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
824 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
825 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
826 | } | |
827 | ||
828 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
829 | { | |
830 | u32 *msrpm = svm->msrpm; | |
831 | ||
832 | svm->vmcb->control.lbr_ctl = 0; | |
833 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
834 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
835 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
836 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
837 | } | |
838 | ||
6aa8b732 AK |
839 | static __init int svm_hardware_setup(void) |
840 | { | |
841 | int cpu; | |
842 | struct page *iopm_pages; | |
f65c229c | 843 | void *iopm_va; |
6aa8b732 AK |
844 | int r; |
845 | ||
6aa8b732 AK |
846 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
847 | ||
848 | if (!iopm_pages) | |
849 | return -ENOMEM; | |
c8681339 AL |
850 | |
851 | iopm_va = page_address(iopm_pages); | |
852 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
853 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
854 | ||
323c3d80 JR |
855 | init_msrpm_offsets(); |
856 | ||
50a37eb4 JR |
857 | if (boot_cpu_has(X86_FEATURE_NX)) |
858 | kvm_enable_efer_bits(EFER_NX); | |
859 | ||
1b2fd70c AG |
860 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
861 | kvm_enable_efer_bits(EFER_FFXSR); | |
862 | ||
92a1f12d JR |
863 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
864 | u64 max; | |
865 | ||
866 | kvm_has_tsc_control = true; | |
867 | ||
868 | /* | |
869 | * Make sure the user can only configure tsc_khz values that | |
870 | * fit into a signed integer. | |
871 | * A min value is not calculated needed because it will always | |
872 | * be 1 on all machines and a value of 0 is used to disable | |
873 | * tsc-scaling for the vcpu. | |
874 | */ | |
875 | max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX)); | |
876 | ||
877 | kvm_max_guest_tsc_khz = max; | |
878 | } | |
879 | ||
236de055 AG |
880 | if (nested) { |
881 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 882 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
883 | } |
884 | ||
3230bb47 | 885 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
886 | r = svm_cpu_init(cpu); |
887 | if (r) | |
f65c229c | 888 | goto err; |
6aa8b732 | 889 | } |
33bd6a0b | 890 | |
2a6b20b8 | 891 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
892 | npt_enabled = false; |
893 | ||
6c7dac72 JR |
894 | if (npt_enabled && !npt) { |
895 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
896 | npt_enabled = false; | |
897 | } | |
898 | ||
18552672 | 899 | if (npt_enabled) { |
e3da3acd | 900 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 901 | kvm_enable_tdp(); |
5f4cb662 JR |
902 | } else |
903 | kvm_disable_tdp(); | |
e3da3acd | 904 | |
6aa8b732 AK |
905 | return 0; |
906 | ||
f65c229c | 907 | err: |
6aa8b732 AK |
908 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
909 | iopm_base = 0; | |
910 | return r; | |
911 | } | |
912 | ||
913 | static __exit void svm_hardware_unsetup(void) | |
914 | { | |
0da1db75 JR |
915 | int cpu; |
916 | ||
3230bb47 | 917 | for_each_possible_cpu(cpu) |
0da1db75 JR |
918 | svm_cpu_uninit(cpu); |
919 | ||
6aa8b732 | 920 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 921 | iopm_base = 0; |
6aa8b732 AK |
922 | } |
923 | ||
924 | static void init_seg(struct vmcb_seg *seg) | |
925 | { | |
926 | seg->selector = 0; | |
927 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 928 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
929 | seg->limit = 0xffff; |
930 | seg->base = 0; | |
931 | } | |
932 | ||
933 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
934 | { | |
935 | seg->selector = 0; | |
936 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
937 | seg->limit = 0xffff; | |
938 | seg->base = 0; | |
939 | } | |
940 | ||
fbc0db76 JR |
941 | static u64 __scale_tsc(u64 ratio, u64 tsc) |
942 | { | |
943 | u64 mult, frac, _tsc; | |
944 | ||
945 | mult = ratio >> 32; | |
946 | frac = ratio & ((1ULL << 32) - 1); | |
947 | ||
948 | _tsc = tsc; | |
949 | _tsc *= mult; | |
950 | _tsc += (tsc >> 32) * frac; | |
951 | _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32; | |
952 | ||
953 | return _tsc; | |
954 | } | |
955 | ||
956 | static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
957 | { | |
958 | struct vcpu_svm *svm = to_svm(vcpu); | |
959 | u64 _tsc = tsc; | |
960 | ||
961 | if (svm->tsc_ratio != TSC_RATIO_DEFAULT) | |
962 | _tsc = __scale_tsc(svm->tsc_ratio, tsc); | |
963 | ||
964 | return _tsc; | |
965 | } | |
966 | ||
cc578287 | 967 | static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
4051b188 JR |
968 | { |
969 | struct vcpu_svm *svm = to_svm(vcpu); | |
970 | u64 ratio; | |
971 | u64 khz; | |
972 | ||
cc578287 ZA |
973 | /* Guest TSC same frequency as host TSC? */ |
974 | if (!scale) { | |
975 | svm->tsc_ratio = TSC_RATIO_DEFAULT; | |
4051b188 | 976 | return; |
cc578287 | 977 | } |
4051b188 | 978 | |
cc578287 ZA |
979 | /* TSC scaling supported? */ |
980 | if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { | |
981 | if (user_tsc_khz > tsc_khz) { | |
982 | vcpu->arch.tsc_catchup = 1; | |
983 | vcpu->arch.tsc_always_catchup = 1; | |
984 | } else | |
985 | WARN(1, "user requested TSC rate below hardware speed\n"); | |
4051b188 JR |
986 | return; |
987 | } | |
988 | ||
989 | khz = user_tsc_khz; | |
990 | ||
991 | /* TSC scaling required - calculate ratio */ | |
992 | ratio = khz << 32; | |
993 | do_div(ratio, tsc_khz); | |
994 | ||
995 | if (ratio == 0 || ratio & TSC_RATIO_RSVD) { | |
996 | WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n", | |
997 | user_tsc_khz); | |
998 | return; | |
999 | } | |
4051b188 JR |
1000 | svm->tsc_ratio = ratio; |
1001 | } | |
1002 | ||
f4e1b3c8 ZA |
1003 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1004 | { | |
1005 | struct vcpu_svm *svm = to_svm(vcpu); | |
1006 | u64 g_tsc_offset = 0; | |
1007 | ||
2030753d | 1008 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
1009 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1010 | svm->nested.hsave->control.tsc_offset; | |
1011 | svm->nested.hsave->control.tsc_offset = offset; | |
1012 | } | |
1013 | ||
1014 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1015 | |
1016 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
1017 | } |
1018 | ||
f1e2b260 | 1019 | static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host) |
e48672fa ZA |
1020 | { |
1021 | struct vcpu_svm *svm = to_svm(vcpu); | |
1022 | ||
f1e2b260 MT |
1023 | WARN_ON(adjustment < 0); |
1024 | if (host) | |
1025 | adjustment = svm_scale_tsc(vcpu, adjustment); | |
1026 | ||
e48672fa | 1027 | svm->vmcb->control.tsc_offset += adjustment; |
2030753d | 1028 | if (is_guest_mode(vcpu)) |
e48672fa | 1029 | svm->nested.hsave->control.tsc_offset += adjustment; |
116a0a23 | 1030 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
e48672fa ZA |
1031 | } |
1032 | ||
857e4099 JR |
1033 | static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1034 | { | |
1035 | u64 tsc; | |
1036 | ||
1037 | tsc = svm_scale_tsc(vcpu, native_read_tsc()); | |
1038 | ||
1039 | return target_tsc - tsc; | |
1040 | } | |
1041 | ||
e6101a96 | 1042 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1043 | { |
e6101a96 JR |
1044 | struct vmcb_control_area *control = &svm->vmcb->control; |
1045 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1046 | |
bff78274 | 1047 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 1048 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1049 | |
4ee546b4 RJ |
1050 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1051 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1052 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1053 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1054 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1055 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
1056 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1057 | |
3aed041a JR |
1058 | set_dr_intercept(svm, INTERCEPT_DR0_READ); |
1059 | set_dr_intercept(svm, INTERCEPT_DR1_READ); | |
1060 | set_dr_intercept(svm, INTERCEPT_DR2_READ); | |
1061 | set_dr_intercept(svm, INTERCEPT_DR3_READ); | |
1062 | set_dr_intercept(svm, INTERCEPT_DR4_READ); | |
1063 | set_dr_intercept(svm, INTERCEPT_DR5_READ); | |
1064 | set_dr_intercept(svm, INTERCEPT_DR6_READ); | |
1065 | set_dr_intercept(svm, INTERCEPT_DR7_READ); | |
1066 | ||
1067 | set_dr_intercept(svm, INTERCEPT_DR0_WRITE); | |
1068 | set_dr_intercept(svm, INTERCEPT_DR1_WRITE); | |
1069 | set_dr_intercept(svm, INTERCEPT_DR2_WRITE); | |
1070 | set_dr_intercept(svm, INTERCEPT_DR3_WRITE); | |
1071 | set_dr_intercept(svm, INTERCEPT_DR4_WRITE); | |
1072 | set_dr_intercept(svm, INTERCEPT_DR5_WRITE); | |
1073 | set_dr_intercept(svm, INTERCEPT_DR6_WRITE); | |
1074 | set_dr_intercept(svm, INTERCEPT_DR7_WRITE); | |
6aa8b732 | 1075 | |
18c918c5 JR |
1076 | set_exception_intercept(svm, PF_VECTOR); |
1077 | set_exception_intercept(svm, UD_VECTOR); | |
1078 | set_exception_intercept(svm, MC_VECTOR); | |
6aa8b732 | 1079 | |
8a05a1b8 JR |
1080 | set_intercept(svm, INTERCEPT_INTR); |
1081 | set_intercept(svm, INTERCEPT_NMI); | |
1082 | set_intercept(svm, INTERCEPT_SMI); | |
1083 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1084 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1085 | set_intercept(svm, INTERCEPT_CPUID); |
1086 | set_intercept(svm, INTERCEPT_INVD); | |
1087 | set_intercept(svm, INTERCEPT_HLT); | |
1088 | set_intercept(svm, INTERCEPT_INVLPG); | |
1089 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1090 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1091 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1092 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1093 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1094 | set_intercept(svm, INTERCEPT_VMRUN); | |
1095 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1096 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1097 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1098 | set_intercept(svm, INTERCEPT_STGI); | |
1099 | set_intercept(svm, INTERCEPT_CLGI); | |
1100 | set_intercept(svm, INTERCEPT_SKINIT); | |
1101 | set_intercept(svm, INTERCEPT_WBINVD); | |
1102 | set_intercept(svm, INTERCEPT_MONITOR); | |
1103 | set_intercept(svm, INTERCEPT_MWAIT); | |
81dd35d4 | 1104 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 AK |
1105 | |
1106 | control->iopm_base_pa = iopm_base; | |
f65c229c | 1107 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
1108 | control->int_ctl = V_INTR_MASKING_MASK; |
1109 | ||
1110 | init_seg(&save->es); | |
1111 | init_seg(&save->ss); | |
1112 | init_seg(&save->ds); | |
1113 | init_seg(&save->fs); | |
1114 | init_seg(&save->gs); | |
1115 | ||
1116 | save->cs.selector = 0xf000; | |
1117 | /* Executable/Readable Code Segment */ | |
1118 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1119 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1120 | save->cs.limit = 0xffff; | |
d92899a0 AK |
1121 | /* |
1122 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
1123 | * be consistent with it. | |
1124 | * | |
1125 | * Replace when we have real mode working for vmx. | |
1126 | */ | |
1127 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
1128 | |
1129 | save->gdtr.limit = 0xffff; | |
1130 | save->idtr.limit = 0xffff; | |
1131 | ||
1132 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1133 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1134 | ||
eaa48512 | 1135 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1136 | save->dr6 = 0xffff0ff0; |
6aa8b732 | 1137 | save->dr7 = 0x400; |
f6e78475 | 1138 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1139 | save->rip = 0x0000fff0; |
5fdbf976 | 1140 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1141 | |
e0231715 JR |
1142 | /* |
1143 | * This is the guest-visible cr0 value. | |
18fa000a | 1144 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 1145 | */ |
678041ad MT |
1146 | svm->vcpu.arch.cr0 = 0; |
1147 | (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); | |
18fa000a | 1148 | |
66aee91a | 1149 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1150 | /* rdx = ?? */ |
709ddebf JR |
1151 | |
1152 | if (npt_enabled) { | |
1153 | /* Setup VMCB for Nested Paging */ | |
1154 | control->nested_ctl = 1; | |
8a05a1b8 | 1155 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1156 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1157 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1158 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
709ddebf | 1159 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
1160 | save->cr3 = 0; |
1161 | save->cr4 = 0; | |
1162 | } | |
f40f6a45 | 1163 | svm->asid_generation = 0; |
1371d904 | 1164 | |
e6aa9abd | 1165 | svm->nested.vmcb = 0; |
2af9194d JR |
1166 | svm->vcpu.arch.hflags = 0; |
1167 | ||
2a6b20b8 | 1168 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1169 | control->pause_filter_count = 3000; |
8a05a1b8 | 1170 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1171 | } |
1172 | ||
8d28fec4 RJ |
1173 | mark_all_dirty(svm->vmcb); |
1174 | ||
2af9194d | 1175 | enable_gif(svm); |
6aa8b732 AK |
1176 | } |
1177 | ||
e00c8cf2 | 1178 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
1179 | { |
1180 | struct vcpu_svm *svm = to_svm(vcpu); | |
1181 | ||
e6101a96 | 1182 | init_vmcb(svm); |
70433389 | 1183 | |
c5af89b6 | 1184 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 1185 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
1186 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
1187 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 1188 | } |
5fdbf976 MT |
1189 | vcpu->arch.regs_avail = ~0; |
1190 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
1191 | |
1192 | return 0; | |
04d2cc77 AK |
1193 | } |
1194 | ||
fb3f0f51 | 1195 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1196 | { |
a2fa3e9f | 1197 | struct vcpu_svm *svm; |
6aa8b732 | 1198 | struct page *page; |
f65c229c | 1199 | struct page *msrpm_pages; |
b286d5d8 | 1200 | struct page *hsave_page; |
3d6368ef | 1201 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1202 | int err; |
6aa8b732 | 1203 | |
c16f862d | 1204 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1205 | if (!svm) { |
1206 | err = -ENOMEM; | |
1207 | goto out; | |
1208 | } | |
1209 | ||
fbc0db76 JR |
1210 | svm->tsc_ratio = TSC_RATIO_DEFAULT; |
1211 | ||
fb3f0f51 RR |
1212 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); |
1213 | if (err) | |
1214 | goto free_svm; | |
1215 | ||
b7af4043 | 1216 | err = -ENOMEM; |
6aa8b732 | 1217 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1218 | if (!page) |
fb3f0f51 | 1219 | goto uninit; |
6aa8b732 | 1220 | |
f65c229c JR |
1221 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1222 | if (!msrpm_pages) | |
b7af4043 | 1223 | goto free_page1; |
3d6368ef AG |
1224 | |
1225 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1226 | if (!nested_msrpm_pages) | |
b7af4043 | 1227 | goto free_page2; |
f65c229c | 1228 | |
b286d5d8 AG |
1229 | hsave_page = alloc_page(GFP_KERNEL); |
1230 | if (!hsave_page) | |
b7af4043 TY |
1231 | goto free_page3; |
1232 | ||
e6aa9abd | 1233 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1234 | |
b7af4043 TY |
1235 | svm->msrpm = page_address(msrpm_pages); |
1236 | svm_vcpu_init_msrpm(svm->msrpm); | |
1237 | ||
e6aa9abd | 1238 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1239 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1240 | |
a2fa3e9f GH |
1241 | svm->vmcb = page_address(page); |
1242 | clear_page(svm->vmcb); | |
1243 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1244 | svm->asid_generation = 0; | |
e6101a96 | 1245 | init_vmcb(svm); |
99e3e30a | 1246 | kvm_write_tsc(&svm->vcpu, 0); |
a2fa3e9f | 1247 | |
10ab25cd JK |
1248 | err = fx_init(&svm->vcpu); |
1249 | if (err) | |
1250 | goto free_page4; | |
1251 | ||
ad312c7c | 1252 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 1253 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 1254 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 1255 | |
2b036c6b BO |
1256 | svm_init_osvw(&svm->vcpu); |
1257 | ||
fb3f0f51 | 1258 | return &svm->vcpu; |
36241b8c | 1259 | |
10ab25cd JK |
1260 | free_page4: |
1261 | __free_page(hsave_page); | |
b7af4043 TY |
1262 | free_page3: |
1263 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1264 | free_page2: | |
1265 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1266 | free_page1: | |
1267 | __free_page(page); | |
fb3f0f51 RR |
1268 | uninit: |
1269 | kvm_vcpu_uninit(&svm->vcpu); | |
1270 | free_svm: | |
a4770347 | 1271 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1272 | out: |
1273 | return ERR_PTR(err); | |
6aa8b732 AK |
1274 | } |
1275 | ||
1276 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1277 | { | |
a2fa3e9f GH |
1278 | struct vcpu_svm *svm = to_svm(vcpu); |
1279 | ||
fb3f0f51 | 1280 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1281 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1282 | __free_page(virt_to_page(svm->nested.hsave)); |
1283 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1284 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1285 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1286 | } |
1287 | ||
15ad7146 | 1288 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1289 | { |
a2fa3e9f | 1290 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1291 | int i; |
0cc5064d | 1292 | |
0cc5064d | 1293 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1294 | svm->asid_generation = 0; |
8d28fec4 | 1295 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1296 | } |
94dfbdb3 | 1297 | |
82ca2d10 AK |
1298 | #ifdef CONFIG_X86_64 |
1299 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1300 | #endif | |
dacccfdd AK |
1301 | savesegment(fs, svm->host.fs); |
1302 | savesegment(gs, svm->host.gs); | |
1303 | svm->host.ldt = kvm_read_ldt(); | |
1304 | ||
94dfbdb3 | 1305 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1306 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 JR |
1307 | |
1308 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR) && | |
1309 | svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) { | |
1310 | __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio; | |
1311 | wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio); | |
1312 | } | |
6aa8b732 AK |
1313 | } |
1314 | ||
1315 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1316 | { | |
a2fa3e9f | 1317 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1318 | int i; |
1319 | ||
e1beb1d3 | 1320 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1321 | kvm_load_ldt(svm->host.ldt); |
1322 | #ifdef CONFIG_X86_64 | |
1323 | loadsegment(fs, svm->host.fs); | |
dacccfdd | 1324 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); |
893a5ab6 | 1325 | load_gs_index(svm->host.gs); |
dacccfdd | 1326 | #else |
831ca609 | 1327 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1328 | loadsegment(gs, svm->host.gs); |
831ca609 | 1329 | #endif |
dacccfdd | 1330 | #endif |
94dfbdb3 | 1331 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1332 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1333 | } |
1334 | ||
6aa8b732 AK |
1335 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1336 | { | |
a2fa3e9f | 1337 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1338 | } |
1339 | ||
1340 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1341 | { | |
a2fa3e9f | 1342 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1343 | } |
1344 | ||
6de4f3ad AK |
1345 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1346 | { | |
1347 | switch (reg) { | |
1348 | case VCPU_EXREG_PDPTR: | |
1349 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1350 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1351 | break; |
1352 | default: | |
1353 | BUG(); | |
1354 | } | |
1355 | } | |
1356 | ||
f0b85051 AG |
1357 | static void svm_set_vintr(struct vcpu_svm *svm) |
1358 | { | |
8a05a1b8 | 1359 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1360 | } |
1361 | ||
1362 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1363 | { | |
8a05a1b8 | 1364 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1365 | } |
1366 | ||
6aa8b732 AK |
1367 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1368 | { | |
a2fa3e9f | 1369 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1370 | |
1371 | switch (seg) { | |
1372 | case VCPU_SREG_CS: return &save->cs; | |
1373 | case VCPU_SREG_DS: return &save->ds; | |
1374 | case VCPU_SREG_ES: return &save->es; | |
1375 | case VCPU_SREG_FS: return &save->fs; | |
1376 | case VCPU_SREG_GS: return &save->gs; | |
1377 | case VCPU_SREG_SS: return &save->ss; | |
1378 | case VCPU_SREG_TR: return &save->tr; | |
1379 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1380 | } | |
1381 | BUG(); | |
8b6d44c7 | 1382 | return NULL; |
6aa8b732 AK |
1383 | } |
1384 | ||
1385 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1386 | { | |
1387 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1388 | ||
1389 | return s->base; | |
1390 | } | |
1391 | ||
1392 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1393 | struct kvm_segment *var, int seg) | |
1394 | { | |
1395 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1396 | ||
1397 | var->base = s->base; | |
1398 | var->limit = s->limit; | |
1399 | var->selector = s->selector; | |
1400 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1401 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1402 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1403 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1404 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1405 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1406 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1407 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1408 | |
e0231715 JR |
1409 | /* |
1410 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1411 | * for cross vendor migration purposes by "not present" |
1412 | */ | |
1413 | var->unusable = !var->present || (var->type == 0); | |
1414 | ||
1fbdc7a5 AP |
1415 | switch (seg) { |
1416 | case VCPU_SREG_CS: | |
1417 | /* | |
1418 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1419 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1420 | * Intel's VMENTRY has a check on the 'G' bit. | |
1421 | */ | |
25022acc | 1422 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1423 | break; |
1424 | case VCPU_SREG_TR: | |
1425 | /* | |
1426 | * Work around a bug where the busy flag in the tr selector | |
1427 | * isn't exposed | |
1428 | */ | |
c0d09828 | 1429 | var->type |= 0x2; |
1fbdc7a5 AP |
1430 | break; |
1431 | case VCPU_SREG_DS: | |
1432 | case VCPU_SREG_ES: | |
1433 | case VCPU_SREG_FS: | |
1434 | case VCPU_SREG_GS: | |
1435 | /* | |
1436 | * The accessed bit must always be set in the segment | |
1437 | * descriptor cache, although it can be cleared in the | |
1438 | * descriptor, the cached bit always remains at 1. Since | |
1439 | * Intel has a check on this, set it here to support | |
1440 | * cross-vendor migration. | |
1441 | */ | |
1442 | if (!var->unusable) | |
1443 | var->type |= 0x1; | |
1444 | break; | |
b586eb02 | 1445 | case VCPU_SREG_SS: |
e0231715 JR |
1446 | /* |
1447 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1448 | * descriptor is left as 1, although the whole segment has |
1449 | * been made unusable. Clear it here to pass an Intel VMX | |
1450 | * entry check when cross vendor migrating. | |
1451 | */ | |
1452 | if (var->unusable) | |
1453 | var->db = 0; | |
1454 | break; | |
1fbdc7a5 | 1455 | } |
6aa8b732 AK |
1456 | } |
1457 | ||
2e4d2653 IE |
1458 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1459 | { | |
1460 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1461 | ||
1462 | return save->cpl; | |
1463 | } | |
1464 | ||
89a27f4d | 1465 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1466 | { |
a2fa3e9f GH |
1467 | struct vcpu_svm *svm = to_svm(vcpu); |
1468 | ||
89a27f4d GN |
1469 | dt->size = svm->vmcb->save.idtr.limit; |
1470 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1471 | } |
1472 | ||
89a27f4d | 1473 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1474 | { |
a2fa3e9f GH |
1475 | struct vcpu_svm *svm = to_svm(vcpu); |
1476 | ||
89a27f4d GN |
1477 | svm->vmcb->save.idtr.limit = dt->size; |
1478 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1479 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1480 | } |
1481 | ||
89a27f4d | 1482 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1483 | { |
a2fa3e9f GH |
1484 | struct vcpu_svm *svm = to_svm(vcpu); |
1485 | ||
89a27f4d GN |
1486 | dt->size = svm->vmcb->save.gdtr.limit; |
1487 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1488 | } |
1489 | ||
89a27f4d | 1490 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1491 | { |
a2fa3e9f GH |
1492 | struct vcpu_svm *svm = to_svm(vcpu); |
1493 | ||
89a27f4d GN |
1494 | svm->vmcb->save.gdtr.limit = dt->size; |
1495 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1496 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1497 | } |
1498 | ||
e8467fda AK |
1499 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1500 | { | |
1501 | } | |
1502 | ||
aff48baa AK |
1503 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1504 | { | |
1505 | } | |
1506 | ||
25c4c276 | 1507 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1508 | { |
1509 | } | |
1510 | ||
d225157b AK |
1511 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1512 | { | |
1513 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1514 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1515 | ||
1516 | if (!svm->vcpu.fpu_active) | |
1517 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1518 | else | |
1519 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1520 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1521 | ||
dcca1a65 | 1522 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b AK |
1523 | |
1524 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1525 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1526 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1527 | } else { |
4ee546b4 RJ |
1528 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1529 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1530 | } |
1531 | } | |
1532 | ||
6aa8b732 AK |
1533 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1534 | { | |
a2fa3e9f GH |
1535 | struct vcpu_svm *svm = to_svm(vcpu); |
1536 | ||
05b3e0c2 | 1537 | #ifdef CONFIG_X86_64 |
f6801dff | 1538 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1539 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1540 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1541 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1542 | } |
1543 | ||
d77c26fc | 1544 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1545 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1546 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1547 | } |
1548 | } | |
1549 | #endif | |
ad312c7c | 1550 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1551 | |
1552 | if (!npt_enabled) | |
1553 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1554 | |
1555 | if (!vcpu->fpu_active) | |
334df50a | 1556 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1557 | /* |
1558 | * re-enable caching here because the QEMU bios | |
1559 | * does not do it - this results in some delay at | |
1560 | * reboot | |
1561 | */ | |
1562 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1563 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1564 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1565 | update_cr0_intercept(svm); |
6aa8b732 AK |
1566 | } |
1567 | ||
5e1746d6 | 1568 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 1569 | { |
6394b649 | 1570 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1571 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1572 | ||
5e1746d6 NHE |
1573 | if (cr4 & X86_CR4_VMXE) |
1574 | return 1; | |
1575 | ||
e5eab0ce | 1576 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 1577 | svm_flush_tlb(vcpu); |
6394b649 | 1578 | |
ec077263 JR |
1579 | vcpu->arch.cr4 = cr4; |
1580 | if (!npt_enabled) | |
1581 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1582 | cr4 |= host_cr4_mce; |
ec077263 | 1583 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1584 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 1585 | return 0; |
6aa8b732 AK |
1586 | } |
1587 | ||
1588 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1589 | struct kvm_segment *var, int seg) | |
1590 | { | |
a2fa3e9f | 1591 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1592 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1593 | ||
1594 | s->base = var->base; | |
1595 | s->limit = var->limit; | |
1596 | s->selector = var->selector; | |
1597 | if (var->unusable) | |
1598 | s->attrib = 0; | |
1599 | else { | |
1600 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1601 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1602 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1603 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1604 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1605 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1606 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1607 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1608 | } | |
1609 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1610 | svm->vmcb->save.cpl |
1611 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1612 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1613 | ||
060d0c9a | 1614 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
1615 | } |
1616 | ||
44c11430 | 1617 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1618 | { |
d0bfb940 JK |
1619 | struct vcpu_svm *svm = to_svm(vcpu); |
1620 | ||
18c918c5 JR |
1621 | clr_exception_intercept(svm, DB_VECTOR); |
1622 | clr_exception_intercept(svm, BP_VECTOR); | |
44c11430 | 1623 | |
6be7d306 | 1624 | if (svm->nmi_singlestep) |
18c918c5 | 1625 | set_exception_intercept(svm, DB_VECTOR); |
44c11430 | 1626 | |
d0bfb940 JK |
1627 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1628 | if (vcpu->guest_debug & | |
1629 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
18c918c5 | 1630 | set_exception_intercept(svm, DB_VECTOR); |
d0bfb940 | 1631 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1632 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1633 | } else |
1634 | vcpu->guest_debug = 0; | |
44c11430 GN |
1635 | } |
1636 | ||
355be0b9 | 1637 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
44c11430 | 1638 | { |
44c11430 GN |
1639 | struct vcpu_svm *svm = to_svm(vcpu); |
1640 | ||
ae675ef0 JK |
1641 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1642 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1643 | else | |
1644 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1645 | ||
72214b96 JR |
1646 | mark_dirty(svm->vmcb, VMCB_DR); |
1647 | ||
355be0b9 | 1648 | update_db_intercept(vcpu); |
6aa8b732 AK |
1649 | } |
1650 | ||
0fe1e009 | 1651 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1652 | { |
0fe1e009 TH |
1653 | if (sd->next_asid > sd->max_asid) { |
1654 | ++sd->asid_generation; | |
1655 | sd->next_asid = 1; | |
a2fa3e9f | 1656 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1657 | } |
1658 | ||
0fe1e009 TH |
1659 | svm->asid_generation = sd->asid_generation; |
1660 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
1661 | |
1662 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
1663 | } |
1664 | ||
020df079 | 1665 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1666 | { |
42dbaa5a | 1667 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1668 | |
020df079 | 1669 | svm->vmcb->save.dr7 = value; |
72214b96 | 1670 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
1671 | } |
1672 | ||
851ba692 | 1673 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1674 | { |
631bc487 | 1675 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1676 | u32 error_code; |
631bc487 | 1677 | int r = 1; |
6aa8b732 | 1678 | |
631bc487 GN |
1679 | switch (svm->apf_reason) { |
1680 | default: | |
1681 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1682 | |
631bc487 GN |
1683 | trace_kvm_page_fault(fault_address, error_code); |
1684 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1685 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
1686 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
1687 | svm->vmcb->control.insn_bytes, | |
1688 | svm->vmcb->control.insn_len); | |
631bc487 GN |
1689 | break; |
1690 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1691 | svm->apf_reason = 0; | |
1692 | local_irq_disable(); | |
1693 | kvm_async_pf_task_wait(fault_address); | |
1694 | local_irq_enable(); | |
1695 | break; | |
1696 | case KVM_PV_REASON_PAGE_READY: | |
1697 | svm->apf_reason = 0; | |
1698 | local_irq_disable(); | |
1699 | kvm_async_pf_task_wake(fault_address); | |
1700 | local_irq_enable(); | |
1701 | break; | |
1702 | } | |
1703 | return r; | |
6aa8b732 AK |
1704 | } |
1705 | ||
851ba692 | 1706 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1707 | { |
851ba692 AK |
1708 | struct kvm_run *kvm_run = svm->vcpu.run; |
1709 | ||
d0bfb940 | 1710 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1711 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1712 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1713 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1714 | return 1; | |
1715 | } | |
44c11430 | 1716 | |
6be7d306 JK |
1717 | if (svm->nmi_singlestep) { |
1718 | svm->nmi_singlestep = false; | |
44c11430 GN |
1719 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1720 | svm->vmcb->save.rflags &= | |
1721 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1722 | update_db_intercept(&svm->vcpu); | |
1723 | } | |
1724 | ||
1725 | if (svm->vcpu.guest_debug & | |
e0231715 | 1726 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1727 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1728 | kvm_run->debug.arch.pc = | |
1729 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1730 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1731 | return 0; | |
1732 | } | |
1733 | ||
1734 | return 1; | |
d0bfb940 JK |
1735 | } |
1736 | ||
851ba692 | 1737 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1738 | { |
851ba692 AK |
1739 | struct kvm_run *kvm_run = svm->vcpu.run; |
1740 | ||
d0bfb940 JK |
1741 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1742 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1743 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1744 | return 0; | |
1745 | } | |
1746 | ||
851ba692 | 1747 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1748 | { |
1749 | int er; | |
1750 | ||
51d8b661 | 1751 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1752 | if (er != EMULATE_DONE) |
7ee5d940 | 1753 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1754 | return 1; |
1755 | } | |
1756 | ||
6b52d186 | 1757 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1758 | { |
6b52d186 | 1759 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1760 | |
18c918c5 | 1761 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1762 | |
e756fc62 | 1763 | svm->vcpu.fpu_active = 1; |
d225157b | 1764 | update_cr0_intercept(svm); |
6b52d186 | 1765 | } |
a2fa3e9f | 1766 | |
6b52d186 AK |
1767 | static int nm_interception(struct vcpu_svm *svm) |
1768 | { | |
1769 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1770 | return 1; |
7807fa6c AL |
1771 | } |
1772 | ||
67ec6607 JR |
1773 | static bool is_erratum_383(void) |
1774 | { | |
1775 | int err, i; | |
1776 | u64 value; | |
1777 | ||
1778 | if (!erratum_383_found) | |
1779 | return false; | |
1780 | ||
1781 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1782 | if (err) | |
1783 | return false; | |
1784 | ||
1785 | /* Bit 62 may or may not be set for this mce */ | |
1786 | value &= ~(1ULL << 62); | |
1787 | ||
1788 | if (value != 0xb600000000010015ULL) | |
1789 | return false; | |
1790 | ||
1791 | /* Clear MCi_STATUS registers */ | |
1792 | for (i = 0; i < 6; ++i) | |
1793 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1794 | ||
1795 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1796 | if (!err) { | |
1797 | u32 low, high; | |
1798 | ||
1799 | value &= ~(1ULL << 2); | |
1800 | low = lower_32_bits(value); | |
1801 | high = upper_32_bits(value); | |
1802 | ||
1803 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1804 | } | |
1805 | ||
1806 | /* Flush tlb to evict multi-match entries */ | |
1807 | __flush_tlb_all(); | |
1808 | ||
1809 | return true; | |
1810 | } | |
1811 | ||
fe5913e4 | 1812 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1813 | { |
67ec6607 JR |
1814 | if (is_erratum_383()) { |
1815 | /* | |
1816 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1817 | * guest. | |
1818 | */ | |
1819 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1820 | ||
a8eeb04a | 1821 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1822 | |
1823 | return; | |
1824 | } | |
1825 | ||
53371b50 JR |
1826 | /* |
1827 | * On an #MC intercept the MCE handler is not called automatically in | |
1828 | * the host. So do it by hand here. | |
1829 | */ | |
1830 | asm volatile ( | |
1831 | "int $0x12\n"); | |
1832 | /* not sure if we ever come back to this point */ | |
1833 | ||
fe5913e4 JR |
1834 | return; |
1835 | } | |
1836 | ||
1837 | static int mc_interception(struct vcpu_svm *svm) | |
1838 | { | |
53371b50 JR |
1839 | return 1; |
1840 | } | |
1841 | ||
851ba692 | 1842 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1843 | { |
851ba692 AK |
1844 | struct kvm_run *kvm_run = svm->vcpu.run; |
1845 | ||
46fe4ddd JR |
1846 | /* |
1847 | * VMCB is undefined after a SHUTDOWN intercept | |
1848 | * so reinitialize it. | |
1849 | */ | |
a2fa3e9f | 1850 | clear_page(svm->vmcb); |
e6101a96 | 1851 | init_vmcb(svm); |
46fe4ddd JR |
1852 | |
1853 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1854 | return 0; | |
1855 | } | |
1856 | ||
851ba692 | 1857 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1858 | { |
cf8f70bf | 1859 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1860 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1861 | int size, in, string; |
039576c0 | 1862 | unsigned port; |
6aa8b732 | 1863 | |
e756fc62 | 1864 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1865 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1866 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1867 | if (string || in) |
51d8b661 | 1868 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 1869 | |
039576c0 AK |
1870 | port = io_info >> 16; |
1871 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1872 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1873 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1874 | |
1875 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1876 | } |
1877 | ||
851ba692 | 1878 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1879 | { |
1880 | return 1; | |
1881 | } | |
1882 | ||
851ba692 | 1883 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1884 | { |
1885 | ++svm->vcpu.stat.irq_exits; | |
1886 | return 1; | |
1887 | } | |
1888 | ||
851ba692 | 1889 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1890 | { |
1891 | return 1; | |
1892 | } | |
1893 | ||
851ba692 | 1894 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1895 | { |
5fdbf976 | 1896 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1897 | skip_emulated_instruction(&svm->vcpu); |
1898 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1899 | } |
1900 | ||
851ba692 | 1901 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1902 | { |
5fdbf976 | 1903 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1904 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1905 | kvm_emulate_hypercall(&svm->vcpu); |
1906 | return 1; | |
02e235bc AK |
1907 | } |
1908 | ||
5bd2edc3 JR |
1909 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1910 | { | |
1911 | struct vcpu_svm *svm = to_svm(vcpu); | |
1912 | ||
1913 | return svm->nested.nested_cr3; | |
1914 | } | |
1915 | ||
e4e517b4 AK |
1916 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
1917 | { | |
1918 | struct vcpu_svm *svm = to_svm(vcpu); | |
1919 | u64 cr3 = svm->nested.nested_cr3; | |
1920 | u64 pdpte; | |
1921 | int ret; | |
1922 | ||
1923 | ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte, | |
1924 | offset_in_page(cr3) + index * 8, 8); | |
1925 | if (ret) | |
1926 | return 0; | |
1927 | return pdpte; | |
1928 | } | |
1929 | ||
5bd2edc3 JR |
1930 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
1931 | unsigned long root) | |
1932 | { | |
1933 | struct vcpu_svm *svm = to_svm(vcpu); | |
1934 | ||
1935 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 1936 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 1937 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
1938 | } |
1939 | ||
6389ee94 AK |
1940 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
1941 | struct x86_exception *fault) | |
5bd2edc3 JR |
1942 | { |
1943 | struct vcpu_svm *svm = to_svm(vcpu); | |
1944 | ||
1945 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1946 | svm->vmcb->control.exit_code_hi = 0; | |
6389ee94 AK |
1947 | svm->vmcb->control.exit_info_1 = fault->error_code; |
1948 | svm->vmcb->control.exit_info_2 = fault->address; | |
5bd2edc3 JR |
1949 | |
1950 | nested_svm_vmexit(svm); | |
1951 | } | |
1952 | ||
4b16184c JR |
1953 | static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
1954 | { | |
1955 | int r; | |
1956 | ||
1957 | r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); | |
1958 | ||
1959 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; | |
1960 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 1961 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c JR |
1962 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
1963 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
1964 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
1965 | ||
1966 | return r; | |
1967 | } | |
1968 | ||
1969 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1970 | { | |
1971 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1972 | } | |
1973 | ||
c0725420 AG |
1974 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1975 | { | |
f6801dff | 1976 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1977 | || !is_paging(&svm->vcpu)) { |
1978 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1979 | return 1; | |
1980 | } | |
1981 | ||
1982 | if (svm->vmcb->save.cpl) { | |
1983 | kvm_inject_gp(&svm->vcpu, 0); | |
1984 | return 1; | |
1985 | } | |
1986 | ||
1987 | return 0; | |
1988 | } | |
1989 | ||
cf74a78b AG |
1990 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1991 | bool has_error_code, u32 error_code) | |
1992 | { | |
b8e88bc8 JR |
1993 | int vmexit; |
1994 | ||
2030753d | 1995 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 1996 | return 0; |
cf74a78b | 1997 | |
0295ad7d JR |
1998 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1999 | svm->vmcb->control.exit_code_hi = 0; | |
2000 | svm->vmcb->control.exit_info_1 = error_code; | |
2001 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
2002 | ||
b8e88bc8 JR |
2003 | vmexit = nested_svm_intercept(svm); |
2004 | if (vmexit == NESTED_EXIT_DONE) | |
2005 | svm->nested.exit_required = true; | |
2006 | ||
2007 | return vmexit; | |
cf74a78b AG |
2008 | } |
2009 | ||
8fe54654 JR |
2010 | /* This function returns true if it is save to enable the irq window */ |
2011 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 2012 | { |
2030753d | 2013 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 2014 | return true; |
cf74a78b | 2015 | |
26666957 | 2016 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 2017 | return true; |
cf74a78b | 2018 | |
26666957 | 2019 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 2020 | return false; |
cf74a78b | 2021 | |
a0a07cd2 GN |
2022 | /* |
2023 | * if vmexit was already requested (by intercepted exception | |
2024 | * for instance) do not overwrite it with "external interrupt" | |
2025 | * vmexit. | |
2026 | */ | |
2027 | if (svm->nested.exit_required) | |
2028 | return false; | |
2029 | ||
197717d5 JR |
2030 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
2031 | svm->vmcb->control.exit_info_1 = 0; | |
2032 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 2033 | |
cd3ff653 JR |
2034 | if (svm->nested.intercept & 1ULL) { |
2035 | /* | |
2036 | * The #vmexit can't be emulated here directly because this | |
2037 | * code path runs with irqs and preemtion disabled. A | |
2038 | * #vmexit emulation might sleep. Only signal request for | |
2039 | * the #vmexit here. | |
2040 | */ | |
2041 | svm->nested.exit_required = true; | |
236649de | 2042 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2043 | return false; |
cf74a78b AG |
2044 | } |
2045 | ||
8fe54654 | 2046 | return true; |
cf74a78b AG |
2047 | } |
2048 | ||
887f500c JR |
2049 | /* This function returns true if it is save to enable the nmi window */ |
2050 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2051 | { | |
2030753d | 2052 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2053 | return true; |
2054 | ||
2055 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2056 | return true; | |
2057 | ||
2058 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2059 | svm->nested.exit_required = true; | |
2060 | ||
2061 | return false; | |
cf74a78b AG |
2062 | } |
2063 | ||
7597f129 | 2064 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2065 | { |
2066 | struct page *page; | |
2067 | ||
6c3bd3d7 JR |
2068 | might_sleep(); |
2069 | ||
34f80cfa | 2070 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2071 | if (is_error_page(page)) |
2072 | goto error; | |
2073 | ||
7597f129 JR |
2074 | *_page = page; |
2075 | ||
2076 | return kmap(page); | |
34f80cfa JR |
2077 | |
2078 | error: | |
2079 | kvm_release_page_clean(page); | |
2080 | kvm_inject_gp(&svm->vcpu, 0); | |
2081 | ||
2082 | return NULL; | |
2083 | } | |
2084 | ||
7597f129 | 2085 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2086 | { |
7597f129 | 2087 | kunmap(page); |
34f80cfa JR |
2088 | kvm_release_page_dirty(page); |
2089 | } | |
34f80cfa | 2090 | |
ce2ac085 JR |
2091 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2092 | { | |
2093 | unsigned port; | |
2094 | u8 val, bit; | |
2095 | u64 gpa; | |
34f80cfa | 2096 | |
ce2ac085 JR |
2097 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2098 | return NESTED_EXIT_HOST; | |
34f80cfa | 2099 | |
ce2ac085 JR |
2100 | port = svm->vmcb->control.exit_info_1 >> 16; |
2101 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
2102 | bit = port % 8; | |
2103 | val = 0; | |
2104 | ||
2105 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
2106 | val &= (1 << bit); | |
2107 | ||
2108 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
2109 | } |
2110 | ||
d2477826 | 2111 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2112 | { |
0d6b3537 JR |
2113 | u32 offset, msr, value; |
2114 | int write, mask; | |
4c2161ae | 2115 | |
3d62d9aa | 2116 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2117 | return NESTED_EXIT_HOST; |
3d62d9aa | 2118 | |
0d6b3537 JR |
2119 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2120 | offset = svm_msrpm_offset(msr); | |
2121 | write = svm->vmcb->control.exit_info_1 & 1; | |
2122 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2123 | |
0d6b3537 JR |
2124 | if (offset == MSR_INVALID) |
2125 | return NESTED_EXIT_DONE; | |
4c2161ae | 2126 | |
0d6b3537 JR |
2127 | /* Offset is in 32 bit units but need in 8 bit units */ |
2128 | offset *= 4; | |
4c2161ae | 2129 | |
0d6b3537 JR |
2130 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
2131 | return NESTED_EXIT_DONE; | |
3d62d9aa | 2132 | |
0d6b3537 | 2133 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2134 | } |
2135 | ||
410e4d57 | 2136 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2137 | { |
cf74a78b | 2138 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2139 | |
410e4d57 JR |
2140 | switch (exit_code) { |
2141 | case SVM_EXIT_INTR: | |
2142 | case SVM_EXIT_NMI: | |
ff47a49b | 2143 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2144 | return NESTED_EXIT_HOST; |
410e4d57 | 2145 | case SVM_EXIT_NPF: |
e0231715 | 2146 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2147 | if (npt_enabled) |
2148 | return NESTED_EXIT_HOST; | |
2149 | break; | |
410e4d57 | 2150 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
2151 | /* When we're shadowing, trap PFs, but not async PF */ |
2152 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
2153 | return NESTED_EXIT_HOST; |
2154 | break; | |
66a562f7 JR |
2155 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
2156 | nm_interception(svm); | |
2157 | break; | |
410e4d57 JR |
2158 | default: |
2159 | break; | |
cf74a78b AG |
2160 | } |
2161 | ||
410e4d57 JR |
2162 | return NESTED_EXIT_CONTINUE; |
2163 | } | |
2164 | ||
2165 | /* | |
2166 | * If this function returns true, this #vmexit was already handled | |
2167 | */ | |
b8e88bc8 | 2168 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2169 | { |
2170 | u32 exit_code = svm->vmcb->control.exit_code; | |
2171 | int vmexit = NESTED_EXIT_HOST; | |
2172 | ||
cf74a78b | 2173 | switch (exit_code) { |
9c4e40b9 | 2174 | case SVM_EXIT_MSR: |
3d62d9aa | 2175 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2176 | break; |
ce2ac085 JR |
2177 | case SVM_EXIT_IOIO: |
2178 | vmexit = nested_svm_intercept_ioio(svm); | |
2179 | break; | |
4ee546b4 RJ |
2180 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2181 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2182 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2183 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2184 | break; |
2185 | } | |
3aed041a JR |
2186 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2187 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2188 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2189 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2190 | break; |
2191 | } | |
2192 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2193 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 2194 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 2195 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
2196 | /* async page fault always cause vmexit */ |
2197 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
2198 | svm->apf_reason != 0) | |
2199 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2200 | break; |
2201 | } | |
228070b1 JR |
2202 | case SVM_EXIT_ERR: { |
2203 | vmexit = NESTED_EXIT_DONE; | |
2204 | break; | |
2205 | } | |
cf74a78b AG |
2206 | default: { |
2207 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2208 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2209 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2210 | } |
2211 | } | |
2212 | ||
b8e88bc8 JR |
2213 | return vmexit; |
2214 | } | |
2215 | ||
2216 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2217 | { | |
2218 | int vmexit; | |
2219 | ||
2220 | vmexit = nested_svm_intercept(svm); | |
2221 | ||
2222 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2223 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2224 | |
2225 | return vmexit; | |
cf74a78b AG |
2226 | } |
2227 | ||
0460a979 JR |
2228 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2229 | { | |
2230 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2231 | struct vmcb_control_area *from = &from_vmcb->control; | |
2232 | ||
4ee546b4 | 2233 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2234 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2235 | dst->intercept_exceptions = from->intercept_exceptions; |
2236 | dst->intercept = from->intercept; | |
2237 | dst->iopm_base_pa = from->iopm_base_pa; | |
2238 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2239 | dst->tsc_offset = from->tsc_offset; | |
2240 | dst->asid = from->asid; | |
2241 | dst->tlb_ctl = from->tlb_ctl; | |
2242 | dst->int_ctl = from->int_ctl; | |
2243 | dst->int_vector = from->int_vector; | |
2244 | dst->int_state = from->int_state; | |
2245 | dst->exit_code = from->exit_code; | |
2246 | dst->exit_code_hi = from->exit_code_hi; | |
2247 | dst->exit_info_1 = from->exit_info_1; | |
2248 | dst->exit_info_2 = from->exit_info_2; | |
2249 | dst->exit_int_info = from->exit_int_info; | |
2250 | dst->exit_int_info_err = from->exit_int_info_err; | |
2251 | dst->nested_ctl = from->nested_ctl; | |
2252 | dst->event_inj = from->event_inj; | |
2253 | dst->event_inj_err = from->event_inj_err; | |
2254 | dst->nested_cr3 = from->nested_cr3; | |
2255 | dst->lbr_ctl = from->lbr_ctl; | |
2256 | } | |
2257 | ||
34f80cfa | 2258 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2259 | { |
34f80cfa | 2260 | struct vmcb *nested_vmcb; |
e6aa9abd | 2261 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2262 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2263 | struct page *page; |
cf74a78b | 2264 | |
17897f36 JR |
2265 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2266 | vmcb->control.exit_info_1, | |
2267 | vmcb->control.exit_info_2, | |
2268 | vmcb->control.exit_int_info, | |
e097e5ff SH |
2269 | vmcb->control.exit_int_info_err, |
2270 | KVM_ISA_SVM); | |
17897f36 | 2271 | |
7597f129 | 2272 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2273 | if (!nested_vmcb) |
2274 | return 1; | |
2275 | ||
2030753d JR |
2276 | /* Exit Guest-Mode */ |
2277 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2278 | svm->nested.vmcb = 0; |
2279 | ||
cf74a78b | 2280 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2281 | disable_gif(svm); |
2282 | ||
2283 | nested_vmcb->save.es = vmcb->save.es; | |
2284 | nested_vmcb->save.cs = vmcb->save.cs; | |
2285 | nested_vmcb->save.ss = vmcb->save.ss; | |
2286 | nested_vmcb->save.ds = vmcb->save.ds; | |
2287 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2288 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2289 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2290 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2291 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2292 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2293 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2294 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2295 | nested_vmcb->save.rip = vmcb->save.rip; |
2296 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2297 | nested_vmcb->save.rax = vmcb->save.rax; | |
2298 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2299 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2300 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2301 | ||
2302 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2303 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2304 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2305 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2306 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2307 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2308 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2309 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2310 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
7a190667 | 2311 | nested_vmcb->control.next_rip = vmcb->control.next_rip; |
8d23c466 AG |
2312 | |
2313 | /* | |
2314 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2315 | * to make sure that we do not lose injected events. So check event_inj | |
2316 | * here and copy it to exit_int_info if it is valid. | |
2317 | * Exit_int_info and event_inj can't be both valid because the case | |
2318 | * below only happens on a VMRUN instruction intercept which has | |
2319 | * no valid exit_int_info set. | |
2320 | */ | |
2321 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2322 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2323 | ||
2324 | nc->exit_int_info = vmcb->control.event_inj; | |
2325 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2326 | } | |
2327 | ||
33740e40 JR |
2328 | nested_vmcb->control.tlb_ctl = 0; |
2329 | nested_vmcb->control.event_inj = 0; | |
2330 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2331 | |
2332 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2333 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2334 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2335 | ||
cf74a78b | 2336 | /* Restore the original control entries */ |
0460a979 | 2337 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2338 | |
219b65dc AG |
2339 | kvm_clear_exception_queue(&svm->vcpu); |
2340 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2341 | |
4b16184c JR |
2342 | svm->nested.nested_cr3 = 0; |
2343 | ||
cf74a78b AG |
2344 | /* Restore selected save entries */ |
2345 | svm->vmcb->save.es = hsave->save.es; | |
2346 | svm->vmcb->save.cs = hsave->save.cs; | |
2347 | svm->vmcb->save.ss = hsave->save.ss; | |
2348 | svm->vmcb->save.ds = hsave->save.ds; | |
2349 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2350 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2351 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2352 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2353 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2354 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2355 | if (npt_enabled) { | |
2356 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2357 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2358 | } else { | |
2390218b | 2359 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2360 | } |
2361 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2362 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2363 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2364 | svm->vmcb->save.dr7 = 0; | |
2365 | svm->vmcb->save.cpl = 0; | |
2366 | svm->vmcb->control.exit_int_info = 0; | |
2367 | ||
8d28fec4 RJ |
2368 | mark_all_dirty(svm->vmcb); |
2369 | ||
7597f129 | 2370 | nested_svm_unmap(page); |
cf74a78b | 2371 | |
4b16184c | 2372 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2373 | kvm_mmu_reset_context(&svm->vcpu); |
2374 | kvm_mmu_load(&svm->vcpu); | |
2375 | ||
2376 | return 0; | |
2377 | } | |
3d6368ef | 2378 | |
9738b2c9 | 2379 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2380 | { |
323c3d80 JR |
2381 | /* |
2382 | * This function merges the msr permission bitmaps of kvm and the | |
2383 | * nested vmcb. It is omptimized in that it only merges the parts where | |
2384 | * the kvm msr permission bitmap may contain zero bits | |
2385 | */ | |
3d6368ef | 2386 | int i; |
9738b2c9 | 2387 | |
323c3d80 JR |
2388 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2389 | return true; | |
9738b2c9 | 2390 | |
323c3d80 JR |
2391 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2392 | u32 value, p; | |
2393 | u64 offset; | |
9738b2c9 | 2394 | |
323c3d80 JR |
2395 | if (msrpm_offsets[i] == 0xffffffff) |
2396 | break; | |
3d6368ef | 2397 | |
0d6b3537 JR |
2398 | p = msrpm_offsets[i]; |
2399 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2400 | |
2401 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2402 | return false; | |
2403 | ||
2404 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2405 | } | |
3d6368ef | 2406 | |
323c3d80 | 2407 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2408 | |
2409 | return true; | |
3d6368ef AG |
2410 | } |
2411 | ||
52c65a30 JR |
2412 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2413 | { | |
2414 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2415 | return false; | |
2416 | ||
dbe77584 JR |
2417 | if (vmcb->control.asid == 0) |
2418 | return false; | |
2419 | ||
4b16184c JR |
2420 | if (vmcb->control.nested_ctl && !npt_enabled) |
2421 | return false; | |
2422 | ||
52c65a30 JR |
2423 | return true; |
2424 | } | |
2425 | ||
9738b2c9 | 2426 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2427 | { |
9738b2c9 | 2428 | struct vmcb *nested_vmcb; |
e6aa9abd | 2429 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2430 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2431 | struct page *page; |
06fc7772 | 2432 | u64 vmcb_gpa; |
3d6368ef | 2433 | |
06fc7772 | 2434 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2435 | |
7597f129 | 2436 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2437 | if (!nested_vmcb) |
2438 | return false; | |
2439 | ||
52c65a30 JR |
2440 | if (!nested_vmcb_checks(nested_vmcb)) { |
2441 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2442 | nested_vmcb->control.exit_code_hi = 0; | |
2443 | nested_vmcb->control.exit_info_1 = 0; | |
2444 | nested_vmcb->control.exit_info_2 = 0; | |
2445 | ||
2446 | nested_svm_unmap(page); | |
2447 | ||
2448 | return false; | |
2449 | } | |
2450 | ||
b75f4eb3 | 2451 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2452 | nested_vmcb->save.rip, |
2453 | nested_vmcb->control.int_ctl, | |
2454 | nested_vmcb->control.event_inj, | |
2455 | nested_vmcb->control.nested_ctl); | |
2456 | ||
4ee546b4 RJ |
2457 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2458 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2459 | nested_vmcb->control.intercept_exceptions, |
2460 | nested_vmcb->control.intercept); | |
2461 | ||
3d6368ef | 2462 | /* Clear internal status */ |
219b65dc AG |
2463 | kvm_clear_exception_queue(&svm->vcpu); |
2464 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2465 | |
e0231715 JR |
2466 | /* |
2467 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2468 | * restore everything when a VMEXIT occurs | |
2469 | */ | |
defbba56 JR |
2470 | hsave->save.es = vmcb->save.es; |
2471 | hsave->save.cs = vmcb->save.cs; | |
2472 | hsave->save.ss = vmcb->save.ss; | |
2473 | hsave->save.ds = vmcb->save.ds; | |
2474 | hsave->save.gdtr = vmcb->save.gdtr; | |
2475 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2476 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2477 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 | 2478 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2479 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); |
b75f4eb3 | 2480 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2481 | hsave->save.rsp = vmcb->save.rsp; |
2482 | hsave->save.rax = vmcb->save.rax; | |
2483 | if (npt_enabled) | |
2484 | hsave->save.cr3 = vmcb->save.cr3; | |
2485 | else | |
9f8fe504 | 2486 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2487 | |
0460a979 | 2488 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef | 2489 | |
f6e78475 | 2490 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2491 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2492 | else | |
2493 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2494 | ||
4b16184c JR |
2495 | if (nested_vmcb->control.nested_ctl) { |
2496 | kvm_mmu_unload(&svm->vcpu); | |
2497 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2498 | nested_svm_init_mmu_context(&svm->vcpu); | |
2499 | } | |
2500 | ||
3d6368ef AG |
2501 | /* Load the nested guest state */ |
2502 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2503 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2504 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2505 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2506 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2507 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2508 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2509 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
2510 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2511 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2512 | if (npt_enabled) { | |
2513 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2514 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2515 | } else |
2390218b | 2516 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2517 | |
2518 | /* Guest paging mode is active - reset mmu */ | |
2519 | kvm_mmu_reset_context(&svm->vcpu); | |
2520 | ||
defbba56 | 2521 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2522 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2523 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2524 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2525 | |
3d6368ef AG |
2526 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2527 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2528 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2529 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2530 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2531 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2532 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2533 | ||
f7138538 | 2534 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2535 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2536 | |
aad42c64 | 2537 | /* cache intercepts */ |
4ee546b4 | 2538 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2539 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2540 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2541 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2542 | ||
f40f6a45 | 2543 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2544 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2545 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2546 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2547 | else | |
2548 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2549 | ||
88ab24ad JR |
2550 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2551 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2552 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2553 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2554 | } |
2555 | ||
0d945bd9 | 2556 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2557 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2558 | |
88ab24ad | 2559 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2560 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2561 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2562 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2563 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2564 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2565 | ||
7597f129 | 2566 | nested_svm_unmap(page); |
9738b2c9 | 2567 | |
2030753d JR |
2568 | /* Enter Guest-Mode */ |
2569 | enter_guest_mode(&svm->vcpu); | |
2570 | ||
384c6368 JR |
2571 | /* |
2572 | * Merge guest and host intercepts - must be called with vcpu in | |
2573 | * guest-mode to take affect here | |
2574 | */ | |
2575 | recalc_intercepts(svm); | |
2576 | ||
06fc7772 | 2577 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2578 | |
2af9194d | 2579 | enable_gif(svm); |
3d6368ef | 2580 | |
8d28fec4 RJ |
2581 | mark_all_dirty(svm->vmcb); |
2582 | ||
9738b2c9 | 2583 | return true; |
3d6368ef AG |
2584 | } |
2585 | ||
9966bf68 | 2586 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2587 | { |
2588 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2589 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2590 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2591 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2592 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2593 | to_vmcb->save.star = from_vmcb->save.star; | |
2594 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2595 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2596 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2597 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2598 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2599 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2600 | } |
2601 | ||
851ba692 | 2602 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2603 | { |
9966bf68 | 2604 | struct vmcb *nested_vmcb; |
7597f129 | 2605 | struct page *page; |
9966bf68 | 2606 | |
5542675b AG |
2607 | if (nested_svm_check_permissions(svm)) |
2608 | return 1; | |
2609 | ||
7597f129 | 2610 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2611 | if (!nested_vmcb) |
2612 | return 1; | |
2613 | ||
e3e9ed3d JR |
2614 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2615 | skip_emulated_instruction(&svm->vcpu); | |
2616 | ||
9966bf68 | 2617 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 2618 | nested_svm_unmap(page); |
5542675b AG |
2619 | |
2620 | return 1; | |
2621 | } | |
2622 | ||
851ba692 | 2623 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2624 | { |
9966bf68 | 2625 | struct vmcb *nested_vmcb; |
7597f129 | 2626 | struct page *page; |
9966bf68 | 2627 | |
5542675b AG |
2628 | if (nested_svm_check_permissions(svm)) |
2629 | return 1; | |
2630 | ||
7597f129 | 2631 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2632 | if (!nested_vmcb) |
2633 | return 1; | |
2634 | ||
e3e9ed3d JR |
2635 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2636 | skip_emulated_instruction(&svm->vcpu); | |
2637 | ||
9966bf68 | 2638 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 2639 | nested_svm_unmap(page); |
5542675b AG |
2640 | |
2641 | return 1; | |
2642 | } | |
2643 | ||
851ba692 | 2644 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2645 | { |
3d6368ef AG |
2646 | if (nested_svm_check_permissions(svm)) |
2647 | return 1; | |
2648 | ||
b75f4eb3 RJ |
2649 | /* Save rip after vmrun instruction */ |
2650 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2651 | |
9738b2c9 | 2652 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2653 | return 1; |
2654 | ||
9738b2c9 | 2655 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2656 | goto failed; |
2657 | ||
2658 | return 1; | |
2659 | ||
2660 | failed: | |
2661 | ||
2662 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2663 | svm->vmcb->control.exit_code_hi = 0; | |
2664 | svm->vmcb->control.exit_info_1 = 0; | |
2665 | svm->vmcb->control.exit_info_2 = 0; | |
2666 | ||
2667 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2668 | |
2669 | return 1; | |
2670 | } | |
2671 | ||
851ba692 | 2672 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2673 | { |
2674 | if (nested_svm_check_permissions(svm)) | |
2675 | return 1; | |
2676 | ||
2677 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2678 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2679 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2680 | |
2af9194d | 2681 | enable_gif(svm); |
1371d904 AG |
2682 | |
2683 | return 1; | |
2684 | } | |
2685 | ||
851ba692 | 2686 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2687 | { |
2688 | if (nested_svm_check_permissions(svm)) | |
2689 | return 1; | |
2690 | ||
2691 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2692 | skip_emulated_instruction(&svm->vcpu); | |
2693 | ||
2af9194d | 2694 | disable_gif(svm); |
1371d904 AG |
2695 | |
2696 | /* After a CLGI no interrupts should come */ | |
2697 | svm_clear_vintr(svm); | |
2698 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2699 | ||
decdbf6a JR |
2700 | mark_dirty(svm->vmcb, VMCB_INTR); |
2701 | ||
1371d904 AG |
2702 | return 1; |
2703 | } | |
2704 | ||
851ba692 | 2705 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2706 | { |
2707 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2708 | |
ec1ff790 JR |
2709 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2710 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2711 | ||
ff092385 AG |
2712 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2713 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2714 | ||
2715 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2716 | skip_emulated_instruction(&svm->vcpu); | |
2717 | return 1; | |
2718 | } | |
2719 | ||
532a46b9 JR |
2720 | static int skinit_interception(struct vcpu_svm *svm) |
2721 | { | |
2722 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2723 | ||
2724 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2725 | return 1; | |
2726 | } | |
2727 | ||
81dd35d4 JR |
2728 | static int xsetbv_interception(struct vcpu_svm *svm) |
2729 | { | |
2730 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
2731 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
2732 | ||
2733 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
2734 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2735 | skip_emulated_instruction(&svm->vcpu); | |
2736 | } | |
2737 | ||
2738 | return 1; | |
2739 | } | |
2740 | ||
851ba692 | 2741 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2742 | { |
7ee5d940 | 2743 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2744 | return 1; |
2745 | } | |
2746 | ||
851ba692 | 2747 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2748 | { |
37817f29 | 2749 | u16 tss_selector; |
64a7ec06 GN |
2750 | int reason; |
2751 | int int_type = svm->vmcb->control.exit_int_info & | |
2752 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2753 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2754 | uint32_t type = |
2755 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2756 | uint32_t idt_v = | |
2757 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2758 | bool has_error_code = false; |
2759 | u32 error_code = 0; | |
37817f29 IE |
2760 | |
2761 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2762 | |
37817f29 IE |
2763 | if (svm->vmcb->control.exit_info_2 & |
2764 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2765 | reason = TASK_SWITCH_IRET; |
2766 | else if (svm->vmcb->control.exit_info_2 & | |
2767 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2768 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2769 | else if (idt_v) |
64a7ec06 GN |
2770 | reason = TASK_SWITCH_GATE; |
2771 | else | |
2772 | reason = TASK_SWITCH_CALL; | |
2773 | ||
fe8e7f83 GN |
2774 | if (reason == TASK_SWITCH_GATE) { |
2775 | switch (type) { | |
2776 | case SVM_EXITINTINFO_TYPE_NMI: | |
2777 | svm->vcpu.arch.nmi_injected = false; | |
2778 | break; | |
2779 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2780 | if (svm->vmcb->control.exit_info_2 & |
2781 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2782 | has_error_code = true; | |
2783 | error_code = | |
2784 | (u32)svm->vmcb->control.exit_info_2; | |
2785 | } | |
fe8e7f83 GN |
2786 | kvm_clear_exception_queue(&svm->vcpu); |
2787 | break; | |
2788 | case SVM_EXITINTINFO_TYPE_INTR: | |
2789 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2790 | break; | |
2791 | default: | |
2792 | break; | |
2793 | } | |
2794 | } | |
64a7ec06 | 2795 | |
8317c298 GN |
2796 | if (reason != TASK_SWITCH_GATE || |
2797 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2798 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2799 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2800 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2801 | |
acb54517 GN |
2802 | if (kvm_task_switch(&svm->vcpu, tss_selector, reason, |
2803 | has_error_code, error_code) == EMULATE_FAIL) { | |
2804 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2805 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2806 | svm->vcpu.run->internal.ndata = 0; | |
2807 | return 0; | |
2808 | } | |
2809 | return 1; | |
6aa8b732 AK |
2810 | } |
2811 | ||
851ba692 | 2812 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2813 | { |
5fdbf976 | 2814 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2815 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2816 | return 1; |
6aa8b732 AK |
2817 | } |
2818 | ||
851ba692 | 2819 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2820 | { |
2821 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 2822 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 2823 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 2824 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
95ba8273 GN |
2825 | return 1; |
2826 | } | |
2827 | ||
851ba692 | 2828 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2829 | { |
df4f3108 AP |
2830 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
2831 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
2832 | ||
2833 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
2834 | skip_emulated_instruction(&svm->vcpu); | |
2835 | return 1; | |
a7052897 MT |
2836 | } |
2837 | ||
851ba692 | 2838 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2839 | { |
51d8b661 | 2840 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
2841 | } |
2842 | ||
332b56e4 AK |
2843 | static int rdpmc_interception(struct vcpu_svm *svm) |
2844 | { | |
2845 | int err; | |
2846 | ||
2847 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
2848 | return emulate_on_interception(svm); | |
2849 | ||
2850 | err = kvm_rdpmc(&svm->vcpu); | |
2851 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2852 | ||
2853 | return 1; | |
2854 | } | |
2855 | ||
628afd2a JR |
2856 | bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val) |
2857 | { | |
2858 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
2859 | bool ret = false; | |
2860 | u64 intercept; | |
2861 | ||
2862 | intercept = svm->nested.intercept; | |
2863 | ||
2864 | if (!is_guest_mode(&svm->vcpu) || | |
2865 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
2866 | return false; | |
2867 | ||
2868 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
2869 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
2870 | ||
2871 | if (cr0 ^ val) { | |
2872 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
2873 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
2874 | } | |
2875 | ||
2876 | return ret; | |
2877 | } | |
2878 | ||
7ff76d58 AP |
2879 | #define CR_VALID (1ULL << 63) |
2880 | ||
2881 | static int cr_interception(struct vcpu_svm *svm) | |
2882 | { | |
2883 | int reg, cr; | |
2884 | unsigned long val; | |
2885 | int err; | |
2886 | ||
2887 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2888 | return emulate_on_interception(svm); | |
2889 | ||
2890 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
2891 | return emulate_on_interception(svm); | |
2892 | ||
2893 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2894 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
2895 | ||
2896 | err = 0; | |
2897 | if (cr >= 16) { /* mov to cr */ | |
2898 | cr -= 16; | |
2899 | val = kvm_register_read(&svm->vcpu, reg); | |
2900 | switch (cr) { | |
2901 | case 0: | |
628afd2a JR |
2902 | if (!check_selective_cr0_intercepted(svm, val)) |
2903 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
2904 | else |
2905 | return 1; | |
2906 | ||
7ff76d58 AP |
2907 | break; |
2908 | case 3: | |
2909 | err = kvm_set_cr3(&svm->vcpu, val); | |
2910 | break; | |
2911 | case 4: | |
2912 | err = kvm_set_cr4(&svm->vcpu, val); | |
2913 | break; | |
2914 | case 8: | |
2915 | err = kvm_set_cr8(&svm->vcpu, val); | |
2916 | break; | |
2917 | default: | |
2918 | WARN(1, "unhandled write to CR%d", cr); | |
2919 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2920 | return 1; | |
2921 | } | |
2922 | } else { /* mov from cr */ | |
2923 | switch (cr) { | |
2924 | case 0: | |
2925 | val = kvm_read_cr0(&svm->vcpu); | |
2926 | break; | |
2927 | case 2: | |
2928 | val = svm->vcpu.arch.cr2; | |
2929 | break; | |
2930 | case 3: | |
9f8fe504 | 2931 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
2932 | break; |
2933 | case 4: | |
2934 | val = kvm_read_cr4(&svm->vcpu); | |
2935 | break; | |
2936 | case 8: | |
2937 | val = kvm_get_cr8(&svm->vcpu); | |
2938 | break; | |
2939 | default: | |
2940 | WARN(1, "unhandled read from CR%d", cr); | |
2941 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2942 | return 1; | |
2943 | } | |
2944 | kvm_register_write(&svm->vcpu, reg, val); | |
2945 | } | |
2946 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2947 | ||
2948 | return 1; | |
2949 | } | |
2950 | ||
cae3797a AP |
2951 | static int dr_interception(struct vcpu_svm *svm) |
2952 | { | |
2953 | int reg, dr; | |
2954 | unsigned long val; | |
2955 | int err; | |
2956 | ||
2957 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2958 | return emulate_on_interception(svm); | |
2959 | ||
2960 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2961 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
2962 | ||
2963 | if (dr >= 16) { /* mov to DRn */ | |
2964 | val = kvm_register_read(&svm->vcpu, reg); | |
2965 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
2966 | } else { | |
2967 | err = kvm_get_dr(&svm->vcpu, dr, &val); | |
2968 | if (!err) | |
2969 | kvm_register_write(&svm->vcpu, reg, val); | |
2970 | } | |
2971 | ||
2c46d2ae JR |
2972 | skip_emulated_instruction(&svm->vcpu); |
2973 | ||
cae3797a AP |
2974 | return 1; |
2975 | } | |
2976 | ||
851ba692 | 2977 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2978 | { |
851ba692 | 2979 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 2980 | int r; |
851ba692 | 2981 | |
0a5fff19 GN |
2982 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2983 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 2984 | r = cr_interception(svm); |
95ba8273 | 2985 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
4ee546b4 | 2986 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
7ff76d58 | 2987 | return r; |
95ba8273 | 2988 | } |
0a5fff19 | 2989 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 2990 | return r; |
1d075434 JR |
2991 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2992 | return 0; | |
2993 | } | |
2994 | ||
d5c1785d NHE |
2995 | u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu) |
2996 | { | |
2997 | struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu)); | |
2998 | return vmcb->control.tsc_offset + | |
2999 | svm_scale_tsc(vcpu, native_read_tsc()); | |
3000 | } | |
3001 | ||
6aa8b732 AK |
3002 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
3003 | { | |
a2fa3e9f GH |
3004 | struct vcpu_svm *svm = to_svm(vcpu); |
3005 | ||
6aa8b732 | 3006 | switch (ecx) { |
af24a4e4 | 3007 | case MSR_IA32_TSC: { |
45133eca | 3008 | *data = svm->vmcb->control.tsc_offset + |
fbc0db76 JR |
3009 | svm_scale_tsc(vcpu, native_read_tsc()); |
3010 | ||
6aa8b732 AK |
3011 | break; |
3012 | } | |
8c06585d | 3013 | case MSR_STAR: |
a2fa3e9f | 3014 | *data = svm->vmcb->save.star; |
6aa8b732 | 3015 | break; |
0e859cac | 3016 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3017 | case MSR_LSTAR: |
a2fa3e9f | 3018 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3019 | break; |
3020 | case MSR_CSTAR: | |
a2fa3e9f | 3021 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3022 | break; |
3023 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3024 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3025 | break; |
3026 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3027 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3028 | break; |
3029 | #endif | |
3030 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3031 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3032 | break; |
3033 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3034 | *data = svm->sysenter_eip; |
6aa8b732 AK |
3035 | break; |
3036 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3037 | *data = svm->sysenter_esp; |
6aa8b732 | 3038 | break; |
e0231715 JR |
3039 | /* |
3040 | * Nobody will change the following 5 values in the VMCB so we can | |
3041 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3042 | * implemented. | |
3043 | */ | |
a2938c80 JR |
3044 | case MSR_IA32_DEBUGCTLMSR: |
3045 | *data = svm->vmcb->save.dbgctl; | |
3046 | break; | |
3047 | case MSR_IA32_LASTBRANCHFROMIP: | |
3048 | *data = svm->vmcb->save.br_from; | |
3049 | break; | |
3050 | case MSR_IA32_LASTBRANCHTOIP: | |
3051 | *data = svm->vmcb->save.br_to; | |
3052 | break; | |
3053 | case MSR_IA32_LASTINTFROMIP: | |
3054 | *data = svm->vmcb->save.last_excp_from; | |
3055 | break; | |
3056 | case MSR_IA32_LASTINTTOIP: | |
3057 | *data = svm->vmcb->save.last_excp_to; | |
3058 | break; | |
b286d5d8 | 3059 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3060 | *data = svm->nested.hsave_msr; |
b286d5d8 | 3061 | break; |
eb6f302e | 3062 | case MSR_VM_CR: |
4a810181 | 3063 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 3064 | break; |
c8a73f18 AG |
3065 | case MSR_IA32_UCODE_REV: |
3066 | *data = 0x01000065; | |
3067 | break; | |
6aa8b732 | 3068 | default: |
3bab1f5d | 3069 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
3070 | } |
3071 | return 0; | |
3072 | } | |
3073 | ||
851ba692 | 3074 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3075 | { |
ad312c7c | 3076 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
3077 | u64 data; |
3078 | ||
59200273 AK |
3079 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
3080 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 3081 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 3082 | } else { |
229456fc | 3083 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 3084 | |
5fdbf976 | 3085 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 3086 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 3087 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 3088 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
3089 | } |
3090 | return 1; | |
3091 | } | |
3092 | ||
4a810181 JR |
3093 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3094 | { | |
3095 | struct vcpu_svm *svm = to_svm(vcpu); | |
3096 | int svm_dis, chg_mask; | |
3097 | ||
3098 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3099 | return 1; | |
3100 | ||
3101 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3102 | ||
3103 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3104 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3105 | ||
3106 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3107 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3108 | ||
3109 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3110 | ||
3111 | /* check for svm_disable while efer.svme is set */ | |
3112 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3113 | return 1; | |
3114 | ||
3115 | return 0; | |
3116 | } | |
3117 | ||
6aa8b732 AK |
3118 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) |
3119 | { | |
a2fa3e9f GH |
3120 | struct vcpu_svm *svm = to_svm(vcpu); |
3121 | ||
6aa8b732 | 3122 | switch (ecx) { |
f4e1b3c8 | 3123 | case MSR_IA32_TSC: |
99e3e30a | 3124 | kvm_write_tsc(vcpu, data); |
6aa8b732 | 3125 | break; |
8c06585d | 3126 | case MSR_STAR: |
a2fa3e9f | 3127 | svm->vmcb->save.star = data; |
6aa8b732 | 3128 | break; |
49b14f24 | 3129 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3130 | case MSR_LSTAR: |
a2fa3e9f | 3131 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3132 | break; |
3133 | case MSR_CSTAR: | |
a2fa3e9f | 3134 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3135 | break; |
3136 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3137 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3138 | break; |
3139 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3140 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3141 | break; |
3142 | #endif | |
3143 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3144 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3145 | break; |
3146 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3147 | svm->sysenter_eip = data; |
a2fa3e9f | 3148 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
3149 | break; |
3150 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3151 | svm->sysenter_esp = data; |
a2fa3e9f | 3152 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 3153 | break; |
a2938c80 | 3154 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 3155 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
24e09cbf | 3156 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
b8688d51 | 3157 | __func__, data); |
24e09cbf JR |
3158 | break; |
3159 | } | |
3160 | if (data & DEBUGCTL_RESERVED_BITS) | |
3161 | return 1; | |
3162 | ||
3163 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 3164 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
3165 | if (data & (1ULL<<0)) |
3166 | svm_enable_lbrv(svm); | |
3167 | else | |
3168 | svm_disable_lbrv(svm); | |
a2938c80 | 3169 | break; |
b286d5d8 | 3170 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3171 | svm->nested.hsave_msr = data; |
62b9abaa | 3172 | break; |
3c5d0a44 | 3173 | case MSR_VM_CR: |
4a810181 | 3174 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3175 | case MSR_VM_IGNNE: |
3c5d0a44 AG |
3176 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3177 | break; | |
6aa8b732 | 3178 | default: |
3bab1f5d | 3179 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
3180 | } |
3181 | return 0; | |
3182 | } | |
3183 | ||
851ba692 | 3184 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3185 | { |
ad312c7c | 3186 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 3187 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 3188 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 3189 | |
af9ca2d7 | 3190 | |
5fdbf976 | 3191 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
59200273 AK |
3192 | if (svm_set_msr(&svm->vcpu, ecx, data)) { |
3193 | trace_kvm_msr_write_ex(ecx, data); | |
c1a5d4f9 | 3194 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
3195 | } else { |
3196 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 3197 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 3198 | } |
6aa8b732 AK |
3199 | return 1; |
3200 | } | |
3201 | ||
851ba692 | 3202 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3203 | { |
e756fc62 | 3204 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3205 | return wrmsr_interception(svm); |
6aa8b732 | 3206 | else |
851ba692 | 3207 | return rdmsr_interception(svm); |
6aa8b732 AK |
3208 | } |
3209 | ||
851ba692 | 3210 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3211 | { |
851ba692 AK |
3212 | struct kvm_run *kvm_run = svm->vcpu.run; |
3213 | ||
3842d135 | 3214 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3215 | svm_clear_vintr(svm); |
85f455f7 | 3216 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3217 | mark_dirty(svm->vmcb, VMCB_INTR); |
c1150d8c DL |
3218 | /* |
3219 | * If the user space waits to inject interrupts, exit as soon as | |
3220 | * possible | |
3221 | */ | |
8061823a GN |
3222 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
3223 | kvm_run->request_interrupt_window && | |
3224 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 3225 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3226 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
3227 | return 0; | |
3228 | } | |
3229 | ||
3230 | return 1; | |
3231 | } | |
3232 | ||
565d0998 ML |
3233 | static int pause_interception(struct vcpu_svm *svm) |
3234 | { | |
3235 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3236 | return 1; | |
3237 | } | |
3238 | ||
851ba692 | 3239 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
3240 | [SVM_EXIT_READ_CR0] = cr_interception, |
3241 | [SVM_EXIT_READ_CR3] = cr_interception, | |
3242 | [SVM_EXIT_READ_CR4] = cr_interception, | |
3243 | [SVM_EXIT_READ_CR8] = cr_interception, | |
d225157b | 3244 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
628afd2a | 3245 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
3246 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
3247 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 3248 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
3249 | [SVM_EXIT_READ_DR0] = dr_interception, |
3250 | [SVM_EXIT_READ_DR1] = dr_interception, | |
3251 | [SVM_EXIT_READ_DR2] = dr_interception, | |
3252 | [SVM_EXIT_READ_DR3] = dr_interception, | |
3253 | [SVM_EXIT_READ_DR4] = dr_interception, | |
3254 | [SVM_EXIT_READ_DR5] = dr_interception, | |
3255 | [SVM_EXIT_READ_DR6] = dr_interception, | |
3256 | [SVM_EXIT_READ_DR7] = dr_interception, | |
3257 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
3258 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
3259 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
3260 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
3261 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
3262 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
3263 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
3264 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
3265 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
3266 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 3267 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
3268 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
3269 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
3270 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
3271 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 3272 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
3273 | [SVM_EXIT_SMI] = nop_on_interception, |
3274 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 3275 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 3276 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 3277 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 3278 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 3279 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 3280 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 3281 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 3282 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 3283 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 3284 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
3285 | [SVM_EXIT_MSR] = msr_interception, |
3286 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 3287 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 3288 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 3289 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
3290 | [SVM_EXIT_VMLOAD] = vmload_interception, |
3291 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
3292 | [SVM_EXIT_STGI] = stgi_interception, |
3293 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 3294 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 3295 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
3296 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
3297 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
81dd35d4 | 3298 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 3299 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
3300 | }; |
3301 | ||
ae8cc059 | 3302 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
3303 | { |
3304 | struct vcpu_svm *svm = to_svm(vcpu); | |
3305 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3306 | struct vmcb_save_area *save = &svm->vmcb->save; | |
3307 | ||
3308 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
3309 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
3310 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
3311 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
3312 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
3313 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
3314 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
3315 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
3316 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
3317 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
3318 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
3319 | pr_err("%-20s%d\n", "asid:", control->asid); | |
3320 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
3321 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
3322 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
3323 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
3324 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
3325 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
3326 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
3327 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
3328 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
3329 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
3330 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
3331 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); | |
3332 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
3333 | pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl); | |
3334 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); | |
3f10c846 | 3335 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
3336 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
3337 | "es:", | |
3338 | save->es.selector, save->es.attrib, | |
3339 | save->es.limit, save->es.base); | |
3340 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3341 | "cs:", | |
3342 | save->cs.selector, save->cs.attrib, | |
3343 | save->cs.limit, save->cs.base); | |
3344 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3345 | "ss:", | |
3346 | save->ss.selector, save->ss.attrib, | |
3347 | save->ss.limit, save->ss.base); | |
3348 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3349 | "ds:", | |
3350 | save->ds.selector, save->ds.attrib, | |
3351 | save->ds.limit, save->ds.base); | |
3352 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3353 | "fs:", | |
3354 | save->fs.selector, save->fs.attrib, | |
3355 | save->fs.limit, save->fs.base); | |
3356 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3357 | "gs:", | |
3358 | save->gs.selector, save->gs.attrib, | |
3359 | save->gs.limit, save->gs.base); | |
3360 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3361 | "gdtr:", | |
3362 | save->gdtr.selector, save->gdtr.attrib, | |
3363 | save->gdtr.limit, save->gdtr.base); | |
3364 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3365 | "ldtr:", | |
3366 | save->ldtr.selector, save->ldtr.attrib, | |
3367 | save->ldtr.limit, save->ldtr.base); | |
3368 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3369 | "idtr:", | |
3370 | save->idtr.selector, save->idtr.attrib, | |
3371 | save->idtr.limit, save->idtr.base); | |
3372 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3373 | "tr:", | |
3374 | save->tr.selector, save->tr.attrib, | |
3375 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
3376 | pr_err("cpl: %d efer: %016llx\n", |
3377 | save->cpl, save->efer); | |
ae8cc059 JP |
3378 | pr_err("%-15s %016llx %-13s %016llx\n", |
3379 | "cr0:", save->cr0, "cr2:", save->cr2); | |
3380 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3381 | "cr3:", save->cr3, "cr4:", save->cr4); | |
3382 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3383 | "dr6:", save->dr6, "dr7:", save->dr7); | |
3384 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3385 | "rip:", save->rip, "rflags:", save->rflags); | |
3386 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3387 | "rsp:", save->rsp, "rax:", save->rax); | |
3388 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3389 | "star:", save->star, "lstar:", save->lstar); | |
3390 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3391 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
3392 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3393 | "kernel_gs_base:", save->kernel_gs_base, | |
3394 | "sysenter_cs:", save->sysenter_cs); | |
3395 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3396 | "sysenter_esp:", save->sysenter_esp, | |
3397 | "sysenter_eip:", save->sysenter_eip); | |
3398 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3399 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
3400 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3401 | "br_from:", save->br_from, "br_to:", save->br_to); | |
3402 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3403 | "excp_from:", save->last_excp_from, | |
3404 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
3405 | } |
3406 | ||
586f9607 AK |
3407 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3408 | { | |
3409 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3410 | ||
3411 | *info1 = control->exit_info_1; | |
3412 | *info2 = control->exit_info_2; | |
3413 | } | |
3414 | ||
851ba692 | 3415 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3416 | { |
04d2cc77 | 3417 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3418 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3419 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3420 | |
4ee546b4 | 3421 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3422 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3423 | if (npt_enabled) | |
3424 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3425 | |
cd3ff653 JR |
3426 | if (unlikely(svm->nested.exit_required)) { |
3427 | nested_svm_vmexit(svm); | |
3428 | svm->nested.exit_required = false; | |
3429 | ||
3430 | return 1; | |
3431 | } | |
3432 | ||
2030753d | 3433 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3434 | int vmexit; |
3435 | ||
d8cabddf JR |
3436 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3437 | svm->vmcb->control.exit_info_1, | |
3438 | svm->vmcb->control.exit_info_2, | |
3439 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
3440 | svm->vmcb->control.exit_int_info_err, |
3441 | KVM_ISA_SVM); | |
d8cabddf | 3442 | |
410e4d57 JR |
3443 | vmexit = nested_svm_exit_special(svm); |
3444 | ||
3445 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3446 | vmexit = nested_svm_exit_handled(svm); | |
3447 | ||
3448 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3449 | return 1; |
cf74a78b AG |
3450 | } |
3451 | ||
a5c3832d JR |
3452 | svm_complete_interrupts(svm); |
3453 | ||
04d2cc77 AK |
3454 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3455 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3456 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3457 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3458 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3459 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3460 | return 0; |
3461 | } | |
3462 | ||
a2fa3e9f | 3463 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3464 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3465 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3466 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6aa8b732 AK |
3467 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
3468 | "exit_code 0x%x\n", | |
b8688d51 | 3469 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3470 | exit_code); |
3471 | ||
9d8f549d | 3472 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3473 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 3474 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 3475 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
3476 | return 0; |
3477 | } | |
3478 | ||
851ba692 | 3479 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3480 | } |
3481 | ||
3482 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3483 | { | |
3484 | int cpu = raw_smp_processor_id(); | |
3485 | ||
0fe1e009 TH |
3486 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3487 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3488 | load_TR_desc(); |
3489 | } | |
3490 | ||
e756fc62 | 3491 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3492 | { |
3493 | int cpu = raw_smp_processor_id(); | |
3494 | ||
0fe1e009 | 3495 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3496 | |
4b656b12 | 3497 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3498 | if (svm->asid_generation != sd->asid_generation) |
3499 | new_asid(svm, sd); | |
6aa8b732 AK |
3500 | } |
3501 | ||
95ba8273 GN |
3502 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3503 | { | |
3504 | struct vcpu_svm *svm = to_svm(vcpu); | |
3505 | ||
3506 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3507 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3508 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
3509 | ++vcpu->stat.nmi_injections; |
3510 | } | |
6aa8b732 | 3511 | |
85f455f7 | 3512 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3513 | { |
3514 | struct vmcb_control_area *control; | |
3515 | ||
e756fc62 | 3516 | control = &svm->vmcb->control; |
85f455f7 | 3517 | control->int_vector = irq; |
6aa8b732 AK |
3518 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3519 | control->int_ctl |= V_IRQ_MASK | | |
3520 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 3521 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
3522 | } |
3523 | ||
66fd3f7f | 3524 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3525 | { |
3526 | struct vcpu_svm *svm = to_svm(vcpu); | |
3527 | ||
2af9194d | 3528 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3529 | |
9fb2d2b4 GN |
3530 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3531 | ++vcpu->stat.irq_injections; | |
3532 | ||
219b65dc AG |
3533 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3534 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3535 | } |
3536 | ||
95ba8273 | 3537 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3538 | { |
3539 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3540 | |
2030753d | 3541 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3542 | return; |
3543 | ||
95ba8273 | 3544 | if (irr == -1) |
aaacfc9a JR |
3545 | return; |
3546 | ||
95ba8273 | 3547 | if (tpr >= irr) |
4ee546b4 | 3548 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3549 | } |
aaacfc9a | 3550 | |
95ba8273 GN |
3551 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3552 | { | |
3553 | struct vcpu_svm *svm = to_svm(vcpu); | |
3554 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3555 | int ret; |
3556 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3557 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3558 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3559 | ||
3560 | return ret; | |
aaacfc9a JR |
3561 | } |
3562 | ||
3cfc3092 JK |
3563 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3564 | { | |
3565 | struct vcpu_svm *svm = to_svm(vcpu); | |
3566 | ||
3567 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3568 | } | |
3569 | ||
3570 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3571 | { | |
3572 | struct vcpu_svm *svm = to_svm(vcpu); | |
3573 | ||
3574 | if (masked) { | |
3575 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3576 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3577 | } else { |
3578 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 3579 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3580 | } |
3581 | } | |
3582 | ||
78646121 GN |
3583 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3584 | { | |
3585 | struct vcpu_svm *svm = to_svm(vcpu); | |
3586 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3587 | int ret; |
3588 | ||
3589 | if (!gif_set(svm) || | |
3590 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3591 | return 0; | |
3592 | ||
f6e78475 | 3593 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 3594 | |
2030753d | 3595 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3596 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3597 | ||
3598 | return ret; | |
78646121 GN |
3599 | } |
3600 | ||
9222be18 | 3601 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3602 | { |
219b65dc | 3603 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3604 | |
e0231715 JR |
3605 | /* |
3606 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3607 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3608 | * get that intercept, this function will be called again though and | |
3609 | * we'll get the vintr intercept. | |
3610 | */ | |
8fe54654 | 3611 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3612 | svm_set_vintr(svm); |
3613 | svm_inject_irq(svm, 0x0); | |
3614 | } | |
85f455f7 ED |
3615 | } |
3616 | ||
95ba8273 | 3617 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3618 | { |
04d2cc77 | 3619 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3620 | |
44c11430 GN |
3621 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3622 | == HF_NMI_MASK) | |
3623 | return; /* IRET will cause a vm exit */ | |
3624 | ||
e0231715 JR |
3625 | /* |
3626 | * Something prevents NMI from been injected. Single step over possible | |
3627 | * problem (IRET or exception injection or interrupt shadow) | |
3628 | */ | |
6be7d306 | 3629 | svm->nmi_singlestep = true; |
44c11430 GN |
3630 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
3631 | update_db_intercept(vcpu); | |
c1150d8c DL |
3632 | } |
3633 | ||
cbc94022 IE |
3634 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3635 | { | |
3636 | return 0; | |
3637 | } | |
3638 | ||
d9e368d6 AK |
3639 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3640 | { | |
38e5e92f JR |
3641 | struct vcpu_svm *svm = to_svm(vcpu); |
3642 | ||
3643 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
3644 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
3645 | else | |
3646 | svm->asid_generation--; | |
d9e368d6 AK |
3647 | } |
3648 | ||
04d2cc77 AK |
3649 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3650 | { | |
3651 | } | |
3652 | ||
d7bf8221 JR |
3653 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3654 | { | |
3655 | struct vcpu_svm *svm = to_svm(vcpu); | |
3656 | ||
2030753d | 3657 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3658 | return; |
3659 | ||
4ee546b4 | 3660 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3661 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3662 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3663 | } |
3664 | } | |
3665 | ||
649d6864 JR |
3666 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3667 | { | |
3668 | struct vcpu_svm *svm = to_svm(vcpu); | |
3669 | u64 cr8; | |
3670 | ||
2030753d | 3671 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3672 | return; |
3673 | ||
649d6864 JR |
3674 | cr8 = kvm_get_cr8(vcpu); |
3675 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3676 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3677 | } | |
3678 | ||
9222be18 GN |
3679 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3680 | { | |
3681 | u8 vector; | |
3682 | int type; | |
3683 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3684 | unsigned int3_injected = svm->int3_injected; |
3685 | ||
3686 | svm->int3_injected = 0; | |
9222be18 | 3687 | |
bd3d1ec3 AK |
3688 | /* |
3689 | * If we've made progress since setting HF_IRET_MASK, we've | |
3690 | * executed an IRET and can allow NMI injection. | |
3691 | */ | |
3692 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
3693 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 3694 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3695 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3696 | } | |
44c11430 | 3697 | |
9222be18 GN |
3698 | svm->vcpu.arch.nmi_injected = false; |
3699 | kvm_clear_exception_queue(&svm->vcpu); | |
3700 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3701 | ||
3702 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3703 | return; | |
3704 | ||
3842d135 AK |
3705 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3706 | ||
9222be18 GN |
3707 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3708 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3709 | ||
3710 | switch (type) { | |
3711 | case SVM_EXITINTINFO_TYPE_NMI: | |
3712 | svm->vcpu.arch.nmi_injected = true; | |
3713 | break; | |
3714 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3715 | /* |
3716 | * In case of software exceptions, do not reinject the vector, | |
3717 | * but re-execute the instruction instead. Rewind RIP first | |
3718 | * if we emulated INT3 before. | |
3719 | */ | |
3720 | if (kvm_exception_is_soft(vector)) { | |
3721 | if (vector == BP_VECTOR && int3_injected && | |
3722 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3723 | kvm_rip_write(&svm->vcpu, | |
3724 | kvm_rip_read(&svm->vcpu) - | |
3725 | int3_injected); | |
9222be18 | 3726 | break; |
66b7138f | 3727 | } |
9222be18 GN |
3728 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3729 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3730 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3731 | |
3732 | } else | |
ce7ddec4 | 3733 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3734 | break; |
3735 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3736 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3737 | break; |
3738 | default: | |
3739 | break; | |
3740 | } | |
3741 | } | |
3742 | ||
b463a6f7 AK |
3743 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3744 | { | |
3745 | struct vcpu_svm *svm = to_svm(vcpu); | |
3746 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3747 | ||
3748 | control->exit_int_info = control->event_inj; | |
3749 | control->exit_int_info_err = control->event_inj_err; | |
3750 | control->event_inj = 0; | |
3751 | svm_complete_interrupts(svm); | |
3752 | } | |
3753 | ||
80e31d4f AK |
3754 | #ifdef CONFIG_X86_64 |
3755 | #define R "r" | |
3756 | #else | |
3757 | #define R "e" | |
3758 | #endif | |
3759 | ||
851ba692 | 3760 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3761 | { |
a2fa3e9f | 3762 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3763 | |
2041a06a JR |
3764 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3765 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3766 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3767 | ||
cd3ff653 JR |
3768 | /* |
3769 | * A vmexit emulation is required before the vcpu can be executed | |
3770 | * again. | |
3771 | */ | |
3772 | if (unlikely(svm->nested.exit_required)) | |
3773 | return; | |
3774 | ||
e756fc62 | 3775 | pre_svm_run(svm); |
6aa8b732 | 3776 | |
649d6864 JR |
3777 | sync_lapic_to_cr8(vcpu); |
3778 | ||
cda0ffdd | 3779 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3780 | |
04d2cc77 AK |
3781 | clgi(); |
3782 | ||
3783 | local_irq_enable(); | |
36241b8c | 3784 | |
6aa8b732 | 3785 | asm volatile ( |
80e31d4f AK |
3786 | "push %%"R"bp; \n\t" |
3787 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
3788 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
3789 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
3790 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
3791 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
3792 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 3793 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3794 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3795 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3796 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3797 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3798 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3799 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3800 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3801 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3802 | #endif |
3803 | ||
6aa8b732 | 3804 | /* Enter guest mode */ |
80e31d4f AK |
3805 | "push %%"R"ax \n\t" |
3806 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
3807 | __ex(SVM_VMLOAD) "\n\t" |
3808 | __ex(SVM_VMRUN) "\n\t" | |
3809 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 3810 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
3811 | |
3812 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
3813 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
3814 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
3815 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
3816 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
3817 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
3818 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3819 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3820 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3821 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3822 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3823 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3824 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3825 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3826 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3827 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3828 | #endif |
80e31d4f | 3829 | "pop %%"R"bp" |
6aa8b732 | 3830 | : |
fb3f0f51 | 3831 | : [svm]"a"(svm), |
6aa8b732 | 3832 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3833 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3834 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3835 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3836 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3837 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3838 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3839 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3840 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3841 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3842 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3843 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3844 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3845 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3846 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3847 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3848 | #endif |
54a08c04 | 3849 | : "cc", "memory" |
80e31d4f | 3850 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 3851 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
3852 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
3853 | #endif | |
3854 | ); | |
6aa8b732 | 3855 | |
82ca2d10 AK |
3856 | #ifdef CONFIG_X86_64 |
3857 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3858 | #else | |
dacccfdd | 3859 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
3860 | #ifndef CONFIG_X86_32_LAZY_GS |
3861 | loadsegment(gs, svm->host.gs); | |
3862 | #endif | |
9581d442 | 3863 | #endif |
6aa8b732 AK |
3864 | |
3865 | reload_tss(vcpu); | |
3866 | ||
56ba47dd AK |
3867 | local_irq_disable(); |
3868 | ||
13c34e07 AK |
3869 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3870 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3871 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3872 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3873 | ||
1e2b1dd7 JK |
3874 | trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM); |
3875 | ||
3781c01c JR |
3876 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
3877 | kvm_before_handle_nmi(&svm->vcpu); | |
3878 | ||
3879 | stgi(); | |
3880 | ||
3881 | /* Any pending NMI will happen here */ | |
3882 | ||
3883 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
3884 | kvm_after_handle_nmi(&svm->vcpu); | |
3885 | ||
d7bf8221 JR |
3886 | sync_cr8_to_lapic(vcpu); |
3887 | ||
a2fa3e9f | 3888 | svm->next_rip = 0; |
9222be18 | 3889 | |
38e5e92f JR |
3890 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
3891 | ||
631bc487 GN |
3892 | /* if exit due to PF check for async PF */ |
3893 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3894 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3895 | ||
6de4f3ad AK |
3896 | if (npt_enabled) { |
3897 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3898 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3899 | } | |
fe5913e4 JR |
3900 | |
3901 | /* | |
3902 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3903 | * change the physical cpu | |
3904 | */ | |
3905 | if (unlikely(svm->vmcb->control.exit_code == | |
3906 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3907 | svm_handle_mce(svm); | |
8d28fec4 RJ |
3908 | |
3909 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
3910 | } |
3911 | ||
80e31d4f AK |
3912 | #undef R |
3913 | ||
6aa8b732 AK |
3914 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3915 | { | |
a2fa3e9f GH |
3916 | struct vcpu_svm *svm = to_svm(vcpu); |
3917 | ||
3918 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 3919 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 3920 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
3921 | } |
3922 | ||
1c97f0a0 JR |
3923 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3924 | { | |
3925 | struct vcpu_svm *svm = to_svm(vcpu); | |
3926 | ||
3927 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 3928 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
3929 | |
3930 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 3931 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 3932 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 3933 | |
f40f6a45 | 3934 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
3935 | } |
3936 | ||
6aa8b732 AK |
3937 | static int is_disabled(void) |
3938 | { | |
6031a61c JR |
3939 | u64 vm_cr; |
3940 | ||
3941 | rdmsrl(MSR_VM_CR, vm_cr); | |
3942 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3943 | return 1; | |
3944 | ||
6aa8b732 AK |
3945 | return 0; |
3946 | } | |
3947 | ||
102d8325 IM |
3948 | static void |
3949 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3950 | { | |
3951 | /* | |
3952 | * Patch in the VMMCALL instruction: | |
3953 | */ | |
3954 | hypercall[0] = 0x0f; | |
3955 | hypercall[1] = 0x01; | |
3956 | hypercall[2] = 0xd9; | |
102d8325 IM |
3957 | } |
3958 | ||
002c7f7c YS |
3959 | static void svm_check_processor_compat(void *rtn) |
3960 | { | |
3961 | *(int *)rtn = 0; | |
3962 | } | |
3963 | ||
774ead3a AK |
3964 | static bool svm_cpu_has_accelerated_tpr(void) |
3965 | { | |
3966 | return false; | |
3967 | } | |
3968 | ||
4b12f0de | 3969 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
3970 | { |
3971 | return 0; | |
3972 | } | |
3973 | ||
0e851880 SY |
3974 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
3975 | { | |
3976 | } | |
3977 | ||
d4330ef2 JR |
3978 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
3979 | { | |
c2c63a49 | 3980 | switch (func) { |
4c62a2dc JR |
3981 | case 0x80000001: |
3982 | if (nested) | |
3983 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
3984 | break; | |
c2c63a49 JR |
3985 | case 0x8000000A: |
3986 | entry->eax = 1; /* SVM revision 1 */ | |
3987 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
3988 | ASID emulation to nested SVM */ | |
3989 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
3990 | entry->edx = 0; /* Per default do not support any |
3991 | additional features */ | |
3992 | ||
3993 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 3994 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 3995 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 3996 | |
3d4aeaad JR |
3997 | /* Support NPT for the guest if enabled */ |
3998 | if (npt_enabled) | |
3999 | entry->edx |= SVM_FEATURE_NPT; | |
4000 | ||
c2c63a49 JR |
4001 | break; |
4002 | } | |
d4330ef2 JR |
4003 | } |
4004 | ||
17cc3935 | 4005 | static int svm_get_lpage_level(void) |
344f414f | 4006 | { |
17cc3935 | 4007 | return PT_PDPE_LEVEL; |
344f414f JR |
4008 | } |
4009 | ||
4e47c7a6 SY |
4010 | static bool svm_rdtscp_supported(void) |
4011 | { | |
4012 | return false; | |
4013 | } | |
4014 | ||
f5f48ee1 SY |
4015 | static bool svm_has_wbinvd_exit(void) |
4016 | { | |
4017 | return true; | |
4018 | } | |
4019 | ||
02daab21 AK |
4020 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
4021 | { | |
4022 | struct vcpu_svm *svm = to_svm(vcpu); | |
4023 | ||
18c918c5 | 4024 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 4025 | update_cr0_intercept(svm); |
02daab21 AK |
4026 | } |
4027 | ||
8061252e | 4028 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4029 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 4030 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4031 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 4032 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 4033 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb JR |
4034 | |
4035 | static struct __x86_intercept { | |
4036 | u32 exit_code; | |
4037 | enum x86_intercept_stage stage; | |
cfec82cb JR |
4038 | } x86_intercept_map[] = { |
4039 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
4040 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4041 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4042 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4043 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
4044 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
4045 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
4046 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
4047 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
4048 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
4049 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
4050 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
4051 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
4052 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
4053 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
4054 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
4055 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
4056 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
4057 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
4058 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
4059 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
4060 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
4061 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
4062 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
4063 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
4064 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
4065 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
4066 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
4067 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
4068 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
4069 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
4070 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
4071 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
4072 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
4073 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
4074 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
4075 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
4076 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
4077 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
4078 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
4079 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
4080 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
4081 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
4082 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
4083 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
4084 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
4085 | }; |
4086 | ||
8061252e | 4087 | #undef PRE_EX |
cfec82cb | 4088 | #undef POST_EX |
d7eb8203 | 4089 | #undef POST_MEM |
cfec82cb | 4090 | |
8a76d7f2 JR |
4091 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
4092 | struct x86_instruction_info *info, | |
4093 | enum x86_intercept_stage stage) | |
4094 | { | |
cfec82cb JR |
4095 | struct vcpu_svm *svm = to_svm(vcpu); |
4096 | int vmexit, ret = X86EMUL_CONTINUE; | |
4097 | struct __x86_intercept icpt_info; | |
4098 | struct vmcb *vmcb = svm->vmcb; | |
4099 | ||
4100 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
4101 | goto out; | |
4102 | ||
4103 | icpt_info = x86_intercept_map[info->intercept]; | |
4104 | ||
40e19b51 | 4105 | if (stage != icpt_info.stage) |
cfec82cb JR |
4106 | goto out; |
4107 | ||
4108 | switch (icpt_info.exit_code) { | |
4109 | case SVM_EXIT_READ_CR0: | |
4110 | if (info->intercept == x86_intercept_cr_read) | |
4111 | icpt_info.exit_code += info->modrm_reg; | |
4112 | break; | |
4113 | case SVM_EXIT_WRITE_CR0: { | |
4114 | unsigned long cr0, val; | |
4115 | u64 intercept; | |
4116 | ||
4117 | if (info->intercept == x86_intercept_cr_write) | |
4118 | icpt_info.exit_code += info->modrm_reg; | |
4119 | ||
4120 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0) | |
4121 | break; | |
4122 | ||
4123 | intercept = svm->nested.intercept; | |
4124 | ||
4125 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
4126 | break; | |
4127 | ||
4128 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
4129 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
4130 | ||
4131 | if (info->intercept == x86_intercept_lmsw) { | |
4132 | cr0 &= 0xfUL; | |
4133 | val &= 0xfUL; | |
4134 | /* lmsw can't clear PE - catch this here */ | |
4135 | if (cr0 & X86_CR0_PE) | |
4136 | val |= X86_CR0_PE; | |
4137 | } | |
4138 | ||
4139 | if (cr0 ^ val) | |
4140 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
4141 | ||
4142 | break; | |
4143 | } | |
3b88e41a JR |
4144 | case SVM_EXIT_READ_DR0: |
4145 | case SVM_EXIT_WRITE_DR0: | |
4146 | icpt_info.exit_code += info->modrm_reg; | |
4147 | break; | |
8061252e JR |
4148 | case SVM_EXIT_MSR: |
4149 | if (info->intercept == x86_intercept_wrmsr) | |
4150 | vmcb->control.exit_info_1 = 1; | |
4151 | else | |
4152 | vmcb->control.exit_info_1 = 0; | |
4153 | break; | |
bf608f88 JR |
4154 | case SVM_EXIT_PAUSE: |
4155 | /* | |
4156 | * We get this for NOP only, but pause | |
4157 | * is rep not, check this here | |
4158 | */ | |
4159 | if (info->rep_prefix != REPE_PREFIX) | |
4160 | goto out; | |
f6511935 JR |
4161 | case SVM_EXIT_IOIO: { |
4162 | u64 exit_info; | |
4163 | u32 bytes; | |
4164 | ||
4165 | exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16; | |
4166 | ||
4167 | if (info->intercept == x86_intercept_in || | |
4168 | info->intercept == x86_intercept_ins) { | |
4169 | exit_info |= SVM_IOIO_TYPE_MASK; | |
4170 | bytes = info->src_bytes; | |
4171 | } else { | |
4172 | bytes = info->dst_bytes; | |
4173 | } | |
4174 | ||
4175 | if (info->intercept == x86_intercept_outs || | |
4176 | info->intercept == x86_intercept_ins) | |
4177 | exit_info |= SVM_IOIO_STR_MASK; | |
4178 | ||
4179 | if (info->rep_prefix) | |
4180 | exit_info |= SVM_IOIO_REP_MASK; | |
4181 | ||
4182 | bytes = min(bytes, 4u); | |
4183 | ||
4184 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
4185 | ||
4186 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
4187 | ||
4188 | vmcb->control.exit_info_1 = exit_info; | |
4189 | vmcb->control.exit_info_2 = info->next_rip; | |
4190 | ||
4191 | break; | |
4192 | } | |
cfec82cb JR |
4193 | default: |
4194 | break; | |
4195 | } | |
4196 | ||
4197 | vmcb->control.next_rip = info->next_rip; | |
4198 | vmcb->control.exit_code = icpt_info.exit_code; | |
4199 | vmexit = nested_svm_exit_handled(svm); | |
4200 | ||
4201 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
4202 | : X86EMUL_CONTINUE; | |
4203 | ||
4204 | out: | |
4205 | return ret; | |
8a76d7f2 JR |
4206 | } |
4207 | ||
cbdd1bea | 4208 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
4209 | .cpu_has_kvm_support = has_svm, |
4210 | .disabled_by_bios = is_disabled, | |
4211 | .hardware_setup = svm_hardware_setup, | |
4212 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 4213 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
4214 | .hardware_enable = svm_hardware_enable, |
4215 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 4216 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
4217 | |
4218 | .vcpu_create = svm_create_vcpu, | |
4219 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 4220 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 4221 | |
04d2cc77 | 4222 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
4223 | .vcpu_load = svm_vcpu_load, |
4224 | .vcpu_put = svm_vcpu_put, | |
4225 | ||
4226 | .set_guest_debug = svm_guest_debug, | |
4227 | .get_msr = svm_get_msr, | |
4228 | .set_msr = svm_set_msr, | |
4229 | .get_segment_base = svm_get_segment_base, | |
4230 | .get_segment = svm_get_segment, | |
4231 | .set_segment = svm_set_segment, | |
2e4d2653 | 4232 | .get_cpl = svm_get_cpl, |
1747fb71 | 4233 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 4234 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 4235 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 4236 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 4237 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
4238 | .set_cr3 = svm_set_cr3, |
4239 | .set_cr4 = svm_set_cr4, | |
4240 | .set_efer = svm_set_efer, | |
4241 | .get_idt = svm_get_idt, | |
4242 | .set_idt = svm_set_idt, | |
4243 | .get_gdt = svm_get_gdt, | |
4244 | .set_gdt = svm_set_gdt, | |
020df079 | 4245 | .set_dr7 = svm_set_dr7, |
6de4f3ad | 4246 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
4247 | .get_rflags = svm_get_rflags, |
4248 | .set_rflags = svm_set_rflags, | |
6b52d186 | 4249 | .fpu_activate = svm_fpu_activate, |
02daab21 | 4250 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 4251 | |
6aa8b732 | 4252 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 4253 | |
6aa8b732 | 4254 | .run = svm_vcpu_run, |
04d2cc77 | 4255 | .handle_exit = handle_exit, |
6aa8b732 | 4256 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4257 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
4258 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 4259 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 4260 | .set_irq = svm_set_irq, |
95ba8273 | 4261 | .set_nmi = svm_inject_nmi, |
298101da | 4262 | .queue_exception = svm_queue_exception, |
b463a6f7 | 4263 | .cancel_injection = svm_cancel_injection, |
78646121 | 4264 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 4265 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
4266 | .get_nmi_mask = svm_get_nmi_mask, |
4267 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
4268 | .enable_nmi_window = enable_nmi_window, |
4269 | .enable_irq_window = enable_irq_window, | |
4270 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
4271 | |
4272 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 4273 | .get_tdp_level = get_npt_level, |
4b12f0de | 4274 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 4275 | |
586f9607 | 4276 | .get_exit_info = svm_get_exit_info, |
586f9607 | 4277 | |
17cc3935 | 4278 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
4279 | |
4280 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
4281 | |
4282 | .rdtscp_supported = svm_rdtscp_supported, | |
d4330ef2 JR |
4283 | |
4284 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
4285 | |
4286 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a | 4287 | |
4051b188 | 4288 | .set_tsc_khz = svm_set_tsc_khz, |
99e3e30a | 4289 | .write_tsc_offset = svm_write_tsc_offset, |
e48672fa | 4290 | .adjust_tsc_offset = svm_adjust_tsc_offset, |
857e4099 | 4291 | .compute_tsc_offset = svm_compute_tsc_offset, |
d5c1785d | 4292 | .read_l1_tsc = svm_read_l1_tsc, |
1c97f0a0 JR |
4293 | |
4294 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
4295 | |
4296 | .check_intercept = svm_check_intercept, | |
6aa8b732 AK |
4297 | }; |
4298 | ||
4299 | static int __init svm_init(void) | |
4300 | { | |
cb498ea2 | 4301 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 4302 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
4303 | } |
4304 | ||
4305 | static void __exit svm_exit(void) | |
4306 | { | |
cb498ea2 | 4307 | kvm_exit(); |
6aa8b732 AK |
4308 | } |
4309 | ||
4310 | module_init(svm_init) | |
4311 | module_exit(svm_exit) |