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KVM: MMU: cleanup pte write path
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
443381a8
AL		 72static int __read_mostly yield_on_hlt = 1;
73module_param(yield_on_hlt, bool, S_IRUGO);
74
cdc0e244
AK		 75#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77#define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 80 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 81#define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 83#define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
85 | X86_CR4_OSXMMEXCPT)
86
cdc0e244
AK		 87#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
89
78ac8b47
AK		 90#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
91
4b8d54f9
ZE		 92/*
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 96 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
102 */
00c25bce 103#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 104#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
106module_param(ple_gap, int, S_IRUGO);
107
108static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
109module_param(ple_window, int, S_IRUGO);
110
61d2ef2c
AK		 111#define NR_AUTOLOAD_MSRS 1
112
a2fa3e9f
GH		 113struct vmcs {
114 u32 revision_id;
115 u32 abort;
116 char data[0];
117};
118
26bb0981
AK		 119struct shared_msr_entry {
120 unsigned index;
121 u64 data;
d5696725 122 u64 mask;
26bb0981
AK		 123};
124
a2fa3e9f 125struct vcpu_vmx {
fb3f0f51 126 struct kvm_vcpu vcpu;
543e4243 127 struct list_head local_vcpus_link;
313dbd49 128 unsigned long host_rsp;
a2fa3e9f 129 int launched;
29bd8a78 130 u8 fail;
51aa01d1 131 u32 exit_intr_info;
1155f76a 132 u32 idt_vectoring_info;
26bb0981 133 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 134 int nmsrs;
135 int save_nmsrs;
a2fa3e9f 136#ifdef CONFIG_X86_64
44ea2b17
AK		 137 u64 msr_host_kernel_gs_base;
138 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 139#endif
140 struct vmcs *vmcs;
61d2ef2c
AK		 141 struct msr_autoload {
142 unsigned nr;
143 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
144 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
145 } msr_autoload;
a2fa3e9f
GH		 146 struct {
147 int loaded;
148 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 149 int gs_ldt_reload_needed;
150 int fs_reload_needed;
d77c26fc 151 } host_state;
9c8cba37 152 struct {
7ffd92c5 153 int vm86_active;
78ac8b47 154 ulong save_rflags;
7ffd92c5
AK		 155 struct kvm_save_segment {
156 u16 selector;
157 unsigned long base;
158 u32 limit;
159 u32 ar;
160 } tr, es, ds, fs, gs;
9c8cba37 161 } rmode;
2384d2b3 162 int vpid;
04fa4d32 163 bool emulation_required;
3b86cd99
JK		 164
165 /* Support for vnmi-less CPUs */
166 int soft_vnmi_blocked;
167 ktime_t entry_time;
168 s64 vnmi_blocked_time;
a0861c02 169 u32 exit_reason;
4e47c7a6
SY		 170
171 bool rdtscp_enabled;
a2fa3e9f
GH		 172};
173
174static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
175{
fb3f0f51 176 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 177}
178
4e1096d2 179static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 180static void kvm_cpu_vmxon(u64 addr);
181static void kvm_cpu_vmxoff(void);
aff48baa 182static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
75880a01 183
6aa8b732
AK		 184static DEFINE_PER_CPU(struct vmcs *, vmxarea);
185static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 186static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
3444d7da 187static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 188
3e7c73e9
AK		 189static unsigned long *vmx_io_bitmap_a;
190static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 191static unsigned long *vmx_msr_bitmap_legacy;
192static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 193
110312c8
AK		 194static bool cpu_has_load_ia32_efer;
195
2384d2b3
SY		 196static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
197static DEFINE_SPINLOCK(vmx_vpid_lock);
198
1c3d14fe 199static struct vmcs_config {
6aa8b732
AK		 200 int size;
201 int order;
202 u32 revision_id;
1c3d14fe
YS		 203 u32 pin_based_exec_ctrl;
204 u32 cpu_based_exec_ctrl;
f78e0e2e 205 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 206 u32 vmexit_ctrl;
207 u32 vmentry_ctrl;
208} vmcs_config;
6aa8b732 209
efff9e53 210static struct vmx_capability {
d56f546d
SY		 211 u32 ept;
212 u32 vpid;
213} vmx_capability;
214
6aa8b732
AK		 215#define VMX_SEGMENT_FIELD(seg) \
216 [VCPU_SREG_##seg] = { \
217 .selector = GUEST_##seg##_SELECTOR, \
218 .base = GUEST_##seg##_BASE, \
219 .limit = GUEST_##seg##_LIMIT, \
220 .ar_bytes = GUEST_##seg##_AR_BYTES, \
221 }
222
223static struct kvm_vmx_segment_field {
224 unsigned selector;
225 unsigned base;
226 unsigned limit;
227 unsigned ar_bytes;
228} kvm_vmx_segment_fields[] = {
229 VMX_SEGMENT_FIELD(CS),
230 VMX_SEGMENT_FIELD(DS),
231 VMX_SEGMENT_FIELD(ES),
232 VMX_SEGMENT_FIELD(FS),
233 VMX_SEGMENT_FIELD(GS),
234 VMX_SEGMENT_FIELD(SS),
235 VMX_SEGMENT_FIELD(TR),
236 VMX_SEGMENT_FIELD(LDTR),
237};
238
26bb0981
AK		 239static u64 host_efer;
240
6de4f3ad
AK		 241static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
242
4d56c8a7 243/*
8c06585d 244 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 245 * away by decrementing the array size.
246 */
6aa8b732 247static const u32 vmx_msr_index[] = {
05b3e0c2 248#ifdef CONFIG_X86_64
44ea2b17 249 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 250#endif
8c06585d 251 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 252};
9d8f549d 253#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 254
31299944 255static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 256{
257 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
258 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 259 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 260}
261
31299944 262static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 263{
264 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
265 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 266 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 267}
268
31299944 269static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 270{
271 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
272 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 273 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 274}
275
31299944 276static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 277{
278 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
279 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
280}
281
31299944 282static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 283{
284 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
285 INTR_INFO_VALID_MASK)) ==
286 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
287}
288
31299944 289static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 290{
04547156 291 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 292}
293
31299944 294static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 295{
04547156 296 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 297}
298
31299944 299static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 300{
04547156 301 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 302}
303
31299944 304static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 305{
04547156
SY		 306 return vmcs_config.cpu_based_exec_ctrl &
307 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 308}
309
774ead3a 310static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 311{
04547156
SY		 312 return vmcs_config.cpu_based_2nd_exec_ctrl &
313 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
314}
315
316static inline bool cpu_has_vmx_flexpriority(void)
317{
318 return cpu_has_vmx_tpr_shadow() &&
319 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 320}
321
e799794e
MT		 322static inline bool cpu_has_vmx_ept_execute_only(void)
323{
31299944 324 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 325}
326
327static inline bool cpu_has_vmx_eptp_uncacheable(void)
328{
31299944 329 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 330}
331
332static inline bool cpu_has_vmx_eptp_writeback(void)
333{
31299944 334 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 335}
336
337static inline bool cpu_has_vmx_ept_2m_page(void)
338{
31299944 339 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 340}
341
878403b7
SY		 342static inline bool cpu_has_vmx_ept_1g_page(void)
343{
31299944 344 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 345}
346
4bc9b982
SY		 347static inline bool cpu_has_vmx_ept_4levels(void)
348{
349 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
350}
351
31299944 352static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 353{
31299944 354 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 355}
356
31299944 357static inline bool cpu_has_vmx_invept_context(void)
d56f546d 358{
31299944 359 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 360}
361
31299944 362static inline bool cpu_has_vmx_invept_global(void)
d56f546d 363{
31299944 364 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 365}
366
518c8aee
GJ		 367static inline bool cpu_has_vmx_invvpid_single(void)
368{
369 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
370}
371
b9d762fa
GJ		 372static inline bool cpu_has_vmx_invvpid_global(void)
373{
374 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
375}
376
31299944 377static inline bool cpu_has_vmx_ept(void)
d56f546d 378{
04547156
SY		 379 return vmcs_config.cpu_based_2nd_exec_ctrl &
380 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 381}
382
31299944 383static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 384{
385 return vmcs_config.cpu_based_2nd_exec_ctrl &
386 SECONDARY_EXEC_UNRESTRICTED_GUEST;
387}
388
31299944 389static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 390{
391 return vmcs_config.cpu_based_2nd_exec_ctrl &
392 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
393}
394
31299944 395static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 396{
6d3e435e 397 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 398}
399
31299944 400static inline bool cpu_has_vmx_vpid(void)
2384d2b3 401{
04547156
SY		 402 return vmcs_config.cpu_based_2nd_exec_ctrl &
403 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 404}
405
31299944 406static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 407{
408 return vmcs_config.cpu_based_2nd_exec_ctrl &
409 SECONDARY_EXEC_RDTSCP;
410}
411
31299944 412static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 413{
414 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
415}
416
f5f48ee1
SY		 417static inline bool cpu_has_vmx_wbinvd_exit(void)
418{
419 return vmcs_config.cpu_based_2nd_exec_ctrl &
420 SECONDARY_EXEC_WBINVD_EXITING;
421}
422
04547156
SY		 423static inline bool report_flexpriority(void)
424{
425 return flexpriority_enabled;
426}
427
8b9cf98c 428static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 429{
430 int i;
431
a2fa3e9f 432 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 433 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 434 return i;
435 return -1;
436}
437
2384d2b3
SY		 438static inline void __invvpid(int ext, u16 vpid, gva_t gva)
439{
440 struct {
441 u64 vpid : 16;
442 u64 rsvd : 48;
443 u64 gva;
444 } operand = { vpid, 0, gva };
445
4ecac3fd 446 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 447 /* CF==1 or ZF==1 --> rc = -1 */
448 "; ja 1f ; ud2 ; 1:"
449 : : "a"(&operand), "c"(ext) : "cc", "memory");
450}
451
1439442c
SY		 452static inline void __invept(int ext, u64 eptp, gpa_t gpa)
453{
454 struct {
455 u64 eptp, gpa;
456 } operand = {eptp, gpa};
457
4ecac3fd 458 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 459 /* CF==1 or ZF==1 --> rc = -1 */
460 "; ja 1f ; ud2 ; 1:\n"
461 : : "a" (&operand), "c" (ext) : "cc", "memory");
462}
463
26bb0981 464static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 465{
466 int i;
467
8b9cf98c 468 i = __find_msr_index(vmx, msr);
a75beee6 469 if (i >= 0)
a2fa3e9f 470 return &vmx->guest_msrs[i];
8b6d44c7 471 return NULL;
7725f0ba
AK		 472}
473
6aa8b732
AK		 474static void vmcs_clear(struct vmcs *vmcs)
475{
476 u64 phys_addr = __pa(vmcs);
477 u8 error;
478
4ecac3fd 479 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 480 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 481 : "cc", "memory");
482 if (error)
483 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
484 vmcs, phys_addr);
485}
486
7725b894
DX		 487static void vmcs_load(struct vmcs *vmcs)
488{
489 u64 phys_addr = __pa(vmcs);
490 u8 error;
491
492 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 493 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 494 : "cc", "memory");
495 if (error)
496 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
497 vmcs, phys_addr);
498}
499
6aa8b732
AK		 500static void __vcpu_clear(void *arg)
501{
8b9cf98c 502 struct vcpu_vmx *vmx = arg;
d3b2c338 503 int cpu = raw_smp_processor_id();
6aa8b732 504
8b9cf98c 505 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 506 vmcs_clear(vmx->vmcs);
507 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 508 per_cpu(current_vmcs, cpu) = NULL;
543e4243
AK		 509 list_del(&vmx->local_vcpus_link);
510 vmx->vcpu.cpu = -1;
511 vmx->launched = 0;
6aa8b732
AK		 512}
513
8b9cf98c 514static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 515{
eae5ecb5
AK		 516 if (vmx->vcpu.cpu == -1)
517 return;
8691e5a8 518 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 519}
520
1760dd49 521static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 522{
523 if (vmx->vpid == 0)
524 return;
525
518c8aee
GJ		 526 if (cpu_has_vmx_invvpid_single())
527 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 528}
529
b9d762fa
GJ		 530static inline void vpid_sync_vcpu_global(void)
531{
532 if (cpu_has_vmx_invvpid_global())
533 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
534}
535
536static inline void vpid_sync_context(struct vcpu_vmx *vmx)
537{
538 if (cpu_has_vmx_invvpid_single())
1760dd49 539 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 540 else
541 vpid_sync_vcpu_global();
542}
543
1439442c
SY		 544static inline void ept_sync_global(void)
545{
546 if (cpu_has_vmx_invept_global())
547 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
548}
549
550static inline void ept_sync_context(u64 eptp)
551{
089d034e 552 if (enable_ept) {
1439442c
SY		 553 if (cpu_has_vmx_invept_context())
554 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
555 else
556 ept_sync_global();
557 }
558}
559
560static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
561{
089d034e 562 if (enable_ept) {
1439442c
SY		 563 if (cpu_has_vmx_invept_individual_addr())
564 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
565 eptp, gpa);
566 else
567 ept_sync_context(eptp);
568 }
569}
570
6aa8b732
AK		 571static unsigned long vmcs_readl(unsigned long field)
572{
a295673a 573 unsigned long value = 0;
6aa8b732 574
4ecac3fd 575 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
a295673a 576 : "+a"(value) : "d"(field) : "cc");
6aa8b732
AK		 577 return value;
578}
579
580static u16 vmcs_read16(unsigned long field)
581{
582 return vmcs_readl(field);
583}
584
585static u32 vmcs_read32(unsigned long field)
586{
587 return vmcs_readl(field);
588}
589
590static u64 vmcs_read64(unsigned long field)
591{
05b3e0c2 592#ifdef CONFIG_X86_64
6aa8b732
AK		 593 return vmcs_readl(field);
594#else
595 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
596#endif
597}
598
e52de1b8
AK		 599static noinline void vmwrite_error(unsigned long field, unsigned long value)
600{
601 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
602 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
603 dump_stack();
604}
605
6aa8b732
AK		 606static void vmcs_writel(unsigned long field, unsigned long value)
607{
608 u8 error;
609
4ecac3fd 610 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 611 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 612 if (unlikely(error))
613 vmwrite_error(field, value);
6aa8b732
AK		 614}
615
616static void vmcs_write16(unsigned long field, u16 value)
617{
618 vmcs_writel(field, value);
619}
620
621static void vmcs_write32(unsigned long field, u32 value)
622{
623 vmcs_writel(field, value);
624}
625
626static void vmcs_write64(unsigned long field, u64 value)
627{
6aa8b732 628 vmcs_writel(field, value);
7682f2d0 629#ifndef CONFIG_X86_64
6aa8b732
AK		 630 asm volatile ("");
631 vmcs_writel(field+1, value >> 32);
632#endif
633}
634
2ab455cc
AL		 635static void vmcs_clear_bits(unsigned long field, u32 mask)
636{
637 vmcs_writel(field, vmcs_readl(field) & ~mask);
638}
639
640static void vmcs_set_bits(unsigned long field, u32 mask)
641{
642 vmcs_writel(field, vmcs_readl(field) | mask);
643}
644
abd3f2d6
AK		 645static void update_exception_bitmap(struct kvm_vcpu *vcpu)
646{
647 u32 eb;
648
fd7373cc
JK		 649 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
650 (1u << NM_VECTOR) | (1u << DB_VECTOR);
651 if ((vcpu->guest_debug &
652 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
653 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
654 eb |= 1u << BP_VECTOR;
7ffd92c5 655 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 656 eb = ~0;
089d034e 657 if (enable_ept)
1439442c 658 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 659 if (vcpu->fpu_active)
660 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 661 vmcs_write32(EXCEPTION_BITMAP, eb);
662}
663
61d2ef2c
AK		 664static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
665{
666 unsigned i;
667 struct msr_autoload *m = &vmx->msr_autoload;
668
110312c8
AK		 669 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
670 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
671 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
672 return;
673 }
674
61d2ef2c
AK		 675 for (i = 0; i < m->nr; ++i)
676 if (m->guest[i].index == msr)
677 break;
678
679 if (i == m->nr)
680 return;
681 --m->nr;
682 m->guest[i] = m->guest[m->nr];
683 m->host[i] = m->host[m->nr];
684 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
685 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
686}
687
688static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
689 u64 guest_val, u64 host_val)
690{
691 unsigned i;
692 struct msr_autoload *m = &vmx->msr_autoload;
693
110312c8
AK		 694 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
695 vmcs_write64(GUEST_IA32_EFER, guest_val);
696 vmcs_write64(HOST_IA32_EFER, host_val);
697 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
698 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
699 return;
700 }
701
61d2ef2c
AK		 702 for (i = 0; i < m->nr; ++i)
703 if (m->guest[i].index == msr)
704 break;
705
706 if (i == m->nr) {
707 ++m->nr;
708 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
709 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
710 }
711
712 m->guest[i].index = msr;
713 m->guest[i].value = guest_val;
714 m->host[i].index = msr;
715 m->host[i].value = host_val;
716}
717
33ed6329
AK		 718static void reload_tss(void)
719{
33ed6329
AK		 720 /*
721 * VT restores TR but not its size. Useless.
722 */
d359192f 723 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 724 struct desc_struct *descs;
33ed6329 725
d359192f 726 descs = (void *)gdt->address;
33ed6329
AK		 727 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
728 load_TR_desc();
33ed6329
AK		 729}
730
92c0d900 731static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 732{
3a34a881 733 u64 guest_efer;
51c6cf66
AK		 734 u64 ignore_bits;
735
f6801dff 736 guest_efer = vmx->vcpu.arch.efer;
3a34a881 737
51c6cf66
AK		 738 /*
739 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
740 * outside long mode
741 */
742 ignore_bits = EFER_NX | EFER_SCE;
743#ifdef CONFIG_X86_64
744 ignore_bits |= EFER_LMA | EFER_LME;
745 /* SCE is meaningful only in long mode on Intel */
746 if (guest_efer & EFER_LMA)
747 ignore_bits &= ~(u64)EFER_SCE;
748#endif
51c6cf66
AK		 749 guest_efer &= ~ignore_bits;
750 guest_efer |= host_efer & ignore_bits;
26bb0981 751 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 752 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 753
754 clear_atomic_switch_msr(vmx, MSR_EFER);
755 /* On ept, can't emulate nx, and must switch nx atomically */
756 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
757 guest_efer = vmx->vcpu.arch.efer;
758 if (!(guest_efer & EFER_LMA))
759 guest_efer &= ~EFER_LME;
760 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
761 return false;
762 }
763
26bb0981 764 return true;
51c6cf66
AK		 765}
766
2d49ec72
GN		 767static unsigned long segment_base(u16 selector)
768{
d359192f 769 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 770 struct desc_struct *d;
771 unsigned long table_base;
772 unsigned long v;
773
774 if (!(selector & ~3))
775 return 0;
776
d359192f 777 table_base = gdt->address;
2d49ec72
GN		 778
779 if (selector & 4) { /* from ldt */
780 u16 ldt_selector = kvm_read_ldt();
781
782 if (!(ldt_selector & ~3))
783 return 0;
784
785 table_base = segment_base(ldt_selector);
786 }
787 d = (struct desc_struct *)(table_base + (selector & ~7));
788 v = get_desc_base(d);
789#ifdef CONFIG_X86_64
790 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
791 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
792#endif
793 return v;
794}
795
796static inline unsigned long kvm_read_tr_base(void)
797{
798 u16 tr;
799 asm("str %0" : "=g"(tr));
800 return segment_base(tr);
801}
802
04d2cc77 803static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 804{
04d2cc77 805 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 806 int i;
04d2cc77 807
a2fa3e9f 808 if (vmx->host_state.loaded)
33ed6329
AK		 809 return;
810
a2fa3e9f 811 vmx->host_state.loaded = 1;
33ed6329
AK		 812 /*
813 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
814 * allow segment selectors with cpl > 0 or ti == 1.
815 */
d6e88aec 816 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 817 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 818 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 819 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 820 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 821 vmx->host_state.fs_reload_needed = 0;
822 } else {
33ed6329 823 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 824 vmx->host_state.fs_reload_needed = 1;
33ed6329 825 }
9581d442 826 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 827 if (!(vmx->host_state.gs_sel & 7))
828 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 829 else {
830 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 831 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 832 }
833
834#ifdef CONFIG_X86_64
835 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
836 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
837#else
a2fa3e9f
GH		 838 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
839 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 840#endif
707c0874
AK		 841
842#ifdef CONFIG_X86_64
c8770e7b
AK		 843 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
844 if (is_long_mode(&vmx->vcpu))
44ea2b17 845 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 846#endif
26bb0981
AK		 847 for (i = 0; i < vmx->save_nmsrs; ++i)
848 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 849 vmx->guest_msrs[i].data,
850 vmx->guest_msrs[i].mask);
33ed6329
AK		 851}
852
a9b21b62 853static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 854{
a2fa3e9f 855 if (!vmx->host_state.loaded)
33ed6329
AK		 856 return;
857
e1beb1d3 858 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 859 vmx->host_state.loaded = 0;
c8770e7b
AK		 860#ifdef CONFIG_X86_64
861 if (is_long_mode(&vmx->vcpu))
862 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
863#endif
152d3f2f 864 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 865 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 866#ifdef CONFIG_X86_64
9581d442 867 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 868#else
869 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 870#endif
33ed6329 871 }
0a77fe4c
AK		 872 if (vmx->host_state.fs_reload_needed)
873 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 874 reload_tss();
44ea2b17 875#ifdef CONFIG_X86_64
c8770e7b 876 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 877#endif
1c11e713
AK		 878 if (current_thread_info()->status & TS_USEDFPU)
879 clts();
3444d7da 880 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 881}
882
a9b21b62
AK		 883static void vmx_load_host_state(struct vcpu_vmx *vmx)
884{
885 preempt_disable();
886 __vmx_load_host_state(vmx);
887 preempt_enable();
888}
889
6aa8b732
AK		 890/*
891 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
892 * vcpu mutex is already taken.
893 */
15ad7146 894static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 895{
a2fa3e9f 896 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 897 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 898
4610c9cc
DX		 899 if (!vmm_exclusive)
900 kvm_cpu_vmxon(phys_addr);
901 else if (vcpu->cpu != cpu)
8b9cf98c 902 vcpu_clear(vmx);
6aa8b732 903
a2fa3e9f 904 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 905 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 906 vmcs_load(vmx->vmcs);
6aa8b732
AK		 907 }
908
909 if (vcpu->cpu != cpu) {
d359192f 910 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 911 unsigned long sysenter_esp;
912
a8eeb04a 913 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be
DX		 914 local_irq_disable();
915 list_add(&vmx->local_vcpus_link,
916 &per_cpu(vcpus_on_cpu, cpu));
917 local_irq_enable();
918
6aa8b732
AK		 919 /*
920 * Linux uses per-cpu TSS and GDT, so set these when switching
921 * processors.
922 */
d6e88aec 923 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 924 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 925
926 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
927 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
928 }
6aa8b732
AK		 929}
930
931static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
932{
a9b21b62 933 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 934 if (!vmm_exclusive) {
b923e62e 935 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 936 kvm_cpu_vmxoff();
937 }
6aa8b732
AK		 938}
939
5fd86fcf
AK		 940static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
941{
81231c69
AK		 942 ulong cr0;
943
5fd86fcf
AK		 944 if (vcpu->fpu_active)
945 return;
946 vcpu->fpu_active = 1;
81231c69
AK		 947 cr0 = vmcs_readl(GUEST_CR0);
948 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
949 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
950 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 951 update_exception_bitmap(vcpu);
edcafe3c
AK		 952 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
953 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 954}
955
edcafe3c
AK		 956static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
957
5fd86fcf
AK		 958static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
959{
edcafe3c 960 vmx_decache_cr0_guest_bits(vcpu);
81231c69 961 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 962 update_exception_bitmap(vcpu);
edcafe3c
AK		 963 vcpu->arch.cr0_guest_owned_bits = 0;
964 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
965 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 966}
967
6aa8b732
AK		 968static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
969{
78ac8b47 970 unsigned long rflags, save_rflags;
345dcaa8
AK		 971
972 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 973 if (to_vmx(vcpu)->rmode.vm86_active) {
974 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
975 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
976 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
977 }
345dcaa8 978 return rflags;
6aa8b732
AK		 979}
980
981static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
982{
78ac8b47
AK		 983 if (to_vmx(vcpu)->rmode.vm86_active) {
984 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 985 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 986 }
6aa8b732
AK		 987 vmcs_writel(GUEST_RFLAGS, rflags);
988}
989
2809f5d2
GC		 990static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
991{
992 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
993 int ret = 0;
994
995 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 996 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 997 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 998 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 999
1000 return ret & mask;
1001}
1002
1003static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1004{
1005 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1006 u32 interruptibility = interruptibility_old;
1007
1008 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1009
48005f64 1010 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1011 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1012 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1013 interruptibility |= GUEST_INTR_STATE_STI;
1014
1015 if ((interruptibility != interruptibility_old))
1016 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1017}
1018
6aa8b732
AK		 1019static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1020{
1021 unsigned long rip;
6aa8b732 1022
5fdbf976 1023 rip = kvm_rip_read(vcpu);
6aa8b732 1024 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1025 kvm_rip_write(vcpu, rip);
6aa8b732 1026
2809f5d2
GC		 1027 /* skipping an emulated instruction also counts */
1028 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1029}
1030
443381a8
AL		 1031static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1032{
1033 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1034 * explicitly skip the instruction because if the HLT state is set, then
1035 * the instruction is already executing and RIP has already been
1036 * advanced. */
1037 if (!yield_on_hlt &&
1038 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1039 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1040}
1041
298101da 1042static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1043 bool has_error_code, u32 error_code,
1044 bool reinject)
298101da 1045{
77ab6db0 1046 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1047 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1048
8ab2d2e2 1049 if (has_error_code) {
77ab6db0 1050 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1051 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1052 }
77ab6db0 1053
7ffd92c5 1054 if (vmx->rmode.vm86_active) {
a92601bb
MG		 1055 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1056 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1057 return;
1058 }
1059
66fd3f7f
GN		 1060 if (kvm_exception_is_soft(nr)) {
1061 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1062 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1063 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1064 } else
1065 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1066
1067 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1068 vmx_clear_hlt(vcpu);
298101da
AK		 1069}
1070
4e47c7a6
SY		 1071static bool vmx_rdtscp_supported(void)
1072{
1073 return cpu_has_vmx_rdtscp();
1074}
1075
a75beee6
ED		 1076/*
1077 * Swap MSR entry in host/guest MSR entry array.
1078 */
8b9cf98c 1079static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1080{
26bb0981 1081 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1082
1083 tmp = vmx->guest_msrs[to];
1084 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1085 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1086}
1087
e38aea3e
AK		 1088/*
1089 * Set up the vmcs to automatically save and restore system
1090 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1091 * mode, as fiddling with msrs is very expensive.
1092 */
8b9cf98c 1093static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1094{
26bb0981 1095 int save_nmsrs, index;
5897297b 1096 unsigned long *msr_bitmap;
e38aea3e 1097
33f9c505 1098 vmx_load_host_state(vmx);
a75beee6
ED		 1099 save_nmsrs = 0;
1100#ifdef CONFIG_X86_64
8b9cf98c 1101 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1102 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1103 if (index >= 0)
8b9cf98c
RR		 1104 move_msr_up(vmx, index, save_nmsrs++);
1105 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1106 if (index >= 0)
8b9cf98c
RR		 1107 move_msr_up(vmx, index, save_nmsrs++);
1108 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1109 if (index >= 0)
8b9cf98c 1110 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1111 index = __find_msr_index(vmx, MSR_TSC_AUX);
1112 if (index >= 0 && vmx->rdtscp_enabled)
1113 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1114 /*
8c06585d 1115 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1116 * if efer.sce is enabled.
1117 */
8c06585d 1118 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1119 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1120 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1121 }
1122#endif
92c0d900
AK		 1123 index = __find_msr_index(vmx, MSR_EFER);
1124 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1125 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1126
26bb0981 1127 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1128
1129 if (cpu_has_vmx_msr_bitmap()) {
1130 if (is_long_mode(&vmx->vcpu))
1131 msr_bitmap = vmx_msr_bitmap_longmode;
1132 else
1133 msr_bitmap = vmx_msr_bitmap_legacy;
1134
1135 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1136 }
e38aea3e
AK		 1137}
1138
6aa8b732
AK		 1139/*
1140 * reads and returns guest's timestamp counter "register"
1141 * guest_tsc = host_tsc + tsc_offset -- 21.3
1142 */
1143static u64 guest_read_tsc(void)
1144{
1145 u64 host_tsc, tsc_offset;
1146
1147 rdtscll(host_tsc);
1148 tsc_offset = vmcs_read64(TSC_OFFSET);
1149 return host_tsc + tsc_offset;
1150}
1151
1152/*
99e3e30a 1153 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1154 */
99e3e30a 1155static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1156{
f4e1b3c8 1157 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1158}
1159
e48672fa
ZA		 1160static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1161{
1162 u64 offset = vmcs_read64(TSC_OFFSET);
1163 vmcs_write64(TSC_OFFSET, offset + adjustment);
1164}
1165
6aa8b732
AK		 1166/*
1167 * Reads an msr value (of 'msr_index') into 'pdata'.
1168 * Returns 0 on success, non-0 otherwise.
1169 * Assumes vcpu_load() was already called.
1170 */
1171static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1172{
1173 u64 data;
26bb0981 1174 struct shared_msr_entry *msr;
6aa8b732
AK		 1175
1176 if (!pdata) {
1177 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1178 return -EINVAL;
1179 }
1180
1181 switch (msr_index) {
05b3e0c2 1182#ifdef CONFIG_X86_64
6aa8b732
AK		 1183 case MSR_FS_BASE:
1184 data = vmcs_readl(GUEST_FS_BASE);
1185 break;
1186 case MSR_GS_BASE:
1187 data = vmcs_readl(GUEST_GS_BASE);
1188 break;
44ea2b17
AK		 1189 case MSR_KERNEL_GS_BASE:
1190 vmx_load_host_state(to_vmx(vcpu));
1191 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1192 break;
26bb0981 1193#endif
6aa8b732 1194 case MSR_EFER:
3bab1f5d 1195 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1196 case MSR_IA32_TSC:
6aa8b732
AK		 1197 data = guest_read_tsc();
1198 break;
1199 case MSR_IA32_SYSENTER_CS:
1200 data = vmcs_read32(GUEST_SYSENTER_CS);
1201 break;
1202 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1203 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1204 break;
1205 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1206 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1207 break;
4e47c7a6
SY		 1208 case MSR_TSC_AUX:
1209 if (!to_vmx(vcpu)->rdtscp_enabled)
1210 return 1;
1211 /* Otherwise falls through */
6aa8b732 1212 default:
26bb0981 1213 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1214 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1215 if (msr) {
542423b0 1216 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1217 data = msr->data;
1218 break;
6aa8b732 1219 }
3bab1f5d 1220 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1221 }
1222
1223 *pdata = data;
1224 return 0;
1225}
1226
1227/*
1228 * Writes msr value into into the appropriate "register".
1229 * Returns 0 on success, non-0 otherwise.
1230 * Assumes vcpu_load() was already called.
1231 */
1232static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1233{
a2fa3e9f 1234 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1235 struct shared_msr_entry *msr;
2cc51560
ED		 1236 int ret = 0;
1237
6aa8b732 1238 switch (msr_index) {
3bab1f5d 1239 case MSR_EFER:
a9b21b62 1240 vmx_load_host_state(vmx);
2cc51560 1241 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1242 break;
16175a79 1243#ifdef CONFIG_X86_64
6aa8b732
AK		 1244 case MSR_FS_BASE:
1245 vmcs_writel(GUEST_FS_BASE, data);
1246 break;
1247 case MSR_GS_BASE:
1248 vmcs_writel(GUEST_GS_BASE, data);
1249 break;
44ea2b17
AK		 1250 case MSR_KERNEL_GS_BASE:
1251 vmx_load_host_state(vmx);
1252 vmx->msr_guest_kernel_gs_base = data;
1253 break;
6aa8b732
AK		 1254#endif
1255 case MSR_IA32_SYSENTER_CS:
1256 vmcs_write32(GUEST_SYSENTER_CS, data);
1257 break;
1258 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1259 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1260 break;
1261 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1262 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1263 break;
af24a4e4 1264 case MSR_IA32_TSC:
99e3e30a 1265 kvm_write_tsc(vcpu, data);
6aa8b732 1266 break;
468d472f
SY		 1267 case MSR_IA32_CR_PAT:
1268 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1269 vmcs_write64(GUEST_IA32_PAT, data);
1270 vcpu->arch.pat = data;
1271 break;
1272 }
4e47c7a6
SY		 1273 ret = kvm_set_msr_common(vcpu, msr_index, data);
1274 break;
1275 case MSR_TSC_AUX:
1276 if (!vmx->rdtscp_enabled)
1277 return 1;
1278 /* Check reserved bit, higher 32 bits should be zero */
1279 if ((data >> 32) != 0)
1280 return 1;
1281 /* Otherwise falls through */
6aa8b732 1282 default:
8b9cf98c 1283 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1284 if (msr) {
542423b0 1285 vmx_load_host_state(vmx);
3bab1f5d
AK		 1286 msr->data = data;
1287 break;
6aa8b732 1288 }
2cc51560 1289 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1290 }
1291
2cc51560 1292 return ret;
6aa8b732
AK		 1293}
1294
5fdbf976 1295static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1296{
5fdbf976
MT		 1297 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1298 switch (reg) {
1299 case VCPU_REGS_RSP:
1300 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1301 break;
1302 case VCPU_REGS_RIP:
1303 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1304 break;
6de4f3ad
AK		 1305 case VCPU_EXREG_PDPTR:
1306 if (enable_ept)
1307 ept_save_pdptrs(vcpu);
1308 break;
5fdbf976
MT		 1309 default:
1310 break;
1311 }
6aa8b732
AK		 1312}
1313
355be0b9 1314static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1315{
ae675ef0
JK		 1316 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1317 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1318 else
1319 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1320
abd3f2d6 1321 update_exception_bitmap(vcpu);
6aa8b732
AK		 1322}
1323
1324static __init int cpu_has_kvm_support(void)
1325{
6210e37b 1326 return cpu_has_vmx();
6aa8b732
AK		 1327}
1328
1329static __init int vmx_disabled_by_bios(void)
1330{
1331 u64 msr;
1332
1333 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 1334 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 1335 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 1336 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1337 && tboot_enabled())
1338 return 1;
23f3e991 1339 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 1340 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 1341 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 1342 && !tboot_enabled()) {
1343 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 1344 "activate TXT before enabling KVM\n");
cafd6659 1345 return 1;
f9335afe 1346 }
23f3e991
JC		 1347 /* launched w/o TXT and VMX disabled */
1348 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1349 && !tboot_enabled())
1350 return 1;
cafd6659
SW		 1351 }
1352
1353 return 0;
6aa8b732
AK		 1354}
1355
7725b894
DX		 1356static void kvm_cpu_vmxon(u64 addr)
1357{
1358 asm volatile (ASM_VMX_VMXON_RAX
1359 : : "a"(&addr), "m"(addr)
1360 : "memory", "cc");
1361}
1362
10474ae8 1363static int hardware_enable(void *garbage)
6aa8b732
AK		 1364{
1365 int cpu = raw_smp_processor_id();
1366 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1367 u64 old, test_bits;
6aa8b732 1368
10474ae8
AG		 1369 if (read_cr4() & X86_CR4_VMXE)
1370 return -EBUSY;
1371
543e4243 1372 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1373 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1374
1375 test_bits = FEATURE_CONTROL_LOCKED;
1376 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1377 if (tboot_enabled())
1378 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1379
1380 if ((old & test_bits) != test_bits) {
6aa8b732 1381 /* enable and lock */
cafd6659
SW		 1382 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1383 }
66aee91a 1384 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1385
4610c9cc
DX		 1386 if (vmm_exclusive) {
1387 kvm_cpu_vmxon(phys_addr);
1388 ept_sync_global();
1389 }
10474ae8 1390
3444d7da
AK		 1391 store_gdt(&__get_cpu_var(host_gdt));
1392
10474ae8 1393 return 0;
6aa8b732
AK		 1394}
1395
543e4243
AK		 1396static void vmclear_local_vcpus(void)
1397{
1398 int cpu = raw_smp_processor_id();
1399 struct vcpu_vmx *vmx, *n;
1400
1401 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1402 local_vcpus_link)
1403 __vcpu_clear(vmx);
1404}
1405
710ff4a8
EH		 1406
1407/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1408 * tricks.
1409 */
1410static void kvm_cpu_vmxoff(void)
6aa8b732 1411{
4ecac3fd 1412 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1413}
1414
710ff4a8
EH		 1415static void hardware_disable(void *garbage)
1416{
4610c9cc
DX		 1417 if (vmm_exclusive) {
1418 vmclear_local_vcpus();
1419 kvm_cpu_vmxoff();
1420 }
7725b894 1421 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1422}
1423
1c3d14fe 1424static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1425 u32 msr, u32 *result)
1c3d14fe
YS		 1426{
1427 u32 vmx_msr_low, vmx_msr_high;
1428 u32 ctl = ctl_min | ctl_opt;
1429
1430 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1431
1432 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1433 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1434
1435 /* Ensure minimum (required) set of control bits are supported. */
1436 if (ctl_min & ~ctl)
002c7f7c 1437 return -EIO;
1c3d14fe
YS		 1438
1439 *result = ctl;
1440 return 0;
1441}
1442
110312c8
AK		 1443static __init bool allow_1_setting(u32 msr, u32 ctl)
1444{
1445 u32 vmx_msr_low, vmx_msr_high;
1446
1447 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1448 return vmx_msr_high & ctl;
1449}
1450
002c7f7c 1451static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1452{
1453 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1454 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1455 u32 _pin_based_exec_control = 0;
1456 u32 _cpu_based_exec_control = 0;
f78e0e2e 1457 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1458 u32 _vmexit_control = 0;
1459 u32 _vmentry_control = 0;
1460
1461 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1462 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1463 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1464 &_pin_based_exec_control) < 0)
002c7f7c 1465 return -EIO;
1c3d14fe 1466
443381a8 1467 min =
1c3d14fe
YS		 1468#ifdef CONFIG_X86_64
1469 CPU_BASED_CR8_LOAD_EXITING |
1470 CPU_BASED_CR8_STORE_EXITING |
1471#endif
d56f546d
SY		 1472 CPU_BASED_CR3_LOAD_EXITING |
1473 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1474 CPU_BASED_USE_IO_BITMAPS |
1475 CPU_BASED_MOV_DR_EXITING |
a7052897 1476 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1477 CPU_BASED_MWAIT_EXITING |
1478 CPU_BASED_MONITOR_EXITING |
a7052897 1479 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 1480
1481 if (yield_on_hlt)
1482 min |= CPU_BASED_HLT_EXITING;
1483
f78e0e2e 1484 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1485 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1486 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1487 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1488 &_cpu_based_exec_control) < 0)
002c7f7c 1489 return -EIO;
6e5d865c
YS		 1490#ifdef CONFIG_X86_64
1491 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1492 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1493 ~CPU_BASED_CR8_STORE_EXITING;
1494#endif
f78e0e2e 1495 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1496 min2 = 0;
1497 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1498 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1499 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1500 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1501 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1502 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1503 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1504 if (adjust_vmx_controls(min2, opt2,
1505 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1506 &_cpu_based_2nd_exec_control) < 0)
1507 return -EIO;
1508 }
1509#ifndef CONFIG_X86_64
1510 if (!(_cpu_based_2nd_exec_control &
1511 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1512 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1513#endif
d56f546d 1514 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1515 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1516 enabled */
5fff7d27
GN		 1517 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1518 CPU_BASED_CR3_STORE_EXITING |
1519 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1520 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1521 vmx_capability.ept, vmx_capability.vpid);
1522 }
1c3d14fe
YS		 1523
1524 min = 0;
1525#ifdef CONFIG_X86_64
1526 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1527#endif
468d472f 1528 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1529 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1530 &_vmexit_control) < 0)
002c7f7c 1531 return -EIO;
1c3d14fe 1532
468d472f
SY		 1533 min = 0;
1534 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1535 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1536 &_vmentry_control) < 0)
002c7f7c 1537 return -EIO;
6aa8b732 1538
c68876fd 1539 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1540
1541 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1542 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1543 return -EIO;
1c3d14fe
YS		 1544
1545#ifdef CONFIG_X86_64
1546 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1547 if (vmx_msr_high & (1u<<16))
002c7f7c 1548 return -EIO;
1c3d14fe
YS		 1549#endif
1550
1551 /* Require Write-Back (WB) memory type for VMCS accesses. */
1552 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1553 return -EIO;
1c3d14fe 1554
002c7f7c
YS		 1555 vmcs_conf->size = vmx_msr_high & 0x1fff;
1556 vmcs_conf->order = get_order(vmcs_config.size);
1557 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1558
002c7f7c
YS		 1559 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1560 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1561 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1562 vmcs_conf->vmexit_ctrl = _vmexit_control;
1563 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 1564
110312c8
AK		 1565 cpu_has_load_ia32_efer =
1566 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1567 VM_ENTRY_LOAD_IA32_EFER)
1568 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1569 VM_EXIT_LOAD_IA32_EFER);
1570
1c3d14fe 1571 return 0;
c68876fd 1572}
6aa8b732
AK		 1573
1574static struct vmcs *alloc_vmcs_cpu(int cpu)
1575{
1576 int node = cpu_to_node(cpu);
1577 struct page *pages;
1578 struct vmcs *vmcs;
1579
6484eb3e 1580 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1581 if (!pages)
1582 return NULL;
1583 vmcs = page_address(pages);
1c3d14fe
YS		 1584 memset(vmcs, 0, vmcs_config.size);
1585 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1586 return vmcs;
1587}
1588
1589static struct vmcs *alloc_vmcs(void)
1590{
d3b2c338 1591 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1592}
1593
1594static void free_vmcs(struct vmcs *vmcs)
1595{
1c3d14fe 1596 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1597}
1598
39959588 1599static void free_kvm_area(void)
6aa8b732
AK		 1600{
1601 int cpu;
1602
3230bb47 1603 for_each_possible_cpu(cpu) {
6aa8b732 1604 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1605 per_cpu(vmxarea, cpu) = NULL;
1606 }
6aa8b732
AK		 1607}
1608
6aa8b732
AK		 1609static __init int alloc_kvm_area(void)
1610{
1611 int cpu;
1612
3230bb47 1613 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1614 struct vmcs *vmcs;
1615
1616 vmcs = alloc_vmcs_cpu(cpu);
1617 if (!vmcs) {
1618 free_kvm_area();
1619 return -ENOMEM;
1620 }
1621
1622 per_cpu(vmxarea, cpu) = vmcs;
1623 }
1624 return 0;
1625}
1626
1627static __init int hardware_setup(void)
1628{
002c7f7c
YS		 1629 if (setup_vmcs_config(&vmcs_config) < 0)
1630 return -EIO;
50a37eb4
JR		 1631
1632 if (boot_cpu_has(X86_FEATURE_NX))
1633 kvm_enable_efer_bits(EFER_NX);
1634
93ba03c2
SY		 1635 if (!cpu_has_vmx_vpid())
1636 enable_vpid = 0;
1637
4bc9b982
SY		 1638 if (!cpu_has_vmx_ept() ||
1639 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1640 enable_ept = 0;
3a624e29
NK		 1641 enable_unrestricted_guest = 0;
1642 }
1643
1644 if (!cpu_has_vmx_unrestricted_guest())
1645 enable_unrestricted_guest = 0;
93ba03c2
SY		 1646
1647 if (!cpu_has_vmx_flexpriority())
1648 flexpriority_enabled = 0;
1649
95ba8273
GN		 1650 if (!cpu_has_vmx_tpr_shadow())
1651 kvm_x86_ops->update_cr8_intercept = NULL;
1652
54dee993
MT		 1653 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1654 kvm_disable_largepages();
1655
4b8d54f9
ZE		 1656 if (!cpu_has_vmx_ple())
1657 ple_gap = 0;
1658
6aa8b732
AK		 1659 return alloc_kvm_area();
1660}
1661
1662static __exit void hardware_unsetup(void)
1663{
1664 free_kvm_area();
1665}
1666
6aa8b732
AK		 1667static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1668{
1669 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1670
6af11b9e 1671 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1672 vmcs_write16(sf->selector, save->selector);
1673 vmcs_writel(sf->base, save->base);
1674 vmcs_write32(sf->limit, save->limit);
1675 vmcs_write32(sf->ar_bytes, save->ar);
1676 } else {
1677 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1678 << AR_DPL_SHIFT;
1679 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1680 }
1681}
1682
1683static void enter_pmode(struct kvm_vcpu *vcpu)
1684{
1685 unsigned long flags;
a89a8fb9 1686 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1687
a89a8fb9 1688 vmx->emulation_required = 1;
7ffd92c5 1689 vmx->rmode.vm86_active = 0;
6aa8b732 1690
d0ba64f9 1691 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 1692 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1693 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1694 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1695
1696 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1697 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1698 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1699 vmcs_writel(GUEST_RFLAGS, flags);
1700
66aee91a
RR		 1701 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1702 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1703
1704 update_exception_bitmap(vcpu);
1705
a89a8fb9
MG		 1706 if (emulate_invalid_guest_state)
1707 return;
1708
7ffd92c5
AK		 1709 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1710 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1711 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1712 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1713
1714 vmcs_write16(GUEST_SS_SELECTOR, 0);
1715 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1716
1717 vmcs_write16(GUEST_CS_SELECTOR,
1718 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1719 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1720}
1721
d77c26fc 1722static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1723{
bfc6d222 1724 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1725 struct kvm_memslots *slots;
1726 gfn_t base_gfn;
1727
90d83dc3 1728 slots = kvm_memslots(kvm);
f495c6e5 1729 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1730 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1731 return base_gfn << PAGE_SHIFT;
1732 }
bfc6d222 1733 return kvm->arch.tss_addr;
6aa8b732
AK		 1734}
1735
1736static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1737{
1738 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1739
1740 save->selector = vmcs_read16(sf->selector);
1741 save->base = vmcs_readl(sf->base);
1742 save->limit = vmcs_read32(sf->limit);
1743 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 1744 vmcs_write16(sf->selector, save->base >> 4);
444e863d 1745 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 1746 vmcs_write32(sf->limit, 0xffff);
1747 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 1748 if (save->base & 0xf)
1749 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1750 " aligned when entering protected mode (seg=%d)",
1751 seg);
6aa8b732
AK		 1752}
1753
1754static void enter_rmode(struct kvm_vcpu *vcpu)
1755{
1756 unsigned long flags;
a89a8fb9 1757 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1758
3a624e29
NK		 1759 if (enable_unrestricted_guest)
1760 return;
1761
a89a8fb9 1762 vmx->emulation_required = 1;
7ffd92c5 1763 vmx->rmode.vm86_active = 1;
6aa8b732 1764
d0ba64f9 1765 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 1766 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1767 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1768
7ffd92c5 1769 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1770 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1771
7ffd92c5 1772 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1773 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1774
1775 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1776 vmx->rmode.save_rflags = flags;
6aa8b732 1777
053de044 1778 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1779
1780 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1781 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1782 update_exception_bitmap(vcpu);
1783
a89a8fb9
MG		 1784 if (emulate_invalid_guest_state)
1785 goto continue_rmode;
1786
6aa8b732
AK		 1787 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1788 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1789 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1790
1791 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1792 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1793 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1794 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1795 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1796
7ffd92c5
AK		 1797 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1798 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1799 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1800 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1801
a89a8fb9 1802continue_rmode:
8668a3c4 1803 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 1804}
1805
401d10de
AS		 1806static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1807{
1808 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1809 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1810
1811 if (!msr)
1812 return;
401d10de 1813
44ea2b17
AK		 1814 /*
1815 * Force kernel_gs_base reloading before EFER changes, as control
1816 * of this msr depends on is_long_mode().
1817 */
1818 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1819 vcpu->arch.efer = efer;
401d10de
AS		 1820 if (efer & EFER_LMA) {
1821 vmcs_write32(VM_ENTRY_CONTROLS,
1822 vmcs_read32(VM_ENTRY_CONTROLS) |
1823 VM_ENTRY_IA32E_MODE);
1824 msr->data = efer;
1825 } else {
1826 vmcs_write32(VM_ENTRY_CONTROLS,
1827 vmcs_read32(VM_ENTRY_CONTROLS) &
1828 ~VM_ENTRY_IA32E_MODE);
1829
1830 msr->data = efer & ~EFER_LME;
1831 }
1832 setup_msrs(vmx);
1833}
1834
05b3e0c2 1835#ifdef CONFIG_X86_64
6aa8b732
AK		 1836
1837static void enter_lmode(struct kvm_vcpu *vcpu)
1838{
1839 u32 guest_tr_ar;
1840
1841 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1842 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1843 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1844 __func__);
6aa8b732
AK		 1845 vmcs_write32(GUEST_TR_AR_BYTES,
1846 (guest_tr_ar & ~AR_TYPE_MASK)
1847 | AR_TYPE_BUSY_64_TSS);
1848 }
da38f438 1849 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1850}
1851
1852static void exit_lmode(struct kvm_vcpu *vcpu)
1853{
6aa8b732
AK		 1854 vmcs_write32(VM_ENTRY_CONTROLS,
1855 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1856 & ~VM_ENTRY_IA32E_MODE);
da38f438 1857 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1858}
1859
1860#endif
1861
2384d2b3
SY		 1862static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1863{
b9d762fa 1864 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 1865 if (enable_ept) {
1866 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1867 return;
4e1096d2 1868 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 1869 }
2384d2b3
SY		 1870}
1871
e8467fda
AK		 1872static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1873{
1874 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1875
1876 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1877 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1878}
1879
aff48baa
AK		 1880static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1881{
1882 if (enable_ept && is_paging(vcpu))
1883 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1884 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1885}
1886
25c4c276 1887static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1888{
fc78f519
AK		 1889 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1890
1891 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1892 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1893}
1894
1439442c
SY		 1895static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1896{
6de4f3ad
AK		 1897 if (!test_bit(VCPU_EXREG_PDPTR,
1898 (unsigned long *)&vcpu->arch.regs_dirty))
1899 return;
1900
1439442c 1901 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1902 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1903 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1904 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1905 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 1906 }
1907}
1908
8f5d549f
AK		 1909static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1910{
1911 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1912 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1913 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1914 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1915 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 1916 }
6de4f3ad
AK		 1917
1918 __set_bit(VCPU_EXREG_PDPTR,
1919 (unsigned long *)&vcpu->arch.regs_avail);
1920 __set_bit(VCPU_EXREG_PDPTR,
1921 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1922}
1923
1439442c
SY		 1924static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1925
1926static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1927 unsigned long cr0,
1928 struct kvm_vcpu *vcpu)
1929{
aff48baa 1930 vmx_decache_cr3(vcpu);
1439442c
SY		 1931 if (!(cr0 & X86_CR0_PG)) {
1932 /* From paging/starting to nonpaging */
1933 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1934 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1935 (CPU_BASED_CR3_LOAD_EXITING |
1936 CPU_BASED_CR3_STORE_EXITING));
1937 vcpu->arch.cr0 = cr0;
fc78f519 1938 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1939 } else if (!is_paging(vcpu)) {
1940 /* From nonpaging to paging */
1941 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1942 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1943 ~(CPU_BASED_CR3_LOAD_EXITING |
1944 CPU_BASED_CR3_STORE_EXITING));
1945 vcpu->arch.cr0 = cr0;
fc78f519 1946 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1947 }
95eb84a7
SY		 1948
1949 if (!(cr0 & X86_CR0_WP))
1950 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1951}
1952
6aa8b732
AK		 1953static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1954{
7ffd92c5 1955 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1956 unsigned long hw_cr0;
1957
1958 if (enable_unrestricted_guest)
1959 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1960 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1961 else
1962 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1963
7ffd92c5 1964 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1965 enter_pmode(vcpu);
1966
7ffd92c5 1967 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1968 enter_rmode(vcpu);
1969
05b3e0c2 1970#ifdef CONFIG_X86_64
f6801dff 1971 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1972 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1973 enter_lmode(vcpu);
707d92fa 1974 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1975 exit_lmode(vcpu);
1976 }
1977#endif
1978
089d034e 1979 if (enable_ept)
1439442c
SY		 1980 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1981
02daab21 1982 if (!vcpu->fpu_active)
81231c69 1983 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1984
6aa8b732 1985 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1986 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1987 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1988}
1989
1439442c
SY		 1990static u64 construct_eptp(unsigned long root_hpa)
1991{
1992 u64 eptp;
1993
1994 /* TODO write the value reading from MSR */
1995 eptp = VMX_EPT_DEFAULT_MT |
1996 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1997 eptp |= (root_hpa & PAGE_MASK);
1998
1999 return eptp;
2000}
2001
6aa8b732
AK		 2002static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2003{
1439442c
SY		 2004 unsigned long guest_cr3;
2005 u64 eptp;
2006
2007 guest_cr3 = cr3;
089d034e 2008 if (enable_ept) {
1439442c
SY		 2009 eptp = construct_eptp(cr3);
2010 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 2011 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 2012 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 2013 ept_load_pdptrs(vcpu);
1439442c
SY		 2014 }
2015
2384d2b3 2016 vmx_flush_tlb(vcpu);
1439442c 2017 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2018}
2019
2020static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2021{
7ffd92c5 2022 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2023 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2024
ad312c7c 2025 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2026 if (enable_ept) {
2027 if (!is_paging(vcpu)) {
2028 hw_cr4 &= ~X86_CR4_PAE;
2029 hw_cr4 |= X86_CR4_PSE;
2030 } else if (!(cr4 & X86_CR4_PAE)) {
2031 hw_cr4 &= ~X86_CR4_PAE;
2032 }
2033 }
1439442c
SY		 2034
2035 vmcs_writel(CR4_READ_SHADOW, cr4);
2036 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 2037}
2038
6aa8b732
AK		 2039static void vmx_get_segment(struct kvm_vcpu *vcpu,
2040 struct kvm_segment *var, int seg)
2041{
a9179499 2042 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2043 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
a9179499 2044 struct kvm_save_segment *save;
6aa8b732
AK		 2045 u32 ar;
2046
a9179499
AK		 2047 if (vmx->rmode.vm86_active
2048 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2049 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2050 || seg == VCPU_SREG_GS)
2051 && !emulate_invalid_guest_state) {
2052 switch (seg) {
2053 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2054 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2055 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2056 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2057 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2058 default: BUG();
2059 }
2060 var->selector = save->selector;
2061 var->base = save->base;
2062 var->limit = save->limit;
2063 ar = save->ar;
2064 if (seg == VCPU_SREG_TR
2065 || var->selector == vmcs_read16(sf->selector))
2066 goto use_saved_rmode_seg;
2067 }
6aa8b732
AK		 2068 var->base = vmcs_readl(sf->base);
2069 var->limit = vmcs_read32(sf->limit);
2070 var->selector = vmcs_read16(sf->selector);
2071 ar = vmcs_read32(sf->ar_bytes);
a9179499 2072use_saved_rmode_seg:
9fd4a3b7 2073 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2074 ar = 0;
2075 var->type = ar & 15;
2076 var->s = (ar >> 4) & 1;
2077 var->dpl = (ar >> 5) & 3;
2078 var->present = (ar >> 7) & 1;
2079 var->avl = (ar >> 12) & 1;
2080 var->l = (ar >> 13) & 1;
2081 var->db = (ar >> 14) & 1;
2082 var->g = (ar >> 15) & 1;
2083 var->unusable = (ar >> 16) & 1;
2084}
2085
a9179499
AK		 2086static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2087{
2088 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2089 struct kvm_segment s;
2090
2091 if (to_vmx(vcpu)->rmode.vm86_active) {
2092 vmx_get_segment(vcpu, &s, seg);
2093 return s.base;
2094 }
2095 return vmcs_readl(sf->base);
2096}
2097
2e4d2653
IE		 2098static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2099{
3eeb3288 2100 if (!is_protmode(vcpu))
2e4d2653
IE		 2101 return 0;
2102
2103 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2104 return 3;
2105
eab4b8aa 2106 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2107}
2108
653e3108 2109static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2110{
6aa8b732
AK		 2111 u32 ar;
2112
653e3108 2113 if (var->unusable)
6aa8b732
AK		 2114 ar = 1 << 16;
2115 else {
2116 ar = var->type & 15;
2117 ar |= (var->s & 1) << 4;
2118 ar |= (var->dpl & 3) << 5;
2119 ar |= (var->present & 1) << 7;
2120 ar |= (var->avl & 1) << 12;
2121 ar |= (var->l & 1) << 13;
2122 ar |= (var->db & 1) << 14;
2123 ar |= (var->g & 1) << 15;
2124 }
f7fbf1fd
UL		 2125 if (ar == 0) /* a 0 value means unusable */
2126 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2127
2128 return ar;
2129}
2130
2131static void vmx_set_segment(struct kvm_vcpu *vcpu,
2132 struct kvm_segment *var, int seg)
2133{
7ffd92c5 2134 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2135 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2136 u32 ar;
2137
7ffd92c5 2138 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 2139 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 2140 vmx->rmode.tr.selector = var->selector;
2141 vmx->rmode.tr.base = var->base;
2142 vmx->rmode.tr.limit = var->limit;
2143 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2144 return;
2145 }
2146 vmcs_writel(sf->base, var->base);
2147 vmcs_write32(sf->limit, var->limit);
2148 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2149 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2150 /*
2151 * Hack real-mode segments into vm86 compatibility.
2152 */
2153 if (var->base == 0xffff0000 && var->selector == 0xf000)
2154 vmcs_writel(sf->base, 0xf0000);
2155 ar = 0xf3;
2156 } else
2157 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2158
2159 /*
2160 * Fix the "Accessed" bit in AR field of segment registers for older
2161 * qemu binaries.
2162 * IA32 arch specifies that at the time of processor reset the
2163 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2164 * is setting it to 0 in the usedland code. This causes invalid guest
2165 * state vmexit when "unrestricted guest" mode is turned on.
2166 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2167 * tree. Newer qemu binaries with that qemu fix would not need this
2168 * kvm hack.
2169 */
2170 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2171 ar |= 0x1; /* Accessed */
2172
6aa8b732
AK		 2173 vmcs_write32(sf->ar_bytes, ar);
2174}
2175
6aa8b732
AK		 2176static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2177{
2178 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2179
2180 *db = (ar >> 14) & 1;
2181 *l = (ar >> 13) & 1;
2182}
2183
89a27f4d 2184static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2185{
89a27f4d
GN		 2186 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2187 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2188}
2189
89a27f4d 2190static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2191{
89a27f4d
GN		 2192 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2193 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2194}
2195
89a27f4d 2196static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2197{
89a27f4d
GN		 2198 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2199 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2200}
2201
89a27f4d 2202static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2203{
89a27f4d
GN		 2204 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2205 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2206}
2207
648dfaa7
MG		 2208static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2209{
2210 struct kvm_segment var;
2211 u32 ar;
2212
2213 vmx_get_segment(vcpu, &var, seg);
2214 ar = vmx_segment_access_rights(&var);
2215
2216 if (var.base != (var.selector << 4))
2217 return false;
2218 if (var.limit != 0xffff)
2219 return false;
2220 if (ar != 0xf3)
2221 return false;
2222
2223 return true;
2224}
2225
2226static bool code_segment_valid(struct kvm_vcpu *vcpu)
2227{
2228 struct kvm_segment cs;
2229 unsigned int cs_rpl;
2230
2231 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2232 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2233
1872a3f4
AK		 2234 if (cs.unusable)
2235 return false;
648dfaa7
MG		 2236 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2237 return false;
2238 if (!cs.s)
2239 return false;
1872a3f4 2240 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2241 if (cs.dpl > cs_rpl)
2242 return false;
1872a3f4 2243 } else {
648dfaa7
MG		 2244 if (cs.dpl != cs_rpl)
2245 return false;
2246 }
2247 if (!cs.present)
2248 return false;
2249
2250 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2251 return true;
2252}
2253
2254static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2255{
2256 struct kvm_segment ss;
2257 unsigned int ss_rpl;
2258
2259 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2260 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2261
1872a3f4
AK		 2262 if (ss.unusable)
2263 return true;
2264 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2265 return false;
2266 if (!ss.s)
2267 return false;
2268 if (ss.dpl != ss_rpl) /* DPL != RPL */
2269 return false;
2270 if (!ss.present)
2271 return false;
2272
2273 return true;
2274}
2275
2276static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2277{
2278 struct kvm_segment var;
2279 unsigned int rpl;
2280
2281 vmx_get_segment(vcpu, &var, seg);
2282 rpl = var.selector & SELECTOR_RPL_MASK;
2283
1872a3f4
AK		 2284 if (var.unusable)
2285 return true;
648dfaa7
MG		 2286 if (!var.s)
2287 return false;
2288 if (!var.present)
2289 return false;
2290 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2291 if (var.dpl < rpl) /* DPL < RPL */
2292 return false;
2293 }
2294
2295 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2296 * rights flags
2297 */
2298 return true;
2299}
2300
2301static bool tr_valid(struct kvm_vcpu *vcpu)
2302{
2303 struct kvm_segment tr;
2304
2305 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2306
1872a3f4
AK		 2307 if (tr.unusable)
2308 return false;
648dfaa7
MG		 2309 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2310 return false;
1872a3f4 2311 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2312 return false;
2313 if (!tr.present)
2314 return false;
2315
2316 return true;
2317}
2318
2319static bool ldtr_valid(struct kvm_vcpu *vcpu)
2320{
2321 struct kvm_segment ldtr;
2322
2323 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2324
1872a3f4
AK		 2325 if (ldtr.unusable)
2326 return true;
648dfaa7
MG		 2327 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2328 return false;
2329 if (ldtr.type != 2)
2330 return false;
2331 if (!ldtr.present)
2332 return false;
2333
2334 return true;
2335}
2336
2337static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2338{
2339 struct kvm_segment cs, ss;
2340
2341 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2342 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2343
2344 return ((cs.selector & SELECTOR_RPL_MASK) ==
2345 (ss.selector & SELECTOR_RPL_MASK));
2346}
2347
2348/*
2349 * Check if guest state is valid. Returns true if valid, false if
2350 * not.
2351 * We assume that registers are always usable
2352 */
2353static bool guest_state_valid(struct kvm_vcpu *vcpu)
2354{
2355 /* real mode guest state checks */
3eeb3288 2356 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2357 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2358 return false;
2359 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2360 return false;
2361 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2362 return false;
2363 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2364 return false;
2365 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2366 return false;
2367 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2368 return false;
2369 } else {
2370 /* protected mode guest state checks */
2371 if (!cs_ss_rpl_check(vcpu))
2372 return false;
2373 if (!code_segment_valid(vcpu))
2374 return false;
2375 if (!stack_segment_valid(vcpu))
2376 return false;
2377 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2378 return false;
2379 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2380 return false;
2381 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2382 return false;
2383 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2384 return false;
2385 if (!tr_valid(vcpu))
2386 return false;
2387 if (!ldtr_valid(vcpu))
2388 return false;
2389 }
2390 /* TODO:
2391 * - Add checks on RIP
2392 * - Add checks on RFLAGS
2393 */
2394
2395 return true;
2396}
2397
d77c26fc 2398static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2399{
40dcaa9f 2400 gfn_t fn;
195aefde 2401 u16 data = 0;
40dcaa9f 2402 int r, idx, ret = 0;
6aa8b732 2403
40dcaa9f
XG		 2404 idx = srcu_read_lock(&kvm->srcu);
2405 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 2406 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2407 if (r < 0)
10589a46 2408 goto out;
195aefde 2409 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2410 r = kvm_write_guest_page(kvm, fn++, &data,
2411 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2412 if (r < 0)
10589a46 2413 goto out;
195aefde
IE		 2414 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2415 if (r < 0)
10589a46 2416 goto out;
195aefde
IE		 2417 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2418 if (r < 0)
10589a46 2419 goto out;
195aefde 2420 data = ~0;
10589a46
MT		 2421 r = kvm_write_guest_page(kvm, fn, &data,
2422 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2423 sizeof(u8));
195aefde 2424 if (r < 0)
10589a46
MT		 2425 goto out;
2426
2427 ret = 1;
2428out:
40dcaa9f 2429 srcu_read_unlock(&kvm->srcu, idx);
10589a46 2430 return ret;
6aa8b732
AK		 2431}
2432
b7ebfb05
SY		 2433static int init_rmode_identity_map(struct kvm *kvm)
2434{
40dcaa9f 2435 int i, idx, r, ret;
b7ebfb05
SY		 2436 pfn_t identity_map_pfn;
2437 u32 tmp;
2438
089d034e 2439 if (!enable_ept)
b7ebfb05
SY		 2440 return 1;
2441 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2442 printk(KERN_ERR "EPT: identity-mapping pagetable "
2443 "haven't been allocated!\n");
2444 return 0;
2445 }
2446 if (likely(kvm->arch.ept_identity_pagetable_done))
2447 return 1;
2448 ret = 0;
b927a3ce 2449 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 2450 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 2451 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2452 if (r < 0)
2453 goto out;
2454 /* Set up identity-mapping pagetable for EPT in real mode */
2455 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2456 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2457 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2458 r = kvm_write_guest_page(kvm, identity_map_pfn,
2459 &tmp, i * sizeof(tmp), sizeof(tmp));
2460 if (r < 0)
2461 goto out;
2462 }
2463 kvm->arch.ept_identity_pagetable_done = true;
2464 ret = 1;
2465out:
40dcaa9f 2466 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 2467 return ret;
2468}
2469
6aa8b732
AK		 2470static void seg_setup(int seg)
2471{
2472 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2473 unsigned int ar;
6aa8b732
AK		 2474
2475 vmcs_write16(sf->selector, 0);
2476 vmcs_writel(sf->base, 0);
2477 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2478 if (enable_unrestricted_guest) {
2479 ar = 0x93;
2480 if (seg == VCPU_SREG_CS)
2481 ar |= 0x08; /* code segment */
2482 } else
2483 ar = 0xf3;
2484
2485 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2486}
2487
f78e0e2e
SY		 2488static int alloc_apic_access_page(struct kvm *kvm)
2489{
2490 struct kvm_userspace_memory_region kvm_userspace_mem;
2491 int r = 0;
2492
79fac95e 2493 mutex_lock(&kvm->slots_lock);
bfc6d222 2494 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2495 goto out;
2496 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2497 kvm_userspace_mem.flags = 0;
2498 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2499 kvm_userspace_mem.memory_size = PAGE_SIZE;
2500 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2501 if (r)
2502 goto out;
72dc67a6 2503
bfc6d222 2504 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2505out:
79fac95e 2506 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2507 return r;
2508}
2509
b7ebfb05
SY		 2510static int alloc_identity_pagetable(struct kvm *kvm)
2511{
2512 struct kvm_userspace_memory_region kvm_userspace_mem;
2513 int r = 0;
2514
79fac95e 2515 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2516 if (kvm->arch.ept_identity_pagetable)
2517 goto out;
2518 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2519 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2520 kvm_userspace_mem.guest_phys_addr =
2521 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2522 kvm_userspace_mem.memory_size = PAGE_SIZE;
2523 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2524 if (r)
2525 goto out;
2526
b7ebfb05 2527 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2528 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2529out:
79fac95e 2530 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2531 return r;
2532}
2533
2384d2b3
SY		 2534static void allocate_vpid(struct vcpu_vmx *vmx)
2535{
2536 int vpid;
2537
2538 vmx->vpid = 0;
919818ab 2539 if (!enable_vpid)
2384d2b3
SY		 2540 return;
2541 spin_lock(&vmx_vpid_lock);
2542 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2543 if (vpid < VMX_NR_VPIDS) {
2544 vmx->vpid = vpid;
2545 __set_bit(vpid, vmx_vpid_bitmap);
2546 }
2547 spin_unlock(&vmx_vpid_lock);
2548}
2549
cdbecfc3
LJ		 2550static void free_vpid(struct vcpu_vmx *vmx)
2551{
2552 if (!enable_vpid)
2553 return;
2554 spin_lock(&vmx_vpid_lock);
2555 if (vmx->vpid != 0)
2556 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2557 spin_unlock(&vmx_vpid_lock);
2558}
2559
5897297b 2560static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2561{
3e7c73e9 2562 int f = sizeof(unsigned long);
25c5f225
SY		 2563
2564 if (!cpu_has_vmx_msr_bitmap())
2565 return;
2566
2567 /*
2568 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2569 * have the write-low and read-high bitmap offsets the wrong way round.
2570 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2571 */
25c5f225 2572 if (msr <= 0x1fff) {
3e7c73e9
AK		 2573 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2574 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2575 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2576 msr &= 0x1fff;
3e7c73e9
AK		 2577 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2578 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2579 }
25c5f225
SY		 2580}
2581
5897297b
AK		 2582static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2583{
2584 if (!longmode_only)
2585 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2586 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2587}
2588
6aa8b732
AK		 2589/*
2590 * Sets up the vmcs for emulated real mode.
2591 */
8b9cf98c 2592static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2593{
468d472f 2594 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2595 u32 junk;
f4e1b3c8 2596 u64 host_pat;
6aa8b732 2597 unsigned long a;
89a27f4d 2598 struct desc_ptr dt;
6aa8b732 2599 int i;
cd2276a7 2600 unsigned long kvm_vmx_return;
6e5d865c 2601 u32 exec_control;
6aa8b732 2602
6aa8b732 2603 /* I/O */
3e7c73e9
AK		 2604 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2605 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2606
25c5f225 2607 if (cpu_has_vmx_msr_bitmap())
5897297b 2608 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2609
6aa8b732
AK		 2610 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2611
6aa8b732 2612 /* Control */
1c3d14fe
YS		 2613 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2614 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2615
2616 exec_control = vmcs_config.cpu_based_exec_ctrl;
2617 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2618 exec_control &= ~CPU_BASED_TPR_SHADOW;
2619#ifdef CONFIG_X86_64
2620 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2621 CPU_BASED_CR8_LOAD_EXITING;
2622#endif
2623 }
089d034e 2624 if (!enable_ept)
d56f546d 2625 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2626 CPU_BASED_CR3_LOAD_EXITING |
2627 CPU_BASED_INVLPG_EXITING;
6e5d865c 2628 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2629
83ff3b9d
SY		 2630 if (cpu_has_secondary_exec_ctrls()) {
2631 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2632 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2633 exec_control &=
2634 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2635 if (vmx->vpid == 0)
2636 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2637 if (!enable_ept) {
d56f546d 2638 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2639 enable_unrestricted_guest = 0;
2640 }
3a624e29
NK		 2641 if (!enable_unrestricted_guest)
2642 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2643 if (!ple_gap)
2644 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2645 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2646 }
f78e0e2e 2647
4b8d54f9
ZE		 2648 if (ple_gap) {
2649 vmcs_write32(PLE_GAP, ple_gap);
2650 vmcs_write32(PLE_WINDOW, ple_window);
2651 }
2652
c7addb90
AK		 2653 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2654 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2655 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2656
1c11e713 2657 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2658 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2659 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2660
2661 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2662 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2663 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
9581d442
AK		 2664 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2665 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6aa8b732 2666 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2667#ifdef CONFIG_X86_64
6aa8b732
AK		 2668 rdmsrl(MSR_FS_BASE, a);
2669 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2670 rdmsrl(MSR_GS_BASE, a);
2671 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2672#else
2673 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2674 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2675#endif
2676
2677 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2678
ec68798c 2679 native_store_idt(&dt);
89a27f4d 2680 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2681
d77c26fc 2682 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2683 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2684 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2685 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2686 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2687 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2688 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2689
2690 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2691 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2692 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2693 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2694 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2695 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2696
468d472f
SY		 2697 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2698 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2699 host_pat = msr_low | ((u64) msr_high << 32);
2700 vmcs_write64(HOST_IA32_PAT, host_pat);
2701 }
2702 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2703 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2704 host_pat = msr_low | ((u64) msr_high << 32);
2705 /* Write the default value follow host pat */
2706 vmcs_write64(GUEST_IA32_PAT, host_pat);
2707 /* Keep arch.pat sync with GUEST_IA32_PAT */
2708 vmx->vcpu.arch.pat = host_pat;
2709 }
2710
6aa8b732
AK		 2711 for (i = 0; i < NR_VMX_MSR; ++i) {
2712 u32 index = vmx_msr_index[i];
2713 u32 data_low, data_high;
a2fa3e9f 2714 int j = vmx->nmsrs;
6aa8b732
AK		 2715
2716 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2717 continue;
432bd6cb
AK		 2718 if (wrmsr_safe(index, data_low, data_high) < 0)
2719 continue;
26bb0981
AK		 2720 vmx->guest_msrs[j].index = i;
2721 vmx->guest_msrs[j].data = 0;
d5696725 2722 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2723 ++vmx->nmsrs;
6aa8b732 2724 }
6aa8b732 2725
1c3d14fe 2726 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2727
2728 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2729 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2730
e00c8cf2 2731 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2732 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2733 if (enable_ept)
2734 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2735 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2736
99e3e30a 2737 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 2738
e00c8cf2
AK		 2739 return 0;
2740}
2741
2742static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2743{
2744 struct vcpu_vmx *vmx = to_vmx(vcpu);
2745 u64 msr;
4b9d3a04 2746 int ret;
e00c8cf2 2747
5fdbf976 2748 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 2749
7ffd92c5 2750 vmx->rmode.vm86_active = 0;
e00c8cf2 2751
3b86cd99
JK		 2752 vmx->soft_vnmi_blocked = 0;
2753
ad312c7c 2754 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2755 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2756 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2757 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2758 msr |= MSR_IA32_APICBASE_BSP;
2759 kvm_set_apic_base(&vmx->vcpu, msr);
2760
10ab25cd
JK		 2761 ret = fx_init(&vmx->vcpu);
2762 if (ret != 0)
2763 goto out;
e00c8cf2 2764
5706be0d 2765 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2766 /*
2767 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2768 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2769 */
c5af89b6 2770 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2771 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2772 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2773 } else {
ad312c7c
ZX		 2774 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2775 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2776 }
e00c8cf2
AK		 2777
2778 seg_setup(VCPU_SREG_DS);
2779 seg_setup(VCPU_SREG_ES);
2780 seg_setup(VCPU_SREG_FS);
2781 seg_setup(VCPU_SREG_GS);
2782 seg_setup(VCPU_SREG_SS);
2783
2784 vmcs_write16(GUEST_TR_SELECTOR, 0);
2785 vmcs_writel(GUEST_TR_BASE, 0);
2786 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2787 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2788
2789 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2790 vmcs_writel(GUEST_LDTR_BASE, 0);
2791 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2792 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2793
2794 vmcs_write32(GUEST_SYSENTER_CS, 0);
2795 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2796 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2797
2798 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2799 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2800 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2801 else
5fdbf976
MT		 2802 kvm_rip_write(vcpu, 0);
2803 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2804
e00c8cf2
AK		 2805 vmcs_writel(GUEST_DR7, 0x400);
2806
2807 vmcs_writel(GUEST_GDTR_BASE, 0);
2808 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2809
2810 vmcs_writel(GUEST_IDTR_BASE, 0);
2811 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2812
443381a8 2813 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 2814 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2815 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2816
e00c8cf2
AK		 2817 /* Special registers */
2818 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2819
2820 setup_msrs(vmx);
2821
6aa8b732
AK		 2822 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2823
f78e0e2e
SY		 2824 if (cpu_has_vmx_tpr_shadow()) {
2825 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2826 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2827 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 2828 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 2829 vmcs_write32(TPR_THRESHOLD, 0);
2830 }
2831
2832 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2833 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2834 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2835
2384d2b3
SY		 2836 if (vmx->vpid != 0)
2837 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2838
fa40052c 2839 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2840 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2841 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2842 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2843 vmx_fpu_activate(&vmx->vcpu);
2844 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2845
b9d762fa 2846 vpid_sync_context(vmx);
2384d2b3 2847
3200f405 2848 ret = 0;
6aa8b732 2849
a89a8fb9
MG		 2850 /* HACK: Don't enable emulation on guest boot/reset */
2851 vmx->emulation_required = 0;
2852
6aa8b732
AK		 2853out:
2854 return ret;
2855}
2856
3b86cd99
JK		 2857static void enable_irq_window(struct kvm_vcpu *vcpu)
2858{
2859 u32 cpu_based_vm_exec_control;
2860
2861 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2862 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2863 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2864}
2865
2866static void enable_nmi_window(struct kvm_vcpu *vcpu)
2867{
2868 u32 cpu_based_vm_exec_control;
2869
2870 if (!cpu_has_virtual_nmis()) {
2871 enable_irq_window(vcpu);
2872 return;
2873 }
2874
30bd0c4c
AK		 2875 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2876 enable_irq_window(vcpu);
2877 return;
2878 }
3b86cd99
JK		 2879 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2880 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2881 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2882}
2883
66fd3f7f 2884static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2885{
9c8cba37 2886 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2887 uint32_t intr;
2888 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2889
229456fc 2890 trace_kvm_inj_virq(irq);
2714d1d3 2891
fa89a817 2892 ++vcpu->stat.irq_injections;
7ffd92c5 2893 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2894 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2895 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 2896 return;
2897 }
66fd3f7f
GN		 2898 intr = irq | INTR_INFO_VALID_MASK;
2899 if (vcpu->arch.interrupt.soft) {
2900 intr |= INTR_TYPE_SOFT_INTR;
2901 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2902 vmx->vcpu.arch.event_exit_inst_len);
2903 } else
2904 intr |= INTR_TYPE_EXT_INTR;
2905 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 2906 vmx_clear_hlt(vcpu);
85f455f7
ED		 2907}
2908
f08864b4
SY		 2909static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2910{
66a5a347
JK		 2911 struct vcpu_vmx *vmx = to_vmx(vcpu);
2912
3b86cd99
JK		 2913 if (!cpu_has_virtual_nmis()) {
2914 /*
2915 * Tracking the NMI-blocked state in software is built upon
2916 * finding the next open IRQ window. This, in turn, depends on
2917 * well-behaving guests: They have to keep IRQs disabled at
2918 * least as long as the NMI handler runs. Otherwise we may
2919 * cause NMI nesting, maybe breaking the guest. But as this is
2920 * highly unlikely, we can live with the residual risk.
2921 */
2922 vmx->soft_vnmi_blocked = 1;
2923 vmx->vnmi_blocked_time = 0;
2924 }
2925
487b391d 2926 ++vcpu->stat.nmi_injections;
7ffd92c5 2927 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2928 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2929 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 2930 return;
2931 }
f08864b4
SY		 2932 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2933 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 2934 vmx_clear_hlt(vcpu);
f08864b4
SY		 2935}
2936
c4282df9 2937static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2938{
3b86cd99 2939 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2940 return 0;
33f089ca 2941
c4282df9 2942 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 2943 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2944 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2945}
2946
3cfc3092
JK		 2947static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2948{
2949 if (!cpu_has_virtual_nmis())
2950 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2951 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2952}
2953
2954static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2955{
2956 struct vcpu_vmx *vmx = to_vmx(vcpu);
2957
2958 if (!cpu_has_virtual_nmis()) {
2959 if (vmx->soft_vnmi_blocked != masked) {
2960 vmx->soft_vnmi_blocked = masked;
2961 vmx->vnmi_blocked_time = 0;
2962 }
2963 } else {
2964 if (masked)
2965 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2966 GUEST_INTR_STATE_NMI);
2967 else
2968 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2969 GUEST_INTR_STATE_NMI);
2970 }
2971}
2972
78646121
GN		 2973static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2974{
c4282df9
GN		 2975 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2976 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2977 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2978}
2979
cbc94022
IE		 2980static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2981{
2982 int ret;
2983 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2984 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2985 .guest_phys_addr = addr,
2986 .memory_size = PAGE_SIZE * 3,
2987 .flags = 0,
2988 };
2989
2990 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2991 if (ret)
2992 return ret;
bfc6d222 2993 kvm->arch.tss_addr = addr;
93ea5388
GN		 2994 if (!init_rmode_tss(kvm))
2995 return -ENOMEM;
2996
cbc94022
IE		 2997 return 0;
2998}
2999
6aa8b732
AK		 3000static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3001 int vec, u32 err_code)
3002{
b3f37707
NK		 3003 /*
3004 * Instruction with address size override prefix opcode 0x67
3005 * Cause the #SS fault with 0 error code in VM86 mode.
3006 */
3007 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 3008 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 3009 return 1;
77ab6db0
JK		 3010 /*
3011 * Forward all other exceptions that are valid in real mode.
3012 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3013 * the required debugging infrastructure rework.
3014 */
3015 switch (vec) {
77ab6db0 3016 case DB_VECTOR:
d0bfb940
JK		 3017 if (vcpu->guest_debug &
3018 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3019 return 0;
3020 kvm_queue_exception(vcpu, vec);
3021 return 1;
77ab6db0 3022 case BP_VECTOR:
c573cd22
JK		 3023 /*
3024 * Update instruction length as we may reinject the exception
3025 * from user space while in guest debugging mode.
3026 */
3027 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3028 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 3029 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3030 return 0;
3031 /* fall through */
3032 case DE_VECTOR:
77ab6db0
JK		 3033 case OF_VECTOR:
3034 case BR_VECTOR:
3035 case UD_VECTOR:
3036 case DF_VECTOR:
3037 case SS_VECTOR:
3038 case GP_VECTOR:
3039 case MF_VECTOR:
3040 kvm_queue_exception(vcpu, vec);
3041 return 1;
3042 }
6aa8b732
AK		 3043 return 0;
3044}
3045
a0861c02
AK		 3046/*
3047 * Trigger machine check on the host. We assume all the MSRs are already set up
3048 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3049 * We pass a fake environment to the machine check handler because we want
3050 * the guest to be always treated like user space, no matter what context
3051 * it used internally.
3052 */
3053static void kvm_machine_check(void)
3054{
3055#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3056 struct pt_regs regs = {
3057 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3058 .flags = X86_EFLAGS_IF,
3059 };
3060
3061 do_machine_check(&regs, 0);
3062#endif
3063}
3064
851ba692 3065static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3066{
3067 /* already handled by vcpu_run */
3068 return 1;
3069}
3070
851ba692 3071static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3072{
1155f76a 3073 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3074 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3075 u32 intr_info, ex_no, error_code;
42dbaa5a 3076 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3077 u32 vect_info;
3078 enum emulation_result er;
3079
1155f76a 3080 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 3081 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3082
a0861c02 3083 if (is_machine_check(intr_info))
851ba692 3084 return handle_machine_check(vcpu);
a0861c02 3085
6aa8b732 3086 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3087 !is_page_fault(intr_info)) {
3088 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3089 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3090 vcpu->run->internal.ndata = 2;
3091 vcpu->run->internal.data[0] = vect_info;
3092 vcpu->run->internal.data[1] = intr_info;
3093 return 0;
3094 }
6aa8b732 3095
e4a41889 3096 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3097 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3098
3099 if (is_no_device(intr_info)) {
5fd86fcf 3100 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3101 return 1;
3102 }
3103
7aa81cc0 3104 if (is_invalid_opcode(intr_info)) {
51d8b661 3105 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 3106 if (er != EMULATE_DONE)
7ee5d940 3107 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3108 return 1;
3109 }
3110
6aa8b732 3111 error_code = 0;
5fdbf976 3112 rip = kvm_rip_read(vcpu);
2e11384c 3113 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3114 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3115 if (is_page_fault(intr_info)) {
1439442c 3116 /* EPT won't cause page fault directly */
089d034e 3117 if (enable_ept)
1439442c 3118 BUG();
6aa8b732 3119 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3120 trace_kvm_page_fault(cr2, error_code);
3121
3298b75c 3122 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3123 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 3124 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 3125 }
3126
7ffd92c5 3127 if (vmx->rmode.vm86_active &&
6aa8b732 3128 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3129 error_code)) {
ad312c7c
ZX		 3130 if (vcpu->arch.halt_request) {
3131 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3132 return kvm_emulate_halt(vcpu);
3133 }
6aa8b732 3134 return 1;
72d6e5a0 3135 }
6aa8b732 3136
d0bfb940 3137 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3138 switch (ex_no) {
3139 case DB_VECTOR:
3140 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3141 if (!(vcpu->guest_debug &
3142 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3143 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3144 kvm_queue_exception(vcpu, DB_VECTOR);
3145 return 1;
3146 }
3147 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3148 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3149 /* fall through */
3150 case BP_VECTOR:
c573cd22
JK		 3151 /*
3152 * Update instruction length as we may reinject #BP from
3153 * user space while in guest debugging mode. Reading it for
3154 * #DB as well causes no harm, it is not used in that case.
3155 */
3156 vmx->vcpu.arch.event_exit_inst_len =
3157 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3158 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3159 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3160 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3161 break;
3162 default:
d0bfb940
JK		 3163 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3164 kvm_run->ex.exception = ex_no;
3165 kvm_run->ex.error_code = error_code;
42dbaa5a 3166 break;
6aa8b732 3167 }
6aa8b732
AK		 3168 return 0;
3169}
3170
851ba692 3171static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3172{
1165f5fe 3173 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3174 return 1;
3175}
3176
851ba692 3177static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3178{
851ba692 3179 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3180 return 0;
3181}
6aa8b732 3182
851ba692 3183static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3184{
bfdaab09 3185 unsigned long exit_qualification;
34c33d16 3186 int size, in, string;
039576c0 3187 unsigned port;
6aa8b732 3188
bfdaab09 3189 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3190 string = (exit_qualification & 16) != 0;
cf8f70bf 3191 in = (exit_qualification & 8) != 0;
e70669ab 3192
cf8f70bf 3193 ++vcpu->stat.io_exits;
e70669ab 3194
cf8f70bf 3195 if (string || in)
51d8b661 3196 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 3197
cf8f70bf
GN		 3198 port = exit_qualification >> 16;
3199 size = (exit_qualification & 7) + 1;
e93f36bc 3200 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3201
3202 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3203}
3204
102d8325
IM		 3205static void
3206vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3207{
3208 /*
3209 * Patch in the VMCALL instruction:
3210 */
3211 hypercall[0] = 0x0f;
3212 hypercall[1] = 0x01;
3213 hypercall[2] = 0xc1;
102d8325
IM		 3214}
3215
851ba692 3216static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3217{
229456fc 3218 unsigned long exit_qualification, val;
6aa8b732
AK		 3219 int cr;
3220 int reg;
49a9b07e 3221 int err;
6aa8b732 3222
bfdaab09 3223 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3224 cr = exit_qualification & 15;
3225 reg = (exit_qualification >> 8) & 15;
3226 switch ((exit_qualification >> 4) & 3) {
3227 case 0: /* mov to cr */
229456fc
MT		 3228 val = kvm_register_read(vcpu, reg);
3229 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3230 switch (cr) {
3231 case 0:
49a9b07e 3232 err = kvm_set_cr0(vcpu, val);
db8fcefa 3233 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3234 return 1;
3235 case 3:
2390218b 3236 err = kvm_set_cr3(vcpu, val);
db8fcefa 3237 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3238 return 1;
3239 case 4:
a83b29c6 3240 err = kvm_set_cr4(vcpu, val);
db8fcefa 3241 kvm_complete_insn_gp(vcpu, err);
6aa8b732 3242 return 1;
0a5fff19
GN		 3243 case 8: {
3244 u8 cr8_prev = kvm_get_cr8(vcpu);
3245 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 3246 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 3247 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 3248 if (irqchip_in_kernel(vcpu->kvm))
3249 return 1;
3250 if (cr8_prev <= cr8)
3251 return 1;
851ba692 3252 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3253 return 0;
3254 }
6aa8b732
AK		 3255 };
3256 break;
25c4c276 3257 case 2: /* clts */
edcafe3c 3258 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3259 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3260 skip_emulated_instruction(vcpu);
6b52d186 3261 vmx_fpu_activate(vcpu);
25c4c276 3262 return 1;
6aa8b732
AK		 3263 case 1: /*mov from cr*/
3264 switch (cr) {
3265 case 3:
9f8fe504
AK		 3266 val = kvm_read_cr3(vcpu);
3267 kvm_register_write(vcpu, reg, val);
3268 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3269 skip_emulated_instruction(vcpu);
3270 return 1;
3271 case 8:
229456fc
MT		 3272 val = kvm_get_cr8(vcpu);
3273 kvm_register_write(vcpu, reg, val);
3274 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3275 skip_emulated_instruction(vcpu);
3276 return 1;
3277 }
3278 break;
3279 case 3: /* lmsw */
a1f83a74 3280 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3281 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3282 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3283
3284 skip_emulated_instruction(vcpu);
3285 return 1;
3286 default:
3287 break;
3288 }
851ba692 3289 vcpu->run->exit_reason = 0;
f0242478 3290 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3291 (int)(exit_qualification >> 4) & 3, cr);
3292 return 0;
3293}
3294
851ba692 3295static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3296{
bfdaab09 3297 unsigned long exit_qualification;
6aa8b732
AK		 3298 int dr, reg;
3299
f2483415 3300 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3301 if (!kvm_require_cpl(vcpu, 0))
3302 return 1;
42dbaa5a
JK		 3303 dr = vmcs_readl(GUEST_DR7);
3304 if (dr & DR7_GD) {
3305 /*
3306 * As the vm-exit takes precedence over the debug trap, we
3307 * need to emulate the latter, either for the host or the
3308 * guest debugging itself.
3309 */
3310 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3311 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3312 vcpu->run->debug.arch.dr7 = dr;
3313 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3314 vmcs_readl(GUEST_CS_BASE) +
3315 vmcs_readl(GUEST_RIP);
851ba692
AK		 3316 vcpu->run->debug.arch.exception = DB_VECTOR;
3317 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3318 return 0;
3319 } else {
3320 vcpu->arch.dr7 &= ~DR7_GD;
3321 vcpu->arch.dr6 |= DR6_BD;
3322 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3323 kvm_queue_exception(vcpu, DB_VECTOR);
3324 return 1;
3325 }
3326 }
3327
bfdaab09 3328 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3329 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3330 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3331 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3332 unsigned long val;
3333 if (!kvm_get_dr(vcpu, dr, &val))
3334 kvm_register_write(vcpu, reg, val);
3335 } else
3336 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3337 skip_emulated_instruction(vcpu);
3338 return 1;
3339}
3340
020df079
GN		 3341static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3342{
3343 vmcs_writel(GUEST_DR7, val);
3344}
3345
851ba692 3346static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3347{
06465c5a
AK		 3348 kvm_emulate_cpuid(vcpu);
3349 return 1;
6aa8b732
AK		 3350}
3351
851ba692 3352static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3353{
ad312c7c 3354 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3355 u64 data;
3356
3357 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3358 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3359 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3360 return 1;
3361 }
3362
229456fc 3363 trace_kvm_msr_read(ecx, data);
2714d1d3 3364
6aa8b732 3365 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3366 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3367 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3368 skip_emulated_instruction(vcpu);
3369 return 1;
3370}
3371
851ba692 3372static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3373{
ad312c7c
ZX		 3374 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3375 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3376 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3377
3378 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3379 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3380 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3381 return 1;
3382 }
3383
59200273 3384 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3385 skip_emulated_instruction(vcpu);
3386 return 1;
3387}
3388
851ba692 3389static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 3390{
3842d135 3391 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 3392 return 1;
3393}
3394
851ba692 3395static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3396{
85f455f7
ED		 3397 u32 cpu_based_vm_exec_control;
3398
3399 /* clear pending irq */
3400 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3401 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3402 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3403
3842d135
AK		 3404 kvm_make_request(KVM_REQ_EVENT, vcpu);
3405
a26bf12a 3406 ++vcpu->stat.irq_window_exits;
2714d1d3 3407
c1150d8c
DL		 3408 /*
3409 * If the user space waits to inject interrupts, exit as soon as
3410 * possible
3411 */
8061823a 3412 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3413 vcpu->run->request_interrupt_window &&
8061823a 3414 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3415 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3416 return 0;
3417 }
6aa8b732
AK		 3418 return 1;
3419}
3420
851ba692 3421static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3422{
3423 skip_emulated_instruction(vcpu);
d3bef15f 3424 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3425}
3426
851ba692 3427static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3428{
510043da 3429 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3430 kvm_emulate_hypercall(vcpu);
3431 return 1;
c21415e8
IM		 3432}
3433
851ba692 3434static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3435{
3436 kvm_queue_exception(vcpu, UD_VECTOR);
3437 return 1;
3438}
3439
ec25d5e6
GN		 3440static int handle_invd(struct kvm_vcpu *vcpu)
3441{
51d8b661 3442 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 3443}
3444
851ba692 3445static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3446{
f9c617f6 3447 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3448
3449 kvm_mmu_invlpg(vcpu, exit_qualification);
3450 skip_emulated_instruction(vcpu);
3451 return 1;
3452}
3453
851ba692 3454static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3455{
3456 skip_emulated_instruction(vcpu);
f5f48ee1 3457 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3458 return 1;
3459}
3460
2acf923e
DC		 3461static int handle_xsetbv(struct kvm_vcpu *vcpu)
3462{
3463 u64 new_bv = kvm_read_edx_eax(vcpu);
3464 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3465
3466 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3467 skip_emulated_instruction(vcpu);
3468 return 1;
3469}
3470
851ba692 3471static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3472{
51d8b661 3473 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 3474}
3475
851ba692 3476static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3477{
60637aac 3478 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3479 unsigned long exit_qualification;
e269fb21
JK		 3480 bool has_error_code = false;
3481 u32 error_code = 0;
37817f29 3482 u16 tss_selector;
64a7ec06
GN		 3483 int reason, type, idt_v;
3484
3485 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3486 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3487
3488 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3489
3490 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3491 if (reason == TASK_SWITCH_GATE && idt_v) {
3492 switch (type) {
3493 case INTR_TYPE_NMI_INTR:
3494 vcpu->arch.nmi_injected = false;
3495 if (cpu_has_virtual_nmis())
3496 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3497 GUEST_INTR_STATE_NMI);
3498 break;
3499 case INTR_TYPE_EXT_INTR:
66fd3f7f 3500 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3501 kvm_clear_interrupt_queue(vcpu);
3502 break;
3503 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3504 if (vmx->idt_vectoring_info &
3505 VECTORING_INFO_DELIVER_CODE_MASK) {
3506 has_error_code = true;
3507 error_code =
3508 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3509 }
3510 /* fall through */
64a7ec06
GN		 3511 case INTR_TYPE_SOFT_EXCEPTION:
3512 kvm_clear_exception_queue(vcpu);
3513 break;
3514 default:
3515 break;
3516 }
60637aac 3517 }
37817f29
IE		 3518 tss_selector = exit_qualification;
3519
64a7ec06
GN		 3520 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3521 type != INTR_TYPE_EXT_INTR &&
3522 type != INTR_TYPE_NMI_INTR))
3523 skip_emulated_instruction(vcpu);
3524
acb54517
GN		 3525 if (kvm_task_switch(vcpu, tss_selector, reason,
3526 has_error_code, error_code) == EMULATE_FAIL) {
3527 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3528 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3529 vcpu->run->internal.ndata = 0;
42dbaa5a 3530 return 0;
acb54517 3531 }
42dbaa5a
JK		 3532
3533 /* clear all local breakpoint enable flags */
3534 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3535
3536 /*
3537 * TODO: What about debug traps on tss switch?
3538 * Are we supposed to inject them and update dr6?
3539 */
3540
3541 return 1;
37817f29
IE		 3542}
3543
851ba692 3544static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3545{
f9c617f6 3546 unsigned long exit_qualification;
1439442c 3547 gpa_t gpa;
1439442c 3548 int gla_validity;
1439442c 3549
f9c617f6 3550 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3551
3552 if (exit_qualification & (1 << 6)) {
3553 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3554 return -EINVAL;
1439442c
SY		 3555 }
3556
3557 gla_validity = (exit_qualification >> 7) & 0x3;
3558 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3559 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3560 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3561 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3562 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3563 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3564 (long unsigned int)exit_qualification);
851ba692
AK		 3565 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3566 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3567 return 0;
1439442c
SY		 3568 }
3569
3570 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3571 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 3572 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 3573}
3574
68f89400
MT		 3575static u64 ept_rsvd_mask(u64 spte, int level)
3576{
3577 int i;
3578 u64 mask = 0;
3579
3580 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3581 mask |= (1ULL << i);
3582
3583 if (level > 2)
3584 /* bits 7:3 reserved */
3585 mask |= 0xf8;
3586 else if (level == 2) {
3587 if (spte & (1ULL << 7))
3588 /* 2MB ref, bits 20:12 reserved */
3589 mask |= 0x1ff000;
3590 else
3591 /* bits 6:3 reserved */
3592 mask |= 0x78;
3593 }
3594
3595 return mask;
3596}
3597
3598static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3599 int level)
3600{
3601 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3602
3603 /* 010b (write-only) */
3604 WARN_ON((spte & 0x7) == 0x2);
3605
3606 /* 110b (write/execute) */
3607 WARN_ON((spte & 0x7) == 0x6);
3608
3609 /* 100b (execute-only) and value not supported by logical processor */
3610 if (!cpu_has_vmx_ept_execute_only())
3611 WARN_ON((spte & 0x7) == 0x4);
3612
3613 /* not 000b */
3614 if ((spte & 0x7)) {
3615 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3616
3617 if (rsvd_bits != 0) {
3618 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3619 __func__, rsvd_bits);
3620 WARN_ON(1);
3621 }
3622
3623 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3624 u64 ept_mem_type = (spte & 0x38) >> 3;
3625
3626 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3627 ept_mem_type == 7) {
3628 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3629 __func__, ept_mem_type);
3630 WARN_ON(1);
3631 }
3632 }
3633 }
3634}
3635
851ba692 3636static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3637{
3638 u64 sptes[4];
3639 int nr_sptes, i;
3640 gpa_t gpa;
3641
3642 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3643
3644 printk(KERN_ERR "EPT: Misconfiguration.\n");
3645 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3646
3647 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3648
3649 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3650 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3651
851ba692
AK		 3652 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3653 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3654
3655 return 0;
3656}
3657
851ba692 3658static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3659{
3660 u32 cpu_based_vm_exec_control;
3661
3662 /* clear pending NMI */
3663 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3664 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3665 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3666 ++vcpu->stat.nmi_window_exits;
3842d135 3667 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 3668
3669 return 1;
3670}
3671
80ced186 3672static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3673{
8b3079a5
AK		 3674 struct vcpu_vmx *vmx = to_vmx(vcpu);
3675 enum emulation_result err = EMULATE_DONE;
80ced186 3676 int ret = 1;
49e9d557
AK		 3677 u32 cpu_exec_ctrl;
3678 bool intr_window_requested;
3679
3680 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3681 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 3682
3683 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 3684 if (intr_window_requested
3685 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3686 return handle_interrupt_window(&vmx->vcpu);
3687
51d8b661 3688 err = emulate_instruction(vcpu, 0);
ea953ef0 3689
80ced186
MG		 3690 if (err == EMULATE_DO_MMIO) {
3691 ret = 0;
3692 goto out;
3693 }
1d5a4d9b 3694
6d77dbfc
GN		 3695 if (err != EMULATE_DONE)
3696 return 0;
ea953ef0
MG		 3697
3698 if (signal_pending(current))
80ced186 3699 goto out;
ea953ef0
MG		 3700 if (need_resched())
3701 schedule();
3702 }
3703
80ced186
MG		 3704 vmx->emulation_required = 0;
3705out:
3706 return ret;
ea953ef0
MG		 3707}
3708
4b8d54f9
ZE		 3709/*
3710 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3711 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3712 */
9fb41ba8 3713static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3714{
3715 skip_emulated_instruction(vcpu);
3716 kvm_vcpu_on_spin(vcpu);
3717
3718 return 1;
3719}
3720
59708670
SY		 3721static int handle_invalid_op(struct kvm_vcpu *vcpu)
3722{
3723 kvm_queue_exception(vcpu, UD_VECTOR);
3724 return 1;
3725}
3726
6aa8b732
AK		 3727/*
3728 * The exit handlers return 1 if the exit was handled fully and guest execution
3729 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3730 * to be done to userspace and return 0.
3731 */
851ba692 3732static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3733 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3734 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3735 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3736 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3737 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3738 [EXIT_REASON_CR_ACCESS] = handle_cr,
3739 [EXIT_REASON_DR_ACCESS] = handle_dr,
3740 [EXIT_REASON_CPUID] = handle_cpuid,
3741 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3742 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3743 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3744 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 3745 [EXIT_REASON_INVD] = handle_invd,
a7052897 3746 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3747 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3748 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3749 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3750 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3751 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3752 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3753 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3754 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3755 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3756 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3757 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3758 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3759 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3760 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3761 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3762 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3763 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3764 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3765 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3766 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3767 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3768};
3769
3770static const int kvm_vmx_max_exit_handlers =
50a3485c 3771 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 3772
586f9607
AK		 3773static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3774{
3775 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3776 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3777}
3778
6aa8b732
AK		 3779/*
3780 * The guest has exited. See if we can fix it or if we need userspace
3781 * assistance.
3782 */
851ba692 3783static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3784{
29bd8a78 3785 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3786 u32 exit_reason = vmx->exit_reason;
1155f76a 3787 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3788
aa17911e 3789 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 3790
80ced186
MG		 3791 /* If guest state is invalid, start emulating */
3792 if (vmx->emulation_required && emulate_invalid_guest_state)
3793 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3794
5120702e
MG		 3795 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3796 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3797 vcpu->run->fail_entry.hardware_entry_failure_reason
3798 = exit_reason;
3799 return 0;
3800 }
3801
29bd8a78 3802 if (unlikely(vmx->fail)) {
851ba692
AK		 3803 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3804 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3805 = vmcs_read32(VM_INSTRUCTION_ERROR);
3806 return 0;
3807 }
6aa8b732 3808
d77c26fc 3809 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3810 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3811 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3812 exit_reason != EXIT_REASON_TASK_SWITCH))
3813 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3814 "(0x%x) and exit reason is 0x%x\n",
3815 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3816
3817 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3818 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3819 vmx->soft_vnmi_blocked = 0;
3b86cd99 3820 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3821 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3822 /*
3823 * This CPU don't support us in finding the end of an
3824 * NMI-blocked window if the guest runs with IRQs
3825 * disabled. So we pull the trigger after 1 s of
3826 * futile waiting, but inform the user about this.
3827 */
3828 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3829 "state on VCPU %d after 1 s timeout\n",
3830 __func__, vcpu->vcpu_id);
3831 vmx->soft_vnmi_blocked = 0;
3b86cd99 3832 }
3b86cd99
JK		 3833 }
3834
6aa8b732
AK		 3835 if (exit_reason < kvm_vmx_max_exit_handlers
3836 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3837 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3838 else {
851ba692
AK		 3839 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3840 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3841 }
3842 return 0;
3843}
3844
95ba8273 3845static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3846{
95ba8273 3847 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3848 vmcs_write32(TPR_THRESHOLD, 0);
3849 return;
3850 }
3851
95ba8273 3852 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3853}
3854
51aa01d1 3855static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 3856{
51aa01d1 3857 u32 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 3858
3859 /* Handle machine checks before interrupts are enabled */
3860 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3861 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3862 && is_machine_check(exit_intr_info)))
3863 kvm_machine_check();
3864
20f65983
GN		 3865 /* We need to handle NMIs before interrupts are enabled */
3866 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3867 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3868 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3869 asm("int $2");
ff9d07a0
ZY		 3870 kvm_after_handle_nmi(&vmx->vcpu);
3871 }
51aa01d1 3872}
20f65983 3873
51aa01d1
AK		 3874static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3875{
3876 u32 exit_intr_info = vmx->exit_intr_info;
3877 bool unblock_nmi;
3878 u8 vector;
3879 bool idtv_info_valid;
3880
3881 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 3882
cf393f75
AK		 3883 if (cpu_has_virtual_nmis()) {
3884 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3885 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3886 /*
7b4a25cb 3887 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3888 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3889 * a guest IRET fault.
7b4a25cb
GN		 3890 * SDM 3: 23.2.2 (September 2008)
3891 * Bit 12 is undefined in any of the following cases:
3892 * If the VM exit sets the valid bit in the IDT-vectoring
3893 * information field.
3894 * If the VM exit is due to a double fault.
cf393f75 3895 */
7b4a25cb
GN		 3896 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3897 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3898 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3899 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3900 } else if (unlikely(vmx->soft_vnmi_blocked))
3901 vmx->vnmi_blocked_time +=
3902 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 3903}
3904
83422e17
AK		 3905static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3906 u32 idt_vectoring_info,
3907 int instr_len_field,
3908 int error_code_field)
51aa01d1 3909{
51aa01d1
AK		 3910 u8 vector;
3911 int type;
3912 bool idtv_info_valid;
3913
3914 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 3915
37b96e98
GN		 3916 vmx->vcpu.arch.nmi_injected = false;
3917 kvm_clear_exception_queue(&vmx->vcpu);
3918 kvm_clear_interrupt_queue(&vmx->vcpu);
3919
3920 if (!idtv_info_valid)
3921 return;
3922
3842d135
AK		 3923 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3924
668f612f
AK		 3925 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3926 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3927
64a7ec06 3928 switch (type) {
37b96e98
GN		 3929 case INTR_TYPE_NMI_INTR:
3930 vmx->vcpu.arch.nmi_injected = true;
668f612f 3931 /*
7b4a25cb 3932 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3933 * Clear bit "block by NMI" before VM entry if a NMI
3934 * delivery faulted.
668f612f 3935 */
37b96e98
GN		 3936 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3937 GUEST_INTR_STATE_NMI);
3938 break;
37b96e98 3939 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 3940 vmx->vcpu.arch.event_exit_inst_len =
83422e17 3941 vmcs_read32(instr_len_field);
66fd3f7f
GN		 3942 /* fall through */
3943 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3944 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 3945 u32 err = vmcs_read32(error_code_field);
37b96e98 3946 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3947 } else
3948 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3949 break;
66fd3f7f
GN		 3950 case INTR_TYPE_SOFT_INTR:
3951 vmx->vcpu.arch.event_exit_inst_len =
83422e17 3952 vmcs_read32(instr_len_field);
66fd3f7f 3953 /* fall through */
37b96e98 3954 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3955 kvm_queue_interrupt(&vmx->vcpu, vector,
3956 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3957 break;
3958 default:
3959 break;
f7d9238f 3960 }
cf393f75
AK		 3961}
3962
83422e17
AK		 3963static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3964{
3965 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3966 VM_EXIT_INSTRUCTION_LEN,
3967 IDT_VECTORING_ERROR_CODE);
3968}
3969
b463a6f7
AK		 3970static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3971{
3972 __vmx_complete_interrupts(to_vmx(vcpu),
3973 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3974 VM_ENTRY_INSTRUCTION_LEN,
3975 VM_ENTRY_EXCEPTION_ERROR_CODE);
3976
3977 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3978}
3979
c801949d
AK		 3980#ifdef CONFIG_X86_64
3981#define R "r"
3982#define Q "q"
3983#else
3984#define R "e"
3985#define Q "l"
3986#endif
3987
a3b5ba49 3988static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3989{
a2fa3e9f 3990 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b
AK		 3991
3992 /* Record the guest's net vcpu time for enforced NMI injections. */
3993 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3994 vmx->entry_time = ktime_get();
3995
3996 /* Don't enter VMX if guest state is invalid, let the exit handler
3997 start emulation until we arrive back to a valid state */
3998 if (vmx->emulation_required && emulate_invalid_guest_state)
3999 return;
4000
4001 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4002 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4003 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4004 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4005
4006 /* When single-stepping over STI and MOV SS, we must clear the
4007 * corresponding interruptibility bits in the guest state. Otherwise
4008 * vmentry fails as it then expects bit 14 (BS) in pending debug
4009 * exceptions being set, but that's not correct for the guest debugging
4010 * case. */
4011 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4012 vmx_set_interrupt_shadow(vcpu, 0);
4013
4014 asm(
6aa8b732 4015 /* Store host registers */
c801949d 4016 "push %%"R"dx; push %%"R"bp;"
40712fae 4017 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 4018 "push %%"R"cx \n\t"
313dbd49
AK		 4019 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4020 "je 1f \n\t"
4021 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 4022 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 4023 "1: \n\t"
d3edefc0
AK		 4024 /* Reload cr2 if changed */
4025 "mov %c[cr2](%0), %%"R"ax \n\t"
4026 "mov %%cr2, %%"R"dx \n\t"
4027 "cmp %%"R"ax, %%"R"dx \n\t"
4028 "je 2f \n\t"
4029 "mov %%"R"ax, %%cr2 \n\t"
4030 "2: \n\t"
6aa8b732 4031 /* Check if vmlaunch of vmresume is needed */
e08aa78a 4032 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 4033 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 4034 "mov %c[rax](%0), %%"R"ax \n\t"
4035 "mov %c[rbx](%0), %%"R"bx \n\t"
4036 "mov %c[rdx](%0), %%"R"dx \n\t"
4037 "mov %c[rsi](%0), %%"R"si \n\t"
4038 "mov %c[rdi](%0), %%"R"di \n\t"
4039 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 4040#ifdef CONFIG_X86_64
e08aa78a
AK		 4041 "mov %c[r8](%0), %%r8 \n\t"
4042 "mov %c[r9](%0), %%r9 \n\t"
4043 "mov %c[r10](%0), %%r10 \n\t"
4044 "mov %c[r11](%0), %%r11 \n\t"
4045 "mov %c[r12](%0), %%r12 \n\t"
4046 "mov %c[r13](%0), %%r13 \n\t"
4047 "mov %c[r14](%0), %%r14 \n\t"
4048 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 4049#endif
c801949d
AK		 4050 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4051
6aa8b732 4052 /* Enter guest mode */
cd2276a7 4053 "jne .Llaunched \n\t"
4ecac3fd 4054 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 4055 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 4056 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 4057 ".Lkvm_vmx_return: "
6aa8b732 4058 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 4059 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4060 "pop %0 \n\t"
c801949d
AK		 4061 "mov %%"R"ax, %c[rax](%0) \n\t"
4062 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 4063 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 4064 "mov %%"R"dx, %c[rdx](%0) \n\t"
4065 "mov %%"R"si, %c[rsi](%0) \n\t"
4066 "mov %%"R"di, %c[rdi](%0) \n\t"
4067 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 4068#ifdef CONFIG_X86_64
e08aa78a
AK		 4069 "mov %%r8, %c[r8](%0) \n\t"
4070 "mov %%r9, %c[r9](%0) \n\t"
4071 "mov %%r10, %c[r10](%0) \n\t"
4072 "mov %%r11, %c[r11](%0) \n\t"
4073 "mov %%r12, %c[r12](%0) \n\t"
4074 "mov %%r13, %c[r13](%0) \n\t"
4075 "mov %%r14, %c[r14](%0) \n\t"
4076 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 4077#endif
c801949d
AK		 4078 "mov %%cr2, %%"R"ax \n\t"
4079 "mov %%"R"ax, %c[cr2](%0) \n\t"
4080
1c696d0e 4081 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 4082 "setbe %c[fail](%0) \n\t"
4083 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4084 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4085 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 4086 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 4087 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4088 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4089 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4090 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4091 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4092 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4093 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4094#ifdef CONFIG_X86_64
ad312c7c
ZX		 4095 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4096 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4097 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4098 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4099 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4100 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4101 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4102 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4103#endif
40712fae
AK		 4104 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4105 [wordsize]"i"(sizeof(ulong))
c2036300 4106 : "cc", "memory"
07d6f555 4107 , R"ax", R"bx", R"di", R"si"
c2036300 4108#ifdef CONFIG_X86_64
c2036300
LV		 4109 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4110#endif
4111 );
6aa8b732 4112
6de4f3ad 4113 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
aff48baa
AK		 4114 | (1 << VCPU_EXREG_PDPTR)
4115 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 4116 vcpu->arch.regs_dirty = 0;
4117
1155f76a
AK		 4118 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4119
d77c26fc 4120 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4121 vmx->launched = 1;
1b6269db 4122
51aa01d1
AK		 4123 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4124 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4125
4126 vmx_complete_atomic_exit(vmx);
4127 vmx_recover_nmi_blocking(vmx);
cf393f75 4128 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4129}
4130
c801949d
AK		 4131#undef R
4132#undef Q
4133
6aa8b732
AK		 4134static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4135{
a2fa3e9f
GH		 4136 struct vcpu_vmx *vmx = to_vmx(vcpu);
4137
4138 if (vmx->vmcs) {
543e4243 4139 vcpu_clear(vmx);
a2fa3e9f
GH		 4140 free_vmcs(vmx->vmcs);
4141 vmx->vmcs = NULL;
6aa8b732
AK		 4142 }
4143}
4144
4145static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4146{
fb3f0f51
RR		 4147 struct vcpu_vmx *vmx = to_vmx(vcpu);
4148
cdbecfc3 4149 free_vpid(vmx);
6aa8b732 4150 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4151 kfree(vmx->guest_msrs);
4152 kvm_vcpu_uninit(vcpu);
a4770347 4153 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4154}
4155
4610c9cc
DX		 4156static inline void vmcs_init(struct vmcs *vmcs)
4157{
4158 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4159
4160 if (!vmm_exclusive)
4161 kvm_cpu_vmxon(phys_addr);
4162
4163 vmcs_clear(vmcs);
4164
4165 if (!vmm_exclusive)
4166 kvm_cpu_vmxoff();
4167}
4168
fb3f0f51 4169static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4170{
fb3f0f51 4171 int err;
c16f862d 4172 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4173 int cpu;
6aa8b732 4174
a2fa3e9f 4175 if (!vmx)
fb3f0f51
RR		 4176 return ERR_PTR(-ENOMEM);
4177
2384d2b3
SY		 4178 allocate_vpid(vmx);
4179
fb3f0f51
RR		 4180 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4181 if (err)
4182 goto free_vcpu;
965b58a5 4183
a2fa3e9f 4184 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4185 if (!vmx->guest_msrs) {
4186 err = -ENOMEM;
4187 goto uninit_vcpu;
4188 }
965b58a5 4189
a2fa3e9f
GH		 4190 vmx->vmcs = alloc_vmcs();
4191 if (!vmx->vmcs)
fb3f0f51 4192 goto free_msrs;
a2fa3e9f 4193
4610c9cc 4194 vmcs_init(vmx->vmcs);
a2fa3e9f 4195
15ad7146
AK		 4196 cpu = get_cpu();
4197 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 4198 vmx->vcpu.cpu = cpu;
8b9cf98c 4199 err = vmx_vcpu_setup(vmx);
fb3f0f51 4200 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4201 put_cpu();
fb3f0f51
RR		 4202 if (err)
4203 goto free_vmcs;
5e4a0b3c
MT		 4204 if (vm_need_virtualize_apic_accesses(kvm))
4205 if (alloc_apic_access_page(kvm) != 0)
4206 goto free_vmcs;
fb3f0f51 4207
b927a3ce
SY		 4208 if (enable_ept) {
4209 if (!kvm->arch.ept_identity_map_addr)
4210 kvm->arch.ept_identity_map_addr =
4211 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 4212 err = -ENOMEM;
b7ebfb05
SY		 4213 if (alloc_identity_pagetable(kvm) != 0)
4214 goto free_vmcs;
93ea5388
GN		 4215 if (!init_rmode_identity_map(kvm))
4216 goto free_vmcs;
b927a3ce 4217 }
b7ebfb05 4218
fb3f0f51
RR		 4219 return &vmx->vcpu;
4220
4221free_vmcs:
4222 free_vmcs(vmx->vmcs);
4223free_msrs:
fb3f0f51
RR		 4224 kfree(vmx->guest_msrs);
4225uninit_vcpu:
4226 kvm_vcpu_uninit(&vmx->vcpu);
4227free_vcpu:
cdbecfc3 4228 free_vpid(vmx);
a4770347 4229 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4230 return ERR_PTR(err);
6aa8b732
AK		 4231}
4232
002c7f7c
YS		 4233static void __init vmx_check_processor_compat(void *rtn)
4234{
4235 struct vmcs_config vmcs_conf;
4236
4237 *(int *)rtn = 0;
4238 if (setup_vmcs_config(&vmcs_conf) < 0)
4239 *(int *)rtn = -EIO;
4240 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4241 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4242 smp_processor_id());
4243 *(int *)rtn = -EIO;
4244 }
4245}
4246
67253af5
SY		 4247static int get_ept_level(void)
4248{
4249 return VMX_EPT_DEFAULT_GAW + 1;
4250}
4251
4b12f0de 4252static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4253{
4b12f0de
SY		 4254 u64 ret;
4255
522c68c4
SY		 4256 /* For VT-d and EPT combination
4257 * 1. MMIO: always map as UC
4258 * 2. EPT with VT-d:
4259 * a. VT-d without snooping control feature: can't guarantee the
4260 * result, try to trust guest.
4261 * b. VT-d with snooping control feature: snooping control feature of
4262 * VT-d engine can guarantee the cache correctness. Just set it
4263 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4264 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4265 * consistent with host MTRR
4266 */
4b12f0de
SY		 4267 if (is_mmio)
4268 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4269 else if (vcpu->kvm->arch.iommu_domain &&
4270 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4271 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4272 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4273 else
522c68c4 4274 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4275 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4276
4277 return ret;
64d4d521
SY		 4278}
4279
f4c9e87c
AK		 4280#define _ER(x) { EXIT_REASON_##x, #x }
4281
229456fc 4282static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4283 _ER(EXCEPTION_NMI),
4284 _ER(EXTERNAL_INTERRUPT),
4285 _ER(TRIPLE_FAULT),
4286 _ER(PENDING_INTERRUPT),
4287 _ER(NMI_WINDOW),
4288 _ER(TASK_SWITCH),
4289 _ER(CPUID),
4290 _ER(HLT),
4291 _ER(INVLPG),
4292 _ER(RDPMC),
4293 _ER(RDTSC),
4294 _ER(VMCALL),
4295 _ER(VMCLEAR),
4296 _ER(VMLAUNCH),
4297 _ER(VMPTRLD),
4298 _ER(VMPTRST),
4299 _ER(VMREAD),
4300 _ER(VMRESUME),
4301 _ER(VMWRITE),
4302 _ER(VMOFF),
4303 _ER(VMON),
4304 _ER(CR_ACCESS),
4305 _ER(DR_ACCESS),
4306 _ER(IO_INSTRUCTION),
4307 _ER(MSR_READ),
4308 _ER(MSR_WRITE),
4309 _ER(MWAIT_INSTRUCTION),
4310 _ER(MONITOR_INSTRUCTION),
4311 _ER(PAUSE_INSTRUCTION),
4312 _ER(MCE_DURING_VMENTRY),
4313 _ER(TPR_BELOW_THRESHOLD),
4314 _ER(APIC_ACCESS),
4315 _ER(EPT_VIOLATION),
4316 _ER(EPT_MISCONFIG),
4317 _ER(WBINVD),
229456fc
MT		 4318 { -1, NULL }
4319};
4320
f4c9e87c
AK		 4321#undef _ER
4322
17cc3935 4323static int vmx_get_lpage_level(void)
344f414f 4324{
878403b7
SY		 4325 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4326 return PT_DIRECTORY_LEVEL;
4327 else
4328 /* For shadow and EPT supported 1GB page */
4329 return PT_PDPE_LEVEL;
344f414f
JR		 4330}
4331
0e851880
SY		 4332static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4333{
4e47c7a6
SY		 4334 struct kvm_cpuid_entry2 *best;
4335 struct vcpu_vmx *vmx = to_vmx(vcpu);
4336 u32 exec_control;
4337
4338 vmx->rdtscp_enabled = false;
4339 if (vmx_rdtscp_supported()) {
4340 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4341 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4342 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4343 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4344 vmx->rdtscp_enabled = true;
4345 else {
4346 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4347 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4348 exec_control);
4349 }
4350 }
4351 }
0e851880
SY		 4352}
4353
d4330ef2
JR		 4354static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4355{
4356}
4357
cbdd1bea 4358static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4359 .cpu_has_kvm_support = cpu_has_kvm_support,
4360 .disabled_by_bios = vmx_disabled_by_bios,
4361 .hardware_setup = hardware_setup,
4362 .hardware_unsetup = hardware_unsetup,
002c7f7c 4363 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4364 .hardware_enable = hardware_enable,
4365 .hardware_disable = hardware_disable,
04547156 4366 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4367
4368 .vcpu_create = vmx_create_vcpu,
4369 .vcpu_free = vmx_free_vcpu,
04d2cc77 4370 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4371
04d2cc77 4372 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4373 .vcpu_load = vmx_vcpu_load,
4374 .vcpu_put = vmx_vcpu_put,
4375
4376 .set_guest_debug = set_guest_debug,
4377 .get_msr = vmx_get_msr,
4378 .set_msr = vmx_set_msr,
4379 .get_segment_base = vmx_get_segment_base,
4380 .get_segment = vmx_get_segment,
4381 .set_segment = vmx_set_segment,
2e4d2653 4382 .get_cpl = vmx_get_cpl,
6aa8b732 4383 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4384 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 4385 .decache_cr3 = vmx_decache_cr3,
25c4c276 4386 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4387 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4388 .set_cr3 = vmx_set_cr3,
4389 .set_cr4 = vmx_set_cr4,
6aa8b732 4390 .set_efer = vmx_set_efer,
6aa8b732
AK		 4391 .get_idt = vmx_get_idt,
4392 .set_idt = vmx_set_idt,
4393 .get_gdt = vmx_get_gdt,
4394 .set_gdt = vmx_set_gdt,
020df079 4395 .set_dr7 = vmx_set_dr7,
5fdbf976 4396 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4397 .get_rflags = vmx_get_rflags,
4398 .set_rflags = vmx_set_rflags,
ebcbab4c 4399 .fpu_activate = vmx_fpu_activate,
02daab21 4400 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4401
4402 .tlb_flush = vmx_flush_tlb,
6aa8b732 4403
6aa8b732 4404 .run = vmx_vcpu_run,
6062d012 4405 .handle_exit = vmx_handle_exit,
6aa8b732 4406 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4407 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4408 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4409 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4410 .set_irq = vmx_inject_irq,
95ba8273 4411 .set_nmi = vmx_inject_nmi,
298101da 4412 .queue_exception = vmx_queue_exception,
b463a6f7 4413 .cancel_injection = vmx_cancel_injection,
78646121 4414 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4415 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4416 .get_nmi_mask = vmx_get_nmi_mask,
4417 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4418 .enable_nmi_window = enable_nmi_window,
4419 .enable_irq_window = enable_irq_window,
4420 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4421
cbc94022 4422 .set_tss_addr = vmx_set_tss_addr,
67253af5 4423 .get_tdp_level = get_ept_level,
4b12f0de 4424 .get_mt_mask = vmx_get_mt_mask,
229456fc 4425
586f9607 4426 .get_exit_info = vmx_get_exit_info,
229456fc 4427 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 4428
17cc3935 4429 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4430
4431 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4432
4433 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4434
4435 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4436
4437 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA		 4438
4439 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 4440 .adjust_tsc_offset = vmx_adjust_tsc_offset,
1c97f0a0
JR		 4441
4442 .set_tdp_cr3 = vmx_set_cr3,
6aa8b732
AK		 4443};
4444
4445static int __init vmx_init(void)
4446{
26bb0981
AK		 4447 int r, i;
4448
4449 rdmsrl_safe(MSR_EFER, &host_efer);
4450
4451 for (i = 0; i < NR_VMX_MSR; ++i)
4452 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4453
3e7c73e9 4454 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4455 if (!vmx_io_bitmap_a)
4456 return -ENOMEM;
4457
3e7c73e9 4458 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4459 if (!vmx_io_bitmap_b) {
4460 r = -ENOMEM;
4461 goto out;
4462 }
4463
5897297b
AK		 4464 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4465 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4466 r = -ENOMEM;
4467 goto out1;
4468 }
4469
5897297b
AK		 4470 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4471 if (!vmx_msr_bitmap_longmode) {
4472 r = -ENOMEM;
4473 goto out2;
4474 }
4475
fdef3ad1
HQ		 4476 /*
4477 * Allow direct access to the PC debug port (it is often used for I/O
4478 * delays, but the vmexits simply slow things down).
4479 */
3e7c73e9
AK		 4480 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4481 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4482
3e7c73e9 4483 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4484
5897297b
AK		 4485 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4486 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4487
2384d2b3
SY		 4488 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4489
0ee75bea
AK		 4490 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4491 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4492 if (r)
5897297b 4493 goto out3;
25c5f225 4494
5897297b
AK		 4495 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4496 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4497 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4498 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4499 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4500 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4501
089d034e 4502 if (enable_ept) {
1439442c 4503 bypass_guest_pf = 0;
534e38b4 4504 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4505 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4506 kvm_enable_tdp();
4507 } else
4508 kvm_disable_tdp();
1439442c 4509
c7addb90
AK		 4510 if (bypass_guest_pf)
4511 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4512
fdef3ad1
HQ		 4513 return 0;
4514
5897297b
AK		 4515out3:
4516 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4517out2:
5897297b 4518 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4519out1:
3e7c73e9 4520 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4521out:
3e7c73e9 4522 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4523 return r;
6aa8b732
AK		 4524}
4525
4526static void __exit vmx_exit(void)
4527{
5897297b
AK		 4528 free_page((unsigned long)vmx_msr_bitmap_legacy);
4529 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4530 free_page((unsigned long)vmx_io_bitmap_b);
4531 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4532
cb498ea2 4533 kvm_exit();
6aa8b732
AK		 4534}
4535
4536module_init(vmx_init)
4537module_exit(vmx_exit)
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