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KVM: X86: Implement call-back to propagate virtual_tsc_khz
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
443381a8
AL		 72static int __read_mostly yield_on_hlt = 1;
73module_param(yield_on_hlt, bool, S_IRUGO);
74
cdc0e244
AK		 75#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77#define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 80 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 81#define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 83#define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
85 | X86_CR4_OSXMMEXCPT)
86
cdc0e244
AK		 87#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
89
78ac8b47
AK		 90#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
91
4b8d54f9
ZE		 92/*
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 96 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
102 */
00c25bce 103#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 104#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
106module_param(ple_gap, int, S_IRUGO);
107
108static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
109module_param(ple_window, int, S_IRUGO);
110
61d2ef2c
AK		 111#define NR_AUTOLOAD_MSRS 1
112
a2fa3e9f
GH		 113struct vmcs {
114 u32 revision_id;
115 u32 abort;
116 char data[0];
117};
118
26bb0981
AK		 119struct shared_msr_entry {
120 unsigned index;
121 u64 data;
d5696725 122 u64 mask;
26bb0981
AK		 123};
124
a2fa3e9f 125struct vcpu_vmx {
fb3f0f51 126 struct kvm_vcpu vcpu;
543e4243 127 struct list_head local_vcpus_link;
313dbd49 128 unsigned long host_rsp;
a2fa3e9f 129 int launched;
29bd8a78 130 u8 fail;
69c73028 131 u8 cpl;
9d58b931 132 bool nmi_known_unmasked;
51aa01d1 133 u32 exit_intr_info;
1155f76a 134 u32 idt_vectoring_info;
6de12732 135 ulong rflags;
26bb0981 136 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 137 int nmsrs;
138 int save_nmsrs;
a2fa3e9f 139#ifdef CONFIG_X86_64
44ea2b17
AK		 140 u64 msr_host_kernel_gs_base;
141 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 142#endif
143 struct vmcs *vmcs;
61d2ef2c
AK		 144 struct msr_autoload {
145 unsigned nr;
146 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
147 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
148 } msr_autoload;
a2fa3e9f
GH		 149 struct {
150 int loaded;
151 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 152 int gs_ldt_reload_needed;
153 int fs_reload_needed;
d77c26fc 154 } host_state;
9c8cba37 155 struct {
7ffd92c5 156 int vm86_active;
78ac8b47 157 ulong save_rflags;
7ffd92c5
AK		 158 struct kvm_save_segment {
159 u16 selector;
160 unsigned long base;
161 u32 limit;
162 u32 ar;
163 } tr, es, ds, fs, gs;
9c8cba37 164 } rmode;
2384d2b3 165 int vpid;
04fa4d32 166 bool emulation_required;
3b86cd99
JK		 167
168 /* Support for vnmi-less CPUs */
169 int soft_vnmi_blocked;
170 ktime_t entry_time;
171 s64 vnmi_blocked_time;
a0861c02 172 u32 exit_reason;
4e47c7a6
SY		 173
174 bool rdtscp_enabled;
a2fa3e9f
GH		 175};
176
177static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
178{
fb3f0f51 179 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 180}
181
4e1096d2 182static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 183static void kvm_cpu_vmxon(u64 addr);
184static void kvm_cpu_vmxoff(void);
aff48baa 185static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 186static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 187
6aa8b732
AK		 188static DEFINE_PER_CPU(struct vmcs *, vmxarea);
189static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 190static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
3444d7da 191static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 192
3e7c73e9
AK		 193static unsigned long *vmx_io_bitmap_a;
194static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 195static unsigned long *vmx_msr_bitmap_legacy;
196static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 197
110312c8
AK		 198static bool cpu_has_load_ia32_efer;
199
2384d2b3
SY		 200static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
201static DEFINE_SPINLOCK(vmx_vpid_lock);
202
1c3d14fe 203static struct vmcs_config {
6aa8b732
AK		 204 int size;
205 int order;
206 u32 revision_id;
1c3d14fe
YS		 207 u32 pin_based_exec_ctrl;
208 u32 cpu_based_exec_ctrl;
f78e0e2e 209 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 210 u32 vmexit_ctrl;
211 u32 vmentry_ctrl;
212} vmcs_config;
6aa8b732 213
efff9e53 214static struct vmx_capability {
d56f546d
SY		 215 u32 ept;
216 u32 vpid;
217} vmx_capability;
218
6aa8b732
AK		 219#define VMX_SEGMENT_FIELD(seg) \
220 [VCPU_SREG_##seg] = { \
221 .selector = GUEST_##seg##_SELECTOR, \
222 .base = GUEST_##seg##_BASE, \
223 .limit = GUEST_##seg##_LIMIT, \
224 .ar_bytes = GUEST_##seg##_AR_BYTES, \
225 }
226
227static struct kvm_vmx_segment_field {
228 unsigned selector;
229 unsigned base;
230 unsigned limit;
231 unsigned ar_bytes;
232} kvm_vmx_segment_fields[] = {
233 VMX_SEGMENT_FIELD(CS),
234 VMX_SEGMENT_FIELD(DS),
235 VMX_SEGMENT_FIELD(ES),
236 VMX_SEGMENT_FIELD(FS),
237 VMX_SEGMENT_FIELD(GS),
238 VMX_SEGMENT_FIELD(SS),
239 VMX_SEGMENT_FIELD(TR),
240 VMX_SEGMENT_FIELD(LDTR),
241};
242
26bb0981
AK		 243static u64 host_efer;
244
6de4f3ad
AK		 245static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
246
4d56c8a7 247/*
8c06585d 248 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 249 * away by decrementing the array size.
250 */
6aa8b732 251static const u32 vmx_msr_index[] = {
05b3e0c2 252#ifdef CONFIG_X86_64
44ea2b17 253 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 254#endif
8c06585d 255 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 256};
9d8f549d 257#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 258
31299944 259static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 260{
261 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
262 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 263 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 264}
265
31299944 266static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 267{
268 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
269 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 270 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 271}
272
31299944 273static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 274{
275 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
276 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 277 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 278}
279
31299944 280static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 281{
282 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
283 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
284}
285
31299944 286static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 287{
288 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
289 INTR_INFO_VALID_MASK)) ==
290 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
291}
292
31299944 293static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 294{
04547156 295 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 296}
297
31299944 298static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 299{
04547156 300 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 301}
302
31299944 303static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 304{
04547156 305 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 306}
307
31299944 308static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 309{
04547156
SY		 310 return vmcs_config.cpu_based_exec_ctrl &
311 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 312}
313
774ead3a 314static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 315{
04547156
SY		 316 return vmcs_config.cpu_based_2nd_exec_ctrl &
317 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
318}
319
320static inline bool cpu_has_vmx_flexpriority(void)
321{
322 return cpu_has_vmx_tpr_shadow() &&
323 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 324}
325
e799794e
MT		 326static inline bool cpu_has_vmx_ept_execute_only(void)
327{
31299944 328 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 329}
330
331static inline bool cpu_has_vmx_eptp_uncacheable(void)
332{
31299944 333 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 334}
335
336static inline bool cpu_has_vmx_eptp_writeback(void)
337{
31299944 338 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 339}
340
341static inline bool cpu_has_vmx_ept_2m_page(void)
342{
31299944 343 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 344}
345
878403b7
SY		 346static inline bool cpu_has_vmx_ept_1g_page(void)
347{
31299944 348 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 349}
350
4bc9b982
SY		 351static inline bool cpu_has_vmx_ept_4levels(void)
352{
353 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
354}
355
31299944 356static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 357{
31299944 358 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 359}
360
31299944 361static inline bool cpu_has_vmx_invept_context(void)
d56f546d 362{
31299944 363 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 364}
365
31299944 366static inline bool cpu_has_vmx_invept_global(void)
d56f546d 367{
31299944 368 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 369}
370
518c8aee
GJ		 371static inline bool cpu_has_vmx_invvpid_single(void)
372{
373 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
374}
375
b9d762fa
GJ		 376static inline bool cpu_has_vmx_invvpid_global(void)
377{
378 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
379}
380
31299944 381static inline bool cpu_has_vmx_ept(void)
d56f546d 382{
04547156
SY		 383 return vmcs_config.cpu_based_2nd_exec_ctrl &
384 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 385}
386
31299944 387static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 388{
389 return vmcs_config.cpu_based_2nd_exec_ctrl &
390 SECONDARY_EXEC_UNRESTRICTED_GUEST;
391}
392
31299944 393static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 394{
395 return vmcs_config.cpu_based_2nd_exec_ctrl &
396 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
397}
398
31299944 399static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 400{
6d3e435e 401 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 402}
403
31299944 404static inline bool cpu_has_vmx_vpid(void)
2384d2b3 405{
04547156
SY		 406 return vmcs_config.cpu_based_2nd_exec_ctrl &
407 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 408}
409
31299944 410static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 411{
412 return vmcs_config.cpu_based_2nd_exec_ctrl &
413 SECONDARY_EXEC_RDTSCP;
414}
415
31299944 416static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 417{
418 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
419}
420
f5f48ee1
SY		 421static inline bool cpu_has_vmx_wbinvd_exit(void)
422{
423 return vmcs_config.cpu_based_2nd_exec_ctrl &
424 SECONDARY_EXEC_WBINVD_EXITING;
425}
426
04547156
SY		 427static inline bool report_flexpriority(void)
428{
429 return flexpriority_enabled;
430}
431
8b9cf98c 432static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 433{
434 int i;
435
a2fa3e9f 436 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 437 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 438 return i;
439 return -1;
440}
441
2384d2b3
SY		 442static inline void __invvpid(int ext, u16 vpid, gva_t gva)
443{
444 struct {
445 u64 vpid : 16;
446 u64 rsvd : 48;
447 u64 gva;
448 } operand = { vpid, 0, gva };
449
4ecac3fd 450 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 451 /* CF==1 or ZF==1 --> rc = -1 */
452 "; ja 1f ; ud2 ; 1:"
453 : : "a"(&operand), "c"(ext) : "cc", "memory");
454}
455
1439442c
SY		 456static inline void __invept(int ext, u64 eptp, gpa_t gpa)
457{
458 struct {
459 u64 eptp, gpa;
460 } operand = {eptp, gpa};
461
4ecac3fd 462 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 463 /* CF==1 or ZF==1 --> rc = -1 */
464 "; ja 1f ; ud2 ; 1:\n"
465 : : "a" (&operand), "c" (ext) : "cc", "memory");
466}
467
26bb0981 468static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 469{
470 int i;
471
8b9cf98c 472 i = __find_msr_index(vmx, msr);
a75beee6 473 if (i >= 0)
a2fa3e9f 474 return &vmx->guest_msrs[i];
8b6d44c7 475 return NULL;
7725f0ba
AK		 476}
477
6aa8b732
AK		 478static void vmcs_clear(struct vmcs *vmcs)
479{
480 u64 phys_addr = __pa(vmcs);
481 u8 error;
482
4ecac3fd 483 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 484 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 485 : "cc", "memory");
486 if (error)
487 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
488 vmcs, phys_addr);
489}
490
7725b894
DX		 491static void vmcs_load(struct vmcs *vmcs)
492{
493 u64 phys_addr = __pa(vmcs);
494 u8 error;
495
496 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 497 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 498 : "cc", "memory");
499 if (error)
500 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
501 vmcs, phys_addr);
502}
503
6aa8b732
AK		 504static void __vcpu_clear(void *arg)
505{
8b9cf98c 506 struct vcpu_vmx *vmx = arg;
d3b2c338 507 int cpu = raw_smp_processor_id();
6aa8b732 508
8b9cf98c 509 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 510 vmcs_clear(vmx->vmcs);
511 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 512 per_cpu(current_vmcs, cpu) = NULL;
543e4243
AK		 513 list_del(&vmx->local_vcpus_link);
514 vmx->vcpu.cpu = -1;
515 vmx->launched = 0;
6aa8b732
AK		 516}
517
8b9cf98c 518static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 519{
eae5ecb5
AK		 520 if (vmx->vcpu.cpu == -1)
521 return;
8691e5a8 522 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 523}
524
1760dd49 525static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 526{
527 if (vmx->vpid == 0)
528 return;
529
518c8aee
GJ		 530 if (cpu_has_vmx_invvpid_single())
531 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 532}
533
b9d762fa
GJ		 534static inline void vpid_sync_vcpu_global(void)
535{
536 if (cpu_has_vmx_invvpid_global())
537 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
538}
539
540static inline void vpid_sync_context(struct vcpu_vmx *vmx)
541{
542 if (cpu_has_vmx_invvpid_single())
1760dd49 543 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 544 else
545 vpid_sync_vcpu_global();
546}
547
1439442c
SY		 548static inline void ept_sync_global(void)
549{
550 if (cpu_has_vmx_invept_global())
551 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
552}
553
554static inline void ept_sync_context(u64 eptp)
555{
089d034e 556 if (enable_ept) {
1439442c
SY		 557 if (cpu_has_vmx_invept_context())
558 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
559 else
560 ept_sync_global();
561 }
562}
563
564static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
565{
089d034e 566 if (enable_ept) {
1439442c
SY		 567 if (cpu_has_vmx_invept_individual_addr())
568 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
569 eptp, gpa);
570 else
571 ept_sync_context(eptp);
572 }
573}
574
6aa8b732
AK		 575static unsigned long vmcs_readl(unsigned long field)
576{
a295673a 577 unsigned long value = 0;
6aa8b732 578
4ecac3fd 579 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
a295673a 580 : "+a"(value) : "d"(field) : "cc");
6aa8b732
AK		 581 return value;
582}
583
584static u16 vmcs_read16(unsigned long field)
585{
586 return vmcs_readl(field);
587}
588
589static u32 vmcs_read32(unsigned long field)
590{
591 return vmcs_readl(field);
592}
593
594static u64 vmcs_read64(unsigned long field)
595{
05b3e0c2 596#ifdef CONFIG_X86_64
6aa8b732
AK		 597 return vmcs_readl(field);
598#else
599 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
600#endif
601}
602
e52de1b8
AK		 603static noinline void vmwrite_error(unsigned long field, unsigned long value)
604{
605 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
606 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
607 dump_stack();
608}
609
6aa8b732
AK		 610static void vmcs_writel(unsigned long field, unsigned long value)
611{
612 u8 error;
613
4ecac3fd 614 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 615 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 616 if (unlikely(error))
617 vmwrite_error(field, value);
6aa8b732
AK		 618}
619
620static void vmcs_write16(unsigned long field, u16 value)
621{
622 vmcs_writel(field, value);
623}
624
625static void vmcs_write32(unsigned long field, u32 value)
626{
627 vmcs_writel(field, value);
628}
629
630static void vmcs_write64(unsigned long field, u64 value)
631{
6aa8b732 632 vmcs_writel(field, value);
7682f2d0 633#ifndef CONFIG_X86_64
6aa8b732
AK		 634 asm volatile ("");
635 vmcs_writel(field+1, value >> 32);
636#endif
637}
638
2ab455cc
AL		 639static void vmcs_clear_bits(unsigned long field, u32 mask)
640{
641 vmcs_writel(field, vmcs_readl(field) & ~mask);
642}
643
644static void vmcs_set_bits(unsigned long field, u32 mask)
645{
646 vmcs_writel(field, vmcs_readl(field) | mask);
647}
648
abd3f2d6
AK		 649static void update_exception_bitmap(struct kvm_vcpu *vcpu)
650{
651 u32 eb;
652
fd7373cc
JK		 653 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
654 (1u << NM_VECTOR) | (1u << DB_VECTOR);
655 if ((vcpu->guest_debug &
656 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
657 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
658 eb |= 1u << BP_VECTOR;
7ffd92c5 659 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 660 eb = ~0;
089d034e 661 if (enable_ept)
1439442c 662 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 663 if (vcpu->fpu_active)
664 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 665 vmcs_write32(EXCEPTION_BITMAP, eb);
666}
667
61d2ef2c
AK		 668static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
669{
670 unsigned i;
671 struct msr_autoload *m = &vmx->msr_autoload;
672
110312c8
AK		 673 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
674 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
675 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
676 return;
677 }
678
61d2ef2c
AK		 679 for (i = 0; i < m->nr; ++i)
680 if (m->guest[i].index == msr)
681 break;
682
683 if (i == m->nr)
684 return;
685 --m->nr;
686 m->guest[i] = m->guest[m->nr];
687 m->host[i] = m->host[m->nr];
688 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
689 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
690}
691
692static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
693 u64 guest_val, u64 host_val)
694{
695 unsigned i;
696 struct msr_autoload *m = &vmx->msr_autoload;
697
110312c8
AK		 698 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
699 vmcs_write64(GUEST_IA32_EFER, guest_val);
700 vmcs_write64(HOST_IA32_EFER, host_val);
701 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
702 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
703 return;
704 }
705
61d2ef2c
AK		 706 for (i = 0; i < m->nr; ++i)
707 if (m->guest[i].index == msr)
708 break;
709
710 if (i == m->nr) {
711 ++m->nr;
712 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
713 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
714 }
715
716 m->guest[i].index = msr;
717 m->guest[i].value = guest_val;
718 m->host[i].index = msr;
719 m->host[i].value = host_val;
720}
721
33ed6329
AK		 722static void reload_tss(void)
723{
33ed6329
AK		 724 /*
725 * VT restores TR but not its size. Useless.
726 */
d359192f 727 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 728 struct desc_struct *descs;
33ed6329 729
d359192f 730 descs = (void *)gdt->address;
33ed6329
AK		 731 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
732 load_TR_desc();
33ed6329
AK		 733}
734
92c0d900 735static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 736{
3a34a881 737 u64 guest_efer;
51c6cf66
AK		 738 u64 ignore_bits;
739
f6801dff 740 guest_efer = vmx->vcpu.arch.efer;
3a34a881 741
51c6cf66
AK		 742 /*
743 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
744 * outside long mode
745 */
746 ignore_bits = EFER_NX | EFER_SCE;
747#ifdef CONFIG_X86_64
748 ignore_bits |= EFER_LMA | EFER_LME;
749 /* SCE is meaningful only in long mode on Intel */
750 if (guest_efer & EFER_LMA)
751 ignore_bits &= ~(u64)EFER_SCE;
752#endif
51c6cf66
AK		 753 guest_efer &= ~ignore_bits;
754 guest_efer |= host_efer & ignore_bits;
26bb0981 755 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 756 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 757
758 clear_atomic_switch_msr(vmx, MSR_EFER);
759 /* On ept, can't emulate nx, and must switch nx atomically */
760 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
761 guest_efer = vmx->vcpu.arch.efer;
762 if (!(guest_efer & EFER_LMA))
763 guest_efer &= ~EFER_LME;
764 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
765 return false;
766 }
767
26bb0981 768 return true;
51c6cf66
AK		 769}
770
2d49ec72
GN		 771static unsigned long segment_base(u16 selector)
772{
d359192f 773 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 774 struct desc_struct *d;
775 unsigned long table_base;
776 unsigned long v;
777
778 if (!(selector & ~3))
779 return 0;
780
d359192f 781 table_base = gdt->address;
2d49ec72
GN		 782
783 if (selector & 4) { /* from ldt */
784 u16 ldt_selector = kvm_read_ldt();
785
786 if (!(ldt_selector & ~3))
787 return 0;
788
789 table_base = segment_base(ldt_selector);
790 }
791 d = (struct desc_struct *)(table_base + (selector & ~7));
792 v = get_desc_base(d);
793#ifdef CONFIG_X86_64
794 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
795 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
796#endif
797 return v;
798}
799
800static inline unsigned long kvm_read_tr_base(void)
801{
802 u16 tr;
803 asm("str %0" : "=g"(tr));
804 return segment_base(tr);
805}
806
04d2cc77 807static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 808{
04d2cc77 809 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 810 int i;
04d2cc77 811
a2fa3e9f 812 if (vmx->host_state.loaded)
33ed6329
AK		 813 return;
814
a2fa3e9f 815 vmx->host_state.loaded = 1;
33ed6329
AK		 816 /*
817 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
818 * allow segment selectors with cpl > 0 or ti == 1.
819 */
d6e88aec 820 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 821 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 822 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 823 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 824 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 825 vmx->host_state.fs_reload_needed = 0;
826 } else {
33ed6329 827 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 828 vmx->host_state.fs_reload_needed = 1;
33ed6329 829 }
9581d442 830 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 831 if (!(vmx->host_state.gs_sel & 7))
832 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 833 else {
834 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 835 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 836 }
837
838#ifdef CONFIG_X86_64
839 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
840 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
841#else
a2fa3e9f
GH		 842 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
843 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 844#endif
707c0874
AK		 845
846#ifdef CONFIG_X86_64
c8770e7b
AK		 847 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
848 if (is_long_mode(&vmx->vcpu))
44ea2b17 849 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 850#endif
26bb0981
AK		 851 for (i = 0; i < vmx->save_nmsrs; ++i)
852 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 853 vmx->guest_msrs[i].data,
854 vmx->guest_msrs[i].mask);
33ed6329
AK		 855}
856
a9b21b62 857static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 858{
a2fa3e9f 859 if (!vmx->host_state.loaded)
33ed6329
AK		 860 return;
861
e1beb1d3 862 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 863 vmx->host_state.loaded = 0;
c8770e7b
AK		 864#ifdef CONFIG_X86_64
865 if (is_long_mode(&vmx->vcpu))
866 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
867#endif
152d3f2f 868 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 869 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 870#ifdef CONFIG_X86_64
9581d442 871 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 872#else
873 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 874#endif
33ed6329 875 }
0a77fe4c
AK		 876 if (vmx->host_state.fs_reload_needed)
877 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 878 reload_tss();
44ea2b17 879#ifdef CONFIG_X86_64
c8770e7b 880 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 881#endif
1c11e713
AK		 882 if (current_thread_info()->status & TS_USEDFPU)
883 clts();
3444d7da 884 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 885}
886
a9b21b62
AK		 887static void vmx_load_host_state(struct vcpu_vmx *vmx)
888{
889 preempt_disable();
890 __vmx_load_host_state(vmx);
891 preempt_enable();
892}
893
6aa8b732
AK		 894/*
895 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
896 * vcpu mutex is already taken.
897 */
15ad7146 898static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 899{
a2fa3e9f 900 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 901 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 902
4610c9cc
DX		 903 if (!vmm_exclusive)
904 kvm_cpu_vmxon(phys_addr);
905 else if (vcpu->cpu != cpu)
8b9cf98c 906 vcpu_clear(vmx);
6aa8b732 907
a2fa3e9f 908 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 909 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 910 vmcs_load(vmx->vmcs);
6aa8b732
AK		 911 }
912
913 if (vcpu->cpu != cpu) {
d359192f 914 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 915 unsigned long sysenter_esp;
916
a8eeb04a 917 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be
DX		 918 local_irq_disable();
919 list_add(&vmx->local_vcpus_link,
920 &per_cpu(vcpus_on_cpu, cpu));
921 local_irq_enable();
922
6aa8b732
AK		 923 /*
924 * Linux uses per-cpu TSS and GDT, so set these when switching
925 * processors.
926 */
d6e88aec 927 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 928 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 929
930 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
931 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
932 }
6aa8b732
AK		 933}
934
935static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
936{
a9b21b62 937 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 938 if (!vmm_exclusive) {
b923e62e 939 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 940 kvm_cpu_vmxoff();
941 }
6aa8b732
AK		 942}
943
5fd86fcf
AK		 944static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
945{
81231c69
AK		 946 ulong cr0;
947
5fd86fcf
AK		 948 if (vcpu->fpu_active)
949 return;
950 vcpu->fpu_active = 1;
81231c69
AK		 951 cr0 = vmcs_readl(GUEST_CR0);
952 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
953 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
954 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 955 update_exception_bitmap(vcpu);
edcafe3c
AK		 956 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
957 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 958}
959
edcafe3c
AK		 960static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
961
5fd86fcf
AK		 962static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
963{
edcafe3c 964 vmx_decache_cr0_guest_bits(vcpu);
81231c69 965 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 966 update_exception_bitmap(vcpu);
edcafe3c
AK		 967 vcpu->arch.cr0_guest_owned_bits = 0;
968 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
969 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 970}
971
6aa8b732
AK		 972static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
973{
78ac8b47 974 unsigned long rflags, save_rflags;
345dcaa8 975
6de12732
AK		 976 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
977 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
978 rflags = vmcs_readl(GUEST_RFLAGS);
979 if (to_vmx(vcpu)->rmode.vm86_active) {
980 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
981 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
982 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
983 }
984 to_vmx(vcpu)->rflags = rflags;
78ac8b47 985 }
6de12732 986 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 987}
988
989static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
990{
6de12732 991 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 992 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 993 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 994 if (to_vmx(vcpu)->rmode.vm86_active) {
995 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 996 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 997 }
6aa8b732
AK		 998 vmcs_writel(GUEST_RFLAGS, rflags);
999}
1000
2809f5d2
GC		 1001static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1002{
1003 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1004 int ret = 0;
1005
1006 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1007 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1008 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1009 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1010
1011 return ret & mask;
1012}
1013
1014static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1015{
1016 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1017 u32 interruptibility = interruptibility_old;
1018
1019 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1020
48005f64 1021 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1022 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1023 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1024 interruptibility |= GUEST_INTR_STATE_STI;
1025
1026 if ((interruptibility != interruptibility_old))
1027 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1028}
1029
6aa8b732
AK		 1030static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1031{
1032 unsigned long rip;
6aa8b732 1033
5fdbf976 1034 rip = kvm_rip_read(vcpu);
6aa8b732 1035 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1036 kvm_rip_write(vcpu, rip);
6aa8b732 1037
2809f5d2
GC		 1038 /* skipping an emulated instruction also counts */
1039 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1040}
1041
443381a8
AL		 1042static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1043{
1044 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1045 * explicitly skip the instruction because if the HLT state is set, then
1046 * the instruction is already executing and RIP has already been
1047 * advanced. */
1048 if (!yield_on_hlt &&
1049 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1050 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1051}
1052
298101da 1053static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1054 bool has_error_code, u32 error_code,
1055 bool reinject)
298101da 1056{
77ab6db0 1057 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1058 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1059
8ab2d2e2 1060 if (has_error_code) {
77ab6db0 1061 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1062 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1063 }
77ab6db0 1064
7ffd92c5 1065 if (vmx->rmode.vm86_active) {
a92601bb
MG		 1066 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1067 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1068 return;
1069 }
1070
66fd3f7f
GN		 1071 if (kvm_exception_is_soft(nr)) {
1072 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1073 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1074 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1075 } else
1076 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1077
1078 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1079 vmx_clear_hlt(vcpu);
298101da
AK		 1080}
1081
4e47c7a6
SY		 1082static bool vmx_rdtscp_supported(void)
1083{
1084 return cpu_has_vmx_rdtscp();
1085}
1086
a75beee6
ED		 1087/*
1088 * Swap MSR entry in host/guest MSR entry array.
1089 */
8b9cf98c 1090static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1091{
26bb0981 1092 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1093
1094 tmp = vmx->guest_msrs[to];
1095 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1096 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1097}
1098
e38aea3e
AK		 1099/*
1100 * Set up the vmcs to automatically save and restore system
1101 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1102 * mode, as fiddling with msrs is very expensive.
1103 */
8b9cf98c 1104static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1105{
26bb0981 1106 int save_nmsrs, index;
5897297b 1107 unsigned long *msr_bitmap;
e38aea3e 1108
33f9c505 1109 vmx_load_host_state(vmx);
a75beee6
ED		 1110 save_nmsrs = 0;
1111#ifdef CONFIG_X86_64
8b9cf98c 1112 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1113 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1114 if (index >= 0)
8b9cf98c
RR		 1115 move_msr_up(vmx, index, save_nmsrs++);
1116 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1117 if (index >= 0)
8b9cf98c
RR		 1118 move_msr_up(vmx, index, save_nmsrs++);
1119 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1120 if (index >= 0)
8b9cf98c 1121 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1122 index = __find_msr_index(vmx, MSR_TSC_AUX);
1123 if (index >= 0 && vmx->rdtscp_enabled)
1124 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1125 /*
8c06585d 1126 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1127 * if efer.sce is enabled.
1128 */
8c06585d 1129 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1130 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1131 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1132 }
1133#endif
92c0d900
AK		 1134 index = __find_msr_index(vmx, MSR_EFER);
1135 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1136 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1137
26bb0981 1138 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1139
1140 if (cpu_has_vmx_msr_bitmap()) {
1141 if (is_long_mode(&vmx->vcpu))
1142 msr_bitmap = vmx_msr_bitmap_longmode;
1143 else
1144 msr_bitmap = vmx_msr_bitmap_legacy;
1145
1146 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1147 }
e38aea3e
AK		 1148}
1149
6aa8b732
AK		 1150/*
1151 * reads and returns guest's timestamp counter "register"
1152 * guest_tsc = host_tsc + tsc_offset -- 21.3
1153 */
1154static u64 guest_read_tsc(void)
1155{
1156 u64 host_tsc, tsc_offset;
1157
1158 rdtscll(host_tsc);
1159 tsc_offset = vmcs_read64(TSC_OFFSET);
1160 return host_tsc + tsc_offset;
1161}
1162
4051b188
JR		 1163/*
1164 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1165 * ioctl. In this case the call-back should update internal vmx state to make
1166 * the changes effective.
1167 */
1168static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1169{
1170 /* Nothing to do here */
1171}
1172
6aa8b732 1173/*
99e3e30a 1174 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1175 */
99e3e30a 1176static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1177{
f4e1b3c8 1178 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1179}
1180
e48672fa
ZA		 1181static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1182{
1183 u64 offset = vmcs_read64(TSC_OFFSET);
1184 vmcs_write64(TSC_OFFSET, offset + adjustment);
1185}
1186
6aa8b732
AK		 1187/*
1188 * Reads an msr value (of 'msr_index') into 'pdata'.
1189 * Returns 0 on success, non-0 otherwise.
1190 * Assumes vcpu_load() was already called.
1191 */
1192static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1193{
1194 u64 data;
26bb0981 1195 struct shared_msr_entry *msr;
6aa8b732
AK		 1196
1197 if (!pdata) {
1198 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1199 return -EINVAL;
1200 }
1201
1202 switch (msr_index) {
05b3e0c2 1203#ifdef CONFIG_X86_64
6aa8b732
AK		 1204 case MSR_FS_BASE:
1205 data = vmcs_readl(GUEST_FS_BASE);
1206 break;
1207 case MSR_GS_BASE:
1208 data = vmcs_readl(GUEST_GS_BASE);
1209 break;
44ea2b17
AK		 1210 case MSR_KERNEL_GS_BASE:
1211 vmx_load_host_state(to_vmx(vcpu));
1212 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1213 break;
26bb0981 1214#endif
6aa8b732 1215 case MSR_EFER:
3bab1f5d 1216 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1217 case MSR_IA32_TSC:
6aa8b732
AK		 1218 data = guest_read_tsc();
1219 break;
1220 case MSR_IA32_SYSENTER_CS:
1221 data = vmcs_read32(GUEST_SYSENTER_CS);
1222 break;
1223 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1224 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1225 break;
1226 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1227 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1228 break;
4e47c7a6
SY		 1229 case MSR_TSC_AUX:
1230 if (!to_vmx(vcpu)->rdtscp_enabled)
1231 return 1;
1232 /* Otherwise falls through */
6aa8b732 1233 default:
26bb0981 1234 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1235 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1236 if (msr) {
542423b0 1237 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1238 data = msr->data;
1239 break;
6aa8b732 1240 }
3bab1f5d 1241 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1242 }
1243
1244 *pdata = data;
1245 return 0;
1246}
1247
1248/*
1249 * Writes msr value into into the appropriate "register".
1250 * Returns 0 on success, non-0 otherwise.
1251 * Assumes vcpu_load() was already called.
1252 */
1253static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1254{
a2fa3e9f 1255 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1256 struct shared_msr_entry *msr;
2cc51560
ED		 1257 int ret = 0;
1258
6aa8b732 1259 switch (msr_index) {
3bab1f5d 1260 case MSR_EFER:
a9b21b62 1261 vmx_load_host_state(vmx);
2cc51560 1262 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1263 break;
16175a79 1264#ifdef CONFIG_X86_64
6aa8b732
AK		 1265 case MSR_FS_BASE:
1266 vmcs_writel(GUEST_FS_BASE, data);
1267 break;
1268 case MSR_GS_BASE:
1269 vmcs_writel(GUEST_GS_BASE, data);
1270 break;
44ea2b17
AK		 1271 case MSR_KERNEL_GS_BASE:
1272 vmx_load_host_state(vmx);
1273 vmx->msr_guest_kernel_gs_base = data;
1274 break;
6aa8b732
AK		 1275#endif
1276 case MSR_IA32_SYSENTER_CS:
1277 vmcs_write32(GUEST_SYSENTER_CS, data);
1278 break;
1279 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1280 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1281 break;
1282 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1283 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1284 break;
af24a4e4 1285 case MSR_IA32_TSC:
99e3e30a 1286 kvm_write_tsc(vcpu, data);
6aa8b732 1287 break;
468d472f
SY		 1288 case MSR_IA32_CR_PAT:
1289 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1290 vmcs_write64(GUEST_IA32_PAT, data);
1291 vcpu->arch.pat = data;
1292 break;
1293 }
4e47c7a6
SY		 1294 ret = kvm_set_msr_common(vcpu, msr_index, data);
1295 break;
1296 case MSR_TSC_AUX:
1297 if (!vmx->rdtscp_enabled)
1298 return 1;
1299 /* Check reserved bit, higher 32 bits should be zero */
1300 if ((data >> 32) != 0)
1301 return 1;
1302 /* Otherwise falls through */
6aa8b732 1303 default:
8b9cf98c 1304 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1305 if (msr) {
542423b0 1306 vmx_load_host_state(vmx);
3bab1f5d
AK		 1307 msr->data = data;
1308 break;
6aa8b732 1309 }
2cc51560 1310 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1311 }
1312
2cc51560 1313 return ret;
6aa8b732
AK		 1314}
1315
5fdbf976 1316static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1317{
5fdbf976
MT		 1318 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1319 switch (reg) {
1320 case VCPU_REGS_RSP:
1321 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1322 break;
1323 case VCPU_REGS_RIP:
1324 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1325 break;
6de4f3ad
AK		 1326 case VCPU_EXREG_PDPTR:
1327 if (enable_ept)
1328 ept_save_pdptrs(vcpu);
1329 break;
5fdbf976
MT		 1330 default:
1331 break;
1332 }
6aa8b732
AK		 1333}
1334
355be0b9 1335static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1336{
ae675ef0
JK		 1337 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1338 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1339 else
1340 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1341
abd3f2d6 1342 update_exception_bitmap(vcpu);
6aa8b732
AK		 1343}
1344
1345static __init int cpu_has_kvm_support(void)
1346{
6210e37b 1347 return cpu_has_vmx();
6aa8b732
AK		 1348}
1349
1350static __init int vmx_disabled_by_bios(void)
1351{
1352 u64 msr;
1353
1354 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 1355 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 1356 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 1357 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1358 && tboot_enabled())
1359 return 1;
23f3e991 1360 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 1361 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 1362 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 1363 && !tboot_enabled()) {
1364 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 1365 "activate TXT before enabling KVM\n");
cafd6659 1366 return 1;
f9335afe 1367 }
23f3e991
JC		 1368 /* launched w/o TXT and VMX disabled */
1369 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1370 && !tboot_enabled())
1371 return 1;
cafd6659
SW		 1372 }
1373
1374 return 0;
6aa8b732
AK		 1375}
1376
7725b894
DX		 1377static void kvm_cpu_vmxon(u64 addr)
1378{
1379 asm volatile (ASM_VMX_VMXON_RAX
1380 : : "a"(&addr), "m"(addr)
1381 : "memory", "cc");
1382}
1383
10474ae8 1384static int hardware_enable(void *garbage)
6aa8b732
AK		 1385{
1386 int cpu = raw_smp_processor_id();
1387 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1388 u64 old, test_bits;
6aa8b732 1389
10474ae8
AG		 1390 if (read_cr4() & X86_CR4_VMXE)
1391 return -EBUSY;
1392
543e4243 1393 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1394 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1395
1396 test_bits = FEATURE_CONTROL_LOCKED;
1397 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1398 if (tboot_enabled())
1399 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1400
1401 if ((old & test_bits) != test_bits) {
6aa8b732 1402 /* enable and lock */
cafd6659
SW		 1403 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1404 }
66aee91a 1405 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1406
4610c9cc
DX		 1407 if (vmm_exclusive) {
1408 kvm_cpu_vmxon(phys_addr);
1409 ept_sync_global();
1410 }
10474ae8 1411
3444d7da
AK		 1412 store_gdt(&__get_cpu_var(host_gdt));
1413
10474ae8 1414 return 0;
6aa8b732
AK		 1415}
1416
543e4243
AK		 1417static void vmclear_local_vcpus(void)
1418{
1419 int cpu = raw_smp_processor_id();
1420 struct vcpu_vmx *vmx, *n;
1421
1422 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1423 local_vcpus_link)
1424 __vcpu_clear(vmx);
1425}
1426
710ff4a8
EH		 1427
1428/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1429 * tricks.
1430 */
1431static void kvm_cpu_vmxoff(void)
6aa8b732 1432{
4ecac3fd 1433 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1434}
1435
710ff4a8
EH		 1436static void hardware_disable(void *garbage)
1437{
4610c9cc
DX		 1438 if (vmm_exclusive) {
1439 vmclear_local_vcpus();
1440 kvm_cpu_vmxoff();
1441 }
7725b894 1442 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1443}
1444
1c3d14fe 1445static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1446 u32 msr, u32 *result)
1c3d14fe
YS		 1447{
1448 u32 vmx_msr_low, vmx_msr_high;
1449 u32 ctl = ctl_min | ctl_opt;
1450
1451 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1452
1453 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1454 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1455
1456 /* Ensure minimum (required) set of control bits are supported. */
1457 if (ctl_min & ~ctl)
002c7f7c 1458 return -EIO;
1c3d14fe
YS		 1459
1460 *result = ctl;
1461 return 0;
1462}
1463
110312c8
AK		 1464static __init bool allow_1_setting(u32 msr, u32 ctl)
1465{
1466 u32 vmx_msr_low, vmx_msr_high;
1467
1468 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1469 return vmx_msr_high & ctl;
1470}
1471
002c7f7c 1472static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1473{
1474 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1475 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1476 u32 _pin_based_exec_control = 0;
1477 u32 _cpu_based_exec_control = 0;
f78e0e2e 1478 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1479 u32 _vmexit_control = 0;
1480 u32 _vmentry_control = 0;
1481
1482 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1483 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1484 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1485 &_pin_based_exec_control) < 0)
002c7f7c 1486 return -EIO;
1c3d14fe 1487
443381a8 1488 min =
1c3d14fe
YS		 1489#ifdef CONFIG_X86_64
1490 CPU_BASED_CR8_LOAD_EXITING |
1491 CPU_BASED_CR8_STORE_EXITING |
1492#endif
d56f546d
SY		 1493 CPU_BASED_CR3_LOAD_EXITING |
1494 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1495 CPU_BASED_USE_IO_BITMAPS |
1496 CPU_BASED_MOV_DR_EXITING |
a7052897 1497 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1498 CPU_BASED_MWAIT_EXITING |
1499 CPU_BASED_MONITOR_EXITING |
a7052897 1500 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 1501
1502 if (yield_on_hlt)
1503 min |= CPU_BASED_HLT_EXITING;
1504
f78e0e2e 1505 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1506 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1507 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1508 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1509 &_cpu_based_exec_control) < 0)
002c7f7c 1510 return -EIO;
6e5d865c
YS		 1511#ifdef CONFIG_X86_64
1512 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1513 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1514 ~CPU_BASED_CR8_STORE_EXITING;
1515#endif
f78e0e2e 1516 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1517 min2 = 0;
1518 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1519 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1520 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1521 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1522 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1523 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1524 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1525 if (adjust_vmx_controls(min2, opt2,
1526 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1527 &_cpu_based_2nd_exec_control) < 0)
1528 return -EIO;
1529 }
1530#ifndef CONFIG_X86_64
1531 if (!(_cpu_based_2nd_exec_control &
1532 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1533 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1534#endif
d56f546d 1535 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1536 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1537 enabled */
5fff7d27
GN		 1538 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1539 CPU_BASED_CR3_STORE_EXITING |
1540 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1541 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1542 vmx_capability.ept, vmx_capability.vpid);
1543 }
1c3d14fe
YS		 1544
1545 min = 0;
1546#ifdef CONFIG_X86_64
1547 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1548#endif
468d472f 1549 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1550 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1551 &_vmexit_control) < 0)
002c7f7c 1552 return -EIO;
1c3d14fe 1553
468d472f
SY		 1554 min = 0;
1555 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1556 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1557 &_vmentry_control) < 0)
002c7f7c 1558 return -EIO;
6aa8b732 1559
c68876fd 1560 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1561
1562 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1563 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1564 return -EIO;
1c3d14fe
YS		 1565
1566#ifdef CONFIG_X86_64
1567 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1568 if (vmx_msr_high & (1u<<16))
002c7f7c 1569 return -EIO;
1c3d14fe
YS		 1570#endif
1571
1572 /* Require Write-Back (WB) memory type for VMCS accesses. */
1573 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1574 return -EIO;
1c3d14fe 1575
002c7f7c
YS		 1576 vmcs_conf->size = vmx_msr_high & 0x1fff;
1577 vmcs_conf->order = get_order(vmcs_config.size);
1578 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1579
002c7f7c
YS		 1580 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1581 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1582 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1583 vmcs_conf->vmexit_ctrl = _vmexit_control;
1584 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 1585
110312c8
AK		 1586 cpu_has_load_ia32_efer =
1587 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1588 VM_ENTRY_LOAD_IA32_EFER)
1589 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1590 VM_EXIT_LOAD_IA32_EFER);
1591
1c3d14fe 1592 return 0;
c68876fd 1593}
6aa8b732
AK		 1594
1595static struct vmcs *alloc_vmcs_cpu(int cpu)
1596{
1597 int node = cpu_to_node(cpu);
1598 struct page *pages;
1599 struct vmcs *vmcs;
1600
6484eb3e 1601 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1602 if (!pages)
1603 return NULL;
1604 vmcs = page_address(pages);
1c3d14fe
YS		 1605 memset(vmcs, 0, vmcs_config.size);
1606 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1607 return vmcs;
1608}
1609
1610static struct vmcs *alloc_vmcs(void)
1611{
d3b2c338 1612 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1613}
1614
1615static void free_vmcs(struct vmcs *vmcs)
1616{
1c3d14fe 1617 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1618}
1619
39959588 1620static void free_kvm_area(void)
6aa8b732
AK		 1621{
1622 int cpu;
1623
3230bb47 1624 for_each_possible_cpu(cpu) {
6aa8b732 1625 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1626 per_cpu(vmxarea, cpu) = NULL;
1627 }
6aa8b732
AK		 1628}
1629
6aa8b732
AK		 1630static __init int alloc_kvm_area(void)
1631{
1632 int cpu;
1633
3230bb47 1634 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1635 struct vmcs *vmcs;
1636
1637 vmcs = alloc_vmcs_cpu(cpu);
1638 if (!vmcs) {
1639 free_kvm_area();
1640 return -ENOMEM;
1641 }
1642
1643 per_cpu(vmxarea, cpu) = vmcs;
1644 }
1645 return 0;
1646}
1647
1648static __init int hardware_setup(void)
1649{
002c7f7c
YS		 1650 if (setup_vmcs_config(&vmcs_config) < 0)
1651 return -EIO;
50a37eb4
JR		 1652
1653 if (boot_cpu_has(X86_FEATURE_NX))
1654 kvm_enable_efer_bits(EFER_NX);
1655
93ba03c2
SY		 1656 if (!cpu_has_vmx_vpid())
1657 enable_vpid = 0;
1658
4bc9b982
SY		 1659 if (!cpu_has_vmx_ept() ||
1660 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1661 enable_ept = 0;
3a624e29
NK		 1662 enable_unrestricted_guest = 0;
1663 }
1664
1665 if (!cpu_has_vmx_unrestricted_guest())
1666 enable_unrestricted_guest = 0;
93ba03c2
SY		 1667
1668 if (!cpu_has_vmx_flexpriority())
1669 flexpriority_enabled = 0;
1670
95ba8273
GN		 1671 if (!cpu_has_vmx_tpr_shadow())
1672 kvm_x86_ops->update_cr8_intercept = NULL;
1673
54dee993
MT		 1674 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1675 kvm_disable_largepages();
1676
4b8d54f9
ZE		 1677 if (!cpu_has_vmx_ple())
1678 ple_gap = 0;
1679
6aa8b732
AK		 1680 return alloc_kvm_area();
1681}
1682
1683static __exit void hardware_unsetup(void)
1684{
1685 free_kvm_area();
1686}
1687
6aa8b732
AK		 1688static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1689{
1690 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1691
6af11b9e 1692 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1693 vmcs_write16(sf->selector, save->selector);
1694 vmcs_writel(sf->base, save->base);
1695 vmcs_write32(sf->limit, save->limit);
1696 vmcs_write32(sf->ar_bytes, save->ar);
1697 } else {
1698 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1699 << AR_DPL_SHIFT;
1700 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1701 }
1702}
1703
1704static void enter_pmode(struct kvm_vcpu *vcpu)
1705{
1706 unsigned long flags;
a89a8fb9 1707 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1708
a89a8fb9 1709 vmx->emulation_required = 1;
7ffd92c5 1710 vmx->rmode.vm86_active = 0;
6aa8b732 1711
d0ba64f9 1712 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 1713 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1714 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1715 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1716
1717 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1718 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1719 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1720 vmcs_writel(GUEST_RFLAGS, flags);
1721
66aee91a
RR		 1722 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1723 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1724
1725 update_exception_bitmap(vcpu);
1726
a89a8fb9
MG		 1727 if (emulate_invalid_guest_state)
1728 return;
1729
7ffd92c5
AK		 1730 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1731 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1732 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1733 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1734
1735 vmcs_write16(GUEST_SS_SELECTOR, 0);
1736 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1737
1738 vmcs_write16(GUEST_CS_SELECTOR,
1739 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1740 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1741}
1742
d77c26fc 1743static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1744{
bfc6d222 1745 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1746 struct kvm_memslots *slots;
1747 gfn_t base_gfn;
1748
90d83dc3 1749 slots = kvm_memslots(kvm);
f495c6e5 1750 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1751 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1752 return base_gfn << PAGE_SHIFT;
1753 }
bfc6d222 1754 return kvm->arch.tss_addr;
6aa8b732
AK		 1755}
1756
1757static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1758{
1759 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1760
1761 save->selector = vmcs_read16(sf->selector);
1762 save->base = vmcs_readl(sf->base);
1763 save->limit = vmcs_read32(sf->limit);
1764 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 1765 vmcs_write16(sf->selector, save->base >> 4);
444e863d 1766 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 1767 vmcs_write32(sf->limit, 0xffff);
1768 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 1769 if (save->base & 0xf)
1770 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1771 " aligned when entering protected mode (seg=%d)",
1772 seg);
6aa8b732
AK		 1773}
1774
1775static void enter_rmode(struct kvm_vcpu *vcpu)
1776{
1777 unsigned long flags;
a89a8fb9 1778 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1779
3a624e29
NK		 1780 if (enable_unrestricted_guest)
1781 return;
1782
a89a8fb9 1783 vmx->emulation_required = 1;
7ffd92c5 1784 vmx->rmode.vm86_active = 1;
6aa8b732 1785
776e58ea
GN		 1786 /*
1787 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
1788 * vcpu. Call it here with phys address pointing 16M below 4G.
1789 */
1790 if (!vcpu->kvm->arch.tss_addr) {
1791 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
1792 "called before entering vcpu\n");
1793 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
1794 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
1795 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
1796 }
1797
d0ba64f9 1798 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 1799 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1800 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1801
7ffd92c5 1802 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1803 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1804
7ffd92c5 1805 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1806 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1807
1808 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1809 vmx->rmode.save_rflags = flags;
6aa8b732 1810
053de044 1811 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1812
1813 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1814 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1815 update_exception_bitmap(vcpu);
1816
a89a8fb9
MG		 1817 if (emulate_invalid_guest_state)
1818 goto continue_rmode;
1819
6aa8b732
AK		 1820 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1821 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1822 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1823
1824 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1825 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1826 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1827 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1828 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1829
7ffd92c5
AK		 1830 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1831 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1832 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1833 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1834
a89a8fb9 1835continue_rmode:
8668a3c4 1836 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 1837}
1838
401d10de
AS		 1839static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1840{
1841 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1842 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1843
1844 if (!msr)
1845 return;
401d10de 1846
44ea2b17
AK		 1847 /*
1848 * Force kernel_gs_base reloading before EFER changes, as control
1849 * of this msr depends on is_long_mode().
1850 */
1851 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1852 vcpu->arch.efer = efer;
401d10de
AS		 1853 if (efer & EFER_LMA) {
1854 vmcs_write32(VM_ENTRY_CONTROLS,
1855 vmcs_read32(VM_ENTRY_CONTROLS) |
1856 VM_ENTRY_IA32E_MODE);
1857 msr->data = efer;
1858 } else {
1859 vmcs_write32(VM_ENTRY_CONTROLS,
1860 vmcs_read32(VM_ENTRY_CONTROLS) &
1861 ~VM_ENTRY_IA32E_MODE);
1862
1863 msr->data = efer & ~EFER_LME;
1864 }
1865 setup_msrs(vmx);
1866}
1867
05b3e0c2 1868#ifdef CONFIG_X86_64
6aa8b732
AK		 1869
1870static void enter_lmode(struct kvm_vcpu *vcpu)
1871{
1872 u32 guest_tr_ar;
1873
1874 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1875 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1876 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1877 __func__);
6aa8b732
AK		 1878 vmcs_write32(GUEST_TR_AR_BYTES,
1879 (guest_tr_ar & ~AR_TYPE_MASK)
1880 | AR_TYPE_BUSY_64_TSS);
1881 }
da38f438 1882 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1883}
1884
1885static void exit_lmode(struct kvm_vcpu *vcpu)
1886{
6aa8b732
AK		 1887 vmcs_write32(VM_ENTRY_CONTROLS,
1888 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1889 & ~VM_ENTRY_IA32E_MODE);
da38f438 1890 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1891}
1892
1893#endif
1894
2384d2b3
SY		 1895static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1896{
b9d762fa 1897 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 1898 if (enable_ept) {
1899 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1900 return;
4e1096d2 1901 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 1902 }
2384d2b3
SY		 1903}
1904
e8467fda
AK		 1905static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1906{
1907 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1908
1909 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1910 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1911}
1912
aff48baa
AK		 1913static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1914{
1915 if (enable_ept && is_paging(vcpu))
1916 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1917 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1918}
1919
25c4c276 1920static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1921{
fc78f519
AK		 1922 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1923
1924 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1925 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1926}
1927
1439442c
SY		 1928static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1929{
6de4f3ad
AK		 1930 if (!test_bit(VCPU_EXREG_PDPTR,
1931 (unsigned long *)&vcpu->arch.regs_dirty))
1932 return;
1933
1439442c 1934 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1935 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1936 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1937 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1938 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 1939 }
1940}
1941
8f5d549f
AK		 1942static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1943{
1944 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1945 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1946 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1947 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1948 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 1949 }
6de4f3ad
AK		 1950
1951 __set_bit(VCPU_EXREG_PDPTR,
1952 (unsigned long *)&vcpu->arch.regs_avail);
1953 __set_bit(VCPU_EXREG_PDPTR,
1954 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1955}
1956
1439442c
SY		 1957static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1958
1959static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1960 unsigned long cr0,
1961 struct kvm_vcpu *vcpu)
1962{
aff48baa 1963 vmx_decache_cr3(vcpu);
1439442c
SY		 1964 if (!(cr0 & X86_CR0_PG)) {
1965 /* From paging/starting to nonpaging */
1966 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1967 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1968 (CPU_BASED_CR3_LOAD_EXITING |
1969 CPU_BASED_CR3_STORE_EXITING));
1970 vcpu->arch.cr0 = cr0;
fc78f519 1971 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1972 } else if (!is_paging(vcpu)) {
1973 /* From nonpaging to paging */
1974 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1975 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1976 ~(CPU_BASED_CR3_LOAD_EXITING |
1977 CPU_BASED_CR3_STORE_EXITING));
1978 vcpu->arch.cr0 = cr0;
fc78f519 1979 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1980 }
95eb84a7
SY		 1981
1982 if (!(cr0 & X86_CR0_WP))
1983 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1984}
1985
6aa8b732
AK		 1986static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1987{
7ffd92c5 1988 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1989 unsigned long hw_cr0;
1990
1991 if (enable_unrestricted_guest)
1992 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1993 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1994 else
1995 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1996
7ffd92c5 1997 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1998 enter_pmode(vcpu);
1999
7ffd92c5 2000 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2001 enter_rmode(vcpu);
2002
05b3e0c2 2003#ifdef CONFIG_X86_64
f6801dff 2004 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2005 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2006 enter_lmode(vcpu);
707d92fa 2007 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2008 exit_lmode(vcpu);
2009 }
2010#endif
2011
089d034e 2012 if (enable_ept)
1439442c
SY		 2013 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2014
02daab21 2015 if (!vcpu->fpu_active)
81231c69 2016 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2017
6aa8b732 2018 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2019 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2020 vcpu->arch.cr0 = cr0;
69c73028 2021 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2022}
2023
1439442c
SY		 2024static u64 construct_eptp(unsigned long root_hpa)
2025{
2026 u64 eptp;
2027
2028 /* TODO write the value reading from MSR */
2029 eptp = VMX_EPT_DEFAULT_MT |
2030 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2031 eptp |= (root_hpa & PAGE_MASK);
2032
2033 return eptp;
2034}
2035
6aa8b732
AK		 2036static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2037{
1439442c
SY		 2038 unsigned long guest_cr3;
2039 u64 eptp;
2040
2041 guest_cr3 = cr3;
089d034e 2042 if (enable_ept) {
1439442c
SY		 2043 eptp = construct_eptp(cr3);
2044 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 2045 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 2046 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 2047 ept_load_pdptrs(vcpu);
1439442c
SY		 2048 }
2049
2384d2b3 2050 vmx_flush_tlb(vcpu);
1439442c 2051 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2052}
2053
2054static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2055{
7ffd92c5 2056 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2057 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2058
ad312c7c 2059 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2060 if (enable_ept) {
2061 if (!is_paging(vcpu)) {
2062 hw_cr4 &= ~X86_CR4_PAE;
2063 hw_cr4 |= X86_CR4_PSE;
2064 } else if (!(cr4 & X86_CR4_PAE)) {
2065 hw_cr4 &= ~X86_CR4_PAE;
2066 }
2067 }
1439442c
SY		 2068
2069 vmcs_writel(CR4_READ_SHADOW, cr4);
2070 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 2071}
2072
6aa8b732
AK		 2073static void vmx_get_segment(struct kvm_vcpu *vcpu,
2074 struct kvm_segment *var, int seg)
2075{
a9179499 2076 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2077 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
a9179499 2078 struct kvm_save_segment *save;
6aa8b732
AK		 2079 u32 ar;
2080
a9179499
AK		 2081 if (vmx->rmode.vm86_active
2082 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2083 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2084 || seg == VCPU_SREG_GS)
2085 && !emulate_invalid_guest_state) {
2086 switch (seg) {
2087 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2088 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2089 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2090 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2091 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2092 default: BUG();
2093 }
2094 var->selector = save->selector;
2095 var->base = save->base;
2096 var->limit = save->limit;
2097 ar = save->ar;
2098 if (seg == VCPU_SREG_TR
2099 || var->selector == vmcs_read16(sf->selector))
2100 goto use_saved_rmode_seg;
2101 }
6aa8b732
AK		 2102 var->base = vmcs_readl(sf->base);
2103 var->limit = vmcs_read32(sf->limit);
2104 var->selector = vmcs_read16(sf->selector);
2105 ar = vmcs_read32(sf->ar_bytes);
a9179499 2106use_saved_rmode_seg:
9fd4a3b7 2107 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2108 ar = 0;
2109 var->type = ar & 15;
2110 var->s = (ar >> 4) & 1;
2111 var->dpl = (ar >> 5) & 3;
2112 var->present = (ar >> 7) & 1;
2113 var->avl = (ar >> 12) & 1;
2114 var->l = (ar >> 13) & 1;
2115 var->db = (ar >> 14) & 1;
2116 var->g = (ar >> 15) & 1;
2117 var->unusable = (ar >> 16) & 1;
2118}
2119
a9179499
AK		 2120static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2121{
2122 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2123 struct kvm_segment s;
2124
2125 if (to_vmx(vcpu)->rmode.vm86_active) {
2126 vmx_get_segment(vcpu, &s, seg);
2127 return s.base;
2128 }
2129 return vmcs_readl(sf->base);
2130}
2131
69c73028 2132static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 2133{
3eeb3288 2134 if (!is_protmode(vcpu))
2e4d2653
IE		 2135 return 0;
2136
f4c63e5d
AK		 2137 if (!is_long_mode(vcpu)
2138 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 2139 return 3;
2140
eab4b8aa 2141 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2142}
2143
69c73028
AK		 2144static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2145{
2146 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2147 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2148 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2149 }
2150 return to_vmx(vcpu)->cpl;
2151}
2152
2153
653e3108 2154static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2155{
6aa8b732
AK		 2156 u32 ar;
2157
653e3108 2158 if (var->unusable)
6aa8b732
AK		 2159 ar = 1 << 16;
2160 else {
2161 ar = var->type & 15;
2162 ar |= (var->s & 1) << 4;
2163 ar |= (var->dpl & 3) << 5;
2164 ar |= (var->present & 1) << 7;
2165 ar |= (var->avl & 1) << 12;
2166 ar |= (var->l & 1) << 13;
2167 ar |= (var->db & 1) << 14;
2168 ar |= (var->g & 1) << 15;
2169 }
f7fbf1fd
UL		 2170 if (ar == 0) /* a 0 value means unusable */
2171 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2172
2173 return ar;
2174}
2175
2176static void vmx_set_segment(struct kvm_vcpu *vcpu,
2177 struct kvm_segment *var, int seg)
2178{
7ffd92c5 2179 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2180 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2181 u32 ar;
2182
7ffd92c5 2183 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 2184 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 2185 vmx->rmode.tr.selector = var->selector;
2186 vmx->rmode.tr.base = var->base;
2187 vmx->rmode.tr.limit = var->limit;
2188 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2189 return;
2190 }
2191 vmcs_writel(sf->base, var->base);
2192 vmcs_write32(sf->limit, var->limit);
2193 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2194 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2195 /*
2196 * Hack real-mode segments into vm86 compatibility.
2197 */
2198 if (var->base == 0xffff0000 && var->selector == 0xf000)
2199 vmcs_writel(sf->base, 0xf0000);
2200 ar = 0xf3;
2201 } else
2202 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2203
2204 /*
2205 * Fix the "Accessed" bit in AR field of segment registers for older
2206 * qemu binaries.
2207 * IA32 arch specifies that at the time of processor reset the
2208 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2209 * is setting it to 0 in the usedland code. This causes invalid guest
2210 * state vmexit when "unrestricted guest" mode is turned on.
2211 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2212 * tree. Newer qemu binaries with that qemu fix would not need this
2213 * kvm hack.
2214 */
2215 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2216 ar |= 0x1; /* Accessed */
2217
6aa8b732 2218 vmcs_write32(sf->ar_bytes, ar);
69c73028 2219 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2220}
2221
6aa8b732
AK		 2222static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2223{
2224 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2225
2226 *db = (ar >> 14) & 1;
2227 *l = (ar >> 13) & 1;
2228}
2229
89a27f4d 2230static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2231{
89a27f4d
GN		 2232 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2233 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2234}
2235
89a27f4d 2236static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2237{
89a27f4d
GN		 2238 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2239 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2240}
2241
89a27f4d 2242static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2243{
89a27f4d
GN		 2244 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2245 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2246}
2247
89a27f4d 2248static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2249{
89a27f4d
GN		 2250 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2251 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2252}
2253
648dfaa7
MG		 2254static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2255{
2256 struct kvm_segment var;
2257 u32 ar;
2258
2259 vmx_get_segment(vcpu, &var, seg);
2260 ar = vmx_segment_access_rights(&var);
2261
2262 if (var.base != (var.selector << 4))
2263 return false;
2264 if (var.limit != 0xffff)
2265 return false;
2266 if (ar != 0xf3)
2267 return false;
2268
2269 return true;
2270}
2271
2272static bool code_segment_valid(struct kvm_vcpu *vcpu)
2273{
2274 struct kvm_segment cs;
2275 unsigned int cs_rpl;
2276
2277 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2278 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2279
1872a3f4
AK		 2280 if (cs.unusable)
2281 return false;
648dfaa7
MG		 2282 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2283 return false;
2284 if (!cs.s)
2285 return false;
1872a3f4 2286 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2287 if (cs.dpl > cs_rpl)
2288 return false;
1872a3f4 2289 } else {
648dfaa7
MG		 2290 if (cs.dpl != cs_rpl)
2291 return false;
2292 }
2293 if (!cs.present)
2294 return false;
2295
2296 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2297 return true;
2298}
2299
2300static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2301{
2302 struct kvm_segment ss;
2303 unsigned int ss_rpl;
2304
2305 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2306 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2307
1872a3f4
AK		 2308 if (ss.unusable)
2309 return true;
2310 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2311 return false;
2312 if (!ss.s)
2313 return false;
2314 if (ss.dpl != ss_rpl) /* DPL != RPL */
2315 return false;
2316 if (!ss.present)
2317 return false;
2318
2319 return true;
2320}
2321
2322static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2323{
2324 struct kvm_segment var;
2325 unsigned int rpl;
2326
2327 vmx_get_segment(vcpu, &var, seg);
2328 rpl = var.selector & SELECTOR_RPL_MASK;
2329
1872a3f4
AK		 2330 if (var.unusable)
2331 return true;
648dfaa7
MG		 2332 if (!var.s)
2333 return false;
2334 if (!var.present)
2335 return false;
2336 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2337 if (var.dpl < rpl) /* DPL < RPL */
2338 return false;
2339 }
2340
2341 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2342 * rights flags
2343 */
2344 return true;
2345}
2346
2347static bool tr_valid(struct kvm_vcpu *vcpu)
2348{
2349 struct kvm_segment tr;
2350
2351 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2352
1872a3f4
AK		 2353 if (tr.unusable)
2354 return false;
648dfaa7
MG		 2355 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2356 return false;
1872a3f4 2357 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2358 return false;
2359 if (!tr.present)
2360 return false;
2361
2362 return true;
2363}
2364
2365static bool ldtr_valid(struct kvm_vcpu *vcpu)
2366{
2367 struct kvm_segment ldtr;
2368
2369 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2370
1872a3f4
AK		 2371 if (ldtr.unusable)
2372 return true;
648dfaa7
MG		 2373 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2374 return false;
2375 if (ldtr.type != 2)
2376 return false;
2377 if (!ldtr.present)
2378 return false;
2379
2380 return true;
2381}
2382
2383static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2384{
2385 struct kvm_segment cs, ss;
2386
2387 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2388 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2389
2390 return ((cs.selector & SELECTOR_RPL_MASK) ==
2391 (ss.selector & SELECTOR_RPL_MASK));
2392}
2393
2394/*
2395 * Check if guest state is valid. Returns true if valid, false if
2396 * not.
2397 * We assume that registers are always usable
2398 */
2399static bool guest_state_valid(struct kvm_vcpu *vcpu)
2400{
2401 /* real mode guest state checks */
3eeb3288 2402 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2403 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2404 return false;
2405 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2406 return false;
2407 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2408 return false;
2409 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2410 return false;
2411 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2412 return false;
2413 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2414 return false;
2415 } else {
2416 /* protected mode guest state checks */
2417 if (!cs_ss_rpl_check(vcpu))
2418 return false;
2419 if (!code_segment_valid(vcpu))
2420 return false;
2421 if (!stack_segment_valid(vcpu))
2422 return false;
2423 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2424 return false;
2425 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2426 return false;
2427 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2428 return false;
2429 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2430 return false;
2431 if (!tr_valid(vcpu))
2432 return false;
2433 if (!ldtr_valid(vcpu))
2434 return false;
2435 }
2436 /* TODO:
2437 * - Add checks on RIP
2438 * - Add checks on RFLAGS
2439 */
2440
2441 return true;
2442}
2443
d77c26fc 2444static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2445{
40dcaa9f 2446 gfn_t fn;
195aefde 2447 u16 data = 0;
40dcaa9f 2448 int r, idx, ret = 0;
6aa8b732 2449
40dcaa9f
XG		 2450 idx = srcu_read_lock(&kvm->srcu);
2451 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 2452 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2453 if (r < 0)
10589a46 2454 goto out;
195aefde 2455 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2456 r = kvm_write_guest_page(kvm, fn++, &data,
2457 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2458 if (r < 0)
10589a46 2459 goto out;
195aefde
IE		 2460 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2461 if (r < 0)
10589a46 2462 goto out;
195aefde
IE		 2463 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2464 if (r < 0)
10589a46 2465 goto out;
195aefde 2466 data = ~0;
10589a46
MT		 2467 r = kvm_write_guest_page(kvm, fn, &data,
2468 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2469 sizeof(u8));
195aefde 2470 if (r < 0)
10589a46
MT		 2471 goto out;
2472
2473 ret = 1;
2474out:
40dcaa9f 2475 srcu_read_unlock(&kvm->srcu, idx);
10589a46 2476 return ret;
6aa8b732
AK		 2477}
2478
b7ebfb05
SY		 2479static int init_rmode_identity_map(struct kvm *kvm)
2480{
40dcaa9f 2481 int i, idx, r, ret;
b7ebfb05
SY		 2482 pfn_t identity_map_pfn;
2483 u32 tmp;
2484
089d034e 2485 if (!enable_ept)
b7ebfb05
SY		 2486 return 1;
2487 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2488 printk(KERN_ERR "EPT: identity-mapping pagetable "
2489 "haven't been allocated!\n");
2490 return 0;
2491 }
2492 if (likely(kvm->arch.ept_identity_pagetable_done))
2493 return 1;
2494 ret = 0;
b927a3ce 2495 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 2496 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 2497 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2498 if (r < 0)
2499 goto out;
2500 /* Set up identity-mapping pagetable for EPT in real mode */
2501 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2502 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2503 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2504 r = kvm_write_guest_page(kvm, identity_map_pfn,
2505 &tmp, i * sizeof(tmp), sizeof(tmp));
2506 if (r < 0)
2507 goto out;
2508 }
2509 kvm->arch.ept_identity_pagetable_done = true;
2510 ret = 1;
2511out:
40dcaa9f 2512 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 2513 return ret;
2514}
2515
6aa8b732
AK		 2516static void seg_setup(int seg)
2517{
2518 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2519 unsigned int ar;
6aa8b732
AK		 2520
2521 vmcs_write16(sf->selector, 0);
2522 vmcs_writel(sf->base, 0);
2523 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2524 if (enable_unrestricted_guest) {
2525 ar = 0x93;
2526 if (seg == VCPU_SREG_CS)
2527 ar |= 0x08; /* code segment */
2528 } else
2529 ar = 0xf3;
2530
2531 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2532}
2533
f78e0e2e
SY		 2534static int alloc_apic_access_page(struct kvm *kvm)
2535{
2536 struct kvm_userspace_memory_region kvm_userspace_mem;
2537 int r = 0;
2538
79fac95e 2539 mutex_lock(&kvm->slots_lock);
bfc6d222 2540 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2541 goto out;
2542 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2543 kvm_userspace_mem.flags = 0;
2544 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2545 kvm_userspace_mem.memory_size = PAGE_SIZE;
2546 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2547 if (r)
2548 goto out;
72dc67a6 2549
bfc6d222 2550 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2551out:
79fac95e 2552 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2553 return r;
2554}
2555
b7ebfb05
SY		 2556static int alloc_identity_pagetable(struct kvm *kvm)
2557{
2558 struct kvm_userspace_memory_region kvm_userspace_mem;
2559 int r = 0;
2560
79fac95e 2561 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2562 if (kvm->arch.ept_identity_pagetable)
2563 goto out;
2564 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2565 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2566 kvm_userspace_mem.guest_phys_addr =
2567 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2568 kvm_userspace_mem.memory_size = PAGE_SIZE;
2569 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2570 if (r)
2571 goto out;
2572
b7ebfb05 2573 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2574 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2575out:
79fac95e 2576 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2577 return r;
2578}
2579
2384d2b3
SY		 2580static void allocate_vpid(struct vcpu_vmx *vmx)
2581{
2582 int vpid;
2583
2584 vmx->vpid = 0;
919818ab 2585 if (!enable_vpid)
2384d2b3
SY		 2586 return;
2587 spin_lock(&vmx_vpid_lock);
2588 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2589 if (vpid < VMX_NR_VPIDS) {
2590 vmx->vpid = vpid;
2591 __set_bit(vpid, vmx_vpid_bitmap);
2592 }
2593 spin_unlock(&vmx_vpid_lock);
2594}
2595
cdbecfc3
LJ		 2596static void free_vpid(struct vcpu_vmx *vmx)
2597{
2598 if (!enable_vpid)
2599 return;
2600 spin_lock(&vmx_vpid_lock);
2601 if (vmx->vpid != 0)
2602 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2603 spin_unlock(&vmx_vpid_lock);
2604}
2605
5897297b 2606static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2607{
3e7c73e9 2608 int f = sizeof(unsigned long);
25c5f225
SY		 2609
2610 if (!cpu_has_vmx_msr_bitmap())
2611 return;
2612
2613 /*
2614 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2615 * have the write-low and read-high bitmap offsets the wrong way round.
2616 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2617 */
25c5f225 2618 if (msr <= 0x1fff) {
3e7c73e9
AK		 2619 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2620 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2621 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2622 msr &= 0x1fff;
3e7c73e9
AK		 2623 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2624 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2625 }
25c5f225
SY		 2626}
2627
5897297b
AK		 2628static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2629{
2630 if (!longmode_only)
2631 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2632 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2633}
2634
6aa8b732
AK		 2635/*
2636 * Sets up the vmcs for emulated real mode.
2637 */
8b9cf98c 2638static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2639{
468d472f 2640 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2641 u32 junk;
f4e1b3c8 2642 u64 host_pat;
6aa8b732 2643 unsigned long a;
89a27f4d 2644 struct desc_ptr dt;
6aa8b732 2645 int i;
cd2276a7 2646 unsigned long kvm_vmx_return;
6e5d865c 2647 u32 exec_control;
6aa8b732 2648
6aa8b732 2649 /* I/O */
3e7c73e9
AK		 2650 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2651 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2652
25c5f225 2653 if (cpu_has_vmx_msr_bitmap())
5897297b 2654 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2655
6aa8b732
AK		 2656 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2657
6aa8b732 2658 /* Control */
1c3d14fe
YS		 2659 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2660 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2661
2662 exec_control = vmcs_config.cpu_based_exec_ctrl;
2663 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2664 exec_control &= ~CPU_BASED_TPR_SHADOW;
2665#ifdef CONFIG_X86_64
2666 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2667 CPU_BASED_CR8_LOAD_EXITING;
2668#endif
2669 }
089d034e 2670 if (!enable_ept)
d56f546d 2671 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2672 CPU_BASED_CR3_LOAD_EXITING |
2673 CPU_BASED_INVLPG_EXITING;
6e5d865c 2674 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2675
83ff3b9d
SY		 2676 if (cpu_has_secondary_exec_ctrls()) {
2677 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2678 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2679 exec_control &=
2680 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2681 if (vmx->vpid == 0)
2682 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2683 if (!enable_ept) {
d56f546d 2684 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2685 enable_unrestricted_guest = 0;
2686 }
3a624e29
NK		 2687 if (!enable_unrestricted_guest)
2688 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2689 if (!ple_gap)
2690 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2691 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2692 }
f78e0e2e 2693
4b8d54f9
ZE		 2694 if (ple_gap) {
2695 vmcs_write32(PLE_GAP, ple_gap);
2696 vmcs_write32(PLE_WINDOW, ple_window);
2697 }
2698
c7addb90
AK		 2699 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2700 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2701 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2702
1c11e713 2703 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2704 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2705 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2706
2707 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2708 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2709 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
9581d442
AK		 2710 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2711 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6aa8b732 2712 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2713#ifdef CONFIG_X86_64
6aa8b732
AK		 2714 rdmsrl(MSR_FS_BASE, a);
2715 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2716 rdmsrl(MSR_GS_BASE, a);
2717 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2718#else
2719 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2720 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2721#endif
2722
2723 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2724
ec68798c 2725 native_store_idt(&dt);
89a27f4d 2726 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2727
d77c26fc 2728 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2729 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2730 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2731 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2732 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2733 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2734 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2735
2736 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2737 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2738 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2739 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2740 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2741 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2742
468d472f
SY		 2743 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2744 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2745 host_pat = msr_low | ((u64) msr_high << 32);
2746 vmcs_write64(HOST_IA32_PAT, host_pat);
2747 }
2748 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2749 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2750 host_pat = msr_low | ((u64) msr_high << 32);
2751 /* Write the default value follow host pat */
2752 vmcs_write64(GUEST_IA32_PAT, host_pat);
2753 /* Keep arch.pat sync with GUEST_IA32_PAT */
2754 vmx->vcpu.arch.pat = host_pat;
2755 }
2756
6aa8b732
AK		 2757 for (i = 0; i < NR_VMX_MSR; ++i) {
2758 u32 index = vmx_msr_index[i];
2759 u32 data_low, data_high;
a2fa3e9f 2760 int j = vmx->nmsrs;
6aa8b732
AK		 2761
2762 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2763 continue;
432bd6cb
AK		 2764 if (wrmsr_safe(index, data_low, data_high) < 0)
2765 continue;
26bb0981
AK		 2766 vmx->guest_msrs[j].index = i;
2767 vmx->guest_msrs[j].data = 0;
d5696725 2768 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2769 ++vmx->nmsrs;
6aa8b732 2770 }
6aa8b732 2771
1c3d14fe 2772 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2773
2774 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2775 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2776
e00c8cf2 2777 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2778 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2779 if (enable_ept)
2780 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2781 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2782
99e3e30a 2783 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 2784
e00c8cf2
AK		 2785 return 0;
2786}
2787
2788static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2789{
2790 struct vcpu_vmx *vmx = to_vmx(vcpu);
2791 u64 msr;
4b9d3a04 2792 int ret;
e00c8cf2 2793
5fdbf976 2794 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 2795
7ffd92c5 2796 vmx->rmode.vm86_active = 0;
e00c8cf2 2797
3b86cd99
JK		 2798 vmx->soft_vnmi_blocked = 0;
2799
ad312c7c 2800 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2801 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2802 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2803 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2804 msr |= MSR_IA32_APICBASE_BSP;
2805 kvm_set_apic_base(&vmx->vcpu, msr);
2806
10ab25cd
JK		 2807 ret = fx_init(&vmx->vcpu);
2808 if (ret != 0)
2809 goto out;
e00c8cf2 2810
5706be0d 2811 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2812 /*
2813 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2814 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2815 */
c5af89b6 2816 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2817 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2818 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2819 } else {
ad312c7c
ZX		 2820 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2821 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2822 }
e00c8cf2
AK		 2823
2824 seg_setup(VCPU_SREG_DS);
2825 seg_setup(VCPU_SREG_ES);
2826 seg_setup(VCPU_SREG_FS);
2827 seg_setup(VCPU_SREG_GS);
2828 seg_setup(VCPU_SREG_SS);
2829
2830 vmcs_write16(GUEST_TR_SELECTOR, 0);
2831 vmcs_writel(GUEST_TR_BASE, 0);
2832 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2833 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2834
2835 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2836 vmcs_writel(GUEST_LDTR_BASE, 0);
2837 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2838 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2839
2840 vmcs_write32(GUEST_SYSENTER_CS, 0);
2841 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2842 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2843
2844 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2845 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2846 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2847 else
5fdbf976
MT		 2848 kvm_rip_write(vcpu, 0);
2849 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2850
e00c8cf2
AK		 2851 vmcs_writel(GUEST_DR7, 0x400);
2852
2853 vmcs_writel(GUEST_GDTR_BASE, 0);
2854 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2855
2856 vmcs_writel(GUEST_IDTR_BASE, 0);
2857 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2858
443381a8 2859 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 2860 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2861 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2862
e00c8cf2
AK		 2863 /* Special registers */
2864 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2865
2866 setup_msrs(vmx);
2867
6aa8b732
AK		 2868 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2869
f78e0e2e
SY		 2870 if (cpu_has_vmx_tpr_shadow()) {
2871 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2872 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2873 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 2874 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 2875 vmcs_write32(TPR_THRESHOLD, 0);
2876 }
2877
2878 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2879 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2880 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2881
2384d2b3
SY		 2882 if (vmx->vpid != 0)
2883 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2884
fa40052c 2885 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2886 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2887 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2888 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2889 vmx_fpu_activate(&vmx->vcpu);
2890 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2891
b9d762fa 2892 vpid_sync_context(vmx);
2384d2b3 2893
3200f405 2894 ret = 0;
6aa8b732 2895
a89a8fb9
MG		 2896 /* HACK: Don't enable emulation on guest boot/reset */
2897 vmx->emulation_required = 0;
2898
6aa8b732
AK		 2899out:
2900 return ret;
2901}
2902
3b86cd99
JK		 2903static void enable_irq_window(struct kvm_vcpu *vcpu)
2904{
2905 u32 cpu_based_vm_exec_control;
2906
2907 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2908 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2909 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2910}
2911
2912static void enable_nmi_window(struct kvm_vcpu *vcpu)
2913{
2914 u32 cpu_based_vm_exec_control;
2915
2916 if (!cpu_has_virtual_nmis()) {
2917 enable_irq_window(vcpu);
2918 return;
2919 }
2920
30bd0c4c
AK		 2921 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2922 enable_irq_window(vcpu);
2923 return;
2924 }
3b86cd99
JK		 2925 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2926 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2927 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2928}
2929
66fd3f7f 2930static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2931{
9c8cba37 2932 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2933 uint32_t intr;
2934 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2935
229456fc 2936 trace_kvm_inj_virq(irq);
2714d1d3 2937
fa89a817 2938 ++vcpu->stat.irq_injections;
7ffd92c5 2939 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2940 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2941 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 2942 return;
2943 }
66fd3f7f
GN		 2944 intr = irq | INTR_INFO_VALID_MASK;
2945 if (vcpu->arch.interrupt.soft) {
2946 intr |= INTR_TYPE_SOFT_INTR;
2947 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2948 vmx->vcpu.arch.event_exit_inst_len);
2949 } else
2950 intr |= INTR_TYPE_EXT_INTR;
2951 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 2952 vmx_clear_hlt(vcpu);
85f455f7
ED		 2953}
2954
f08864b4
SY		 2955static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2956{
66a5a347
JK		 2957 struct vcpu_vmx *vmx = to_vmx(vcpu);
2958
3b86cd99
JK		 2959 if (!cpu_has_virtual_nmis()) {
2960 /*
2961 * Tracking the NMI-blocked state in software is built upon
2962 * finding the next open IRQ window. This, in turn, depends on
2963 * well-behaving guests: They have to keep IRQs disabled at
2964 * least as long as the NMI handler runs. Otherwise we may
2965 * cause NMI nesting, maybe breaking the guest. But as this is
2966 * highly unlikely, we can live with the residual risk.
2967 */
2968 vmx->soft_vnmi_blocked = 1;
2969 vmx->vnmi_blocked_time = 0;
2970 }
2971
487b391d 2972 ++vcpu->stat.nmi_injections;
9d58b931 2973 vmx->nmi_known_unmasked = false;
7ffd92c5 2974 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2975 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2976 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 2977 return;
2978 }
f08864b4
SY		 2979 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2980 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 2981 vmx_clear_hlt(vcpu);
f08864b4
SY		 2982}
2983
c4282df9 2984static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2985{
3b86cd99 2986 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2987 return 0;
33f089ca 2988
c4282df9 2989 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 2990 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2991 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2992}
2993
3cfc3092
JK		 2994static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2995{
2996 if (!cpu_has_virtual_nmis())
2997 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 2998 if (to_vmx(vcpu)->nmi_known_unmasked)
2999 return false;
c332c83a 3000 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 3001}
3002
3003static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3004{
3005 struct vcpu_vmx *vmx = to_vmx(vcpu);
3006
3007 if (!cpu_has_virtual_nmis()) {
3008 if (vmx->soft_vnmi_blocked != masked) {
3009 vmx->soft_vnmi_blocked = masked;
3010 vmx->vnmi_blocked_time = 0;
3011 }
3012 } else {
9d58b931 3013 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 3014 if (masked)
3015 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3016 GUEST_INTR_STATE_NMI);
3017 else
3018 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3019 GUEST_INTR_STATE_NMI);
3020 }
3021}
3022
78646121
GN		 3023static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3024{
c4282df9
GN		 3025 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3026 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3027 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 3028}
3029
cbc94022
IE		 3030static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3031{
3032 int ret;
3033 struct kvm_userspace_memory_region tss_mem = {
6fe63979 3034 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 3035 .guest_phys_addr = addr,
3036 .memory_size = PAGE_SIZE * 3,
3037 .flags = 0,
3038 };
3039
3040 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3041 if (ret)
3042 return ret;
bfc6d222 3043 kvm->arch.tss_addr = addr;
93ea5388
GN		 3044 if (!init_rmode_tss(kvm))
3045 return -ENOMEM;
3046
cbc94022
IE		 3047 return 0;
3048}
3049
6aa8b732
AK		 3050static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3051 int vec, u32 err_code)
3052{
b3f37707
NK		 3053 /*
3054 * Instruction with address size override prefix opcode 0x67
3055 * Cause the #SS fault with 0 error code in VM86 mode.
3056 */
3057 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 3058 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 3059 return 1;
77ab6db0
JK		 3060 /*
3061 * Forward all other exceptions that are valid in real mode.
3062 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3063 * the required debugging infrastructure rework.
3064 */
3065 switch (vec) {
77ab6db0 3066 case DB_VECTOR:
d0bfb940
JK		 3067 if (vcpu->guest_debug &
3068 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3069 return 0;
3070 kvm_queue_exception(vcpu, vec);
3071 return 1;
77ab6db0 3072 case BP_VECTOR:
c573cd22
JK		 3073 /*
3074 * Update instruction length as we may reinject the exception
3075 * from user space while in guest debugging mode.
3076 */
3077 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3078 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 3079 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3080 return 0;
3081 /* fall through */
3082 case DE_VECTOR:
77ab6db0
JK		 3083 case OF_VECTOR:
3084 case BR_VECTOR:
3085 case UD_VECTOR:
3086 case DF_VECTOR:
3087 case SS_VECTOR:
3088 case GP_VECTOR:
3089 case MF_VECTOR:
3090 kvm_queue_exception(vcpu, vec);
3091 return 1;
3092 }
6aa8b732
AK		 3093 return 0;
3094}
3095
a0861c02
AK		 3096/*
3097 * Trigger machine check on the host. We assume all the MSRs are already set up
3098 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3099 * We pass a fake environment to the machine check handler because we want
3100 * the guest to be always treated like user space, no matter what context
3101 * it used internally.
3102 */
3103static void kvm_machine_check(void)
3104{
3105#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3106 struct pt_regs regs = {
3107 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3108 .flags = X86_EFLAGS_IF,
3109 };
3110
3111 do_machine_check(&regs, 0);
3112#endif
3113}
3114
851ba692 3115static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3116{
3117 /* already handled by vcpu_run */
3118 return 1;
3119}
3120
851ba692 3121static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3122{
1155f76a 3123 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3124 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3125 u32 intr_info, ex_no, error_code;
42dbaa5a 3126 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3127 u32 vect_info;
3128 enum emulation_result er;
3129
1155f76a 3130 vect_info = vmx->idt_vectoring_info;
88786475 3131 intr_info = vmx->exit_intr_info;
6aa8b732 3132
a0861c02 3133 if (is_machine_check(intr_info))
851ba692 3134 return handle_machine_check(vcpu);
a0861c02 3135
6aa8b732 3136 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3137 !is_page_fault(intr_info)) {
3138 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3139 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3140 vcpu->run->internal.ndata = 2;
3141 vcpu->run->internal.data[0] = vect_info;
3142 vcpu->run->internal.data[1] = intr_info;
3143 return 0;
3144 }
6aa8b732 3145
e4a41889 3146 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3147 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3148
3149 if (is_no_device(intr_info)) {
5fd86fcf 3150 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3151 return 1;
3152 }
3153
7aa81cc0 3154 if (is_invalid_opcode(intr_info)) {
51d8b661 3155 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 3156 if (er != EMULATE_DONE)
7ee5d940 3157 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3158 return 1;
3159 }
3160
6aa8b732 3161 error_code = 0;
5fdbf976 3162 rip = kvm_rip_read(vcpu);
2e11384c 3163 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3164 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3165 if (is_page_fault(intr_info)) {
1439442c 3166 /* EPT won't cause page fault directly */
089d034e 3167 if (enable_ept)
1439442c 3168 BUG();
6aa8b732 3169 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3170 trace_kvm_page_fault(cr2, error_code);
3171
3298b75c 3172 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3173 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 3174 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 3175 }
3176
7ffd92c5 3177 if (vmx->rmode.vm86_active &&
6aa8b732 3178 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3179 error_code)) {
ad312c7c
ZX		 3180 if (vcpu->arch.halt_request) {
3181 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3182 return kvm_emulate_halt(vcpu);
3183 }
6aa8b732 3184 return 1;
72d6e5a0 3185 }
6aa8b732 3186
d0bfb940 3187 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3188 switch (ex_no) {
3189 case DB_VECTOR:
3190 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3191 if (!(vcpu->guest_debug &
3192 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3193 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3194 kvm_queue_exception(vcpu, DB_VECTOR);
3195 return 1;
3196 }
3197 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3198 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3199 /* fall through */
3200 case BP_VECTOR:
c573cd22
JK		 3201 /*
3202 * Update instruction length as we may reinject #BP from
3203 * user space while in guest debugging mode. Reading it for
3204 * #DB as well causes no harm, it is not used in that case.
3205 */
3206 vmx->vcpu.arch.event_exit_inst_len =
3207 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3208 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3209 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3210 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3211 break;
3212 default:
d0bfb940
JK		 3213 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3214 kvm_run->ex.exception = ex_no;
3215 kvm_run->ex.error_code = error_code;
42dbaa5a 3216 break;
6aa8b732 3217 }
6aa8b732
AK		 3218 return 0;
3219}
3220
851ba692 3221static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3222{
1165f5fe 3223 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3224 return 1;
3225}
3226
851ba692 3227static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3228{
851ba692 3229 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3230 return 0;
3231}
6aa8b732 3232
851ba692 3233static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3234{
bfdaab09 3235 unsigned long exit_qualification;
34c33d16 3236 int size, in, string;
039576c0 3237 unsigned port;
6aa8b732 3238
bfdaab09 3239 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3240 string = (exit_qualification & 16) != 0;
cf8f70bf 3241 in = (exit_qualification & 8) != 0;
e70669ab 3242
cf8f70bf 3243 ++vcpu->stat.io_exits;
e70669ab 3244
cf8f70bf 3245 if (string || in)
51d8b661 3246 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 3247
cf8f70bf
GN		 3248 port = exit_qualification >> 16;
3249 size = (exit_qualification & 7) + 1;
e93f36bc 3250 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3251
3252 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3253}
3254
102d8325
IM		 3255static void
3256vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3257{
3258 /*
3259 * Patch in the VMCALL instruction:
3260 */
3261 hypercall[0] = 0x0f;
3262 hypercall[1] = 0x01;
3263 hypercall[2] = 0xc1;
102d8325
IM		 3264}
3265
851ba692 3266static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3267{
229456fc 3268 unsigned long exit_qualification, val;
6aa8b732
AK		 3269 int cr;
3270 int reg;
49a9b07e 3271 int err;
6aa8b732 3272
bfdaab09 3273 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3274 cr = exit_qualification & 15;
3275 reg = (exit_qualification >> 8) & 15;
3276 switch ((exit_qualification >> 4) & 3) {
3277 case 0: /* mov to cr */
229456fc
MT		 3278 val = kvm_register_read(vcpu, reg);
3279 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3280 switch (cr) {
3281 case 0:
49a9b07e 3282 err = kvm_set_cr0(vcpu, val);
db8fcefa 3283 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3284 return 1;
3285 case 3:
2390218b 3286 err = kvm_set_cr3(vcpu, val);
db8fcefa 3287 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3288 return 1;
3289 case 4:
a83b29c6 3290 err = kvm_set_cr4(vcpu, val);
db8fcefa 3291 kvm_complete_insn_gp(vcpu, err);
6aa8b732 3292 return 1;
0a5fff19
GN		 3293 case 8: {
3294 u8 cr8_prev = kvm_get_cr8(vcpu);
3295 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 3296 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 3297 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 3298 if (irqchip_in_kernel(vcpu->kvm))
3299 return 1;
3300 if (cr8_prev <= cr8)
3301 return 1;
851ba692 3302 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3303 return 0;
3304 }
6aa8b732
AK		 3305 };
3306 break;
25c4c276 3307 case 2: /* clts */
edcafe3c 3308 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3309 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3310 skip_emulated_instruction(vcpu);
6b52d186 3311 vmx_fpu_activate(vcpu);
25c4c276 3312 return 1;
6aa8b732
AK		 3313 case 1: /*mov from cr*/
3314 switch (cr) {
3315 case 3:
9f8fe504
AK		 3316 val = kvm_read_cr3(vcpu);
3317 kvm_register_write(vcpu, reg, val);
3318 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3319 skip_emulated_instruction(vcpu);
3320 return 1;
3321 case 8:
229456fc
MT		 3322 val = kvm_get_cr8(vcpu);
3323 kvm_register_write(vcpu, reg, val);
3324 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3325 skip_emulated_instruction(vcpu);
3326 return 1;
3327 }
3328 break;
3329 case 3: /* lmsw */
a1f83a74 3330 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3331 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3332 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3333
3334 skip_emulated_instruction(vcpu);
3335 return 1;
3336 default:
3337 break;
3338 }
851ba692 3339 vcpu->run->exit_reason = 0;
f0242478 3340 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3341 (int)(exit_qualification >> 4) & 3, cr);
3342 return 0;
3343}
3344
851ba692 3345static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3346{
bfdaab09 3347 unsigned long exit_qualification;
6aa8b732
AK		 3348 int dr, reg;
3349
f2483415 3350 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3351 if (!kvm_require_cpl(vcpu, 0))
3352 return 1;
42dbaa5a
JK		 3353 dr = vmcs_readl(GUEST_DR7);
3354 if (dr & DR7_GD) {
3355 /*
3356 * As the vm-exit takes precedence over the debug trap, we
3357 * need to emulate the latter, either for the host or the
3358 * guest debugging itself.
3359 */
3360 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3361 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3362 vcpu->run->debug.arch.dr7 = dr;
3363 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3364 vmcs_readl(GUEST_CS_BASE) +
3365 vmcs_readl(GUEST_RIP);
851ba692
AK		 3366 vcpu->run->debug.arch.exception = DB_VECTOR;
3367 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3368 return 0;
3369 } else {
3370 vcpu->arch.dr7 &= ~DR7_GD;
3371 vcpu->arch.dr6 |= DR6_BD;
3372 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3373 kvm_queue_exception(vcpu, DB_VECTOR);
3374 return 1;
3375 }
3376 }
3377
bfdaab09 3378 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3379 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3380 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3381 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3382 unsigned long val;
3383 if (!kvm_get_dr(vcpu, dr, &val))
3384 kvm_register_write(vcpu, reg, val);
3385 } else
3386 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3387 skip_emulated_instruction(vcpu);
3388 return 1;
3389}
3390
020df079
GN		 3391static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3392{
3393 vmcs_writel(GUEST_DR7, val);
3394}
3395
851ba692 3396static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3397{
06465c5a
AK		 3398 kvm_emulate_cpuid(vcpu);
3399 return 1;
6aa8b732
AK		 3400}
3401
851ba692 3402static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3403{
ad312c7c 3404 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3405 u64 data;
3406
3407 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3408 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3409 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3410 return 1;
3411 }
3412
229456fc 3413 trace_kvm_msr_read(ecx, data);
2714d1d3 3414
6aa8b732 3415 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3416 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3417 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3418 skip_emulated_instruction(vcpu);
3419 return 1;
3420}
3421
851ba692 3422static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3423{
ad312c7c
ZX		 3424 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3425 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3426 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3427
3428 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3429 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3430 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3431 return 1;
3432 }
3433
59200273 3434 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3435 skip_emulated_instruction(vcpu);
3436 return 1;
3437}
3438
851ba692 3439static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 3440{
3842d135 3441 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 3442 return 1;
3443}
3444
851ba692 3445static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3446{
85f455f7
ED		 3447 u32 cpu_based_vm_exec_control;
3448
3449 /* clear pending irq */
3450 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3451 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3452 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3453
3842d135
AK		 3454 kvm_make_request(KVM_REQ_EVENT, vcpu);
3455
a26bf12a 3456 ++vcpu->stat.irq_window_exits;
2714d1d3 3457
c1150d8c
DL		 3458 /*
3459 * If the user space waits to inject interrupts, exit as soon as
3460 * possible
3461 */
8061823a 3462 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3463 vcpu->run->request_interrupt_window &&
8061823a 3464 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3465 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3466 return 0;
3467 }
6aa8b732
AK		 3468 return 1;
3469}
3470
851ba692 3471static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3472{
3473 skip_emulated_instruction(vcpu);
d3bef15f 3474 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3475}
3476
851ba692 3477static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3478{
510043da 3479 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3480 kvm_emulate_hypercall(vcpu);
3481 return 1;
c21415e8
IM		 3482}
3483
851ba692 3484static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3485{
3486 kvm_queue_exception(vcpu, UD_VECTOR);
3487 return 1;
3488}
3489
ec25d5e6
GN		 3490static int handle_invd(struct kvm_vcpu *vcpu)
3491{
51d8b661 3492 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 3493}
3494
851ba692 3495static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3496{
f9c617f6 3497 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3498
3499 kvm_mmu_invlpg(vcpu, exit_qualification);
3500 skip_emulated_instruction(vcpu);
3501 return 1;
3502}
3503
851ba692 3504static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3505{
3506 skip_emulated_instruction(vcpu);
f5f48ee1 3507 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3508 return 1;
3509}
3510
2acf923e
DC		 3511static int handle_xsetbv(struct kvm_vcpu *vcpu)
3512{
3513 u64 new_bv = kvm_read_edx_eax(vcpu);
3514 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3515
3516 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3517 skip_emulated_instruction(vcpu);
3518 return 1;
3519}
3520
851ba692 3521static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3522{
51d8b661 3523 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 3524}
3525
851ba692 3526static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3527{
60637aac 3528 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3529 unsigned long exit_qualification;
e269fb21
JK		 3530 bool has_error_code = false;
3531 u32 error_code = 0;
37817f29 3532 u16 tss_selector;
64a7ec06
GN		 3533 int reason, type, idt_v;
3534
3535 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3536 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3537
3538 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3539
3540 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3541 if (reason == TASK_SWITCH_GATE && idt_v) {
3542 switch (type) {
3543 case INTR_TYPE_NMI_INTR:
3544 vcpu->arch.nmi_injected = false;
654f06fc 3545 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 3546 break;
3547 case INTR_TYPE_EXT_INTR:
66fd3f7f 3548 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3549 kvm_clear_interrupt_queue(vcpu);
3550 break;
3551 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3552 if (vmx->idt_vectoring_info &
3553 VECTORING_INFO_DELIVER_CODE_MASK) {
3554 has_error_code = true;
3555 error_code =
3556 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3557 }
3558 /* fall through */
64a7ec06
GN		 3559 case INTR_TYPE_SOFT_EXCEPTION:
3560 kvm_clear_exception_queue(vcpu);
3561 break;
3562 default:
3563 break;
3564 }
60637aac 3565 }
37817f29
IE		 3566 tss_selector = exit_qualification;
3567
64a7ec06
GN		 3568 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3569 type != INTR_TYPE_EXT_INTR &&
3570 type != INTR_TYPE_NMI_INTR))
3571 skip_emulated_instruction(vcpu);
3572
acb54517
GN		 3573 if (kvm_task_switch(vcpu, tss_selector, reason,
3574 has_error_code, error_code) == EMULATE_FAIL) {
3575 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3576 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3577 vcpu->run->internal.ndata = 0;
42dbaa5a 3578 return 0;
acb54517 3579 }
42dbaa5a
JK		 3580
3581 /* clear all local breakpoint enable flags */
3582 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3583
3584 /*
3585 * TODO: What about debug traps on tss switch?
3586 * Are we supposed to inject them and update dr6?
3587 */
3588
3589 return 1;
37817f29
IE		 3590}
3591
851ba692 3592static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3593{
f9c617f6 3594 unsigned long exit_qualification;
1439442c 3595 gpa_t gpa;
1439442c 3596 int gla_validity;
1439442c 3597
f9c617f6 3598 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3599
3600 if (exit_qualification & (1 << 6)) {
3601 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3602 return -EINVAL;
1439442c
SY		 3603 }
3604
3605 gla_validity = (exit_qualification >> 7) & 0x3;
3606 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3607 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3608 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3609 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3610 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3611 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3612 (long unsigned int)exit_qualification);
851ba692
AK		 3613 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3614 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3615 return 0;
1439442c
SY		 3616 }
3617
3618 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3619 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 3620 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 3621}
3622
68f89400
MT		 3623static u64 ept_rsvd_mask(u64 spte, int level)
3624{
3625 int i;
3626 u64 mask = 0;
3627
3628 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3629 mask |= (1ULL << i);
3630
3631 if (level > 2)
3632 /* bits 7:3 reserved */
3633 mask |= 0xf8;
3634 else if (level == 2) {
3635 if (spte & (1ULL << 7))
3636 /* 2MB ref, bits 20:12 reserved */
3637 mask |= 0x1ff000;
3638 else
3639 /* bits 6:3 reserved */
3640 mask |= 0x78;
3641 }
3642
3643 return mask;
3644}
3645
3646static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3647 int level)
3648{
3649 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3650
3651 /* 010b (write-only) */
3652 WARN_ON((spte & 0x7) == 0x2);
3653
3654 /* 110b (write/execute) */
3655 WARN_ON((spte & 0x7) == 0x6);
3656
3657 /* 100b (execute-only) and value not supported by logical processor */
3658 if (!cpu_has_vmx_ept_execute_only())
3659 WARN_ON((spte & 0x7) == 0x4);
3660
3661 /* not 000b */
3662 if ((spte & 0x7)) {
3663 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3664
3665 if (rsvd_bits != 0) {
3666 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3667 __func__, rsvd_bits);
3668 WARN_ON(1);
3669 }
3670
3671 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3672 u64 ept_mem_type = (spte & 0x38) >> 3;
3673
3674 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3675 ept_mem_type == 7) {
3676 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3677 __func__, ept_mem_type);
3678 WARN_ON(1);
3679 }
3680 }
3681 }
3682}
3683
851ba692 3684static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3685{
3686 u64 sptes[4];
3687 int nr_sptes, i;
3688 gpa_t gpa;
3689
3690 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3691
3692 printk(KERN_ERR "EPT: Misconfiguration.\n");
3693 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3694
3695 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3696
3697 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3698 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3699
851ba692
AK		 3700 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3701 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3702
3703 return 0;
3704}
3705
851ba692 3706static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3707{
3708 u32 cpu_based_vm_exec_control;
3709
3710 /* clear pending NMI */
3711 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3712 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3713 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3714 ++vcpu->stat.nmi_window_exits;
3842d135 3715 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 3716
3717 return 1;
3718}
3719
80ced186 3720static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3721{
8b3079a5
AK		 3722 struct vcpu_vmx *vmx = to_vmx(vcpu);
3723 enum emulation_result err = EMULATE_DONE;
80ced186 3724 int ret = 1;
49e9d557
AK		 3725 u32 cpu_exec_ctrl;
3726 bool intr_window_requested;
3727
3728 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3729 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 3730
3731 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 3732 if (intr_window_requested
3733 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3734 return handle_interrupt_window(&vmx->vcpu);
3735
51d8b661 3736 err = emulate_instruction(vcpu, 0);
ea953ef0 3737
80ced186
MG		 3738 if (err == EMULATE_DO_MMIO) {
3739 ret = 0;
3740 goto out;
3741 }
1d5a4d9b 3742
6d77dbfc
GN		 3743 if (err != EMULATE_DONE)
3744 return 0;
ea953ef0
MG		 3745
3746 if (signal_pending(current))
80ced186 3747 goto out;
ea953ef0
MG		 3748 if (need_resched())
3749 schedule();
3750 }
3751
80ced186
MG		 3752 vmx->emulation_required = 0;
3753out:
3754 return ret;
ea953ef0
MG		 3755}
3756
4b8d54f9
ZE		 3757/*
3758 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3759 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3760 */
9fb41ba8 3761static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3762{
3763 skip_emulated_instruction(vcpu);
3764 kvm_vcpu_on_spin(vcpu);
3765
3766 return 1;
3767}
3768
59708670
SY		 3769static int handle_invalid_op(struct kvm_vcpu *vcpu)
3770{
3771 kvm_queue_exception(vcpu, UD_VECTOR);
3772 return 1;
3773}
3774
6aa8b732
AK		 3775/*
3776 * The exit handlers return 1 if the exit was handled fully and guest execution
3777 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3778 * to be done to userspace and return 0.
3779 */
851ba692 3780static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3781 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3782 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3783 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3784 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3785 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3786 [EXIT_REASON_CR_ACCESS] = handle_cr,
3787 [EXIT_REASON_DR_ACCESS] = handle_dr,
3788 [EXIT_REASON_CPUID] = handle_cpuid,
3789 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3790 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3791 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3792 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 3793 [EXIT_REASON_INVD] = handle_invd,
a7052897 3794 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3795 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3796 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3797 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3798 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3799 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3800 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3801 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3802 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3803 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3804 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3805 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3806 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3807 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3808 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3809 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3810 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3811 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3812 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3813 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3814 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3815 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3816};
3817
3818static const int kvm_vmx_max_exit_handlers =
50a3485c 3819 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 3820
586f9607
AK		 3821static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3822{
3823 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3824 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3825}
3826
6aa8b732
AK		 3827/*
3828 * The guest has exited. See if we can fix it or if we need userspace
3829 * assistance.
3830 */
851ba692 3831static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3832{
29bd8a78 3833 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3834 u32 exit_reason = vmx->exit_reason;
1155f76a 3835 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3836
aa17911e 3837 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 3838
80ced186
MG		 3839 /* If guest state is invalid, start emulating */
3840 if (vmx->emulation_required && emulate_invalid_guest_state)
3841 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3842
5120702e
MG		 3843 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3844 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3845 vcpu->run->fail_entry.hardware_entry_failure_reason
3846 = exit_reason;
3847 return 0;
3848 }
3849
29bd8a78 3850 if (unlikely(vmx->fail)) {
851ba692
AK		 3851 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3852 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3853 = vmcs_read32(VM_INSTRUCTION_ERROR);
3854 return 0;
3855 }
6aa8b732 3856
d77c26fc 3857 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3858 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3859 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3860 exit_reason != EXIT_REASON_TASK_SWITCH))
3861 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3862 "(0x%x) and exit reason is 0x%x\n",
3863 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3864
3865 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3866 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3867 vmx->soft_vnmi_blocked = 0;
3b86cd99 3868 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3869 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3870 /*
3871 * This CPU don't support us in finding the end of an
3872 * NMI-blocked window if the guest runs with IRQs
3873 * disabled. So we pull the trigger after 1 s of
3874 * futile waiting, but inform the user about this.
3875 */
3876 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3877 "state on VCPU %d after 1 s timeout\n",
3878 __func__, vcpu->vcpu_id);
3879 vmx->soft_vnmi_blocked = 0;
3b86cd99 3880 }
3b86cd99
JK		 3881 }
3882
6aa8b732
AK		 3883 if (exit_reason < kvm_vmx_max_exit_handlers
3884 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3885 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3886 else {
851ba692
AK		 3887 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3888 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3889 }
3890 return 0;
3891}
3892
95ba8273 3893static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3894{
95ba8273 3895 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3896 vmcs_write32(TPR_THRESHOLD, 0);
3897 return;
3898 }
3899
95ba8273 3900 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3901}
3902
51aa01d1 3903static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 3904{
00eba012
AK		 3905 u32 exit_intr_info;
3906
3907 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
3908 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
3909 return;
3910
c5ca8e57 3911 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 3912 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 3913
3914 /* Handle machine checks before interrupts are enabled */
00eba012 3915 if (is_machine_check(exit_intr_info))
a0861c02
AK		 3916 kvm_machine_check();
3917
20f65983 3918 /* We need to handle NMIs before interrupts are enabled */
00eba012 3919 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3920 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3921 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3922 asm("int $2");
ff9d07a0
ZY		 3923 kvm_after_handle_nmi(&vmx->vcpu);
3924 }
51aa01d1 3925}
20f65983 3926
51aa01d1
AK		 3927static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3928{
c5ca8e57 3929 u32 exit_intr_info;
51aa01d1
AK		 3930 bool unblock_nmi;
3931 u8 vector;
3932 bool idtv_info_valid;
3933
3934 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 3935
cf393f75 3936 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 3937 if (vmx->nmi_known_unmasked)
3938 return;
c5ca8e57
AK		 3939 /*
3940 * Can't use vmx->exit_intr_info since we're not sure what
3941 * the exit reason is.
3942 */
3943 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 3944 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3945 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3946 /*
7b4a25cb 3947 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3948 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3949 * a guest IRET fault.
7b4a25cb
GN		 3950 * SDM 3: 23.2.2 (September 2008)
3951 * Bit 12 is undefined in any of the following cases:
3952 * If the VM exit sets the valid bit in the IDT-vectoring
3953 * information field.
3954 * If the VM exit is due to a double fault.
cf393f75 3955 */
7b4a25cb
GN		 3956 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3957 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3958 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3959 GUEST_INTR_STATE_NMI);
9d58b931
AK		 3960 else
3961 vmx->nmi_known_unmasked =
3962 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
3963 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3964 } else if (unlikely(vmx->soft_vnmi_blocked))
3965 vmx->vnmi_blocked_time +=
3966 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 3967}
3968
83422e17
AK		 3969static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3970 u32 idt_vectoring_info,
3971 int instr_len_field,
3972 int error_code_field)
51aa01d1 3973{
51aa01d1
AK		 3974 u8 vector;
3975 int type;
3976 bool idtv_info_valid;
3977
3978 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 3979
37b96e98
GN		 3980 vmx->vcpu.arch.nmi_injected = false;
3981 kvm_clear_exception_queue(&vmx->vcpu);
3982 kvm_clear_interrupt_queue(&vmx->vcpu);
3983
3984 if (!idtv_info_valid)
3985 return;
3986
3842d135
AK		 3987 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3988
668f612f
AK		 3989 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3990 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3991
64a7ec06 3992 switch (type) {
37b96e98
GN		 3993 case INTR_TYPE_NMI_INTR:
3994 vmx->vcpu.arch.nmi_injected = true;
668f612f 3995 /*
7b4a25cb 3996 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3997 * Clear bit "block by NMI" before VM entry if a NMI
3998 * delivery faulted.
668f612f 3999 */
654f06fc 4000 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 4001 break;
37b96e98 4002 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 4003 vmx->vcpu.arch.event_exit_inst_len =
83422e17 4004 vmcs_read32(instr_len_field);
66fd3f7f
GN		 4005 /* fall through */
4006 case INTR_TYPE_HARD_EXCEPTION:
35920a35 4007 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 4008 u32 err = vmcs_read32(error_code_field);
37b96e98 4009 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 4010 } else
4011 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 4012 break;
66fd3f7f
GN		 4013 case INTR_TYPE_SOFT_INTR:
4014 vmx->vcpu.arch.event_exit_inst_len =
83422e17 4015 vmcs_read32(instr_len_field);
66fd3f7f 4016 /* fall through */
37b96e98 4017 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 4018 kvm_queue_interrupt(&vmx->vcpu, vector,
4019 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 4020 break;
4021 default:
4022 break;
f7d9238f 4023 }
cf393f75
AK		 4024}
4025
83422e17
AK		 4026static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
4027{
4028 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
4029 VM_EXIT_INSTRUCTION_LEN,
4030 IDT_VECTORING_ERROR_CODE);
4031}
4032
b463a6f7
AK		 4033static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
4034{
4035 __vmx_complete_interrupts(to_vmx(vcpu),
4036 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
4037 VM_ENTRY_INSTRUCTION_LEN,
4038 VM_ENTRY_EXCEPTION_ERROR_CODE);
4039
4040 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
4041}
4042
c801949d
AK		 4043#ifdef CONFIG_X86_64
4044#define R "r"
4045#define Q "q"
4046#else
4047#define R "e"
4048#define Q "l"
4049#endif
4050
a3b5ba49 4051static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 4052{
a2fa3e9f 4053 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b
AK		 4054
4055 /* Record the guest's net vcpu time for enforced NMI injections. */
4056 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4057 vmx->entry_time = ktime_get();
4058
4059 /* Don't enter VMX if guest state is invalid, let the exit handler
4060 start emulation until we arrive back to a valid state */
4061 if (vmx->emulation_required && emulate_invalid_guest_state)
4062 return;
4063
4064 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4065 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4066 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4067 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4068
4069 /* When single-stepping over STI and MOV SS, we must clear the
4070 * corresponding interruptibility bits in the guest state. Otherwise
4071 * vmentry fails as it then expects bit 14 (BS) in pending debug
4072 * exceptions being set, but that's not correct for the guest debugging
4073 * case. */
4074 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4075 vmx_set_interrupt_shadow(vcpu, 0);
4076
4077 asm(
6aa8b732 4078 /* Store host registers */
c801949d 4079 "push %%"R"dx; push %%"R"bp;"
40712fae 4080 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 4081 "push %%"R"cx \n\t"
313dbd49
AK		 4082 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4083 "je 1f \n\t"
4084 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 4085 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 4086 "1: \n\t"
d3edefc0
AK		 4087 /* Reload cr2 if changed */
4088 "mov %c[cr2](%0), %%"R"ax \n\t"
4089 "mov %%cr2, %%"R"dx \n\t"
4090 "cmp %%"R"ax, %%"R"dx \n\t"
4091 "je 2f \n\t"
4092 "mov %%"R"ax, %%cr2 \n\t"
4093 "2: \n\t"
6aa8b732 4094 /* Check if vmlaunch of vmresume is needed */
e08aa78a 4095 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 4096 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 4097 "mov %c[rax](%0), %%"R"ax \n\t"
4098 "mov %c[rbx](%0), %%"R"bx \n\t"
4099 "mov %c[rdx](%0), %%"R"dx \n\t"
4100 "mov %c[rsi](%0), %%"R"si \n\t"
4101 "mov %c[rdi](%0), %%"R"di \n\t"
4102 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 4103#ifdef CONFIG_X86_64
e08aa78a
AK		 4104 "mov %c[r8](%0), %%r8 \n\t"
4105 "mov %c[r9](%0), %%r9 \n\t"
4106 "mov %c[r10](%0), %%r10 \n\t"
4107 "mov %c[r11](%0), %%r11 \n\t"
4108 "mov %c[r12](%0), %%r12 \n\t"
4109 "mov %c[r13](%0), %%r13 \n\t"
4110 "mov %c[r14](%0), %%r14 \n\t"
4111 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 4112#endif
c801949d
AK		 4113 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4114
6aa8b732 4115 /* Enter guest mode */
cd2276a7 4116 "jne .Llaunched \n\t"
4ecac3fd 4117 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 4118 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 4119 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 4120 ".Lkvm_vmx_return: "
6aa8b732 4121 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 4122 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4123 "pop %0 \n\t"
c801949d
AK		 4124 "mov %%"R"ax, %c[rax](%0) \n\t"
4125 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 4126 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 4127 "mov %%"R"dx, %c[rdx](%0) \n\t"
4128 "mov %%"R"si, %c[rsi](%0) \n\t"
4129 "mov %%"R"di, %c[rdi](%0) \n\t"
4130 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 4131#ifdef CONFIG_X86_64
e08aa78a
AK		 4132 "mov %%r8, %c[r8](%0) \n\t"
4133 "mov %%r9, %c[r9](%0) \n\t"
4134 "mov %%r10, %c[r10](%0) \n\t"
4135 "mov %%r11, %c[r11](%0) \n\t"
4136 "mov %%r12, %c[r12](%0) \n\t"
4137 "mov %%r13, %c[r13](%0) \n\t"
4138 "mov %%r14, %c[r14](%0) \n\t"
4139 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 4140#endif
c801949d
AK		 4141 "mov %%cr2, %%"R"ax \n\t"
4142 "mov %%"R"ax, %c[cr2](%0) \n\t"
4143
1c696d0e 4144 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 4145 "setbe %c[fail](%0) \n\t"
4146 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4147 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4148 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 4149 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 4150 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4151 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4152 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4153 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4154 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4155 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4156 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4157#ifdef CONFIG_X86_64
ad312c7c
ZX		 4158 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4159 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4160 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4161 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4162 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4163 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4164 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4165 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4166#endif
40712fae
AK		 4167 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4168 [wordsize]"i"(sizeof(ulong))
c2036300 4169 : "cc", "memory"
07d6f555 4170 , R"ax", R"bx", R"di", R"si"
c2036300 4171#ifdef CONFIG_X86_64
c2036300
LV		 4172 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4173#endif
4174 );
6aa8b732 4175
6de4f3ad 4176 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 4177 | (1 << VCPU_EXREG_RFLAGS)
69c73028 4178 | (1 << VCPU_EXREG_CPL)
aff48baa
AK		 4179 | (1 << VCPU_EXREG_PDPTR)
4180 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 4181 vcpu->arch.regs_dirty = 0;
4182
1155f76a
AK		 4183 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4184
d77c26fc 4185 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4186 vmx->launched = 1;
1b6269db 4187
51aa01d1 4188 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1
AK		 4189
4190 vmx_complete_atomic_exit(vmx);
4191 vmx_recover_nmi_blocking(vmx);
cf393f75 4192 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4193}
4194
c801949d
AK		 4195#undef R
4196#undef Q
4197
6aa8b732
AK		 4198static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4199{
a2fa3e9f
GH		 4200 struct vcpu_vmx *vmx = to_vmx(vcpu);
4201
4202 if (vmx->vmcs) {
543e4243 4203 vcpu_clear(vmx);
a2fa3e9f
GH		 4204 free_vmcs(vmx->vmcs);
4205 vmx->vmcs = NULL;
6aa8b732
AK		 4206 }
4207}
4208
4209static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4210{
fb3f0f51
RR		 4211 struct vcpu_vmx *vmx = to_vmx(vcpu);
4212
cdbecfc3 4213 free_vpid(vmx);
6aa8b732 4214 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4215 kfree(vmx->guest_msrs);
4216 kvm_vcpu_uninit(vcpu);
a4770347 4217 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4218}
4219
4610c9cc
DX		 4220static inline void vmcs_init(struct vmcs *vmcs)
4221{
4222 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4223
4224 if (!vmm_exclusive)
4225 kvm_cpu_vmxon(phys_addr);
4226
4227 vmcs_clear(vmcs);
4228
4229 if (!vmm_exclusive)
4230 kvm_cpu_vmxoff();
4231}
4232
fb3f0f51 4233static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4234{
fb3f0f51 4235 int err;
c16f862d 4236 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4237 int cpu;
6aa8b732 4238
a2fa3e9f 4239 if (!vmx)
fb3f0f51
RR		 4240 return ERR_PTR(-ENOMEM);
4241
2384d2b3
SY		 4242 allocate_vpid(vmx);
4243
fb3f0f51
RR		 4244 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4245 if (err)
4246 goto free_vcpu;
965b58a5 4247
a2fa3e9f 4248 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4249 if (!vmx->guest_msrs) {
4250 err = -ENOMEM;
4251 goto uninit_vcpu;
4252 }
965b58a5 4253
a2fa3e9f
GH		 4254 vmx->vmcs = alloc_vmcs();
4255 if (!vmx->vmcs)
fb3f0f51 4256 goto free_msrs;
a2fa3e9f 4257
4610c9cc 4258 vmcs_init(vmx->vmcs);
a2fa3e9f 4259
15ad7146
AK		 4260 cpu = get_cpu();
4261 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 4262 vmx->vcpu.cpu = cpu;
8b9cf98c 4263 err = vmx_vcpu_setup(vmx);
fb3f0f51 4264 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4265 put_cpu();
fb3f0f51
RR		 4266 if (err)
4267 goto free_vmcs;
5e4a0b3c
MT		 4268 if (vm_need_virtualize_apic_accesses(kvm))
4269 if (alloc_apic_access_page(kvm) != 0)
4270 goto free_vmcs;
fb3f0f51 4271
b927a3ce
SY		 4272 if (enable_ept) {
4273 if (!kvm->arch.ept_identity_map_addr)
4274 kvm->arch.ept_identity_map_addr =
4275 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 4276 err = -ENOMEM;
b7ebfb05
SY		 4277 if (alloc_identity_pagetable(kvm) != 0)
4278 goto free_vmcs;
93ea5388
GN		 4279 if (!init_rmode_identity_map(kvm))
4280 goto free_vmcs;
b927a3ce 4281 }
b7ebfb05 4282
fb3f0f51
RR		 4283 return &vmx->vcpu;
4284
4285free_vmcs:
4286 free_vmcs(vmx->vmcs);
4287free_msrs:
fb3f0f51
RR		 4288 kfree(vmx->guest_msrs);
4289uninit_vcpu:
4290 kvm_vcpu_uninit(&vmx->vcpu);
4291free_vcpu:
cdbecfc3 4292 free_vpid(vmx);
a4770347 4293 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4294 return ERR_PTR(err);
6aa8b732
AK		 4295}
4296
002c7f7c
YS		 4297static void __init vmx_check_processor_compat(void *rtn)
4298{
4299 struct vmcs_config vmcs_conf;
4300
4301 *(int *)rtn = 0;
4302 if (setup_vmcs_config(&vmcs_conf) < 0)
4303 *(int *)rtn = -EIO;
4304 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4305 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4306 smp_processor_id());
4307 *(int *)rtn = -EIO;
4308 }
4309}
4310
67253af5
SY		 4311static int get_ept_level(void)
4312{
4313 return VMX_EPT_DEFAULT_GAW + 1;
4314}
4315
4b12f0de 4316static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4317{
4b12f0de
SY		 4318 u64 ret;
4319
522c68c4
SY		 4320 /* For VT-d and EPT combination
4321 * 1. MMIO: always map as UC
4322 * 2. EPT with VT-d:
4323 * a. VT-d without snooping control feature: can't guarantee the
4324 * result, try to trust guest.
4325 * b. VT-d with snooping control feature: snooping control feature of
4326 * VT-d engine can guarantee the cache correctness. Just set it
4327 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4328 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4329 * consistent with host MTRR
4330 */
4b12f0de
SY		 4331 if (is_mmio)
4332 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4333 else if (vcpu->kvm->arch.iommu_domain &&
4334 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4335 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4336 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4337 else
522c68c4 4338 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4339 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4340
4341 return ret;
64d4d521
SY		 4342}
4343
f4c9e87c
AK		 4344#define _ER(x) { EXIT_REASON_##x, #x }
4345
229456fc 4346static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4347 _ER(EXCEPTION_NMI),
4348 _ER(EXTERNAL_INTERRUPT),
4349 _ER(TRIPLE_FAULT),
4350 _ER(PENDING_INTERRUPT),
4351 _ER(NMI_WINDOW),
4352 _ER(TASK_SWITCH),
4353 _ER(CPUID),
4354 _ER(HLT),
4355 _ER(INVLPG),
4356 _ER(RDPMC),
4357 _ER(RDTSC),
4358 _ER(VMCALL),
4359 _ER(VMCLEAR),
4360 _ER(VMLAUNCH),
4361 _ER(VMPTRLD),
4362 _ER(VMPTRST),
4363 _ER(VMREAD),
4364 _ER(VMRESUME),
4365 _ER(VMWRITE),
4366 _ER(VMOFF),
4367 _ER(VMON),
4368 _ER(CR_ACCESS),
4369 _ER(DR_ACCESS),
4370 _ER(IO_INSTRUCTION),
4371 _ER(MSR_READ),
4372 _ER(MSR_WRITE),
4373 _ER(MWAIT_INSTRUCTION),
4374 _ER(MONITOR_INSTRUCTION),
4375 _ER(PAUSE_INSTRUCTION),
4376 _ER(MCE_DURING_VMENTRY),
4377 _ER(TPR_BELOW_THRESHOLD),
4378 _ER(APIC_ACCESS),
4379 _ER(EPT_VIOLATION),
4380 _ER(EPT_MISCONFIG),
4381 _ER(WBINVD),
229456fc
MT		 4382 { -1, NULL }
4383};
4384
f4c9e87c
AK		 4385#undef _ER
4386
17cc3935 4387static int vmx_get_lpage_level(void)
344f414f 4388{
878403b7
SY		 4389 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4390 return PT_DIRECTORY_LEVEL;
4391 else
4392 /* For shadow and EPT supported 1GB page */
4393 return PT_PDPE_LEVEL;
344f414f
JR		 4394}
4395
0e851880
SY		 4396static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4397{
4e47c7a6
SY		 4398 struct kvm_cpuid_entry2 *best;
4399 struct vcpu_vmx *vmx = to_vmx(vcpu);
4400 u32 exec_control;
4401
4402 vmx->rdtscp_enabled = false;
4403 if (vmx_rdtscp_supported()) {
4404 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4405 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4406 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4407 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4408 vmx->rdtscp_enabled = true;
4409 else {
4410 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4411 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4412 exec_control);
4413 }
4414 }
4415 }
0e851880
SY		 4416}
4417
d4330ef2
JR		 4418static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4419{
4420}
4421
8a76d7f2
JR		 4422static int vmx_check_intercept(struct kvm_vcpu *vcpu,
4423 struct x86_instruction_info *info,
4424 enum x86_intercept_stage stage)
4425{
4426 return X86EMUL_CONTINUE;
4427}
4428
cbdd1bea 4429static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4430 .cpu_has_kvm_support = cpu_has_kvm_support,
4431 .disabled_by_bios = vmx_disabled_by_bios,
4432 .hardware_setup = hardware_setup,
4433 .hardware_unsetup = hardware_unsetup,
002c7f7c 4434 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4435 .hardware_enable = hardware_enable,
4436 .hardware_disable = hardware_disable,
04547156 4437 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4438
4439 .vcpu_create = vmx_create_vcpu,
4440 .vcpu_free = vmx_free_vcpu,
04d2cc77 4441 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4442
04d2cc77 4443 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4444 .vcpu_load = vmx_vcpu_load,
4445 .vcpu_put = vmx_vcpu_put,
4446
4447 .set_guest_debug = set_guest_debug,
4448 .get_msr = vmx_get_msr,
4449 .set_msr = vmx_set_msr,
4450 .get_segment_base = vmx_get_segment_base,
4451 .get_segment = vmx_get_segment,
4452 .set_segment = vmx_set_segment,
2e4d2653 4453 .get_cpl = vmx_get_cpl,
6aa8b732 4454 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4455 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 4456 .decache_cr3 = vmx_decache_cr3,
25c4c276 4457 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4458 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4459 .set_cr3 = vmx_set_cr3,
4460 .set_cr4 = vmx_set_cr4,
6aa8b732 4461 .set_efer = vmx_set_efer,
6aa8b732
AK		 4462 .get_idt = vmx_get_idt,
4463 .set_idt = vmx_set_idt,
4464 .get_gdt = vmx_get_gdt,
4465 .set_gdt = vmx_set_gdt,
020df079 4466 .set_dr7 = vmx_set_dr7,
5fdbf976 4467 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4468 .get_rflags = vmx_get_rflags,
4469 .set_rflags = vmx_set_rflags,
ebcbab4c 4470 .fpu_activate = vmx_fpu_activate,
02daab21 4471 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4472
4473 .tlb_flush = vmx_flush_tlb,
6aa8b732 4474
6aa8b732 4475 .run = vmx_vcpu_run,
6062d012 4476 .handle_exit = vmx_handle_exit,
6aa8b732 4477 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4478 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4479 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4480 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4481 .set_irq = vmx_inject_irq,
95ba8273 4482 .set_nmi = vmx_inject_nmi,
298101da 4483 .queue_exception = vmx_queue_exception,
b463a6f7 4484 .cancel_injection = vmx_cancel_injection,
78646121 4485 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4486 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4487 .get_nmi_mask = vmx_get_nmi_mask,
4488 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4489 .enable_nmi_window = enable_nmi_window,
4490 .enable_irq_window = enable_irq_window,
4491 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4492
cbc94022 4493 .set_tss_addr = vmx_set_tss_addr,
67253af5 4494 .get_tdp_level = get_ept_level,
4b12f0de 4495 .get_mt_mask = vmx_get_mt_mask,
229456fc 4496
586f9607 4497 .get_exit_info = vmx_get_exit_info,
229456fc 4498 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 4499
17cc3935 4500 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4501
4502 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4503
4504 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4505
4506 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4507
4508 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 4509
4051b188 4510 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 4511 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 4512 .adjust_tsc_offset = vmx_adjust_tsc_offset,
1c97f0a0
JR		 4513
4514 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 4515
4516 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 4517};
4518
4519static int __init vmx_init(void)
4520{
26bb0981
AK		 4521 int r, i;
4522
4523 rdmsrl_safe(MSR_EFER, &host_efer);
4524
4525 for (i = 0; i < NR_VMX_MSR; ++i)
4526 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4527
3e7c73e9 4528 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4529 if (!vmx_io_bitmap_a)
4530 return -ENOMEM;
4531
3e7c73e9 4532 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4533 if (!vmx_io_bitmap_b) {
4534 r = -ENOMEM;
4535 goto out;
4536 }
4537
5897297b
AK		 4538 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4539 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4540 r = -ENOMEM;
4541 goto out1;
4542 }
4543
5897297b
AK		 4544 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4545 if (!vmx_msr_bitmap_longmode) {
4546 r = -ENOMEM;
4547 goto out2;
4548 }
4549
fdef3ad1
HQ		 4550 /*
4551 * Allow direct access to the PC debug port (it is often used for I/O
4552 * delays, but the vmexits simply slow things down).
4553 */
3e7c73e9
AK		 4554 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4555 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4556
3e7c73e9 4557 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4558
5897297b
AK		 4559 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4560 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4561
2384d2b3
SY		 4562 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4563
0ee75bea
AK		 4564 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4565 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4566 if (r)
5897297b 4567 goto out3;
25c5f225 4568
5897297b
AK		 4569 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4570 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4571 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4572 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4573 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4574 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4575
089d034e 4576 if (enable_ept) {
1439442c 4577 bypass_guest_pf = 0;
534e38b4 4578 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4579 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4580 kvm_enable_tdp();
4581 } else
4582 kvm_disable_tdp();
1439442c 4583
c7addb90
AK		 4584 if (bypass_guest_pf)
4585 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4586
fdef3ad1
HQ		 4587 return 0;
4588
5897297b
AK		 4589out3:
4590 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4591out2:
5897297b 4592 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4593out1:
3e7c73e9 4594 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4595out:
3e7c73e9 4596 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4597 return r;
6aa8b732
AK		 4598}
4599
4600static void __exit vmx_exit(void)
4601{
5897297b
AK		 4602 free_page((unsigned long)vmx_msr_bitmap_legacy);
4603 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4604 free_page((unsigned long)vmx_io_bitmap_b);
4605 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4606
cb498ea2 4607 kvm_exit();
6aa8b732
AK		 4608}
4609
4610module_init(vmx_init)
4611module_exit(vmx_exit)
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