]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/x86/kvm/vmx.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: VMX: Optimize vmx_get_rflags()
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
443381a8
AL		 72static int __read_mostly yield_on_hlt = 1;
73module_param(yield_on_hlt, bool, S_IRUGO);
74
cdc0e244
AK		 75#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77#define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 80 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 81#define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 83#define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
85 | X86_CR4_OSXMMEXCPT)
86
cdc0e244
AK		 87#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
89
78ac8b47
AK		 90#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
91
4b8d54f9
ZE		 92/*
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 96 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
102 */
00c25bce 103#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 104#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
106module_param(ple_gap, int, S_IRUGO);
107
108static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
109module_param(ple_window, int, S_IRUGO);
110
61d2ef2c
AK		 111#define NR_AUTOLOAD_MSRS 1
112
a2fa3e9f
GH		 113struct vmcs {
114 u32 revision_id;
115 u32 abort;
116 char data[0];
117};
118
26bb0981
AK		 119struct shared_msr_entry {
120 unsigned index;
121 u64 data;
d5696725 122 u64 mask;
26bb0981
AK		 123};
124
a2fa3e9f 125struct vcpu_vmx {
fb3f0f51 126 struct kvm_vcpu vcpu;
543e4243 127 struct list_head local_vcpus_link;
313dbd49 128 unsigned long host_rsp;
a2fa3e9f 129 int launched;
29bd8a78 130 u8 fail;
51aa01d1 131 u32 exit_intr_info;
1155f76a 132 u32 idt_vectoring_info;
6de12732 133 ulong rflags;
26bb0981 134 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 135 int nmsrs;
136 int save_nmsrs;
a2fa3e9f 137#ifdef CONFIG_X86_64
44ea2b17
AK		 138 u64 msr_host_kernel_gs_base;
139 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 140#endif
141 struct vmcs *vmcs;
61d2ef2c
AK		 142 struct msr_autoload {
143 unsigned nr;
144 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
145 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
146 } msr_autoload;
a2fa3e9f
GH		 147 struct {
148 int loaded;
149 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 150 int gs_ldt_reload_needed;
151 int fs_reload_needed;
d77c26fc 152 } host_state;
9c8cba37 153 struct {
7ffd92c5 154 int vm86_active;
78ac8b47 155 ulong save_rflags;
7ffd92c5
AK		 156 struct kvm_save_segment {
157 u16 selector;
158 unsigned long base;
159 u32 limit;
160 u32 ar;
161 } tr, es, ds, fs, gs;
9c8cba37 162 } rmode;
2384d2b3 163 int vpid;
04fa4d32 164 bool emulation_required;
3b86cd99
JK		 165
166 /* Support for vnmi-less CPUs */
167 int soft_vnmi_blocked;
168 ktime_t entry_time;
169 s64 vnmi_blocked_time;
a0861c02 170 u32 exit_reason;
4e47c7a6
SY		 171
172 bool rdtscp_enabled;
a2fa3e9f
GH		 173};
174
175static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
176{
fb3f0f51 177 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 178}
179
4e1096d2 180static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 181static void kvm_cpu_vmxon(u64 addr);
182static void kvm_cpu_vmxoff(void);
aff48baa 183static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 184static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 185
6aa8b732
AK		 186static DEFINE_PER_CPU(struct vmcs *, vmxarea);
187static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 188static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
3444d7da 189static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 190
3e7c73e9
AK		 191static unsigned long *vmx_io_bitmap_a;
192static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 193static unsigned long *vmx_msr_bitmap_legacy;
194static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 195
110312c8
AK		 196static bool cpu_has_load_ia32_efer;
197
2384d2b3
SY		 198static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
199static DEFINE_SPINLOCK(vmx_vpid_lock);
200
1c3d14fe 201static struct vmcs_config {
6aa8b732
AK		 202 int size;
203 int order;
204 u32 revision_id;
1c3d14fe
YS		 205 u32 pin_based_exec_ctrl;
206 u32 cpu_based_exec_ctrl;
f78e0e2e 207 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 208 u32 vmexit_ctrl;
209 u32 vmentry_ctrl;
210} vmcs_config;
6aa8b732 211
efff9e53 212static struct vmx_capability {
d56f546d
SY		 213 u32 ept;
214 u32 vpid;
215} vmx_capability;
216
6aa8b732
AK		 217#define VMX_SEGMENT_FIELD(seg) \
218 [VCPU_SREG_##seg] = { \
219 .selector = GUEST_##seg##_SELECTOR, \
220 .base = GUEST_##seg##_BASE, \
221 .limit = GUEST_##seg##_LIMIT, \
222 .ar_bytes = GUEST_##seg##_AR_BYTES, \
223 }
224
225static struct kvm_vmx_segment_field {
226 unsigned selector;
227 unsigned base;
228 unsigned limit;
229 unsigned ar_bytes;
230} kvm_vmx_segment_fields[] = {
231 VMX_SEGMENT_FIELD(CS),
232 VMX_SEGMENT_FIELD(DS),
233 VMX_SEGMENT_FIELD(ES),
234 VMX_SEGMENT_FIELD(FS),
235 VMX_SEGMENT_FIELD(GS),
236 VMX_SEGMENT_FIELD(SS),
237 VMX_SEGMENT_FIELD(TR),
238 VMX_SEGMENT_FIELD(LDTR),
239};
240
26bb0981
AK		 241static u64 host_efer;
242
6de4f3ad
AK		 243static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
244
4d56c8a7 245/*
8c06585d 246 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 247 * away by decrementing the array size.
248 */
6aa8b732 249static const u32 vmx_msr_index[] = {
05b3e0c2 250#ifdef CONFIG_X86_64
44ea2b17 251 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 252#endif
8c06585d 253 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 254};
9d8f549d 255#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 256
31299944 257static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 258{
259 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
260 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 261 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 262}
263
31299944 264static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 265{
266 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
267 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 268 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 269}
270
31299944 271static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 272{
273 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
274 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 275 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 276}
277
31299944 278static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 279{
280 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
281 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
282}
283
31299944 284static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 285{
286 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
287 INTR_INFO_VALID_MASK)) ==
288 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
289}
290
31299944 291static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 292{
04547156 293 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 294}
295
31299944 296static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 297{
04547156 298 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 299}
300
31299944 301static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 302{
04547156 303 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 304}
305
31299944 306static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 307{
04547156
SY		 308 return vmcs_config.cpu_based_exec_ctrl &
309 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 310}
311
774ead3a 312static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 313{
04547156
SY		 314 return vmcs_config.cpu_based_2nd_exec_ctrl &
315 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
316}
317
318static inline bool cpu_has_vmx_flexpriority(void)
319{
320 return cpu_has_vmx_tpr_shadow() &&
321 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 322}
323
e799794e
MT		 324static inline bool cpu_has_vmx_ept_execute_only(void)
325{
31299944 326 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 327}
328
329static inline bool cpu_has_vmx_eptp_uncacheable(void)
330{
31299944 331 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 332}
333
334static inline bool cpu_has_vmx_eptp_writeback(void)
335{
31299944 336 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 337}
338
339static inline bool cpu_has_vmx_ept_2m_page(void)
340{
31299944 341 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 342}
343
878403b7
SY		 344static inline bool cpu_has_vmx_ept_1g_page(void)
345{
31299944 346 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 347}
348
4bc9b982
SY		 349static inline bool cpu_has_vmx_ept_4levels(void)
350{
351 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
352}
353
31299944 354static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 355{
31299944 356 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 357}
358
31299944 359static inline bool cpu_has_vmx_invept_context(void)
d56f546d 360{
31299944 361 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 362}
363
31299944 364static inline bool cpu_has_vmx_invept_global(void)
d56f546d 365{
31299944 366 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 367}
368
518c8aee
GJ		 369static inline bool cpu_has_vmx_invvpid_single(void)
370{
371 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
372}
373
b9d762fa
GJ		 374static inline bool cpu_has_vmx_invvpid_global(void)
375{
376 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
377}
378
31299944 379static inline bool cpu_has_vmx_ept(void)
d56f546d 380{
04547156
SY		 381 return vmcs_config.cpu_based_2nd_exec_ctrl &
382 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 383}
384
31299944 385static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 386{
387 return vmcs_config.cpu_based_2nd_exec_ctrl &
388 SECONDARY_EXEC_UNRESTRICTED_GUEST;
389}
390
31299944 391static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 392{
393 return vmcs_config.cpu_based_2nd_exec_ctrl &
394 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
395}
396
31299944 397static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 398{
6d3e435e 399 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 400}
401
31299944 402static inline bool cpu_has_vmx_vpid(void)
2384d2b3 403{
04547156
SY		 404 return vmcs_config.cpu_based_2nd_exec_ctrl &
405 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 406}
407
31299944 408static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 409{
410 return vmcs_config.cpu_based_2nd_exec_ctrl &
411 SECONDARY_EXEC_RDTSCP;
412}
413
31299944 414static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 415{
416 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
417}
418
f5f48ee1
SY		 419static inline bool cpu_has_vmx_wbinvd_exit(void)
420{
421 return vmcs_config.cpu_based_2nd_exec_ctrl &
422 SECONDARY_EXEC_WBINVD_EXITING;
423}
424
04547156
SY		 425static inline bool report_flexpriority(void)
426{
427 return flexpriority_enabled;
428}
429
8b9cf98c 430static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 431{
432 int i;
433
a2fa3e9f 434 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 435 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 436 return i;
437 return -1;
438}
439
2384d2b3
SY		 440static inline void __invvpid(int ext, u16 vpid, gva_t gva)
441{
442 struct {
443 u64 vpid : 16;
444 u64 rsvd : 48;
445 u64 gva;
446 } operand = { vpid, 0, gva };
447
4ecac3fd 448 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 449 /* CF==1 or ZF==1 --> rc = -1 */
450 "; ja 1f ; ud2 ; 1:"
451 : : "a"(&operand), "c"(ext) : "cc", "memory");
452}
453
1439442c
SY		 454static inline void __invept(int ext, u64 eptp, gpa_t gpa)
455{
456 struct {
457 u64 eptp, gpa;
458 } operand = {eptp, gpa};
459
4ecac3fd 460 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 461 /* CF==1 or ZF==1 --> rc = -1 */
462 "; ja 1f ; ud2 ; 1:\n"
463 : : "a" (&operand), "c" (ext) : "cc", "memory");
464}
465
26bb0981 466static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 467{
468 int i;
469
8b9cf98c 470 i = __find_msr_index(vmx, msr);
a75beee6 471 if (i >= 0)
a2fa3e9f 472 return &vmx->guest_msrs[i];
8b6d44c7 473 return NULL;
7725f0ba
AK		 474}
475
6aa8b732
AK		 476static void vmcs_clear(struct vmcs *vmcs)
477{
478 u64 phys_addr = __pa(vmcs);
479 u8 error;
480
4ecac3fd 481 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 482 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 483 : "cc", "memory");
484 if (error)
485 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
486 vmcs, phys_addr);
487}
488
7725b894
DX		 489static void vmcs_load(struct vmcs *vmcs)
490{
491 u64 phys_addr = __pa(vmcs);
492 u8 error;
493
494 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 495 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 496 : "cc", "memory");
497 if (error)
498 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
499 vmcs, phys_addr);
500}
501
6aa8b732
AK		 502static void __vcpu_clear(void *arg)
503{
8b9cf98c 504 struct vcpu_vmx *vmx = arg;
d3b2c338 505 int cpu = raw_smp_processor_id();
6aa8b732 506
8b9cf98c 507 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 508 vmcs_clear(vmx->vmcs);
509 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 510 per_cpu(current_vmcs, cpu) = NULL;
543e4243
AK		 511 list_del(&vmx->local_vcpus_link);
512 vmx->vcpu.cpu = -1;
513 vmx->launched = 0;
6aa8b732
AK		 514}
515
8b9cf98c 516static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 517{
eae5ecb5
AK		 518 if (vmx->vcpu.cpu == -1)
519 return;
8691e5a8 520 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 521}
522
1760dd49 523static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 524{
525 if (vmx->vpid == 0)
526 return;
527
518c8aee
GJ		 528 if (cpu_has_vmx_invvpid_single())
529 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 530}
531
b9d762fa
GJ		 532static inline void vpid_sync_vcpu_global(void)
533{
534 if (cpu_has_vmx_invvpid_global())
535 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
536}
537
538static inline void vpid_sync_context(struct vcpu_vmx *vmx)
539{
540 if (cpu_has_vmx_invvpid_single())
1760dd49 541 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 542 else
543 vpid_sync_vcpu_global();
544}
545
1439442c
SY		 546static inline void ept_sync_global(void)
547{
548 if (cpu_has_vmx_invept_global())
549 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
550}
551
552static inline void ept_sync_context(u64 eptp)
553{
089d034e 554 if (enable_ept) {
1439442c
SY		 555 if (cpu_has_vmx_invept_context())
556 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
557 else
558 ept_sync_global();
559 }
560}
561
562static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
563{
089d034e 564 if (enable_ept) {
1439442c
SY		 565 if (cpu_has_vmx_invept_individual_addr())
566 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
567 eptp, gpa);
568 else
569 ept_sync_context(eptp);
570 }
571}
572
6aa8b732
AK		 573static unsigned long vmcs_readl(unsigned long field)
574{
a295673a 575 unsigned long value = 0;
6aa8b732 576
4ecac3fd 577 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
a295673a 578 : "+a"(value) : "d"(field) : "cc");
6aa8b732
AK		 579 return value;
580}
581
582static u16 vmcs_read16(unsigned long field)
583{
584 return vmcs_readl(field);
585}
586
587static u32 vmcs_read32(unsigned long field)
588{
589 return vmcs_readl(field);
590}
591
592static u64 vmcs_read64(unsigned long field)
593{
05b3e0c2 594#ifdef CONFIG_X86_64
6aa8b732
AK		 595 return vmcs_readl(field);
596#else
597 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
598#endif
599}
600
e52de1b8
AK		 601static noinline void vmwrite_error(unsigned long field, unsigned long value)
602{
603 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
604 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
605 dump_stack();
606}
607
6aa8b732
AK		 608static void vmcs_writel(unsigned long field, unsigned long value)
609{
610 u8 error;
611
4ecac3fd 612 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 613 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 614 if (unlikely(error))
615 vmwrite_error(field, value);
6aa8b732
AK		 616}
617
618static void vmcs_write16(unsigned long field, u16 value)
619{
620 vmcs_writel(field, value);
621}
622
623static void vmcs_write32(unsigned long field, u32 value)
624{
625 vmcs_writel(field, value);
626}
627
628static void vmcs_write64(unsigned long field, u64 value)
629{
6aa8b732 630 vmcs_writel(field, value);
7682f2d0 631#ifndef CONFIG_X86_64
6aa8b732
AK		 632 asm volatile ("");
633 vmcs_writel(field+1, value >> 32);
634#endif
635}
636
2ab455cc
AL		 637static void vmcs_clear_bits(unsigned long field, u32 mask)
638{
639 vmcs_writel(field, vmcs_readl(field) & ~mask);
640}
641
642static void vmcs_set_bits(unsigned long field, u32 mask)
643{
644 vmcs_writel(field, vmcs_readl(field) | mask);
645}
646
abd3f2d6
AK		 647static void update_exception_bitmap(struct kvm_vcpu *vcpu)
648{
649 u32 eb;
650
fd7373cc
JK		 651 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
652 (1u << NM_VECTOR) | (1u << DB_VECTOR);
653 if ((vcpu->guest_debug &
654 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
655 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
656 eb |= 1u << BP_VECTOR;
7ffd92c5 657 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 658 eb = ~0;
089d034e 659 if (enable_ept)
1439442c 660 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 661 if (vcpu->fpu_active)
662 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 663 vmcs_write32(EXCEPTION_BITMAP, eb);
664}
665
61d2ef2c
AK		 666static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
667{
668 unsigned i;
669 struct msr_autoload *m = &vmx->msr_autoload;
670
110312c8
AK		 671 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
672 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
673 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
674 return;
675 }
676
61d2ef2c
AK		 677 for (i = 0; i < m->nr; ++i)
678 if (m->guest[i].index == msr)
679 break;
680
681 if (i == m->nr)
682 return;
683 --m->nr;
684 m->guest[i] = m->guest[m->nr];
685 m->host[i] = m->host[m->nr];
686 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
687 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
688}
689
690static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
691 u64 guest_val, u64 host_val)
692{
693 unsigned i;
694 struct msr_autoload *m = &vmx->msr_autoload;
695
110312c8
AK		 696 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
697 vmcs_write64(GUEST_IA32_EFER, guest_val);
698 vmcs_write64(HOST_IA32_EFER, host_val);
699 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
700 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
701 return;
702 }
703
61d2ef2c
AK		 704 for (i = 0; i < m->nr; ++i)
705 if (m->guest[i].index == msr)
706 break;
707
708 if (i == m->nr) {
709 ++m->nr;
710 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
711 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
712 }
713
714 m->guest[i].index = msr;
715 m->guest[i].value = guest_val;
716 m->host[i].index = msr;
717 m->host[i].value = host_val;
718}
719
33ed6329
AK		 720static void reload_tss(void)
721{
33ed6329
AK		 722 /*
723 * VT restores TR but not its size. Useless.
724 */
d359192f 725 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 726 struct desc_struct *descs;
33ed6329 727
d359192f 728 descs = (void *)gdt->address;
33ed6329
AK		 729 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
730 load_TR_desc();
33ed6329
AK		 731}
732
92c0d900 733static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 734{
3a34a881 735 u64 guest_efer;
51c6cf66
AK		 736 u64 ignore_bits;
737
f6801dff 738 guest_efer = vmx->vcpu.arch.efer;
3a34a881 739
51c6cf66
AK		 740 /*
741 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
742 * outside long mode
743 */
744 ignore_bits = EFER_NX | EFER_SCE;
745#ifdef CONFIG_X86_64
746 ignore_bits |= EFER_LMA | EFER_LME;
747 /* SCE is meaningful only in long mode on Intel */
748 if (guest_efer & EFER_LMA)
749 ignore_bits &= ~(u64)EFER_SCE;
750#endif
51c6cf66
AK		 751 guest_efer &= ~ignore_bits;
752 guest_efer |= host_efer & ignore_bits;
26bb0981 753 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 754 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 755
756 clear_atomic_switch_msr(vmx, MSR_EFER);
757 /* On ept, can't emulate nx, and must switch nx atomically */
758 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
759 guest_efer = vmx->vcpu.arch.efer;
760 if (!(guest_efer & EFER_LMA))
761 guest_efer &= ~EFER_LME;
762 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
763 return false;
764 }
765
26bb0981 766 return true;
51c6cf66
AK		 767}
768
2d49ec72
GN		 769static unsigned long segment_base(u16 selector)
770{
d359192f 771 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 772 struct desc_struct *d;
773 unsigned long table_base;
774 unsigned long v;
775
776 if (!(selector & ~3))
777 return 0;
778
d359192f 779 table_base = gdt->address;
2d49ec72
GN		 780
781 if (selector & 4) { /* from ldt */
782 u16 ldt_selector = kvm_read_ldt();
783
784 if (!(ldt_selector & ~3))
785 return 0;
786
787 table_base = segment_base(ldt_selector);
788 }
789 d = (struct desc_struct *)(table_base + (selector & ~7));
790 v = get_desc_base(d);
791#ifdef CONFIG_X86_64
792 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
793 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
794#endif
795 return v;
796}
797
798static inline unsigned long kvm_read_tr_base(void)
799{
800 u16 tr;
801 asm("str %0" : "=g"(tr));
802 return segment_base(tr);
803}
804
04d2cc77 805static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 806{
04d2cc77 807 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 808 int i;
04d2cc77 809
a2fa3e9f 810 if (vmx->host_state.loaded)
33ed6329
AK		 811 return;
812
a2fa3e9f 813 vmx->host_state.loaded = 1;
33ed6329
AK		 814 /*
815 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
816 * allow segment selectors with cpl > 0 or ti == 1.
817 */
d6e88aec 818 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 819 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 820 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 821 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 822 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 823 vmx->host_state.fs_reload_needed = 0;
824 } else {
33ed6329 825 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 826 vmx->host_state.fs_reload_needed = 1;
33ed6329 827 }
9581d442 828 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 829 if (!(vmx->host_state.gs_sel & 7))
830 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 831 else {
832 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 833 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 834 }
835
836#ifdef CONFIG_X86_64
837 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
838 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
839#else
a2fa3e9f
GH		 840 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
841 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 842#endif
707c0874
AK		 843
844#ifdef CONFIG_X86_64
c8770e7b
AK		 845 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
846 if (is_long_mode(&vmx->vcpu))
44ea2b17 847 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 848#endif
26bb0981
AK		 849 for (i = 0; i < vmx->save_nmsrs; ++i)
850 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 851 vmx->guest_msrs[i].data,
852 vmx->guest_msrs[i].mask);
33ed6329
AK		 853}
854
a9b21b62 855static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 856{
a2fa3e9f 857 if (!vmx->host_state.loaded)
33ed6329
AK		 858 return;
859
e1beb1d3 860 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 861 vmx->host_state.loaded = 0;
c8770e7b
AK		 862#ifdef CONFIG_X86_64
863 if (is_long_mode(&vmx->vcpu))
864 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
865#endif
152d3f2f 866 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 867 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 868#ifdef CONFIG_X86_64
9581d442 869 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 870#else
871 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 872#endif
33ed6329 873 }
0a77fe4c
AK		 874 if (vmx->host_state.fs_reload_needed)
875 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 876 reload_tss();
44ea2b17 877#ifdef CONFIG_X86_64
c8770e7b 878 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 879#endif
1c11e713
AK		 880 if (current_thread_info()->status & TS_USEDFPU)
881 clts();
3444d7da 882 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 883}
884
a9b21b62
AK		 885static void vmx_load_host_state(struct vcpu_vmx *vmx)
886{
887 preempt_disable();
888 __vmx_load_host_state(vmx);
889 preempt_enable();
890}
891
6aa8b732
AK		 892/*
893 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
894 * vcpu mutex is already taken.
895 */
15ad7146 896static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 897{
a2fa3e9f 898 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 899 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 900
4610c9cc
DX		 901 if (!vmm_exclusive)
902 kvm_cpu_vmxon(phys_addr);
903 else if (vcpu->cpu != cpu)
8b9cf98c 904 vcpu_clear(vmx);
6aa8b732 905
a2fa3e9f 906 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 907 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 908 vmcs_load(vmx->vmcs);
6aa8b732
AK		 909 }
910
911 if (vcpu->cpu != cpu) {
d359192f 912 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 913 unsigned long sysenter_esp;
914
a8eeb04a 915 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be
DX		 916 local_irq_disable();
917 list_add(&vmx->local_vcpus_link,
918 &per_cpu(vcpus_on_cpu, cpu));
919 local_irq_enable();
920
6aa8b732
AK		 921 /*
922 * Linux uses per-cpu TSS and GDT, so set these when switching
923 * processors.
924 */
d6e88aec 925 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 926 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 927
928 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
929 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
930 }
6aa8b732
AK		 931}
932
933static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
934{
a9b21b62 935 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 936 if (!vmm_exclusive) {
b923e62e 937 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 938 kvm_cpu_vmxoff();
939 }
6aa8b732
AK		 940}
941
5fd86fcf
AK		 942static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
943{
81231c69
AK		 944 ulong cr0;
945
5fd86fcf
AK		 946 if (vcpu->fpu_active)
947 return;
948 vcpu->fpu_active = 1;
81231c69
AK		 949 cr0 = vmcs_readl(GUEST_CR0);
950 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
951 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
952 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 953 update_exception_bitmap(vcpu);
edcafe3c
AK		 954 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
955 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 956}
957
edcafe3c
AK		 958static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
959
5fd86fcf
AK		 960static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
961{
edcafe3c 962 vmx_decache_cr0_guest_bits(vcpu);
81231c69 963 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 964 update_exception_bitmap(vcpu);
edcafe3c
AK		 965 vcpu->arch.cr0_guest_owned_bits = 0;
966 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
967 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 968}
969
6aa8b732
AK		 970static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
971{
78ac8b47 972 unsigned long rflags, save_rflags;
345dcaa8 973
6de12732
AK		 974 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
975 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
976 rflags = vmcs_readl(GUEST_RFLAGS);
977 if (to_vmx(vcpu)->rmode.vm86_active) {
978 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
979 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
980 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
981 }
982 to_vmx(vcpu)->rflags = rflags;
78ac8b47 983 }
6de12732 984 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 985}
986
987static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
988{
6de12732
AK		 989 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
990 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 991 if (to_vmx(vcpu)->rmode.vm86_active) {
992 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 993 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 994 }
6aa8b732
AK		 995 vmcs_writel(GUEST_RFLAGS, rflags);
996}
997
2809f5d2
GC		 998static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
999{
1000 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1001 int ret = 0;
1002
1003 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1004 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1005 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1006 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1007
1008 return ret & mask;
1009}
1010
1011static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1012{
1013 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1014 u32 interruptibility = interruptibility_old;
1015
1016 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1017
48005f64 1018 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1019 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1020 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1021 interruptibility |= GUEST_INTR_STATE_STI;
1022
1023 if ((interruptibility != interruptibility_old))
1024 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1025}
1026
6aa8b732
AK		 1027static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1028{
1029 unsigned long rip;
6aa8b732 1030
5fdbf976 1031 rip = kvm_rip_read(vcpu);
6aa8b732 1032 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1033 kvm_rip_write(vcpu, rip);
6aa8b732 1034
2809f5d2
GC		 1035 /* skipping an emulated instruction also counts */
1036 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1037}
1038
443381a8
AL		 1039static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1040{
1041 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1042 * explicitly skip the instruction because if the HLT state is set, then
1043 * the instruction is already executing and RIP has already been
1044 * advanced. */
1045 if (!yield_on_hlt &&
1046 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1047 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1048}
1049
298101da 1050static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1051 bool has_error_code, u32 error_code,
1052 bool reinject)
298101da 1053{
77ab6db0 1054 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1055 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1056
8ab2d2e2 1057 if (has_error_code) {
77ab6db0 1058 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1059 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1060 }
77ab6db0 1061
7ffd92c5 1062 if (vmx->rmode.vm86_active) {
a92601bb
MG		 1063 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1064 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1065 return;
1066 }
1067
66fd3f7f
GN		 1068 if (kvm_exception_is_soft(nr)) {
1069 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1070 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1071 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1072 } else
1073 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1074
1075 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1076 vmx_clear_hlt(vcpu);
298101da
AK		 1077}
1078
4e47c7a6
SY		 1079static bool vmx_rdtscp_supported(void)
1080{
1081 return cpu_has_vmx_rdtscp();
1082}
1083
a75beee6
ED		 1084/*
1085 * Swap MSR entry in host/guest MSR entry array.
1086 */
8b9cf98c 1087static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1088{
26bb0981 1089 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1090
1091 tmp = vmx->guest_msrs[to];
1092 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1093 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1094}
1095
e38aea3e
AK		 1096/*
1097 * Set up the vmcs to automatically save and restore system
1098 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1099 * mode, as fiddling with msrs is very expensive.
1100 */
8b9cf98c 1101static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1102{
26bb0981 1103 int save_nmsrs, index;
5897297b 1104 unsigned long *msr_bitmap;
e38aea3e 1105
33f9c505 1106 vmx_load_host_state(vmx);
a75beee6
ED		 1107 save_nmsrs = 0;
1108#ifdef CONFIG_X86_64
8b9cf98c 1109 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1110 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1111 if (index >= 0)
8b9cf98c
RR		 1112 move_msr_up(vmx, index, save_nmsrs++);
1113 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1114 if (index >= 0)
8b9cf98c
RR		 1115 move_msr_up(vmx, index, save_nmsrs++);
1116 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1117 if (index >= 0)
8b9cf98c 1118 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1119 index = __find_msr_index(vmx, MSR_TSC_AUX);
1120 if (index >= 0 && vmx->rdtscp_enabled)
1121 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1122 /*
8c06585d 1123 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1124 * if efer.sce is enabled.
1125 */
8c06585d 1126 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1127 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1128 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1129 }
1130#endif
92c0d900
AK		 1131 index = __find_msr_index(vmx, MSR_EFER);
1132 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1133 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1134
26bb0981 1135 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1136
1137 if (cpu_has_vmx_msr_bitmap()) {
1138 if (is_long_mode(&vmx->vcpu))
1139 msr_bitmap = vmx_msr_bitmap_longmode;
1140 else
1141 msr_bitmap = vmx_msr_bitmap_legacy;
1142
1143 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1144 }
e38aea3e
AK		 1145}
1146
6aa8b732
AK		 1147/*
1148 * reads and returns guest's timestamp counter "register"
1149 * guest_tsc = host_tsc + tsc_offset -- 21.3
1150 */
1151static u64 guest_read_tsc(void)
1152{
1153 u64 host_tsc, tsc_offset;
1154
1155 rdtscll(host_tsc);
1156 tsc_offset = vmcs_read64(TSC_OFFSET);
1157 return host_tsc + tsc_offset;
1158}
1159
1160/*
99e3e30a 1161 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1162 */
99e3e30a 1163static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1164{
f4e1b3c8 1165 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1166}
1167
e48672fa
ZA		 1168static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1169{
1170 u64 offset = vmcs_read64(TSC_OFFSET);
1171 vmcs_write64(TSC_OFFSET, offset + adjustment);
1172}
1173
6aa8b732
AK		 1174/*
1175 * Reads an msr value (of 'msr_index') into 'pdata'.
1176 * Returns 0 on success, non-0 otherwise.
1177 * Assumes vcpu_load() was already called.
1178 */
1179static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1180{
1181 u64 data;
26bb0981 1182 struct shared_msr_entry *msr;
6aa8b732
AK		 1183
1184 if (!pdata) {
1185 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1186 return -EINVAL;
1187 }
1188
1189 switch (msr_index) {
05b3e0c2 1190#ifdef CONFIG_X86_64
6aa8b732
AK		 1191 case MSR_FS_BASE:
1192 data = vmcs_readl(GUEST_FS_BASE);
1193 break;
1194 case MSR_GS_BASE:
1195 data = vmcs_readl(GUEST_GS_BASE);
1196 break;
44ea2b17
AK		 1197 case MSR_KERNEL_GS_BASE:
1198 vmx_load_host_state(to_vmx(vcpu));
1199 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1200 break;
26bb0981 1201#endif
6aa8b732 1202 case MSR_EFER:
3bab1f5d 1203 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1204 case MSR_IA32_TSC:
6aa8b732
AK		 1205 data = guest_read_tsc();
1206 break;
1207 case MSR_IA32_SYSENTER_CS:
1208 data = vmcs_read32(GUEST_SYSENTER_CS);
1209 break;
1210 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1211 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1212 break;
1213 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1214 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1215 break;
4e47c7a6
SY		 1216 case MSR_TSC_AUX:
1217 if (!to_vmx(vcpu)->rdtscp_enabled)
1218 return 1;
1219 /* Otherwise falls through */
6aa8b732 1220 default:
26bb0981 1221 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1222 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1223 if (msr) {
542423b0 1224 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1225 data = msr->data;
1226 break;
6aa8b732 1227 }
3bab1f5d 1228 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1229 }
1230
1231 *pdata = data;
1232 return 0;
1233}
1234
1235/*
1236 * Writes msr value into into the appropriate "register".
1237 * Returns 0 on success, non-0 otherwise.
1238 * Assumes vcpu_load() was already called.
1239 */
1240static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1241{
a2fa3e9f 1242 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1243 struct shared_msr_entry *msr;
2cc51560
ED		 1244 int ret = 0;
1245
6aa8b732 1246 switch (msr_index) {
3bab1f5d 1247 case MSR_EFER:
a9b21b62 1248 vmx_load_host_state(vmx);
2cc51560 1249 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1250 break;
16175a79 1251#ifdef CONFIG_X86_64
6aa8b732
AK		 1252 case MSR_FS_BASE:
1253 vmcs_writel(GUEST_FS_BASE, data);
1254 break;
1255 case MSR_GS_BASE:
1256 vmcs_writel(GUEST_GS_BASE, data);
1257 break;
44ea2b17
AK		 1258 case MSR_KERNEL_GS_BASE:
1259 vmx_load_host_state(vmx);
1260 vmx->msr_guest_kernel_gs_base = data;
1261 break;
6aa8b732
AK		 1262#endif
1263 case MSR_IA32_SYSENTER_CS:
1264 vmcs_write32(GUEST_SYSENTER_CS, data);
1265 break;
1266 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1267 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1268 break;
1269 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1270 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1271 break;
af24a4e4 1272 case MSR_IA32_TSC:
99e3e30a 1273 kvm_write_tsc(vcpu, data);
6aa8b732 1274 break;
468d472f
SY		 1275 case MSR_IA32_CR_PAT:
1276 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1277 vmcs_write64(GUEST_IA32_PAT, data);
1278 vcpu->arch.pat = data;
1279 break;
1280 }
4e47c7a6
SY		 1281 ret = kvm_set_msr_common(vcpu, msr_index, data);
1282 break;
1283 case MSR_TSC_AUX:
1284 if (!vmx->rdtscp_enabled)
1285 return 1;
1286 /* Check reserved bit, higher 32 bits should be zero */
1287 if ((data >> 32) != 0)
1288 return 1;
1289 /* Otherwise falls through */
6aa8b732 1290 default:
8b9cf98c 1291 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1292 if (msr) {
542423b0 1293 vmx_load_host_state(vmx);
3bab1f5d
AK		 1294 msr->data = data;
1295 break;
6aa8b732 1296 }
2cc51560 1297 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1298 }
1299
2cc51560 1300 return ret;
6aa8b732
AK		 1301}
1302
5fdbf976 1303static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1304{
5fdbf976
MT		 1305 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1306 switch (reg) {
1307 case VCPU_REGS_RSP:
1308 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1309 break;
1310 case VCPU_REGS_RIP:
1311 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1312 break;
6de4f3ad
AK		 1313 case VCPU_EXREG_PDPTR:
1314 if (enable_ept)
1315 ept_save_pdptrs(vcpu);
1316 break;
5fdbf976
MT		 1317 default:
1318 break;
1319 }
6aa8b732
AK		 1320}
1321
355be0b9 1322static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1323{
ae675ef0
JK		 1324 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1325 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1326 else
1327 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1328
abd3f2d6 1329 update_exception_bitmap(vcpu);
6aa8b732
AK		 1330}
1331
1332static __init int cpu_has_kvm_support(void)
1333{
6210e37b 1334 return cpu_has_vmx();
6aa8b732
AK		 1335}
1336
1337static __init int vmx_disabled_by_bios(void)
1338{
1339 u64 msr;
1340
1341 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 1342 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 1343 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 1344 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1345 && tboot_enabled())
1346 return 1;
23f3e991 1347 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 1348 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 1349 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 1350 && !tboot_enabled()) {
1351 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 1352 "activate TXT before enabling KVM\n");
cafd6659 1353 return 1;
f9335afe 1354 }
23f3e991
JC		 1355 /* launched w/o TXT and VMX disabled */
1356 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1357 && !tboot_enabled())
1358 return 1;
cafd6659
SW		 1359 }
1360
1361 return 0;
6aa8b732
AK		 1362}
1363
7725b894
DX		 1364static void kvm_cpu_vmxon(u64 addr)
1365{
1366 asm volatile (ASM_VMX_VMXON_RAX
1367 : : "a"(&addr), "m"(addr)
1368 : "memory", "cc");
1369}
1370
10474ae8 1371static int hardware_enable(void *garbage)
6aa8b732
AK		 1372{
1373 int cpu = raw_smp_processor_id();
1374 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1375 u64 old, test_bits;
6aa8b732 1376
10474ae8
AG		 1377 if (read_cr4() & X86_CR4_VMXE)
1378 return -EBUSY;
1379
543e4243 1380 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1381 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1382
1383 test_bits = FEATURE_CONTROL_LOCKED;
1384 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1385 if (tboot_enabled())
1386 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1387
1388 if ((old & test_bits) != test_bits) {
6aa8b732 1389 /* enable and lock */
cafd6659
SW		 1390 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1391 }
66aee91a 1392 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1393
4610c9cc
DX		 1394 if (vmm_exclusive) {
1395 kvm_cpu_vmxon(phys_addr);
1396 ept_sync_global();
1397 }
10474ae8 1398
3444d7da
AK		 1399 store_gdt(&__get_cpu_var(host_gdt));
1400
10474ae8 1401 return 0;
6aa8b732
AK		 1402}
1403
543e4243
AK		 1404static void vmclear_local_vcpus(void)
1405{
1406 int cpu = raw_smp_processor_id();
1407 struct vcpu_vmx *vmx, *n;
1408
1409 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1410 local_vcpus_link)
1411 __vcpu_clear(vmx);
1412}
1413
710ff4a8
EH		 1414
1415/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1416 * tricks.
1417 */
1418static void kvm_cpu_vmxoff(void)
6aa8b732 1419{
4ecac3fd 1420 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1421}
1422
710ff4a8
EH		 1423static void hardware_disable(void *garbage)
1424{
4610c9cc
DX		 1425 if (vmm_exclusive) {
1426 vmclear_local_vcpus();
1427 kvm_cpu_vmxoff();
1428 }
7725b894 1429 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1430}
1431
1c3d14fe 1432static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1433 u32 msr, u32 *result)
1c3d14fe
YS		 1434{
1435 u32 vmx_msr_low, vmx_msr_high;
1436 u32 ctl = ctl_min | ctl_opt;
1437
1438 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1439
1440 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1441 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1442
1443 /* Ensure minimum (required) set of control bits are supported. */
1444 if (ctl_min & ~ctl)
002c7f7c 1445 return -EIO;
1c3d14fe
YS		 1446
1447 *result = ctl;
1448 return 0;
1449}
1450
110312c8
AK		 1451static __init bool allow_1_setting(u32 msr, u32 ctl)
1452{
1453 u32 vmx_msr_low, vmx_msr_high;
1454
1455 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1456 return vmx_msr_high & ctl;
1457}
1458
002c7f7c 1459static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1460{
1461 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1462 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1463 u32 _pin_based_exec_control = 0;
1464 u32 _cpu_based_exec_control = 0;
f78e0e2e 1465 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1466 u32 _vmexit_control = 0;
1467 u32 _vmentry_control = 0;
1468
1469 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1470 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1471 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1472 &_pin_based_exec_control) < 0)
002c7f7c 1473 return -EIO;
1c3d14fe 1474
443381a8 1475 min =
1c3d14fe
YS		 1476#ifdef CONFIG_X86_64
1477 CPU_BASED_CR8_LOAD_EXITING |
1478 CPU_BASED_CR8_STORE_EXITING |
1479#endif
d56f546d
SY		 1480 CPU_BASED_CR3_LOAD_EXITING |
1481 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1482 CPU_BASED_USE_IO_BITMAPS |
1483 CPU_BASED_MOV_DR_EXITING |
a7052897 1484 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1485 CPU_BASED_MWAIT_EXITING |
1486 CPU_BASED_MONITOR_EXITING |
a7052897 1487 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 1488
1489 if (yield_on_hlt)
1490 min |= CPU_BASED_HLT_EXITING;
1491
f78e0e2e 1492 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1493 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1494 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1495 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1496 &_cpu_based_exec_control) < 0)
002c7f7c 1497 return -EIO;
6e5d865c
YS		 1498#ifdef CONFIG_X86_64
1499 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1500 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1501 ~CPU_BASED_CR8_STORE_EXITING;
1502#endif
f78e0e2e 1503 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1504 min2 = 0;
1505 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1506 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1507 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1508 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1509 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1510 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1511 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1512 if (adjust_vmx_controls(min2, opt2,
1513 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1514 &_cpu_based_2nd_exec_control) < 0)
1515 return -EIO;
1516 }
1517#ifndef CONFIG_X86_64
1518 if (!(_cpu_based_2nd_exec_control &
1519 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1520 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1521#endif
d56f546d 1522 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1523 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1524 enabled */
5fff7d27
GN		 1525 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1526 CPU_BASED_CR3_STORE_EXITING |
1527 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1528 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1529 vmx_capability.ept, vmx_capability.vpid);
1530 }
1c3d14fe
YS		 1531
1532 min = 0;
1533#ifdef CONFIG_X86_64
1534 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1535#endif
468d472f 1536 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1537 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1538 &_vmexit_control) < 0)
002c7f7c 1539 return -EIO;
1c3d14fe 1540
468d472f
SY		 1541 min = 0;
1542 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1543 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1544 &_vmentry_control) < 0)
002c7f7c 1545 return -EIO;
6aa8b732 1546
c68876fd 1547 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1548
1549 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1550 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1551 return -EIO;
1c3d14fe
YS		 1552
1553#ifdef CONFIG_X86_64
1554 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1555 if (vmx_msr_high & (1u<<16))
002c7f7c 1556 return -EIO;
1c3d14fe
YS		 1557#endif
1558
1559 /* Require Write-Back (WB) memory type for VMCS accesses. */
1560 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1561 return -EIO;
1c3d14fe 1562
002c7f7c
YS		 1563 vmcs_conf->size = vmx_msr_high & 0x1fff;
1564 vmcs_conf->order = get_order(vmcs_config.size);
1565 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1566
002c7f7c
YS		 1567 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1568 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1569 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1570 vmcs_conf->vmexit_ctrl = _vmexit_control;
1571 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 1572
110312c8
AK		 1573 cpu_has_load_ia32_efer =
1574 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1575 VM_ENTRY_LOAD_IA32_EFER)
1576 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1577 VM_EXIT_LOAD_IA32_EFER);
1578
1c3d14fe 1579 return 0;
c68876fd 1580}
6aa8b732
AK		 1581
1582static struct vmcs *alloc_vmcs_cpu(int cpu)
1583{
1584 int node = cpu_to_node(cpu);
1585 struct page *pages;
1586 struct vmcs *vmcs;
1587
6484eb3e 1588 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1589 if (!pages)
1590 return NULL;
1591 vmcs = page_address(pages);
1c3d14fe
YS		 1592 memset(vmcs, 0, vmcs_config.size);
1593 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1594 return vmcs;
1595}
1596
1597static struct vmcs *alloc_vmcs(void)
1598{
d3b2c338 1599 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1600}
1601
1602static void free_vmcs(struct vmcs *vmcs)
1603{
1c3d14fe 1604 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1605}
1606
39959588 1607static void free_kvm_area(void)
6aa8b732
AK		 1608{
1609 int cpu;
1610
3230bb47 1611 for_each_possible_cpu(cpu) {
6aa8b732 1612 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1613 per_cpu(vmxarea, cpu) = NULL;
1614 }
6aa8b732
AK		 1615}
1616
6aa8b732
AK		 1617static __init int alloc_kvm_area(void)
1618{
1619 int cpu;
1620
3230bb47 1621 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1622 struct vmcs *vmcs;
1623
1624 vmcs = alloc_vmcs_cpu(cpu);
1625 if (!vmcs) {
1626 free_kvm_area();
1627 return -ENOMEM;
1628 }
1629
1630 per_cpu(vmxarea, cpu) = vmcs;
1631 }
1632 return 0;
1633}
1634
1635static __init int hardware_setup(void)
1636{
002c7f7c
YS		 1637 if (setup_vmcs_config(&vmcs_config) < 0)
1638 return -EIO;
50a37eb4
JR		 1639
1640 if (boot_cpu_has(X86_FEATURE_NX))
1641 kvm_enable_efer_bits(EFER_NX);
1642
93ba03c2
SY		 1643 if (!cpu_has_vmx_vpid())
1644 enable_vpid = 0;
1645
4bc9b982
SY		 1646 if (!cpu_has_vmx_ept() ||
1647 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1648 enable_ept = 0;
3a624e29
NK		 1649 enable_unrestricted_guest = 0;
1650 }
1651
1652 if (!cpu_has_vmx_unrestricted_guest())
1653 enable_unrestricted_guest = 0;
93ba03c2
SY		 1654
1655 if (!cpu_has_vmx_flexpriority())
1656 flexpriority_enabled = 0;
1657
95ba8273
GN		 1658 if (!cpu_has_vmx_tpr_shadow())
1659 kvm_x86_ops->update_cr8_intercept = NULL;
1660
54dee993
MT		 1661 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1662 kvm_disable_largepages();
1663
4b8d54f9
ZE		 1664 if (!cpu_has_vmx_ple())
1665 ple_gap = 0;
1666
6aa8b732
AK		 1667 return alloc_kvm_area();
1668}
1669
1670static __exit void hardware_unsetup(void)
1671{
1672 free_kvm_area();
1673}
1674
6aa8b732
AK		 1675static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1676{
1677 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1678
6af11b9e 1679 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1680 vmcs_write16(sf->selector, save->selector);
1681 vmcs_writel(sf->base, save->base);
1682 vmcs_write32(sf->limit, save->limit);
1683 vmcs_write32(sf->ar_bytes, save->ar);
1684 } else {
1685 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1686 << AR_DPL_SHIFT;
1687 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1688 }
1689}
1690
1691static void enter_pmode(struct kvm_vcpu *vcpu)
1692{
1693 unsigned long flags;
a89a8fb9 1694 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1695
a89a8fb9 1696 vmx->emulation_required = 1;
7ffd92c5 1697 vmx->rmode.vm86_active = 0;
6aa8b732 1698
d0ba64f9 1699 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 1700 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1701 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1702 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1703
1704 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1705 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1706 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1707 vmcs_writel(GUEST_RFLAGS, flags);
1708
66aee91a
RR		 1709 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1710 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1711
1712 update_exception_bitmap(vcpu);
1713
a89a8fb9
MG		 1714 if (emulate_invalid_guest_state)
1715 return;
1716
7ffd92c5
AK		 1717 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1718 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1719 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1720 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1721
1722 vmcs_write16(GUEST_SS_SELECTOR, 0);
1723 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1724
1725 vmcs_write16(GUEST_CS_SELECTOR,
1726 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1727 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1728}
1729
d77c26fc 1730static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1731{
bfc6d222 1732 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1733 struct kvm_memslots *slots;
1734 gfn_t base_gfn;
1735
90d83dc3 1736 slots = kvm_memslots(kvm);
f495c6e5 1737 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1738 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1739 return base_gfn << PAGE_SHIFT;
1740 }
bfc6d222 1741 return kvm->arch.tss_addr;
6aa8b732
AK		 1742}
1743
1744static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1745{
1746 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1747
1748 save->selector = vmcs_read16(sf->selector);
1749 save->base = vmcs_readl(sf->base);
1750 save->limit = vmcs_read32(sf->limit);
1751 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 1752 vmcs_write16(sf->selector, save->base >> 4);
444e863d 1753 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 1754 vmcs_write32(sf->limit, 0xffff);
1755 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 1756 if (save->base & 0xf)
1757 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1758 " aligned when entering protected mode (seg=%d)",
1759 seg);
6aa8b732
AK		 1760}
1761
1762static void enter_rmode(struct kvm_vcpu *vcpu)
1763{
1764 unsigned long flags;
a89a8fb9 1765 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1766
3a624e29
NK		 1767 if (enable_unrestricted_guest)
1768 return;
1769
a89a8fb9 1770 vmx->emulation_required = 1;
7ffd92c5 1771 vmx->rmode.vm86_active = 1;
6aa8b732 1772
776e58ea
GN		 1773 /*
1774 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
1775 * vcpu. Call it here with phys address pointing 16M below 4G.
1776 */
1777 if (!vcpu->kvm->arch.tss_addr) {
1778 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
1779 "called before entering vcpu\n");
1780 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
1781 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
1782 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
1783 }
1784
d0ba64f9 1785 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 1786 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1787 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1788
7ffd92c5 1789 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1790 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1791
7ffd92c5 1792 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1793 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1794
1795 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1796 vmx->rmode.save_rflags = flags;
6aa8b732 1797
053de044 1798 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1799
1800 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1801 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1802 update_exception_bitmap(vcpu);
1803
a89a8fb9
MG		 1804 if (emulate_invalid_guest_state)
1805 goto continue_rmode;
1806
6aa8b732
AK		 1807 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1808 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1809 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1810
1811 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1812 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1813 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1814 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1815 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1816
7ffd92c5
AK		 1817 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1818 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1819 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1820 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1821
a89a8fb9 1822continue_rmode:
8668a3c4 1823 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 1824}
1825
401d10de
AS		 1826static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1827{
1828 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1829 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1830
1831 if (!msr)
1832 return;
401d10de 1833
44ea2b17
AK		 1834 /*
1835 * Force kernel_gs_base reloading before EFER changes, as control
1836 * of this msr depends on is_long_mode().
1837 */
1838 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1839 vcpu->arch.efer = efer;
401d10de
AS		 1840 if (efer & EFER_LMA) {
1841 vmcs_write32(VM_ENTRY_CONTROLS,
1842 vmcs_read32(VM_ENTRY_CONTROLS) |
1843 VM_ENTRY_IA32E_MODE);
1844 msr->data = efer;
1845 } else {
1846 vmcs_write32(VM_ENTRY_CONTROLS,
1847 vmcs_read32(VM_ENTRY_CONTROLS) &
1848 ~VM_ENTRY_IA32E_MODE);
1849
1850 msr->data = efer & ~EFER_LME;
1851 }
1852 setup_msrs(vmx);
1853}
1854
05b3e0c2 1855#ifdef CONFIG_X86_64
6aa8b732
AK		 1856
1857static void enter_lmode(struct kvm_vcpu *vcpu)
1858{
1859 u32 guest_tr_ar;
1860
1861 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1862 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1863 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1864 __func__);
6aa8b732
AK		 1865 vmcs_write32(GUEST_TR_AR_BYTES,
1866 (guest_tr_ar & ~AR_TYPE_MASK)
1867 | AR_TYPE_BUSY_64_TSS);
1868 }
da38f438 1869 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1870}
1871
1872static void exit_lmode(struct kvm_vcpu *vcpu)
1873{
6aa8b732
AK		 1874 vmcs_write32(VM_ENTRY_CONTROLS,
1875 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1876 & ~VM_ENTRY_IA32E_MODE);
da38f438 1877 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1878}
1879
1880#endif
1881
2384d2b3
SY		 1882static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1883{
b9d762fa 1884 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 1885 if (enable_ept) {
1886 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1887 return;
4e1096d2 1888 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 1889 }
2384d2b3
SY		 1890}
1891
e8467fda
AK		 1892static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1893{
1894 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1895
1896 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1897 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1898}
1899
aff48baa
AK		 1900static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1901{
1902 if (enable_ept && is_paging(vcpu))
1903 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1904 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1905}
1906
25c4c276 1907static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1908{
fc78f519
AK		 1909 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1910
1911 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1912 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1913}
1914
1439442c
SY		 1915static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1916{
6de4f3ad
AK		 1917 if (!test_bit(VCPU_EXREG_PDPTR,
1918 (unsigned long *)&vcpu->arch.regs_dirty))
1919 return;
1920
1439442c 1921 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1922 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1923 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1924 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1925 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 1926 }
1927}
1928
8f5d549f
AK		 1929static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1930{
1931 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1932 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1933 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1934 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1935 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 1936 }
6de4f3ad
AK		 1937
1938 __set_bit(VCPU_EXREG_PDPTR,
1939 (unsigned long *)&vcpu->arch.regs_avail);
1940 __set_bit(VCPU_EXREG_PDPTR,
1941 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1942}
1943
1439442c
SY		 1944static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1945
1946static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1947 unsigned long cr0,
1948 struct kvm_vcpu *vcpu)
1949{
aff48baa 1950 vmx_decache_cr3(vcpu);
1439442c
SY		 1951 if (!(cr0 & X86_CR0_PG)) {
1952 /* From paging/starting to nonpaging */
1953 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1954 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1955 (CPU_BASED_CR3_LOAD_EXITING |
1956 CPU_BASED_CR3_STORE_EXITING));
1957 vcpu->arch.cr0 = cr0;
fc78f519 1958 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1959 } else if (!is_paging(vcpu)) {
1960 /* From nonpaging to paging */
1961 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1962 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1963 ~(CPU_BASED_CR3_LOAD_EXITING |
1964 CPU_BASED_CR3_STORE_EXITING));
1965 vcpu->arch.cr0 = cr0;
fc78f519 1966 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1967 }
95eb84a7
SY		 1968
1969 if (!(cr0 & X86_CR0_WP))
1970 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1971}
1972
6aa8b732
AK		 1973static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1974{
7ffd92c5 1975 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1976 unsigned long hw_cr0;
1977
1978 if (enable_unrestricted_guest)
1979 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1980 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1981 else
1982 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1983
7ffd92c5 1984 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1985 enter_pmode(vcpu);
1986
7ffd92c5 1987 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1988 enter_rmode(vcpu);
1989
05b3e0c2 1990#ifdef CONFIG_X86_64
f6801dff 1991 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1992 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1993 enter_lmode(vcpu);
707d92fa 1994 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1995 exit_lmode(vcpu);
1996 }
1997#endif
1998
089d034e 1999 if (enable_ept)
1439442c
SY		 2000 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2001
02daab21 2002 if (!vcpu->fpu_active)
81231c69 2003 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2004
6aa8b732 2005 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2006 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2007 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 2008}
2009
1439442c
SY		 2010static u64 construct_eptp(unsigned long root_hpa)
2011{
2012 u64 eptp;
2013
2014 /* TODO write the value reading from MSR */
2015 eptp = VMX_EPT_DEFAULT_MT |
2016 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2017 eptp |= (root_hpa & PAGE_MASK);
2018
2019 return eptp;
2020}
2021
6aa8b732
AK		 2022static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2023{
1439442c
SY		 2024 unsigned long guest_cr3;
2025 u64 eptp;
2026
2027 guest_cr3 = cr3;
089d034e 2028 if (enable_ept) {
1439442c
SY		 2029 eptp = construct_eptp(cr3);
2030 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 2031 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 2032 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 2033 ept_load_pdptrs(vcpu);
1439442c
SY		 2034 }
2035
2384d2b3 2036 vmx_flush_tlb(vcpu);
1439442c 2037 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2038}
2039
2040static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2041{
7ffd92c5 2042 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2043 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2044
ad312c7c 2045 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2046 if (enable_ept) {
2047 if (!is_paging(vcpu)) {
2048 hw_cr4 &= ~X86_CR4_PAE;
2049 hw_cr4 |= X86_CR4_PSE;
2050 } else if (!(cr4 & X86_CR4_PAE)) {
2051 hw_cr4 &= ~X86_CR4_PAE;
2052 }
2053 }
1439442c
SY		 2054
2055 vmcs_writel(CR4_READ_SHADOW, cr4);
2056 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 2057}
2058
6aa8b732
AK		 2059static void vmx_get_segment(struct kvm_vcpu *vcpu,
2060 struct kvm_segment *var, int seg)
2061{
a9179499 2062 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2063 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
a9179499 2064 struct kvm_save_segment *save;
6aa8b732
AK		 2065 u32 ar;
2066
a9179499
AK		 2067 if (vmx->rmode.vm86_active
2068 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2069 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2070 || seg == VCPU_SREG_GS)
2071 && !emulate_invalid_guest_state) {
2072 switch (seg) {
2073 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2074 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2075 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2076 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2077 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2078 default: BUG();
2079 }
2080 var->selector = save->selector;
2081 var->base = save->base;
2082 var->limit = save->limit;
2083 ar = save->ar;
2084 if (seg == VCPU_SREG_TR
2085 || var->selector == vmcs_read16(sf->selector))
2086 goto use_saved_rmode_seg;
2087 }
6aa8b732
AK		 2088 var->base = vmcs_readl(sf->base);
2089 var->limit = vmcs_read32(sf->limit);
2090 var->selector = vmcs_read16(sf->selector);
2091 ar = vmcs_read32(sf->ar_bytes);
a9179499 2092use_saved_rmode_seg:
9fd4a3b7 2093 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2094 ar = 0;
2095 var->type = ar & 15;
2096 var->s = (ar >> 4) & 1;
2097 var->dpl = (ar >> 5) & 3;
2098 var->present = (ar >> 7) & 1;
2099 var->avl = (ar >> 12) & 1;
2100 var->l = (ar >> 13) & 1;
2101 var->db = (ar >> 14) & 1;
2102 var->g = (ar >> 15) & 1;
2103 var->unusable = (ar >> 16) & 1;
2104}
2105
a9179499
AK		 2106static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2107{
2108 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2109 struct kvm_segment s;
2110
2111 if (to_vmx(vcpu)->rmode.vm86_active) {
2112 vmx_get_segment(vcpu, &s, seg);
2113 return s.base;
2114 }
2115 return vmcs_readl(sf->base);
2116}
2117
2e4d2653
IE		 2118static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2119{
3eeb3288 2120 if (!is_protmode(vcpu))
2e4d2653
IE		 2121 return 0;
2122
f6e78475 2123 if (kvm_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2e4d2653
IE		 2124 return 3;
2125
eab4b8aa 2126 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2127}
2128
653e3108 2129static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2130{
6aa8b732
AK		 2131 u32 ar;
2132
653e3108 2133 if (var->unusable)
6aa8b732
AK		 2134 ar = 1 << 16;
2135 else {
2136 ar = var->type & 15;
2137 ar |= (var->s & 1) << 4;
2138 ar |= (var->dpl & 3) << 5;
2139 ar |= (var->present & 1) << 7;
2140 ar |= (var->avl & 1) << 12;
2141 ar |= (var->l & 1) << 13;
2142 ar |= (var->db & 1) << 14;
2143 ar |= (var->g & 1) << 15;
2144 }
f7fbf1fd
UL		 2145 if (ar == 0) /* a 0 value means unusable */
2146 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2147
2148 return ar;
2149}
2150
2151static void vmx_set_segment(struct kvm_vcpu *vcpu,
2152 struct kvm_segment *var, int seg)
2153{
7ffd92c5 2154 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2155 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2156 u32 ar;
2157
7ffd92c5 2158 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 2159 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 2160 vmx->rmode.tr.selector = var->selector;
2161 vmx->rmode.tr.base = var->base;
2162 vmx->rmode.tr.limit = var->limit;
2163 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2164 return;
2165 }
2166 vmcs_writel(sf->base, var->base);
2167 vmcs_write32(sf->limit, var->limit);
2168 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2169 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2170 /*
2171 * Hack real-mode segments into vm86 compatibility.
2172 */
2173 if (var->base == 0xffff0000 && var->selector == 0xf000)
2174 vmcs_writel(sf->base, 0xf0000);
2175 ar = 0xf3;
2176 } else
2177 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2178
2179 /*
2180 * Fix the "Accessed" bit in AR field of segment registers for older
2181 * qemu binaries.
2182 * IA32 arch specifies that at the time of processor reset the
2183 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2184 * is setting it to 0 in the usedland code. This causes invalid guest
2185 * state vmexit when "unrestricted guest" mode is turned on.
2186 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2187 * tree. Newer qemu binaries with that qemu fix would not need this
2188 * kvm hack.
2189 */
2190 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2191 ar |= 0x1; /* Accessed */
2192
6aa8b732
AK		 2193 vmcs_write32(sf->ar_bytes, ar);
2194}
2195
6aa8b732
AK		 2196static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2197{
2198 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2199
2200 *db = (ar >> 14) & 1;
2201 *l = (ar >> 13) & 1;
2202}
2203
89a27f4d 2204static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2205{
89a27f4d
GN		 2206 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2207 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2208}
2209
89a27f4d 2210static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2211{
89a27f4d
GN		 2212 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2213 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2214}
2215
89a27f4d 2216static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2217{
89a27f4d
GN		 2218 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2219 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2220}
2221
89a27f4d 2222static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2223{
89a27f4d
GN		 2224 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2225 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2226}
2227
648dfaa7
MG		 2228static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2229{
2230 struct kvm_segment var;
2231 u32 ar;
2232
2233 vmx_get_segment(vcpu, &var, seg);
2234 ar = vmx_segment_access_rights(&var);
2235
2236 if (var.base != (var.selector << 4))
2237 return false;
2238 if (var.limit != 0xffff)
2239 return false;
2240 if (ar != 0xf3)
2241 return false;
2242
2243 return true;
2244}
2245
2246static bool code_segment_valid(struct kvm_vcpu *vcpu)
2247{
2248 struct kvm_segment cs;
2249 unsigned int cs_rpl;
2250
2251 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2252 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2253
1872a3f4
AK		 2254 if (cs.unusable)
2255 return false;
648dfaa7
MG		 2256 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2257 return false;
2258 if (!cs.s)
2259 return false;
1872a3f4 2260 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2261 if (cs.dpl > cs_rpl)
2262 return false;
1872a3f4 2263 } else {
648dfaa7
MG		 2264 if (cs.dpl != cs_rpl)
2265 return false;
2266 }
2267 if (!cs.present)
2268 return false;
2269
2270 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2271 return true;
2272}
2273
2274static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2275{
2276 struct kvm_segment ss;
2277 unsigned int ss_rpl;
2278
2279 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2280 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2281
1872a3f4
AK		 2282 if (ss.unusable)
2283 return true;
2284 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2285 return false;
2286 if (!ss.s)
2287 return false;
2288 if (ss.dpl != ss_rpl) /* DPL != RPL */
2289 return false;
2290 if (!ss.present)
2291 return false;
2292
2293 return true;
2294}
2295
2296static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2297{
2298 struct kvm_segment var;
2299 unsigned int rpl;
2300
2301 vmx_get_segment(vcpu, &var, seg);
2302 rpl = var.selector & SELECTOR_RPL_MASK;
2303
1872a3f4
AK		 2304 if (var.unusable)
2305 return true;
648dfaa7
MG		 2306 if (!var.s)
2307 return false;
2308 if (!var.present)
2309 return false;
2310 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2311 if (var.dpl < rpl) /* DPL < RPL */
2312 return false;
2313 }
2314
2315 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2316 * rights flags
2317 */
2318 return true;
2319}
2320
2321static bool tr_valid(struct kvm_vcpu *vcpu)
2322{
2323 struct kvm_segment tr;
2324
2325 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2326
1872a3f4
AK		 2327 if (tr.unusable)
2328 return false;
648dfaa7
MG		 2329 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2330 return false;
1872a3f4 2331 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2332 return false;
2333 if (!tr.present)
2334 return false;
2335
2336 return true;
2337}
2338
2339static bool ldtr_valid(struct kvm_vcpu *vcpu)
2340{
2341 struct kvm_segment ldtr;
2342
2343 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2344
1872a3f4
AK		 2345 if (ldtr.unusable)
2346 return true;
648dfaa7
MG		 2347 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2348 return false;
2349 if (ldtr.type != 2)
2350 return false;
2351 if (!ldtr.present)
2352 return false;
2353
2354 return true;
2355}
2356
2357static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2358{
2359 struct kvm_segment cs, ss;
2360
2361 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2362 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2363
2364 return ((cs.selector & SELECTOR_RPL_MASK) ==
2365 (ss.selector & SELECTOR_RPL_MASK));
2366}
2367
2368/*
2369 * Check if guest state is valid. Returns true if valid, false if
2370 * not.
2371 * We assume that registers are always usable
2372 */
2373static bool guest_state_valid(struct kvm_vcpu *vcpu)
2374{
2375 /* real mode guest state checks */
3eeb3288 2376 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2377 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2378 return false;
2379 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2380 return false;
2381 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2382 return false;
2383 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2384 return false;
2385 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2386 return false;
2387 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2388 return false;
2389 } else {
2390 /* protected mode guest state checks */
2391 if (!cs_ss_rpl_check(vcpu))
2392 return false;
2393 if (!code_segment_valid(vcpu))
2394 return false;
2395 if (!stack_segment_valid(vcpu))
2396 return false;
2397 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2398 return false;
2399 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2400 return false;
2401 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2402 return false;
2403 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2404 return false;
2405 if (!tr_valid(vcpu))
2406 return false;
2407 if (!ldtr_valid(vcpu))
2408 return false;
2409 }
2410 /* TODO:
2411 * - Add checks on RIP
2412 * - Add checks on RFLAGS
2413 */
2414
2415 return true;
2416}
2417
d77c26fc 2418static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2419{
40dcaa9f 2420 gfn_t fn;
195aefde 2421 u16 data = 0;
40dcaa9f 2422 int r, idx, ret = 0;
6aa8b732 2423
40dcaa9f
XG		 2424 idx = srcu_read_lock(&kvm->srcu);
2425 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 2426 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2427 if (r < 0)
10589a46 2428 goto out;
195aefde 2429 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2430 r = kvm_write_guest_page(kvm, fn++, &data,
2431 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2432 if (r < 0)
10589a46 2433 goto out;
195aefde
IE		 2434 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2435 if (r < 0)
10589a46 2436 goto out;
195aefde
IE		 2437 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2438 if (r < 0)
10589a46 2439 goto out;
195aefde 2440 data = ~0;
10589a46
MT		 2441 r = kvm_write_guest_page(kvm, fn, &data,
2442 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2443 sizeof(u8));
195aefde 2444 if (r < 0)
10589a46
MT		 2445 goto out;
2446
2447 ret = 1;
2448out:
40dcaa9f 2449 srcu_read_unlock(&kvm->srcu, idx);
10589a46 2450 return ret;
6aa8b732
AK		 2451}
2452
b7ebfb05
SY		 2453static int init_rmode_identity_map(struct kvm *kvm)
2454{
40dcaa9f 2455 int i, idx, r, ret;
b7ebfb05
SY		 2456 pfn_t identity_map_pfn;
2457 u32 tmp;
2458
089d034e 2459 if (!enable_ept)
b7ebfb05
SY		 2460 return 1;
2461 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2462 printk(KERN_ERR "EPT: identity-mapping pagetable "
2463 "haven't been allocated!\n");
2464 return 0;
2465 }
2466 if (likely(kvm->arch.ept_identity_pagetable_done))
2467 return 1;
2468 ret = 0;
b927a3ce 2469 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 2470 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 2471 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2472 if (r < 0)
2473 goto out;
2474 /* Set up identity-mapping pagetable for EPT in real mode */
2475 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2476 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2477 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2478 r = kvm_write_guest_page(kvm, identity_map_pfn,
2479 &tmp, i * sizeof(tmp), sizeof(tmp));
2480 if (r < 0)
2481 goto out;
2482 }
2483 kvm->arch.ept_identity_pagetable_done = true;
2484 ret = 1;
2485out:
40dcaa9f 2486 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 2487 return ret;
2488}
2489
6aa8b732
AK		 2490static void seg_setup(int seg)
2491{
2492 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2493 unsigned int ar;
6aa8b732
AK		 2494
2495 vmcs_write16(sf->selector, 0);
2496 vmcs_writel(sf->base, 0);
2497 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2498 if (enable_unrestricted_guest) {
2499 ar = 0x93;
2500 if (seg == VCPU_SREG_CS)
2501 ar |= 0x08; /* code segment */
2502 } else
2503 ar = 0xf3;
2504
2505 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2506}
2507
f78e0e2e
SY		 2508static int alloc_apic_access_page(struct kvm *kvm)
2509{
2510 struct kvm_userspace_memory_region kvm_userspace_mem;
2511 int r = 0;
2512
79fac95e 2513 mutex_lock(&kvm->slots_lock);
bfc6d222 2514 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2515 goto out;
2516 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2517 kvm_userspace_mem.flags = 0;
2518 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2519 kvm_userspace_mem.memory_size = PAGE_SIZE;
2520 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2521 if (r)
2522 goto out;
72dc67a6 2523
bfc6d222 2524 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2525out:
79fac95e 2526 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2527 return r;
2528}
2529
b7ebfb05
SY		 2530static int alloc_identity_pagetable(struct kvm *kvm)
2531{
2532 struct kvm_userspace_memory_region kvm_userspace_mem;
2533 int r = 0;
2534
79fac95e 2535 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2536 if (kvm->arch.ept_identity_pagetable)
2537 goto out;
2538 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2539 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2540 kvm_userspace_mem.guest_phys_addr =
2541 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2542 kvm_userspace_mem.memory_size = PAGE_SIZE;
2543 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2544 if (r)
2545 goto out;
2546
b7ebfb05 2547 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2548 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2549out:
79fac95e 2550 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2551 return r;
2552}
2553
2384d2b3
SY		 2554static void allocate_vpid(struct vcpu_vmx *vmx)
2555{
2556 int vpid;
2557
2558 vmx->vpid = 0;
919818ab 2559 if (!enable_vpid)
2384d2b3
SY		 2560 return;
2561 spin_lock(&vmx_vpid_lock);
2562 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2563 if (vpid < VMX_NR_VPIDS) {
2564 vmx->vpid = vpid;
2565 __set_bit(vpid, vmx_vpid_bitmap);
2566 }
2567 spin_unlock(&vmx_vpid_lock);
2568}
2569
cdbecfc3
LJ		 2570static void free_vpid(struct vcpu_vmx *vmx)
2571{
2572 if (!enable_vpid)
2573 return;
2574 spin_lock(&vmx_vpid_lock);
2575 if (vmx->vpid != 0)
2576 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2577 spin_unlock(&vmx_vpid_lock);
2578}
2579
5897297b 2580static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2581{
3e7c73e9 2582 int f = sizeof(unsigned long);
25c5f225
SY		 2583
2584 if (!cpu_has_vmx_msr_bitmap())
2585 return;
2586
2587 /*
2588 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2589 * have the write-low and read-high bitmap offsets the wrong way round.
2590 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2591 */
25c5f225 2592 if (msr <= 0x1fff) {
3e7c73e9
AK		 2593 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2594 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2595 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2596 msr &= 0x1fff;
3e7c73e9
AK		 2597 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2598 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2599 }
25c5f225
SY		 2600}
2601
5897297b
AK		 2602static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2603{
2604 if (!longmode_only)
2605 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2606 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2607}
2608
6aa8b732
AK		 2609/*
2610 * Sets up the vmcs for emulated real mode.
2611 */
8b9cf98c 2612static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2613{
468d472f 2614 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2615 u32 junk;
f4e1b3c8 2616 u64 host_pat;
6aa8b732 2617 unsigned long a;
89a27f4d 2618 struct desc_ptr dt;
6aa8b732 2619 int i;
cd2276a7 2620 unsigned long kvm_vmx_return;
6e5d865c 2621 u32 exec_control;
6aa8b732 2622
6aa8b732 2623 /* I/O */
3e7c73e9
AK		 2624 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2625 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2626
25c5f225 2627 if (cpu_has_vmx_msr_bitmap())
5897297b 2628 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2629
6aa8b732
AK		 2630 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2631
6aa8b732 2632 /* Control */
1c3d14fe
YS		 2633 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2634 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2635
2636 exec_control = vmcs_config.cpu_based_exec_ctrl;
2637 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2638 exec_control &= ~CPU_BASED_TPR_SHADOW;
2639#ifdef CONFIG_X86_64
2640 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2641 CPU_BASED_CR8_LOAD_EXITING;
2642#endif
2643 }
089d034e 2644 if (!enable_ept)
d56f546d 2645 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2646 CPU_BASED_CR3_LOAD_EXITING |
2647 CPU_BASED_INVLPG_EXITING;
6e5d865c 2648 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2649
83ff3b9d
SY		 2650 if (cpu_has_secondary_exec_ctrls()) {
2651 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2652 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2653 exec_control &=
2654 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2655 if (vmx->vpid == 0)
2656 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2657 if (!enable_ept) {
d56f546d 2658 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2659 enable_unrestricted_guest = 0;
2660 }
3a624e29
NK		 2661 if (!enable_unrestricted_guest)
2662 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2663 if (!ple_gap)
2664 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2665 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2666 }
f78e0e2e 2667
4b8d54f9
ZE		 2668 if (ple_gap) {
2669 vmcs_write32(PLE_GAP, ple_gap);
2670 vmcs_write32(PLE_WINDOW, ple_window);
2671 }
2672
c7addb90
AK		 2673 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2674 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2675 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2676
1c11e713 2677 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2678 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2679 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2680
2681 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2682 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2683 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
9581d442
AK		 2684 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2685 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6aa8b732 2686 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2687#ifdef CONFIG_X86_64
6aa8b732
AK		 2688 rdmsrl(MSR_FS_BASE, a);
2689 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2690 rdmsrl(MSR_GS_BASE, a);
2691 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2692#else
2693 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2694 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2695#endif
2696
2697 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2698
ec68798c 2699 native_store_idt(&dt);
89a27f4d 2700 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2701
d77c26fc 2702 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2703 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2704 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2705 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2706 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2707 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2708 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2709
2710 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2711 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2712 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2713 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2714 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2715 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2716
468d472f
SY		 2717 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2718 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2719 host_pat = msr_low | ((u64) msr_high << 32);
2720 vmcs_write64(HOST_IA32_PAT, host_pat);
2721 }
2722 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2723 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2724 host_pat = msr_low | ((u64) msr_high << 32);
2725 /* Write the default value follow host pat */
2726 vmcs_write64(GUEST_IA32_PAT, host_pat);
2727 /* Keep arch.pat sync with GUEST_IA32_PAT */
2728 vmx->vcpu.arch.pat = host_pat;
2729 }
2730
6aa8b732
AK		 2731 for (i = 0; i < NR_VMX_MSR; ++i) {
2732 u32 index = vmx_msr_index[i];
2733 u32 data_low, data_high;
a2fa3e9f 2734 int j = vmx->nmsrs;
6aa8b732
AK		 2735
2736 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2737 continue;
432bd6cb
AK		 2738 if (wrmsr_safe(index, data_low, data_high) < 0)
2739 continue;
26bb0981
AK		 2740 vmx->guest_msrs[j].index = i;
2741 vmx->guest_msrs[j].data = 0;
d5696725 2742 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2743 ++vmx->nmsrs;
6aa8b732 2744 }
6aa8b732 2745
1c3d14fe 2746 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2747
2748 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2749 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2750
e00c8cf2 2751 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2752 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2753 if (enable_ept)
2754 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2755 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2756
99e3e30a 2757 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 2758
e00c8cf2
AK		 2759 return 0;
2760}
2761
2762static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2763{
2764 struct vcpu_vmx *vmx = to_vmx(vcpu);
2765 u64 msr;
4b9d3a04 2766 int ret;
e00c8cf2 2767
5fdbf976 2768 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 2769
7ffd92c5 2770 vmx->rmode.vm86_active = 0;
e00c8cf2 2771
3b86cd99
JK		 2772 vmx->soft_vnmi_blocked = 0;
2773
ad312c7c 2774 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2775 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2776 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2777 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2778 msr |= MSR_IA32_APICBASE_BSP;
2779 kvm_set_apic_base(&vmx->vcpu, msr);
2780
10ab25cd
JK		 2781 ret = fx_init(&vmx->vcpu);
2782 if (ret != 0)
2783 goto out;
e00c8cf2 2784
5706be0d 2785 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2786 /*
2787 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2788 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2789 */
c5af89b6 2790 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2791 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2792 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2793 } else {
ad312c7c
ZX		 2794 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2795 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2796 }
e00c8cf2
AK		 2797
2798 seg_setup(VCPU_SREG_DS);
2799 seg_setup(VCPU_SREG_ES);
2800 seg_setup(VCPU_SREG_FS);
2801 seg_setup(VCPU_SREG_GS);
2802 seg_setup(VCPU_SREG_SS);
2803
2804 vmcs_write16(GUEST_TR_SELECTOR, 0);
2805 vmcs_writel(GUEST_TR_BASE, 0);
2806 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2807 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2808
2809 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2810 vmcs_writel(GUEST_LDTR_BASE, 0);
2811 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2812 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2813
2814 vmcs_write32(GUEST_SYSENTER_CS, 0);
2815 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2816 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2817
2818 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2819 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2820 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2821 else
5fdbf976
MT		 2822 kvm_rip_write(vcpu, 0);
2823 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2824
e00c8cf2
AK		 2825 vmcs_writel(GUEST_DR7, 0x400);
2826
2827 vmcs_writel(GUEST_GDTR_BASE, 0);
2828 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2829
2830 vmcs_writel(GUEST_IDTR_BASE, 0);
2831 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2832
443381a8 2833 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 2834 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2835 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2836
e00c8cf2
AK		 2837 /* Special registers */
2838 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2839
2840 setup_msrs(vmx);
2841
6aa8b732
AK		 2842 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2843
f78e0e2e
SY		 2844 if (cpu_has_vmx_tpr_shadow()) {
2845 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2846 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2847 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 2848 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 2849 vmcs_write32(TPR_THRESHOLD, 0);
2850 }
2851
2852 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2853 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2854 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2855
2384d2b3
SY		 2856 if (vmx->vpid != 0)
2857 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2858
fa40052c 2859 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2860 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2861 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2862 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2863 vmx_fpu_activate(&vmx->vcpu);
2864 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2865
b9d762fa 2866 vpid_sync_context(vmx);
2384d2b3 2867
3200f405 2868 ret = 0;
6aa8b732 2869
a89a8fb9
MG		 2870 /* HACK: Don't enable emulation on guest boot/reset */
2871 vmx->emulation_required = 0;
2872
6aa8b732
AK		 2873out:
2874 return ret;
2875}
2876
3b86cd99
JK		 2877static void enable_irq_window(struct kvm_vcpu *vcpu)
2878{
2879 u32 cpu_based_vm_exec_control;
2880
2881 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2882 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2883 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2884}
2885
2886static void enable_nmi_window(struct kvm_vcpu *vcpu)
2887{
2888 u32 cpu_based_vm_exec_control;
2889
2890 if (!cpu_has_virtual_nmis()) {
2891 enable_irq_window(vcpu);
2892 return;
2893 }
2894
30bd0c4c
AK		 2895 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2896 enable_irq_window(vcpu);
2897 return;
2898 }
3b86cd99
JK		 2899 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2900 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2901 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2902}
2903
66fd3f7f 2904static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2905{
9c8cba37 2906 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2907 uint32_t intr;
2908 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2909
229456fc 2910 trace_kvm_inj_virq(irq);
2714d1d3 2911
fa89a817 2912 ++vcpu->stat.irq_injections;
7ffd92c5 2913 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2914 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2915 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 2916 return;
2917 }
66fd3f7f
GN		 2918 intr = irq | INTR_INFO_VALID_MASK;
2919 if (vcpu->arch.interrupt.soft) {
2920 intr |= INTR_TYPE_SOFT_INTR;
2921 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2922 vmx->vcpu.arch.event_exit_inst_len);
2923 } else
2924 intr |= INTR_TYPE_EXT_INTR;
2925 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 2926 vmx_clear_hlt(vcpu);
85f455f7
ED		 2927}
2928
f08864b4
SY		 2929static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2930{
66a5a347
JK		 2931 struct vcpu_vmx *vmx = to_vmx(vcpu);
2932
3b86cd99
JK		 2933 if (!cpu_has_virtual_nmis()) {
2934 /*
2935 * Tracking the NMI-blocked state in software is built upon
2936 * finding the next open IRQ window. This, in turn, depends on
2937 * well-behaving guests: They have to keep IRQs disabled at
2938 * least as long as the NMI handler runs. Otherwise we may
2939 * cause NMI nesting, maybe breaking the guest. But as this is
2940 * highly unlikely, we can live with the residual risk.
2941 */
2942 vmx->soft_vnmi_blocked = 1;
2943 vmx->vnmi_blocked_time = 0;
2944 }
2945
487b391d 2946 ++vcpu->stat.nmi_injections;
7ffd92c5 2947 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2948 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2949 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 2950 return;
2951 }
f08864b4
SY		 2952 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2953 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 2954 vmx_clear_hlt(vcpu);
f08864b4
SY		 2955}
2956
c4282df9 2957static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2958{
3b86cd99 2959 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2960 return 0;
33f089ca 2961
c4282df9 2962 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 2963 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2964 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2965}
2966
3cfc3092
JK		 2967static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2968{
2969 if (!cpu_has_virtual_nmis())
2970 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2971 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2972}
2973
2974static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2975{
2976 struct vcpu_vmx *vmx = to_vmx(vcpu);
2977
2978 if (!cpu_has_virtual_nmis()) {
2979 if (vmx->soft_vnmi_blocked != masked) {
2980 vmx->soft_vnmi_blocked = masked;
2981 vmx->vnmi_blocked_time = 0;
2982 }
2983 } else {
2984 if (masked)
2985 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2986 GUEST_INTR_STATE_NMI);
2987 else
2988 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2989 GUEST_INTR_STATE_NMI);
2990 }
2991}
2992
78646121
GN		 2993static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2994{
c4282df9
GN		 2995 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2996 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2997 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2998}
2999
cbc94022
IE		 3000static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3001{
3002 int ret;
3003 struct kvm_userspace_memory_region tss_mem = {
6fe63979 3004 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 3005 .guest_phys_addr = addr,
3006 .memory_size = PAGE_SIZE * 3,
3007 .flags = 0,
3008 };
3009
3010 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3011 if (ret)
3012 return ret;
bfc6d222 3013 kvm->arch.tss_addr = addr;
93ea5388
GN		 3014 if (!init_rmode_tss(kvm))
3015 return -ENOMEM;
3016
cbc94022
IE		 3017 return 0;
3018}
3019
6aa8b732
AK		 3020static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3021 int vec, u32 err_code)
3022{
b3f37707
NK		 3023 /*
3024 * Instruction with address size override prefix opcode 0x67
3025 * Cause the #SS fault with 0 error code in VM86 mode.
3026 */
3027 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 3028 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 3029 return 1;
77ab6db0
JK		 3030 /*
3031 * Forward all other exceptions that are valid in real mode.
3032 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3033 * the required debugging infrastructure rework.
3034 */
3035 switch (vec) {
77ab6db0 3036 case DB_VECTOR:
d0bfb940
JK		 3037 if (vcpu->guest_debug &
3038 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3039 return 0;
3040 kvm_queue_exception(vcpu, vec);
3041 return 1;
77ab6db0 3042 case BP_VECTOR:
c573cd22
JK		 3043 /*
3044 * Update instruction length as we may reinject the exception
3045 * from user space while in guest debugging mode.
3046 */
3047 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3048 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 3049 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3050 return 0;
3051 /* fall through */
3052 case DE_VECTOR:
77ab6db0
JK		 3053 case OF_VECTOR:
3054 case BR_VECTOR:
3055 case UD_VECTOR:
3056 case DF_VECTOR:
3057 case SS_VECTOR:
3058 case GP_VECTOR:
3059 case MF_VECTOR:
3060 kvm_queue_exception(vcpu, vec);
3061 return 1;
3062 }
6aa8b732
AK		 3063 return 0;
3064}
3065
a0861c02
AK		 3066/*
3067 * Trigger machine check on the host. We assume all the MSRs are already set up
3068 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3069 * We pass a fake environment to the machine check handler because we want
3070 * the guest to be always treated like user space, no matter what context
3071 * it used internally.
3072 */
3073static void kvm_machine_check(void)
3074{
3075#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3076 struct pt_regs regs = {
3077 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3078 .flags = X86_EFLAGS_IF,
3079 };
3080
3081 do_machine_check(&regs, 0);
3082#endif
3083}
3084
851ba692 3085static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3086{
3087 /* already handled by vcpu_run */
3088 return 1;
3089}
3090
851ba692 3091static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3092{
1155f76a 3093 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3094 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3095 u32 intr_info, ex_no, error_code;
42dbaa5a 3096 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3097 u32 vect_info;
3098 enum emulation_result er;
3099
1155f76a 3100 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 3101 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3102
a0861c02 3103 if (is_machine_check(intr_info))
851ba692 3104 return handle_machine_check(vcpu);
a0861c02 3105
6aa8b732 3106 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3107 !is_page_fault(intr_info)) {
3108 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3109 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3110 vcpu->run->internal.ndata = 2;
3111 vcpu->run->internal.data[0] = vect_info;
3112 vcpu->run->internal.data[1] = intr_info;
3113 return 0;
3114 }
6aa8b732 3115
e4a41889 3116 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3117 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3118
3119 if (is_no_device(intr_info)) {
5fd86fcf 3120 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3121 return 1;
3122 }
3123
7aa81cc0 3124 if (is_invalid_opcode(intr_info)) {
51d8b661 3125 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 3126 if (er != EMULATE_DONE)
7ee5d940 3127 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3128 return 1;
3129 }
3130
6aa8b732 3131 error_code = 0;
5fdbf976 3132 rip = kvm_rip_read(vcpu);
2e11384c 3133 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3134 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3135 if (is_page_fault(intr_info)) {
1439442c 3136 /* EPT won't cause page fault directly */
089d034e 3137 if (enable_ept)
1439442c 3138 BUG();
6aa8b732 3139 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3140 trace_kvm_page_fault(cr2, error_code);
3141
3298b75c 3142 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3143 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 3144 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 3145 }
3146
7ffd92c5 3147 if (vmx->rmode.vm86_active &&
6aa8b732 3148 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3149 error_code)) {
ad312c7c
ZX		 3150 if (vcpu->arch.halt_request) {
3151 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3152 return kvm_emulate_halt(vcpu);
3153 }
6aa8b732 3154 return 1;
72d6e5a0 3155 }
6aa8b732 3156
d0bfb940 3157 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3158 switch (ex_no) {
3159 case DB_VECTOR:
3160 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3161 if (!(vcpu->guest_debug &
3162 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3163 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3164 kvm_queue_exception(vcpu, DB_VECTOR);
3165 return 1;
3166 }
3167 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3168 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3169 /* fall through */
3170 case BP_VECTOR:
c573cd22
JK		 3171 /*
3172 * Update instruction length as we may reinject #BP from
3173 * user space while in guest debugging mode. Reading it for
3174 * #DB as well causes no harm, it is not used in that case.
3175 */
3176 vmx->vcpu.arch.event_exit_inst_len =
3177 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3178 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3179 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3180 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3181 break;
3182 default:
d0bfb940
JK		 3183 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3184 kvm_run->ex.exception = ex_no;
3185 kvm_run->ex.error_code = error_code;
42dbaa5a 3186 break;
6aa8b732 3187 }
6aa8b732
AK		 3188 return 0;
3189}
3190
851ba692 3191static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3192{
1165f5fe 3193 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3194 return 1;
3195}
3196
851ba692 3197static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3198{
851ba692 3199 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3200 return 0;
3201}
6aa8b732 3202
851ba692 3203static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3204{
bfdaab09 3205 unsigned long exit_qualification;
34c33d16 3206 int size, in, string;
039576c0 3207 unsigned port;
6aa8b732 3208
bfdaab09 3209 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3210 string = (exit_qualification & 16) != 0;
cf8f70bf 3211 in = (exit_qualification & 8) != 0;
e70669ab 3212
cf8f70bf 3213 ++vcpu->stat.io_exits;
e70669ab 3214
cf8f70bf 3215 if (string || in)
51d8b661 3216 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 3217
cf8f70bf
GN		 3218 port = exit_qualification >> 16;
3219 size = (exit_qualification & 7) + 1;
e93f36bc 3220 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3221
3222 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3223}
3224
102d8325
IM		 3225static void
3226vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3227{
3228 /*
3229 * Patch in the VMCALL instruction:
3230 */
3231 hypercall[0] = 0x0f;
3232 hypercall[1] = 0x01;
3233 hypercall[2] = 0xc1;
102d8325
IM		 3234}
3235
851ba692 3236static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3237{
229456fc 3238 unsigned long exit_qualification, val;
6aa8b732
AK		 3239 int cr;
3240 int reg;
49a9b07e 3241 int err;
6aa8b732 3242
bfdaab09 3243 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3244 cr = exit_qualification & 15;
3245 reg = (exit_qualification >> 8) & 15;
3246 switch ((exit_qualification >> 4) & 3) {
3247 case 0: /* mov to cr */
229456fc
MT		 3248 val = kvm_register_read(vcpu, reg);
3249 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3250 switch (cr) {
3251 case 0:
49a9b07e 3252 err = kvm_set_cr0(vcpu, val);
db8fcefa 3253 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3254 return 1;
3255 case 3:
2390218b 3256 err = kvm_set_cr3(vcpu, val);
db8fcefa 3257 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3258 return 1;
3259 case 4:
a83b29c6 3260 err = kvm_set_cr4(vcpu, val);
db8fcefa 3261 kvm_complete_insn_gp(vcpu, err);
6aa8b732 3262 return 1;
0a5fff19
GN		 3263 case 8: {
3264 u8 cr8_prev = kvm_get_cr8(vcpu);
3265 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 3266 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 3267 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 3268 if (irqchip_in_kernel(vcpu->kvm))
3269 return 1;
3270 if (cr8_prev <= cr8)
3271 return 1;
851ba692 3272 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3273 return 0;
3274 }
6aa8b732
AK		 3275 };
3276 break;
25c4c276 3277 case 2: /* clts */
edcafe3c 3278 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3279 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3280 skip_emulated_instruction(vcpu);
6b52d186 3281 vmx_fpu_activate(vcpu);
25c4c276 3282 return 1;
6aa8b732
AK		 3283 case 1: /*mov from cr*/
3284 switch (cr) {
3285 case 3:
9f8fe504
AK		 3286 val = kvm_read_cr3(vcpu);
3287 kvm_register_write(vcpu, reg, val);
3288 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3289 skip_emulated_instruction(vcpu);
3290 return 1;
3291 case 8:
229456fc
MT		 3292 val = kvm_get_cr8(vcpu);
3293 kvm_register_write(vcpu, reg, val);
3294 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3295 skip_emulated_instruction(vcpu);
3296 return 1;
3297 }
3298 break;
3299 case 3: /* lmsw */
a1f83a74 3300 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3301 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3302 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3303
3304 skip_emulated_instruction(vcpu);
3305 return 1;
3306 default:
3307 break;
3308 }
851ba692 3309 vcpu->run->exit_reason = 0;
f0242478 3310 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3311 (int)(exit_qualification >> 4) & 3, cr);
3312 return 0;
3313}
3314
851ba692 3315static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3316{
bfdaab09 3317 unsigned long exit_qualification;
6aa8b732
AK		 3318 int dr, reg;
3319
f2483415 3320 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3321 if (!kvm_require_cpl(vcpu, 0))
3322 return 1;
42dbaa5a
JK		 3323 dr = vmcs_readl(GUEST_DR7);
3324 if (dr & DR7_GD) {
3325 /*
3326 * As the vm-exit takes precedence over the debug trap, we
3327 * need to emulate the latter, either for the host or the
3328 * guest debugging itself.
3329 */
3330 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3331 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3332 vcpu->run->debug.arch.dr7 = dr;
3333 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3334 vmcs_readl(GUEST_CS_BASE) +
3335 vmcs_readl(GUEST_RIP);
851ba692
AK		 3336 vcpu->run->debug.arch.exception = DB_VECTOR;
3337 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3338 return 0;
3339 } else {
3340 vcpu->arch.dr7 &= ~DR7_GD;
3341 vcpu->arch.dr6 |= DR6_BD;
3342 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3343 kvm_queue_exception(vcpu, DB_VECTOR);
3344 return 1;
3345 }
3346 }
3347
bfdaab09 3348 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3349 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3350 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3351 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3352 unsigned long val;
3353 if (!kvm_get_dr(vcpu, dr, &val))
3354 kvm_register_write(vcpu, reg, val);
3355 } else
3356 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3357 skip_emulated_instruction(vcpu);
3358 return 1;
3359}
3360
020df079
GN		 3361static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3362{
3363 vmcs_writel(GUEST_DR7, val);
3364}
3365
851ba692 3366static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3367{
06465c5a
AK		 3368 kvm_emulate_cpuid(vcpu);
3369 return 1;
6aa8b732
AK		 3370}
3371
851ba692 3372static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3373{
ad312c7c 3374 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3375 u64 data;
3376
3377 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3378 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3379 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3380 return 1;
3381 }
3382
229456fc 3383 trace_kvm_msr_read(ecx, data);
2714d1d3 3384
6aa8b732 3385 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3386 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3387 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3388 skip_emulated_instruction(vcpu);
3389 return 1;
3390}
3391
851ba692 3392static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3393{
ad312c7c
ZX		 3394 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3395 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3396 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3397
3398 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3399 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3400 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3401 return 1;
3402 }
3403
59200273 3404 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3405 skip_emulated_instruction(vcpu);
3406 return 1;
3407}
3408
851ba692 3409static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 3410{
3842d135 3411 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 3412 return 1;
3413}
3414
851ba692 3415static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3416{
85f455f7
ED		 3417 u32 cpu_based_vm_exec_control;
3418
3419 /* clear pending irq */
3420 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3421 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3422 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3423
3842d135
AK		 3424 kvm_make_request(KVM_REQ_EVENT, vcpu);
3425
a26bf12a 3426 ++vcpu->stat.irq_window_exits;
2714d1d3 3427
c1150d8c
DL		 3428 /*
3429 * If the user space waits to inject interrupts, exit as soon as
3430 * possible
3431 */
8061823a 3432 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3433 vcpu->run->request_interrupt_window &&
8061823a 3434 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3435 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3436 return 0;
3437 }
6aa8b732
AK		 3438 return 1;
3439}
3440
851ba692 3441static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3442{
3443 skip_emulated_instruction(vcpu);
d3bef15f 3444 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3445}
3446
851ba692 3447static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3448{
510043da 3449 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3450 kvm_emulate_hypercall(vcpu);
3451 return 1;
c21415e8
IM		 3452}
3453
851ba692 3454static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3455{
3456 kvm_queue_exception(vcpu, UD_VECTOR);
3457 return 1;
3458}
3459
ec25d5e6
GN		 3460static int handle_invd(struct kvm_vcpu *vcpu)
3461{
51d8b661 3462 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 3463}
3464
851ba692 3465static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3466{
f9c617f6 3467 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3468
3469 kvm_mmu_invlpg(vcpu, exit_qualification);
3470 skip_emulated_instruction(vcpu);
3471 return 1;
3472}
3473
851ba692 3474static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3475{
3476 skip_emulated_instruction(vcpu);
f5f48ee1 3477 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3478 return 1;
3479}
3480
2acf923e
DC		 3481static int handle_xsetbv(struct kvm_vcpu *vcpu)
3482{
3483 u64 new_bv = kvm_read_edx_eax(vcpu);
3484 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3485
3486 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3487 skip_emulated_instruction(vcpu);
3488 return 1;
3489}
3490
851ba692 3491static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3492{
51d8b661 3493 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 3494}
3495
851ba692 3496static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3497{
60637aac 3498 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3499 unsigned long exit_qualification;
e269fb21
JK		 3500 bool has_error_code = false;
3501 u32 error_code = 0;
37817f29 3502 u16 tss_selector;
64a7ec06
GN		 3503 int reason, type, idt_v;
3504
3505 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3506 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3507
3508 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3509
3510 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3511 if (reason == TASK_SWITCH_GATE && idt_v) {
3512 switch (type) {
3513 case INTR_TYPE_NMI_INTR:
3514 vcpu->arch.nmi_injected = false;
3515 if (cpu_has_virtual_nmis())
3516 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3517 GUEST_INTR_STATE_NMI);
3518 break;
3519 case INTR_TYPE_EXT_INTR:
66fd3f7f 3520 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3521 kvm_clear_interrupt_queue(vcpu);
3522 break;
3523 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3524 if (vmx->idt_vectoring_info &
3525 VECTORING_INFO_DELIVER_CODE_MASK) {
3526 has_error_code = true;
3527 error_code =
3528 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3529 }
3530 /* fall through */
64a7ec06
GN		 3531 case INTR_TYPE_SOFT_EXCEPTION:
3532 kvm_clear_exception_queue(vcpu);
3533 break;
3534 default:
3535 break;
3536 }
60637aac 3537 }
37817f29
IE		 3538 tss_selector = exit_qualification;
3539
64a7ec06
GN		 3540 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3541 type != INTR_TYPE_EXT_INTR &&
3542 type != INTR_TYPE_NMI_INTR))
3543 skip_emulated_instruction(vcpu);
3544
acb54517
GN		 3545 if (kvm_task_switch(vcpu, tss_selector, reason,
3546 has_error_code, error_code) == EMULATE_FAIL) {
3547 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3548 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3549 vcpu->run->internal.ndata = 0;
42dbaa5a 3550 return 0;
acb54517 3551 }
42dbaa5a
JK		 3552
3553 /* clear all local breakpoint enable flags */
3554 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3555
3556 /*
3557 * TODO: What about debug traps on tss switch?
3558 * Are we supposed to inject them and update dr6?
3559 */
3560
3561 return 1;
37817f29
IE		 3562}
3563
851ba692 3564static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3565{
f9c617f6 3566 unsigned long exit_qualification;
1439442c 3567 gpa_t gpa;
1439442c 3568 int gla_validity;
1439442c 3569
f9c617f6 3570 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3571
3572 if (exit_qualification & (1 << 6)) {
3573 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3574 return -EINVAL;
1439442c
SY		 3575 }
3576
3577 gla_validity = (exit_qualification >> 7) & 0x3;
3578 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3579 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3580 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3581 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3582 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3583 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3584 (long unsigned int)exit_qualification);
851ba692
AK		 3585 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3586 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3587 return 0;
1439442c
SY		 3588 }
3589
3590 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3591 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 3592 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 3593}
3594
68f89400
MT		 3595static u64 ept_rsvd_mask(u64 spte, int level)
3596{
3597 int i;
3598 u64 mask = 0;
3599
3600 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3601 mask |= (1ULL << i);
3602
3603 if (level > 2)
3604 /* bits 7:3 reserved */
3605 mask |= 0xf8;
3606 else if (level == 2) {
3607 if (spte & (1ULL << 7))
3608 /* 2MB ref, bits 20:12 reserved */
3609 mask |= 0x1ff000;
3610 else
3611 /* bits 6:3 reserved */
3612 mask |= 0x78;
3613 }
3614
3615 return mask;
3616}
3617
3618static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3619 int level)
3620{
3621 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3622
3623 /* 010b (write-only) */
3624 WARN_ON((spte & 0x7) == 0x2);
3625
3626 /* 110b (write/execute) */
3627 WARN_ON((spte & 0x7) == 0x6);
3628
3629 /* 100b (execute-only) and value not supported by logical processor */
3630 if (!cpu_has_vmx_ept_execute_only())
3631 WARN_ON((spte & 0x7) == 0x4);
3632
3633 /* not 000b */
3634 if ((spte & 0x7)) {
3635 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3636
3637 if (rsvd_bits != 0) {
3638 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3639 __func__, rsvd_bits);
3640 WARN_ON(1);
3641 }
3642
3643 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3644 u64 ept_mem_type = (spte & 0x38) >> 3;
3645
3646 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3647 ept_mem_type == 7) {
3648 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3649 __func__, ept_mem_type);
3650 WARN_ON(1);
3651 }
3652 }
3653 }
3654}
3655
851ba692 3656static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3657{
3658 u64 sptes[4];
3659 int nr_sptes, i;
3660 gpa_t gpa;
3661
3662 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3663
3664 printk(KERN_ERR "EPT: Misconfiguration.\n");
3665 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3666
3667 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3668
3669 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3670 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3671
851ba692
AK		 3672 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3673 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3674
3675 return 0;
3676}
3677
851ba692 3678static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3679{
3680 u32 cpu_based_vm_exec_control;
3681
3682 /* clear pending NMI */
3683 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3684 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3685 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3686 ++vcpu->stat.nmi_window_exits;
3842d135 3687 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 3688
3689 return 1;
3690}
3691
80ced186 3692static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3693{
8b3079a5
AK		 3694 struct vcpu_vmx *vmx = to_vmx(vcpu);
3695 enum emulation_result err = EMULATE_DONE;
80ced186 3696 int ret = 1;
49e9d557
AK		 3697 u32 cpu_exec_ctrl;
3698 bool intr_window_requested;
3699
3700 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3701 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 3702
3703 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 3704 if (intr_window_requested
3705 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3706 return handle_interrupt_window(&vmx->vcpu);
3707
51d8b661 3708 err = emulate_instruction(vcpu, 0);
ea953ef0 3709
80ced186
MG		 3710 if (err == EMULATE_DO_MMIO) {
3711 ret = 0;
3712 goto out;
3713 }
1d5a4d9b 3714
6d77dbfc
GN		 3715 if (err != EMULATE_DONE)
3716 return 0;
ea953ef0
MG		 3717
3718 if (signal_pending(current))
80ced186 3719 goto out;
ea953ef0
MG		 3720 if (need_resched())
3721 schedule();
3722 }
3723
80ced186
MG		 3724 vmx->emulation_required = 0;
3725out:
3726 return ret;
ea953ef0
MG		 3727}
3728
4b8d54f9
ZE		 3729/*
3730 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3731 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3732 */
9fb41ba8 3733static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3734{
3735 skip_emulated_instruction(vcpu);
3736 kvm_vcpu_on_spin(vcpu);
3737
3738 return 1;
3739}
3740
59708670
SY		 3741static int handle_invalid_op(struct kvm_vcpu *vcpu)
3742{
3743 kvm_queue_exception(vcpu, UD_VECTOR);
3744 return 1;
3745}
3746
6aa8b732
AK		 3747/*
3748 * The exit handlers return 1 if the exit was handled fully and guest execution
3749 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3750 * to be done to userspace and return 0.
3751 */
851ba692 3752static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3753 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3754 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3755 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3756 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3757 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3758 [EXIT_REASON_CR_ACCESS] = handle_cr,
3759 [EXIT_REASON_DR_ACCESS] = handle_dr,
3760 [EXIT_REASON_CPUID] = handle_cpuid,
3761 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3762 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3763 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3764 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 3765 [EXIT_REASON_INVD] = handle_invd,
a7052897 3766 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3767 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3768 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3769 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3770 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3771 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3772 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3773 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3774 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3775 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3776 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3777 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3778 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3779 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3780 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3781 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3782 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3783 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3784 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3785 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3786 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3787 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3788};
3789
3790static const int kvm_vmx_max_exit_handlers =
50a3485c 3791 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 3792
586f9607
AK		 3793static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3794{
3795 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3796 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3797}
3798
6aa8b732
AK		 3799/*
3800 * The guest has exited. See if we can fix it or if we need userspace
3801 * assistance.
3802 */
851ba692 3803static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3804{
29bd8a78 3805 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3806 u32 exit_reason = vmx->exit_reason;
1155f76a 3807 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3808
aa17911e 3809 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 3810
80ced186
MG		 3811 /* If guest state is invalid, start emulating */
3812 if (vmx->emulation_required && emulate_invalid_guest_state)
3813 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3814
5120702e
MG		 3815 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3816 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3817 vcpu->run->fail_entry.hardware_entry_failure_reason
3818 = exit_reason;
3819 return 0;
3820 }
3821
29bd8a78 3822 if (unlikely(vmx->fail)) {
851ba692
AK		 3823 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3824 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3825 = vmcs_read32(VM_INSTRUCTION_ERROR);
3826 return 0;
3827 }
6aa8b732 3828
d77c26fc 3829 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3830 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3831 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3832 exit_reason != EXIT_REASON_TASK_SWITCH))
3833 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3834 "(0x%x) and exit reason is 0x%x\n",
3835 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3836
3837 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3838 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3839 vmx->soft_vnmi_blocked = 0;
3b86cd99 3840 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3841 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3842 /*
3843 * This CPU don't support us in finding the end of an
3844 * NMI-blocked window if the guest runs with IRQs
3845 * disabled. So we pull the trigger after 1 s of
3846 * futile waiting, but inform the user about this.
3847 */
3848 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3849 "state on VCPU %d after 1 s timeout\n",
3850 __func__, vcpu->vcpu_id);
3851 vmx->soft_vnmi_blocked = 0;
3b86cd99 3852 }
3b86cd99
JK		 3853 }
3854
6aa8b732
AK		 3855 if (exit_reason < kvm_vmx_max_exit_handlers
3856 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3857 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3858 else {
851ba692
AK		 3859 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3860 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3861 }
3862 return 0;
3863}
3864
95ba8273 3865static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3866{
95ba8273 3867 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3868 vmcs_write32(TPR_THRESHOLD, 0);
3869 return;
3870 }
3871
95ba8273 3872 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3873}
3874
51aa01d1 3875static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 3876{
51aa01d1 3877 u32 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 3878
3879 /* Handle machine checks before interrupts are enabled */
3880 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3881 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3882 && is_machine_check(exit_intr_info)))
3883 kvm_machine_check();
3884
20f65983
GN		 3885 /* We need to handle NMIs before interrupts are enabled */
3886 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3887 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3888 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3889 asm("int $2");
ff9d07a0
ZY		 3890 kvm_after_handle_nmi(&vmx->vcpu);
3891 }
51aa01d1 3892}
20f65983 3893
51aa01d1
AK		 3894static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3895{
3896 u32 exit_intr_info = vmx->exit_intr_info;
3897 bool unblock_nmi;
3898 u8 vector;
3899 bool idtv_info_valid;
3900
3901 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 3902
cf393f75
AK		 3903 if (cpu_has_virtual_nmis()) {
3904 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3905 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3906 /*
7b4a25cb 3907 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3908 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3909 * a guest IRET fault.
7b4a25cb
GN		 3910 * SDM 3: 23.2.2 (September 2008)
3911 * Bit 12 is undefined in any of the following cases:
3912 * If the VM exit sets the valid bit in the IDT-vectoring
3913 * information field.
3914 * If the VM exit is due to a double fault.
cf393f75 3915 */
7b4a25cb
GN		 3916 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3917 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3918 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3919 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3920 } else if (unlikely(vmx->soft_vnmi_blocked))
3921 vmx->vnmi_blocked_time +=
3922 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 3923}
3924
83422e17
AK		 3925static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3926 u32 idt_vectoring_info,
3927 int instr_len_field,
3928 int error_code_field)
51aa01d1 3929{
51aa01d1
AK		 3930 u8 vector;
3931 int type;
3932 bool idtv_info_valid;
3933
3934 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 3935
37b96e98
GN		 3936 vmx->vcpu.arch.nmi_injected = false;
3937 kvm_clear_exception_queue(&vmx->vcpu);
3938 kvm_clear_interrupt_queue(&vmx->vcpu);
3939
3940 if (!idtv_info_valid)
3941 return;
3942
3842d135
AK		 3943 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3944
668f612f
AK		 3945 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3946 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3947
64a7ec06 3948 switch (type) {
37b96e98
GN		 3949 case INTR_TYPE_NMI_INTR:
3950 vmx->vcpu.arch.nmi_injected = true;
668f612f 3951 /*
7b4a25cb 3952 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3953 * Clear bit "block by NMI" before VM entry if a NMI
3954 * delivery faulted.
668f612f 3955 */
37b96e98
GN		 3956 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3957 GUEST_INTR_STATE_NMI);
3958 break;
37b96e98 3959 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 3960 vmx->vcpu.arch.event_exit_inst_len =
83422e17 3961 vmcs_read32(instr_len_field);
66fd3f7f
GN		 3962 /* fall through */
3963 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3964 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 3965 u32 err = vmcs_read32(error_code_field);
37b96e98 3966 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3967 } else
3968 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3969 break;
66fd3f7f
GN		 3970 case INTR_TYPE_SOFT_INTR:
3971 vmx->vcpu.arch.event_exit_inst_len =
83422e17 3972 vmcs_read32(instr_len_field);
66fd3f7f 3973 /* fall through */
37b96e98 3974 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3975 kvm_queue_interrupt(&vmx->vcpu, vector,
3976 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3977 break;
3978 default:
3979 break;
f7d9238f 3980 }
cf393f75
AK		 3981}
3982
83422e17
AK		 3983static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3984{
3985 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3986 VM_EXIT_INSTRUCTION_LEN,
3987 IDT_VECTORING_ERROR_CODE);
3988}
3989
b463a6f7
AK		 3990static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3991{
3992 __vmx_complete_interrupts(to_vmx(vcpu),
3993 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3994 VM_ENTRY_INSTRUCTION_LEN,
3995 VM_ENTRY_EXCEPTION_ERROR_CODE);
3996
3997 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3998}
3999
c801949d
AK		 4000#ifdef CONFIG_X86_64
4001#define R "r"
4002#define Q "q"
4003#else
4004#define R "e"
4005#define Q "l"
4006#endif
4007
a3b5ba49 4008static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 4009{
a2fa3e9f 4010 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b
AK		 4011
4012 /* Record the guest's net vcpu time for enforced NMI injections. */
4013 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4014 vmx->entry_time = ktime_get();
4015
4016 /* Don't enter VMX if guest state is invalid, let the exit handler
4017 start emulation until we arrive back to a valid state */
4018 if (vmx->emulation_required && emulate_invalid_guest_state)
4019 return;
4020
4021 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4022 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4023 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4024 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4025
4026 /* When single-stepping over STI and MOV SS, we must clear the
4027 * corresponding interruptibility bits in the guest state. Otherwise
4028 * vmentry fails as it then expects bit 14 (BS) in pending debug
4029 * exceptions being set, but that's not correct for the guest debugging
4030 * case. */
4031 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4032 vmx_set_interrupt_shadow(vcpu, 0);
4033
4034 asm(
6aa8b732 4035 /* Store host registers */
c801949d 4036 "push %%"R"dx; push %%"R"bp;"
40712fae 4037 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 4038 "push %%"R"cx \n\t"
313dbd49
AK		 4039 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4040 "je 1f \n\t"
4041 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 4042 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 4043 "1: \n\t"
d3edefc0
AK		 4044 /* Reload cr2 if changed */
4045 "mov %c[cr2](%0), %%"R"ax \n\t"
4046 "mov %%cr2, %%"R"dx \n\t"
4047 "cmp %%"R"ax, %%"R"dx \n\t"
4048 "je 2f \n\t"
4049 "mov %%"R"ax, %%cr2 \n\t"
4050 "2: \n\t"
6aa8b732 4051 /* Check if vmlaunch of vmresume is needed */
e08aa78a 4052 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 4053 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 4054 "mov %c[rax](%0), %%"R"ax \n\t"
4055 "mov %c[rbx](%0), %%"R"bx \n\t"
4056 "mov %c[rdx](%0), %%"R"dx \n\t"
4057 "mov %c[rsi](%0), %%"R"si \n\t"
4058 "mov %c[rdi](%0), %%"R"di \n\t"
4059 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 4060#ifdef CONFIG_X86_64
e08aa78a
AK		 4061 "mov %c[r8](%0), %%r8 \n\t"
4062 "mov %c[r9](%0), %%r9 \n\t"
4063 "mov %c[r10](%0), %%r10 \n\t"
4064 "mov %c[r11](%0), %%r11 \n\t"
4065 "mov %c[r12](%0), %%r12 \n\t"
4066 "mov %c[r13](%0), %%r13 \n\t"
4067 "mov %c[r14](%0), %%r14 \n\t"
4068 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 4069#endif
c801949d
AK		 4070 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4071
6aa8b732 4072 /* Enter guest mode */
cd2276a7 4073 "jne .Llaunched \n\t"
4ecac3fd 4074 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 4075 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 4076 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 4077 ".Lkvm_vmx_return: "
6aa8b732 4078 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 4079 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4080 "pop %0 \n\t"
c801949d
AK		 4081 "mov %%"R"ax, %c[rax](%0) \n\t"
4082 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 4083 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 4084 "mov %%"R"dx, %c[rdx](%0) \n\t"
4085 "mov %%"R"si, %c[rsi](%0) \n\t"
4086 "mov %%"R"di, %c[rdi](%0) \n\t"
4087 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 4088#ifdef CONFIG_X86_64
e08aa78a
AK		 4089 "mov %%r8, %c[r8](%0) \n\t"
4090 "mov %%r9, %c[r9](%0) \n\t"
4091 "mov %%r10, %c[r10](%0) \n\t"
4092 "mov %%r11, %c[r11](%0) \n\t"
4093 "mov %%r12, %c[r12](%0) \n\t"
4094 "mov %%r13, %c[r13](%0) \n\t"
4095 "mov %%r14, %c[r14](%0) \n\t"
4096 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 4097#endif
c801949d
AK		 4098 "mov %%cr2, %%"R"ax \n\t"
4099 "mov %%"R"ax, %c[cr2](%0) \n\t"
4100
1c696d0e 4101 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 4102 "setbe %c[fail](%0) \n\t"
4103 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4104 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4105 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 4106 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 4107 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4108 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4109 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4110 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4111 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4112 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4113 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4114#ifdef CONFIG_X86_64
ad312c7c
ZX		 4115 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4116 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4117 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4118 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4119 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4120 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4121 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4122 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4123#endif
40712fae
AK		 4124 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4125 [wordsize]"i"(sizeof(ulong))
c2036300 4126 : "cc", "memory"
07d6f555 4127 , R"ax", R"bx", R"di", R"si"
c2036300 4128#ifdef CONFIG_X86_64
c2036300
LV		 4129 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4130#endif
4131 );
6aa8b732 4132
6de4f3ad 4133 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 4134 | (1 << VCPU_EXREG_RFLAGS)
aff48baa
AK		 4135 | (1 << VCPU_EXREG_PDPTR)
4136 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 4137 vcpu->arch.regs_dirty = 0;
4138
1155f76a
AK		 4139 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4140
d77c26fc 4141 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4142 vmx->launched = 1;
1b6269db 4143
51aa01d1
AK		 4144 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4145 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4146
4147 vmx_complete_atomic_exit(vmx);
4148 vmx_recover_nmi_blocking(vmx);
cf393f75 4149 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4150}
4151
c801949d
AK		 4152#undef R
4153#undef Q
4154
6aa8b732
AK		 4155static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4156{
a2fa3e9f
GH		 4157 struct vcpu_vmx *vmx = to_vmx(vcpu);
4158
4159 if (vmx->vmcs) {
543e4243 4160 vcpu_clear(vmx);
a2fa3e9f
GH		 4161 free_vmcs(vmx->vmcs);
4162 vmx->vmcs = NULL;
6aa8b732
AK		 4163 }
4164}
4165
4166static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4167{
fb3f0f51
RR		 4168 struct vcpu_vmx *vmx = to_vmx(vcpu);
4169
cdbecfc3 4170 free_vpid(vmx);
6aa8b732 4171 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4172 kfree(vmx->guest_msrs);
4173 kvm_vcpu_uninit(vcpu);
a4770347 4174 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4175}
4176
4610c9cc
DX		 4177static inline void vmcs_init(struct vmcs *vmcs)
4178{
4179 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4180
4181 if (!vmm_exclusive)
4182 kvm_cpu_vmxon(phys_addr);
4183
4184 vmcs_clear(vmcs);
4185
4186 if (!vmm_exclusive)
4187 kvm_cpu_vmxoff();
4188}
4189
fb3f0f51 4190static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4191{
fb3f0f51 4192 int err;
c16f862d 4193 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4194 int cpu;
6aa8b732 4195
a2fa3e9f 4196 if (!vmx)
fb3f0f51
RR		 4197 return ERR_PTR(-ENOMEM);
4198
2384d2b3
SY		 4199 allocate_vpid(vmx);
4200
fb3f0f51
RR		 4201 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4202 if (err)
4203 goto free_vcpu;
965b58a5 4204
a2fa3e9f 4205 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4206 if (!vmx->guest_msrs) {
4207 err = -ENOMEM;
4208 goto uninit_vcpu;
4209 }
965b58a5 4210
a2fa3e9f
GH		 4211 vmx->vmcs = alloc_vmcs();
4212 if (!vmx->vmcs)
fb3f0f51 4213 goto free_msrs;
a2fa3e9f 4214
4610c9cc 4215 vmcs_init(vmx->vmcs);
a2fa3e9f 4216
15ad7146
AK		 4217 cpu = get_cpu();
4218 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 4219 vmx->vcpu.cpu = cpu;
8b9cf98c 4220 err = vmx_vcpu_setup(vmx);
fb3f0f51 4221 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4222 put_cpu();
fb3f0f51
RR		 4223 if (err)
4224 goto free_vmcs;
5e4a0b3c
MT		 4225 if (vm_need_virtualize_apic_accesses(kvm))
4226 if (alloc_apic_access_page(kvm) != 0)
4227 goto free_vmcs;
fb3f0f51 4228
b927a3ce
SY		 4229 if (enable_ept) {
4230 if (!kvm->arch.ept_identity_map_addr)
4231 kvm->arch.ept_identity_map_addr =
4232 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 4233 err = -ENOMEM;
b7ebfb05
SY		 4234 if (alloc_identity_pagetable(kvm) != 0)
4235 goto free_vmcs;
93ea5388
GN		 4236 if (!init_rmode_identity_map(kvm))
4237 goto free_vmcs;
b927a3ce 4238 }
b7ebfb05 4239
fb3f0f51
RR		 4240 return &vmx->vcpu;
4241
4242free_vmcs:
4243 free_vmcs(vmx->vmcs);
4244free_msrs:
fb3f0f51
RR		 4245 kfree(vmx->guest_msrs);
4246uninit_vcpu:
4247 kvm_vcpu_uninit(&vmx->vcpu);
4248free_vcpu:
cdbecfc3 4249 free_vpid(vmx);
a4770347 4250 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4251 return ERR_PTR(err);
6aa8b732
AK		 4252}
4253
002c7f7c
YS		 4254static void __init vmx_check_processor_compat(void *rtn)
4255{
4256 struct vmcs_config vmcs_conf;
4257
4258 *(int *)rtn = 0;
4259 if (setup_vmcs_config(&vmcs_conf) < 0)
4260 *(int *)rtn = -EIO;
4261 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4262 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4263 smp_processor_id());
4264 *(int *)rtn = -EIO;
4265 }
4266}
4267
67253af5
SY		 4268static int get_ept_level(void)
4269{
4270 return VMX_EPT_DEFAULT_GAW + 1;
4271}
4272
4b12f0de 4273static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4274{
4b12f0de
SY		 4275 u64 ret;
4276
522c68c4
SY		 4277 /* For VT-d and EPT combination
4278 * 1. MMIO: always map as UC
4279 * 2. EPT with VT-d:
4280 * a. VT-d without snooping control feature: can't guarantee the
4281 * result, try to trust guest.
4282 * b. VT-d with snooping control feature: snooping control feature of
4283 * VT-d engine can guarantee the cache correctness. Just set it
4284 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4285 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4286 * consistent with host MTRR
4287 */
4b12f0de
SY		 4288 if (is_mmio)
4289 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4290 else if (vcpu->kvm->arch.iommu_domain &&
4291 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4292 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4293 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4294 else
522c68c4 4295 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4296 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4297
4298 return ret;
64d4d521
SY		 4299}
4300
f4c9e87c
AK		 4301#define _ER(x) { EXIT_REASON_##x, #x }
4302
229456fc 4303static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4304 _ER(EXCEPTION_NMI),
4305 _ER(EXTERNAL_INTERRUPT),
4306 _ER(TRIPLE_FAULT),
4307 _ER(PENDING_INTERRUPT),
4308 _ER(NMI_WINDOW),
4309 _ER(TASK_SWITCH),
4310 _ER(CPUID),
4311 _ER(HLT),
4312 _ER(INVLPG),
4313 _ER(RDPMC),
4314 _ER(RDTSC),
4315 _ER(VMCALL),
4316 _ER(VMCLEAR),
4317 _ER(VMLAUNCH),
4318 _ER(VMPTRLD),
4319 _ER(VMPTRST),
4320 _ER(VMREAD),
4321 _ER(VMRESUME),
4322 _ER(VMWRITE),
4323 _ER(VMOFF),
4324 _ER(VMON),
4325 _ER(CR_ACCESS),
4326 _ER(DR_ACCESS),
4327 _ER(IO_INSTRUCTION),
4328 _ER(MSR_READ),
4329 _ER(MSR_WRITE),
4330 _ER(MWAIT_INSTRUCTION),
4331 _ER(MONITOR_INSTRUCTION),
4332 _ER(PAUSE_INSTRUCTION),
4333 _ER(MCE_DURING_VMENTRY),
4334 _ER(TPR_BELOW_THRESHOLD),
4335 _ER(APIC_ACCESS),
4336 _ER(EPT_VIOLATION),
4337 _ER(EPT_MISCONFIG),
4338 _ER(WBINVD),
229456fc
MT		 4339 { -1, NULL }
4340};
4341
f4c9e87c
AK		 4342#undef _ER
4343
17cc3935 4344static int vmx_get_lpage_level(void)
344f414f 4345{
878403b7
SY		 4346 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4347 return PT_DIRECTORY_LEVEL;
4348 else
4349 /* For shadow and EPT supported 1GB page */
4350 return PT_PDPE_LEVEL;
344f414f
JR		 4351}
4352
0e851880
SY		 4353static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4354{
4e47c7a6
SY		 4355 struct kvm_cpuid_entry2 *best;
4356 struct vcpu_vmx *vmx = to_vmx(vcpu);
4357 u32 exec_control;
4358
4359 vmx->rdtscp_enabled = false;
4360 if (vmx_rdtscp_supported()) {
4361 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4362 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4363 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4364 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4365 vmx->rdtscp_enabled = true;
4366 else {
4367 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4368 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4369 exec_control);
4370 }
4371 }
4372 }
0e851880
SY		 4373}
4374
d4330ef2
JR		 4375static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4376{
4377}
4378
cbdd1bea 4379static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4380 .cpu_has_kvm_support = cpu_has_kvm_support,
4381 .disabled_by_bios = vmx_disabled_by_bios,
4382 .hardware_setup = hardware_setup,
4383 .hardware_unsetup = hardware_unsetup,
002c7f7c 4384 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4385 .hardware_enable = hardware_enable,
4386 .hardware_disable = hardware_disable,
04547156 4387 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4388
4389 .vcpu_create = vmx_create_vcpu,
4390 .vcpu_free = vmx_free_vcpu,
04d2cc77 4391 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4392
04d2cc77 4393 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4394 .vcpu_load = vmx_vcpu_load,
4395 .vcpu_put = vmx_vcpu_put,
4396
4397 .set_guest_debug = set_guest_debug,
4398 .get_msr = vmx_get_msr,
4399 .set_msr = vmx_set_msr,
4400 .get_segment_base = vmx_get_segment_base,
4401 .get_segment = vmx_get_segment,
4402 .set_segment = vmx_set_segment,
2e4d2653 4403 .get_cpl = vmx_get_cpl,
6aa8b732 4404 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4405 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 4406 .decache_cr3 = vmx_decache_cr3,
25c4c276 4407 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4408 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4409 .set_cr3 = vmx_set_cr3,
4410 .set_cr4 = vmx_set_cr4,
6aa8b732 4411 .set_efer = vmx_set_efer,
6aa8b732
AK		 4412 .get_idt = vmx_get_idt,
4413 .set_idt = vmx_set_idt,
4414 .get_gdt = vmx_get_gdt,
4415 .set_gdt = vmx_set_gdt,
020df079 4416 .set_dr7 = vmx_set_dr7,
5fdbf976 4417 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4418 .get_rflags = vmx_get_rflags,
4419 .set_rflags = vmx_set_rflags,
ebcbab4c 4420 .fpu_activate = vmx_fpu_activate,
02daab21 4421 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4422
4423 .tlb_flush = vmx_flush_tlb,
6aa8b732 4424
6aa8b732 4425 .run = vmx_vcpu_run,
6062d012 4426 .handle_exit = vmx_handle_exit,
6aa8b732 4427 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4428 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4429 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4430 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4431 .set_irq = vmx_inject_irq,
95ba8273 4432 .set_nmi = vmx_inject_nmi,
298101da 4433 .queue_exception = vmx_queue_exception,
b463a6f7 4434 .cancel_injection = vmx_cancel_injection,
78646121 4435 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4436 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4437 .get_nmi_mask = vmx_get_nmi_mask,
4438 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4439 .enable_nmi_window = enable_nmi_window,
4440 .enable_irq_window = enable_irq_window,
4441 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4442
cbc94022 4443 .set_tss_addr = vmx_set_tss_addr,
67253af5 4444 .get_tdp_level = get_ept_level,
4b12f0de 4445 .get_mt_mask = vmx_get_mt_mask,
229456fc 4446
586f9607 4447 .get_exit_info = vmx_get_exit_info,
229456fc 4448 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 4449
17cc3935 4450 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4451
4452 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4453
4454 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4455
4456 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4457
4458 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA		 4459
4460 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 4461 .adjust_tsc_offset = vmx_adjust_tsc_offset,
1c97f0a0
JR		 4462
4463 .set_tdp_cr3 = vmx_set_cr3,
6aa8b732
AK		 4464};
4465
4466static int __init vmx_init(void)
4467{
26bb0981
AK		 4468 int r, i;
4469
4470 rdmsrl_safe(MSR_EFER, &host_efer);
4471
4472 for (i = 0; i < NR_VMX_MSR; ++i)
4473 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4474
3e7c73e9 4475 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4476 if (!vmx_io_bitmap_a)
4477 return -ENOMEM;
4478
3e7c73e9 4479 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4480 if (!vmx_io_bitmap_b) {
4481 r = -ENOMEM;
4482 goto out;
4483 }
4484
5897297b
AK		 4485 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4486 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4487 r = -ENOMEM;
4488 goto out1;
4489 }
4490
5897297b
AK		 4491 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4492 if (!vmx_msr_bitmap_longmode) {
4493 r = -ENOMEM;
4494 goto out2;
4495 }
4496
fdef3ad1
HQ		 4497 /*
4498 * Allow direct access to the PC debug port (it is often used for I/O
4499 * delays, but the vmexits simply slow things down).
4500 */
3e7c73e9
AK		 4501 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4502 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4503
3e7c73e9 4504 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4505
5897297b
AK		 4506 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4507 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4508
2384d2b3
SY		 4509 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4510
0ee75bea
AK		 4511 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4512 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4513 if (r)
5897297b 4514 goto out3;
25c5f225 4515
5897297b
AK		 4516 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4517 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4518 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4519 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4520 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4521 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4522
089d034e 4523 if (enable_ept) {
1439442c 4524 bypass_guest_pf = 0;
534e38b4 4525 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4526 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4527 kvm_enable_tdp();
4528 } else
4529 kvm_disable_tdp();
1439442c 4530
c7addb90
AK		 4531 if (bypass_guest_pf)
4532 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4533
fdef3ad1
HQ		 4534 return 0;
4535
5897297b
AK		 4536out3:
4537 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4538out2:
5897297b 4539 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4540out1:
3e7c73e9 4541 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4542out:
3e7c73e9 4543 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4544 return r;
6aa8b732
AK		 4545}
4546
4547static void __exit vmx_exit(void)
4548{
5897297b
AK		 4549 free_page((unsigned long)vmx_msr_bitmap_legacy);
4550 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4551 free_page((unsigned long)vmx_io_bitmap_b);
4552 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4553
cb498ea2 4554 kvm_exit();
6aa8b732
AK		 4555}
4556
4557module_init(vmx_init)
4558module_exit(vmx_exit)
Ubuntu Artful kernel mirror