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KVM: VMX: Save and restore tr selector across mode switches
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
443381a8
AL		 72static int __read_mostly yield_on_hlt = 1;
73module_param(yield_on_hlt, bool, S_IRUGO);
74
cdc0e244
AK		 75#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77#define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 80 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 81#define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 83#define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
85 | X86_CR4_OSXMMEXCPT)
86
cdc0e244
AK		 87#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
89
78ac8b47
AK		 90#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
91
4b8d54f9
ZE		 92/*
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
96 * According to test, this time is usually small than 41 cycles.
97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
102 */
103#define KVM_VMX_DEFAULT_PLE_GAP 41
104#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
106module_param(ple_gap, int, S_IRUGO);
107
108static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
109module_param(ple_window, int, S_IRUGO);
110
61d2ef2c
AK		 111#define NR_AUTOLOAD_MSRS 1
112
a2fa3e9f
GH		 113struct vmcs {
114 u32 revision_id;
115 u32 abort;
116 char data[0];
117};
118
26bb0981
AK		 119struct shared_msr_entry {
120 unsigned index;
121 u64 data;
d5696725 122 u64 mask;
26bb0981
AK		 123};
124
a2fa3e9f 125struct vcpu_vmx {
fb3f0f51 126 struct kvm_vcpu vcpu;
543e4243 127 struct list_head local_vcpus_link;
313dbd49 128 unsigned long host_rsp;
a2fa3e9f 129 int launched;
29bd8a78 130 u8 fail;
51aa01d1 131 u32 exit_intr_info;
1155f76a 132 u32 idt_vectoring_info;
26bb0981 133 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 134 int nmsrs;
135 int save_nmsrs;
a2fa3e9f 136#ifdef CONFIG_X86_64
44ea2b17
AK		 137 u64 msr_host_kernel_gs_base;
138 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 139#endif
140 struct vmcs *vmcs;
61d2ef2c
AK		 141 struct msr_autoload {
142 unsigned nr;
143 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
144 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
145 } msr_autoload;
a2fa3e9f
GH		 146 struct {
147 int loaded;
148 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 149 int gs_ldt_reload_needed;
150 int fs_reload_needed;
d77c26fc 151 } host_state;
9c8cba37 152 struct {
7ffd92c5 153 int vm86_active;
78ac8b47 154 ulong save_rflags;
7ffd92c5
AK		 155 struct kvm_save_segment {
156 u16 selector;
157 unsigned long base;
158 u32 limit;
159 u32 ar;
160 } tr, es, ds, fs, gs;
9c8cba37 161 } rmode;
2384d2b3 162 int vpid;
04fa4d32 163 bool emulation_required;
3b86cd99
JK		 164
165 /* Support for vnmi-less CPUs */
166 int soft_vnmi_blocked;
167 ktime_t entry_time;
168 s64 vnmi_blocked_time;
a0861c02 169 u32 exit_reason;
4e47c7a6
SY		 170
171 bool rdtscp_enabled;
a2fa3e9f
GH		 172};
173
174static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
175{
fb3f0f51 176 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 177}
178
b7ebfb05 179static int init_rmode(struct kvm *kvm);
4e1096d2 180static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 181static void kvm_cpu_vmxon(u64 addr);
182static void kvm_cpu_vmxoff(void);
aff48baa 183static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
75880a01 184
6aa8b732
AK		 185static DEFINE_PER_CPU(struct vmcs *, vmxarea);
186static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 187static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
3444d7da 188static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 189
3e7c73e9
AK		 190static unsigned long *vmx_io_bitmap_a;
191static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 192static unsigned long *vmx_msr_bitmap_legacy;
193static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 194
110312c8
AK		 195static bool cpu_has_load_ia32_efer;
196
2384d2b3
SY		 197static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
198static DEFINE_SPINLOCK(vmx_vpid_lock);
199
1c3d14fe 200static struct vmcs_config {
6aa8b732
AK		 201 int size;
202 int order;
203 u32 revision_id;
1c3d14fe
YS		 204 u32 pin_based_exec_ctrl;
205 u32 cpu_based_exec_ctrl;
f78e0e2e 206 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 207 u32 vmexit_ctrl;
208 u32 vmentry_ctrl;
209} vmcs_config;
6aa8b732 210
efff9e53 211static struct vmx_capability {
d56f546d
SY		 212 u32 ept;
213 u32 vpid;
214} vmx_capability;
215
6aa8b732
AK		 216#define VMX_SEGMENT_FIELD(seg) \
217 [VCPU_SREG_##seg] = { \
218 .selector = GUEST_##seg##_SELECTOR, \
219 .base = GUEST_##seg##_BASE, \
220 .limit = GUEST_##seg##_LIMIT, \
221 .ar_bytes = GUEST_##seg##_AR_BYTES, \
222 }
223
224static struct kvm_vmx_segment_field {
225 unsigned selector;
226 unsigned base;
227 unsigned limit;
228 unsigned ar_bytes;
229} kvm_vmx_segment_fields[] = {
230 VMX_SEGMENT_FIELD(CS),
231 VMX_SEGMENT_FIELD(DS),
232 VMX_SEGMENT_FIELD(ES),
233 VMX_SEGMENT_FIELD(FS),
234 VMX_SEGMENT_FIELD(GS),
235 VMX_SEGMENT_FIELD(SS),
236 VMX_SEGMENT_FIELD(TR),
237 VMX_SEGMENT_FIELD(LDTR),
238};
239
26bb0981
AK		 240static u64 host_efer;
241
6de4f3ad
AK		 242static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
243
4d56c8a7 244/*
8c06585d 245 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 246 * away by decrementing the array size.
247 */
6aa8b732 248static const u32 vmx_msr_index[] = {
05b3e0c2 249#ifdef CONFIG_X86_64
44ea2b17 250 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 251#endif
8c06585d 252 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 253};
9d8f549d 254#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 255
31299944 256static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 257{
258 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
259 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 260 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 261}
262
31299944 263static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 264{
265 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
266 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 267 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 268}
269
31299944 270static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 271{
272 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
273 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 274 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 275}
276
31299944 277static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 278{
279 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
280 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
281}
282
31299944 283static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 284{
285 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
286 INTR_INFO_VALID_MASK)) ==
287 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
288}
289
31299944 290static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 291{
04547156 292 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 293}
294
31299944 295static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 296{
04547156 297 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 298}
299
31299944 300static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 301{
04547156 302 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 303}
304
31299944 305static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 306{
04547156
SY		 307 return vmcs_config.cpu_based_exec_ctrl &
308 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 309}
310
774ead3a 311static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 312{
04547156
SY		 313 return vmcs_config.cpu_based_2nd_exec_ctrl &
314 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
315}
316
317static inline bool cpu_has_vmx_flexpriority(void)
318{
319 return cpu_has_vmx_tpr_shadow() &&
320 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 321}
322
e799794e
MT		 323static inline bool cpu_has_vmx_ept_execute_only(void)
324{
31299944 325 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 326}
327
328static inline bool cpu_has_vmx_eptp_uncacheable(void)
329{
31299944 330 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 331}
332
333static inline bool cpu_has_vmx_eptp_writeback(void)
334{
31299944 335 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 336}
337
338static inline bool cpu_has_vmx_ept_2m_page(void)
339{
31299944 340 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 341}
342
878403b7
SY		 343static inline bool cpu_has_vmx_ept_1g_page(void)
344{
31299944 345 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 346}
347
4bc9b982
SY		 348static inline bool cpu_has_vmx_ept_4levels(void)
349{
350 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
351}
352
31299944 353static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 354{
31299944 355 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 356}
357
31299944 358static inline bool cpu_has_vmx_invept_context(void)
d56f546d 359{
31299944 360 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 361}
362
31299944 363static inline bool cpu_has_vmx_invept_global(void)
d56f546d 364{
31299944 365 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 366}
367
518c8aee
GJ		 368static inline bool cpu_has_vmx_invvpid_single(void)
369{
370 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
371}
372
b9d762fa
GJ		 373static inline bool cpu_has_vmx_invvpid_global(void)
374{
375 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
376}
377
31299944 378static inline bool cpu_has_vmx_ept(void)
d56f546d 379{
04547156
SY		 380 return vmcs_config.cpu_based_2nd_exec_ctrl &
381 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 382}
383
31299944 384static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 385{
386 return vmcs_config.cpu_based_2nd_exec_ctrl &
387 SECONDARY_EXEC_UNRESTRICTED_GUEST;
388}
389
31299944 390static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 391{
392 return vmcs_config.cpu_based_2nd_exec_ctrl &
393 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
394}
395
31299944 396static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 397{
6d3e435e 398 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 399}
400
31299944 401static inline bool cpu_has_vmx_vpid(void)
2384d2b3 402{
04547156
SY		 403 return vmcs_config.cpu_based_2nd_exec_ctrl &
404 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 405}
406
31299944 407static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 408{
409 return vmcs_config.cpu_based_2nd_exec_ctrl &
410 SECONDARY_EXEC_RDTSCP;
411}
412
31299944 413static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 414{
415 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
416}
417
f5f48ee1
SY		 418static inline bool cpu_has_vmx_wbinvd_exit(void)
419{
420 return vmcs_config.cpu_based_2nd_exec_ctrl &
421 SECONDARY_EXEC_WBINVD_EXITING;
422}
423
04547156
SY		 424static inline bool report_flexpriority(void)
425{
426 return flexpriority_enabled;
427}
428
8b9cf98c 429static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 430{
431 int i;
432
a2fa3e9f 433 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 434 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 435 return i;
436 return -1;
437}
438
2384d2b3
SY		 439static inline void __invvpid(int ext, u16 vpid, gva_t gva)
440{
441 struct {
442 u64 vpid : 16;
443 u64 rsvd : 48;
444 u64 gva;
445 } operand = { vpid, 0, gva };
446
4ecac3fd 447 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 448 /* CF==1 or ZF==1 --> rc = -1 */
449 "; ja 1f ; ud2 ; 1:"
450 : : "a"(&operand), "c"(ext) : "cc", "memory");
451}
452
1439442c
SY		 453static inline void __invept(int ext, u64 eptp, gpa_t gpa)
454{
455 struct {
456 u64 eptp, gpa;
457 } operand = {eptp, gpa};
458
4ecac3fd 459 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 460 /* CF==1 or ZF==1 --> rc = -1 */
461 "; ja 1f ; ud2 ; 1:\n"
462 : : "a" (&operand), "c" (ext) : "cc", "memory");
463}
464
26bb0981 465static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 466{
467 int i;
468
8b9cf98c 469 i = __find_msr_index(vmx, msr);
a75beee6 470 if (i >= 0)
a2fa3e9f 471 return &vmx->guest_msrs[i];
8b6d44c7 472 return NULL;
7725f0ba
AK		 473}
474
6aa8b732
AK		 475static void vmcs_clear(struct vmcs *vmcs)
476{
477 u64 phys_addr = __pa(vmcs);
478 u8 error;
479
4ecac3fd 480 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 481 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 482 : "cc", "memory");
483 if (error)
484 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
485 vmcs, phys_addr);
486}
487
7725b894
DX		 488static void vmcs_load(struct vmcs *vmcs)
489{
490 u64 phys_addr = __pa(vmcs);
491 u8 error;
492
493 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 494 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 495 : "cc", "memory");
496 if (error)
497 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
498 vmcs, phys_addr);
499}
500
6aa8b732
AK		 501static void __vcpu_clear(void *arg)
502{
8b9cf98c 503 struct vcpu_vmx *vmx = arg;
d3b2c338 504 int cpu = raw_smp_processor_id();
6aa8b732 505
8b9cf98c 506 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 507 vmcs_clear(vmx->vmcs);
508 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 509 per_cpu(current_vmcs, cpu) = NULL;
543e4243
AK		 510 list_del(&vmx->local_vcpus_link);
511 vmx->vcpu.cpu = -1;
512 vmx->launched = 0;
6aa8b732
AK		 513}
514
8b9cf98c 515static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 516{
eae5ecb5
AK		 517 if (vmx->vcpu.cpu == -1)
518 return;
8691e5a8 519 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 520}
521
1760dd49 522static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 523{
524 if (vmx->vpid == 0)
525 return;
526
518c8aee
GJ		 527 if (cpu_has_vmx_invvpid_single())
528 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 529}
530
b9d762fa
GJ		 531static inline void vpid_sync_vcpu_global(void)
532{
533 if (cpu_has_vmx_invvpid_global())
534 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
535}
536
537static inline void vpid_sync_context(struct vcpu_vmx *vmx)
538{
539 if (cpu_has_vmx_invvpid_single())
1760dd49 540 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 541 else
542 vpid_sync_vcpu_global();
543}
544
1439442c
SY		 545static inline void ept_sync_global(void)
546{
547 if (cpu_has_vmx_invept_global())
548 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
549}
550
551static inline void ept_sync_context(u64 eptp)
552{
089d034e 553 if (enable_ept) {
1439442c
SY		 554 if (cpu_has_vmx_invept_context())
555 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
556 else
557 ept_sync_global();
558 }
559}
560
561static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
562{
089d034e 563 if (enable_ept) {
1439442c
SY		 564 if (cpu_has_vmx_invept_individual_addr())
565 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
566 eptp, gpa);
567 else
568 ept_sync_context(eptp);
569 }
570}
571
6aa8b732
AK		 572static unsigned long vmcs_readl(unsigned long field)
573{
a295673a 574 unsigned long value = 0;
6aa8b732 575
4ecac3fd 576 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
a295673a 577 : "+a"(value) : "d"(field) : "cc");
6aa8b732
AK		 578 return value;
579}
580
581static u16 vmcs_read16(unsigned long field)
582{
583 return vmcs_readl(field);
584}
585
586static u32 vmcs_read32(unsigned long field)
587{
588 return vmcs_readl(field);
589}
590
591static u64 vmcs_read64(unsigned long field)
592{
05b3e0c2 593#ifdef CONFIG_X86_64
6aa8b732
AK		 594 return vmcs_readl(field);
595#else
596 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
597#endif
598}
599
e52de1b8
AK		 600static noinline void vmwrite_error(unsigned long field, unsigned long value)
601{
602 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
603 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
604 dump_stack();
605}
606
6aa8b732
AK		 607static void vmcs_writel(unsigned long field, unsigned long value)
608{
609 u8 error;
610
4ecac3fd 611 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 612 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 613 if (unlikely(error))
614 vmwrite_error(field, value);
6aa8b732
AK		 615}
616
617static void vmcs_write16(unsigned long field, u16 value)
618{
619 vmcs_writel(field, value);
620}
621
622static void vmcs_write32(unsigned long field, u32 value)
623{
624 vmcs_writel(field, value);
625}
626
627static void vmcs_write64(unsigned long field, u64 value)
628{
6aa8b732 629 vmcs_writel(field, value);
7682f2d0 630#ifndef CONFIG_X86_64
6aa8b732
AK		 631 asm volatile ("");
632 vmcs_writel(field+1, value >> 32);
633#endif
634}
635
2ab455cc
AL		 636static void vmcs_clear_bits(unsigned long field, u32 mask)
637{
638 vmcs_writel(field, vmcs_readl(field) & ~mask);
639}
640
641static void vmcs_set_bits(unsigned long field, u32 mask)
642{
643 vmcs_writel(field, vmcs_readl(field) | mask);
644}
645
abd3f2d6
AK		 646static void update_exception_bitmap(struct kvm_vcpu *vcpu)
647{
648 u32 eb;
649
fd7373cc
JK		 650 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
651 (1u << NM_VECTOR) | (1u << DB_VECTOR);
652 if ((vcpu->guest_debug &
653 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
654 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
655 eb |= 1u << BP_VECTOR;
7ffd92c5 656 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 657 eb = ~0;
089d034e 658 if (enable_ept)
1439442c 659 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 660 if (vcpu->fpu_active)
661 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 662 vmcs_write32(EXCEPTION_BITMAP, eb);
663}
664
61d2ef2c
AK		 665static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
666{
667 unsigned i;
668 struct msr_autoload *m = &vmx->msr_autoload;
669
110312c8
AK		 670 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
671 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
672 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
673 return;
674 }
675
61d2ef2c
AK		 676 for (i = 0; i < m->nr; ++i)
677 if (m->guest[i].index == msr)
678 break;
679
680 if (i == m->nr)
681 return;
682 --m->nr;
683 m->guest[i] = m->guest[m->nr];
684 m->host[i] = m->host[m->nr];
685 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
686 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
687}
688
689static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
690 u64 guest_val, u64 host_val)
691{
692 unsigned i;
693 struct msr_autoload *m = &vmx->msr_autoload;
694
110312c8
AK		 695 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
696 vmcs_write64(GUEST_IA32_EFER, guest_val);
697 vmcs_write64(HOST_IA32_EFER, host_val);
698 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
699 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
700 return;
701 }
702
61d2ef2c
AK		 703 for (i = 0; i < m->nr; ++i)
704 if (m->guest[i].index == msr)
705 break;
706
707 if (i == m->nr) {
708 ++m->nr;
709 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
710 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
711 }
712
713 m->guest[i].index = msr;
714 m->guest[i].value = guest_val;
715 m->host[i].index = msr;
716 m->host[i].value = host_val;
717}
718
33ed6329
AK		 719static void reload_tss(void)
720{
33ed6329
AK		 721 /*
722 * VT restores TR but not its size. Useless.
723 */
d359192f 724 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 725 struct desc_struct *descs;
33ed6329 726
d359192f 727 descs = (void *)gdt->address;
33ed6329
AK		 728 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
729 load_TR_desc();
33ed6329
AK		 730}
731
92c0d900 732static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 733{
3a34a881 734 u64 guest_efer;
51c6cf66
AK		 735 u64 ignore_bits;
736
f6801dff 737 guest_efer = vmx->vcpu.arch.efer;
3a34a881 738
51c6cf66
AK		 739 /*
740 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
741 * outside long mode
742 */
743 ignore_bits = EFER_NX | EFER_SCE;
744#ifdef CONFIG_X86_64
745 ignore_bits |= EFER_LMA | EFER_LME;
746 /* SCE is meaningful only in long mode on Intel */
747 if (guest_efer & EFER_LMA)
748 ignore_bits &= ~(u64)EFER_SCE;
749#endif
51c6cf66
AK		 750 guest_efer &= ~ignore_bits;
751 guest_efer |= host_efer & ignore_bits;
26bb0981 752 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 753 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 754
755 clear_atomic_switch_msr(vmx, MSR_EFER);
756 /* On ept, can't emulate nx, and must switch nx atomically */
757 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
758 guest_efer = vmx->vcpu.arch.efer;
759 if (!(guest_efer & EFER_LMA))
760 guest_efer &= ~EFER_LME;
761 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
762 return false;
763 }
764
26bb0981 765 return true;
51c6cf66
AK		 766}
767
2d49ec72
GN		 768static unsigned long segment_base(u16 selector)
769{
d359192f 770 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 771 struct desc_struct *d;
772 unsigned long table_base;
773 unsigned long v;
774
775 if (!(selector & ~3))
776 return 0;
777
d359192f 778 table_base = gdt->address;
2d49ec72
GN		 779
780 if (selector & 4) { /* from ldt */
781 u16 ldt_selector = kvm_read_ldt();
782
783 if (!(ldt_selector & ~3))
784 return 0;
785
786 table_base = segment_base(ldt_selector);
787 }
788 d = (struct desc_struct *)(table_base + (selector & ~7));
789 v = get_desc_base(d);
790#ifdef CONFIG_X86_64
791 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
792 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
793#endif
794 return v;
795}
796
797static inline unsigned long kvm_read_tr_base(void)
798{
799 u16 tr;
800 asm("str %0" : "=g"(tr));
801 return segment_base(tr);
802}
803
04d2cc77 804static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 805{
04d2cc77 806 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 807 int i;
04d2cc77 808
a2fa3e9f 809 if (vmx->host_state.loaded)
33ed6329
AK		 810 return;
811
a2fa3e9f 812 vmx->host_state.loaded = 1;
33ed6329
AK		 813 /*
814 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
815 * allow segment selectors with cpl > 0 or ti == 1.
816 */
d6e88aec 817 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 818 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 819 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 820 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 821 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 822 vmx->host_state.fs_reload_needed = 0;
823 } else {
33ed6329 824 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 825 vmx->host_state.fs_reload_needed = 1;
33ed6329 826 }
9581d442 827 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 828 if (!(vmx->host_state.gs_sel & 7))
829 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 830 else {
831 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 832 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 833 }
834
835#ifdef CONFIG_X86_64
836 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
837 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
838#else
a2fa3e9f
GH		 839 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
840 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 841#endif
707c0874
AK		 842
843#ifdef CONFIG_X86_64
c8770e7b
AK		 844 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
845 if (is_long_mode(&vmx->vcpu))
44ea2b17 846 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 847#endif
26bb0981
AK		 848 for (i = 0; i < vmx->save_nmsrs; ++i)
849 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 850 vmx->guest_msrs[i].data,
851 vmx->guest_msrs[i].mask);
33ed6329
AK		 852}
853
a9b21b62 854static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 855{
a2fa3e9f 856 if (!vmx->host_state.loaded)
33ed6329
AK		 857 return;
858
e1beb1d3 859 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 860 vmx->host_state.loaded = 0;
c8770e7b
AK		 861#ifdef CONFIG_X86_64
862 if (is_long_mode(&vmx->vcpu))
863 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
864#endif
152d3f2f 865 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 866 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 867#ifdef CONFIG_X86_64
9581d442 868 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 869#else
870 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 871#endif
33ed6329 872 }
0a77fe4c
AK		 873 if (vmx->host_state.fs_reload_needed)
874 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 875 reload_tss();
44ea2b17 876#ifdef CONFIG_X86_64
c8770e7b 877 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 878#endif
1c11e713
AK		 879 if (current_thread_info()->status & TS_USEDFPU)
880 clts();
3444d7da 881 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 882}
883
a9b21b62
AK		 884static void vmx_load_host_state(struct vcpu_vmx *vmx)
885{
886 preempt_disable();
887 __vmx_load_host_state(vmx);
888 preempt_enable();
889}
890
6aa8b732
AK		 891/*
892 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
893 * vcpu mutex is already taken.
894 */
15ad7146 895static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 896{
a2fa3e9f 897 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 898 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 899
4610c9cc
DX		 900 if (!vmm_exclusive)
901 kvm_cpu_vmxon(phys_addr);
902 else if (vcpu->cpu != cpu)
8b9cf98c 903 vcpu_clear(vmx);
6aa8b732 904
a2fa3e9f 905 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 906 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 907 vmcs_load(vmx->vmcs);
6aa8b732
AK		 908 }
909
910 if (vcpu->cpu != cpu) {
d359192f 911 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 912 unsigned long sysenter_esp;
913
a8eeb04a 914 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be
DX		 915 local_irq_disable();
916 list_add(&vmx->local_vcpus_link,
917 &per_cpu(vcpus_on_cpu, cpu));
918 local_irq_enable();
919
6aa8b732
AK		 920 /*
921 * Linux uses per-cpu TSS and GDT, so set these when switching
922 * processors.
923 */
d6e88aec 924 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 925 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 926
927 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
928 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
929 }
6aa8b732
AK		 930}
931
932static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
933{
a9b21b62 934 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 935 if (!vmm_exclusive) {
b923e62e 936 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 937 kvm_cpu_vmxoff();
938 }
6aa8b732
AK		 939}
940
5fd86fcf
AK		 941static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
942{
81231c69
AK		 943 ulong cr0;
944
5fd86fcf
AK		 945 if (vcpu->fpu_active)
946 return;
947 vcpu->fpu_active = 1;
81231c69
AK		 948 cr0 = vmcs_readl(GUEST_CR0);
949 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
950 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
951 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 952 update_exception_bitmap(vcpu);
edcafe3c
AK		 953 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
954 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 955}
956
edcafe3c
AK		 957static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
958
5fd86fcf
AK		 959static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
960{
edcafe3c 961 vmx_decache_cr0_guest_bits(vcpu);
81231c69 962 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 963 update_exception_bitmap(vcpu);
edcafe3c
AK		 964 vcpu->arch.cr0_guest_owned_bits = 0;
965 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
966 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 967}
968
6aa8b732
AK		 969static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
970{
78ac8b47 971 unsigned long rflags, save_rflags;
345dcaa8
AK		 972
973 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 974 if (to_vmx(vcpu)->rmode.vm86_active) {
975 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
976 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
977 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
978 }
345dcaa8 979 return rflags;
6aa8b732
AK		 980}
981
982static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
983{
78ac8b47
AK		 984 if (to_vmx(vcpu)->rmode.vm86_active) {
985 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 986 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 987 }
6aa8b732
AK		 988 vmcs_writel(GUEST_RFLAGS, rflags);
989}
990
2809f5d2
GC		 991static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
992{
993 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
994 int ret = 0;
995
996 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 997 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 998 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 999 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1000
1001 return ret & mask;
1002}
1003
1004static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1005{
1006 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1007 u32 interruptibility = interruptibility_old;
1008
1009 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1010
48005f64 1011 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1012 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1013 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1014 interruptibility |= GUEST_INTR_STATE_STI;
1015
1016 if ((interruptibility != interruptibility_old))
1017 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1018}
1019
6aa8b732
AK		 1020static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1021{
1022 unsigned long rip;
6aa8b732 1023
5fdbf976 1024 rip = kvm_rip_read(vcpu);
6aa8b732 1025 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1026 kvm_rip_write(vcpu, rip);
6aa8b732 1027
2809f5d2
GC		 1028 /* skipping an emulated instruction also counts */
1029 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1030}
1031
443381a8
AL		 1032static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1033{
1034 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1035 * explicitly skip the instruction because if the HLT state is set, then
1036 * the instruction is already executing and RIP has already been
1037 * advanced. */
1038 if (!yield_on_hlt &&
1039 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1040 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1041}
1042
298101da 1043static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1044 bool has_error_code, u32 error_code,
1045 bool reinject)
298101da 1046{
77ab6db0 1047 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1048 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1049
8ab2d2e2 1050 if (has_error_code) {
77ab6db0 1051 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1052 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1053 }
77ab6db0 1054
7ffd92c5 1055 if (vmx->rmode.vm86_active) {
a92601bb
MG		 1056 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1057 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1058 return;
1059 }
1060
66fd3f7f
GN		 1061 if (kvm_exception_is_soft(nr)) {
1062 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1063 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1064 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1065 } else
1066 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1067
1068 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1069 vmx_clear_hlt(vcpu);
298101da
AK		 1070}
1071
4e47c7a6
SY		 1072static bool vmx_rdtscp_supported(void)
1073{
1074 return cpu_has_vmx_rdtscp();
1075}
1076
a75beee6
ED		 1077/*
1078 * Swap MSR entry in host/guest MSR entry array.
1079 */
8b9cf98c 1080static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1081{
26bb0981 1082 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1083
1084 tmp = vmx->guest_msrs[to];
1085 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1086 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1087}
1088
e38aea3e
AK		 1089/*
1090 * Set up the vmcs to automatically save and restore system
1091 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1092 * mode, as fiddling with msrs is very expensive.
1093 */
8b9cf98c 1094static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1095{
26bb0981 1096 int save_nmsrs, index;
5897297b 1097 unsigned long *msr_bitmap;
e38aea3e 1098
33f9c505 1099 vmx_load_host_state(vmx);
a75beee6
ED		 1100 save_nmsrs = 0;
1101#ifdef CONFIG_X86_64
8b9cf98c 1102 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1103 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1104 if (index >= 0)
8b9cf98c
RR		 1105 move_msr_up(vmx, index, save_nmsrs++);
1106 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1107 if (index >= 0)
8b9cf98c
RR		 1108 move_msr_up(vmx, index, save_nmsrs++);
1109 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1110 if (index >= 0)
8b9cf98c 1111 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1112 index = __find_msr_index(vmx, MSR_TSC_AUX);
1113 if (index >= 0 && vmx->rdtscp_enabled)
1114 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1115 /*
8c06585d 1116 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1117 * if efer.sce is enabled.
1118 */
8c06585d 1119 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1120 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1121 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1122 }
1123#endif
92c0d900
AK		 1124 index = __find_msr_index(vmx, MSR_EFER);
1125 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1126 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1127
26bb0981 1128 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1129
1130 if (cpu_has_vmx_msr_bitmap()) {
1131 if (is_long_mode(&vmx->vcpu))
1132 msr_bitmap = vmx_msr_bitmap_longmode;
1133 else
1134 msr_bitmap = vmx_msr_bitmap_legacy;
1135
1136 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1137 }
e38aea3e
AK		 1138}
1139
6aa8b732
AK		 1140/*
1141 * reads and returns guest's timestamp counter "register"
1142 * guest_tsc = host_tsc + tsc_offset -- 21.3
1143 */
1144static u64 guest_read_tsc(void)
1145{
1146 u64 host_tsc, tsc_offset;
1147
1148 rdtscll(host_tsc);
1149 tsc_offset = vmcs_read64(TSC_OFFSET);
1150 return host_tsc + tsc_offset;
1151}
1152
1153/*
99e3e30a 1154 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1155 */
99e3e30a 1156static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1157{
f4e1b3c8 1158 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1159}
1160
e48672fa
ZA		 1161static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1162{
1163 u64 offset = vmcs_read64(TSC_OFFSET);
1164 vmcs_write64(TSC_OFFSET, offset + adjustment);
1165}
1166
6aa8b732
AK		 1167/*
1168 * Reads an msr value (of 'msr_index') into 'pdata'.
1169 * Returns 0 on success, non-0 otherwise.
1170 * Assumes vcpu_load() was already called.
1171 */
1172static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1173{
1174 u64 data;
26bb0981 1175 struct shared_msr_entry *msr;
6aa8b732
AK		 1176
1177 if (!pdata) {
1178 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1179 return -EINVAL;
1180 }
1181
1182 switch (msr_index) {
05b3e0c2 1183#ifdef CONFIG_X86_64
6aa8b732
AK		 1184 case MSR_FS_BASE:
1185 data = vmcs_readl(GUEST_FS_BASE);
1186 break;
1187 case MSR_GS_BASE:
1188 data = vmcs_readl(GUEST_GS_BASE);
1189 break;
44ea2b17
AK		 1190 case MSR_KERNEL_GS_BASE:
1191 vmx_load_host_state(to_vmx(vcpu));
1192 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1193 break;
26bb0981 1194#endif
6aa8b732 1195 case MSR_EFER:
3bab1f5d 1196 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1197 case MSR_IA32_TSC:
6aa8b732
AK		 1198 data = guest_read_tsc();
1199 break;
1200 case MSR_IA32_SYSENTER_CS:
1201 data = vmcs_read32(GUEST_SYSENTER_CS);
1202 break;
1203 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1204 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1205 break;
1206 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1207 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1208 break;
4e47c7a6
SY		 1209 case MSR_TSC_AUX:
1210 if (!to_vmx(vcpu)->rdtscp_enabled)
1211 return 1;
1212 /* Otherwise falls through */
6aa8b732 1213 default:
26bb0981 1214 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1215 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1216 if (msr) {
542423b0 1217 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1218 data = msr->data;
1219 break;
6aa8b732 1220 }
3bab1f5d 1221 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1222 }
1223
1224 *pdata = data;
1225 return 0;
1226}
1227
1228/*
1229 * Writes msr value into into the appropriate "register".
1230 * Returns 0 on success, non-0 otherwise.
1231 * Assumes vcpu_load() was already called.
1232 */
1233static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1234{
a2fa3e9f 1235 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1236 struct shared_msr_entry *msr;
2cc51560
ED		 1237 int ret = 0;
1238
6aa8b732 1239 switch (msr_index) {
3bab1f5d 1240 case MSR_EFER:
a9b21b62 1241 vmx_load_host_state(vmx);
2cc51560 1242 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1243 break;
16175a79 1244#ifdef CONFIG_X86_64
6aa8b732
AK		 1245 case MSR_FS_BASE:
1246 vmcs_writel(GUEST_FS_BASE, data);
1247 break;
1248 case MSR_GS_BASE:
1249 vmcs_writel(GUEST_GS_BASE, data);
1250 break;
44ea2b17
AK		 1251 case MSR_KERNEL_GS_BASE:
1252 vmx_load_host_state(vmx);
1253 vmx->msr_guest_kernel_gs_base = data;
1254 break;
6aa8b732
AK		 1255#endif
1256 case MSR_IA32_SYSENTER_CS:
1257 vmcs_write32(GUEST_SYSENTER_CS, data);
1258 break;
1259 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1260 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1261 break;
1262 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1263 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1264 break;
af24a4e4 1265 case MSR_IA32_TSC:
99e3e30a 1266 kvm_write_tsc(vcpu, data);
6aa8b732 1267 break;
468d472f
SY		 1268 case MSR_IA32_CR_PAT:
1269 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1270 vmcs_write64(GUEST_IA32_PAT, data);
1271 vcpu->arch.pat = data;
1272 break;
1273 }
4e47c7a6
SY		 1274 ret = kvm_set_msr_common(vcpu, msr_index, data);
1275 break;
1276 case MSR_TSC_AUX:
1277 if (!vmx->rdtscp_enabled)
1278 return 1;
1279 /* Check reserved bit, higher 32 bits should be zero */
1280 if ((data >> 32) != 0)
1281 return 1;
1282 /* Otherwise falls through */
6aa8b732 1283 default:
8b9cf98c 1284 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1285 if (msr) {
542423b0 1286 vmx_load_host_state(vmx);
3bab1f5d
AK		 1287 msr->data = data;
1288 break;
6aa8b732 1289 }
2cc51560 1290 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1291 }
1292
2cc51560 1293 return ret;
6aa8b732
AK		 1294}
1295
5fdbf976 1296static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1297{
5fdbf976
MT		 1298 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1299 switch (reg) {
1300 case VCPU_REGS_RSP:
1301 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1302 break;
1303 case VCPU_REGS_RIP:
1304 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1305 break;
6de4f3ad
AK		 1306 case VCPU_EXREG_PDPTR:
1307 if (enable_ept)
1308 ept_save_pdptrs(vcpu);
1309 break;
5fdbf976
MT		 1310 default:
1311 break;
1312 }
6aa8b732
AK		 1313}
1314
355be0b9 1315static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1316{
ae675ef0
JK		 1317 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1318 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1319 else
1320 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1321
abd3f2d6 1322 update_exception_bitmap(vcpu);
6aa8b732
AK		 1323}
1324
1325static __init int cpu_has_kvm_support(void)
1326{
6210e37b 1327 return cpu_has_vmx();
6aa8b732
AK		 1328}
1329
1330static __init int vmx_disabled_by_bios(void)
1331{
1332 u64 msr;
1333
1334 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1335 if (msr & FEATURE_CONTROL_LOCKED) {
1336 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1337 && tboot_enabled())
1338 return 1;
1339 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
f9335afe
SW		 1340 && !tboot_enabled()) {
1341 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1342 " activate TXT before enabling KVM\n");
cafd6659 1343 return 1;
f9335afe 1344 }
cafd6659
SW		 1345 }
1346
1347 return 0;
62b3ffb8 1348 /* locked but not enabled */
6aa8b732
AK		 1349}
1350
7725b894
DX		 1351static void kvm_cpu_vmxon(u64 addr)
1352{
1353 asm volatile (ASM_VMX_VMXON_RAX
1354 : : "a"(&addr), "m"(addr)
1355 : "memory", "cc");
1356}
1357
10474ae8 1358static int hardware_enable(void *garbage)
6aa8b732
AK		 1359{
1360 int cpu = raw_smp_processor_id();
1361 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1362 u64 old, test_bits;
6aa8b732 1363
10474ae8
AG		 1364 if (read_cr4() & X86_CR4_VMXE)
1365 return -EBUSY;
1366
543e4243 1367 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1368 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1369
1370 test_bits = FEATURE_CONTROL_LOCKED;
1371 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1372 if (tboot_enabled())
1373 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1374
1375 if ((old & test_bits) != test_bits) {
6aa8b732 1376 /* enable and lock */
cafd6659
SW		 1377 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1378 }
66aee91a 1379 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1380
4610c9cc
DX		 1381 if (vmm_exclusive) {
1382 kvm_cpu_vmxon(phys_addr);
1383 ept_sync_global();
1384 }
10474ae8 1385
3444d7da
AK		 1386 store_gdt(&__get_cpu_var(host_gdt));
1387
10474ae8 1388 return 0;
6aa8b732
AK		 1389}
1390
543e4243
AK		 1391static void vmclear_local_vcpus(void)
1392{
1393 int cpu = raw_smp_processor_id();
1394 struct vcpu_vmx *vmx, *n;
1395
1396 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1397 local_vcpus_link)
1398 __vcpu_clear(vmx);
1399}
1400
710ff4a8
EH		 1401
1402/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1403 * tricks.
1404 */
1405static void kvm_cpu_vmxoff(void)
6aa8b732 1406{
4ecac3fd 1407 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1408}
1409
710ff4a8
EH		 1410static void hardware_disable(void *garbage)
1411{
4610c9cc
DX		 1412 if (vmm_exclusive) {
1413 vmclear_local_vcpus();
1414 kvm_cpu_vmxoff();
1415 }
7725b894 1416 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1417}
1418
1c3d14fe 1419static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1420 u32 msr, u32 *result)
1c3d14fe
YS		 1421{
1422 u32 vmx_msr_low, vmx_msr_high;
1423 u32 ctl = ctl_min | ctl_opt;
1424
1425 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1426
1427 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1428 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1429
1430 /* Ensure minimum (required) set of control bits are supported. */
1431 if (ctl_min & ~ctl)
002c7f7c 1432 return -EIO;
1c3d14fe
YS		 1433
1434 *result = ctl;
1435 return 0;
1436}
1437
110312c8
AK		 1438static __init bool allow_1_setting(u32 msr, u32 ctl)
1439{
1440 u32 vmx_msr_low, vmx_msr_high;
1441
1442 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1443 return vmx_msr_high & ctl;
1444}
1445
002c7f7c 1446static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1447{
1448 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1449 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1450 u32 _pin_based_exec_control = 0;
1451 u32 _cpu_based_exec_control = 0;
f78e0e2e 1452 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1453 u32 _vmexit_control = 0;
1454 u32 _vmentry_control = 0;
1455
1456 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1457 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1458 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1459 &_pin_based_exec_control) < 0)
002c7f7c 1460 return -EIO;
1c3d14fe 1461
443381a8 1462 min =
1c3d14fe
YS		 1463#ifdef CONFIG_X86_64
1464 CPU_BASED_CR8_LOAD_EXITING |
1465 CPU_BASED_CR8_STORE_EXITING |
1466#endif
d56f546d
SY		 1467 CPU_BASED_CR3_LOAD_EXITING |
1468 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1469 CPU_BASED_USE_IO_BITMAPS |
1470 CPU_BASED_MOV_DR_EXITING |
a7052897 1471 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1472 CPU_BASED_MWAIT_EXITING |
1473 CPU_BASED_MONITOR_EXITING |
a7052897 1474 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 1475
1476 if (yield_on_hlt)
1477 min |= CPU_BASED_HLT_EXITING;
1478
f78e0e2e 1479 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1480 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1481 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1482 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1483 &_cpu_based_exec_control) < 0)
002c7f7c 1484 return -EIO;
6e5d865c
YS		 1485#ifdef CONFIG_X86_64
1486 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1487 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1488 ~CPU_BASED_CR8_STORE_EXITING;
1489#endif
f78e0e2e 1490 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1491 min2 = 0;
1492 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1493 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1494 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1495 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1496 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1497 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1498 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1499 if (adjust_vmx_controls(min2, opt2,
1500 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1501 &_cpu_based_2nd_exec_control) < 0)
1502 return -EIO;
1503 }
1504#ifndef CONFIG_X86_64
1505 if (!(_cpu_based_2nd_exec_control &
1506 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1507 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1508#endif
d56f546d 1509 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1510 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1511 enabled */
5fff7d27
GN		 1512 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1513 CPU_BASED_CR3_STORE_EXITING |
1514 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1515 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1516 vmx_capability.ept, vmx_capability.vpid);
1517 }
1c3d14fe
YS		 1518
1519 min = 0;
1520#ifdef CONFIG_X86_64
1521 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1522#endif
468d472f 1523 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1524 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1525 &_vmexit_control) < 0)
002c7f7c 1526 return -EIO;
1c3d14fe 1527
468d472f
SY		 1528 min = 0;
1529 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1530 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1531 &_vmentry_control) < 0)
002c7f7c 1532 return -EIO;
6aa8b732 1533
c68876fd 1534 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1535
1536 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1537 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1538 return -EIO;
1c3d14fe
YS		 1539
1540#ifdef CONFIG_X86_64
1541 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1542 if (vmx_msr_high & (1u<<16))
002c7f7c 1543 return -EIO;
1c3d14fe
YS		 1544#endif
1545
1546 /* Require Write-Back (WB) memory type for VMCS accesses. */
1547 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1548 return -EIO;
1c3d14fe 1549
002c7f7c
YS		 1550 vmcs_conf->size = vmx_msr_high & 0x1fff;
1551 vmcs_conf->order = get_order(vmcs_config.size);
1552 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1553
002c7f7c
YS		 1554 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1555 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1556 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1557 vmcs_conf->vmexit_ctrl = _vmexit_control;
1558 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 1559
110312c8
AK		 1560 cpu_has_load_ia32_efer =
1561 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1562 VM_ENTRY_LOAD_IA32_EFER)
1563 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1564 VM_EXIT_LOAD_IA32_EFER);
1565
1c3d14fe 1566 return 0;
c68876fd 1567}
6aa8b732
AK		 1568
1569static struct vmcs *alloc_vmcs_cpu(int cpu)
1570{
1571 int node = cpu_to_node(cpu);
1572 struct page *pages;
1573 struct vmcs *vmcs;
1574
6484eb3e 1575 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1576 if (!pages)
1577 return NULL;
1578 vmcs = page_address(pages);
1c3d14fe
YS		 1579 memset(vmcs, 0, vmcs_config.size);
1580 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1581 return vmcs;
1582}
1583
1584static struct vmcs *alloc_vmcs(void)
1585{
d3b2c338 1586 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1587}
1588
1589static void free_vmcs(struct vmcs *vmcs)
1590{
1c3d14fe 1591 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1592}
1593
39959588 1594static void free_kvm_area(void)
6aa8b732
AK		 1595{
1596 int cpu;
1597
3230bb47 1598 for_each_possible_cpu(cpu) {
6aa8b732 1599 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1600 per_cpu(vmxarea, cpu) = NULL;
1601 }
6aa8b732
AK		 1602}
1603
6aa8b732
AK		 1604static __init int alloc_kvm_area(void)
1605{
1606 int cpu;
1607
3230bb47 1608 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1609 struct vmcs *vmcs;
1610
1611 vmcs = alloc_vmcs_cpu(cpu);
1612 if (!vmcs) {
1613 free_kvm_area();
1614 return -ENOMEM;
1615 }
1616
1617 per_cpu(vmxarea, cpu) = vmcs;
1618 }
1619 return 0;
1620}
1621
1622static __init int hardware_setup(void)
1623{
002c7f7c
YS		 1624 if (setup_vmcs_config(&vmcs_config) < 0)
1625 return -EIO;
50a37eb4
JR		 1626
1627 if (boot_cpu_has(X86_FEATURE_NX))
1628 kvm_enable_efer_bits(EFER_NX);
1629
93ba03c2
SY		 1630 if (!cpu_has_vmx_vpid())
1631 enable_vpid = 0;
1632
4bc9b982
SY		 1633 if (!cpu_has_vmx_ept() ||
1634 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1635 enable_ept = 0;
3a624e29
NK		 1636 enable_unrestricted_guest = 0;
1637 }
1638
1639 if (!cpu_has_vmx_unrestricted_guest())
1640 enable_unrestricted_guest = 0;
93ba03c2
SY		 1641
1642 if (!cpu_has_vmx_flexpriority())
1643 flexpriority_enabled = 0;
1644
95ba8273
GN		 1645 if (!cpu_has_vmx_tpr_shadow())
1646 kvm_x86_ops->update_cr8_intercept = NULL;
1647
54dee993
MT		 1648 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1649 kvm_disable_largepages();
1650
4b8d54f9
ZE		 1651 if (!cpu_has_vmx_ple())
1652 ple_gap = 0;
1653
6aa8b732
AK		 1654 return alloc_kvm_area();
1655}
1656
1657static __exit void hardware_unsetup(void)
1658{
1659 free_kvm_area();
1660}
1661
6aa8b732
AK		 1662static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1663{
1664 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1665
6af11b9e 1666 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1667 vmcs_write16(sf->selector, save->selector);
1668 vmcs_writel(sf->base, save->base);
1669 vmcs_write32(sf->limit, save->limit);
1670 vmcs_write32(sf->ar_bytes, save->ar);
1671 } else {
1672 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1673 << AR_DPL_SHIFT;
1674 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1675 }
1676}
1677
1678static void enter_pmode(struct kvm_vcpu *vcpu)
1679{
1680 unsigned long flags;
a89a8fb9 1681 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1682
a89a8fb9 1683 vmx->emulation_required = 1;
7ffd92c5 1684 vmx->rmode.vm86_active = 0;
6aa8b732 1685
d0ba64f9 1686 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 1687 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1688 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1689 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1690
1691 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1692 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1693 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1694 vmcs_writel(GUEST_RFLAGS, flags);
1695
66aee91a
RR		 1696 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1697 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1698
1699 update_exception_bitmap(vcpu);
1700
a89a8fb9
MG		 1701 if (emulate_invalid_guest_state)
1702 return;
1703
7ffd92c5
AK		 1704 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1705 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1706 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1707 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1708
1709 vmcs_write16(GUEST_SS_SELECTOR, 0);
1710 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1711
1712 vmcs_write16(GUEST_CS_SELECTOR,
1713 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1714 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1715}
1716
d77c26fc 1717static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1718{
bfc6d222 1719 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1720 struct kvm_memslots *slots;
1721 gfn_t base_gfn;
1722
90d83dc3 1723 slots = kvm_memslots(kvm);
f495c6e5 1724 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1725 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1726 return base_gfn << PAGE_SHIFT;
1727 }
bfc6d222 1728 return kvm->arch.tss_addr;
6aa8b732
AK		 1729}
1730
1731static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1732{
1733 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1734
1735 save->selector = vmcs_read16(sf->selector);
1736 save->base = vmcs_readl(sf->base);
1737 save->limit = vmcs_read32(sf->limit);
1738 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 1739 vmcs_write16(sf->selector, save->base >> 4);
444e863d 1740 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 1741 vmcs_write32(sf->limit, 0xffff);
1742 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 1743 if (save->base & 0xf)
1744 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1745 " aligned when entering protected mode (seg=%d)",
1746 seg);
6aa8b732
AK		 1747}
1748
1749static void enter_rmode(struct kvm_vcpu *vcpu)
1750{
1751 unsigned long flags;
a89a8fb9 1752 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1753
3a624e29
NK		 1754 if (enable_unrestricted_guest)
1755 return;
1756
a89a8fb9 1757 vmx->emulation_required = 1;
7ffd92c5 1758 vmx->rmode.vm86_active = 1;
6aa8b732 1759
d0ba64f9 1760 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 1761 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1762 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1763
7ffd92c5 1764 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1765 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1766
7ffd92c5 1767 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1768 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1769
1770 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1771 vmx->rmode.save_rflags = flags;
6aa8b732 1772
053de044 1773 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1774
1775 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1776 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1777 update_exception_bitmap(vcpu);
1778
a89a8fb9
MG		 1779 if (emulate_invalid_guest_state)
1780 goto continue_rmode;
1781
6aa8b732
AK		 1782 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1783 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1784 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1785
1786 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1787 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1788 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1789 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1790 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1791
7ffd92c5
AK		 1792 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1793 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1794 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1795 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1796
a89a8fb9 1797continue_rmode:
8668a3c4 1798 kvm_mmu_reset_context(vcpu);
b7ebfb05 1799 init_rmode(vcpu->kvm);
6aa8b732
AK		 1800}
1801
401d10de
AS		 1802static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1803{
1804 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1805 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1806
1807 if (!msr)
1808 return;
401d10de 1809
44ea2b17
AK		 1810 /*
1811 * Force kernel_gs_base reloading before EFER changes, as control
1812 * of this msr depends on is_long_mode().
1813 */
1814 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1815 vcpu->arch.efer = efer;
401d10de
AS		 1816 if (efer & EFER_LMA) {
1817 vmcs_write32(VM_ENTRY_CONTROLS,
1818 vmcs_read32(VM_ENTRY_CONTROLS) |
1819 VM_ENTRY_IA32E_MODE);
1820 msr->data = efer;
1821 } else {
1822 vmcs_write32(VM_ENTRY_CONTROLS,
1823 vmcs_read32(VM_ENTRY_CONTROLS) &
1824 ~VM_ENTRY_IA32E_MODE);
1825
1826 msr->data = efer & ~EFER_LME;
1827 }
1828 setup_msrs(vmx);
1829}
1830
05b3e0c2 1831#ifdef CONFIG_X86_64
6aa8b732
AK		 1832
1833static void enter_lmode(struct kvm_vcpu *vcpu)
1834{
1835 u32 guest_tr_ar;
1836
1837 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1838 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1839 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1840 __func__);
6aa8b732
AK		 1841 vmcs_write32(GUEST_TR_AR_BYTES,
1842 (guest_tr_ar & ~AR_TYPE_MASK)
1843 | AR_TYPE_BUSY_64_TSS);
1844 }
da38f438 1845 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1846}
1847
1848static void exit_lmode(struct kvm_vcpu *vcpu)
1849{
6aa8b732
AK		 1850 vmcs_write32(VM_ENTRY_CONTROLS,
1851 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1852 & ~VM_ENTRY_IA32E_MODE);
da38f438 1853 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1854}
1855
1856#endif
1857
2384d2b3
SY		 1858static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1859{
b9d762fa 1860 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 1861 if (enable_ept) {
1862 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1863 return;
4e1096d2 1864 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 1865 }
2384d2b3
SY		 1866}
1867
e8467fda
AK		 1868static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1869{
1870 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1871
1872 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1873 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1874}
1875
aff48baa
AK		 1876static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1877{
1878 if (enable_ept && is_paging(vcpu))
1879 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1880 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1881}
1882
25c4c276 1883static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1884{
fc78f519
AK		 1885 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1886
1887 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1888 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1889}
1890
1439442c
SY		 1891static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1892{
6de4f3ad
AK		 1893 if (!test_bit(VCPU_EXREG_PDPTR,
1894 (unsigned long *)&vcpu->arch.regs_dirty))
1895 return;
1896
1439442c 1897 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1898 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1899 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1900 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1901 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 1902 }
1903}
1904
8f5d549f
AK		 1905static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1906{
1907 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1908 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1909 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1910 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1911 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 1912 }
6de4f3ad
AK		 1913
1914 __set_bit(VCPU_EXREG_PDPTR,
1915 (unsigned long *)&vcpu->arch.regs_avail);
1916 __set_bit(VCPU_EXREG_PDPTR,
1917 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1918}
1919
1439442c
SY		 1920static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1921
1922static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1923 unsigned long cr0,
1924 struct kvm_vcpu *vcpu)
1925{
aff48baa 1926 vmx_decache_cr3(vcpu);
1439442c
SY		 1927 if (!(cr0 & X86_CR0_PG)) {
1928 /* From paging/starting to nonpaging */
1929 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1930 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1931 (CPU_BASED_CR3_LOAD_EXITING |
1932 CPU_BASED_CR3_STORE_EXITING));
1933 vcpu->arch.cr0 = cr0;
fc78f519 1934 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1935 } else if (!is_paging(vcpu)) {
1936 /* From nonpaging to paging */
1937 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1938 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1939 ~(CPU_BASED_CR3_LOAD_EXITING |
1940 CPU_BASED_CR3_STORE_EXITING));
1941 vcpu->arch.cr0 = cr0;
fc78f519 1942 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1943 }
95eb84a7
SY		 1944
1945 if (!(cr0 & X86_CR0_WP))
1946 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1947}
1948
6aa8b732
AK		 1949static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1950{
7ffd92c5 1951 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1952 unsigned long hw_cr0;
1953
1954 if (enable_unrestricted_guest)
1955 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1956 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1957 else
1958 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1959
7ffd92c5 1960 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1961 enter_pmode(vcpu);
1962
7ffd92c5 1963 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1964 enter_rmode(vcpu);
1965
05b3e0c2 1966#ifdef CONFIG_X86_64
f6801dff 1967 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1968 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1969 enter_lmode(vcpu);
707d92fa 1970 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1971 exit_lmode(vcpu);
1972 }
1973#endif
1974
089d034e 1975 if (enable_ept)
1439442c
SY		 1976 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1977
02daab21 1978 if (!vcpu->fpu_active)
81231c69 1979 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1980
6aa8b732 1981 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1982 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1983 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1984}
1985
1439442c
SY		 1986static u64 construct_eptp(unsigned long root_hpa)
1987{
1988 u64 eptp;
1989
1990 /* TODO write the value reading from MSR */
1991 eptp = VMX_EPT_DEFAULT_MT |
1992 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1993 eptp |= (root_hpa & PAGE_MASK);
1994
1995 return eptp;
1996}
1997
6aa8b732
AK		 1998static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1999{
1439442c
SY		 2000 unsigned long guest_cr3;
2001 u64 eptp;
2002
2003 guest_cr3 = cr3;
089d034e 2004 if (enable_ept) {
1439442c
SY		 2005 eptp = construct_eptp(cr3);
2006 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 2007 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 2008 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 2009 ept_load_pdptrs(vcpu);
1439442c
SY		 2010 }
2011
2384d2b3 2012 vmx_flush_tlb(vcpu);
1439442c 2013 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2014}
2015
2016static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2017{
7ffd92c5 2018 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2019 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2020
ad312c7c 2021 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2022 if (enable_ept) {
2023 if (!is_paging(vcpu)) {
2024 hw_cr4 &= ~X86_CR4_PAE;
2025 hw_cr4 |= X86_CR4_PSE;
2026 } else if (!(cr4 & X86_CR4_PAE)) {
2027 hw_cr4 &= ~X86_CR4_PAE;
2028 }
2029 }
1439442c
SY		 2030
2031 vmcs_writel(CR4_READ_SHADOW, cr4);
2032 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 2033}
2034
6aa8b732
AK		 2035static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2036{
2037 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2038
2039 return vmcs_readl(sf->base);
2040}
2041
2042static void vmx_get_segment(struct kvm_vcpu *vcpu,
2043 struct kvm_segment *var, int seg)
2044{
2045 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2046 u32 ar;
2047
2048 var->base = vmcs_readl(sf->base);
2049 var->limit = vmcs_read32(sf->limit);
2050 var->selector = vmcs_read16(sf->selector);
2051 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 2052 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2053 ar = 0;
2054 var->type = ar & 15;
2055 var->s = (ar >> 4) & 1;
2056 var->dpl = (ar >> 5) & 3;
2057 var->present = (ar >> 7) & 1;
2058 var->avl = (ar >> 12) & 1;
2059 var->l = (ar >> 13) & 1;
2060 var->db = (ar >> 14) & 1;
2061 var->g = (ar >> 15) & 1;
2062 var->unusable = (ar >> 16) & 1;
2063}
2064
2e4d2653
IE		 2065static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2066{
3eeb3288 2067 if (!is_protmode(vcpu))
2e4d2653
IE		 2068 return 0;
2069
2070 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2071 return 3;
2072
eab4b8aa 2073 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2074}
2075
653e3108 2076static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2077{
6aa8b732
AK		 2078 u32 ar;
2079
653e3108 2080 if (var->unusable)
6aa8b732
AK		 2081 ar = 1 << 16;
2082 else {
2083 ar = var->type & 15;
2084 ar |= (var->s & 1) << 4;
2085 ar |= (var->dpl & 3) << 5;
2086 ar |= (var->present & 1) << 7;
2087 ar |= (var->avl & 1) << 12;
2088 ar |= (var->l & 1) << 13;
2089 ar |= (var->db & 1) << 14;
2090 ar |= (var->g & 1) << 15;
2091 }
f7fbf1fd
UL		 2092 if (ar == 0) /* a 0 value means unusable */
2093 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2094
2095 return ar;
2096}
2097
2098static void vmx_set_segment(struct kvm_vcpu *vcpu,
2099 struct kvm_segment *var, int seg)
2100{
7ffd92c5 2101 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2102 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2103 u32 ar;
2104
7ffd92c5
AK		 2105 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2106 vmx->rmode.tr.selector = var->selector;
2107 vmx->rmode.tr.base = var->base;
2108 vmx->rmode.tr.limit = var->limit;
2109 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2110 return;
2111 }
2112 vmcs_writel(sf->base, var->base);
2113 vmcs_write32(sf->limit, var->limit);
2114 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2115 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2116 /*
2117 * Hack real-mode segments into vm86 compatibility.
2118 */
2119 if (var->base == 0xffff0000 && var->selector == 0xf000)
2120 vmcs_writel(sf->base, 0xf0000);
2121 ar = 0xf3;
2122 } else
2123 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2124
2125 /*
2126 * Fix the "Accessed" bit in AR field of segment registers for older
2127 * qemu binaries.
2128 * IA32 arch specifies that at the time of processor reset the
2129 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2130 * is setting it to 0 in the usedland code. This causes invalid guest
2131 * state vmexit when "unrestricted guest" mode is turned on.
2132 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2133 * tree. Newer qemu binaries with that qemu fix would not need this
2134 * kvm hack.
2135 */
2136 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2137 ar |= 0x1; /* Accessed */
2138
6aa8b732
AK		 2139 vmcs_write32(sf->ar_bytes, ar);
2140}
2141
6aa8b732
AK		 2142static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2143{
2144 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2145
2146 *db = (ar >> 14) & 1;
2147 *l = (ar >> 13) & 1;
2148}
2149
89a27f4d 2150static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2151{
89a27f4d
GN		 2152 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2153 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2154}
2155
89a27f4d 2156static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2157{
89a27f4d
GN		 2158 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2159 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2160}
2161
89a27f4d 2162static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2163{
89a27f4d
GN		 2164 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2165 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2166}
2167
89a27f4d 2168static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2169{
89a27f4d
GN		 2170 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2171 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2172}
2173
648dfaa7
MG		 2174static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2175{
2176 struct kvm_segment var;
2177 u32 ar;
2178
2179 vmx_get_segment(vcpu, &var, seg);
2180 ar = vmx_segment_access_rights(&var);
2181
2182 if (var.base != (var.selector << 4))
2183 return false;
2184 if (var.limit != 0xffff)
2185 return false;
2186 if (ar != 0xf3)
2187 return false;
2188
2189 return true;
2190}
2191
2192static bool code_segment_valid(struct kvm_vcpu *vcpu)
2193{
2194 struct kvm_segment cs;
2195 unsigned int cs_rpl;
2196
2197 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2198 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2199
1872a3f4
AK		 2200 if (cs.unusable)
2201 return false;
648dfaa7
MG		 2202 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2203 return false;
2204 if (!cs.s)
2205 return false;
1872a3f4 2206 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2207 if (cs.dpl > cs_rpl)
2208 return false;
1872a3f4 2209 } else {
648dfaa7
MG		 2210 if (cs.dpl != cs_rpl)
2211 return false;
2212 }
2213 if (!cs.present)
2214 return false;
2215
2216 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2217 return true;
2218}
2219
2220static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2221{
2222 struct kvm_segment ss;
2223 unsigned int ss_rpl;
2224
2225 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2226 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2227
1872a3f4
AK		 2228 if (ss.unusable)
2229 return true;
2230 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2231 return false;
2232 if (!ss.s)
2233 return false;
2234 if (ss.dpl != ss_rpl) /* DPL != RPL */
2235 return false;
2236 if (!ss.present)
2237 return false;
2238
2239 return true;
2240}
2241
2242static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2243{
2244 struct kvm_segment var;
2245 unsigned int rpl;
2246
2247 vmx_get_segment(vcpu, &var, seg);
2248 rpl = var.selector & SELECTOR_RPL_MASK;
2249
1872a3f4
AK		 2250 if (var.unusable)
2251 return true;
648dfaa7
MG		 2252 if (!var.s)
2253 return false;
2254 if (!var.present)
2255 return false;
2256 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2257 if (var.dpl < rpl) /* DPL < RPL */
2258 return false;
2259 }
2260
2261 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2262 * rights flags
2263 */
2264 return true;
2265}
2266
2267static bool tr_valid(struct kvm_vcpu *vcpu)
2268{
2269 struct kvm_segment tr;
2270
2271 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2272
1872a3f4
AK		 2273 if (tr.unusable)
2274 return false;
648dfaa7
MG		 2275 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2276 return false;
1872a3f4 2277 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2278 return false;
2279 if (!tr.present)
2280 return false;
2281
2282 return true;
2283}
2284
2285static bool ldtr_valid(struct kvm_vcpu *vcpu)
2286{
2287 struct kvm_segment ldtr;
2288
2289 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2290
1872a3f4
AK		 2291 if (ldtr.unusable)
2292 return true;
648dfaa7
MG		 2293 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2294 return false;
2295 if (ldtr.type != 2)
2296 return false;
2297 if (!ldtr.present)
2298 return false;
2299
2300 return true;
2301}
2302
2303static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2304{
2305 struct kvm_segment cs, ss;
2306
2307 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2308 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2309
2310 return ((cs.selector & SELECTOR_RPL_MASK) ==
2311 (ss.selector & SELECTOR_RPL_MASK));
2312}
2313
2314/*
2315 * Check if guest state is valid. Returns true if valid, false if
2316 * not.
2317 * We assume that registers are always usable
2318 */
2319static bool guest_state_valid(struct kvm_vcpu *vcpu)
2320{
2321 /* real mode guest state checks */
3eeb3288 2322 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2323 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2324 return false;
2325 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2326 return false;
2327 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2328 return false;
2329 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2330 return false;
2331 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2332 return false;
2333 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2334 return false;
2335 } else {
2336 /* protected mode guest state checks */
2337 if (!cs_ss_rpl_check(vcpu))
2338 return false;
2339 if (!code_segment_valid(vcpu))
2340 return false;
2341 if (!stack_segment_valid(vcpu))
2342 return false;
2343 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2344 return false;
2345 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2346 return false;
2347 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2348 return false;
2349 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2350 return false;
2351 if (!tr_valid(vcpu))
2352 return false;
2353 if (!ldtr_valid(vcpu))
2354 return false;
2355 }
2356 /* TODO:
2357 * - Add checks on RIP
2358 * - Add checks on RFLAGS
2359 */
2360
2361 return true;
2362}
2363
d77c26fc 2364static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2365{
6aa8b732 2366 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2367 u16 data = 0;
10589a46 2368 int ret = 0;
195aefde 2369 int r;
6aa8b732 2370
195aefde
IE		 2371 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2372 if (r < 0)
10589a46 2373 goto out;
195aefde 2374 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2375 r = kvm_write_guest_page(kvm, fn++, &data,
2376 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2377 if (r < 0)
10589a46 2378 goto out;
195aefde
IE		 2379 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2380 if (r < 0)
10589a46 2381 goto out;
195aefde
IE		 2382 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2383 if (r < 0)
10589a46 2384 goto out;
195aefde 2385 data = ~0;
10589a46
MT		 2386 r = kvm_write_guest_page(kvm, fn, &data,
2387 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2388 sizeof(u8));
195aefde 2389 if (r < 0)
10589a46
MT		 2390 goto out;
2391
2392 ret = 1;
2393out:
10589a46 2394 return ret;
6aa8b732
AK		 2395}
2396
b7ebfb05
SY		 2397static int init_rmode_identity_map(struct kvm *kvm)
2398{
2399 int i, r, ret;
2400 pfn_t identity_map_pfn;
2401 u32 tmp;
2402
089d034e 2403 if (!enable_ept)
b7ebfb05
SY		 2404 return 1;
2405 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2406 printk(KERN_ERR "EPT: identity-mapping pagetable "
2407 "haven't been allocated!\n");
2408 return 0;
2409 }
2410 if (likely(kvm->arch.ept_identity_pagetable_done))
2411 return 1;
2412 ret = 0;
b927a3ce 2413 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2414 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2415 if (r < 0)
2416 goto out;
2417 /* Set up identity-mapping pagetable for EPT in real mode */
2418 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2419 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2420 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2421 r = kvm_write_guest_page(kvm, identity_map_pfn,
2422 &tmp, i * sizeof(tmp), sizeof(tmp));
2423 if (r < 0)
2424 goto out;
2425 }
2426 kvm->arch.ept_identity_pagetable_done = true;
2427 ret = 1;
2428out:
2429 return ret;
2430}
2431
6aa8b732
AK		 2432static void seg_setup(int seg)
2433{
2434 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2435 unsigned int ar;
6aa8b732
AK		 2436
2437 vmcs_write16(sf->selector, 0);
2438 vmcs_writel(sf->base, 0);
2439 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2440 if (enable_unrestricted_guest) {
2441 ar = 0x93;
2442 if (seg == VCPU_SREG_CS)
2443 ar |= 0x08; /* code segment */
2444 } else
2445 ar = 0xf3;
2446
2447 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2448}
2449
f78e0e2e
SY		 2450static int alloc_apic_access_page(struct kvm *kvm)
2451{
2452 struct kvm_userspace_memory_region kvm_userspace_mem;
2453 int r = 0;
2454
79fac95e 2455 mutex_lock(&kvm->slots_lock);
bfc6d222 2456 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2457 goto out;
2458 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2459 kvm_userspace_mem.flags = 0;
2460 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2461 kvm_userspace_mem.memory_size = PAGE_SIZE;
2462 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2463 if (r)
2464 goto out;
72dc67a6 2465
bfc6d222 2466 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2467out:
79fac95e 2468 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2469 return r;
2470}
2471
b7ebfb05
SY		 2472static int alloc_identity_pagetable(struct kvm *kvm)
2473{
2474 struct kvm_userspace_memory_region kvm_userspace_mem;
2475 int r = 0;
2476
79fac95e 2477 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2478 if (kvm->arch.ept_identity_pagetable)
2479 goto out;
2480 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2481 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2482 kvm_userspace_mem.guest_phys_addr =
2483 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2484 kvm_userspace_mem.memory_size = PAGE_SIZE;
2485 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2486 if (r)
2487 goto out;
2488
b7ebfb05 2489 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2490 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2491out:
79fac95e 2492 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2493 return r;
2494}
2495
2384d2b3
SY		 2496static void allocate_vpid(struct vcpu_vmx *vmx)
2497{
2498 int vpid;
2499
2500 vmx->vpid = 0;
919818ab 2501 if (!enable_vpid)
2384d2b3
SY		 2502 return;
2503 spin_lock(&vmx_vpid_lock);
2504 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2505 if (vpid < VMX_NR_VPIDS) {
2506 vmx->vpid = vpid;
2507 __set_bit(vpid, vmx_vpid_bitmap);
2508 }
2509 spin_unlock(&vmx_vpid_lock);
2510}
2511
cdbecfc3
LJ		 2512static void free_vpid(struct vcpu_vmx *vmx)
2513{
2514 if (!enable_vpid)
2515 return;
2516 spin_lock(&vmx_vpid_lock);
2517 if (vmx->vpid != 0)
2518 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2519 spin_unlock(&vmx_vpid_lock);
2520}
2521
5897297b 2522static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2523{
3e7c73e9 2524 int f = sizeof(unsigned long);
25c5f225
SY		 2525
2526 if (!cpu_has_vmx_msr_bitmap())
2527 return;
2528
2529 /*
2530 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2531 * have the write-low and read-high bitmap offsets the wrong way round.
2532 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2533 */
25c5f225 2534 if (msr <= 0x1fff) {
3e7c73e9
AK		 2535 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2536 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2537 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2538 msr &= 0x1fff;
3e7c73e9
AK		 2539 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2540 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2541 }
25c5f225
SY		 2542}
2543
5897297b
AK		 2544static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2545{
2546 if (!longmode_only)
2547 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2548 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2549}
2550
6aa8b732
AK		 2551/*
2552 * Sets up the vmcs for emulated real mode.
2553 */
8b9cf98c 2554static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2555{
468d472f 2556 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2557 u32 junk;
f4e1b3c8 2558 u64 host_pat;
6aa8b732 2559 unsigned long a;
89a27f4d 2560 struct desc_ptr dt;
6aa8b732 2561 int i;
cd2276a7 2562 unsigned long kvm_vmx_return;
6e5d865c 2563 u32 exec_control;
6aa8b732 2564
6aa8b732 2565 /* I/O */
3e7c73e9
AK		 2566 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2567 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2568
25c5f225 2569 if (cpu_has_vmx_msr_bitmap())
5897297b 2570 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2571
6aa8b732
AK		 2572 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2573
6aa8b732 2574 /* Control */
1c3d14fe
YS		 2575 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2576 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2577
2578 exec_control = vmcs_config.cpu_based_exec_ctrl;
2579 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2580 exec_control &= ~CPU_BASED_TPR_SHADOW;
2581#ifdef CONFIG_X86_64
2582 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2583 CPU_BASED_CR8_LOAD_EXITING;
2584#endif
2585 }
089d034e 2586 if (!enable_ept)
d56f546d 2587 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2588 CPU_BASED_CR3_LOAD_EXITING |
2589 CPU_BASED_INVLPG_EXITING;
6e5d865c 2590 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2591
83ff3b9d
SY		 2592 if (cpu_has_secondary_exec_ctrls()) {
2593 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2594 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2595 exec_control &=
2596 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2597 if (vmx->vpid == 0)
2598 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2599 if (!enable_ept) {
d56f546d 2600 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2601 enable_unrestricted_guest = 0;
2602 }
3a624e29
NK		 2603 if (!enable_unrestricted_guest)
2604 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2605 if (!ple_gap)
2606 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2607 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2608 }
f78e0e2e 2609
4b8d54f9
ZE		 2610 if (ple_gap) {
2611 vmcs_write32(PLE_GAP, ple_gap);
2612 vmcs_write32(PLE_WINDOW, ple_window);
2613 }
2614
c7addb90
AK		 2615 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2616 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2617 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2618
1c11e713 2619 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2620 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2621 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2622
2623 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2624 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2625 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
9581d442
AK		 2626 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2627 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6aa8b732 2628 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2629#ifdef CONFIG_X86_64
6aa8b732
AK		 2630 rdmsrl(MSR_FS_BASE, a);
2631 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2632 rdmsrl(MSR_GS_BASE, a);
2633 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2634#else
2635 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2636 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2637#endif
2638
2639 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2640
ec68798c 2641 native_store_idt(&dt);
89a27f4d 2642 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2643
d77c26fc 2644 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2645 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2646 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2647 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2648 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2649 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2650 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2651
2652 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2653 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2654 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2655 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2656 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2657 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2658
468d472f
SY		 2659 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2660 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2661 host_pat = msr_low | ((u64) msr_high << 32);
2662 vmcs_write64(HOST_IA32_PAT, host_pat);
2663 }
2664 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2665 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2666 host_pat = msr_low | ((u64) msr_high << 32);
2667 /* Write the default value follow host pat */
2668 vmcs_write64(GUEST_IA32_PAT, host_pat);
2669 /* Keep arch.pat sync with GUEST_IA32_PAT */
2670 vmx->vcpu.arch.pat = host_pat;
2671 }
2672
6aa8b732
AK		 2673 for (i = 0; i < NR_VMX_MSR; ++i) {
2674 u32 index = vmx_msr_index[i];
2675 u32 data_low, data_high;
a2fa3e9f 2676 int j = vmx->nmsrs;
6aa8b732
AK		 2677
2678 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2679 continue;
432bd6cb
AK		 2680 if (wrmsr_safe(index, data_low, data_high) < 0)
2681 continue;
26bb0981
AK		 2682 vmx->guest_msrs[j].index = i;
2683 vmx->guest_msrs[j].data = 0;
d5696725 2684 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2685 ++vmx->nmsrs;
6aa8b732 2686 }
6aa8b732 2687
1c3d14fe 2688 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2689
2690 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2691 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2692
e00c8cf2 2693 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2694 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2695 if (enable_ept)
2696 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2697 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2698
99e3e30a 2699 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 2700
e00c8cf2
AK		 2701 return 0;
2702}
2703
b7ebfb05
SY		 2704static int init_rmode(struct kvm *kvm)
2705{
4b9d3a04
XG		 2706 int idx, ret = 0;
2707
2708 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05 2709 if (!init_rmode_tss(kvm))
4b9d3a04 2710 goto exit;
b7ebfb05 2711 if (!init_rmode_identity_map(kvm))
4b9d3a04
XG		 2712 goto exit;
2713
2714 ret = 1;
2715exit:
2716 srcu_read_unlock(&kvm->srcu, idx);
2717 return ret;
b7ebfb05
SY		 2718}
2719
e00c8cf2
AK		 2720static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2721{
2722 struct vcpu_vmx *vmx = to_vmx(vcpu);
2723 u64 msr;
4b9d3a04 2724 int ret;
e00c8cf2 2725
5fdbf976 2726 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
b7ebfb05 2727 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2728 ret = -ENOMEM;
2729 goto out;
2730 }
2731
7ffd92c5 2732 vmx->rmode.vm86_active = 0;
e00c8cf2 2733
3b86cd99
JK		 2734 vmx->soft_vnmi_blocked = 0;
2735
ad312c7c 2736 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2737 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2738 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2739 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2740 msr |= MSR_IA32_APICBASE_BSP;
2741 kvm_set_apic_base(&vmx->vcpu, msr);
2742
10ab25cd
JK		 2743 ret = fx_init(&vmx->vcpu);
2744 if (ret != 0)
2745 goto out;
e00c8cf2 2746
5706be0d 2747 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2748 /*
2749 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2750 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2751 */
c5af89b6 2752 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2753 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2754 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2755 } else {
ad312c7c
ZX		 2756 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2757 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2758 }
e00c8cf2
AK		 2759
2760 seg_setup(VCPU_SREG_DS);
2761 seg_setup(VCPU_SREG_ES);
2762 seg_setup(VCPU_SREG_FS);
2763 seg_setup(VCPU_SREG_GS);
2764 seg_setup(VCPU_SREG_SS);
2765
2766 vmcs_write16(GUEST_TR_SELECTOR, 0);
2767 vmcs_writel(GUEST_TR_BASE, 0);
2768 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2769 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2770
2771 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2772 vmcs_writel(GUEST_LDTR_BASE, 0);
2773 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2774 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2775
2776 vmcs_write32(GUEST_SYSENTER_CS, 0);
2777 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2778 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2779
2780 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2781 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2782 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2783 else
5fdbf976
MT		 2784 kvm_rip_write(vcpu, 0);
2785 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2786
e00c8cf2
AK		 2787 vmcs_writel(GUEST_DR7, 0x400);
2788
2789 vmcs_writel(GUEST_GDTR_BASE, 0);
2790 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2791
2792 vmcs_writel(GUEST_IDTR_BASE, 0);
2793 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2794
443381a8 2795 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 2796 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2797 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2798
e00c8cf2
AK		 2799 /* Special registers */
2800 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2801
2802 setup_msrs(vmx);
2803
6aa8b732
AK		 2804 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2805
f78e0e2e
SY		 2806 if (cpu_has_vmx_tpr_shadow()) {
2807 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2808 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2809 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2810 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2811 vmcs_write32(TPR_THRESHOLD, 0);
2812 }
2813
2814 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2815 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2816 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2817
2384d2b3
SY		 2818 if (vmx->vpid != 0)
2819 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2820
fa40052c 2821 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2822 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2823 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2824 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2825 vmx_fpu_activate(&vmx->vcpu);
2826 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2827
b9d762fa 2828 vpid_sync_context(vmx);
2384d2b3 2829
3200f405 2830 ret = 0;
6aa8b732 2831
a89a8fb9
MG		 2832 /* HACK: Don't enable emulation on guest boot/reset */
2833 vmx->emulation_required = 0;
2834
6aa8b732
AK		 2835out:
2836 return ret;
2837}
2838
3b86cd99
JK		 2839static void enable_irq_window(struct kvm_vcpu *vcpu)
2840{
2841 u32 cpu_based_vm_exec_control;
2842
2843 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2844 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2845 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2846}
2847
2848static void enable_nmi_window(struct kvm_vcpu *vcpu)
2849{
2850 u32 cpu_based_vm_exec_control;
2851
2852 if (!cpu_has_virtual_nmis()) {
2853 enable_irq_window(vcpu);
2854 return;
2855 }
2856
30bd0c4c
AK		 2857 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2858 enable_irq_window(vcpu);
2859 return;
2860 }
3b86cd99
JK		 2861 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2862 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2863 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2864}
2865
66fd3f7f 2866static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2867{
9c8cba37 2868 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2869 uint32_t intr;
2870 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2871
229456fc 2872 trace_kvm_inj_virq(irq);
2714d1d3 2873
fa89a817 2874 ++vcpu->stat.irq_injections;
7ffd92c5 2875 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2876 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2877 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 2878 return;
2879 }
66fd3f7f
GN		 2880 intr = irq | INTR_INFO_VALID_MASK;
2881 if (vcpu->arch.interrupt.soft) {
2882 intr |= INTR_TYPE_SOFT_INTR;
2883 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2884 vmx->vcpu.arch.event_exit_inst_len);
2885 } else
2886 intr |= INTR_TYPE_EXT_INTR;
2887 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 2888 vmx_clear_hlt(vcpu);
85f455f7
ED		 2889}
2890
f08864b4
SY		 2891static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2892{
66a5a347
JK		 2893 struct vcpu_vmx *vmx = to_vmx(vcpu);
2894
3b86cd99
JK		 2895 if (!cpu_has_virtual_nmis()) {
2896 /*
2897 * Tracking the NMI-blocked state in software is built upon
2898 * finding the next open IRQ window. This, in turn, depends on
2899 * well-behaving guests: They have to keep IRQs disabled at
2900 * least as long as the NMI handler runs. Otherwise we may
2901 * cause NMI nesting, maybe breaking the guest. But as this is
2902 * highly unlikely, we can live with the residual risk.
2903 */
2904 vmx->soft_vnmi_blocked = 1;
2905 vmx->vnmi_blocked_time = 0;
2906 }
2907
487b391d 2908 ++vcpu->stat.nmi_injections;
7ffd92c5 2909 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2910 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2911 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 2912 return;
2913 }
f08864b4
SY		 2914 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2915 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 2916 vmx_clear_hlt(vcpu);
f08864b4
SY		 2917}
2918
c4282df9 2919static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2920{
3b86cd99 2921 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2922 return 0;
33f089ca 2923
c4282df9 2924 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 2925 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2926 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2927}
2928
3cfc3092
JK		 2929static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2930{
2931 if (!cpu_has_virtual_nmis())
2932 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2933 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2934}
2935
2936static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2937{
2938 struct vcpu_vmx *vmx = to_vmx(vcpu);
2939
2940 if (!cpu_has_virtual_nmis()) {
2941 if (vmx->soft_vnmi_blocked != masked) {
2942 vmx->soft_vnmi_blocked = masked;
2943 vmx->vnmi_blocked_time = 0;
2944 }
2945 } else {
2946 if (masked)
2947 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2948 GUEST_INTR_STATE_NMI);
2949 else
2950 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2951 GUEST_INTR_STATE_NMI);
2952 }
2953}
2954
78646121
GN		 2955static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2956{
c4282df9
GN		 2957 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2958 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2959 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2960}
2961
cbc94022
IE		 2962static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2963{
2964 int ret;
2965 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2966 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2967 .guest_phys_addr = addr,
2968 .memory_size = PAGE_SIZE * 3,
2969 .flags = 0,
2970 };
2971
2972 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2973 if (ret)
2974 return ret;
bfc6d222 2975 kvm->arch.tss_addr = addr;
cbc94022
IE		 2976 return 0;
2977}
2978
6aa8b732
AK		 2979static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2980 int vec, u32 err_code)
2981{
b3f37707
NK		 2982 /*
2983 * Instruction with address size override prefix opcode 0x67
2984 * Cause the #SS fault with 0 error code in VM86 mode.
2985 */
2986 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 2987 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 2988 return 1;
77ab6db0
JK		 2989 /*
2990 * Forward all other exceptions that are valid in real mode.
2991 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2992 * the required debugging infrastructure rework.
2993 */
2994 switch (vec) {
77ab6db0 2995 case DB_VECTOR:
d0bfb940
JK		 2996 if (vcpu->guest_debug &
2997 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2998 return 0;
2999 kvm_queue_exception(vcpu, vec);
3000 return 1;
77ab6db0 3001 case BP_VECTOR:
c573cd22
JK		 3002 /*
3003 * Update instruction length as we may reinject the exception
3004 * from user space while in guest debugging mode.
3005 */
3006 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3007 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 3008 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3009 return 0;
3010 /* fall through */
3011 case DE_VECTOR:
77ab6db0
JK		 3012 case OF_VECTOR:
3013 case BR_VECTOR:
3014 case UD_VECTOR:
3015 case DF_VECTOR:
3016 case SS_VECTOR:
3017 case GP_VECTOR:
3018 case MF_VECTOR:
3019 kvm_queue_exception(vcpu, vec);
3020 return 1;
3021 }
6aa8b732
AK		 3022 return 0;
3023}
3024
a0861c02
AK		 3025/*
3026 * Trigger machine check on the host. We assume all the MSRs are already set up
3027 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3028 * We pass a fake environment to the machine check handler because we want
3029 * the guest to be always treated like user space, no matter what context
3030 * it used internally.
3031 */
3032static void kvm_machine_check(void)
3033{
3034#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3035 struct pt_regs regs = {
3036 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3037 .flags = X86_EFLAGS_IF,
3038 };
3039
3040 do_machine_check(&regs, 0);
3041#endif
3042}
3043
851ba692 3044static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3045{
3046 /* already handled by vcpu_run */
3047 return 1;
3048}
3049
851ba692 3050static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3051{
1155f76a 3052 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3053 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3054 u32 intr_info, ex_no, error_code;
42dbaa5a 3055 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3056 u32 vect_info;
3057 enum emulation_result er;
3058
1155f76a 3059 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 3060 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3061
a0861c02 3062 if (is_machine_check(intr_info))
851ba692 3063 return handle_machine_check(vcpu);
a0861c02 3064
6aa8b732 3065 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3066 !is_page_fault(intr_info)) {
3067 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3068 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3069 vcpu->run->internal.ndata = 2;
3070 vcpu->run->internal.data[0] = vect_info;
3071 vcpu->run->internal.data[1] = intr_info;
3072 return 0;
3073 }
6aa8b732 3074
e4a41889 3075 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3076 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3077
3078 if (is_no_device(intr_info)) {
5fd86fcf 3079 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3080 return 1;
3081 }
3082
7aa81cc0 3083 if (is_invalid_opcode(intr_info)) {
51d8b661 3084 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 3085 if (er != EMULATE_DONE)
7ee5d940 3086 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3087 return 1;
3088 }
3089
6aa8b732 3090 error_code = 0;
5fdbf976 3091 rip = kvm_rip_read(vcpu);
2e11384c 3092 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3093 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3094 if (is_page_fault(intr_info)) {
1439442c 3095 /* EPT won't cause page fault directly */
089d034e 3096 if (enable_ept)
1439442c 3097 BUG();
6aa8b732 3098 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3099 trace_kvm_page_fault(cr2, error_code);
3100
3298b75c 3101 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3102 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 3103 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 3104 }
3105
7ffd92c5 3106 if (vmx->rmode.vm86_active &&
6aa8b732 3107 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3108 error_code)) {
ad312c7c
ZX		 3109 if (vcpu->arch.halt_request) {
3110 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3111 return kvm_emulate_halt(vcpu);
3112 }
6aa8b732 3113 return 1;
72d6e5a0 3114 }
6aa8b732 3115
d0bfb940 3116 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3117 switch (ex_no) {
3118 case DB_VECTOR:
3119 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3120 if (!(vcpu->guest_debug &
3121 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3122 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3123 kvm_queue_exception(vcpu, DB_VECTOR);
3124 return 1;
3125 }
3126 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3127 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3128 /* fall through */
3129 case BP_VECTOR:
c573cd22
JK		 3130 /*
3131 * Update instruction length as we may reinject #BP from
3132 * user space while in guest debugging mode. Reading it for
3133 * #DB as well causes no harm, it is not used in that case.
3134 */
3135 vmx->vcpu.arch.event_exit_inst_len =
3136 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3137 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3138 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3139 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3140 break;
3141 default:
d0bfb940
JK		 3142 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3143 kvm_run->ex.exception = ex_no;
3144 kvm_run->ex.error_code = error_code;
42dbaa5a 3145 break;
6aa8b732 3146 }
6aa8b732
AK		 3147 return 0;
3148}
3149
851ba692 3150static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3151{
1165f5fe 3152 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3153 return 1;
3154}
3155
851ba692 3156static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3157{
851ba692 3158 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3159 return 0;
3160}
6aa8b732 3161
851ba692 3162static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3163{
bfdaab09 3164 unsigned long exit_qualification;
34c33d16 3165 int size, in, string;
039576c0 3166 unsigned port;
6aa8b732 3167
bfdaab09 3168 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3169 string = (exit_qualification & 16) != 0;
cf8f70bf 3170 in = (exit_qualification & 8) != 0;
e70669ab 3171
cf8f70bf 3172 ++vcpu->stat.io_exits;
e70669ab 3173
cf8f70bf 3174 if (string || in)
51d8b661 3175 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 3176
cf8f70bf
GN		 3177 port = exit_qualification >> 16;
3178 size = (exit_qualification & 7) + 1;
e93f36bc 3179 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3180
3181 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3182}
3183
102d8325
IM		 3184static void
3185vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3186{
3187 /*
3188 * Patch in the VMCALL instruction:
3189 */
3190 hypercall[0] = 0x0f;
3191 hypercall[1] = 0x01;
3192 hypercall[2] = 0xc1;
102d8325
IM		 3193}
3194
851ba692 3195static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3196{
229456fc 3197 unsigned long exit_qualification, val;
6aa8b732
AK		 3198 int cr;
3199 int reg;
49a9b07e 3200 int err;
6aa8b732 3201
bfdaab09 3202 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3203 cr = exit_qualification & 15;
3204 reg = (exit_qualification >> 8) & 15;
3205 switch ((exit_qualification >> 4) & 3) {
3206 case 0: /* mov to cr */
229456fc
MT		 3207 val = kvm_register_read(vcpu, reg);
3208 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3209 switch (cr) {
3210 case 0:
49a9b07e 3211 err = kvm_set_cr0(vcpu, val);
db8fcefa 3212 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3213 return 1;
3214 case 3:
2390218b 3215 err = kvm_set_cr3(vcpu, val);
db8fcefa 3216 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3217 return 1;
3218 case 4:
a83b29c6 3219 err = kvm_set_cr4(vcpu, val);
db8fcefa 3220 kvm_complete_insn_gp(vcpu, err);
6aa8b732 3221 return 1;
0a5fff19
GN		 3222 case 8: {
3223 u8 cr8_prev = kvm_get_cr8(vcpu);
3224 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 3225 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 3226 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 3227 if (irqchip_in_kernel(vcpu->kvm))
3228 return 1;
3229 if (cr8_prev <= cr8)
3230 return 1;
851ba692 3231 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3232 return 0;
3233 }
6aa8b732
AK		 3234 };
3235 break;
25c4c276 3236 case 2: /* clts */
edcafe3c 3237 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3238 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3239 skip_emulated_instruction(vcpu);
6b52d186 3240 vmx_fpu_activate(vcpu);
25c4c276 3241 return 1;
6aa8b732
AK		 3242 case 1: /*mov from cr*/
3243 switch (cr) {
3244 case 3:
9f8fe504
AK		 3245 val = kvm_read_cr3(vcpu);
3246 kvm_register_write(vcpu, reg, val);
3247 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3248 skip_emulated_instruction(vcpu);
3249 return 1;
3250 case 8:
229456fc
MT		 3251 val = kvm_get_cr8(vcpu);
3252 kvm_register_write(vcpu, reg, val);
3253 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3254 skip_emulated_instruction(vcpu);
3255 return 1;
3256 }
3257 break;
3258 case 3: /* lmsw */
a1f83a74 3259 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3260 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3261 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3262
3263 skip_emulated_instruction(vcpu);
3264 return 1;
3265 default:
3266 break;
3267 }
851ba692 3268 vcpu->run->exit_reason = 0;
f0242478 3269 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3270 (int)(exit_qualification >> 4) & 3, cr);
3271 return 0;
3272}
3273
851ba692 3274static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3275{
bfdaab09 3276 unsigned long exit_qualification;
6aa8b732
AK		 3277 int dr, reg;
3278
f2483415 3279 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3280 if (!kvm_require_cpl(vcpu, 0))
3281 return 1;
42dbaa5a
JK		 3282 dr = vmcs_readl(GUEST_DR7);
3283 if (dr & DR7_GD) {
3284 /*
3285 * As the vm-exit takes precedence over the debug trap, we
3286 * need to emulate the latter, either for the host or the
3287 * guest debugging itself.
3288 */
3289 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3290 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3291 vcpu->run->debug.arch.dr7 = dr;
3292 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3293 vmcs_readl(GUEST_CS_BASE) +
3294 vmcs_readl(GUEST_RIP);
851ba692
AK		 3295 vcpu->run->debug.arch.exception = DB_VECTOR;
3296 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3297 return 0;
3298 } else {
3299 vcpu->arch.dr7 &= ~DR7_GD;
3300 vcpu->arch.dr6 |= DR6_BD;
3301 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3302 kvm_queue_exception(vcpu, DB_VECTOR);
3303 return 1;
3304 }
3305 }
3306
bfdaab09 3307 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3308 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3309 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3310 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3311 unsigned long val;
3312 if (!kvm_get_dr(vcpu, dr, &val))
3313 kvm_register_write(vcpu, reg, val);
3314 } else
3315 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3316 skip_emulated_instruction(vcpu);
3317 return 1;
3318}
3319
020df079
GN		 3320static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3321{
3322 vmcs_writel(GUEST_DR7, val);
3323}
3324
851ba692 3325static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3326{
06465c5a
AK		 3327 kvm_emulate_cpuid(vcpu);
3328 return 1;
6aa8b732
AK		 3329}
3330
851ba692 3331static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3332{
ad312c7c 3333 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3334 u64 data;
3335
3336 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3337 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3338 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3339 return 1;
3340 }
3341
229456fc 3342 trace_kvm_msr_read(ecx, data);
2714d1d3 3343
6aa8b732 3344 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3345 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3346 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3347 skip_emulated_instruction(vcpu);
3348 return 1;
3349}
3350
851ba692 3351static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3352{
ad312c7c
ZX		 3353 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3354 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3355 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3356
3357 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3358 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3359 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3360 return 1;
3361 }
3362
59200273 3363 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3364 skip_emulated_instruction(vcpu);
3365 return 1;
3366}
3367
851ba692 3368static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 3369{
3842d135 3370 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 3371 return 1;
3372}
3373
851ba692 3374static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3375{
85f455f7
ED		 3376 u32 cpu_based_vm_exec_control;
3377
3378 /* clear pending irq */
3379 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3380 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3381 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3382
3842d135
AK		 3383 kvm_make_request(KVM_REQ_EVENT, vcpu);
3384
a26bf12a 3385 ++vcpu->stat.irq_window_exits;
2714d1d3 3386
c1150d8c
DL		 3387 /*
3388 * If the user space waits to inject interrupts, exit as soon as
3389 * possible
3390 */
8061823a 3391 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3392 vcpu->run->request_interrupt_window &&
8061823a 3393 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3394 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3395 return 0;
3396 }
6aa8b732
AK		 3397 return 1;
3398}
3399
851ba692 3400static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3401{
3402 skip_emulated_instruction(vcpu);
d3bef15f 3403 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3404}
3405
851ba692 3406static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3407{
510043da 3408 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3409 kvm_emulate_hypercall(vcpu);
3410 return 1;
c21415e8
IM		 3411}
3412
851ba692 3413static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3414{
3415 kvm_queue_exception(vcpu, UD_VECTOR);
3416 return 1;
3417}
3418
ec25d5e6
GN		 3419static int handle_invd(struct kvm_vcpu *vcpu)
3420{
51d8b661 3421 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 3422}
3423
851ba692 3424static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3425{
f9c617f6 3426 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3427
3428 kvm_mmu_invlpg(vcpu, exit_qualification);
3429 skip_emulated_instruction(vcpu);
3430 return 1;
3431}
3432
851ba692 3433static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3434{
3435 skip_emulated_instruction(vcpu);
f5f48ee1 3436 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3437 return 1;
3438}
3439
2acf923e
DC		 3440static int handle_xsetbv(struct kvm_vcpu *vcpu)
3441{
3442 u64 new_bv = kvm_read_edx_eax(vcpu);
3443 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3444
3445 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3446 skip_emulated_instruction(vcpu);
3447 return 1;
3448}
3449
851ba692 3450static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3451{
51d8b661 3452 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 3453}
3454
851ba692 3455static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3456{
60637aac 3457 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3458 unsigned long exit_qualification;
e269fb21
JK		 3459 bool has_error_code = false;
3460 u32 error_code = 0;
37817f29 3461 u16 tss_selector;
64a7ec06
GN		 3462 int reason, type, idt_v;
3463
3464 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3465 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3466
3467 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3468
3469 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3470 if (reason == TASK_SWITCH_GATE && idt_v) {
3471 switch (type) {
3472 case INTR_TYPE_NMI_INTR:
3473 vcpu->arch.nmi_injected = false;
3474 if (cpu_has_virtual_nmis())
3475 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3476 GUEST_INTR_STATE_NMI);
3477 break;
3478 case INTR_TYPE_EXT_INTR:
66fd3f7f 3479 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3480 kvm_clear_interrupt_queue(vcpu);
3481 break;
3482 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3483 if (vmx->idt_vectoring_info &
3484 VECTORING_INFO_DELIVER_CODE_MASK) {
3485 has_error_code = true;
3486 error_code =
3487 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3488 }
3489 /* fall through */
64a7ec06
GN		 3490 case INTR_TYPE_SOFT_EXCEPTION:
3491 kvm_clear_exception_queue(vcpu);
3492 break;
3493 default:
3494 break;
3495 }
60637aac 3496 }
37817f29
IE		 3497 tss_selector = exit_qualification;
3498
64a7ec06
GN		 3499 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3500 type != INTR_TYPE_EXT_INTR &&
3501 type != INTR_TYPE_NMI_INTR))
3502 skip_emulated_instruction(vcpu);
3503
acb54517
GN		 3504 if (kvm_task_switch(vcpu, tss_selector, reason,
3505 has_error_code, error_code) == EMULATE_FAIL) {
3506 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3507 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3508 vcpu->run->internal.ndata = 0;
42dbaa5a 3509 return 0;
acb54517 3510 }
42dbaa5a
JK		 3511
3512 /* clear all local breakpoint enable flags */
3513 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3514
3515 /*
3516 * TODO: What about debug traps on tss switch?
3517 * Are we supposed to inject them and update dr6?
3518 */
3519
3520 return 1;
37817f29
IE		 3521}
3522
851ba692 3523static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3524{
f9c617f6 3525 unsigned long exit_qualification;
1439442c 3526 gpa_t gpa;
1439442c 3527 int gla_validity;
1439442c 3528
f9c617f6 3529 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3530
3531 if (exit_qualification & (1 << 6)) {
3532 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3533 return -EINVAL;
1439442c
SY		 3534 }
3535
3536 gla_validity = (exit_qualification >> 7) & 0x3;
3537 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3538 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3539 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3540 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3541 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3542 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3543 (long unsigned int)exit_qualification);
851ba692
AK		 3544 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3545 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3546 return 0;
1439442c
SY		 3547 }
3548
3549 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3550 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 3551 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 3552}
3553
68f89400
MT		 3554static u64 ept_rsvd_mask(u64 spte, int level)
3555{
3556 int i;
3557 u64 mask = 0;
3558
3559 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3560 mask |= (1ULL << i);
3561
3562 if (level > 2)
3563 /* bits 7:3 reserved */
3564 mask |= 0xf8;
3565 else if (level == 2) {
3566 if (spte & (1ULL << 7))
3567 /* 2MB ref, bits 20:12 reserved */
3568 mask |= 0x1ff000;
3569 else
3570 /* bits 6:3 reserved */
3571 mask |= 0x78;
3572 }
3573
3574 return mask;
3575}
3576
3577static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3578 int level)
3579{
3580 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3581
3582 /* 010b (write-only) */
3583 WARN_ON((spte & 0x7) == 0x2);
3584
3585 /* 110b (write/execute) */
3586 WARN_ON((spte & 0x7) == 0x6);
3587
3588 /* 100b (execute-only) and value not supported by logical processor */
3589 if (!cpu_has_vmx_ept_execute_only())
3590 WARN_ON((spte & 0x7) == 0x4);
3591
3592 /* not 000b */
3593 if ((spte & 0x7)) {
3594 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3595
3596 if (rsvd_bits != 0) {
3597 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3598 __func__, rsvd_bits);
3599 WARN_ON(1);
3600 }
3601
3602 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3603 u64 ept_mem_type = (spte & 0x38) >> 3;
3604
3605 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3606 ept_mem_type == 7) {
3607 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3608 __func__, ept_mem_type);
3609 WARN_ON(1);
3610 }
3611 }
3612 }
3613}
3614
851ba692 3615static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3616{
3617 u64 sptes[4];
3618 int nr_sptes, i;
3619 gpa_t gpa;
3620
3621 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3622
3623 printk(KERN_ERR "EPT: Misconfiguration.\n");
3624 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3625
3626 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3627
3628 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3629 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3630
851ba692
AK		 3631 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3632 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3633
3634 return 0;
3635}
3636
851ba692 3637static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3638{
3639 u32 cpu_based_vm_exec_control;
3640
3641 /* clear pending NMI */
3642 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3643 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3644 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3645 ++vcpu->stat.nmi_window_exits;
3842d135 3646 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 3647
3648 return 1;
3649}
3650
80ced186 3651static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3652{
8b3079a5
AK		 3653 struct vcpu_vmx *vmx = to_vmx(vcpu);
3654 enum emulation_result err = EMULATE_DONE;
80ced186 3655 int ret = 1;
49e9d557
AK		 3656 u32 cpu_exec_ctrl;
3657 bool intr_window_requested;
3658
3659 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3660 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 3661
3662 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 3663 if (intr_window_requested
3664 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3665 return handle_interrupt_window(&vmx->vcpu);
3666
51d8b661 3667 err = emulate_instruction(vcpu, 0);
ea953ef0 3668
80ced186
MG		 3669 if (err == EMULATE_DO_MMIO) {
3670 ret = 0;
3671 goto out;
3672 }
1d5a4d9b 3673
6d77dbfc
GN		 3674 if (err != EMULATE_DONE)
3675 return 0;
ea953ef0
MG		 3676
3677 if (signal_pending(current))
80ced186 3678 goto out;
ea953ef0
MG		 3679 if (need_resched())
3680 schedule();
3681 }
3682
80ced186
MG		 3683 vmx->emulation_required = 0;
3684out:
3685 return ret;
ea953ef0
MG		 3686}
3687
4b8d54f9
ZE		 3688/*
3689 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3690 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3691 */
9fb41ba8 3692static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3693{
3694 skip_emulated_instruction(vcpu);
3695 kvm_vcpu_on_spin(vcpu);
3696
3697 return 1;
3698}
3699
59708670
SY		 3700static int handle_invalid_op(struct kvm_vcpu *vcpu)
3701{
3702 kvm_queue_exception(vcpu, UD_VECTOR);
3703 return 1;
3704}
3705
6aa8b732
AK		 3706/*
3707 * The exit handlers return 1 if the exit was handled fully and guest execution
3708 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3709 * to be done to userspace and return 0.
3710 */
851ba692 3711static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3712 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3713 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3714 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3715 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3716 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3717 [EXIT_REASON_CR_ACCESS] = handle_cr,
3718 [EXIT_REASON_DR_ACCESS] = handle_dr,
3719 [EXIT_REASON_CPUID] = handle_cpuid,
3720 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3721 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3722 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3723 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 3724 [EXIT_REASON_INVD] = handle_invd,
a7052897 3725 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3726 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3727 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3728 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3729 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3730 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3731 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3732 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3733 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3734 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3735 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3736 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3737 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3738 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3739 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3740 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3741 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3742 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3743 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3744 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3745 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3746 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3747};
3748
3749static const int kvm_vmx_max_exit_handlers =
50a3485c 3750 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 3751
586f9607
AK		 3752static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3753{
3754 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3755 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3756}
3757
6aa8b732
AK		 3758/*
3759 * The guest has exited. See if we can fix it or if we need userspace
3760 * assistance.
3761 */
851ba692 3762static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3763{
29bd8a78 3764 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3765 u32 exit_reason = vmx->exit_reason;
1155f76a 3766 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3767
aa17911e 3768 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 3769
80ced186
MG		 3770 /* If guest state is invalid, start emulating */
3771 if (vmx->emulation_required && emulate_invalid_guest_state)
3772 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3773
5120702e
MG		 3774 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3775 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3776 vcpu->run->fail_entry.hardware_entry_failure_reason
3777 = exit_reason;
3778 return 0;
3779 }
3780
29bd8a78 3781 if (unlikely(vmx->fail)) {
851ba692
AK		 3782 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3783 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3784 = vmcs_read32(VM_INSTRUCTION_ERROR);
3785 return 0;
3786 }
6aa8b732 3787
d77c26fc 3788 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3789 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3790 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3791 exit_reason != EXIT_REASON_TASK_SWITCH))
3792 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3793 "(0x%x) and exit reason is 0x%x\n",
3794 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3795
3796 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3797 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3798 vmx->soft_vnmi_blocked = 0;
3b86cd99 3799 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3800 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3801 /*
3802 * This CPU don't support us in finding the end of an
3803 * NMI-blocked window if the guest runs with IRQs
3804 * disabled. So we pull the trigger after 1 s of
3805 * futile waiting, but inform the user about this.
3806 */
3807 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3808 "state on VCPU %d after 1 s timeout\n",
3809 __func__, vcpu->vcpu_id);
3810 vmx->soft_vnmi_blocked = 0;
3b86cd99 3811 }
3b86cd99
JK		 3812 }
3813
6aa8b732
AK		 3814 if (exit_reason < kvm_vmx_max_exit_handlers
3815 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3816 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3817 else {
851ba692
AK		 3818 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3819 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3820 }
3821 return 0;
3822}
3823
95ba8273 3824static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3825{
95ba8273 3826 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3827 vmcs_write32(TPR_THRESHOLD, 0);
3828 return;
3829 }
3830
95ba8273 3831 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3832}
3833
51aa01d1 3834static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 3835{
51aa01d1 3836 u32 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 3837
3838 /* Handle machine checks before interrupts are enabled */
3839 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3840 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3841 && is_machine_check(exit_intr_info)))
3842 kvm_machine_check();
3843
20f65983
GN		 3844 /* We need to handle NMIs before interrupts are enabled */
3845 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3846 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3847 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3848 asm("int $2");
ff9d07a0
ZY		 3849 kvm_after_handle_nmi(&vmx->vcpu);
3850 }
51aa01d1 3851}
20f65983 3852
51aa01d1
AK		 3853static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3854{
3855 u32 exit_intr_info = vmx->exit_intr_info;
3856 bool unblock_nmi;
3857 u8 vector;
3858 bool idtv_info_valid;
3859
3860 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 3861
cf393f75
AK		 3862 if (cpu_has_virtual_nmis()) {
3863 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3864 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3865 /*
7b4a25cb 3866 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3867 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3868 * a guest IRET fault.
7b4a25cb
GN		 3869 * SDM 3: 23.2.2 (September 2008)
3870 * Bit 12 is undefined in any of the following cases:
3871 * If the VM exit sets the valid bit in the IDT-vectoring
3872 * information field.
3873 * If the VM exit is due to a double fault.
cf393f75 3874 */
7b4a25cb
GN		 3875 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3876 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3877 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3878 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3879 } else if (unlikely(vmx->soft_vnmi_blocked))
3880 vmx->vnmi_blocked_time +=
3881 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 3882}
3883
83422e17
AK		 3884static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3885 u32 idt_vectoring_info,
3886 int instr_len_field,
3887 int error_code_field)
51aa01d1 3888{
51aa01d1
AK		 3889 u8 vector;
3890 int type;
3891 bool idtv_info_valid;
3892
3893 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 3894
37b96e98
GN		 3895 vmx->vcpu.arch.nmi_injected = false;
3896 kvm_clear_exception_queue(&vmx->vcpu);
3897 kvm_clear_interrupt_queue(&vmx->vcpu);
3898
3899 if (!idtv_info_valid)
3900 return;
3901
3842d135
AK		 3902 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3903
668f612f
AK		 3904 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3905 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3906
64a7ec06 3907 switch (type) {
37b96e98
GN		 3908 case INTR_TYPE_NMI_INTR:
3909 vmx->vcpu.arch.nmi_injected = true;
668f612f 3910 /*
7b4a25cb 3911 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3912 * Clear bit "block by NMI" before VM entry if a NMI
3913 * delivery faulted.
668f612f 3914 */
37b96e98
GN		 3915 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3916 GUEST_INTR_STATE_NMI);
3917 break;
37b96e98 3918 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 3919 vmx->vcpu.arch.event_exit_inst_len =
83422e17 3920 vmcs_read32(instr_len_field);
66fd3f7f
GN		 3921 /* fall through */
3922 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3923 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 3924 u32 err = vmcs_read32(error_code_field);
37b96e98 3925 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3926 } else
3927 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3928 break;
66fd3f7f
GN		 3929 case INTR_TYPE_SOFT_INTR:
3930 vmx->vcpu.arch.event_exit_inst_len =
83422e17 3931 vmcs_read32(instr_len_field);
66fd3f7f 3932 /* fall through */
37b96e98 3933 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3934 kvm_queue_interrupt(&vmx->vcpu, vector,
3935 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3936 break;
3937 default:
3938 break;
f7d9238f 3939 }
cf393f75
AK		 3940}
3941
83422e17
AK		 3942static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3943{
3944 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3945 VM_EXIT_INSTRUCTION_LEN,
3946 IDT_VECTORING_ERROR_CODE);
3947}
3948
b463a6f7
AK		 3949static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3950{
3951 __vmx_complete_interrupts(to_vmx(vcpu),
3952 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3953 VM_ENTRY_INSTRUCTION_LEN,
3954 VM_ENTRY_EXCEPTION_ERROR_CODE);
3955
3956 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3957}
3958
c801949d
AK		 3959#ifdef CONFIG_X86_64
3960#define R "r"
3961#define Q "q"
3962#else
3963#define R "e"
3964#define Q "l"
3965#endif
3966
104f226b 3967static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3968{
a2fa3e9f 3969 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b
AK		 3970
3971 /* Record the guest's net vcpu time for enforced NMI injections. */
3972 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3973 vmx->entry_time = ktime_get();
3974
3975 /* Don't enter VMX if guest state is invalid, let the exit handler
3976 start emulation until we arrive back to a valid state */
3977 if (vmx->emulation_required && emulate_invalid_guest_state)
3978 return;
3979
3980 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3981 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3982 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3983 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3984
3985 /* When single-stepping over STI and MOV SS, we must clear the
3986 * corresponding interruptibility bits in the guest state. Otherwise
3987 * vmentry fails as it then expects bit 14 (BS) in pending debug
3988 * exceptions being set, but that's not correct for the guest debugging
3989 * case. */
3990 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3991 vmx_set_interrupt_shadow(vcpu, 0);
3992
3993 asm(
6aa8b732 3994 /* Store host registers */
c801949d
AK		 3995 "push %%"R"dx; push %%"R"bp;"
3996 "push %%"R"cx \n\t"
313dbd49
AK		 3997 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3998 "je 1f \n\t"
3999 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 4000 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 4001 "1: \n\t"
d3edefc0
AK		 4002 /* Reload cr2 if changed */
4003 "mov %c[cr2](%0), %%"R"ax \n\t"
4004 "mov %%cr2, %%"R"dx \n\t"
4005 "cmp %%"R"ax, %%"R"dx \n\t"
4006 "je 2f \n\t"
4007 "mov %%"R"ax, %%cr2 \n\t"
4008 "2: \n\t"
6aa8b732 4009 /* Check if vmlaunch of vmresume is needed */
e08aa78a 4010 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 4011 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 4012 "mov %c[rax](%0), %%"R"ax \n\t"
4013 "mov %c[rbx](%0), %%"R"bx \n\t"
4014 "mov %c[rdx](%0), %%"R"dx \n\t"
4015 "mov %c[rsi](%0), %%"R"si \n\t"
4016 "mov %c[rdi](%0), %%"R"di \n\t"
4017 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 4018#ifdef CONFIG_X86_64
e08aa78a
AK		 4019 "mov %c[r8](%0), %%r8 \n\t"
4020 "mov %c[r9](%0), %%r9 \n\t"
4021 "mov %c[r10](%0), %%r10 \n\t"
4022 "mov %c[r11](%0), %%r11 \n\t"
4023 "mov %c[r12](%0), %%r12 \n\t"
4024 "mov %c[r13](%0), %%r13 \n\t"
4025 "mov %c[r14](%0), %%r14 \n\t"
4026 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 4027#endif
c801949d
AK		 4028 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4029
6aa8b732 4030 /* Enter guest mode */
cd2276a7 4031 "jne .Llaunched \n\t"
4ecac3fd 4032 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 4033 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 4034 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 4035 ".Lkvm_vmx_return: "
6aa8b732 4036 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 4037 "xchg %0, (%%"R"sp) \n\t"
4038 "mov %%"R"ax, %c[rax](%0) \n\t"
4039 "mov %%"R"bx, %c[rbx](%0) \n\t"
4040 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
4041 "mov %%"R"dx, %c[rdx](%0) \n\t"
4042 "mov %%"R"si, %c[rsi](%0) \n\t"
4043 "mov %%"R"di, %c[rdi](%0) \n\t"
4044 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 4045#ifdef CONFIG_X86_64
e08aa78a
AK		 4046 "mov %%r8, %c[r8](%0) \n\t"
4047 "mov %%r9, %c[r9](%0) \n\t"
4048 "mov %%r10, %c[r10](%0) \n\t"
4049 "mov %%r11, %c[r11](%0) \n\t"
4050 "mov %%r12, %c[r12](%0) \n\t"
4051 "mov %%r13, %c[r13](%0) \n\t"
4052 "mov %%r14, %c[r14](%0) \n\t"
4053 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 4054#endif
c801949d
AK		 4055 "mov %%cr2, %%"R"ax \n\t"
4056 "mov %%"R"ax, %c[cr2](%0) \n\t"
4057
4058 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 4059 "setbe %c[fail](%0) \n\t"
4060 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4061 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4062 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 4063 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 4064 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4065 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4066 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4067 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4068 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4069 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4070 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4071#ifdef CONFIG_X86_64
ad312c7c
ZX		 4072 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4073 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4074 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4075 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4076 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4077 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4078 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4079 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4080#endif
ad312c7c 4081 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 4082 : "cc", "memory"
07d6f555 4083 , R"ax", R"bx", R"di", R"si"
c2036300 4084#ifdef CONFIG_X86_64
c2036300
LV		 4085 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4086#endif
4087 );
6aa8b732 4088
6de4f3ad 4089 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
aff48baa
AK		 4090 | (1 << VCPU_EXREG_PDPTR)
4091 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 4092 vcpu->arch.regs_dirty = 0;
4093
1155f76a
AK		 4094 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4095
d77c26fc 4096 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4097 vmx->launched = 1;
1b6269db 4098
51aa01d1
AK		 4099 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4100 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4101
4102 vmx_complete_atomic_exit(vmx);
4103 vmx_recover_nmi_blocking(vmx);
cf393f75 4104 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4105}
4106
c801949d
AK		 4107#undef R
4108#undef Q
4109
6aa8b732
AK		 4110static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4111{
a2fa3e9f
GH		 4112 struct vcpu_vmx *vmx = to_vmx(vcpu);
4113
4114 if (vmx->vmcs) {
543e4243 4115 vcpu_clear(vmx);
a2fa3e9f
GH		 4116 free_vmcs(vmx->vmcs);
4117 vmx->vmcs = NULL;
6aa8b732
AK		 4118 }
4119}
4120
4121static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4122{
fb3f0f51
RR		 4123 struct vcpu_vmx *vmx = to_vmx(vcpu);
4124
cdbecfc3 4125 free_vpid(vmx);
6aa8b732 4126 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4127 kfree(vmx->guest_msrs);
4128 kvm_vcpu_uninit(vcpu);
a4770347 4129 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4130}
4131
4610c9cc
DX		 4132static inline void vmcs_init(struct vmcs *vmcs)
4133{
4134 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4135
4136 if (!vmm_exclusive)
4137 kvm_cpu_vmxon(phys_addr);
4138
4139 vmcs_clear(vmcs);
4140
4141 if (!vmm_exclusive)
4142 kvm_cpu_vmxoff();
4143}
4144
fb3f0f51 4145static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4146{
fb3f0f51 4147 int err;
c16f862d 4148 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4149 int cpu;
6aa8b732 4150
a2fa3e9f 4151 if (!vmx)
fb3f0f51
RR		 4152 return ERR_PTR(-ENOMEM);
4153
2384d2b3
SY		 4154 allocate_vpid(vmx);
4155
fb3f0f51
RR		 4156 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4157 if (err)
4158 goto free_vcpu;
965b58a5 4159
a2fa3e9f 4160 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4161 if (!vmx->guest_msrs) {
4162 err = -ENOMEM;
4163 goto uninit_vcpu;
4164 }
965b58a5 4165
a2fa3e9f
GH		 4166 vmx->vmcs = alloc_vmcs();
4167 if (!vmx->vmcs)
fb3f0f51 4168 goto free_msrs;
a2fa3e9f 4169
4610c9cc 4170 vmcs_init(vmx->vmcs);
a2fa3e9f 4171
15ad7146
AK		 4172 cpu = get_cpu();
4173 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 4174 vmx->vcpu.cpu = cpu;
8b9cf98c 4175 err = vmx_vcpu_setup(vmx);
fb3f0f51 4176 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4177 put_cpu();
fb3f0f51
RR		 4178 if (err)
4179 goto free_vmcs;
5e4a0b3c
MT		 4180 if (vm_need_virtualize_apic_accesses(kvm))
4181 if (alloc_apic_access_page(kvm) != 0)
4182 goto free_vmcs;
fb3f0f51 4183
b927a3ce
SY		 4184 if (enable_ept) {
4185 if (!kvm->arch.ept_identity_map_addr)
4186 kvm->arch.ept_identity_map_addr =
4187 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4188 if (alloc_identity_pagetable(kvm) != 0)
4189 goto free_vmcs;
b927a3ce 4190 }
b7ebfb05 4191
fb3f0f51
RR		 4192 return &vmx->vcpu;
4193
4194free_vmcs:
4195 free_vmcs(vmx->vmcs);
4196free_msrs:
fb3f0f51
RR		 4197 kfree(vmx->guest_msrs);
4198uninit_vcpu:
4199 kvm_vcpu_uninit(&vmx->vcpu);
4200free_vcpu:
cdbecfc3 4201 free_vpid(vmx);
a4770347 4202 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4203 return ERR_PTR(err);
6aa8b732
AK		 4204}
4205
002c7f7c
YS		 4206static void __init vmx_check_processor_compat(void *rtn)
4207{
4208 struct vmcs_config vmcs_conf;
4209
4210 *(int *)rtn = 0;
4211 if (setup_vmcs_config(&vmcs_conf) < 0)
4212 *(int *)rtn = -EIO;
4213 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4214 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4215 smp_processor_id());
4216 *(int *)rtn = -EIO;
4217 }
4218}
4219
67253af5
SY		 4220static int get_ept_level(void)
4221{
4222 return VMX_EPT_DEFAULT_GAW + 1;
4223}
4224
4b12f0de 4225static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4226{
4b12f0de
SY		 4227 u64 ret;
4228
522c68c4
SY		 4229 /* For VT-d and EPT combination
4230 * 1. MMIO: always map as UC
4231 * 2. EPT with VT-d:
4232 * a. VT-d without snooping control feature: can't guarantee the
4233 * result, try to trust guest.
4234 * b. VT-d with snooping control feature: snooping control feature of
4235 * VT-d engine can guarantee the cache correctness. Just set it
4236 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4237 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4238 * consistent with host MTRR
4239 */
4b12f0de
SY		 4240 if (is_mmio)
4241 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4242 else if (vcpu->kvm->arch.iommu_domain &&
4243 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4244 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4245 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4246 else
522c68c4 4247 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4248 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4249
4250 return ret;
64d4d521
SY		 4251}
4252
f4c9e87c
AK		 4253#define _ER(x) { EXIT_REASON_##x, #x }
4254
229456fc 4255static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4256 _ER(EXCEPTION_NMI),
4257 _ER(EXTERNAL_INTERRUPT),
4258 _ER(TRIPLE_FAULT),
4259 _ER(PENDING_INTERRUPT),
4260 _ER(NMI_WINDOW),
4261 _ER(TASK_SWITCH),
4262 _ER(CPUID),
4263 _ER(HLT),
4264 _ER(INVLPG),
4265 _ER(RDPMC),
4266 _ER(RDTSC),
4267 _ER(VMCALL),
4268 _ER(VMCLEAR),
4269 _ER(VMLAUNCH),
4270 _ER(VMPTRLD),
4271 _ER(VMPTRST),
4272 _ER(VMREAD),
4273 _ER(VMRESUME),
4274 _ER(VMWRITE),
4275 _ER(VMOFF),
4276 _ER(VMON),
4277 _ER(CR_ACCESS),
4278 _ER(DR_ACCESS),
4279 _ER(IO_INSTRUCTION),
4280 _ER(MSR_READ),
4281 _ER(MSR_WRITE),
4282 _ER(MWAIT_INSTRUCTION),
4283 _ER(MONITOR_INSTRUCTION),
4284 _ER(PAUSE_INSTRUCTION),
4285 _ER(MCE_DURING_VMENTRY),
4286 _ER(TPR_BELOW_THRESHOLD),
4287 _ER(APIC_ACCESS),
4288 _ER(EPT_VIOLATION),
4289 _ER(EPT_MISCONFIG),
4290 _ER(WBINVD),
229456fc
MT		 4291 { -1, NULL }
4292};
4293
f4c9e87c
AK		 4294#undef _ER
4295
17cc3935 4296static int vmx_get_lpage_level(void)
344f414f 4297{
878403b7
SY		 4298 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4299 return PT_DIRECTORY_LEVEL;
4300 else
4301 /* For shadow and EPT supported 1GB page */
4302 return PT_PDPE_LEVEL;
344f414f
JR		 4303}
4304
0e851880
SY		 4305static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4306{
4e47c7a6
SY		 4307 struct kvm_cpuid_entry2 *best;
4308 struct vcpu_vmx *vmx = to_vmx(vcpu);
4309 u32 exec_control;
4310
4311 vmx->rdtscp_enabled = false;
4312 if (vmx_rdtscp_supported()) {
4313 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4314 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4315 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4316 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4317 vmx->rdtscp_enabled = true;
4318 else {
4319 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4320 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4321 exec_control);
4322 }
4323 }
4324 }
0e851880
SY		 4325}
4326
d4330ef2
JR		 4327static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4328{
4329}
4330
cbdd1bea 4331static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4332 .cpu_has_kvm_support = cpu_has_kvm_support,
4333 .disabled_by_bios = vmx_disabled_by_bios,
4334 .hardware_setup = hardware_setup,
4335 .hardware_unsetup = hardware_unsetup,
002c7f7c 4336 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4337 .hardware_enable = hardware_enable,
4338 .hardware_disable = hardware_disable,
04547156 4339 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4340
4341 .vcpu_create = vmx_create_vcpu,
4342 .vcpu_free = vmx_free_vcpu,
04d2cc77 4343 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4344
04d2cc77 4345 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4346 .vcpu_load = vmx_vcpu_load,
4347 .vcpu_put = vmx_vcpu_put,
4348
4349 .set_guest_debug = set_guest_debug,
4350 .get_msr = vmx_get_msr,
4351 .set_msr = vmx_set_msr,
4352 .get_segment_base = vmx_get_segment_base,
4353 .get_segment = vmx_get_segment,
4354 .set_segment = vmx_set_segment,
2e4d2653 4355 .get_cpl = vmx_get_cpl,
6aa8b732 4356 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4357 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 4358 .decache_cr3 = vmx_decache_cr3,
25c4c276 4359 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4360 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4361 .set_cr3 = vmx_set_cr3,
4362 .set_cr4 = vmx_set_cr4,
6aa8b732 4363 .set_efer = vmx_set_efer,
6aa8b732
AK		 4364 .get_idt = vmx_get_idt,
4365 .set_idt = vmx_set_idt,
4366 .get_gdt = vmx_get_gdt,
4367 .set_gdt = vmx_set_gdt,
020df079 4368 .set_dr7 = vmx_set_dr7,
5fdbf976 4369 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4370 .get_rflags = vmx_get_rflags,
4371 .set_rflags = vmx_set_rflags,
ebcbab4c 4372 .fpu_activate = vmx_fpu_activate,
02daab21 4373 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4374
4375 .tlb_flush = vmx_flush_tlb,
6aa8b732 4376
6aa8b732 4377 .run = vmx_vcpu_run,
6062d012 4378 .handle_exit = vmx_handle_exit,
6aa8b732 4379 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4380 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4381 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4382 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4383 .set_irq = vmx_inject_irq,
95ba8273 4384 .set_nmi = vmx_inject_nmi,
298101da 4385 .queue_exception = vmx_queue_exception,
b463a6f7 4386 .cancel_injection = vmx_cancel_injection,
78646121 4387 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4388 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4389 .get_nmi_mask = vmx_get_nmi_mask,
4390 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4391 .enable_nmi_window = enable_nmi_window,
4392 .enable_irq_window = enable_irq_window,
4393 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4394
cbc94022 4395 .set_tss_addr = vmx_set_tss_addr,
67253af5 4396 .get_tdp_level = get_ept_level,
4b12f0de 4397 .get_mt_mask = vmx_get_mt_mask,
229456fc 4398
586f9607 4399 .get_exit_info = vmx_get_exit_info,
229456fc 4400 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 4401
17cc3935 4402 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4403
4404 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4405
4406 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4407
4408 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4409
4410 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA		 4411
4412 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 4413 .adjust_tsc_offset = vmx_adjust_tsc_offset,
1c97f0a0
JR		 4414
4415 .set_tdp_cr3 = vmx_set_cr3,
6aa8b732
AK		 4416};
4417
4418static int __init vmx_init(void)
4419{
26bb0981
AK		 4420 int r, i;
4421
4422 rdmsrl_safe(MSR_EFER, &host_efer);
4423
4424 for (i = 0; i < NR_VMX_MSR; ++i)
4425 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4426
3e7c73e9 4427 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4428 if (!vmx_io_bitmap_a)
4429 return -ENOMEM;
4430
3e7c73e9 4431 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4432 if (!vmx_io_bitmap_b) {
4433 r = -ENOMEM;
4434 goto out;
4435 }
4436
5897297b
AK		 4437 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4438 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4439 r = -ENOMEM;
4440 goto out1;
4441 }
4442
5897297b
AK		 4443 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4444 if (!vmx_msr_bitmap_longmode) {
4445 r = -ENOMEM;
4446 goto out2;
4447 }
4448
fdef3ad1
HQ		 4449 /*
4450 * Allow direct access to the PC debug port (it is often used for I/O
4451 * delays, but the vmexits simply slow things down).
4452 */
3e7c73e9
AK		 4453 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4454 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4455
3e7c73e9 4456 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4457
5897297b
AK		 4458 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4459 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4460
2384d2b3
SY		 4461 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4462
0ee75bea
AK		 4463 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4464 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4465 if (r)
5897297b 4466 goto out3;
25c5f225 4467
5897297b
AK		 4468 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4469 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4470 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4471 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4472 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4473 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4474
089d034e 4475 if (enable_ept) {
1439442c 4476 bypass_guest_pf = 0;
534e38b4 4477 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4478 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4479 kvm_enable_tdp();
4480 } else
4481 kvm_disable_tdp();
1439442c 4482
c7addb90
AK		 4483 if (bypass_guest_pf)
4484 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4485
fdef3ad1
HQ		 4486 return 0;
4487
5897297b
AK		 4488out3:
4489 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4490out2:
5897297b 4491 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4492out1:
3e7c73e9 4493 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4494out:
3e7c73e9 4495 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4496 return r;
6aa8b732
AK		 4497}
4498
4499static void __exit vmx_exit(void)
4500{
5897297b
AK		 4501 free_page((unsigned long)vmx_msr_bitmap_legacy);
4502 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4503 free_page((unsigned long)vmx_io_bitmap_b);
4504 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4505
cb498ea2 4506 kvm_exit();
6aa8b732
AK		 4507}
4508
4509module_init(vmx_init)
4510module_exit(vmx_exit)
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