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c6dc6f63
AP
1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf
EH
26#include "sysemu/cpus.h"
27#include "topology.h"
c6dc6f63 28
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29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
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33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
53a89e26 44#include "hw/qdev-properties.h"
62fc403f 45#include "hw/cpu/icc_bus.h"
bdeec802 46#ifndef CONFIG_USER_ONLY
0d09e41a 47#include "hw/xen/xen.h"
0d09e41a 48#include "hw/i386/apic_internal.h"
bdeec802
IM
49#endif
50
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EH
51
52/* Cache topology CPUID constants: */
53
54/* CPUID Leaf 2 Descriptors */
55
56#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57#define CPUID_2_L1I_32KB_8WAY_64B 0x30
58#define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61/* CPUID Leaf 4 constants: */
62
63/* EAX: */
64#define CPUID_4_TYPE_DCACHE 1
65#define CPUID_4_TYPE_ICACHE 2
66#define CPUID_4_TYPE_UNIFIED 3
67
68#define CPUID_4_LEVEL(l) ((l) << 5)
69
70#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71#define CPUID_4_FULLY_ASSOC (1 << 9)
72
73/* EDX: */
74#define CPUID_4_NO_INVD_SHARING (1 << 0)
75#define CPUID_4_INCLUSIVE (1 << 1)
76#define CPUID_4_COMPLEX_IDX (1 << 2)
77
78#define ASSOC_FULL 0xFF
79
80/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95/* Definitions of the hardcoded cache entries we expose: */
96
97/* L1 data cache: */
98#define L1D_LINE_SIZE 64
99#define L1D_ASSOCIATIVITY 8
100#define L1D_SETS 64
101#define L1D_PARTITIONS 1
102/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105#define L1D_LINES_PER_TAG 1
106#define L1D_SIZE_KB_AMD 64
107#define L1D_ASSOCIATIVITY_AMD 2
108
109/* L1 instruction cache: */
110#define L1I_LINE_SIZE 64
111#define L1I_ASSOCIATIVITY 8
112#define L1I_SETS 64
113#define L1I_PARTITIONS 1
114/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117#define L1I_LINES_PER_TAG 1
118#define L1I_SIZE_KB_AMD 64
119#define L1I_ASSOCIATIVITY_AMD 2
120
121/* Level 2 unified cache: */
122#define L2_LINE_SIZE 64
123#define L2_ASSOCIATIVITY 16
124#define L2_SETS 4096
125#define L2_PARTITIONS 1
126/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130#define L2_LINES_PER_TAG 1
131#define L2_SIZE_KB_AMD 512
132
133/* No L3 cache: */
134#define L3_SIZE_KB 0 /* disabled */
135#define L3_ASSOCIATIVITY 0 /* disabled */
136#define L3_LINES_PER_TAG 0 /* disabled */
137#define L3_LINE_SIZE 0 /* disabled */
138
139/* TLB definitions: */
140
141#define L1_DTLB_2M_ASSOC 1
142#define L1_DTLB_2M_ENTRIES 255
143#define L1_DTLB_4K_ASSOC 1
144#define L1_DTLB_4K_ENTRIES 255
145
146#define L1_ITLB_2M_ASSOC 1
147#define L1_ITLB_2M_ENTRIES 255
148#define L1_ITLB_4K_ASSOC 1
149#define L1_ITLB_4K_ENTRIES 255
150
151#define L2_DTLB_2M_ASSOC 0 /* disabled */
152#define L2_DTLB_2M_ENTRIES 0 /* disabled */
153#define L2_DTLB_4K_ASSOC 4
154#define L2_DTLB_4K_ENTRIES 512
155
156#define L2_ITLB_2M_ASSOC 0 /* disabled */
157#define L2_ITLB_2M_ENTRIES 0 /* disabled */
158#define L2_ITLB_4K_ASSOC 4
159#define L2_ITLB_4K_ENTRIES 512
160
161
162
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163static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165{
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173}
174
c6dc6f63
AP
175/* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188};
189static const char *ext_feature_name[] = {
f370be3c 190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 191 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 192 "tm2", "ssse3", "cid", NULL,
e117f772 193 "fma", "cx16", "xtpr", "pdcm",
434acb81 194 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 196 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 197 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 198};
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EH
199/* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
c6dc6f63 204static const char *ext2_feature_name[] = {
3b671a40
EH
205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 212 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP
213};
214static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 217 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP
218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP
222 NULL, NULL, NULL, NULL,
223};
224
89e49c8b
EH
225static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234};
235
c6dc6f63 236static const char *kvm_feature_name[] = {
c3d39807 237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS
239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
c6dc6f63
AP
245};
246
296acb64
JR
247static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256};
257
a9321a4d 258static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH
259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA
262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263};
264
5ef57876
EH
265typedef struct FeatureWordInfo {
266 const char **feat_names;
04d104b6
EH
267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
5ef57876
EH
271} FeatureWordInfo;
272
273static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH
274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
89e49c8b
EH
290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
bffd67b0
EH
294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH
304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
bffd67b0 307 },
5ef57876
EH
308};
309
8e8aba50
EH
310typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315} X86RegisterInfo32;
316
317#define REGISTER(reg) \
318 [R_##reg] = { .name = #reg, .qapi_enum = X86_C_P_U_REGISTER32_##reg }
319X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328};
329#undef REGISTER
330
2560f19f
PB
331typedef struct ExtSaveArea {
332 uint32_t feature, bits;
333 uint32_t offset, size;
334} ExtSaveArea;
335
336static const ExtSaveArea ext_save_areas[] = {
337 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
338 .offset = 0x100, .size = 0x240 },
339};
8e8aba50 340
8b4beddc
EH
341const char *get_register_name_32(unsigned int reg)
342{
31ccdde2 343 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH
344 return NULL;
345 }
8e8aba50 346 return x86_reg_info_32[reg].name;
8b4beddc
EH
347}
348
c6dc6f63
AP
349/* collects per-function cpuid data
350 */
351typedef struct model_features_t {
352 uint32_t *guest_feat;
353 uint32_t *host_feat;
bffd67b0 354 FeatureWord feat_word;
8b4beddc 355} model_features_t;
c6dc6f63
AP
356
357int check_cpuid = 0;
358int enforce_cpuid = 0;
359
dc59944b
MT
360static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
361 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT
362 (1 << KVM_FEATURE_CLOCKSOURCE2) |
363 (1 << KVM_FEATURE_ASYNC_PF) |
364 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 365 (1 << KVM_FEATURE_PV_EOI) |
dc59944b 366 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
dc59944b 367
29694758 368void disable_kvm_pv_eoi(void)
dc59944b 369{
29694758 370 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
dc59944b
MT
371}
372
bb44e0d1
JK
373void host_cpuid(uint32_t function, uint32_t count,
374 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP
375{
376#if defined(CONFIG_KVM)
a1fd24af
AL
377 uint32_t vec[4];
378
379#ifdef __x86_64__
380 asm volatile("cpuid"
381 : "=a"(vec[0]), "=b"(vec[1]),
382 "=c"(vec[2]), "=d"(vec[3])
383 : "0"(function), "c"(count) : "cc");
384#else
385 asm volatile("pusha \n\t"
386 "cpuid \n\t"
387 "mov %%eax, 0(%2) \n\t"
388 "mov %%ebx, 4(%2) \n\t"
389 "mov %%ecx, 8(%2) \n\t"
390 "mov %%edx, 12(%2) \n\t"
391 "popa"
392 : : "a"(function), "c"(count), "S"(vec)
393 : "memory", "cc");
394#endif
395
bdde476a 396 if (eax)
a1fd24af 397 *eax = vec[0];
bdde476a 398 if (ebx)
a1fd24af 399 *ebx = vec[1];
bdde476a 400 if (ecx)
a1fd24af 401 *ecx = vec[2];
bdde476a 402 if (edx)
a1fd24af 403 *edx = vec[3];
bdde476a
AP
404#endif
405}
c6dc6f63
AP
406
407#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
408
409/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
410 * a substring. ex if !NULL points to the first char after a substring,
411 * otherwise the string is assumed to sized by a terminating nul.
412 * Return lexical ordering of *s1:*s2.
413 */
414static int sstrcmp(const char *s1, const char *e1, const char *s2,
415 const char *e2)
416{
417 for (;;) {
418 if (!*s1 || !*s2 || *s1 != *s2)
419 return (*s1 - *s2);
420 ++s1, ++s2;
421 if (s1 == e1 && s2 == e2)
422 return (0);
423 else if (s1 == e1)
424 return (*s2);
425 else if (s2 == e2)
426 return (*s1);
427 }
428}
429
430/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
431 * '|' delimited (possibly empty) strings in which case search for a match
432 * within the alternatives proceeds left to right. Return 0 for success,
433 * non-zero otherwise.
434 */
435static int altcmp(const char *s, const char *e, const char *altstr)
436{
437 const char *p, *q;
438
439 for (q = p = altstr; ; ) {
440 while (*p && *p != '|')
441 ++p;
442 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
443 return (0);
444 if (!*p)
445 return (1);
446 else
447 q = ++p;
448 }
449}
450
451/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 452 * *pval and return true, otherwise return false
c6dc6f63 453 */
e41e0fc6
JK
454static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
455 const char **featureset)
c6dc6f63
AP
456{
457 uint32_t mask;
458 const char **ppc;
e41e0fc6 459 bool found = false;
c6dc6f63 460
e41e0fc6 461 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP
462 if (*ppc && !altcmp(s, e, *ppc)) {
463 *pval |= mask;
e41e0fc6 464 found = true;
c6dc6f63 465 }
e41e0fc6
JK
466 }
467 return found;
c6dc6f63
AP
468}
469
5ef57876
EH
470static void add_flagname_to_bitmaps(const char *flagname,
471 FeatureWordArray words)
c6dc6f63 472{
5ef57876
EH
473 FeatureWord w;
474 for (w = 0; w < FEATURE_WORDS; w++) {
475 FeatureWordInfo *wi = &feature_word_info[w];
476 if (wi->feat_names &&
477 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
478 break;
479 }
480 }
481 if (w == FEATURE_WORDS) {
482 fprintf(stderr, "CPU feature %s not found\n", flagname);
483 }
c6dc6f63
AP
484}
485
486typedef struct x86_def_t {
c6dc6f63
AP
487 const char *name;
488 uint32_t level;
90e4b0c3
EH
489 uint32_t xlevel;
490 uint32_t xlevel2;
99b88a17
IM
491 /* vendor is zero-terminated, 12 character ASCII string */
492 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP
493 int family;
494 int model;
495 int stepping;
0514ef2f 496 FeatureWordArray features;
c6dc6f63 497 char model_id[48];
787aaf57 498 bool cache_info_passthrough;
c6dc6f63
AP
499} x86_def_t;
500
501#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
502#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
503 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
504#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
505 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
506 CPUID_PSE36 | CPUID_FXSR)
507#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
508#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
509 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
510 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
511 CPUID_PAE | CPUID_SEP | CPUID_APIC)
512
551a2dec
AP
513#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
514 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
515 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
516 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
517 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ
518 /* partly implemented:
519 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
520 CPUID_PSE36 (needed for Solaris) */
521 /* missing:
522 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
e71827bc
AJ
523#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
524 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
525 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
d640045a 526 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
8560efed 527 /* missing:
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528 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
529 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
530 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
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531 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
532 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
83f7dc28 533 CPUID_EXT_RDRAND */
60032ac0 534#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
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535 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
536 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
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537 /* missing:
538 CPUID_EXT2_PDPE1GB */
551a2dec
AP
539#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
540 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 541#define TCG_SVM_FEATURES 0
7073fbad 542#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
cd7f97ca 543 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
111994ee 544 /* missing:
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545 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
546 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
cd7f97ca 547 CPUID_7_0_EBX_RDSEED */
551a2dec 548
7fc9b714 549/* built-in CPU model definitions
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550 */
551static x86_def_t builtin_x86_defs[] = {
c6dc6f63
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552 {
553 .name = "qemu64",
554 .level = 4,
99b88a17 555 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 556 .family = 6,
f8e6a11a 557 .model = 6,
c6dc6f63 558 .stepping = 3,
0514ef2f 559 .features[FEAT_1_EDX] =
27861ecc 560 PPRO_FEATURES |
c6dc6f63 561 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 562 CPUID_PSE36,
0514ef2f 563 .features[FEAT_1_ECX] =
27861ecc 564 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 565 .features[FEAT_8000_0001_EDX] =
27861ecc 566 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 567 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 568 .features[FEAT_8000_0001_ECX] =
27861ecc 569 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
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570 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
571 .xlevel = 0x8000000A,
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572 },
573 {
574 .name = "phenom",
575 .level = 5,
99b88a17 576 .vendor = CPUID_VENDOR_AMD,
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AP
577 .family = 16,
578 .model = 2,
579 .stepping = 3,
0514ef2f 580 .features[FEAT_1_EDX] =
27861ecc 581 PPRO_FEATURES |
c6dc6f63 582 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 583 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 584 .features[FEAT_1_ECX] =
27861ecc 585 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 586 CPUID_EXT_POPCNT,
0514ef2f 587 .features[FEAT_8000_0001_EDX] =
27861ecc 588 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
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589 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
590 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 591 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
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592 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
593 CPUID_EXT3_CR8LEG,
594 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
595 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 596 .features[FEAT_8000_0001_ECX] =
27861ecc 597 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 598 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 599 .features[FEAT_SVM] =
27861ecc 600 CPUID_SVM_NPT | CPUID_SVM_LBRV,
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601 .xlevel = 0x8000001A,
602 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
603 },
604 {
605 .name = "core2duo",
606 .level = 10,
99b88a17 607 .vendor = CPUID_VENDOR_INTEL,
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608 .family = 6,
609 .model = 15,
610 .stepping = 11,
0514ef2f 611 .features[FEAT_1_EDX] =
27861ecc 612 PPRO_FEATURES |
c6dc6f63 613 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
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614 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
615 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 616 .features[FEAT_1_ECX] =
27861ecc 617 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
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618 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
619 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 620 .features[FEAT_8000_0001_EDX] =
27861ecc 621 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 622 .features[FEAT_8000_0001_ECX] =
27861ecc 623 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP
624 .xlevel = 0x80000008,
625 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
626 },
627 {
628 .name = "kvm64",
629 .level = 5,
99b88a17 630 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
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631 .family = 15,
632 .model = 6,
633 .stepping = 1,
634 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 635 .features[FEAT_1_EDX] =
27861ecc 636 PPRO_FEATURES |
c6dc6f63
AP
637 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
638 CPUID_PSE36,
639 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 640 .features[FEAT_1_ECX] =
27861ecc 641 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 642 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 643 .features[FEAT_8000_0001_EDX] =
27861ecc 644 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP
645 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
646 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
647 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
648 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
649 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 650 .features[FEAT_8000_0001_ECX] =
27861ecc 651 0,
c6dc6f63
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652 .xlevel = 0x80000008,
653 .model_id = "Common KVM processor"
654 },
c6dc6f63
AP
655 {
656 .name = "qemu32",
657 .level = 4,
99b88a17 658 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 659 .family = 6,
f8e6a11a 660 .model = 6,
c6dc6f63 661 .stepping = 3,
0514ef2f 662 .features[FEAT_1_EDX] =
27861ecc 663 PPRO_FEATURES,
0514ef2f 664 .features[FEAT_1_ECX] =
27861ecc 665 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 666 .xlevel = 0x80000004,
c6dc6f63 667 },
eafaf1e5
AP
668 {
669 .name = "kvm32",
670 .level = 5,
99b88a17 671 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP
672 .family = 15,
673 .model = 6,
674 .stepping = 1,
0514ef2f 675 .features[FEAT_1_EDX] =
27861ecc 676 PPRO_FEATURES |
eafaf1e5 677 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 678 .features[FEAT_1_ECX] =
27861ecc 679 CPUID_EXT_SSE3,
0514ef2f 680 .features[FEAT_8000_0001_EDX] =
27861ecc 681 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 682 .features[FEAT_8000_0001_ECX] =
27861ecc 683 0,
eafaf1e5
AP
684 .xlevel = 0x80000008,
685 .model_id = "Common 32-bit KVM processor"
686 },
c6dc6f63
AP
687 {
688 .name = "coreduo",
689 .level = 10,
99b88a17 690 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP
691 .family = 6,
692 .model = 14,
693 .stepping = 8,
0514ef2f 694 .features[FEAT_1_EDX] =
27861ecc 695 PPRO_FEATURES | CPUID_VME |
8560efed
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696 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
697 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 698 .features[FEAT_1_ECX] =
27861ecc 699 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 700 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 701 .features[FEAT_8000_0001_EDX] =
27861ecc 702 CPUID_EXT2_NX,
c6dc6f63
AP
703 .xlevel = 0x80000008,
704 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
705 },
706 {
707 .name = "486",
58012d66 708 .level = 1,
99b88a17 709 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 710 .family = 4,
b2a856d9 711 .model = 8,
c6dc6f63 712 .stepping = 0,
0514ef2f 713 .features[FEAT_1_EDX] =
27861ecc 714 I486_FEATURES,
c6dc6f63
AP
715 .xlevel = 0,
716 },
717 {
718 .name = "pentium",
719 .level = 1,
99b88a17 720 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP
721 .family = 5,
722 .model = 4,
723 .stepping = 3,
0514ef2f 724 .features[FEAT_1_EDX] =
27861ecc 725 PENTIUM_FEATURES,
c6dc6f63
AP
726 .xlevel = 0,
727 },
728 {
729 .name = "pentium2",
730 .level = 2,
99b88a17 731 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP
732 .family = 6,
733 .model = 5,
734 .stepping = 2,
0514ef2f 735 .features[FEAT_1_EDX] =
27861ecc 736 PENTIUM2_FEATURES,
c6dc6f63
AP
737 .xlevel = 0,
738 },
739 {
740 .name = "pentium3",
741 .level = 2,
99b88a17 742 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP
743 .family = 6,
744 .model = 7,
745 .stepping = 3,
0514ef2f 746 .features[FEAT_1_EDX] =
27861ecc 747 PENTIUM3_FEATURES,
c6dc6f63
AP
748 .xlevel = 0,
749 },
750 {
751 .name = "athlon",
752 .level = 2,
99b88a17 753 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP
754 .family = 6,
755 .model = 2,
756 .stepping = 3,
0514ef2f 757 .features[FEAT_1_EDX] =
27861ecc 758 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 759 CPUID_MCA,
0514ef2f 760 .features[FEAT_8000_0001_EDX] =
27861ecc 761 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 762 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 763 .xlevel = 0x80000008,
c6dc6f63
AP
764 },
765 {
766 .name = "n270",
767 /* original is on level 10 */
768 .level = 5,
99b88a17 769 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP
770 .family = 6,
771 .model = 28,
772 .stepping = 2,
0514ef2f 773 .features[FEAT_1_EDX] =
27861ecc 774 PPRO_FEATURES |
8560efed
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775 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
776 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 777 /* Some CPUs got no CPUID_SEP */
0514ef2f 778 .features[FEAT_1_ECX] =
27861ecc 779 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP
780 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
781 CPUID_EXT_MOVBE,
0514ef2f 782 .features[FEAT_8000_0001_EDX] =
27861ecc 783 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 784 CPUID_EXT2_NX,
0514ef2f 785 .features[FEAT_8000_0001_ECX] =
27861ecc 786 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP
787 .xlevel = 0x8000000A,
788 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
789 },
3eca4642
EH
790 {
791 .name = "Conroe",
6b11322e 792 .level = 4,
99b88a17 793 .vendor = CPUID_VENDOR_INTEL,
3eca4642 794 .family = 6,
ffce9ebb 795 .model = 15,
3eca4642 796 .stepping = 3,
0514ef2f 797 .features[FEAT_1_EDX] =
27861ecc 798 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH
799 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
800 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
801 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
802 CPUID_DE | CPUID_FP87,
0514ef2f 803 .features[FEAT_1_ECX] =
27861ecc 804 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 805 .features[FEAT_8000_0001_EDX] =
27861ecc 806 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 807 .features[FEAT_8000_0001_ECX] =
27861ecc 808 CPUID_EXT3_LAHF_LM,
3eca4642
EH
809 .xlevel = 0x8000000A,
810 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
811 },
812 {
813 .name = "Penryn",
6b11322e 814 .level = 4,
99b88a17 815 .vendor = CPUID_VENDOR_INTEL,
3eca4642 816 .family = 6,
ffce9ebb 817 .model = 23,
3eca4642 818 .stepping = 3,
0514ef2f 819 .features[FEAT_1_EDX] =
27861ecc 820 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH
821 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
822 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
823 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
824 CPUID_DE | CPUID_FP87,
0514ef2f 825 .features[FEAT_1_ECX] =
27861ecc 826 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 827 CPUID_EXT_SSE3,
0514ef2f 828 .features[FEAT_8000_0001_EDX] =
27861ecc 829 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 830 .features[FEAT_8000_0001_ECX] =
27861ecc 831 CPUID_EXT3_LAHF_LM,
3eca4642
EH
832 .xlevel = 0x8000000A,
833 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
834 },
835 {
836 .name = "Nehalem",
6b11322e 837 .level = 4,
99b88a17 838 .vendor = CPUID_VENDOR_INTEL,
3eca4642 839 .family = 6,
ffce9ebb 840 .model = 26,
3eca4642 841 .stepping = 3,
0514ef2f 842 .features[FEAT_1_EDX] =
27861ecc 843 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH
844 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
845 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
846 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
847 CPUID_DE | CPUID_FP87,
0514ef2f 848 .features[FEAT_1_ECX] =
27861ecc 849 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 850 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 851 .features[FEAT_8000_0001_EDX] =
27861ecc 852 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 853 .features[FEAT_8000_0001_ECX] =
27861ecc 854 CPUID_EXT3_LAHF_LM,
3eca4642
EH
855 .xlevel = 0x8000000A,
856 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
857 },
858 {
859 .name = "Westmere",
860 .level = 11,
99b88a17 861 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH
862 .family = 6,
863 .model = 44,
864 .stepping = 1,
0514ef2f 865 .features[FEAT_1_EDX] =
27861ecc 866 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH
867 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
868 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
869 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
870 CPUID_DE | CPUID_FP87,
0514ef2f 871 .features[FEAT_1_ECX] =
27861ecc 872 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 873 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 874 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 875 .features[FEAT_8000_0001_EDX] =
27861ecc 876 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 877 .features[FEAT_8000_0001_ECX] =
27861ecc 878 CPUID_EXT3_LAHF_LM,
3eca4642
EH
879 .xlevel = 0x8000000A,
880 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
881 },
882 {
883 .name = "SandyBridge",
884 .level = 0xd,
99b88a17 885 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH
886 .family = 6,
887 .model = 42,
888 .stepping = 1,
0514ef2f 889 .features[FEAT_1_EDX] =
27861ecc 890 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH
891 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
892 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
893 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
894 CPUID_DE | CPUID_FP87,
0514ef2f 895 .features[FEAT_1_ECX] =
27861ecc 896 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH
897 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
898 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
899 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
900 CPUID_EXT_SSE3,
0514ef2f 901 .features[FEAT_8000_0001_EDX] =
27861ecc 902 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 903 CPUID_EXT2_SYSCALL,
0514ef2f 904 .features[FEAT_8000_0001_ECX] =
27861ecc 905 CPUID_EXT3_LAHF_LM,
3eca4642
EH
906 .xlevel = 0x8000000A,
907 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
908 },
37507094
EH
909 {
910 .name = "Haswell",
911 .level = 0xd,
99b88a17 912 .vendor = CPUID_VENDOR_INTEL,
37507094
EH
913 .family = 6,
914 .model = 60,
915 .stepping = 1,
0514ef2f 916 .features[FEAT_1_EDX] =
27861ecc 917 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 918 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 919 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH
920 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
921 CPUID_DE | CPUID_FP87,
0514ef2f 922 .features[FEAT_1_ECX] =
27861ecc 923 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH
924 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
925 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
926 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
927 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
928 CPUID_EXT_PCID,
0514ef2f 929 .features[FEAT_8000_0001_EDX] =
27861ecc 930 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 931 CPUID_EXT2_SYSCALL,
0514ef2f 932 .features[FEAT_8000_0001_ECX] =
27861ecc 933 CPUID_EXT3_LAHF_LM,
0514ef2f 934 .features[FEAT_7_0_EBX] =
27861ecc 935 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH
936 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
937 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
938 CPUID_7_0_EBX_RTM,
939 .xlevel = 0x8000000A,
940 .model_id = "Intel Core Processor (Haswell)",
941 },
3eca4642
EH
942 {
943 .name = "Opteron_G1",
944 .level = 5,
99b88a17 945 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH
946 .family = 15,
947 .model = 6,
948 .stepping = 1,
0514ef2f 949 .features[FEAT_1_EDX] =
27861ecc 950 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH
951 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
952 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
953 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
954 CPUID_DE | CPUID_FP87,
0514ef2f 955 .features[FEAT_1_ECX] =
27861ecc 956 CPUID_EXT_SSE3,
0514ef2f 957 .features[FEAT_8000_0001_EDX] =
27861ecc 958 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH
959 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
960 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
961 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
962 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
963 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
964 .xlevel = 0x80000008,
965 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
966 },
967 {
968 .name = "Opteron_G2",
969 .level = 5,
99b88a17 970 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH
971 .family = 15,
972 .model = 6,
973 .stepping = 1,
0514ef2f 974 .features[FEAT_1_EDX] =
27861ecc 975 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH
976 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
977 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
978 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
979 CPUID_DE | CPUID_FP87,
0514ef2f 980 .features[FEAT_1_ECX] =
27861ecc 981 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 982 .features[FEAT_8000_0001_EDX] =
27861ecc 983 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH
984 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
985 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
986 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
987 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
988 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
989 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 990 .features[FEAT_8000_0001_ECX] =
27861ecc 991 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH
992 .xlevel = 0x80000008,
993 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
994 },
995 {
996 .name = "Opteron_G3",
997 .level = 5,
99b88a17 998 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH
999 .family = 15,
1000 .model = 6,
1001 .stepping = 1,
0514ef2f 1002 .features[FEAT_1_EDX] =
27861ecc 1003 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH
1004 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1005 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1006 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1007 CPUID_DE | CPUID_FP87,
0514ef2f 1008 .features[FEAT_1_ECX] =
27861ecc 1009 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1010 CPUID_EXT_SSE3,
0514ef2f 1011 .features[FEAT_8000_0001_EDX] =
27861ecc 1012 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH
1013 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1014 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1015 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1016 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1017 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1018 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1019 .features[FEAT_8000_0001_ECX] =
27861ecc 1020 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH
1021 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1022 .xlevel = 0x80000008,
1023 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1024 },
1025 {
1026 .name = "Opteron_G4",
1027 .level = 0xd,
99b88a17 1028 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH
1029 .family = 21,
1030 .model = 1,
1031 .stepping = 2,
0514ef2f 1032 .features[FEAT_1_EDX] =
27861ecc 1033 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH
1034 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1035 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1036 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1037 CPUID_DE | CPUID_FP87,
0514ef2f 1038 .features[FEAT_1_ECX] =
27861ecc 1039 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH
1040 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1041 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1042 CPUID_EXT_SSE3,
0514ef2f 1043 .features[FEAT_8000_0001_EDX] =
27861ecc 1044 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH
1045 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1046 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1047 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1048 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1049 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1050 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1051 .features[FEAT_8000_0001_ECX] =
27861ecc 1052 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH
1053 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1054 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1055 CPUID_EXT3_LAHF_LM,
1056 .xlevel = 0x8000001A,
1057 .model_id = "AMD Opteron 62xx class CPU",
1058 },
021941b9
AP
1059 {
1060 .name = "Opteron_G5",
1061 .level = 0xd,
99b88a17 1062 .vendor = CPUID_VENDOR_AMD,
021941b9
AP
1063 .family = 21,
1064 .model = 2,
1065 .stepping = 0,
0514ef2f 1066 .features[FEAT_1_EDX] =
27861ecc 1067 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP
1068 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1069 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1070 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1071 CPUID_DE | CPUID_FP87,
0514ef2f 1072 .features[FEAT_1_ECX] =
27861ecc 1073 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP
1074 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1075 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1076 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1077 .features[FEAT_8000_0001_EDX] =
27861ecc 1078 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP
1079 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1080 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1081 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1082 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1083 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1084 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1085 .features[FEAT_8000_0001_ECX] =
27861ecc 1086 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP
1087 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1088 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1089 CPUID_EXT3_LAHF_LM,
1090 .xlevel = 0x8000001A,
1091 .model_id = "AMD Opteron 63xx class CPU",
1092 },
c6dc6f63
AP
1093};
1094
0668af54
EH
1095/**
1096 * x86_cpu_compat_set_features:
1097 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1098 * @w: Identifies the feature word to be changed.
1099 * @feat_add: Feature bits to be added to feature word
1100 * @feat_remove: Feature bits to be removed from feature word
1101 *
1102 * Change CPU model feature bits for compatibility.
1103 *
1104 * This function may be used by machine-type compatibility functions
1105 * to enable or disable feature bits on specific CPU models.
1106 */
1107void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1108 uint32_t feat_add, uint32_t feat_remove)
1109{
1110 x86_def_t *def;
1111 int i;
1112 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1113 def = &builtin_x86_defs[i];
1114 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1115 def->features[w] |= feat_add;
1116 def->features[w] &= ~feat_remove;
1117 }
1118 }
1119}
1120
e4ab0d6b 1121#ifdef CONFIG_KVM
c6dc6f63
AP
1122static int cpu_x86_fill_model_id(char *str)
1123{
1124 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1125 int i;
1126
1127 for (i = 0; i < 3; i++) {
1128 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1129 memcpy(str + i * 16 + 0, &eax, 4);
1130 memcpy(str + i * 16 + 4, &ebx, 4);
1131 memcpy(str + i * 16 + 8, &ecx, 4);
1132 memcpy(str + i * 16 + 12, &edx, 4);
1133 }
1134 return 0;
1135}
e4ab0d6b 1136#endif
c6dc6f63 1137
6e746f30
EH
1138/* Fill a x86_def_t struct with information about the host CPU, and
1139 * the CPU features supported by the host hardware + host kernel
1140 *
1141 * This function may be called only if KVM is enabled.
1142 */
1143static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 1144{
e4ab0d6b 1145#ifdef CONFIG_KVM
12869995 1146 KVMState *s = kvm_state;
c6dc6f63
AP
1147 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1148
6e746f30
EH
1149 assert(kvm_enabled());
1150
c6dc6f63 1151 x86_cpu_def->name = "host";
787aaf57 1152 x86_cpu_def->cache_info_passthrough = true;
c6dc6f63 1153 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
99b88a17 1154 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
c6dc6f63
AP
1155
1156 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1157 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1158 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1159 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 1160
12869995 1161 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
0514ef2f 1162 x86_cpu_def->features[FEAT_1_EDX] =
27861ecc 1163 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
0514ef2f 1164 x86_cpu_def->features[FEAT_1_ECX] =
27861ecc 1165 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 1166
6e746f30 1167 if (x86_cpu_def->level >= 7) {
0514ef2f 1168 x86_cpu_def->features[FEAT_7_0_EBX] =
12869995 1169 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728 1170 } else {
0514ef2f 1171 x86_cpu_def->features[FEAT_7_0_EBX] = 0;
13526728
EH
1172 }
1173
12869995 1174 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
0514ef2f 1175 x86_cpu_def->features[FEAT_8000_0001_EDX] =
12869995 1176 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
0514ef2f 1177 x86_cpu_def->features[FEAT_8000_0001_ECX] =
12869995 1178 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 1179
c6dc6f63 1180 cpu_x86_fill_model_id(x86_cpu_def->model_id);
c6dc6f63 1181
b3baa152 1182 /* Call Centaur's CPUID instruction. */
99b88a17 1183 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
b3baa152 1184 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
12869995 1185 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
b3baa152
BW
1186 if (eax >= 0xC0000001) {
1187 /* Support VIA max extended level */
1188 x86_cpu_def->xlevel2 = eax;
1189 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
0514ef2f 1190 x86_cpu_def->features[FEAT_C000_0001_EDX] =
12869995 1191 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
b3baa152
BW
1192 }
1193 }
296acb64 1194
fcb93c03 1195 /* Other KVM-specific feature fields: */
0514ef2f 1196 x86_cpu_def->features[FEAT_SVM] =
fcb93c03 1197 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
0514ef2f 1198 x86_cpu_def->features[FEAT_KVM] =
bd004bef 1199 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 1200
e4ab0d6b 1201#endif /* CONFIG_KVM */
c6dc6f63
AP
1202}
1203
bffd67b0 1204static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP
1205{
1206 int i;
1207
1208 for (i = 0; i < 32; ++i)
1209 if (1 << i & mask) {
bffd67b0 1210 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH
1211 assert(reg);
1212 fprintf(stderr, "warning: host doesn't support requested feature: "
1213 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH
1214 f->cpuid_eax, reg,
1215 f->feat_names[i] ? "." : "",
1216 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP
1217 break;
1218 }
1219 return 0;
1220}
1221
07ca5945
EH
1222/* Check if all requested cpu flags are making their way to the guest
1223 *
1224 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH
1225 *
1226 * This function may be called only if KVM is enabled.
c6dc6f63 1227 */
5ec01c2e 1228static int kvm_check_features_against_host(X86CPU *cpu)
c6dc6f63 1229{
5ec01c2e 1230 CPUX86State *env = &cpu->env;
c6dc6f63
AP
1231 x86_def_t host_def;
1232 uint32_t mask;
1233 int rv, i;
1234 struct model_features_t ft[] = {
0514ef2f
EH
1235 {&env->features[FEAT_1_EDX],
1236 &host_def.features[FEAT_1_EDX],
bffd67b0 1237 FEAT_1_EDX },
0514ef2f
EH
1238 {&env->features[FEAT_1_ECX],
1239 &host_def.features[FEAT_1_ECX],
bffd67b0 1240 FEAT_1_ECX },
0514ef2f
EH
1241 {&env->features[FEAT_8000_0001_EDX],
1242 &host_def.features[FEAT_8000_0001_EDX],
bffd67b0 1243 FEAT_8000_0001_EDX },
0514ef2f
EH
1244 {&env->features[FEAT_8000_0001_ECX],
1245 &host_def.features[FEAT_8000_0001_ECX],
bffd67b0 1246 FEAT_8000_0001_ECX },
0514ef2f
EH
1247 {&env->features[FEAT_C000_0001_EDX],
1248 &host_def.features[FEAT_C000_0001_EDX],
07ca5945 1249 FEAT_C000_0001_EDX },
0514ef2f
EH
1250 {&env->features[FEAT_7_0_EBX],
1251 &host_def.features[FEAT_7_0_EBX],
07ca5945 1252 FEAT_7_0_EBX },
0514ef2f
EH
1253 {&env->features[FEAT_SVM],
1254 &host_def.features[FEAT_SVM],
07ca5945 1255 FEAT_SVM },
0514ef2f
EH
1256 {&env->features[FEAT_KVM],
1257 &host_def.features[FEAT_KVM],
07ca5945 1258 FEAT_KVM },
8b4beddc 1259 };
c6dc6f63 1260
6e746f30
EH
1261 assert(kvm_enabled());
1262
1263 kvm_cpu_fill_host(&host_def);
bffd67b0
EH
1264 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1265 FeatureWord w = ft[i].feat_word;
1266 FeatureWordInfo *wi = &feature_word_info[w];
1267 for (mask = 1; mask; mask <<= 1) {
e8beac00 1268 if (*ft[i].guest_feat & mask &&
c6dc6f63 1269 !(*ft[i].host_feat & mask)) {
bffd67b0
EH
1270 unavailable_host_feature(wi, mask);
1271 rv = 1;
1272 }
1273 }
1274 }
c6dc6f63
AP
1275 return rv;
1276}
1277
95b8519d
AF
1278static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1279 const char *name, Error **errp)
1280{
1281 X86CPU *cpu = X86_CPU(obj);
1282 CPUX86State *env = &cpu->env;
1283 int64_t value;
1284
1285 value = (env->cpuid_version >> 8) & 0xf;
1286 if (value == 0xf) {
1287 value += (env->cpuid_version >> 20) & 0xff;
1288 }
1289 visit_type_int(v, &value, name, errp);
1290}
1291
71ad61d3
AF
1292static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1293 const char *name, Error **errp)
ed5e1ec3 1294{
71ad61d3
AF
1295 X86CPU *cpu = X86_CPU(obj);
1296 CPUX86State *env = &cpu->env;
1297 const int64_t min = 0;
1298 const int64_t max = 0xff + 0xf;
1299 int64_t value;
1300
1301 visit_type_int(v, &value, name, errp);
1302 if (error_is_set(errp)) {
1303 return;
1304 }
1305 if (value < min || value > max) {
1306 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1307 name ? name : "null", value, min, max);
1308 return;
1309 }
1310
ed5e1ec3 1311 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF
1312 if (value > 0x0f) {
1313 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1314 } else {
71ad61d3 1315 env->cpuid_version |= value << 8;
ed5e1ec3
AF
1316 }
1317}
1318
67e30c83
AF
1319static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1320 const char *name, Error **errp)
1321{
1322 X86CPU *cpu = X86_CPU(obj);
1323 CPUX86State *env = &cpu->env;
1324 int64_t value;
1325
1326 value = (env->cpuid_version >> 4) & 0xf;
1327 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1328 visit_type_int(v, &value, name, errp);
1329}
1330
c5291a4f
AF
1331static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1332 const char *name, Error **errp)
b0704cbd 1333{
c5291a4f
AF
1334 X86CPU *cpu = X86_CPU(obj);
1335 CPUX86State *env = &cpu->env;
1336 const int64_t min = 0;
1337 const int64_t max = 0xff;
1338 int64_t value;
1339
1340 visit_type_int(v, &value, name, errp);
1341 if (error_is_set(errp)) {
1342 return;
1343 }
1344 if (value < min || value > max) {
1345 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1346 name ? name : "null", value, min, max);
1347 return;
1348 }
1349
b0704cbd 1350 env->cpuid_version &= ~0xf00f0;
c5291a4f 1351 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF
1352}
1353
35112e41
AF
1354static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1355 void *opaque, const char *name,
1356 Error **errp)
1357{
1358 X86CPU *cpu = X86_CPU(obj);
1359 CPUX86State *env = &cpu->env;
1360 int64_t value;
1361
1362 value = env->cpuid_version & 0xf;
1363 visit_type_int(v, &value, name, errp);
1364}
1365
036e2222
AF
1366static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1367 void *opaque, const char *name,
1368 Error **errp)
38c3dc46 1369{
036e2222
AF
1370 X86CPU *cpu = X86_CPU(obj);
1371 CPUX86State *env = &cpu->env;
1372 const int64_t min = 0;
1373 const int64_t max = 0xf;
1374 int64_t value;
1375
1376 visit_type_int(v, &value, name, errp);
1377 if (error_is_set(errp)) {
1378 return;
1379 }
1380 if (value < min || value > max) {
1381 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1382 name ? name : "null", value, min, max);
1383 return;
1384 }
1385
38c3dc46 1386 env->cpuid_version &= ~0xf;
036e2222 1387 env->cpuid_version |= value & 0xf;
38c3dc46
AF
1388}
1389
8e1898bf
AF
1390static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1391 const char *name, Error **errp)
1392{
1393 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1394
fa029887 1395 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF
1396}
1397
1398static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1399 const char *name, Error **errp)
1400{
1401 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1402
fa029887 1403 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF
1404}
1405
16b93aa8
AF
1406static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1407 const char *name, Error **errp)
1408{
1409 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1410
fa029887 1411 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF
1412}
1413
1414static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1415 const char *name, Error **errp)
1416{
1417 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1418
fa029887 1419 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF
1420}
1421
d480e1af
AF
1422static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1423{
1424 X86CPU *cpu = X86_CPU(obj);
1425 CPUX86State *env = &cpu->env;
1426 char *value;
d480e1af 1427
9df694ee 1428 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM
1429 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1430 env->cpuid_vendor3);
d480e1af
AF
1431 return value;
1432}
1433
1434static void x86_cpuid_set_vendor(Object *obj, const char *value,
1435 Error **errp)
1436{
1437 X86CPU *cpu = X86_CPU(obj);
1438 CPUX86State *env = &cpu->env;
1439 int i;
1440
9df694ee 1441 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF
1442 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1443 "vendor", value);
1444 return;
1445 }
1446
1447 env->cpuid_vendor1 = 0;
1448 env->cpuid_vendor2 = 0;
1449 env->cpuid_vendor3 = 0;
1450 for (i = 0; i < 4; i++) {
1451 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1452 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1453 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1454 }
d480e1af
AF
1455}
1456
63e886eb
AF
1457static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1458{
1459 X86CPU *cpu = X86_CPU(obj);
1460 CPUX86State *env = &cpu->env;
1461 char *value;
1462 int i;
1463
1464 value = g_malloc(48 + 1);
1465 for (i = 0; i < 48; i++) {
1466 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1467 }
1468 value[48] = '\0';
1469 return value;
1470}
1471
938d4c25
AF
1472static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1473 Error **errp)
dcce6675 1474{
938d4c25
AF
1475 X86CPU *cpu = X86_CPU(obj);
1476 CPUX86State *env = &cpu->env;
dcce6675
AF
1477 int c, len, i;
1478
1479 if (model_id == NULL) {
1480 model_id = "";
1481 }
1482 len = strlen(model_id);
d0a6acf4 1483 memset(env->cpuid_model, 0, 48);
dcce6675
AF
1484 for (i = 0; i < 48; i++) {
1485 if (i >= len) {
1486 c = '\0';
1487 } else {
1488 c = (uint8_t)model_id[i];
1489 }
1490 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1491 }
1492}
1493
89e48965
AF
1494static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1495 const char *name, Error **errp)
1496{
1497 X86CPU *cpu = X86_CPU(obj);
1498 int64_t value;
1499
1500 value = cpu->env.tsc_khz * 1000;
1501 visit_type_int(v, &value, name, errp);
1502}
1503
1504static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1505 const char *name, Error **errp)
1506{
1507 X86CPU *cpu = X86_CPU(obj);
1508 const int64_t min = 0;
2e84849a 1509 const int64_t max = INT64_MAX;
89e48965
AF
1510 int64_t value;
1511
1512 visit_type_int(v, &value, name, errp);
1513 if (error_is_set(errp)) {
1514 return;
1515 }
1516 if (value < min || value > max) {
1517 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1518 name ? name : "null", value, min, max);
1519 return;
1520 }
1521
1522 cpu->env.tsc_khz = value / 1000;
1523}
1524
31050930
IM
1525static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1526 const char *name, Error **errp)
1527{
1528 X86CPU *cpu = X86_CPU(obj);
1529 int64_t value = cpu->env.cpuid_apic_id;
1530
1531 visit_type_int(v, &value, name, errp);
1532}
1533
1534static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1535 const char *name, Error **errp)
1536{
1537 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1538 DeviceState *dev = DEVICE(obj);
31050930
IM
1539 const int64_t min = 0;
1540 const int64_t max = UINT32_MAX;
1541 Error *error = NULL;
1542 int64_t value;
1543
8d6d4980
IM
1544 if (dev->realized) {
1545 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1546 "it was realized", name, object_get_typename(obj));
1547 return;
1548 }
1549
31050930
IM
1550 visit_type_int(v, &value, name, &error);
1551 if (error) {
1552 error_propagate(errp, error);
1553 return;
1554 }
1555 if (value < min || value > max) {
1556 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1557 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1558 object_get_typename(obj), name, value, min, max);
1559 return;
1560 }
1561
1562 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1563 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1564 return;
1565 }
1566 cpu->env.cpuid_apic_id = value;
1567}
1568
7e5292b5 1569/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH
1570static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1571 const char *name, Error **errp)
1572{
7e5292b5 1573 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH
1574 FeatureWord w;
1575 Error *err = NULL;
1576 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1577 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1578 X86CPUFeatureWordInfoList *list = NULL;
1579
1580 for (w = 0; w < FEATURE_WORDS; w++) {
1581 FeatureWordInfo *wi = &feature_word_info[w];
1582 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1583 qwi->cpuid_input_eax = wi->cpuid_eax;
1584 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1585 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1586 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1587 qwi->features = array[w];
8e8aba50
EH
1588
1589 /* List will be in reverse order, but order shouldn't matter */
1590 list_entries[w].next = list;
1591 list_entries[w].value = &word_infos[w];
1592 list = &list_entries[w];
1593 }
1594
1595 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1596 error_propagate(errp, err);
1597}
1598
c1399112
EH
1599static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def,
1600 const char *name)
c6dc6f63 1601{
c6dc6f63 1602 x86_def_t *def;
9337e3b6 1603 Error *err = NULL;
7fc9b714 1604 int i;
c6dc6f63 1605
4bfe910d
AF
1606 if (name == NULL) {
1607 return -1;
9f3fb565 1608 }
4bfe910d 1609 if (kvm_enabled() && strcmp(name, "host") == 0) {
6e746f30 1610 kvm_cpu_fill_host(x86_cpu_def);
9337e3b6
EH
1611 object_property_set_bool(OBJECT(cpu), true, "pmu", &err);
1612 assert_no_error(err);
4bfe910d 1613 return 0;
c6dc6f63
AP
1614 }
1615
7fc9b714
AF
1616 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1617 def = &builtin_x86_defs[i];
4bfe910d
AF
1618 if (strcmp(name, def->name) == 0) {
1619 memcpy(x86_cpu_def, def, sizeof(*def));
11acfdd5
IM
1620 /* sysenter isn't supported in compatibility mode on AMD,
1621 * syscall isn't supported in compatibility mode on Intel.
1622 * Normally we advertise the actual CPU vendor, but you can
1623 * override this using the 'vendor' property if you want to use
1624 * KVM's sysenter/syscall emulation in compatibility mode and
1625 * when doing cross vendor migration
1626 */
1627 if (kvm_enabled()) {
1628 uint32_t ebx = 0, ecx = 0, edx = 0;
1629 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1630 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1631 }
4bfe910d
AF
1632 return 0;
1633 }
1634 }
1635
1636 return -1;
8f961357
EH
1637}
1638
72ac2e87
IM
1639/* Convert all '_' in a feature string option name to '-', to make feature
1640 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1641 */
1642static inline void feat2prop(char *s)
1643{
1644 while ((s = strchr(s, '_'))) {
1645 *s = '-';
1646 }
1647}
1648
8f961357
EH
1649/* Parse "+feature,-feature,feature=foo" CPU feature string
1650 */
a91987c2 1651static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
8f961357 1652{
8f961357
EH
1653 char *featurestr; /* Single 'key=value" string being parsed */
1654 /* Features to be added */
077c68c3 1655 FeatureWordArray plus_features = { 0 };
8f961357 1656 /* Features to be removed */
5ef57876 1657 FeatureWordArray minus_features = { 0 };
8f961357 1658 uint32_t numvalue;
a91987c2 1659 CPUX86State *env = &cpu->env;
8f961357 1660
8f961357 1661 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP
1662
1663 while (featurestr) {
1664 char *val;
1665 if (featurestr[0] == '+') {
5ef57876 1666 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1667 } else if (featurestr[0] == '-') {
5ef57876 1668 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP
1669 } else if ((val = strchr(featurestr, '='))) {
1670 *val = 0; val++;
72ac2e87 1671 feat2prop(featurestr);
c6dc6f63 1672 if (!strcmp(featurestr, "family")) {
a91987c2 1673 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1674 } else if (!strcmp(featurestr, "model")) {
a91987c2 1675 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1676 } else if (!strcmp(featurestr, "stepping")) {
a91987c2 1677 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1678 } else if (!strcmp(featurestr, "level")) {
a91987c2 1679 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63
AP
1680 } else if (!strcmp(featurestr, "xlevel")) {
1681 char *err;
a91987c2
IM
1682 char num[32];
1683
c6dc6f63
AP
1684 numvalue = strtoul(val, &err, 0);
1685 if (!*val || *err) {
312fd5f2 1686 error_setg(errp, "bad numerical value %s", val);
a91987c2 1687 goto out;
c6dc6f63
AP
1688 }
1689 if (numvalue < 0x80000000) {
8ba8a698
IM
1690 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1691 ", fixup will be removed in future versions\n");
2f7a21c4 1692 numvalue += 0x80000000;
c6dc6f63 1693 }
a91987c2
IM
1694 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1695 object_property_parse(OBJECT(cpu), num, featurestr, errp);
c6dc6f63 1696 } else if (!strcmp(featurestr, "vendor")) {
a91987c2 1697 object_property_parse(OBJECT(cpu), val, featurestr, errp);
72ac2e87
IM
1698 } else if (!strcmp(featurestr, "model-id")) {
1699 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1700 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR
1701 int64_t tsc_freq;
1702 char *err;
a91987c2 1703 char num[32];
b862d1fe
JR
1704
1705 tsc_freq = strtosz_suffix_unit(val, &err,
1706 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1707 if (tsc_freq < 0 || *err) {
312fd5f2 1708 error_setg(errp, "bad numerical value %s", val);
a91987c2 1709 goto out;
b862d1fe 1710 }
a91987c2
IM
1711 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1712 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
72ac2e87 1713 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1714 char *err;
92067bf4 1715 const int min = 0xFFF;
28f52cc0
VR
1716 numvalue = strtoul(val, &err, 0);
1717 if (!*val || *err) {
312fd5f2 1718 error_setg(errp, "bad numerical value %s", val);
a91987c2 1719 goto out;
28f52cc0 1720 }
92067bf4
IM
1721 if (numvalue < min) {
1722 fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1723 ", fixup will be removed in future versions\n",
1724 min);
1725 numvalue = min;
1726 }
1727 cpu->hyperv_spinlock_attempts = numvalue;
c6dc6f63 1728 } else {
312fd5f2 1729 error_setg(errp, "unrecognized feature %s", featurestr);
a91987c2 1730 goto out;
c6dc6f63
AP
1731 }
1732 } else if (!strcmp(featurestr, "check")) {
1733 check_cpuid = 1;
1734 } else if (!strcmp(featurestr, "enforce")) {
1735 check_cpuid = enforce_cpuid = 1;
28f52cc0 1736 } else if (!strcmp(featurestr, "hv_relaxed")) {
92067bf4 1737 cpu->hyperv_relaxed_timing = true;
28f52cc0 1738 } else if (!strcmp(featurestr, "hv_vapic")) {
92067bf4 1739 cpu->hyperv_vapic = true;
c6dc6f63 1740 } else {
a91987c2 1741 error_setg(errp, "feature string `%s' not in format (+feature|"
312fd5f2 1742 "-feature|feature=xyz)", featurestr);
a91987c2
IM
1743 goto out;
1744 }
1745 if (error_is_set(errp)) {
1746 goto out;
c6dc6f63
AP
1747 }
1748 featurestr = strtok(NULL, ",");
1749 }
0514ef2f
EH
1750 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1751 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1752 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1753 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1754 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1755 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1756 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1757 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1758 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1759 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1760 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1761 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1762 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1763 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1764 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1765 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63 1766
a91987c2
IM
1767out:
1768 return;
c6dc6f63
AP
1769}
1770
1771/* generate a composite string into buf of all cpuid names in featureset
1772 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1773 * if flags, suppress names undefined in featureset.
1774 */
1775static void listflags(char *buf, int bufsize, uint32_t fbits,
1776 const char **featureset, uint32_t flags)
1777{
1778 const char **p = &featureset[31];
1779 char *q, *b, bit;
1780 int nc;
1781
1782 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1783 *buf = '\0';
1784 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1785 if (fbits & 1 << bit && (*p || !flags)) {
1786 if (*p)
1787 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1788 else
1789 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1790 if (bufsize <= nc) {
1791 if (b) {
1792 memcpy(b, "...", sizeof("..."));
1793 }
1794 return;
1795 }
1796 q += nc;
1797 bufsize -= nc;
1798 }
1799}
1800
e916cbf8
PM
1801/* generate CPU information. */
1802void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1803{
c6dc6f63
AP
1804 x86_def_t *def;
1805 char buf[256];
7fc9b714 1806 int i;
c6dc6f63 1807
7fc9b714
AF
1808 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1809 def = &builtin_x86_defs[i];
c04321b3 1810 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1811 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1812 }
21ad7789
JK
1813#ifdef CONFIG_KVM
1814 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1815 "KVM processor with all supported host features "
1816 "(only available in KVM mode)");
1817#endif
1818
6cdf8854 1819 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK
1820 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1821 FeatureWordInfo *fw = &feature_word_info[i];
1822
1823 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1824 (*cpu_fprintf)(f, " %s\n", buf);
1825 }
c6dc6f63
AP
1826}
1827
76b64a7a 1828CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL
1829{
1830 CpuDefinitionInfoList *cpu_list = NULL;
1831 x86_def_t *def;
7fc9b714 1832 int i;
e3966126 1833
7fc9b714 1834 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL
1835 CpuDefinitionInfoList *entry;
1836 CpuDefinitionInfo *info;
1837
7fc9b714 1838 def = &builtin_x86_defs[i];
e3966126
AL
1839 info = g_malloc0(sizeof(*info));
1840 info->name = g_strdup(def->name);
1841
1842 entry = g_malloc0(sizeof(*entry));
1843 entry->value = info;
1844 entry->next = cpu_list;
1845 cpu_list = entry;
1846 }
1847
1848 return cpu_list;
1849}
1850
bc74b7db
EH
1851#ifdef CONFIG_KVM
1852static void filter_features_for_kvm(X86CPU *cpu)
1853{
1854 CPUX86State *env = &cpu->env;
1855 KVMState *s = kvm_state;
bd87d2a2 1856 FeatureWord w;
bc74b7db 1857
bd87d2a2
EH
1858 for (w = 0; w < FEATURE_WORDS; w++) {
1859 FeatureWordInfo *wi = &feature_word_info[w];
034acf4a
EH
1860 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1861 wi->cpuid_ecx,
1862 wi->cpuid_reg);
1863 uint32_t requested_features = env->features[w];
1864 env->features[w] &= host_feat;
1865 cpu->filtered_features[w] = requested_features & ~env->features[w];
bd87d2a2 1866 }
bc74b7db
EH
1867}
1868#endif
1869
2d64255b 1870static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
c6dc6f63 1871{
61dcd775 1872 CPUX86State *env = &cpu->env;
c6dc6f63
AP
1873 x86_def_t def1, *def = &def1;
1874
db0ad1ba
JR
1875 memset(def, 0, sizeof(*def));
1876
c1399112 1877 if (cpu_x86_find_by_name(cpu, def, name) < 0) {
2d64255b
AF
1878 error_setg(errp, "Unable to find CPU definition: %s", name);
1879 return;
8f961357
EH
1880 }
1881
aa87d458 1882 if (kvm_enabled()) {
0514ef2f 1883 def->features[FEAT_KVM] |= kvm_default_features;
aa87d458 1884 }
0514ef2f 1885 def->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
077c68c3 1886
2d64255b
AF
1887 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1888 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1889 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1890 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1891 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
0514ef2f
EH
1892 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1893 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1894 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1895 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
2d64255b 1896 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
0514ef2f
EH
1897 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1898 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1899 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1900 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
b3baa152 1901 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1902 cpu->cache_info_passthrough = def->cache_info_passthrough;
3b671a40 1903
2d64255b 1904 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
c6dc6f63
AP
1905}
1906
62fc403f
IM
1907X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1908 Error **errp)
5c3c6a68 1909{
2d64255b 1910 X86CPU *cpu = NULL;
2d64255b
AF
1911 gchar **model_pieces;
1912 char *name, *features;
ba2bc7a4 1913 char *typename;
5c3c6a68
AF
1914 Error *error = NULL;
1915
2d64255b
AF
1916 model_pieces = g_strsplit(cpu_model, ",", 2);
1917 if (!model_pieces[0]) {
1918 error_setg(&error, "Invalid/empty CPU model name");
1919 goto out;
1920 }
1921 name = model_pieces[0];
1922 features = model_pieces[1];
1923
5c3c6a68 1924 cpu = X86_CPU(object_new(TYPE_X86_CPU));
62fc403f
IM
1925#ifndef CONFIG_USER_ONLY
1926 if (icc_bridge == NULL) {
1927 error_setg(&error, "Invalid icc-bridge value");
1928 goto out;
1929 }
1930 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1931 object_unref(OBJECT(cpu));
1932#endif
5c3c6a68 1933
2d64255b
AF
1934 cpu_x86_register(cpu, name, &error);
1935 if (error) {
1936 goto out;
1937 }
1938
ba2bc7a4
AF
1939 /* Emulate per-model subclasses for global properties */
1940 typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1941 qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1942 g_free(typename);
1943 if (error) {
1944 goto out;
1945 }
1946
2d64255b
AF
1947 cpu_x86_parse_featurestr(cpu, features, &error);
1948 if (error) {
1949 goto out;
5c3c6a68
AF
1950 }
1951
7f833247 1952out:
cd7b87ff
AF
1953 if (error != NULL) {
1954 error_propagate(errp, error);
1955 object_unref(OBJECT(cpu));
1956 cpu = NULL;
1957 }
7f833247
IM
1958 g_strfreev(model_pieces);
1959 return cpu;
1960}
1961
1962X86CPU *cpu_x86_init(const char *cpu_model)
1963{
1964 Error *error = NULL;
1965 X86CPU *cpu;
1966
62fc403f 1967 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1968 if (error) {
2d64255b
AF
1969 goto out;
1970 }
1971
7f833247
IM
1972 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1973
2d64255b 1974out:
2d64255b 1975 if (error) {
4a44d85e 1976 error_report("%s", error_get_pretty(error));
5c3c6a68 1977 error_free(error);
2d64255b
AF
1978 if (cpu != NULL) {
1979 object_unref(OBJECT(cpu));
1980 cpu = NULL;
1981 }
5c3c6a68
AF
1982 }
1983 return cpu;
1984}
1985
c6dc6f63 1986#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1987
0e26b7b8
BS
1988void cpu_clear_apic_feature(CPUX86State *env)
1989{
0514ef2f 1990 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS
1991}
1992
c6dc6f63
AP
1993#endif /* !CONFIG_USER_ONLY */
1994
c04321b3 1995/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP
1996 */
1997void x86_cpudef_setup(void)
1998{
93bfef4c
CV
1999 int i, j;
2000 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP
2001
2002 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291 2003 x86_def_t *def = &builtin_x86_defs[i];
93bfef4c
CV
2004
2005 /* Look for specific "cpudef" models that */
09faecf2 2006 /* have the QEMU version in .model_id */
93bfef4c 2007 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH
2008 if (strcmp(model_with_versions[j], def->name) == 0) {
2009 pstrcpy(def->model_id, sizeof(def->model_id),
2010 "QEMU Virtual CPU version ");
2011 pstrcat(def->model_id, sizeof(def->model_id),
2012 qemu_get_version());
93bfef4c
CV
2013 break;
2014 }
2015 }
c6dc6f63 2016 }
c6dc6f63
AP
2017}
2018
c6dc6f63
AP
2019static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2020 uint32_t *ecx, uint32_t *edx)
2021{
2022 *ebx = env->cpuid_vendor1;
2023 *edx = env->cpuid_vendor2;
2024 *ecx = env->cpuid_vendor3;
c6dc6f63
AP
2025}
2026
2027void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2028 uint32_t *eax, uint32_t *ebx,
2029 uint32_t *ecx, uint32_t *edx)
2030{
a60f24b5
AF
2031 X86CPU *cpu = x86_env_get_cpu(env);
2032 CPUState *cs = CPU(cpu);
2033
c6dc6f63
AP
2034 /* test if maximum index reached */
2035 if (index & 0x80000000) {
b3baa152
BW
2036 if (index > env->cpuid_xlevel) {
2037 if (env->cpuid_xlevel2 > 0) {
2038 /* Handle the Centaur's CPUID instruction. */
2039 if (index > env->cpuid_xlevel2) {
2040 index = env->cpuid_xlevel2;
2041 } else if (index < 0xC0000000) {
2042 index = env->cpuid_xlevel;
2043 }
2044 } else {
57f26ae7
EH
2045 /* Intel documentation states that invalid EAX input will
2046 * return the same information as EAX=cpuid_level
2047 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2048 */
2049 index = env->cpuid_level;
b3baa152
BW
2050 }
2051 }
c6dc6f63
AP
2052 } else {
2053 if (index > env->cpuid_level)
2054 index = env->cpuid_level;
2055 }
2056
2057 switch(index) {
2058 case 0:
2059 *eax = env->cpuid_level;
2060 get_cpuid_vendor(env, ebx, ecx, edx);
2061 break;
2062 case 1:
2063 *eax = env->cpuid_version;
2064 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH
2065 *ecx = env->features[FEAT_1_ECX];
2066 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF
2067 if (cs->nr_cores * cs->nr_threads > 1) {
2068 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP
2069 *edx |= 1 << 28; /* HTT bit */
2070 }
2071 break;
2072 case 2:
2073 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC
2074 if (cpu->cache_info_passthrough) {
2075 host_cpuid(index, 0, eax, ebx, ecx, edx);
2076 break;
2077 }
5e891bf8 2078 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP
2079 *ebx = 0;
2080 *ecx = 0;
5e891bf8
EH
2081 *edx = (L1D_DESCRIPTOR << 16) | \
2082 (L1I_DESCRIPTOR << 8) | \
2083 (L2_DESCRIPTOR);
c6dc6f63
AP
2084 break;
2085 case 4:
2086 /* cache info: needed for Core compatibility */
787aaf57
BC
2087 if (cpu->cache_info_passthrough) {
2088 host_cpuid(index, count, eax, ebx, ecx, edx);
2089 break;
2090 }
ce3960eb
AF
2091 if (cs->nr_cores > 1) {
2092 *eax = (cs->nr_cores - 1) << 26;
c6dc6f63 2093 } else {
2f7a21c4 2094 *eax = 0;
c6dc6f63
AP
2095 }
2096 switch (count) {
2097 case 0: /* L1 dcache info */
5e891bf8
EH
2098 *eax |= CPUID_4_TYPE_DCACHE | \
2099 CPUID_4_LEVEL(1) | \
2100 CPUID_4_SELF_INIT_LEVEL;
2101 *ebx = (L1D_LINE_SIZE - 1) | \
2102 ((L1D_PARTITIONS - 1) << 12) | \
2103 ((L1D_ASSOCIATIVITY - 1) << 22);
2104 *ecx = L1D_SETS - 1;
2105 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP
2106 break;
2107 case 1: /* L1 icache info */
5e891bf8
EH
2108 *eax |= CPUID_4_TYPE_ICACHE | \
2109 CPUID_4_LEVEL(1) | \
2110 CPUID_4_SELF_INIT_LEVEL;
2111 *ebx = (L1I_LINE_SIZE - 1) | \
2112 ((L1I_PARTITIONS - 1) << 12) | \
2113 ((L1I_ASSOCIATIVITY - 1) << 22);
2114 *ecx = L1I_SETS - 1;
2115 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP
2116 break;
2117 case 2: /* L2 cache info */
5e891bf8
EH
2118 *eax |= CPUID_4_TYPE_UNIFIED | \
2119 CPUID_4_LEVEL(2) | \
2120 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF
2121 if (cs->nr_threads > 1) {
2122 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2123 }
5e891bf8
EH
2124 *ebx = (L2_LINE_SIZE - 1) | \
2125 ((L2_PARTITIONS - 1) << 12) | \
2126 ((L2_ASSOCIATIVITY - 1) << 22);
2127 *ecx = L2_SETS - 1;
2128 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP
2129 break;
2130 default: /* end of info */
2131 *eax = 0;
2132 *ebx = 0;
2133 *ecx = 0;
2134 *edx = 0;
2135 break;
2136 }
2137 break;
2138 case 5:
2139 /* mwait info: needed for Core compatibility */
2140 *eax = 0; /* Smallest monitor-line size in bytes */
2141 *ebx = 0; /* Largest monitor-line size in bytes */
2142 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2143 *edx = 0;
2144 break;
2145 case 6:
2146 /* Thermal and Power Leaf */
2147 *eax = 0;
2148 *ebx = 0;
2149 *ecx = 0;
2150 *edx = 0;
2151 break;
f7911686 2152 case 7:
13526728
EH
2153 /* Structured Extended Feature Flags Enumeration Leaf */
2154 if (count == 0) {
2155 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2156 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH
2157 *ecx = 0; /* Reserved */
2158 *edx = 0; /* Reserved */
f7911686
YW
2159 } else {
2160 *eax = 0;
2161 *ebx = 0;
2162 *ecx = 0;
2163 *edx = 0;
2164 }
2165 break;
c6dc6f63
AP
2166 case 9:
2167 /* Direct Cache Access Information Leaf */
2168 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2169 *ebx = 0;
2170 *ecx = 0;
2171 *edx = 0;
2172 break;
2173 case 0xA:
2174 /* Architectural Performance Monitoring Leaf */
9337e3b6 2175 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2176 KVMState *s = cs->kvm_state;
a0fa8208
GN
2177
2178 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2179 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2180 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2181 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2182 } else {
2183 *eax = 0;
2184 *ebx = 0;
2185 *ecx = 0;
2186 *edx = 0;
2187 }
c6dc6f63 2188 break;
2560f19f
PB
2189 case 0xD: {
2190 KVMState *s = cs->kvm_state;
2191 uint64_t kvm_mask;
2192 int i;
2193
51e49430 2194 /* Processor Extended State */
2560f19f
PB
2195 *eax = 0;
2196 *ebx = 0;
2197 *ecx = 0;
2198 *edx = 0;
2199 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY
2200 break;
2201 }
2560f19f
PB
2202 kvm_mask =
2203 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2204 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2205
2560f19f
PB
2206 if (count == 0) {
2207 *ecx = 0x240;
2208 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2209 const ExtSaveArea *esa = &ext_save_areas[i];
2210 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2211 (kvm_mask & (1 << i)) != 0) {
2212 if (i < 32) {
2213 *eax |= 1 << i;
2214 } else {
2215 *edx |= 1 << (i - 32);
2216 }
2217 *ecx = MAX(*ecx, esa->offset + esa->size);
2218 }
2219 }
2220 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2221 *ebx = *ecx;
2222 } else if (count == 1) {
2223 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2224 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2225 const ExtSaveArea *esa = &ext_save_areas[count];
2226 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2227 (kvm_mask & (1 << count)) != 0) {
2228 *eax = esa->offset;
2229 *ebx = esa->size;
2230 }
51e49430
SY
2231 }
2232 break;
2560f19f 2233 }
c6dc6f63
AP
2234 case 0x80000000:
2235 *eax = env->cpuid_xlevel;
2236 *ebx = env->cpuid_vendor1;
2237 *edx = env->cpuid_vendor2;
2238 *ecx = env->cpuid_vendor3;
2239 break;
2240 case 0x80000001:
2241 *eax = env->cpuid_version;
2242 *ebx = 0;
0514ef2f
EH
2243 *ecx = env->features[FEAT_8000_0001_ECX];
2244 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP
2245
2246 /* The Linux kernel checks for the CMPLegacy bit and
2247 * discards multiple thread information if it is set.
2248 * So dont set it here for Intel to make Linux guests happy.
2249 */
ce3960eb 2250 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP
2251 uint32_t tebx, tecx, tedx;
2252 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2253 if (tebx != CPUID_VENDOR_INTEL_1 ||
2254 tedx != CPUID_VENDOR_INTEL_2 ||
2255 tecx != CPUID_VENDOR_INTEL_3) {
2256 *ecx |= 1 << 1; /* CmpLegacy bit */
2257 }
2258 }
c6dc6f63
AP
2259 break;
2260 case 0x80000002:
2261 case 0x80000003:
2262 case 0x80000004:
2263 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2264 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2265 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2266 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2267 break;
2268 case 0x80000005:
2269 /* cache info (L1 cache) */
787aaf57
BC
2270 if (cpu->cache_info_passthrough) {
2271 host_cpuid(index, 0, eax, ebx, ecx, edx);
2272 break;
2273 }
5e891bf8
EH
2274 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2275 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2276 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2277 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2278 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2279 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2280 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2281 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP
2282 break;
2283 case 0x80000006:
2284 /* cache info (L2 cache) */
787aaf57
BC
2285 if (cpu->cache_info_passthrough) {
2286 host_cpuid(index, 0, eax, ebx, ecx, edx);
2287 break;
2288 }
5e891bf8
EH
2289 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2290 (L2_DTLB_2M_ENTRIES << 16) | \
2291 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2292 (L2_ITLB_2M_ENTRIES);
2293 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2294 (L2_DTLB_4K_ENTRIES << 16) | \
2295 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2296 (L2_ITLB_4K_ENTRIES);
2297 *ecx = (L2_SIZE_KB_AMD << 16) | \
2298 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2299 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2300 *edx = ((L3_SIZE_KB/512) << 18) | \
2301 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2302 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP
2303 break;
2304 case 0x80000008:
2305 /* virtual & phys address size in low 2 bytes. */
2306/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2307 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP
2308 /* 64 bit processor */
2309/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2310 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2311 } else {
0514ef2f 2312 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2313 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2314 } else {
c6dc6f63 2315 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2316 }
c6dc6f63
AP
2317 }
2318 *ebx = 0;
2319 *ecx = 0;
2320 *edx = 0;
ce3960eb
AF
2321 if (cs->nr_cores * cs->nr_threads > 1) {
2322 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP
2323 }
2324 break;
2325 case 0x8000000A:
0514ef2f 2326 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH
2327 *eax = 0x00000001; /* SVM Revision */
2328 *ebx = 0x00000010; /* nr of ASIDs */
2329 *ecx = 0;
0514ef2f 2330 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH
2331 } else {
2332 *eax = 0;
2333 *ebx = 0;
2334 *ecx = 0;
2335 *edx = 0;
2336 }
c6dc6f63 2337 break;
b3baa152
BW
2338 case 0xC0000000:
2339 *eax = env->cpuid_xlevel2;
2340 *ebx = 0;
2341 *ecx = 0;
2342 *edx = 0;
2343 break;
2344 case 0xC0000001:
2345 /* Support for VIA CPU's CPUID instruction */
2346 *eax = env->cpuid_version;
2347 *ebx = 0;
2348 *ecx = 0;
0514ef2f 2349 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW
2350 break;
2351 case 0xC0000002:
2352 case 0xC0000003:
2353 case 0xC0000004:
2354 /* Reserved for the future, and now filled with zero */
2355 *eax = 0;
2356 *ebx = 0;
2357 *ecx = 0;
2358 *edx = 0;
2359 break;
c6dc6f63
AP
2360 default:
2361 /* reserved values: zero */
2362 *eax = 0;
2363 *ebx = 0;
2364 *ecx = 0;
2365 *edx = 0;
2366 break;
2367 }
2368}
5fd2087a
AF
2369
2370/* CPUClass::reset() */
2371static void x86_cpu_reset(CPUState *s)
2372{
2373 X86CPU *cpu = X86_CPU(s);
2374 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2375 CPUX86State *env = &cpu->env;
c1958aea
AF
2376 int i;
2377
5fd2087a
AF
2378 xcc->parent_reset(s);
2379
c1958aea
AF
2380
2381 memset(env, 0, offsetof(CPUX86State, breakpoints));
2382
2383 tlb_flush(env, 1);
2384
2385 env->old_exception = -1;
2386
2387 /* init to reset state */
2388
2389#ifdef CONFIG_SOFTMMU
2390 env->hflags |= HF_SOFTMMU_MASK;
2391#endif
2392 env->hflags2 |= HF2_GIF_MASK;
2393
2394 cpu_x86_update_cr0(env, 0x60000010);
2395 env->a20_mask = ~0x0;
2396 env->smbase = 0x30000;
2397
2398 env->idt.limit = 0xffff;
2399 env->gdt.limit = 0xffff;
2400 env->ldt.limit = 0xffff;
2401 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2402 env->tr.limit = 0xffff;
2403 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2404
2405 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2406 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2407 DESC_R_MASK | DESC_A_MASK);
2408 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2409 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2410 DESC_A_MASK);
2411 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2412 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2413 DESC_A_MASK);
2414 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2415 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2416 DESC_A_MASK);
2417 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2418 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2419 DESC_A_MASK);
2420 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2421 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2422 DESC_A_MASK);
2423
2424 env->eip = 0xfff0;
2425 env->regs[R_EDX] = env->cpuid_version;
2426
2427 env->eflags = 0x2;
2428
2429 /* FPU init */
2430 for (i = 0; i < 8; i++) {
2431 env->fptags[i] = 1;
2432 }
2433 env->fpuc = 0x37f;
2434
2435 env->mxcsr = 0x1f80;
c74f41bb 2436 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF
2437
2438 env->pat = 0x0007040600070406ULL;
2439 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2440
2441 memset(env->dr, 0, sizeof(env->dr));
2442 env->dr[6] = DR6_FIXED_1;
2443 env->dr[7] = DR7_FIXED_1;
2444 cpu_breakpoint_remove_all(env, BP_CPU);
2445 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM
2446
2447#if !defined(CONFIG_USER_ONLY)
2448 /* We hard-wire the BSP to the first CPU. */
55e5c285 2449 if (s->cpu_index == 0) {
dd673288
IM
2450 apic_designate_bsp(env->apic_state);
2451 }
2452
259186a7 2453 s->halted = !cpu_is_bsp(cpu);
dd673288 2454#endif
5fd2087a
AF
2455}
2456
dd673288
IM
2457#ifndef CONFIG_USER_ONLY
2458bool cpu_is_bsp(X86CPU *cpu)
2459{
2460 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2461}
65dee380
IM
2462
2463/* TODO: remove me, when reset over QOM tree is implemented */
2464static void x86_cpu_machine_reset_cb(void *opaque)
2465{
2466 X86CPU *cpu = opaque;
2467 cpu_reset(CPU(cpu));
2468}
dd673288
IM
2469#endif
2470
de024815
AF
2471static void mce_init(X86CPU *cpu)
2472{
2473 CPUX86State *cenv = &cpu->env;
2474 unsigned int bank;
2475
2476 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2477 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF
2478 (CPUID_MCE | CPUID_MCA)) {
2479 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2480 cenv->mcg_ctl = ~(uint64_t)0;
2481 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2482 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2483 }
2484 }
2485}
2486
bdeec802 2487#ifndef CONFIG_USER_ONLY
d3c64d6a 2488static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2489{
bdeec802 2490 CPUX86State *env = &cpu->env;
53a89e26 2491 DeviceState *dev = DEVICE(cpu);
449994eb 2492 APICCommonState *apic;
bdeec802
IM
2493 const char *apic_type = "apic";
2494
2495 if (kvm_irqchip_in_kernel()) {
2496 apic_type = "kvm-apic";
2497 } else if (xen_enabled()) {
2498 apic_type = "xen-apic";
2499 }
2500
53a89e26 2501 env->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
bdeec802
IM
2502 if (env->apic_state == NULL) {
2503 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2504 return;
2505 }
2506
2507 object_property_add_child(OBJECT(cpu), "apic",
2508 OBJECT(env->apic_state), NULL);
2509 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2510 /* TODO: convert to link<> */
449994eb 2511 apic = APIC_COMMON(env->apic_state);
60671e58 2512 apic->cpu = cpu;
d3c64d6a
IM
2513}
2514
2515static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2516{
2517 CPUX86State *env = &cpu->env;
d3c64d6a
IM
2518
2519 if (env->apic_state == NULL) {
2520 return;
2521 }
bdeec802
IM
2522
2523 if (qdev_init(env->apic_state)) {
2524 error_setg(errp, "APIC device '%s' could not be initialized",
2525 object_get_typename(OBJECT(env->apic_state)));
2526 return;
2527 }
bdeec802 2528}
d3c64d6a
IM
2529#else
2530static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2531{
2532}
bdeec802
IM
2533#endif
2534
2b6f294c 2535static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2536{
14a10fc3 2537 CPUState *cs = CPU(dev);
2b6f294c
AF
2538 X86CPU *cpu = X86_CPU(dev);
2539 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2540 CPUX86State *env = &cpu->env;
2b6f294c 2541 Error *local_err = NULL;
b34d12d1 2542
0514ef2f 2543 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM
2544 env->cpuid_level = 7;
2545 }
7a059953 2546
9b15cd9e
IM
2547 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2548 * CPUID[1].EDX.
2549 */
2550 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2551 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2552 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH
2553 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2554 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM
2555 & CPUID_EXT2_AMD_ALIASES);
2556 }
2557
4586f157 2558 if (!kvm_enabled()) {
0514ef2f
EH
2559 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2560 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2561 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
4586f157
IM
2562#ifdef TARGET_X86_64
2563 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2564#endif
2565 );
0514ef2f
EH
2566 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2567 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
4586f157 2568 } else {
5ec01c2e
IM
2569 if (check_cpuid && kvm_check_features_against_host(cpu)
2570 && enforce_cpuid) {
4dc1f449
IM
2571 error_setg(&local_err,
2572 "Host's CPU doesn't support requested features");
2573 goto out;
5ec01c2e 2574 }
a509d632
EH
2575#ifdef CONFIG_KVM
2576 filter_features_for_kvm(cpu);
2577#endif
4586f157
IM
2578 }
2579
65dee380
IM
2580#ifndef CONFIG_USER_ONLY
2581 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2582
0514ef2f 2583 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2584 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2585 if (local_err != NULL) {
4dc1f449 2586 goto out;
bdeec802
IM
2587 }
2588 }
65dee380
IM
2589#endif
2590
7a059953 2591 mce_init(cpu);
14a10fc3 2592 qemu_init_vcpu(cs);
d3c64d6a
IM
2593
2594 x86_cpu_apic_realize(cpu, &local_err);
2595 if (local_err != NULL) {
2596 goto out;
2597 }
14a10fc3 2598 cpu_reset(cs);
2b6f294c 2599
4dc1f449
IM
2600 xcc->parent_realize(dev, &local_err);
2601out:
2602 if (local_err != NULL) {
2603 error_propagate(errp, local_err);
2604 return;
2605 }
7a059953
AF
2606}
2607
8932cfdf
EH
2608/* Enables contiguous-apic-ID mode, for compatibility */
2609static bool compat_apic_id_mode;
2610
2611void enable_compat_apic_id_mode(void)
2612{
2613 compat_apic_id_mode = true;
2614}
2615
cb41bad3
EH
2616/* Calculates initial APIC ID for a specific CPU index
2617 *
2618 * Currently we need to be able to calculate the APIC ID from the CPU index
2619 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2620 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2621 * all CPUs up to max_cpus.
2622 */
2623uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2624{
8932cfdf
EH
2625 uint32_t correct_id;
2626 static bool warned;
2627
2628 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2629 if (compat_apic_id_mode) {
2630 if (cpu_index != correct_id && !warned) {
2631 error_report("APIC IDs set in compatibility mode, "
2632 "CPU topology won't match the configuration");
2633 warned = true;
2634 }
2635 return cpu_index;
2636 } else {
2637 return correct_id;
2638 }
cb41bad3
EH
2639}
2640
de024815
AF
2641static void x86_cpu_initfn(Object *obj)
2642{
55e5c285 2643 CPUState *cs = CPU(obj);
de024815
AF
2644 X86CPU *cpu = X86_CPU(obj);
2645 CPUX86State *env = &cpu->env;
d65e9815 2646 static int inited;
de024815 2647
c05efcb1 2648 cs->env_ptr = env;
de024815 2649 cpu_exec_init(env);
71ad61d3
AF
2650
2651 object_property_add(obj, "family", "int",
95b8519d 2652 x86_cpuid_version_get_family,
71ad61d3 2653 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2654 object_property_add(obj, "model", "int",
67e30c83 2655 x86_cpuid_version_get_model,
c5291a4f 2656 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2657 object_property_add(obj, "stepping", "int",
35112e41 2658 x86_cpuid_version_get_stepping,
036e2222 2659 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF
2660 object_property_add(obj, "level", "int",
2661 x86_cpuid_get_level,
2662 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF
2663 object_property_add(obj, "xlevel", "int",
2664 x86_cpuid_get_xlevel,
2665 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF
2666 object_property_add_str(obj, "vendor",
2667 x86_cpuid_get_vendor,
2668 x86_cpuid_set_vendor, NULL);
938d4c25 2669 object_property_add_str(obj, "model-id",
63e886eb 2670 x86_cpuid_get_model_id,
938d4c25 2671 x86_cpuid_set_model_id, NULL);
89e48965
AF
2672 object_property_add(obj, "tsc-frequency", "int",
2673 x86_cpuid_get_tsc_freq,
2674 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM
2675 object_property_add(obj, "apic-id", "int",
2676 x86_cpuid_get_apic_id,
2677 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH
2678 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2679 x86_cpu_get_feature_words,
7e5292b5
EH
2680 NULL, NULL, (void *)env->features, NULL);
2681 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2682 x86_cpu_get_feature_words,
2683 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2684
92067bf4 2685 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2686 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815
IM
2687
2688 /* init various static tables used in TCG mode */
2689 if (tcg_enabled() && !inited) {
2690 inited = 1;
2691 optimize_flags_init();
2692#ifndef CONFIG_USER_ONLY
2693 cpu_set_debug_excp_handler(breakpoint_handler);
2694#endif
2695 }
de024815
AF
2696}
2697
997395d3
IM
2698static int64_t x86_cpu_get_arch_id(CPUState *cs)
2699{
2700 X86CPU *cpu = X86_CPU(cs);
2701 CPUX86State *env = &cpu->env;
2702
2703 return env->cpuid_apic_id;
2704}
2705
444d5590
AF
2706static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2707{
2708 X86CPU *cpu = X86_CPU(cs);
2709
2710 return cpu->env.cr[0] & CR0_PG_MASK;
2711}
2712
f45748f1
AF
2713static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2714{
2715 X86CPU *cpu = X86_CPU(cs);
2716
2717 cpu->env.eip = value;
2718}
2719
bdf7ae5b
AF
2720static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2721{
2722 X86CPU *cpu = X86_CPU(cs);
2723
2724 cpu->env.eip = tb->pc - tb->cs_base;
2725}
2726
9337e3b6
EH
2727static Property x86_cpu_properties[] = {
2728 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2729 DEFINE_PROP_END_OF_LIST()
2730};
2731
5fd2087a
AF
2732static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2733{
2734 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2735 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF
2736 DeviceClass *dc = DEVICE_CLASS(oc);
2737
2738 xcc->parent_realize = dc->realize;
2739 dc->realize = x86_cpu_realizefn;
62fc403f 2740 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2741 dc->props = x86_cpu_properties;
5fd2087a
AF
2742
2743 xcc->parent_reset = cc->reset;
2744 cc->reset = x86_cpu_reset;
91b1df8c 2745 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2746
97a8ea5a 2747 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2748 cc->dump_state = x86_cpu_dump_state;
f45748f1 2749 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2750 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF
2751 cc->gdb_read_register = x86_cpu_gdb_read_register;
2752 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF
2753 cc->get_arch_id = x86_cpu_get_arch_id;
2754 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
c72bf468 2755#ifndef CONFIG_USER_ONLY
a23bbfda 2756 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2757 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF
2758 cc->write_elf64_note = x86_cpu_write_elf64_note;
2759 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2760 cc->write_elf32_note = x86_cpu_write_elf32_note;
2761 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2762 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2763#endif
a0e372f0 2764 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF
2765}
2766
2767static const TypeInfo x86_cpu_type_info = {
2768 .name = TYPE_X86_CPU,
2769 .parent = TYPE_CPU,
2770 .instance_size = sizeof(X86CPU),
de024815 2771 .instance_init = x86_cpu_initfn,
5fd2087a
AF
2772 .abstract = false,
2773 .class_size = sizeof(X86CPUClass),
2774 .class_init = x86_cpu_common_class_init,
2775};
2776
2777static void x86_cpu_register_types(void)
2778{
2779 type_register_static(&x86_cpu_type_info);
2780}
2781
2782type_init(x86_cpu_register_types)