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Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
dca51e78 | 19 | #include <linux/blk-mq-pci.h> |
ff5350a8 | 20 | #include <linux/dmi.h> |
b60503ba MW |
21 | #include <linux/init.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
b60503ba MW |
24 | #include <linux/mm.h> |
25 | #include <linux/module.h> | |
77bf25ea | 26 | #include <linux/mutex.h> |
b60503ba | 27 | #include <linux/pci.h> |
be7b6275 | 28 | #include <linux/poison.h> |
e1e5e564 | 29 | #include <linux/t10-pi.h> |
2d55cd5f | 30 | #include <linux/timer.h> |
b60503ba | 31 | #include <linux/types.h> |
2f8e2c87 | 32 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 33 | #include <asm/unaligned.h> |
a98e58e5 | 34 | #include <linux/sed-opal.h> |
797a796a | 35 | |
f11bb3e2 CH |
36 | #include "nvme.h" |
37 | ||
9d43cf64 | 38 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 39 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
40 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
41 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
c965809c | 42 | |
adf68f21 CH |
43 | /* |
44 | * We handle AEN commands ourselves and don't even let the | |
45 | * block layer know about them. | |
46 | */ | |
f866fc42 | 47 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) |
9d43cf64 | 48 | |
58ffacb5 MW |
49 | static int use_threaded_interrupts; |
50 | module_param(use_threaded_interrupts, int, 0); | |
51 | ||
8ffaadf7 JD |
52 | static bool use_cmb_sqes = true; |
53 | module_param(use_cmb_sqes, bool, 0644); | |
54 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
55 | ||
87ad72a5 CH |
56 | static unsigned int max_host_mem_size_mb = 128; |
57 | module_param(max_host_mem_size_mb, uint, 0444); | |
58 | MODULE_PARM_DESC(max_host_mem_size_mb, | |
59 | "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); | |
60 | ||
1c63dc66 CH |
61 | struct nvme_dev; |
62 | struct nvme_queue; | |
b3fffdef | 63 | |
a0fa9647 | 64 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 65 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 66 | |
1c63dc66 CH |
67 | /* |
68 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
69 | */ | |
70 | struct nvme_dev { | |
1c63dc66 CH |
71 | struct nvme_queue **queues; |
72 | struct blk_mq_tag_set tagset; | |
73 | struct blk_mq_tag_set admin_tagset; | |
74 | u32 __iomem *dbs; | |
75 | struct device *dev; | |
76 | struct dma_pool *prp_page_pool; | |
77 | struct dma_pool *prp_small_pool; | |
78 | unsigned queue_count; | |
79 | unsigned online_queues; | |
80 | unsigned max_qid; | |
81 | int q_depth; | |
82 | u32 db_stride; | |
1c63dc66 | 83 | void __iomem *bar; |
97f6ef64 | 84 | unsigned long bar_mapped_size; |
5c8809e6 | 85 | struct work_struct remove_work; |
77bf25ea | 86 | struct mutex shutdown_lock; |
1c63dc66 | 87 | bool subsystem; |
1c63dc66 CH |
88 | void __iomem *cmb; |
89 | dma_addr_t cmb_dma_addr; | |
90 | u64 cmb_size; | |
91 | u32 cmbsz; | |
202021c1 | 92 | u32 cmbloc; |
1c63dc66 | 93 | struct nvme_ctrl ctrl; |
db3cbfff | 94 | struct completion ioq_wait; |
87ad72a5 CH |
95 | |
96 | /* shadow doorbell buffer support: */ | |
f9f38e33 HK |
97 | u32 *dbbuf_dbs; |
98 | dma_addr_t dbbuf_dbs_dma_addr; | |
99 | u32 *dbbuf_eis; | |
100 | dma_addr_t dbbuf_eis_dma_addr; | |
87ad72a5 CH |
101 | |
102 | /* host memory buffer support: */ | |
103 | u64 host_mem_size; | |
104 | u32 nr_host_mem_descs; | |
105 | struct nvme_host_mem_buf_desc *host_mem_descs; | |
106 | void **host_mem_desc_bufs; | |
4d115420 | 107 | }; |
1fa6aead | 108 | |
f9f38e33 HK |
109 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
110 | { | |
111 | return qid * 2 * stride; | |
112 | } | |
113 | ||
114 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) | |
115 | { | |
116 | return (qid * 2 + 1) * stride; | |
117 | } | |
118 | ||
1c63dc66 CH |
119 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
120 | { | |
121 | return container_of(ctrl, struct nvme_dev, ctrl); | |
122 | } | |
123 | ||
b60503ba MW |
124 | /* |
125 | * An NVM Express queue. Each device has at least two (one for admin | |
126 | * commands and one for I/O commands). | |
127 | */ | |
128 | struct nvme_queue { | |
129 | struct device *q_dmadev; | |
091b6092 | 130 | struct nvme_dev *dev; |
b60503ba MW |
131 | spinlock_t q_lock; |
132 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 133 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 134 | volatile struct nvme_completion *cqes; |
42483228 | 135 | struct blk_mq_tags **tags; |
b60503ba MW |
136 | dma_addr_t sq_dma_addr; |
137 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
138 | u32 __iomem *q_db; |
139 | u16 q_depth; | |
6222d172 | 140 | s16 cq_vector; |
b60503ba MW |
141 | u16 sq_tail; |
142 | u16 cq_head; | |
c30341dc | 143 | u16 qid; |
e9539f47 MW |
144 | u8 cq_phase; |
145 | u8 cqe_seen; | |
f9f38e33 HK |
146 | u32 *dbbuf_sq_db; |
147 | u32 *dbbuf_cq_db; | |
148 | u32 *dbbuf_sq_ei; | |
149 | u32 *dbbuf_cq_ei; | |
b60503ba MW |
150 | }; |
151 | ||
71bd150c CH |
152 | /* |
153 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
154 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 155 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
156 | * allocated to store the PRP list. |
157 | */ | |
158 | struct nvme_iod { | |
d49187e9 | 159 | struct nvme_request req; |
f4800d6d CH |
160 | struct nvme_queue *nvmeq; |
161 | int aborted; | |
71bd150c | 162 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
163 | int nents; /* Used in scatterlist */ |
164 | int length; /* Of data, in bytes */ | |
165 | dma_addr_t first_dma; | |
bf684057 | 166 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
167 | struct scatterlist *sg; |
168 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
169 | }; |
170 | ||
171 | /* | |
172 | * Check we didin't inadvertently grow the command struct | |
173 | */ | |
174 | static inline void _nvme_check_size(void) | |
175 | { | |
176 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
177 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
178 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
179 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
180 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 181 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 182 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba | 183 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
0add5e8e JT |
184 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); |
185 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); | |
b60503ba | 186 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); |
6ecec745 | 187 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
f9f38e33 HK |
188 | BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); |
189 | } | |
190 | ||
191 | static inline unsigned int nvme_dbbuf_size(u32 stride) | |
192 | { | |
193 | return ((num_possible_cpus() + 1) * 8 * stride); | |
194 | } | |
195 | ||
196 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) | |
197 | { | |
198 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
199 | ||
200 | if (dev->dbbuf_dbs) | |
201 | return 0; | |
202 | ||
203 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, | |
204 | &dev->dbbuf_dbs_dma_addr, | |
205 | GFP_KERNEL); | |
206 | if (!dev->dbbuf_dbs) | |
207 | return -ENOMEM; | |
208 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, | |
209 | &dev->dbbuf_eis_dma_addr, | |
210 | GFP_KERNEL); | |
211 | if (!dev->dbbuf_eis) { | |
212 | dma_free_coherent(dev->dev, mem_size, | |
213 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
214 | dev->dbbuf_dbs = NULL; | |
215 | return -ENOMEM; | |
216 | } | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
221 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) | |
222 | { | |
223 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
224 | ||
225 | if (dev->dbbuf_dbs) { | |
226 | dma_free_coherent(dev->dev, mem_size, | |
227 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
228 | dev->dbbuf_dbs = NULL; | |
229 | } | |
230 | if (dev->dbbuf_eis) { | |
231 | dma_free_coherent(dev->dev, mem_size, | |
232 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); | |
233 | dev->dbbuf_eis = NULL; | |
234 | } | |
235 | } | |
236 | ||
237 | static void nvme_dbbuf_init(struct nvme_dev *dev, | |
238 | struct nvme_queue *nvmeq, int qid) | |
239 | { | |
240 | if (!dev->dbbuf_dbs || !qid) | |
241 | return; | |
242 | ||
243 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; | |
244 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; | |
245 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; | |
246 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; | |
247 | } | |
248 | ||
249 | static void nvme_dbbuf_set(struct nvme_dev *dev) | |
250 | { | |
251 | struct nvme_command c; | |
252 | ||
253 | if (!dev->dbbuf_dbs) | |
254 | return; | |
255 | ||
256 | memset(&c, 0, sizeof(c)); | |
257 | c.dbbuf.opcode = nvme_admin_dbbuf; | |
258 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); | |
259 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); | |
260 | ||
261 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { | |
9bdcfb10 | 262 | dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); |
f9f38e33 HK |
263 | /* Free memory and continue on */ |
264 | nvme_dbbuf_dma_free(dev); | |
265 | } | |
266 | } | |
267 | ||
268 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) | |
269 | { | |
270 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
271 | } | |
272 | ||
273 | /* Update dbbuf and return true if an MMIO is required */ | |
274 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, | |
275 | volatile u32 *dbbuf_ei) | |
276 | { | |
277 | if (dbbuf_db) { | |
278 | u16 old_value; | |
279 | ||
280 | /* | |
281 | * Ensure that the queue is written before updating | |
282 | * the doorbell in memory | |
283 | */ | |
284 | wmb(); | |
285 | ||
286 | old_value = *dbbuf_db; | |
287 | *dbbuf_db = value; | |
288 | ||
289 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) | |
290 | return false; | |
291 | } | |
292 | ||
293 | return true; | |
b60503ba MW |
294 | } |
295 | ||
ac3dd5bd JA |
296 | /* |
297 | * Max size of iod being embedded in the request payload | |
298 | */ | |
299 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 300 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
301 | |
302 | /* | |
303 | * Will slightly overestimate the number of pages needed. This is OK | |
304 | * as it only leads to a small amount of wasted memory for the lifetime of | |
305 | * the I/O. | |
306 | */ | |
307 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
308 | { | |
5fd4ce1b CH |
309 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
310 | dev->ctrl.page_size); | |
ac3dd5bd JA |
311 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
312 | } | |
313 | ||
f4800d6d CH |
314 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
315 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 316 | { |
f4800d6d CH |
317 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
318 | sizeof(struct scatterlist) * nseg; | |
319 | } | |
ac3dd5bd | 320 | |
f4800d6d CH |
321 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
322 | { | |
323 | return sizeof(struct nvme_iod) + | |
324 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
325 | } |
326 | ||
a4aea562 MB |
327 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
328 | unsigned int hctx_idx) | |
e85248e5 | 329 | { |
a4aea562 MB |
330 | struct nvme_dev *dev = data; |
331 | struct nvme_queue *nvmeq = dev->queues[0]; | |
332 | ||
42483228 KB |
333 | WARN_ON(hctx_idx != 0); |
334 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
335 | WARN_ON(nvmeq->tags); | |
336 | ||
a4aea562 | 337 | hctx->driver_data = nvmeq; |
42483228 | 338 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 339 | return 0; |
e85248e5 MW |
340 | } |
341 | ||
4af0e21c KB |
342 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
343 | { | |
344 | struct nvme_queue *nvmeq = hctx->driver_data; | |
345 | ||
346 | nvmeq->tags = NULL; | |
347 | } | |
348 | ||
a4aea562 MB |
349 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
350 | unsigned int hctx_idx) | |
b60503ba | 351 | { |
a4aea562 | 352 | struct nvme_dev *dev = data; |
42483228 | 353 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 354 | |
42483228 KB |
355 | if (!nvmeq->tags) |
356 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 357 | |
42483228 | 358 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
359 | hctx->driver_data = nvmeq; |
360 | return 0; | |
b60503ba MW |
361 | } |
362 | ||
d6296d39 CH |
363 | static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, |
364 | unsigned int hctx_idx, unsigned int numa_node) | |
b60503ba | 365 | { |
d6296d39 | 366 | struct nvme_dev *dev = set->driver_data; |
f4800d6d | 367 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
0350815a CH |
368 | int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; |
369 | struct nvme_queue *nvmeq = dev->queues[queue_idx]; | |
a4aea562 MB |
370 | |
371 | BUG_ON(!nvmeq); | |
f4800d6d | 372 | iod->nvmeq = nvmeq; |
a4aea562 MB |
373 | return 0; |
374 | } | |
375 | ||
dca51e78 CH |
376 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
377 | { | |
378 | struct nvme_dev *dev = set->driver_data; | |
379 | ||
380 | return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); | |
381 | } | |
382 | ||
b60503ba | 383 | /** |
adf68f21 | 384 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
385 | * @nvmeq: The queue to use |
386 | * @cmd: The command to send | |
387 | * | |
388 | * Safe to use from interrupt context | |
389 | */ | |
e3f879bf SB |
390 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
391 | struct nvme_command *cmd) | |
b60503ba | 392 | { |
a4aea562 MB |
393 | u16 tail = nvmeq->sq_tail; |
394 | ||
8ffaadf7 JD |
395 | if (nvmeq->sq_cmds_io) |
396 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
397 | else | |
398 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
399 | ||
b60503ba MW |
400 | if (++tail == nvmeq->q_depth) |
401 | tail = 0; | |
f9f38e33 HK |
402 | if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, |
403 | nvmeq->dbbuf_sq_ei)) | |
404 | writel(tail, nvmeq->q_db); | |
b60503ba | 405 | nvmeq->sq_tail = tail; |
b60503ba MW |
406 | } |
407 | ||
f4800d6d | 408 | static __le64 **iod_list(struct request *req) |
b60503ba | 409 | { |
f4800d6d | 410 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
f9d03f96 | 411 | return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
412 | } |
413 | ||
fc17b653 | 414 | static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 415 | { |
f4800d6d | 416 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
f9d03f96 | 417 | int nseg = blk_rq_nr_phys_segments(rq); |
b131c61d | 418 | unsigned int size = blk_rq_payload_bytes(rq); |
ac3dd5bd | 419 | |
f4800d6d CH |
420 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
421 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
422 | if (!iod->sg) | |
fc17b653 | 423 | return BLK_STS_RESOURCE; |
f4800d6d CH |
424 | } else { |
425 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
426 | } |
427 | ||
f4800d6d CH |
428 | iod->aborted = 0; |
429 | iod->npages = -1; | |
430 | iod->nents = 0; | |
431 | iod->length = size; | |
f80ec966 | 432 | |
fc17b653 | 433 | return BLK_STS_OK; |
ac3dd5bd JA |
434 | } |
435 | ||
f4800d6d | 436 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 437 | { |
f4800d6d | 438 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 439 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 440 | int i; |
f4800d6d | 441 | __le64 **list = iod_list(req); |
eca18b23 MW |
442 | dma_addr_t prp_dma = iod->first_dma; |
443 | ||
444 | if (iod->npages == 0) | |
445 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
446 | for (i = 0; i < iod->npages; i++) { | |
447 | __le64 *prp_list = list[i]; | |
448 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
449 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
450 | prp_dma = next_prp_dma; | |
451 | } | |
ac3dd5bd | 452 | |
f4800d6d CH |
453 | if (iod->sg != iod->inline_sg) |
454 | kfree(iod->sg); | |
b4ff9c8d KB |
455 | } |
456 | ||
52b68d7e | 457 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
458 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
459 | { | |
460 | if (be32_to_cpu(pi->ref_tag) == v) | |
461 | pi->ref_tag = cpu_to_be32(p); | |
462 | } | |
463 | ||
464 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
465 | { | |
466 | if (be32_to_cpu(pi->ref_tag) == p) | |
467 | pi->ref_tag = cpu_to_be32(v); | |
468 | } | |
469 | ||
470 | /** | |
471 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
472 | * | |
473 | * The virtual start sector is the one that was originally submitted by the | |
474 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
475 | * start sector may be different. Remap protection information to match the | |
476 | * physical LBA on writes, and back to the original seed on reads. | |
477 | * | |
478 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
479 | */ | |
480 | static void nvme_dif_remap(struct request *req, | |
481 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
482 | { | |
483 | struct nvme_ns *ns = req->rq_disk->private_data; | |
484 | struct bio_integrity_payload *bip; | |
485 | struct t10_pi_tuple *pi; | |
486 | void *p, *pmap; | |
487 | u32 i, nlb, ts, phys, virt; | |
488 | ||
489 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
490 | return; | |
491 | ||
492 | bip = bio_integrity(req->bio); | |
493 | if (!bip) | |
494 | return; | |
495 | ||
496 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
497 | |
498 | p = pmap; | |
499 | virt = bip_get_seed(bip); | |
500 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
501 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 502 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
503 | |
504 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
505 | pi = (struct t10_pi_tuple *)p; | |
506 | dif_swap(phys, virt, pi); | |
507 | p += ts; | |
508 | } | |
509 | kunmap_atomic(pmap); | |
510 | } | |
52b68d7e KB |
511 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
512 | static void nvme_dif_remap(struct request *req, | |
513 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
514 | { | |
515 | } | |
516 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
517 | { | |
518 | } | |
519 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
520 | { | |
521 | } | |
52b68d7e KB |
522 | #endif |
523 | ||
b131c61d | 524 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req) |
ff22b54f | 525 | { |
f4800d6d | 526 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 527 | struct dma_pool *pool; |
b131c61d | 528 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 529 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
530 | int dma_len = sg_dma_len(sg); |
531 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 532 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 533 | int offset = dma_addr & (page_size - 1); |
e025344c | 534 | __le64 *prp_list; |
f4800d6d | 535 | __le64 **list = iod_list(req); |
e025344c | 536 | dma_addr_t prp_dma; |
eca18b23 | 537 | int nprps, i; |
ff22b54f | 538 | |
1d090624 | 539 | length -= (page_size - offset); |
ff22b54f | 540 | if (length <= 0) |
69d2b571 | 541 | return true; |
ff22b54f | 542 | |
1d090624 | 543 | dma_len -= (page_size - offset); |
ff22b54f | 544 | if (dma_len) { |
1d090624 | 545 | dma_addr += (page_size - offset); |
ff22b54f MW |
546 | } else { |
547 | sg = sg_next(sg); | |
548 | dma_addr = sg_dma_address(sg); | |
549 | dma_len = sg_dma_len(sg); | |
550 | } | |
551 | ||
1d090624 | 552 | if (length <= page_size) { |
edd10d33 | 553 | iod->first_dma = dma_addr; |
69d2b571 | 554 | return true; |
e025344c SMM |
555 | } |
556 | ||
1d090624 | 557 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
558 | if (nprps <= (256 / 8)) { |
559 | pool = dev->prp_small_pool; | |
eca18b23 | 560 | iod->npages = 0; |
99802a7a MW |
561 | } else { |
562 | pool = dev->prp_page_pool; | |
eca18b23 | 563 | iod->npages = 1; |
99802a7a MW |
564 | } |
565 | ||
69d2b571 | 566 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 567 | if (!prp_list) { |
edd10d33 | 568 | iod->first_dma = dma_addr; |
eca18b23 | 569 | iod->npages = -1; |
69d2b571 | 570 | return false; |
b77954cb | 571 | } |
eca18b23 MW |
572 | list[0] = prp_list; |
573 | iod->first_dma = prp_dma; | |
e025344c SMM |
574 | i = 0; |
575 | for (;;) { | |
1d090624 | 576 | if (i == page_size >> 3) { |
e025344c | 577 | __le64 *old_prp_list = prp_list; |
69d2b571 | 578 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 579 | if (!prp_list) |
69d2b571 | 580 | return false; |
eca18b23 | 581 | list[iod->npages++] = prp_list; |
7523d834 MW |
582 | prp_list[0] = old_prp_list[i - 1]; |
583 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
584 | i = 1; | |
e025344c SMM |
585 | } |
586 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
587 | dma_len -= page_size; |
588 | dma_addr += page_size; | |
589 | length -= page_size; | |
e025344c SMM |
590 | if (length <= 0) |
591 | break; | |
592 | if (dma_len > 0) | |
593 | continue; | |
594 | BUG_ON(dma_len < 0); | |
595 | sg = sg_next(sg); | |
596 | dma_addr = sg_dma_address(sg); | |
597 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
598 | } |
599 | ||
69d2b571 | 600 | return true; |
ff22b54f MW |
601 | } |
602 | ||
fc17b653 | 603 | static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 604 | struct nvme_command *cmnd) |
d29ec824 | 605 | { |
f4800d6d | 606 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
607 | struct request_queue *q = req->q; |
608 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
609 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
fc17b653 | 610 | blk_status_t ret = BLK_STS_IOERR; |
d29ec824 | 611 | |
f9d03f96 | 612 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
ba1ca37e CH |
613 | iod->nents = blk_rq_map_sg(q, req, iod->sg); |
614 | if (!iod->nents) | |
615 | goto out; | |
d29ec824 | 616 | |
fc17b653 | 617 | ret = BLK_STS_RESOURCE; |
2b6b535d MFO |
618 | if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, |
619 | DMA_ATTR_NO_WARN)) | |
ba1ca37e | 620 | goto out; |
d29ec824 | 621 | |
b131c61d | 622 | if (!nvme_setup_prps(dev, req)) |
ba1ca37e | 623 | goto out_unmap; |
0e5e4f0e | 624 | |
fc17b653 | 625 | ret = BLK_STS_IOERR; |
ba1ca37e CH |
626 | if (blk_integrity_rq(req)) { |
627 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
628 | goto out_unmap; | |
0e5e4f0e | 629 | |
bf684057 CH |
630 | sg_init_table(&iod->meta_sg, 1); |
631 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 632 | goto out_unmap; |
0e5e4f0e | 633 | |
ba1ca37e CH |
634 | if (rq_data_dir(req)) |
635 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 636 | |
bf684057 | 637 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 638 | goto out_unmap; |
d29ec824 | 639 | } |
00df5cb4 | 640 | |
eb793e2c CH |
641 | cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
642 | cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); | |
ba1ca37e | 643 | if (blk_integrity_rq(req)) |
bf684057 | 644 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
fc17b653 | 645 | return BLK_STS_OK; |
00df5cb4 | 646 | |
ba1ca37e CH |
647 | out_unmap: |
648 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
649 | out: | |
650 | return ret; | |
00df5cb4 MW |
651 | } |
652 | ||
f4800d6d | 653 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 654 | { |
f4800d6d | 655 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
656 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
657 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
658 | ||
659 | if (iod->nents) { | |
660 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
661 | if (blk_integrity_rq(req)) { | |
662 | if (!rq_data_dir(req)) | |
663 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 664 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 665 | } |
e19b127f | 666 | } |
e1e5e564 | 667 | |
f9d03f96 | 668 | nvme_cleanup_cmd(req); |
f4800d6d | 669 | nvme_free_iod(dev, req); |
d4f6c3ab | 670 | } |
b60503ba | 671 | |
d29ec824 CH |
672 | /* |
673 | * NOTE: ns is NULL when called on the admin queue. | |
674 | */ | |
fc17b653 | 675 | static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
a4aea562 | 676 | const struct blk_mq_queue_data *bd) |
edd10d33 | 677 | { |
a4aea562 MB |
678 | struct nvme_ns *ns = hctx->queue->queuedata; |
679 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 680 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 681 | struct request *req = bd->rq; |
ba1ca37e | 682 | struct nvme_command cmnd; |
ebe6d874 | 683 | blk_status_t ret; |
e1e5e564 | 684 | |
f9d03f96 | 685 | ret = nvme_setup_cmd(ns, req, &cmnd); |
fc17b653 | 686 | if (ret) |
f4800d6d | 687 | return ret; |
a4aea562 | 688 | |
b131c61d | 689 | ret = nvme_init_iod(req, dev); |
fc17b653 | 690 | if (ret) |
f9d03f96 | 691 | goto out_free_cmd; |
a4aea562 | 692 | |
fc17b653 | 693 | if (blk_rq_nr_phys_segments(req)) { |
b131c61d | 694 | ret = nvme_map_data(dev, req, &cmnd); |
fc17b653 CH |
695 | if (ret) |
696 | goto out_cleanup_iod; | |
697 | } | |
a4aea562 | 698 | |
aae239e1 | 699 | blk_mq_start_request(req); |
a4aea562 | 700 | |
ba1ca37e | 701 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 702 | if (unlikely(nvmeq->cq_vector < 0)) { |
fc17b653 | 703 | ret = BLK_STS_IOERR; |
ae1fba20 | 704 | spin_unlock_irq(&nvmeq->q_lock); |
f9d03f96 | 705 | goto out_cleanup_iod; |
ae1fba20 | 706 | } |
ba1ca37e | 707 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
708 | nvme_process_cq(nvmeq); |
709 | spin_unlock_irq(&nvmeq->q_lock); | |
fc17b653 | 710 | return BLK_STS_OK; |
f9d03f96 | 711 | out_cleanup_iod: |
f4800d6d | 712 | nvme_free_iod(dev, req); |
f9d03f96 CH |
713 | out_free_cmd: |
714 | nvme_cleanup_cmd(req); | |
ba1ca37e | 715 | return ret; |
b60503ba | 716 | } |
e1e5e564 | 717 | |
77f02a7a | 718 | static void nvme_pci_complete_rq(struct request *req) |
eee417b0 | 719 | { |
f4800d6d | 720 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 | 721 | |
77f02a7a CH |
722 | nvme_unmap_data(iod->nvmeq->dev, req); |
723 | nvme_complete_rq(req); | |
b60503ba MW |
724 | } |
725 | ||
d783e0bd MR |
726 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
727 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
728 | u16 phase) | |
729 | { | |
730 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
731 | } | |
732 | ||
eb281c82 SG |
733 | static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) |
734 | { | |
735 | u16 head = nvmeq->cq_head; | |
736 | ||
737 | if (likely(nvmeq->cq_vector >= 0)) { | |
738 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, | |
739 | nvmeq->dbbuf_cq_ei)) | |
740 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
741 | } | |
742 | } | |
743 | ||
a0fa9647 | 744 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 745 | { |
82123460 | 746 | u16 head, phase; |
b60503ba | 747 | |
b60503ba | 748 | head = nvmeq->cq_head; |
82123460 | 749 | phase = nvmeq->cq_phase; |
b60503ba | 750 | |
d783e0bd | 751 | while (nvme_cqe_valid(nvmeq, head, phase)) { |
b60503ba | 752 | struct nvme_completion cqe = nvmeq->cqes[head]; |
eee417b0 | 753 | struct request *req; |
adf68f21 | 754 | |
b60503ba MW |
755 | if (++head == nvmeq->q_depth) { |
756 | head = 0; | |
82123460 | 757 | phase = !phase; |
b60503ba | 758 | } |
adf68f21 | 759 | |
a0fa9647 JA |
760 | if (tag && *tag == cqe.command_id) |
761 | *tag = -1; | |
adf68f21 | 762 | |
aae239e1 | 763 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 764 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
765 | "invalid id %d completed on queue %d\n", |
766 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
767 | continue; | |
768 | } | |
769 | ||
adf68f21 CH |
770 | /* |
771 | * AEN requests are special as they don't time out and can | |
772 | * survive any kind of queue freeze and often don't respond to | |
773 | * aborts. We don't even bother to allocate a struct request | |
774 | * for them but rather special case them here. | |
775 | */ | |
776 | if (unlikely(nvmeq->qid == 0 && | |
777 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
7bf58533 CH |
778 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
779 | cqe.status, &cqe.result); | |
adf68f21 CH |
780 | continue; |
781 | } | |
782 | ||
eee417b0 | 783 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
27fa9bc5 | 784 | nvme_end_request(req, cqe.status, cqe.result); |
b60503ba MW |
785 | } |
786 | ||
82123460 | 787 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 788 | return; |
b60503ba | 789 | |
b60503ba | 790 | nvmeq->cq_head = head; |
82123460 | 791 | nvmeq->cq_phase = phase; |
b60503ba | 792 | |
eb281c82 SG |
793 | nvme_ring_cq_doorbell(nvmeq); |
794 | ||
e9539f47 | 795 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
796 | } |
797 | ||
798 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
799 | { | |
800 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
801 | } |
802 | ||
803 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
804 | { |
805 | irqreturn_t result; | |
806 | struct nvme_queue *nvmeq = data; | |
807 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
808 | nvme_process_cq(nvmeq); |
809 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
810 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
811 | spin_unlock(&nvmeq->q_lock); |
812 | return result; | |
813 | } | |
814 | ||
815 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
816 | { | |
817 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
818 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
819 | return IRQ_WAKE_THREAD; | |
820 | return IRQ_NONE; | |
58ffacb5 MW |
821 | } |
822 | ||
7776db1c | 823 | static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) |
a0fa9647 | 824 | { |
d783e0bd | 825 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
a0fa9647 JA |
826 | spin_lock_irq(&nvmeq->q_lock); |
827 | __nvme_process_cq(nvmeq, &tag); | |
828 | spin_unlock_irq(&nvmeq->q_lock); | |
829 | ||
830 | if (tag == -1) | |
831 | return 1; | |
832 | } | |
833 | ||
834 | return 0; | |
835 | } | |
836 | ||
7776db1c KB |
837 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
838 | { | |
839 | struct nvme_queue *nvmeq = hctx->driver_data; | |
840 | ||
841 | return __nvme_poll(nvmeq, tag); | |
842 | } | |
843 | ||
f866fc42 | 844 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) |
b60503ba | 845 | { |
f866fc42 | 846 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 847 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 848 | struct nvme_command c; |
b60503ba | 849 | |
a4aea562 MB |
850 | memset(&c, 0, sizeof(c)); |
851 | c.common.opcode = nvme_admin_async_event; | |
f866fc42 | 852 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; |
3c0cf138 | 853 | |
9396dec9 | 854 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 855 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 856 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
857 | } |
858 | ||
b60503ba | 859 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 860 | { |
b60503ba MW |
861 | struct nvme_command c; |
862 | ||
863 | memset(&c, 0, sizeof(c)); | |
864 | c.delete_queue.opcode = opcode; | |
865 | c.delete_queue.qid = cpu_to_le16(id); | |
866 | ||
1c63dc66 | 867 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
868 | } |
869 | ||
b60503ba MW |
870 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
871 | struct nvme_queue *nvmeq) | |
872 | { | |
b60503ba MW |
873 | struct nvme_command c; |
874 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
875 | ||
d29ec824 CH |
876 | /* |
877 | * Note: we (ab)use the fact the the prp fields survive if no data | |
878 | * is attached to the request. | |
879 | */ | |
b60503ba MW |
880 | memset(&c, 0, sizeof(c)); |
881 | c.create_cq.opcode = nvme_admin_create_cq; | |
882 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
883 | c.create_cq.cqid = cpu_to_le16(qid); | |
884 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
885 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
886 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
887 | ||
1c63dc66 | 888 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
889 | } |
890 | ||
891 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
892 | struct nvme_queue *nvmeq) | |
893 | { | |
b60503ba | 894 | struct nvme_command c; |
81c1cd98 | 895 | int flags = NVME_QUEUE_PHYS_CONTIG; |
b60503ba | 896 | |
d29ec824 CH |
897 | /* |
898 | * Note: we (ab)use the fact the the prp fields survive if no data | |
899 | * is attached to the request. | |
900 | */ | |
b60503ba MW |
901 | memset(&c, 0, sizeof(c)); |
902 | c.create_sq.opcode = nvme_admin_create_sq; | |
903 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
904 | c.create_sq.sqid = cpu_to_le16(qid); | |
905 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
906 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
907 | c.create_sq.cqid = cpu_to_le16(qid); | |
908 | ||
1c63dc66 | 909 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
910 | } |
911 | ||
912 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
913 | { | |
914 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
915 | } | |
916 | ||
917 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
918 | { | |
919 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
920 | } | |
921 | ||
2a842aca | 922 | static void abort_endio(struct request *req, blk_status_t error) |
bc5fc7e4 | 923 | { |
f4800d6d CH |
924 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
925 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e44ac588 | 926 | |
27fa9bc5 CH |
927 | dev_warn(nvmeq->dev->ctrl.device, |
928 | "Abort status: 0x%x", nvme_req(req)->status); | |
e7a2a87d | 929 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 930 | blk_mq_free_request(req); |
bc5fc7e4 MW |
931 | } |
932 | ||
b2a0eb1a KB |
933 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
934 | { | |
935 | ||
936 | /* If true, indicates loss of adapter communication, possibly by a | |
937 | * NVMe Subsystem reset. | |
938 | */ | |
939 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
940 | ||
941 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
942 | if (dev->ctrl.state == NVME_CTRL_RESETTING) | |
943 | return false; | |
944 | ||
945 | /* We shouldn't reset unless the controller is on fatal error state | |
946 | * _or_ if we lost the communication with it. | |
947 | */ | |
948 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
949 | return false; | |
950 | ||
951 | /* If PCI error recovery process is happening, we cannot reset or | |
952 | * the recovery mechanism will surely fail. | |
953 | */ | |
954 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
955 | return false; | |
956 | ||
957 | return true; | |
958 | } | |
959 | ||
960 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) | |
961 | { | |
962 | /* Read a config register to help see what died. */ | |
963 | u16 pci_status; | |
964 | int result; | |
965 | ||
966 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
967 | &pci_status); | |
968 | if (result == PCIBIOS_SUCCESSFUL) | |
969 | dev_warn(dev->ctrl.device, | |
970 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
971 | csts, pci_status); | |
972 | else | |
973 | dev_warn(dev->ctrl.device, | |
974 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
975 | csts, result); | |
976 | } | |
977 | ||
31c7c7d2 | 978 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 979 | { |
f4800d6d CH |
980 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
981 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 982 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 983 | struct request *abort_req; |
a4aea562 | 984 | struct nvme_command cmd; |
b2a0eb1a KB |
985 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
986 | ||
987 | /* | |
988 | * Reset immediately if the controller is failed | |
989 | */ | |
990 | if (nvme_should_reset(dev, csts)) { | |
991 | nvme_warn_reset(dev, csts); | |
992 | nvme_dev_disable(dev, false); | |
d86c4d8e | 993 | nvme_reset_ctrl(&dev->ctrl); |
b2a0eb1a KB |
994 | return BLK_EH_HANDLED; |
995 | } | |
c30341dc | 996 | |
7776db1c KB |
997 | /* |
998 | * Did we miss an interrupt? | |
999 | */ | |
1000 | if (__nvme_poll(nvmeq, req->tag)) { | |
1001 | dev_warn(dev->ctrl.device, | |
1002 | "I/O %d QID %d timeout, completion polled\n", | |
1003 | req->tag, nvmeq->qid); | |
1004 | return BLK_EH_HANDLED; | |
1005 | } | |
1006 | ||
31c7c7d2 | 1007 | /* |
fd634f41 CH |
1008 | * Shutdown immediately if controller times out while starting. The |
1009 | * reset work will see the pci device disabled when it gets the forced | |
1010 | * cancellation error. All outstanding requests are completed on | |
1011 | * shutdown, so we return BLK_EH_HANDLED. | |
1012 | */ | |
bb8d261e | 1013 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 1014 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
1015 | "I/O %d QID %d timeout, disable controller\n", |
1016 | req->tag, nvmeq->qid); | |
a5cdb68c | 1017 | nvme_dev_disable(dev, false); |
27fa9bc5 | 1018 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
fd634f41 | 1019 | return BLK_EH_HANDLED; |
c30341dc KB |
1020 | } |
1021 | ||
fd634f41 CH |
1022 | /* |
1023 | * Shutdown the controller immediately and schedule a reset if the | |
1024 | * command was already aborted once before and still hasn't been | |
1025 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 1026 | */ |
f4800d6d | 1027 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 1028 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
1029 | "I/O %d QID %d timeout, reset controller\n", |
1030 | req->tag, nvmeq->qid); | |
a5cdb68c | 1031 | nvme_dev_disable(dev, false); |
d86c4d8e | 1032 | nvme_reset_ctrl(&dev->ctrl); |
c30341dc | 1033 | |
e1569a16 KB |
1034 | /* |
1035 | * Mark the request as handled, since the inline shutdown | |
1036 | * forces all outstanding requests to complete. | |
1037 | */ | |
27fa9bc5 | 1038 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
e1569a16 | 1039 | return BLK_EH_HANDLED; |
c30341dc | 1040 | } |
c30341dc | 1041 | |
e7a2a87d | 1042 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 1043 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 1044 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1045 | } |
7bf7d778 | 1046 | iod->aborted = 1; |
a4aea562 | 1047 | |
c30341dc KB |
1048 | memset(&cmd, 0, sizeof(cmd)); |
1049 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1050 | cmd.abort.cid = req->tag; |
c30341dc | 1051 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1052 | |
1b3c47c1 SG |
1053 | dev_warn(nvmeq->dev->ctrl.device, |
1054 | "I/O %d QID %d timeout, aborting\n", | |
1055 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
1056 | |
1057 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 1058 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
1059 | if (IS_ERR(abort_req)) { |
1060 | atomic_inc(&dev->ctrl.abort_limit); | |
1061 | return BLK_EH_RESET_TIMER; | |
1062 | } | |
1063 | ||
1064 | abort_req->timeout = ADMIN_TIMEOUT; | |
1065 | abort_req->end_io_data = NULL; | |
1066 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 1067 | |
31c7c7d2 CH |
1068 | /* |
1069 | * The aborted req will be completed on receiving the abort req. | |
1070 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1071 | * as the device then is in a faulty state. | |
1072 | */ | |
1073 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1074 | } |
1075 | ||
a4aea562 MB |
1076 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1077 | { | |
9e866774 MW |
1078 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1079 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1080 | if (nvmeq->sq_cmds) |
1081 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1082 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1083 | kfree(nvmeq); | |
1084 | } | |
1085 | ||
a1a5ef99 | 1086 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1087 | { |
1088 | int i; | |
1089 | ||
a1a5ef99 | 1090 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1091 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1092 | dev->queue_count--; |
a4aea562 | 1093 | dev->queues[i] = NULL; |
f435c282 | 1094 | nvme_free_queue(nvmeq); |
121c7ad4 | 1095 | } |
22404274 KB |
1096 | } |
1097 | ||
4d115420 KB |
1098 | /** |
1099 | * nvme_suspend_queue - put queue into suspended state | |
1100 | * @nvmeq - queue to suspend | |
4d115420 KB |
1101 | */ |
1102 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1103 | { |
2b25d981 | 1104 | int vector; |
b60503ba | 1105 | |
a09115b2 | 1106 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1107 | if (nvmeq->cq_vector == -1) { |
1108 | spin_unlock_irq(&nvmeq->q_lock); | |
1109 | return 1; | |
1110 | } | |
0ff199cb | 1111 | vector = nvmeq->cq_vector; |
42f61420 | 1112 | nvmeq->dev->online_queues--; |
2b25d981 | 1113 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1114 | spin_unlock_irq(&nvmeq->q_lock); |
1115 | ||
1c63dc66 | 1116 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 1117 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1118 | |
0ff199cb | 1119 | pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); |
b60503ba | 1120 | |
4d115420 KB |
1121 | return 0; |
1122 | } | |
b60503ba | 1123 | |
a5cdb68c | 1124 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1125 | { |
a5cdb68c | 1126 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
1127 | |
1128 | if (!nvmeq) | |
1129 | return; | |
1130 | if (nvme_suspend_queue(nvmeq)) | |
1131 | return; | |
1132 | ||
a5cdb68c KB |
1133 | if (shutdown) |
1134 | nvme_shutdown_ctrl(&dev->ctrl); | |
1135 | else | |
1136 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
1137 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
1138 | |
1139 | spin_lock_irq(&nvmeq->q_lock); | |
1140 | nvme_process_cq(nvmeq); | |
1141 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1142 | } |
1143 | ||
8ffaadf7 JD |
1144 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1145 | int entry_size) | |
1146 | { | |
1147 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1148 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1149 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1150 | |
1151 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1152 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1153 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1154 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1155 | |
1156 | /* | |
1157 | * Ensure the reduced q_depth is above some threshold where it | |
1158 | * would be better to map queues in system memory with the | |
1159 | * original depth | |
1160 | */ | |
1161 | if (q_depth < 64) | |
1162 | return -ENOMEM; | |
1163 | } | |
1164 | ||
1165 | return q_depth; | |
1166 | } | |
1167 | ||
1168 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1169 | int qid, int depth) | |
1170 | { | |
1171 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1172 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1173 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1174 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1175 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1176 | } else { | |
1177 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1178 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1179 | if (!nvmeq->sq_cmds) | |
1180 | return -ENOMEM; | |
1181 | } | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
b60503ba | 1186 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
d3af3ecd | 1187 | int depth, int node) |
b60503ba | 1188 | { |
d3af3ecd SL |
1189 | struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, |
1190 | node); | |
b60503ba MW |
1191 | if (!nvmeq) |
1192 | return NULL; | |
1193 | ||
e75ec752 | 1194 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1195 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1196 | if (!nvmeq->cqes) |
1197 | goto free_nvmeq; | |
b60503ba | 1198 | |
8ffaadf7 | 1199 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1200 | goto free_cqdma; |
1201 | ||
e75ec752 | 1202 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1203 | nvmeq->dev = dev; |
b60503ba MW |
1204 | spin_lock_init(&nvmeq->q_lock); |
1205 | nvmeq->cq_head = 0; | |
82123460 | 1206 | nvmeq->cq_phase = 1; |
b80d5ccc | 1207 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1208 | nvmeq->q_depth = depth; |
c30341dc | 1209 | nvmeq->qid = qid; |
758dd7fd | 1210 | nvmeq->cq_vector = -1; |
a4aea562 | 1211 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1212 | dev->queue_count++; |
1213 | ||
b60503ba MW |
1214 | return nvmeq; |
1215 | ||
1216 | free_cqdma: | |
e75ec752 | 1217 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1218 | nvmeq->cq_dma_addr); |
1219 | free_nvmeq: | |
1220 | kfree(nvmeq); | |
1221 | return NULL; | |
1222 | } | |
1223 | ||
dca51e78 | 1224 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1225 | { |
0ff199cb CH |
1226 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
1227 | int nr = nvmeq->dev->ctrl.instance; | |
1228 | ||
1229 | if (use_threaded_interrupts) { | |
1230 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, | |
1231 | nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1232 | } else { | |
1233 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, | |
1234 | NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1235 | } | |
3001082c MW |
1236 | } |
1237 | ||
22404274 | 1238 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1239 | { |
22404274 | 1240 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1241 | |
7be50e93 | 1242 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1243 | nvmeq->sq_tail = 0; |
1244 | nvmeq->cq_head = 0; | |
1245 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1246 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1247 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
f9f38e33 | 1248 | nvme_dbbuf_init(dev, nvmeq, qid); |
42f61420 | 1249 | dev->online_queues++; |
7be50e93 | 1250 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1251 | } |
1252 | ||
1253 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1254 | { | |
1255 | struct nvme_dev *dev = nvmeq->dev; | |
1256 | int result; | |
3f85d50b | 1257 | |
2b25d981 | 1258 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1259 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1260 | if (result < 0) | |
22404274 | 1261 | return result; |
b60503ba MW |
1262 | |
1263 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1264 | if (result < 0) | |
1265 | goto release_cq; | |
1266 | ||
dca51e78 | 1267 | result = queue_request_irq(nvmeq); |
b60503ba MW |
1268 | if (result < 0) |
1269 | goto release_sq; | |
1270 | ||
22404274 | 1271 | nvme_init_queue(nvmeq, qid); |
22404274 | 1272 | return result; |
b60503ba MW |
1273 | |
1274 | release_sq: | |
1275 | adapter_delete_sq(dev, qid); | |
1276 | release_cq: | |
1277 | adapter_delete_cq(dev, qid); | |
22404274 | 1278 | return result; |
b60503ba MW |
1279 | } |
1280 | ||
f363b089 | 1281 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1282 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1283 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1284 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1285 | .exit_hctx = nvme_admin_exit_hctx, |
0350815a | 1286 | .init_request = nvme_init_request, |
a4aea562 MB |
1287 | .timeout = nvme_timeout, |
1288 | }; | |
1289 | ||
f363b089 | 1290 | static const struct blk_mq_ops nvme_mq_ops = { |
a4aea562 | 1291 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1292 | .complete = nvme_pci_complete_rq, |
a4aea562 MB |
1293 | .init_hctx = nvme_init_hctx, |
1294 | .init_request = nvme_init_request, | |
dca51e78 | 1295 | .map_queues = nvme_pci_map_queues, |
a4aea562 | 1296 | .timeout = nvme_timeout, |
a0fa9647 | 1297 | .poll = nvme_poll, |
a4aea562 MB |
1298 | }; |
1299 | ||
ea191d2f KB |
1300 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1301 | { | |
1c63dc66 | 1302 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1303 | /* |
1304 | * If the controller was reset during removal, it's possible | |
1305 | * user requests may be waiting on a stopped queue. Start the | |
1306 | * queue to flush these to completion. | |
1307 | */ | |
1308 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); | |
1c63dc66 | 1309 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1310 | blk_mq_free_tag_set(&dev->admin_tagset); |
1311 | } | |
1312 | } | |
1313 | ||
a4aea562 MB |
1314 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1315 | { | |
1c63dc66 | 1316 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1317 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1318 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1319 | |
1320 | /* | |
1321 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1322 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1323 | */ | |
1324 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1325 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1326 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1327 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
d3484991 | 1328 | dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; |
a4aea562 MB |
1329 | dev->admin_tagset.driver_data = dev; |
1330 | ||
1331 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1332 | return -ENOMEM; | |
1333 | ||
1c63dc66 CH |
1334 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1335 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1336 | blk_mq_free_tag_set(&dev->admin_tagset); |
1337 | return -ENOMEM; | |
1338 | } | |
1c63dc66 | 1339 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1340 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1341 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1342 | return -ENODEV; |
1343 | } | |
0fb59cbc | 1344 | } else |
25646264 | 1345 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1346 | |
1347 | return 0; | |
1348 | } | |
1349 | ||
97f6ef64 XY |
1350 | static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1351 | { | |
1352 | return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); | |
1353 | } | |
1354 | ||
1355 | static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) | |
1356 | { | |
1357 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1358 | ||
1359 | if (size <= dev->bar_mapped_size) | |
1360 | return 0; | |
1361 | if (size > pci_resource_len(pdev, 0)) | |
1362 | return -ENOMEM; | |
1363 | if (dev->bar) | |
1364 | iounmap(dev->bar); | |
1365 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1366 | if (!dev->bar) { | |
1367 | dev->bar_mapped_size = 0; | |
1368 | return -ENOMEM; | |
1369 | } | |
1370 | dev->bar_mapped_size = size; | |
1371 | dev->dbs = dev->bar + NVME_REG_DBS; | |
1372 | ||
1373 | return 0; | |
1374 | } | |
1375 | ||
8d85fce7 | 1376 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1377 | { |
ba47e386 | 1378 | int result; |
b60503ba | 1379 | u32 aqa; |
7a67cbea | 1380 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1381 | struct nvme_queue *nvmeq; |
1382 | ||
97f6ef64 XY |
1383 | result = nvme_remap_bar(dev, db_bar_size(dev, 0)); |
1384 | if (result < 0) | |
1385 | return result; | |
1386 | ||
8ef2074d | 1387 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
dfbac8c7 KB |
1388 | NVME_CAP_NSSRC(cap) : 0; |
1389 | ||
7a67cbea CH |
1390 | if (dev->subsystem && |
1391 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1392 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1393 | |
5fd4ce1b | 1394 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1395 | if (result < 0) |
1396 | return result; | |
b60503ba | 1397 | |
a4aea562 | 1398 | nvmeq = dev->queues[0]; |
cd638946 | 1399 | if (!nvmeq) { |
d3af3ecd SL |
1400 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, |
1401 | dev_to_node(dev->dev)); | |
cd638946 KB |
1402 | if (!nvmeq) |
1403 | return -ENOMEM; | |
cd638946 | 1404 | } |
b60503ba MW |
1405 | |
1406 | aqa = nvmeq->q_depth - 1; | |
1407 | aqa |= aqa << 16; | |
1408 | ||
7a67cbea CH |
1409 | writel(aqa, dev->bar + NVME_REG_AQA); |
1410 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1411 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1412 | |
5fd4ce1b | 1413 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1414 | if (result) |
d4875622 | 1415 | return result; |
a4aea562 | 1416 | |
2b25d981 | 1417 | nvmeq->cq_vector = 0; |
dca51e78 | 1418 | result = queue_request_irq(nvmeq); |
758dd7fd JD |
1419 | if (result) { |
1420 | nvmeq->cq_vector = -1; | |
d4875622 | 1421 | return result; |
758dd7fd | 1422 | } |
025c557a | 1423 | |
b60503ba MW |
1424 | return result; |
1425 | } | |
1426 | ||
749941f2 | 1427 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1428 | { |
949928c1 | 1429 | unsigned i, max; |
749941f2 | 1430 | int ret = 0; |
42f61420 | 1431 | |
749941f2 | 1432 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
d3af3ecd SL |
1433 | /* vector == qid - 1, match nvme_create_queue */ |
1434 | if (!nvme_alloc_queue(dev, i, dev->q_depth, | |
1435 | pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { | |
749941f2 | 1436 | ret = -ENOMEM; |
42f61420 | 1437 | break; |
749941f2 CH |
1438 | } |
1439 | } | |
42f61420 | 1440 | |
949928c1 KB |
1441 | max = min(dev->max_qid, dev->queue_count - 1); |
1442 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 | 1443 | ret = nvme_create_queue(dev->queues[i], i); |
d4875622 | 1444 | if (ret) |
42f61420 | 1445 | break; |
27e8166c | 1446 | } |
749941f2 CH |
1447 | |
1448 | /* | |
1449 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1450 | * than the desired aount of queues, and even a controller without | |
1451 | * I/O queues an still be used to issue admin commands. This might | |
1452 | * be useful to upgrade a buggy firmware for example. | |
1453 | */ | |
1454 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1455 | } |
1456 | ||
202021c1 SB |
1457 | static ssize_t nvme_cmb_show(struct device *dev, |
1458 | struct device_attribute *attr, | |
1459 | char *buf) | |
1460 | { | |
1461 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1462 | ||
c965809c | 1463 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
202021c1 SB |
1464 | ndev->cmbloc, ndev->cmbsz); |
1465 | } | |
1466 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1467 | ||
8ffaadf7 JD |
1468 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1469 | { | |
1470 | u64 szu, size, offset; | |
8ffaadf7 JD |
1471 | resource_size_t bar_size; |
1472 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1473 | void __iomem *cmb; | |
1474 | dma_addr_t dma_addr; | |
1475 | ||
7a67cbea | 1476 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1477 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1478 | return NULL; | |
202021c1 | 1479 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1480 | |
202021c1 SB |
1481 | if (!use_cmb_sqes) |
1482 | return NULL; | |
8ffaadf7 JD |
1483 | |
1484 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1485 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
202021c1 SB |
1486 | offset = szu * NVME_CMB_OFST(dev->cmbloc); |
1487 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); | |
8ffaadf7 JD |
1488 | |
1489 | if (offset > bar_size) | |
1490 | return NULL; | |
1491 | ||
1492 | /* | |
1493 | * Controllers may support a CMB size larger than their BAR, | |
1494 | * for example, due to being behind a bridge. Reduce the CMB to | |
1495 | * the reported size of the BAR | |
1496 | */ | |
1497 | if (size > bar_size - offset) | |
1498 | size = bar_size - offset; | |
1499 | ||
202021c1 | 1500 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; |
8ffaadf7 JD |
1501 | cmb = ioremap_wc(dma_addr, size); |
1502 | if (!cmb) | |
1503 | return NULL; | |
1504 | ||
1505 | dev->cmb_dma_addr = dma_addr; | |
1506 | dev->cmb_size = size; | |
1507 | return cmb; | |
1508 | } | |
1509 | ||
1510 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1511 | { | |
1512 | if (dev->cmb) { | |
1513 | iounmap(dev->cmb); | |
1514 | dev->cmb = NULL; | |
f63572df JD |
1515 | if (dev->cmbsz) { |
1516 | sysfs_remove_file_from_group(&dev->ctrl.device->kobj, | |
1517 | &dev_attr_cmb.attr, NULL); | |
1518 | dev->cmbsz = 0; | |
1519 | } | |
8ffaadf7 JD |
1520 | } |
1521 | } | |
1522 | ||
87ad72a5 CH |
1523 | static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) |
1524 | { | |
1525 | size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs); | |
1526 | struct nvme_command c; | |
1527 | u64 dma_addr; | |
1528 | int ret; | |
1529 | ||
1530 | dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len, | |
1531 | DMA_TO_DEVICE); | |
1532 | if (dma_mapping_error(dev->dev, dma_addr)) | |
1533 | return -ENOMEM; | |
1534 | ||
1535 | memset(&c, 0, sizeof(c)); | |
1536 | c.features.opcode = nvme_admin_set_features; | |
1537 | c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); | |
1538 | c.features.dword11 = cpu_to_le32(bits); | |
1539 | c.features.dword12 = cpu_to_le32(dev->host_mem_size >> | |
1540 | ilog2(dev->ctrl.page_size)); | |
1541 | c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); | |
1542 | c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); | |
1543 | c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); | |
1544 | ||
1545 | ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); | |
1546 | if (ret) { | |
1547 | dev_warn(dev->ctrl.device, | |
1548 | "failed to set host mem (err %d, flags %#x).\n", | |
1549 | ret, bits); | |
1550 | } | |
1551 | dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE); | |
1552 | return ret; | |
1553 | } | |
1554 | ||
1555 | static void nvme_free_host_mem(struct nvme_dev *dev) | |
1556 | { | |
1557 | int i; | |
1558 | ||
1559 | for (i = 0; i < dev->nr_host_mem_descs; i++) { | |
1560 | struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; | |
1561 | size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; | |
1562 | ||
1563 | dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], | |
1564 | le64_to_cpu(desc->addr)); | |
1565 | } | |
1566 | ||
1567 | kfree(dev->host_mem_desc_bufs); | |
1568 | dev->host_mem_desc_bufs = NULL; | |
1569 | kfree(dev->host_mem_descs); | |
1570 | dev->host_mem_descs = NULL; | |
1571 | } | |
1572 | ||
1573 | static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) | |
1574 | { | |
1575 | struct nvme_host_mem_buf_desc *descs; | |
1576 | u32 chunk_size, max_entries, i = 0; | |
1577 | void **bufs; | |
1578 | u64 size, tmp; | |
1579 | ||
1580 | /* start big and work our way down */ | |
1581 | chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER); | |
1582 | retry: | |
1583 | tmp = (preferred + chunk_size - 1); | |
1584 | do_div(tmp, chunk_size); | |
1585 | max_entries = tmp; | |
1586 | descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL); | |
1587 | if (!descs) | |
1588 | goto out; | |
1589 | ||
1590 | bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); | |
1591 | if (!bufs) | |
1592 | goto out_free_descs; | |
1593 | ||
1594 | for (size = 0; size < preferred; size += chunk_size) { | |
1595 | u32 len = min_t(u64, chunk_size, preferred - size); | |
1596 | dma_addr_t dma_addr; | |
1597 | ||
1598 | bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, | |
1599 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
1600 | if (!bufs[i]) | |
1601 | break; | |
1602 | ||
1603 | descs[i].addr = cpu_to_le64(dma_addr); | |
1604 | descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); | |
1605 | i++; | |
1606 | } | |
1607 | ||
1608 | if (!size || (min && size < min)) { | |
1609 | dev_warn(dev->ctrl.device, | |
1610 | "failed to allocate host memory buffer.\n"); | |
1611 | goto out_free_bufs; | |
1612 | } | |
1613 | ||
1614 | dev_info(dev->ctrl.device, | |
1615 | "allocated %lld MiB host memory buffer.\n", | |
1616 | size >> ilog2(SZ_1M)); | |
1617 | dev->nr_host_mem_descs = i; | |
1618 | dev->host_mem_size = size; | |
1619 | dev->host_mem_descs = descs; | |
1620 | dev->host_mem_desc_bufs = bufs; | |
1621 | return 0; | |
1622 | ||
1623 | out_free_bufs: | |
1624 | while (--i >= 0) { | |
1625 | size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; | |
1626 | ||
1627 | dma_free_coherent(dev->dev, size, bufs[i], | |
1628 | le64_to_cpu(descs[i].addr)); | |
1629 | } | |
1630 | ||
1631 | kfree(bufs); | |
1632 | out_free_descs: | |
1633 | kfree(descs); | |
1634 | out: | |
1635 | /* try a smaller chunk size if we failed early */ | |
1636 | if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) { | |
1637 | chunk_size /= 2; | |
1638 | goto retry; | |
1639 | } | |
1640 | dev->host_mem_descs = NULL; | |
1641 | return -ENOMEM; | |
1642 | } | |
1643 | ||
1644 | static void nvme_setup_host_mem(struct nvme_dev *dev) | |
1645 | { | |
1646 | u64 max = (u64)max_host_mem_size_mb * SZ_1M; | |
1647 | u64 preferred = (u64)dev->ctrl.hmpre * 4096; | |
1648 | u64 min = (u64)dev->ctrl.hmmin * 4096; | |
1649 | u32 enable_bits = NVME_HOST_MEM_ENABLE; | |
1650 | ||
1651 | preferred = min(preferred, max); | |
1652 | if (min > max) { | |
1653 | dev_warn(dev->ctrl.device, | |
1654 | "min host memory (%lld MiB) above limit (%d MiB).\n", | |
1655 | min >> ilog2(SZ_1M), max_host_mem_size_mb); | |
1656 | nvme_free_host_mem(dev); | |
1657 | return; | |
1658 | } | |
1659 | ||
1660 | /* | |
1661 | * If we already have a buffer allocated check if we can reuse it. | |
1662 | */ | |
1663 | if (dev->host_mem_descs) { | |
1664 | if (dev->host_mem_size >= min) | |
1665 | enable_bits |= NVME_HOST_MEM_RETURN; | |
1666 | else | |
1667 | nvme_free_host_mem(dev); | |
1668 | } | |
1669 | ||
1670 | if (!dev->host_mem_descs) { | |
1671 | if (nvme_alloc_host_mem(dev, min, preferred)) | |
1672 | return; | |
1673 | } | |
1674 | ||
1675 | if (nvme_set_host_mem(dev, enable_bits)) | |
1676 | nvme_free_host_mem(dev); | |
1677 | } | |
1678 | ||
8d85fce7 | 1679 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1680 | { |
a4aea562 | 1681 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1682 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
97f6ef64 XY |
1683 | int result, nr_io_queues; |
1684 | unsigned long size; | |
b60503ba | 1685 | |
2800b8e7 | 1686 | nr_io_queues = num_online_cpus(); |
9a0be7ab CH |
1687 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1688 | if (result < 0) | |
1b23484b | 1689 | return result; |
9a0be7ab | 1690 | |
f5fa90dc | 1691 | if (nr_io_queues == 0) |
a5229050 | 1692 | return 0; |
b60503ba | 1693 | |
8ffaadf7 JD |
1694 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1695 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1696 | sizeof(struct nvme_command)); | |
1697 | if (result > 0) | |
1698 | dev->q_depth = result; | |
1699 | else | |
1700 | nvme_release_cmb(dev); | |
1701 | } | |
1702 | ||
97f6ef64 XY |
1703 | do { |
1704 | size = db_bar_size(dev, nr_io_queues); | |
1705 | result = nvme_remap_bar(dev, size); | |
1706 | if (!result) | |
1707 | break; | |
1708 | if (!--nr_io_queues) | |
1709 | return -ENOMEM; | |
1710 | } while (1); | |
1711 | adminq->q_db = dev->dbs; | |
f1938f6e | 1712 | |
9d713c2b | 1713 | /* Deregister the admin queue's interrupt */ |
0ff199cb | 1714 | pci_free_irq(pdev, 0, adminq); |
9d713c2b | 1715 | |
e32efbfc JA |
1716 | /* |
1717 | * If we enable msix early due to not intx, disable it again before | |
1718 | * setting up the full range we need. | |
1719 | */ | |
dca51e78 CH |
1720 | pci_free_irq_vectors(pdev); |
1721 | nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, | |
1722 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); | |
1723 | if (nr_io_queues <= 0) | |
1724 | return -EIO; | |
1725 | dev->max_qid = nr_io_queues; | |
fa08a396 | 1726 | |
063a8096 MW |
1727 | /* |
1728 | * Should investigate if there's a performance win from allocating | |
1729 | * more queues than interrupt vectors; it might allow the submission | |
1730 | * path to scale better, even if the receive path is limited by the | |
1731 | * number of interrupts. | |
1732 | */ | |
063a8096 | 1733 | |
dca51e78 | 1734 | result = queue_request_irq(adminq); |
758dd7fd JD |
1735 | if (result) { |
1736 | adminq->cq_vector = -1; | |
d4875622 | 1737 | return result; |
758dd7fd | 1738 | } |
749941f2 | 1739 | return nvme_create_io_queues(dev); |
b60503ba MW |
1740 | } |
1741 | ||
2a842aca | 1742 | static void nvme_del_queue_end(struct request *req, blk_status_t error) |
a5768aa8 | 1743 | { |
db3cbfff | 1744 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1745 | |
db3cbfff KB |
1746 | blk_mq_free_request(req); |
1747 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1748 | } |
1749 | ||
2a842aca | 1750 | static void nvme_del_cq_end(struct request *req, blk_status_t error) |
a5768aa8 | 1751 | { |
db3cbfff | 1752 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1753 | |
db3cbfff KB |
1754 | if (!error) { |
1755 | unsigned long flags; | |
1756 | ||
2e39e0f6 ML |
1757 | /* |
1758 | * We might be called with the AQ q_lock held | |
1759 | * and the I/O queue q_lock should always | |
1760 | * nest inside the AQ one. | |
1761 | */ | |
1762 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1763 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1764 | nvme_process_cq(nvmeq); |
1765 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1766 | } |
db3cbfff KB |
1767 | |
1768 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1769 | } |
1770 | ||
db3cbfff | 1771 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1772 | { |
db3cbfff KB |
1773 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1774 | struct request *req; | |
1775 | struct nvme_command cmd; | |
bda4e0fb | 1776 | |
db3cbfff KB |
1777 | memset(&cmd, 0, sizeof(cmd)); |
1778 | cmd.delete_queue.opcode = opcode; | |
1779 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1780 | |
eb71f435 | 1781 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
1782 | if (IS_ERR(req)) |
1783 | return PTR_ERR(req); | |
bda4e0fb | 1784 | |
db3cbfff KB |
1785 | req->timeout = ADMIN_TIMEOUT; |
1786 | req->end_io_data = nvmeq; | |
1787 | ||
1788 | blk_execute_rq_nowait(q, NULL, req, false, | |
1789 | opcode == nvme_admin_delete_cq ? | |
1790 | nvme_del_cq_end : nvme_del_queue_end); | |
1791 | return 0; | |
bda4e0fb KB |
1792 | } |
1793 | ||
70659060 | 1794 | static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) |
a5768aa8 | 1795 | { |
70659060 | 1796 | int pass; |
db3cbfff KB |
1797 | unsigned long timeout; |
1798 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1799 | |
db3cbfff | 1800 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 1801 | int sent = 0, i = queues; |
db3cbfff KB |
1802 | |
1803 | reinit_completion(&dev->ioq_wait); | |
1804 | retry: | |
1805 | timeout = ADMIN_TIMEOUT; | |
c21377f8 GKB |
1806 | for (; i > 0; i--, sent++) |
1807 | if (nvme_delete_queue(dev->queues[i], opcode)) | |
db3cbfff | 1808 | break; |
c21377f8 | 1809 | |
db3cbfff KB |
1810 | while (sent--) { |
1811 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1812 | if (timeout == 0) | |
1813 | return; | |
1814 | if (i) | |
1815 | goto retry; | |
1816 | } | |
1817 | opcode = nvme_admin_delete_cq; | |
1818 | } | |
a5768aa8 KB |
1819 | } |
1820 | ||
422ef0c7 MW |
1821 | /* |
1822 | * Return: error value if an error occurred setting up the queues or calling | |
1823 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1824 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1825 | * failures should be reported. | |
1826 | */ | |
8d85fce7 | 1827 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1828 | { |
5bae7f73 | 1829 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1830 | dev->tagset.ops = &nvme_mq_ops; |
1831 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1832 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1833 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1834 | dev->tagset.queue_depth = | |
a4aea562 | 1835 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1836 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1837 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1838 | dev->tagset.driver_data = dev; | |
b60503ba | 1839 | |
ffe7704d KB |
1840 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1841 | return 0; | |
5bae7f73 | 1842 | dev->ctrl.tagset = &dev->tagset; |
f9f38e33 HK |
1843 | |
1844 | nvme_dbbuf_set(dev); | |
949928c1 KB |
1845 | } else { |
1846 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1847 | ||
1848 | /* Free previously allocated queues that are no longer usable */ | |
1849 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1850 | } |
949928c1 | 1851 | |
e1e5e564 | 1852 | return 0; |
b60503ba MW |
1853 | } |
1854 | ||
b00a726a | 1855 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1856 | { |
42f61420 | 1857 | u64 cap; |
b00a726a | 1858 | int result = -ENOMEM; |
e75ec752 | 1859 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1860 | |
1861 | if (pci_enable_device_mem(pdev)) | |
1862 | return result; | |
1863 | ||
0877cb0d | 1864 | pci_set_master(pdev); |
0877cb0d | 1865 | |
e75ec752 CH |
1866 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1867 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1868 | goto disable; |
0877cb0d | 1869 | |
7a67cbea | 1870 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1871 | result = -ENODEV; |
b00a726a | 1872 | goto disable; |
0e53d180 | 1873 | } |
e32efbfc JA |
1874 | |
1875 | /* | |
a5229050 KB |
1876 | * Some devices and/or platforms don't advertise or work with INTx |
1877 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1878 | * adjust this later. | |
e32efbfc | 1879 | */ |
dca51e78 CH |
1880 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
1881 | if (result < 0) | |
1882 | return result; | |
e32efbfc | 1883 | |
7a67cbea CH |
1884 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1885 | ||
42f61420 KB |
1886 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1887 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1888 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1889 | |
1890 | /* | |
1891 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1892 | * some MacBook7,1 to avoid controller resets and data loss. | |
1893 | */ | |
1894 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1895 | dev->q_depth = 2; | |
9bdcfb10 CH |
1896 | dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " |
1897 | "set queue depth=%u to work around controller resets\n", | |
1f390c1f SG |
1898 | dev->q_depth); |
1899 | } | |
1900 | ||
202021c1 SB |
1901 | /* |
1902 | * CMBs can currently only exist on >=1.2 PCIe devices. We only | |
1903 | * populate sysfs if a CMB is implemented. Note that we add the | |
1904 | * CMB attribute to the nvme_ctrl kobj which removes the need to remove | |
1905 | * it on exit. Since nvme_dev_attrs_group has no name we can pass | |
1906 | * NULL as final argument to sysfs_add_file_to_group. | |
1907 | */ | |
1908 | ||
8ef2074d | 1909 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { |
8ffaadf7 | 1910 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1911 | |
202021c1 SB |
1912 | if (dev->cmbsz) { |
1913 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, | |
1914 | &dev_attr_cmb.attr, NULL)) | |
9bdcfb10 | 1915 | dev_warn(dev->ctrl.device, |
202021c1 SB |
1916 | "failed to add sysfs attribute for CMB\n"); |
1917 | } | |
1918 | } | |
1919 | ||
a0a3408e KB |
1920 | pci_enable_pcie_error_reporting(pdev); |
1921 | pci_save_state(pdev); | |
0877cb0d KB |
1922 | return 0; |
1923 | ||
1924 | disable: | |
0877cb0d KB |
1925 | pci_disable_device(pdev); |
1926 | return result; | |
1927 | } | |
1928 | ||
1929 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1930 | { |
1931 | if (dev->bar) | |
1932 | iounmap(dev->bar); | |
a1f447b3 | 1933 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
1934 | } |
1935 | ||
1936 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1937 | { |
e75ec752 CH |
1938 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1939 | ||
f63572df | 1940 | nvme_release_cmb(dev); |
dca51e78 | 1941 | pci_free_irq_vectors(pdev); |
0877cb0d | 1942 | |
a0a3408e KB |
1943 | if (pci_is_enabled(pdev)) { |
1944 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1945 | pci_disable_device(pdev); |
4d115420 | 1946 | } |
4d115420 KB |
1947 | } |
1948 | ||
a5cdb68c | 1949 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1950 | { |
70659060 | 1951 | int i, queues; |
302ad8cc KB |
1952 | bool dead = true; |
1953 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
22404274 | 1954 | |
77bf25ea | 1955 | mutex_lock(&dev->shutdown_lock); |
302ad8cc KB |
1956 | if (pci_is_enabled(pdev)) { |
1957 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1958 | ||
1959 | if (dev->ctrl.state == NVME_CTRL_LIVE) | |
1960 | nvme_start_freeze(&dev->ctrl); | |
1961 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || | |
1962 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 1963 | } |
c21377f8 | 1964 | |
302ad8cc KB |
1965 | /* |
1966 | * Give the controller a chance to complete all entered requests if | |
1967 | * doing a safe shutdown. | |
1968 | */ | |
87ad72a5 CH |
1969 | if (!dead) { |
1970 | if (shutdown) | |
1971 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
1972 | ||
1973 | /* | |
1974 | * If the controller is still alive tell it to stop using the | |
1975 | * host memory buffer. In theory the shutdown / reset should | |
1976 | * make sure that it doesn't access the host memoery anymore, | |
1977 | * but I'd rather be safe than sorry.. | |
1978 | */ | |
1979 | if (dev->host_mem_descs) | |
1980 | nvme_set_host_mem(dev, 0); | |
1981 | ||
1982 | } | |
302ad8cc KB |
1983 | nvme_stop_queues(&dev->ctrl); |
1984 | ||
70659060 | 1985 | queues = dev->online_queues - 1; |
c21377f8 GKB |
1986 | for (i = dev->queue_count - 1; i > 0; i--) |
1987 | nvme_suspend_queue(dev->queues[i]); | |
1988 | ||
302ad8cc | 1989 | if (dead) { |
82469c59 GKB |
1990 | /* A device might become IO incapable very soon during |
1991 | * probe, before the admin queue is configured. Thus, | |
1992 | * queue_count can be 0 here. | |
1993 | */ | |
1994 | if (dev->queue_count) | |
1995 | nvme_suspend_queue(dev->queues[0]); | |
4d115420 | 1996 | } else { |
70659060 | 1997 | nvme_disable_io_queues(dev, queues); |
a5cdb68c | 1998 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1999 | } |
b00a726a | 2000 | nvme_pci_disable(dev); |
07836e65 | 2001 | |
e1958e65 ML |
2002 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
2003 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
302ad8cc KB |
2004 | |
2005 | /* | |
2006 | * The driver will not be starting up queues again if shutting down so | |
2007 | * must flush all entered requests to their failed completion to avoid | |
2008 | * deadlocking blk-mq hot-cpu notifier. | |
2009 | */ | |
2010 | if (shutdown) | |
2011 | nvme_start_queues(&dev->ctrl); | |
77bf25ea | 2012 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
2013 | } |
2014 | ||
091b6092 MW |
2015 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2016 | { | |
e75ec752 | 2017 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2018 | PAGE_SIZE, PAGE_SIZE, 0); |
2019 | if (!dev->prp_page_pool) | |
2020 | return -ENOMEM; | |
2021 | ||
99802a7a | 2022 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2023 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2024 | 256, 256, 0); |
2025 | if (!dev->prp_small_pool) { | |
2026 | dma_pool_destroy(dev->prp_page_pool); | |
2027 | return -ENOMEM; | |
2028 | } | |
091b6092 MW |
2029 | return 0; |
2030 | } | |
2031 | ||
2032 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2033 | { | |
2034 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2035 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2036 | } |
2037 | ||
1673f1f0 | 2038 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2039 | { |
1673f1f0 | 2040 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2041 | |
f9f38e33 | 2042 | nvme_dbbuf_dma_free(dev); |
e75ec752 | 2043 | put_device(dev->dev); |
4af0e21c KB |
2044 | if (dev->tagset.tags) |
2045 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2046 | if (dev->ctrl.admin_q) |
2047 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 2048 | kfree(dev->queues); |
e286bcfc | 2049 | free_opal_dev(dev->ctrl.opal_dev); |
5e82e952 KB |
2050 | kfree(dev); |
2051 | } | |
2052 | ||
f58944e2 KB |
2053 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
2054 | { | |
237045fc | 2055 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
2056 | |
2057 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 2058 | nvme_dev_disable(dev, false); |
f58944e2 KB |
2059 | if (!schedule_work(&dev->remove_work)) |
2060 | nvme_put_ctrl(&dev->ctrl); | |
2061 | } | |
2062 | ||
fd634f41 | 2063 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 2064 | { |
d86c4d8e CH |
2065 | struct nvme_dev *dev = |
2066 | container_of(work, struct nvme_dev, ctrl.reset_work); | |
a98e58e5 | 2067 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
f58944e2 | 2068 | int result = -ENODEV; |
5e82e952 | 2069 | |
82b057ca | 2070 | if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) |
fd634f41 | 2071 | goto out; |
5e82e952 | 2072 | |
fd634f41 CH |
2073 | /* |
2074 | * If we're called to reset a live controller first shut it down before | |
2075 | * moving on. | |
2076 | */ | |
b00a726a | 2077 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 2078 | nvme_dev_disable(dev, false); |
5e82e952 | 2079 | |
b00a726a | 2080 | result = nvme_pci_enable(dev); |
f0b50732 | 2081 | if (result) |
3cf519b5 | 2082 | goto out; |
f0b50732 KB |
2083 | |
2084 | result = nvme_configure_admin_queue(dev); | |
2085 | if (result) | |
f58944e2 | 2086 | goto out; |
f0b50732 | 2087 | |
a4aea562 | 2088 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
2089 | result = nvme_alloc_admin_tags(dev); |
2090 | if (result) | |
f58944e2 | 2091 | goto out; |
b9afca3e | 2092 | |
ce4541f4 CH |
2093 | result = nvme_init_identify(&dev->ctrl); |
2094 | if (result) | |
f58944e2 | 2095 | goto out; |
ce4541f4 | 2096 | |
e286bcfc SB |
2097 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
2098 | if (!dev->ctrl.opal_dev) | |
2099 | dev->ctrl.opal_dev = | |
2100 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); | |
2101 | else if (was_suspend) | |
2102 | opal_unlock_from_suspend(dev->ctrl.opal_dev); | |
2103 | } else { | |
2104 | free_opal_dev(dev->ctrl.opal_dev); | |
2105 | dev->ctrl.opal_dev = NULL; | |
4f1244c8 | 2106 | } |
a98e58e5 | 2107 | |
f9f38e33 HK |
2108 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
2109 | result = nvme_dbbuf_dma_alloc(dev); | |
2110 | if (result) | |
2111 | dev_warn(dev->dev, | |
2112 | "unable to allocate dma for dbbuf\n"); | |
2113 | } | |
2114 | ||
87ad72a5 CH |
2115 | if (dev->ctrl.hmpre) |
2116 | nvme_setup_host_mem(dev); | |
2117 | ||
f0b50732 | 2118 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2119 | if (result) |
f58944e2 | 2120 | goto out; |
f0b50732 | 2121 | |
21f033f7 KB |
2122 | /* |
2123 | * A controller that can not execute IO typically requires user | |
2124 | * intervention to correct. For such degraded controllers, the driver | |
2125 | * should not submit commands the user did not request, so skip | |
2126 | * registering for asynchronous event notification on this condition. | |
2127 | */ | |
f866fc42 CH |
2128 | if (dev->online_queues > 1) |
2129 | nvme_queue_async_events(&dev->ctrl); | |
3cf519b5 | 2130 | |
2659e57b CH |
2131 | /* |
2132 | * Keep the controller around but remove all namespaces if we don't have | |
2133 | * any working I/O queue. | |
2134 | */ | |
3cf519b5 | 2135 | if (dev->online_queues < 2) { |
1b3c47c1 | 2136 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 2137 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 2138 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 2139 | } else { |
25646264 | 2140 | nvme_start_queues(&dev->ctrl); |
302ad8cc | 2141 | nvme_wait_freeze(&dev->ctrl); |
3cf519b5 | 2142 | nvme_dev_add(dev); |
302ad8cc | 2143 | nvme_unfreeze(&dev->ctrl); |
3cf519b5 CH |
2144 | } |
2145 | ||
bb8d261e CH |
2146 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
2147 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
2148 | goto out; | |
2149 | } | |
92911a55 CH |
2150 | |
2151 | if (dev->online_queues > 1) | |
5955be21 | 2152 | nvme_queue_scan(&dev->ctrl); |
3cf519b5 | 2153 | return; |
f0b50732 | 2154 | |
3cf519b5 | 2155 | out: |
f58944e2 | 2156 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
2157 | } |
2158 | ||
5c8809e6 | 2159 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2160 | { |
5c8809e6 | 2161 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2162 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 2163 | |
69d9a99c | 2164 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 2165 | if (pci_get_drvdata(pdev)) |
921920ab | 2166 | device_release_driver(&pdev->dev); |
1673f1f0 | 2167 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2168 | } |
2169 | ||
1c63dc66 | 2170 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2171 | { |
1c63dc66 | 2172 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2173 | return 0; |
9ca97374 TH |
2174 | } |
2175 | ||
5fd4ce1b | 2176 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2177 | { |
5fd4ce1b CH |
2178 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2179 | return 0; | |
2180 | } | |
4cc06521 | 2181 | |
7fd8930f CH |
2182 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2183 | { | |
2184 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2185 | return 0; | |
4cc06521 KB |
2186 | } |
2187 | ||
1c63dc66 | 2188 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 2189 | .name = "pcie", |
e439bb12 | 2190 | .module = THIS_MODULE, |
c81bfba9 | 2191 | .flags = NVME_F_METADATA_SUPPORTED, |
1c63dc66 | 2192 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 2193 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2194 | .reg_read64 = nvme_pci_reg_read64, |
1673f1f0 | 2195 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 2196 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 2197 | }; |
4cc06521 | 2198 | |
b00a726a KB |
2199 | static int nvme_dev_map(struct nvme_dev *dev) |
2200 | { | |
b00a726a KB |
2201 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2202 | ||
a1f447b3 | 2203 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
2204 | return -ENODEV; |
2205 | ||
97f6ef64 | 2206 | if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) |
b00a726a KB |
2207 | goto release; |
2208 | ||
9fa196e7 | 2209 | return 0; |
b00a726a | 2210 | release: |
9fa196e7 MG |
2211 | pci_release_mem_regions(pdev); |
2212 | return -ENODEV; | |
b00a726a KB |
2213 | } |
2214 | ||
ff5350a8 AL |
2215 | static unsigned long check_dell_samsung_bug(struct pci_dev *pdev) |
2216 | { | |
2217 | if (pdev->vendor == 0x144d && pdev->device == 0xa802) { | |
2218 | /* | |
2219 | * Several Samsung devices seem to drop off the PCIe bus | |
2220 | * randomly when APST is on and uses the deepest sleep state. | |
2221 | * This has been observed on a Samsung "SM951 NVMe SAMSUNG | |
2222 | * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD | |
2223 | * 950 PRO 256GB", but it seems to be restricted to two Dell | |
2224 | * laptops. | |
2225 | */ | |
2226 | if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && | |
2227 | (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || | |
2228 | dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) | |
2229 | return NVME_QUIRK_NO_DEEPEST_PS; | |
2230 | } | |
2231 | ||
2232 | return 0; | |
2233 | } | |
2234 | ||
8d85fce7 | 2235 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2236 | { |
a4aea562 | 2237 | int node, result = -ENOMEM; |
b60503ba | 2238 | struct nvme_dev *dev; |
ff5350a8 | 2239 | unsigned long quirks = id->driver_data; |
b60503ba | 2240 | |
a4aea562 MB |
2241 | node = dev_to_node(&pdev->dev); |
2242 | if (node == NUMA_NO_NODE) | |
2fa84351 | 2243 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
2244 | |
2245 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2246 | if (!dev) |
2247 | return -ENOMEM; | |
a4aea562 MB |
2248 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2249 | GFP_KERNEL, node); | |
b60503ba MW |
2250 | if (!dev->queues) |
2251 | goto free; | |
2252 | ||
e75ec752 | 2253 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2254 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2255 | |
b00a726a KB |
2256 | result = nvme_dev_map(dev); |
2257 | if (result) | |
2258 | goto free; | |
2259 | ||
d86c4d8e | 2260 | INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); |
5c8809e6 | 2261 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2262 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2263 | init_completion(&dev->ioq_wait); |
b60503ba | 2264 | |
091b6092 MW |
2265 | result = nvme_setup_prp_pools(dev); |
2266 | if (result) | |
a96d4f5c | 2267 | goto put_pci; |
4cc06521 | 2268 | |
ff5350a8 AL |
2269 | quirks |= check_dell_samsung_bug(pdev); |
2270 | ||
f3ca80fc | 2271 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
ff5350a8 | 2272 | quirks); |
4cc06521 | 2273 | if (result) |
2e1d8448 | 2274 | goto release_pools; |
740216fc | 2275 | |
82b057ca | 2276 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING); |
1b3c47c1 SG |
2277 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2278 | ||
d86c4d8e | 2279 | queue_work(nvme_wq, &dev->ctrl.reset_work); |
b60503ba MW |
2280 | return 0; |
2281 | ||
0877cb0d | 2282 | release_pools: |
091b6092 | 2283 | nvme_release_prp_pools(dev); |
a96d4f5c | 2284 | put_pci: |
e75ec752 | 2285 | put_device(dev->dev); |
b00a726a | 2286 | nvme_dev_unmap(dev); |
b60503ba MW |
2287 | free: |
2288 | kfree(dev->queues); | |
b60503ba MW |
2289 | kfree(dev); |
2290 | return result; | |
2291 | } | |
2292 | ||
f0d54a54 KB |
2293 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2294 | { | |
a6739479 | 2295 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2296 | |
a6739479 | 2297 | if (prepare) |
a5cdb68c | 2298 | nvme_dev_disable(dev, false); |
a6739479 | 2299 | else |
d86c4d8e | 2300 | nvme_reset_ctrl(&dev->ctrl); |
f0d54a54 KB |
2301 | } |
2302 | ||
09ece142 KB |
2303 | static void nvme_shutdown(struct pci_dev *pdev) |
2304 | { | |
2305 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2306 | nvme_dev_disable(dev, true); |
09ece142 KB |
2307 | } |
2308 | ||
f58944e2 KB |
2309 | /* |
2310 | * The driver's remove may be called on a device in a partially initialized | |
2311 | * state. This function must not have any dependencies on the device state in | |
2312 | * order to proceed. | |
2313 | */ | |
8d85fce7 | 2314 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2315 | { |
2316 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2317 | |
bb8d261e CH |
2318 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2319 | ||
d86c4d8e | 2320 | cancel_work_sync(&dev->ctrl.reset_work); |
9a6b9458 | 2321 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 2322 | |
6db28eda | 2323 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 2324 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
6db28eda KB |
2325 | nvme_dev_disable(dev, false); |
2326 | } | |
0ff9d4e1 | 2327 | |
d86c4d8e | 2328 | flush_work(&dev->ctrl.reset_work); |
53029b04 | 2329 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 2330 | nvme_dev_disable(dev, true); |
87ad72a5 | 2331 | nvme_free_host_mem(dev); |
a4aea562 | 2332 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2333 | nvme_free_queues(dev, 0); |
9a6b9458 | 2334 | nvme_release_prp_pools(dev); |
b00a726a | 2335 | nvme_dev_unmap(dev); |
1673f1f0 | 2336 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2337 | } |
2338 | ||
13880f5b KB |
2339 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2340 | { | |
2341 | int ret = 0; | |
2342 | ||
2343 | if (numvfs == 0) { | |
2344 | if (pci_vfs_assigned(pdev)) { | |
2345 | dev_warn(&pdev->dev, | |
2346 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2347 | return -EPERM; | |
2348 | } | |
2349 | pci_disable_sriov(pdev); | |
2350 | return 0; | |
2351 | } | |
2352 | ||
2353 | ret = pci_enable_sriov(pdev, numvfs); | |
2354 | return ret ? ret : numvfs; | |
2355 | } | |
2356 | ||
671a6018 | 2357 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2358 | static int nvme_suspend(struct device *dev) |
2359 | { | |
2360 | struct pci_dev *pdev = to_pci_dev(dev); | |
2361 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2362 | ||
a5cdb68c | 2363 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2364 | return 0; |
2365 | } | |
2366 | ||
2367 | static int nvme_resume(struct device *dev) | |
2368 | { | |
2369 | struct pci_dev *pdev = to_pci_dev(dev); | |
2370 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2371 | |
d86c4d8e | 2372 | nvme_reset_ctrl(&ndev->ctrl); |
9a6b9458 | 2373 | return 0; |
cd638946 | 2374 | } |
671a6018 | 2375 | #endif |
cd638946 KB |
2376 | |
2377 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2378 | |
a0a3408e KB |
2379 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2380 | pci_channel_state_t state) | |
2381 | { | |
2382 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2383 | ||
2384 | /* | |
2385 | * A frozen channel requires a reset. When detected, this method will | |
2386 | * shutdown the controller to quiesce. The controller will be restarted | |
2387 | * after the slot reset through driver's slot_reset callback. | |
2388 | */ | |
a0a3408e KB |
2389 | switch (state) { |
2390 | case pci_channel_io_normal: | |
2391 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2392 | case pci_channel_io_frozen: | |
d011fb31 KB |
2393 | dev_warn(dev->ctrl.device, |
2394 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2395 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2396 | return PCI_ERS_RESULT_NEED_RESET; |
2397 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2398 | dev_warn(dev->ctrl.device, |
2399 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2400 | return PCI_ERS_RESULT_DISCONNECT; |
2401 | } | |
2402 | return PCI_ERS_RESULT_NEED_RESET; | |
2403 | } | |
2404 | ||
2405 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2406 | { | |
2407 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2408 | ||
1b3c47c1 | 2409 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2410 | pci_restore_state(pdev); |
d86c4d8e | 2411 | nvme_reset_ctrl(&dev->ctrl); |
a0a3408e KB |
2412 | return PCI_ERS_RESULT_RECOVERED; |
2413 | } | |
2414 | ||
2415 | static void nvme_error_resume(struct pci_dev *pdev) | |
2416 | { | |
2417 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2418 | } | |
2419 | ||
1d352035 | 2420 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2421 | .error_detected = nvme_error_detected, |
b60503ba MW |
2422 | .slot_reset = nvme_slot_reset, |
2423 | .resume = nvme_error_resume, | |
f0d54a54 | 2424 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2425 | }; |
2426 | ||
6eb0d698 | 2427 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2428 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 | 2429 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 2430 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2431 | { PCI_VDEVICE(INTEL, 0x0a53), |
2432 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2433 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2434 | { PCI_VDEVICE(INTEL, 0x0a54), |
2435 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2436 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
50af47d0 AL |
2437 | { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ |
2438 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, | |
540c801c KB |
2439 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2440 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
54adc010 GP |
2441 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2442 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2443 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2444 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
b60503ba | 2445 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2446 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
124298bd | 2447 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
b60503ba MW |
2448 | { 0, } |
2449 | }; | |
2450 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2451 | ||
2452 | static struct pci_driver nvme_driver = { | |
2453 | .name = "nvme", | |
2454 | .id_table = nvme_id_table, | |
2455 | .probe = nvme_probe, | |
8d85fce7 | 2456 | .remove = nvme_remove, |
09ece142 | 2457 | .shutdown = nvme_shutdown, |
cd638946 KB |
2458 | .driver = { |
2459 | .pm = &nvme_dev_pm_ops, | |
2460 | }, | |
13880f5b | 2461 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2462 | .err_handler = &nvme_err_handler, |
2463 | }; | |
2464 | ||
2465 | static int __init nvme_init(void) | |
2466 | { | |
9a6327d2 | 2467 | return pci_register_driver(&nvme_driver); |
b60503ba MW |
2468 | } |
2469 | ||
2470 | static void __exit nvme_exit(void) | |
2471 | { | |
2472 | pci_unregister_driver(&nvme_driver); | |
21bd78bc | 2473 | _nvme_check_size(); |
b60503ba MW |
2474 | } |
2475 | ||
2476 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2477 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2478 | MODULE_VERSION("1.0"); |
b60503ba MW |
2479 | module_init(nvme_init); |
2480 | module_exit(nvme_exit); |