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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
66f7b72e | 23 | #include "cpuid.h" |
e495606d | 24 | |
6aa8b732 | 25 | #include <linux/module.h> |
ae759544 | 26 | #include <linux/mod_devicetable.h> |
9d8f549d | 27 | #include <linux/kernel.h> |
6aa8b732 AK |
28 | #include <linux/vmalloc.h> |
29 | #include <linux/highmem.h> | |
e8edc6e0 | 30 | #include <linux/sched.h> |
229456fc | 31 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
6aa8b732 | 33 | |
1018faa6 | 34 | #include <asm/perf_event.h> |
67ec6607 | 35 | #include <asm/tlbflush.h> |
e495606d | 36 | #include <asm/desc.h> |
facb0139 | 37 | #include <asm/debugreg.h> |
631bc487 | 38 | #include <asm/kvm_para.h> |
6aa8b732 | 39 | |
63d1142f | 40 | #include <asm/virtext.h> |
229456fc | 41 | #include "trace.h" |
63d1142f | 42 | |
4ecac3fd AK |
43 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
44 | ||
6aa8b732 AK |
45 | MODULE_AUTHOR("Qumranet"); |
46 | MODULE_LICENSE("GPL"); | |
47 | ||
ae759544 JT |
48 | static const struct x86_cpu_id svm_cpu_id[] = { |
49 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
50 | {} | |
51 | }; | |
52 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
53 | ||
6aa8b732 AK |
54 | #define IOPM_ALLOC_ORDER 2 |
55 | #define MSRPM_ALLOC_ORDER 1 | |
56 | ||
6aa8b732 AK |
57 | #define SEG_TYPE_LDT 2 |
58 | #define SEG_TYPE_BUSY_TSS16 3 | |
59 | ||
6bc31bdc AP |
60 | #define SVM_FEATURE_NPT (1 << 0) |
61 | #define SVM_FEATURE_LBRV (1 << 1) | |
62 | #define SVM_FEATURE_SVML (1 << 2) | |
63 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
64 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
65 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
66 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
67 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 68 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 69 | |
410e4d57 JR |
70 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
71 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
72 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
73 | ||
24e09cbf JR |
74 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
75 | ||
fbc0db76 | 76 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
77 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
78 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 79 | |
67ec6607 JR |
80 | static bool erratum_383_found __read_mostly; |
81 | ||
6c8166a7 AK |
82 | static const u32 host_save_user_msrs[] = { |
83 | #ifdef CONFIG_X86_64 | |
84 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
85 | MSR_FS_BASE, | |
86 | #endif | |
87 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
88 | }; | |
89 | ||
90 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
91 | ||
92 | struct kvm_vcpu; | |
93 | ||
e6aa9abd JR |
94 | struct nested_state { |
95 | struct vmcb *hsave; | |
96 | u64 hsave_msr; | |
4a810181 | 97 | u64 vm_cr_msr; |
e6aa9abd JR |
98 | u64 vmcb; |
99 | ||
100 | /* These are the merged vectors */ | |
101 | u32 *msrpm; | |
102 | ||
103 | /* gpa pointers to the real vectors */ | |
104 | u64 vmcb_msrpm; | |
ce2ac085 | 105 | u64 vmcb_iopm; |
aad42c64 | 106 | |
cd3ff653 JR |
107 | /* A VMEXIT is required but not yet emulated */ |
108 | bool exit_required; | |
109 | ||
aad42c64 | 110 | /* cache for intercepts of the guest */ |
4ee546b4 | 111 | u32 intercept_cr; |
3aed041a | 112 | u32 intercept_dr; |
aad42c64 JR |
113 | u32 intercept_exceptions; |
114 | u64 intercept; | |
115 | ||
5bd2edc3 JR |
116 | /* Nested Paging related state */ |
117 | u64 nested_cr3; | |
e6aa9abd JR |
118 | }; |
119 | ||
323c3d80 JR |
120 | #define MSRPM_OFFSETS 16 |
121 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
122 | ||
2b036c6b BO |
123 | /* |
124 | * Set osvw_len to higher value when updated Revision Guides | |
125 | * are published and we know what the new status bits are | |
126 | */ | |
127 | static uint64_t osvw_len = 4, osvw_status; | |
128 | ||
6c8166a7 AK |
129 | struct vcpu_svm { |
130 | struct kvm_vcpu vcpu; | |
131 | struct vmcb *vmcb; | |
132 | unsigned long vmcb_pa; | |
133 | struct svm_cpu_data *svm_data; | |
134 | uint64_t asid_generation; | |
135 | uint64_t sysenter_esp; | |
136 | uint64_t sysenter_eip; | |
137 | ||
138 | u64 next_rip; | |
139 | ||
140 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 141 | struct { |
dacccfdd AK |
142 | u16 fs; |
143 | u16 gs; | |
144 | u16 ldt; | |
afe9e66f AK |
145 | u64 gs_base; |
146 | } host; | |
6c8166a7 AK |
147 | |
148 | u32 *msrpm; | |
6c8166a7 | 149 | |
bd3d1ec3 AK |
150 | ulong nmi_iret_rip; |
151 | ||
e6aa9abd | 152 | struct nested_state nested; |
6be7d306 JK |
153 | |
154 | bool nmi_singlestep; | |
66b7138f JK |
155 | |
156 | unsigned int3_injected; | |
157 | unsigned long int3_rip; | |
631bc487 | 158 | u32 apf_reason; |
fbc0db76 JR |
159 | |
160 | u64 tsc_ratio; | |
6c8166a7 AK |
161 | }; |
162 | ||
fbc0db76 JR |
163 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
164 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
165 | ||
455716fa JR |
166 | #define MSR_INVALID 0xffffffffU |
167 | ||
09941fbb | 168 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
169 | u32 index; /* Index of the MSR */ |
170 | bool always; /* True if intercept is always on */ | |
171 | } direct_access_msrs[] = { | |
8c06585d | 172 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
173 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
174 | #ifdef CONFIG_X86_64 | |
175 | { .index = MSR_GS_BASE, .always = true }, | |
176 | { .index = MSR_FS_BASE, .always = true }, | |
177 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
178 | { .index = MSR_LSTAR, .always = true }, | |
179 | { .index = MSR_CSTAR, .always = true }, | |
180 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
181 | #endif | |
182 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
183 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
184 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
185 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
186 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
187 | }; |
188 | ||
709ddebf JR |
189 | /* enable NPT for AMD64 and X86 with PAE */ |
190 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
191 | static bool npt_enabled = true; | |
192 | #else | |
e0231715 | 193 | static bool npt_enabled; |
709ddebf | 194 | #endif |
6c7dac72 | 195 | |
e2358851 DB |
196 | /* allow nested paging (virtualized MMU) for all guests */ |
197 | static int npt = true; | |
6c7dac72 | 198 | module_param(npt, int, S_IRUGO); |
e3da3acd | 199 | |
e2358851 DB |
200 | /* allow nested virtualization in KVM/SVM */ |
201 | static int nested = true; | |
236de055 AG |
202 | module_param(nested, int, S_IRUGO); |
203 | ||
44874f84 | 204 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 205 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 206 | |
410e4d57 | 207 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 208 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 209 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
210 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
211 | bool has_error_code, u32 error_code); | |
92a1f12d | 212 | static u64 __scale_tsc(u64 ratio, u64 tsc); |
cf74a78b | 213 | |
8d28fec4 | 214 | enum { |
116a0a23 JR |
215 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
216 | pause filter count */ | |
f56838e4 | 217 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 218 | VMCB_ASID, /* ASID */ |
decdbf6a | 219 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 220 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 221 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 222 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 223 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 224 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 225 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 226 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
8d28fec4 RJ |
227 | VMCB_DIRTY_MAX, |
228 | }; | |
229 | ||
0574dec0 JR |
230 | /* TPR and CR2 are always written before VMRUN */ |
231 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 RJ |
232 | |
233 | static inline void mark_all_dirty(struct vmcb *vmcb) | |
234 | { | |
235 | vmcb->control.clean = 0; | |
236 | } | |
237 | ||
238 | static inline void mark_all_clean(struct vmcb *vmcb) | |
239 | { | |
240 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
241 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
242 | } | |
243 | ||
244 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
245 | { | |
246 | vmcb->control.clean &= ~(1 << bit); | |
247 | } | |
248 | ||
a2fa3e9f GH |
249 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
250 | { | |
fb3f0f51 | 251 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
252 | } |
253 | ||
384c6368 JR |
254 | static void recalc_intercepts(struct vcpu_svm *svm) |
255 | { | |
256 | struct vmcb_control_area *c, *h; | |
257 | struct nested_state *g; | |
258 | ||
116a0a23 JR |
259 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
260 | ||
384c6368 JR |
261 | if (!is_guest_mode(&svm->vcpu)) |
262 | return; | |
263 | ||
264 | c = &svm->vmcb->control; | |
265 | h = &svm->nested.hsave->control; | |
266 | g = &svm->nested; | |
267 | ||
4ee546b4 | 268 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 269 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
270 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
271 | c->intercept = h->intercept | g->intercept; | |
272 | } | |
273 | ||
4ee546b4 RJ |
274 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
275 | { | |
276 | if (is_guest_mode(&svm->vcpu)) | |
277 | return svm->nested.hsave; | |
278 | else | |
279 | return svm->vmcb; | |
280 | } | |
281 | ||
282 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
283 | { | |
284 | struct vmcb *vmcb = get_host_vmcb(svm); | |
285 | ||
286 | vmcb->control.intercept_cr |= (1U << bit); | |
287 | ||
288 | recalc_intercepts(svm); | |
289 | } | |
290 | ||
291 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
292 | { | |
293 | struct vmcb *vmcb = get_host_vmcb(svm); | |
294 | ||
295 | vmcb->control.intercept_cr &= ~(1U << bit); | |
296 | ||
297 | recalc_intercepts(svm); | |
298 | } | |
299 | ||
300 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
301 | { | |
302 | struct vmcb *vmcb = get_host_vmcb(svm); | |
303 | ||
304 | return vmcb->control.intercept_cr & (1U << bit); | |
305 | } | |
306 | ||
5315c716 | 307 | static inline void set_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
308 | { |
309 | struct vmcb *vmcb = get_host_vmcb(svm); | |
310 | ||
5315c716 PB |
311 | vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) |
312 | | (1 << INTERCEPT_DR1_READ) | |
313 | | (1 << INTERCEPT_DR2_READ) | |
314 | | (1 << INTERCEPT_DR3_READ) | |
315 | | (1 << INTERCEPT_DR4_READ) | |
316 | | (1 << INTERCEPT_DR5_READ) | |
317 | | (1 << INTERCEPT_DR6_READ) | |
318 | | (1 << INTERCEPT_DR7_READ) | |
319 | | (1 << INTERCEPT_DR0_WRITE) | |
320 | | (1 << INTERCEPT_DR1_WRITE) | |
321 | | (1 << INTERCEPT_DR2_WRITE) | |
322 | | (1 << INTERCEPT_DR3_WRITE) | |
323 | | (1 << INTERCEPT_DR4_WRITE) | |
324 | | (1 << INTERCEPT_DR5_WRITE) | |
325 | | (1 << INTERCEPT_DR6_WRITE) | |
326 | | (1 << INTERCEPT_DR7_WRITE); | |
3aed041a JR |
327 | |
328 | recalc_intercepts(svm); | |
329 | } | |
330 | ||
5315c716 | 331 | static inline void clr_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
332 | { |
333 | struct vmcb *vmcb = get_host_vmcb(svm); | |
334 | ||
5315c716 | 335 | vmcb->control.intercept_dr = 0; |
3aed041a JR |
336 | |
337 | recalc_intercepts(svm); | |
338 | } | |
339 | ||
18c918c5 JR |
340 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
341 | { | |
342 | struct vmcb *vmcb = get_host_vmcb(svm); | |
343 | ||
344 | vmcb->control.intercept_exceptions |= (1U << bit); | |
345 | ||
346 | recalc_intercepts(svm); | |
347 | } | |
348 | ||
349 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
350 | { | |
351 | struct vmcb *vmcb = get_host_vmcb(svm); | |
352 | ||
353 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
354 | ||
355 | recalc_intercepts(svm); | |
356 | } | |
357 | ||
8a05a1b8 JR |
358 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
359 | { | |
360 | struct vmcb *vmcb = get_host_vmcb(svm); | |
361 | ||
362 | vmcb->control.intercept |= (1ULL << bit); | |
363 | ||
364 | recalc_intercepts(svm); | |
365 | } | |
366 | ||
367 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
368 | { | |
369 | struct vmcb *vmcb = get_host_vmcb(svm); | |
370 | ||
371 | vmcb->control.intercept &= ~(1ULL << bit); | |
372 | ||
373 | recalc_intercepts(svm); | |
374 | } | |
375 | ||
2af9194d JR |
376 | static inline void enable_gif(struct vcpu_svm *svm) |
377 | { | |
378 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
379 | } | |
380 | ||
381 | static inline void disable_gif(struct vcpu_svm *svm) | |
382 | { | |
383 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
384 | } | |
385 | ||
386 | static inline bool gif_set(struct vcpu_svm *svm) | |
387 | { | |
388 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
389 | } | |
390 | ||
4866d5e3 | 391 | static unsigned long iopm_base; |
6aa8b732 AK |
392 | |
393 | struct kvm_ldttss_desc { | |
394 | u16 limit0; | |
395 | u16 base0; | |
e0231715 JR |
396 | unsigned base1:8, type:5, dpl:2, p:1; |
397 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
398 | u32 base3; |
399 | u32 zero1; | |
400 | } __attribute__((packed)); | |
401 | ||
402 | struct svm_cpu_data { | |
403 | int cpu; | |
404 | ||
5008fdf5 AK |
405 | u64 asid_generation; |
406 | u32 max_asid; | |
407 | u32 next_asid; | |
6aa8b732 AK |
408 | struct kvm_ldttss_desc *tss_desc; |
409 | ||
410 | struct page *save_area; | |
411 | }; | |
412 | ||
413 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
414 | ||
415 | struct svm_init_data { | |
416 | int cpu; | |
417 | int r; | |
418 | }; | |
419 | ||
09941fbb | 420 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 421 | |
9d8f549d | 422 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
423 | #define MSRS_RANGE_SIZE 2048 |
424 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
425 | ||
455716fa JR |
426 | static u32 svm_msrpm_offset(u32 msr) |
427 | { | |
428 | u32 offset; | |
429 | int i; | |
430 | ||
431 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
432 | if (msr < msrpm_ranges[i] || | |
433 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
434 | continue; | |
435 | ||
436 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
437 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
438 | ||
439 | /* Now we have the u8 offset - but need the u32 offset */ | |
440 | return offset / 4; | |
441 | } | |
442 | ||
443 | /* MSR not in any range */ | |
444 | return MSR_INVALID; | |
445 | } | |
446 | ||
6aa8b732 AK |
447 | #define MAX_INST_SIZE 15 |
448 | ||
6aa8b732 AK |
449 | static inline void clgi(void) |
450 | { | |
4ecac3fd | 451 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
452 | } |
453 | ||
454 | static inline void stgi(void) | |
455 | { | |
4ecac3fd | 456 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
457 | } |
458 | ||
459 | static inline void invlpga(unsigned long addr, u32 asid) | |
460 | { | |
e0231715 | 461 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
462 | } |
463 | ||
4b16184c JR |
464 | static int get_npt_level(void) |
465 | { | |
466 | #ifdef CONFIG_X86_64 | |
467 | return PT64_ROOT_LEVEL; | |
468 | #else | |
469 | return PT32E_ROOT_LEVEL; | |
470 | #endif | |
471 | } | |
472 | ||
6aa8b732 AK |
473 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
474 | { | |
6dc696d4 | 475 | vcpu->arch.efer = efer; |
709ddebf | 476 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 477 | efer &= ~EFER_LME; |
6aa8b732 | 478 | |
9962d032 | 479 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 480 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
481 | } |
482 | ||
6aa8b732 AK |
483 | static int is_external_interrupt(u32 info) |
484 | { | |
485 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
486 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
487 | } | |
488 | ||
2809f5d2 GC |
489 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
490 | { | |
491 | struct vcpu_svm *svm = to_svm(vcpu); | |
492 | u32 ret = 0; | |
493 | ||
494 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 495 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
496 | return ret & mask; |
497 | } | |
498 | ||
499 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
500 | { | |
501 | struct vcpu_svm *svm = to_svm(vcpu); | |
502 | ||
503 | if (mask == 0) | |
504 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
505 | else | |
506 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
507 | ||
508 | } | |
509 | ||
6aa8b732 AK |
510 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
511 | { | |
a2fa3e9f GH |
512 | struct vcpu_svm *svm = to_svm(vcpu); |
513 | ||
6bc31bdc AP |
514 | if (svm->vmcb->control.next_rip != 0) |
515 | svm->next_rip = svm->vmcb->control.next_rip; | |
516 | ||
a2fa3e9f | 517 | if (!svm->next_rip) { |
51d8b661 | 518 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
519 | EMULATE_DONE) |
520 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
521 | return; |
522 | } | |
5fdbf976 MT |
523 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
524 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
525 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 526 | |
5fdbf976 | 527 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 528 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
529 | } |
530 | ||
116a4752 | 531 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
532 | bool has_error_code, u32 error_code, |
533 | bool reinject) | |
116a4752 JK |
534 | { |
535 | struct vcpu_svm *svm = to_svm(vcpu); | |
536 | ||
e0231715 JR |
537 | /* |
538 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
539 | * handle the exception | |
540 | */ | |
ce7ddec4 JR |
541 | if (!reinject && |
542 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
543 | return; |
544 | ||
2a6b20b8 | 545 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
546 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
547 | ||
548 | /* | |
549 | * For guest debugging where we have to reinject #BP if some | |
550 | * INT3 is guest-owned: | |
551 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
552 | * raises a fault that is not intercepted. Still better than | |
553 | * failing in all cases. | |
554 | */ | |
555 | skip_emulated_instruction(&svm->vcpu); | |
556 | rip = kvm_rip_read(&svm->vcpu); | |
557 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
558 | svm->int3_injected = rip - old_rip; | |
559 | } | |
560 | ||
116a4752 JK |
561 | svm->vmcb->control.event_inj = nr |
562 | | SVM_EVTINJ_VALID | |
563 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
564 | | SVM_EVTINJ_TYPE_EXEPT; | |
565 | svm->vmcb->control.event_inj_err = error_code; | |
566 | } | |
567 | ||
67ec6607 JR |
568 | static void svm_init_erratum_383(void) |
569 | { | |
570 | u32 low, high; | |
571 | int err; | |
572 | u64 val; | |
573 | ||
e6ee94d5 | 574 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
575 | return; |
576 | ||
577 | /* Use _safe variants to not break nested virtualization */ | |
578 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
579 | if (err) | |
580 | return; | |
581 | ||
582 | val |= (1ULL << 47); | |
583 | ||
584 | low = lower_32_bits(val); | |
585 | high = upper_32_bits(val); | |
586 | ||
587 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
588 | ||
589 | erratum_383_found = true; | |
590 | } | |
591 | ||
2b036c6b BO |
592 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
593 | { | |
594 | /* | |
595 | * Guests should see errata 400 and 415 as fixed (assuming that | |
596 | * HLT and IO instructions are intercepted). | |
597 | */ | |
598 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
599 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
600 | ||
601 | /* | |
602 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
603 | * all osvw.status bits inside that length, including bit 0 (which is | |
604 | * reserved for erratum 298), are valid. However, if host processor's | |
605 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
606 | * be conservative here and therefore we tell the guest that erratum 298 | |
607 | * is present (because we really don't know). | |
608 | */ | |
609 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
610 | vcpu->arch.osvw.status |= 1; | |
611 | } | |
612 | ||
6aa8b732 AK |
613 | static int has_svm(void) |
614 | { | |
63d1142f | 615 | const char *msg; |
6aa8b732 | 616 | |
63d1142f | 617 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 618 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
619 | return 0; |
620 | } | |
621 | ||
6aa8b732 AK |
622 | return 1; |
623 | } | |
624 | ||
625 | static void svm_hardware_disable(void *garbage) | |
626 | { | |
fbc0db76 JR |
627 | /* Make sure we clean up behind us */ |
628 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
629 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
630 | ||
2c8dceeb | 631 | cpu_svm_disable(); |
1018faa6 JR |
632 | |
633 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
634 | } |
635 | ||
10474ae8 | 636 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
637 | { |
638 | ||
0fe1e009 | 639 | struct svm_cpu_data *sd; |
6aa8b732 | 640 | uint64_t efer; |
89a27f4d | 641 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
642 | struct desc_struct *gdt; |
643 | int me = raw_smp_processor_id(); | |
644 | ||
10474ae8 AG |
645 | rdmsrl(MSR_EFER, efer); |
646 | if (efer & EFER_SVME) | |
647 | return -EBUSY; | |
648 | ||
6aa8b732 | 649 | if (!has_svm()) { |
1f5b77f5 | 650 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 651 | return -EINVAL; |
6aa8b732 | 652 | } |
0fe1e009 | 653 | sd = per_cpu(svm_data, me); |
0fe1e009 | 654 | if (!sd) { |
1f5b77f5 | 655 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 656 | return -EINVAL; |
6aa8b732 AK |
657 | } |
658 | ||
0fe1e009 TH |
659 | sd->asid_generation = 1; |
660 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
661 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 662 | |
d6ab1ed4 | 663 | native_store_gdt(&gdt_descr); |
89a27f4d | 664 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 665 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 666 | |
9962d032 | 667 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 668 | |
d0316554 | 669 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 670 | |
fbc0db76 JR |
671 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
672 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
673 | __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT; | |
674 | } | |
675 | ||
2b036c6b BO |
676 | |
677 | /* | |
678 | * Get OSVW bits. | |
679 | * | |
680 | * Note that it is possible to have a system with mixed processor | |
681 | * revisions and therefore different OSVW bits. If bits are not the same | |
682 | * on different processors then choose the worst case (i.e. if erratum | |
683 | * is present on one processor and not on another then assume that the | |
684 | * erratum is present everywhere). | |
685 | */ | |
686 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
687 | uint64_t len, status = 0; | |
688 | int err; | |
689 | ||
690 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
691 | if (!err) | |
692 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
693 | &err); | |
694 | ||
695 | if (err) | |
696 | osvw_status = osvw_len = 0; | |
697 | else { | |
698 | if (len < osvw_len) | |
699 | osvw_len = len; | |
700 | osvw_status |= status; | |
701 | osvw_status &= (1ULL << osvw_len) - 1; | |
702 | } | |
703 | } else | |
704 | osvw_status = osvw_len = 0; | |
705 | ||
67ec6607 JR |
706 | svm_init_erratum_383(); |
707 | ||
1018faa6 JR |
708 | amd_pmu_enable_virt(); |
709 | ||
10474ae8 | 710 | return 0; |
6aa8b732 AK |
711 | } |
712 | ||
0da1db75 JR |
713 | static void svm_cpu_uninit(int cpu) |
714 | { | |
0fe1e009 | 715 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 716 | |
0fe1e009 | 717 | if (!sd) |
0da1db75 JR |
718 | return; |
719 | ||
720 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
721 | __free_page(sd->save_area); |
722 | kfree(sd); | |
0da1db75 JR |
723 | } |
724 | ||
6aa8b732 AK |
725 | static int svm_cpu_init(int cpu) |
726 | { | |
0fe1e009 | 727 | struct svm_cpu_data *sd; |
6aa8b732 AK |
728 | int r; |
729 | ||
0fe1e009 TH |
730 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
731 | if (!sd) | |
6aa8b732 | 732 | return -ENOMEM; |
0fe1e009 TH |
733 | sd->cpu = cpu; |
734 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 735 | r = -ENOMEM; |
0fe1e009 | 736 | if (!sd->save_area) |
6aa8b732 AK |
737 | goto err_1; |
738 | ||
0fe1e009 | 739 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
740 | |
741 | return 0; | |
742 | ||
743 | err_1: | |
0fe1e009 | 744 | kfree(sd); |
6aa8b732 AK |
745 | return r; |
746 | ||
747 | } | |
748 | ||
ac72a9b7 JR |
749 | static bool valid_msr_intercept(u32 index) |
750 | { | |
751 | int i; | |
752 | ||
753 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
754 | if (direct_access_msrs[i].index == index) | |
755 | return true; | |
756 | ||
757 | return false; | |
758 | } | |
759 | ||
bfc733a7 RR |
760 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
761 | int read, int write) | |
6aa8b732 | 762 | { |
455716fa JR |
763 | u8 bit_read, bit_write; |
764 | unsigned long tmp; | |
765 | u32 offset; | |
6aa8b732 | 766 | |
ac72a9b7 JR |
767 | /* |
768 | * If this warning triggers extend the direct_access_msrs list at the | |
769 | * beginning of the file | |
770 | */ | |
771 | WARN_ON(!valid_msr_intercept(msr)); | |
772 | ||
455716fa JR |
773 | offset = svm_msrpm_offset(msr); |
774 | bit_read = 2 * (msr & 0x0f); | |
775 | bit_write = 2 * (msr & 0x0f) + 1; | |
776 | tmp = msrpm[offset]; | |
777 | ||
778 | BUG_ON(offset == MSR_INVALID); | |
779 | ||
780 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
781 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
782 | ||
783 | msrpm[offset] = tmp; | |
6aa8b732 AK |
784 | } |
785 | ||
f65c229c | 786 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
787 | { |
788 | int i; | |
789 | ||
f65c229c JR |
790 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
791 | ||
ac72a9b7 JR |
792 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
793 | if (!direct_access_msrs[i].always) | |
794 | continue; | |
795 | ||
796 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
797 | } | |
f65c229c JR |
798 | } |
799 | ||
323c3d80 JR |
800 | static void add_msr_offset(u32 offset) |
801 | { | |
802 | int i; | |
803 | ||
804 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
805 | ||
806 | /* Offset already in list? */ | |
807 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 808 | return; |
323c3d80 JR |
809 | |
810 | /* Slot used by another offset? */ | |
811 | if (msrpm_offsets[i] != MSR_INVALID) | |
812 | continue; | |
813 | ||
814 | /* Add offset to list */ | |
815 | msrpm_offsets[i] = offset; | |
816 | ||
817 | return; | |
6aa8b732 | 818 | } |
323c3d80 JR |
819 | |
820 | /* | |
821 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
822 | * increase MSRPM_OFFSETS in this case. | |
823 | */ | |
bfc733a7 | 824 | BUG(); |
6aa8b732 AK |
825 | } |
826 | ||
323c3d80 | 827 | static void init_msrpm_offsets(void) |
f65c229c | 828 | { |
323c3d80 | 829 | int i; |
f65c229c | 830 | |
323c3d80 JR |
831 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
832 | ||
833 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
834 | u32 offset; | |
835 | ||
836 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
837 | BUG_ON(offset == MSR_INVALID); | |
838 | ||
839 | add_msr_offset(offset); | |
840 | } | |
f65c229c JR |
841 | } |
842 | ||
24e09cbf JR |
843 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
844 | { | |
845 | u32 *msrpm = svm->msrpm; | |
846 | ||
847 | svm->vmcb->control.lbr_ctl = 1; | |
848 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
849 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
850 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
851 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
852 | } | |
853 | ||
854 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
855 | { | |
856 | u32 *msrpm = svm->msrpm; | |
857 | ||
858 | svm->vmcb->control.lbr_ctl = 0; | |
859 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
860 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
861 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
862 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
863 | } | |
864 | ||
6aa8b732 AK |
865 | static __init int svm_hardware_setup(void) |
866 | { | |
867 | int cpu; | |
868 | struct page *iopm_pages; | |
f65c229c | 869 | void *iopm_va; |
6aa8b732 AK |
870 | int r; |
871 | ||
6aa8b732 AK |
872 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
873 | ||
874 | if (!iopm_pages) | |
875 | return -ENOMEM; | |
c8681339 AL |
876 | |
877 | iopm_va = page_address(iopm_pages); | |
878 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
879 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
880 | ||
323c3d80 JR |
881 | init_msrpm_offsets(); |
882 | ||
50a37eb4 JR |
883 | if (boot_cpu_has(X86_FEATURE_NX)) |
884 | kvm_enable_efer_bits(EFER_NX); | |
885 | ||
1b2fd70c AG |
886 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
887 | kvm_enable_efer_bits(EFER_FFXSR); | |
888 | ||
92a1f12d JR |
889 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
890 | u64 max; | |
891 | ||
892 | kvm_has_tsc_control = true; | |
893 | ||
894 | /* | |
895 | * Make sure the user can only configure tsc_khz values that | |
896 | * fit into a signed integer. | |
897 | * A min value is not calculated needed because it will always | |
898 | * be 1 on all machines and a value of 0 is used to disable | |
899 | * tsc-scaling for the vcpu. | |
900 | */ | |
901 | max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX)); | |
902 | ||
903 | kvm_max_guest_tsc_khz = max; | |
904 | } | |
905 | ||
236de055 AG |
906 | if (nested) { |
907 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 908 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
909 | } |
910 | ||
3230bb47 | 911 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
912 | r = svm_cpu_init(cpu); |
913 | if (r) | |
f65c229c | 914 | goto err; |
6aa8b732 | 915 | } |
33bd6a0b | 916 | |
2a6b20b8 | 917 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
918 | npt_enabled = false; |
919 | ||
6c7dac72 JR |
920 | if (npt_enabled && !npt) { |
921 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
922 | npt_enabled = false; | |
923 | } | |
924 | ||
18552672 | 925 | if (npt_enabled) { |
e3da3acd | 926 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 927 | kvm_enable_tdp(); |
5f4cb662 JR |
928 | } else |
929 | kvm_disable_tdp(); | |
e3da3acd | 930 | |
6aa8b732 AK |
931 | return 0; |
932 | ||
f65c229c | 933 | err: |
6aa8b732 AK |
934 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
935 | iopm_base = 0; | |
936 | return r; | |
937 | } | |
938 | ||
939 | static __exit void svm_hardware_unsetup(void) | |
940 | { | |
0da1db75 JR |
941 | int cpu; |
942 | ||
3230bb47 | 943 | for_each_possible_cpu(cpu) |
0da1db75 JR |
944 | svm_cpu_uninit(cpu); |
945 | ||
6aa8b732 | 946 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 947 | iopm_base = 0; |
6aa8b732 AK |
948 | } |
949 | ||
950 | static void init_seg(struct vmcb_seg *seg) | |
951 | { | |
952 | seg->selector = 0; | |
953 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 954 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
955 | seg->limit = 0xffff; |
956 | seg->base = 0; | |
957 | } | |
958 | ||
959 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
960 | { | |
961 | seg->selector = 0; | |
962 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
963 | seg->limit = 0xffff; | |
964 | seg->base = 0; | |
965 | } | |
966 | ||
fbc0db76 JR |
967 | static u64 __scale_tsc(u64 ratio, u64 tsc) |
968 | { | |
969 | u64 mult, frac, _tsc; | |
970 | ||
971 | mult = ratio >> 32; | |
972 | frac = ratio & ((1ULL << 32) - 1); | |
973 | ||
974 | _tsc = tsc; | |
975 | _tsc *= mult; | |
976 | _tsc += (tsc >> 32) * frac; | |
977 | _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32; | |
978 | ||
979 | return _tsc; | |
980 | } | |
981 | ||
982 | static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
983 | { | |
984 | struct vcpu_svm *svm = to_svm(vcpu); | |
985 | u64 _tsc = tsc; | |
986 | ||
987 | if (svm->tsc_ratio != TSC_RATIO_DEFAULT) | |
988 | _tsc = __scale_tsc(svm->tsc_ratio, tsc); | |
989 | ||
990 | return _tsc; | |
991 | } | |
992 | ||
cc578287 | 993 | static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
4051b188 JR |
994 | { |
995 | struct vcpu_svm *svm = to_svm(vcpu); | |
996 | u64 ratio; | |
997 | u64 khz; | |
998 | ||
cc578287 ZA |
999 | /* Guest TSC same frequency as host TSC? */ |
1000 | if (!scale) { | |
1001 | svm->tsc_ratio = TSC_RATIO_DEFAULT; | |
4051b188 | 1002 | return; |
cc578287 | 1003 | } |
4051b188 | 1004 | |
cc578287 ZA |
1005 | /* TSC scaling supported? */ |
1006 | if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { | |
1007 | if (user_tsc_khz > tsc_khz) { | |
1008 | vcpu->arch.tsc_catchup = 1; | |
1009 | vcpu->arch.tsc_always_catchup = 1; | |
1010 | } else | |
1011 | WARN(1, "user requested TSC rate below hardware speed\n"); | |
4051b188 JR |
1012 | return; |
1013 | } | |
1014 | ||
1015 | khz = user_tsc_khz; | |
1016 | ||
1017 | /* TSC scaling required - calculate ratio */ | |
1018 | ratio = khz << 32; | |
1019 | do_div(ratio, tsc_khz); | |
1020 | ||
1021 | if (ratio == 0 || ratio & TSC_RATIO_RSVD) { | |
1022 | WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n", | |
1023 | user_tsc_khz); | |
1024 | return; | |
1025 | } | |
4051b188 JR |
1026 | svm->tsc_ratio = ratio; |
1027 | } | |
1028 | ||
ba904635 WA |
1029 | static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu) |
1030 | { | |
1031 | struct vcpu_svm *svm = to_svm(vcpu); | |
1032 | ||
1033 | return svm->vmcb->control.tsc_offset; | |
1034 | } | |
1035 | ||
f4e1b3c8 ZA |
1036 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1037 | { | |
1038 | struct vcpu_svm *svm = to_svm(vcpu); | |
1039 | u64 g_tsc_offset = 0; | |
1040 | ||
2030753d | 1041 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
1042 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1043 | svm->nested.hsave->control.tsc_offset; | |
1044 | svm->nested.hsave->control.tsc_offset = offset; | |
489223ed YY |
1045 | } else |
1046 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1047 | svm->vmcb->control.tsc_offset, | |
1048 | offset); | |
f4e1b3c8 ZA |
1049 | |
1050 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1051 | |
1052 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
1053 | } |
1054 | ||
f1e2b260 | 1055 | static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host) |
e48672fa ZA |
1056 | { |
1057 | struct vcpu_svm *svm = to_svm(vcpu); | |
1058 | ||
f1e2b260 MT |
1059 | WARN_ON(adjustment < 0); |
1060 | if (host) | |
1061 | adjustment = svm_scale_tsc(vcpu, adjustment); | |
1062 | ||
e48672fa | 1063 | svm->vmcb->control.tsc_offset += adjustment; |
2030753d | 1064 | if (is_guest_mode(vcpu)) |
e48672fa | 1065 | svm->nested.hsave->control.tsc_offset += adjustment; |
489223ed YY |
1066 | else |
1067 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1068 | svm->vmcb->control.tsc_offset - adjustment, | |
1069 | svm->vmcb->control.tsc_offset); | |
1070 | ||
116a0a23 | 1071 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
e48672fa ZA |
1072 | } |
1073 | ||
857e4099 JR |
1074 | static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1075 | { | |
1076 | u64 tsc; | |
1077 | ||
1078 | tsc = svm_scale_tsc(vcpu, native_read_tsc()); | |
1079 | ||
1080 | return target_tsc - tsc; | |
1081 | } | |
1082 | ||
e6101a96 | 1083 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1084 | { |
e6101a96 JR |
1085 | struct vmcb_control_area *control = &svm->vmcb->control; |
1086 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1087 | |
bff78274 | 1088 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 1089 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1090 | |
4ee546b4 RJ |
1091 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1092 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1093 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1094 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1095 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1096 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
1097 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1098 | |
5315c716 | 1099 | set_dr_intercepts(svm); |
6aa8b732 | 1100 | |
18c918c5 JR |
1101 | set_exception_intercept(svm, PF_VECTOR); |
1102 | set_exception_intercept(svm, UD_VECTOR); | |
1103 | set_exception_intercept(svm, MC_VECTOR); | |
6aa8b732 | 1104 | |
8a05a1b8 JR |
1105 | set_intercept(svm, INTERCEPT_INTR); |
1106 | set_intercept(svm, INTERCEPT_NMI); | |
1107 | set_intercept(svm, INTERCEPT_SMI); | |
1108 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1109 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1110 | set_intercept(svm, INTERCEPT_CPUID); |
1111 | set_intercept(svm, INTERCEPT_INVD); | |
1112 | set_intercept(svm, INTERCEPT_HLT); | |
1113 | set_intercept(svm, INTERCEPT_INVLPG); | |
1114 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1115 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1116 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1117 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1118 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1119 | set_intercept(svm, INTERCEPT_VMRUN); | |
1120 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1121 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1122 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1123 | set_intercept(svm, INTERCEPT_STGI); | |
1124 | set_intercept(svm, INTERCEPT_CLGI); | |
1125 | set_intercept(svm, INTERCEPT_SKINIT); | |
1126 | set_intercept(svm, INTERCEPT_WBINVD); | |
1127 | set_intercept(svm, INTERCEPT_MONITOR); | |
1128 | set_intercept(svm, INTERCEPT_MWAIT); | |
81dd35d4 | 1129 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 AK |
1130 | |
1131 | control->iopm_base_pa = iopm_base; | |
f65c229c | 1132 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
1133 | control->int_ctl = V_INTR_MASKING_MASK; |
1134 | ||
1135 | init_seg(&save->es); | |
1136 | init_seg(&save->ss); | |
1137 | init_seg(&save->ds); | |
1138 | init_seg(&save->fs); | |
1139 | init_seg(&save->gs); | |
1140 | ||
1141 | save->cs.selector = 0xf000; | |
04b66839 | 1142 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1143 | /* Executable/Readable Code Segment */ |
1144 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1145 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1146 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1147 | |
1148 | save->gdtr.limit = 0xffff; | |
1149 | save->idtr.limit = 0xffff; | |
1150 | ||
1151 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1152 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1153 | ||
eaa48512 | 1154 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1155 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1156 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1157 | save->rip = 0x0000fff0; |
5fdbf976 | 1158 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1159 | |
e0231715 JR |
1160 | /* |
1161 | * This is the guest-visible cr0 value. | |
18fa000a | 1162 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 1163 | */ |
678041ad MT |
1164 | svm->vcpu.arch.cr0 = 0; |
1165 | (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); | |
18fa000a | 1166 | |
66aee91a | 1167 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1168 | /* rdx = ?? */ |
709ddebf JR |
1169 | |
1170 | if (npt_enabled) { | |
1171 | /* Setup VMCB for Nested Paging */ | |
1172 | control->nested_ctl = 1; | |
8a05a1b8 | 1173 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1174 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1175 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1176 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
709ddebf | 1177 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
1178 | save->cr3 = 0; |
1179 | save->cr4 = 0; | |
1180 | } | |
f40f6a45 | 1181 | svm->asid_generation = 0; |
1371d904 | 1182 | |
e6aa9abd | 1183 | svm->nested.vmcb = 0; |
2af9194d JR |
1184 | svm->vcpu.arch.hflags = 0; |
1185 | ||
2a6b20b8 | 1186 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1187 | control->pause_filter_count = 3000; |
8a05a1b8 | 1188 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1189 | } |
1190 | ||
8d28fec4 RJ |
1191 | mark_all_dirty(svm->vmcb); |
1192 | ||
2af9194d | 1193 | enable_gif(svm); |
6aa8b732 AK |
1194 | } |
1195 | ||
57f252f2 | 1196 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
1197 | { |
1198 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
1199 | u32 dummy; |
1200 | u32 eax = 1; | |
04d2cc77 | 1201 | |
e6101a96 | 1202 | init_vmcb(svm); |
70433389 | 1203 | |
66f7b72e JS |
1204 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy); |
1205 | kvm_register_write(vcpu, VCPU_REGS_RDX, eax); | |
04d2cc77 AK |
1206 | } |
1207 | ||
fb3f0f51 | 1208 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1209 | { |
a2fa3e9f | 1210 | struct vcpu_svm *svm; |
6aa8b732 | 1211 | struct page *page; |
f65c229c | 1212 | struct page *msrpm_pages; |
b286d5d8 | 1213 | struct page *hsave_page; |
3d6368ef | 1214 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1215 | int err; |
6aa8b732 | 1216 | |
c16f862d | 1217 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1218 | if (!svm) { |
1219 | err = -ENOMEM; | |
1220 | goto out; | |
1221 | } | |
1222 | ||
fbc0db76 JR |
1223 | svm->tsc_ratio = TSC_RATIO_DEFAULT; |
1224 | ||
fb3f0f51 RR |
1225 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); |
1226 | if (err) | |
1227 | goto free_svm; | |
1228 | ||
b7af4043 | 1229 | err = -ENOMEM; |
6aa8b732 | 1230 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1231 | if (!page) |
fb3f0f51 | 1232 | goto uninit; |
6aa8b732 | 1233 | |
f65c229c JR |
1234 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1235 | if (!msrpm_pages) | |
b7af4043 | 1236 | goto free_page1; |
3d6368ef AG |
1237 | |
1238 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1239 | if (!nested_msrpm_pages) | |
b7af4043 | 1240 | goto free_page2; |
f65c229c | 1241 | |
b286d5d8 AG |
1242 | hsave_page = alloc_page(GFP_KERNEL); |
1243 | if (!hsave_page) | |
b7af4043 TY |
1244 | goto free_page3; |
1245 | ||
e6aa9abd | 1246 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1247 | |
b7af4043 TY |
1248 | svm->msrpm = page_address(msrpm_pages); |
1249 | svm_vcpu_init_msrpm(svm->msrpm); | |
1250 | ||
e6aa9abd | 1251 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1252 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1253 | |
a2fa3e9f GH |
1254 | svm->vmcb = page_address(page); |
1255 | clear_page(svm->vmcb); | |
1256 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1257 | svm->asid_generation = 0; | |
e6101a96 | 1258 | init_vmcb(svm); |
a2fa3e9f | 1259 | |
ad312c7c | 1260 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 1261 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 1262 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 1263 | |
2b036c6b BO |
1264 | svm_init_osvw(&svm->vcpu); |
1265 | ||
fb3f0f51 | 1266 | return &svm->vcpu; |
36241b8c | 1267 | |
b7af4043 TY |
1268 | free_page3: |
1269 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1270 | free_page2: | |
1271 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1272 | free_page1: | |
1273 | __free_page(page); | |
fb3f0f51 RR |
1274 | uninit: |
1275 | kvm_vcpu_uninit(&svm->vcpu); | |
1276 | free_svm: | |
a4770347 | 1277 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1278 | out: |
1279 | return ERR_PTR(err); | |
6aa8b732 AK |
1280 | } |
1281 | ||
1282 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1283 | { | |
a2fa3e9f GH |
1284 | struct vcpu_svm *svm = to_svm(vcpu); |
1285 | ||
fb3f0f51 | 1286 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1287 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1288 | __free_page(virt_to_page(svm->nested.hsave)); |
1289 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1290 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1291 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1292 | } |
1293 | ||
15ad7146 | 1294 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1295 | { |
a2fa3e9f | 1296 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1297 | int i; |
0cc5064d | 1298 | |
0cc5064d | 1299 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1300 | svm->asid_generation = 0; |
8d28fec4 | 1301 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1302 | } |
94dfbdb3 | 1303 | |
82ca2d10 AK |
1304 | #ifdef CONFIG_X86_64 |
1305 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1306 | #endif | |
dacccfdd AK |
1307 | savesegment(fs, svm->host.fs); |
1308 | savesegment(gs, svm->host.gs); | |
1309 | svm->host.ldt = kvm_read_ldt(); | |
1310 | ||
94dfbdb3 | 1311 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1312 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 JR |
1313 | |
1314 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR) && | |
1315 | svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) { | |
1316 | __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio; | |
1317 | wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio); | |
1318 | } | |
6aa8b732 AK |
1319 | } |
1320 | ||
1321 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1322 | { | |
a2fa3e9f | 1323 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1324 | int i; |
1325 | ||
e1beb1d3 | 1326 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1327 | kvm_load_ldt(svm->host.ldt); |
1328 | #ifdef CONFIG_X86_64 | |
1329 | loadsegment(fs, svm->host.fs); | |
dacccfdd | 1330 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); |
893a5ab6 | 1331 | load_gs_index(svm->host.gs); |
dacccfdd | 1332 | #else |
831ca609 | 1333 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1334 | loadsegment(gs, svm->host.gs); |
831ca609 | 1335 | #endif |
dacccfdd | 1336 | #endif |
94dfbdb3 | 1337 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1338 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1339 | } |
1340 | ||
6aa8b732 AK |
1341 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1342 | { | |
a2fa3e9f | 1343 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1344 | } |
1345 | ||
1346 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1347 | { | |
ae9fedc7 PB |
1348 | /* |
1349 | * Any change of EFLAGS.VM is accompained by a reload of SS | |
1350 | * (caused by either a task switch or an inter-privilege IRET), | |
1351 | * so we do not need to update the CPL here. | |
1352 | */ | |
a2fa3e9f | 1353 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1354 | } |
1355 | ||
6de4f3ad AK |
1356 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1357 | { | |
1358 | switch (reg) { | |
1359 | case VCPU_EXREG_PDPTR: | |
1360 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1361 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1362 | break; |
1363 | default: | |
1364 | BUG(); | |
1365 | } | |
1366 | } | |
1367 | ||
f0b85051 AG |
1368 | static void svm_set_vintr(struct vcpu_svm *svm) |
1369 | { | |
8a05a1b8 | 1370 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1371 | } |
1372 | ||
1373 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1374 | { | |
8a05a1b8 | 1375 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1376 | } |
1377 | ||
6aa8b732 AK |
1378 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1379 | { | |
a2fa3e9f | 1380 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1381 | |
1382 | switch (seg) { | |
1383 | case VCPU_SREG_CS: return &save->cs; | |
1384 | case VCPU_SREG_DS: return &save->ds; | |
1385 | case VCPU_SREG_ES: return &save->es; | |
1386 | case VCPU_SREG_FS: return &save->fs; | |
1387 | case VCPU_SREG_GS: return &save->gs; | |
1388 | case VCPU_SREG_SS: return &save->ss; | |
1389 | case VCPU_SREG_TR: return &save->tr; | |
1390 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1391 | } | |
1392 | BUG(); | |
8b6d44c7 | 1393 | return NULL; |
6aa8b732 AK |
1394 | } |
1395 | ||
1396 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1397 | { | |
1398 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1399 | ||
1400 | return s->base; | |
1401 | } | |
1402 | ||
1403 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1404 | struct kvm_segment *var, int seg) | |
1405 | { | |
1406 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1407 | ||
1408 | var->base = s->base; | |
1409 | var->limit = s->limit; | |
1410 | var->selector = s->selector; | |
1411 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1412 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1413 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1414 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1415 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1416 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1417 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1418 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1419 | |
e0231715 JR |
1420 | /* |
1421 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1422 | * for cross vendor migration purposes by "not present" |
1423 | */ | |
1424 | var->unusable = !var->present || (var->type == 0); | |
1425 | ||
1fbdc7a5 AP |
1426 | switch (seg) { |
1427 | case VCPU_SREG_CS: | |
1428 | /* | |
1429 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1430 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1431 | * Intel's VMENTRY has a check on the 'G' bit. | |
1432 | */ | |
25022acc | 1433 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1434 | break; |
1435 | case VCPU_SREG_TR: | |
1436 | /* | |
1437 | * Work around a bug where the busy flag in the tr selector | |
1438 | * isn't exposed | |
1439 | */ | |
c0d09828 | 1440 | var->type |= 0x2; |
1fbdc7a5 AP |
1441 | break; |
1442 | case VCPU_SREG_DS: | |
1443 | case VCPU_SREG_ES: | |
1444 | case VCPU_SREG_FS: | |
1445 | case VCPU_SREG_GS: | |
1446 | /* | |
1447 | * The accessed bit must always be set in the segment | |
1448 | * descriptor cache, although it can be cleared in the | |
1449 | * descriptor, the cached bit always remains at 1. Since | |
1450 | * Intel has a check on this, set it here to support | |
1451 | * cross-vendor migration. | |
1452 | */ | |
1453 | if (!var->unusable) | |
1454 | var->type |= 0x1; | |
1455 | break; | |
b586eb02 | 1456 | case VCPU_SREG_SS: |
e0231715 JR |
1457 | /* |
1458 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1459 | * descriptor is left as 1, although the whole segment has |
1460 | * been made unusable. Clear it here to pass an Intel VMX | |
1461 | * entry check when cross vendor migrating. | |
1462 | */ | |
1463 | if (var->unusable) | |
1464 | var->db = 0; | |
33b458d2 | 1465 | var->dpl = to_svm(vcpu)->vmcb->save.cpl; |
b586eb02 | 1466 | break; |
1fbdc7a5 | 1467 | } |
6aa8b732 AK |
1468 | } |
1469 | ||
2e4d2653 IE |
1470 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1471 | { | |
1472 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1473 | ||
1474 | return save->cpl; | |
1475 | } | |
1476 | ||
89a27f4d | 1477 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1478 | { |
a2fa3e9f GH |
1479 | struct vcpu_svm *svm = to_svm(vcpu); |
1480 | ||
89a27f4d GN |
1481 | dt->size = svm->vmcb->save.idtr.limit; |
1482 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1483 | } |
1484 | ||
89a27f4d | 1485 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1486 | { |
a2fa3e9f GH |
1487 | struct vcpu_svm *svm = to_svm(vcpu); |
1488 | ||
89a27f4d GN |
1489 | svm->vmcb->save.idtr.limit = dt->size; |
1490 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1491 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1492 | } |
1493 | ||
89a27f4d | 1494 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1495 | { |
a2fa3e9f GH |
1496 | struct vcpu_svm *svm = to_svm(vcpu); |
1497 | ||
89a27f4d GN |
1498 | dt->size = svm->vmcb->save.gdtr.limit; |
1499 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1500 | } |
1501 | ||
89a27f4d | 1502 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1503 | { |
a2fa3e9f GH |
1504 | struct vcpu_svm *svm = to_svm(vcpu); |
1505 | ||
89a27f4d GN |
1506 | svm->vmcb->save.gdtr.limit = dt->size; |
1507 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1508 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1509 | } |
1510 | ||
e8467fda AK |
1511 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1512 | { | |
1513 | } | |
1514 | ||
aff48baa AK |
1515 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1516 | { | |
1517 | } | |
1518 | ||
25c4c276 | 1519 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1520 | { |
1521 | } | |
1522 | ||
d225157b AK |
1523 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1524 | { | |
1525 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1526 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1527 | ||
1528 | if (!svm->vcpu.fpu_active) | |
1529 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1530 | else | |
1531 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1532 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1533 | ||
dcca1a65 | 1534 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b AK |
1535 | |
1536 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1537 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1538 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1539 | } else { |
4ee546b4 RJ |
1540 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1541 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1542 | } |
1543 | } | |
1544 | ||
6aa8b732 AK |
1545 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1546 | { | |
a2fa3e9f GH |
1547 | struct vcpu_svm *svm = to_svm(vcpu); |
1548 | ||
05b3e0c2 | 1549 | #ifdef CONFIG_X86_64 |
f6801dff | 1550 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1551 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1552 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1553 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1554 | } |
1555 | ||
d77c26fc | 1556 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1557 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1558 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1559 | } |
1560 | } | |
1561 | #endif | |
ad312c7c | 1562 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1563 | |
1564 | if (!npt_enabled) | |
1565 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1566 | |
1567 | if (!vcpu->fpu_active) | |
334df50a | 1568 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1569 | /* |
1570 | * re-enable caching here because the QEMU bios | |
1571 | * does not do it - this results in some delay at | |
1572 | * reboot | |
1573 | */ | |
1574 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1575 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1576 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1577 | update_cr0_intercept(svm); |
6aa8b732 AK |
1578 | } |
1579 | ||
5e1746d6 | 1580 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 1581 | { |
6394b649 | 1582 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1583 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1584 | ||
5e1746d6 NHE |
1585 | if (cr4 & X86_CR4_VMXE) |
1586 | return 1; | |
1587 | ||
e5eab0ce | 1588 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 1589 | svm_flush_tlb(vcpu); |
6394b649 | 1590 | |
ec077263 JR |
1591 | vcpu->arch.cr4 = cr4; |
1592 | if (!npt_enabled) | |
1593 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1594 | cr4 |= host_cr4_mce; |
ec077263 | 1595 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1596 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 1597 | return 0; |
6aa8b732 AK |
1598 | } |
1599 | ||
1600 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1601 | struct kvm_segment *var, int seg) | |
1602 | { | |
a2fa3e9f | 1603 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1604 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1605 | ||
1606 | s->base = var->base; | |
1607 | s->limit = var->limit; | |
1608 | s->selector = var->selector; | |
1609 | if (var->unusable) | |
1610 | s->attrib = 0; | |
1611 | else { | |
1612 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1613 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1614 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1615 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1616 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1617 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1618 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1619 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1620 | } | |
ae9fedc7 PB |
1621 | |
1622 | /* | |
1623 | * This is always accurate, except if SYSRET returned to a segment | |
1624 | * with SS.DPL != 3. Intel does not have this quirk, and always | |
1625 | * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it | |
1626 | * would entail passing the CPL to userspace and back. | |
1627 | */ | |
1628 | if (seg == VCPU_SREG_SS) | |
1629 | svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
6aa8b732 | 1630 | |
060d0c9a | 1631 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
1632 | } |
1633 | ||
c8639010 | 1634 | static void update_db_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1635 | { |
d0bfb940 JK |
1636 | struct vcpu_svm *svm = to_svm(vcpu); |
1637 | ||
18c918c5 JR |
1638 | clr_exception_intercept(svm, DB_VECTOR); |
1639 | clr_exception_intercept(svm, BP_VECTOR); | |
44c11430 | 1640 | |
6be7d306 | 1641 | if (svm->nmi_singlestep) |
18c918c5 | 1642 | set_exception_intercept(svm, DB_VECTOR); |
44c11430 | 1643 | |
d0bfb940 JK |
1644 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1645 | if (vcpu->guest_debug & | |
1646 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
18c918c5 | 1647 | set_exception_intercept(svm, DB_VECTOR); |
d0bfb940 | 1648 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1649 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1650 | } else |
1651 | vcpu->guest_debug = 0; | |
44c11430 GN |
1652 | } |
1653 | ||
0fe1e009 | 1654 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1655 | { |
0fe1e009 TH |
1656 | if (sd->next_asid > sd->max_asid) { |
1657 | ++sd->asid_generation; | |
1658 | sd->next_asid = 1; | |
a2fa3e9f | 1659 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1660 | } |
1661 | ||
0fe1e009 TH |
1662 | svm->asid_generation = sd->asid_generation; |
1663 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
1664 | |
1665 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
1666 | } |
1667 | ||
73aaf249 JK |
1668 | static u64 svm_get_dr6(struct kvm_vcpu *vcpu) |
1669 | { | |
1670 | return to_svm(vcpu)->vmcb->save.dr6; | |
1671 | } | |
1672 | ||
1673 | static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value) | |
1674 | { | |
1675 | struct vcpu_svm *svm = to_svm(vcpu); | |
1676 | ||
1677 | svm->vmcb->save.dr6 = value; | |
1678 | mark_dirty(svm->vmcb, VMCB_DR); | |
1679 | } | |
1680 | ||
facb0139 PB |
1681 | static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
1682 | { | |
1683 | struct vcpu_svm *svm = to_svm(vcpu); | |
1684 | ||
1685 | get_debugreg(vcpu->arch.db[0], 0); | |
1686 | get_debugreg(vcpu->arch.db[1], 1); | |
1687 | get_debugreg(vcpu->arch.db[2], 2); | |
1688 | get_debugreg(vcpu->arch.db[3], 3); | |
1689 | vcpu->arch.dr6 = svm_get_dr6(vcpu); | |
1690 | vcpu->arch.dr7 = svm->vmcb->save.dr7; | |
1691 | ||
1692 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
1693 | set_dr_intercepts(svm); | |
1694 | } | |
1695 | ||
020df079 | 1696 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1697 | { |
42dbaa5a | 1698 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1699 | |
020df079 | 1700 | svm->vmcb->save.dr7 = value; |
72214b96 | 1701 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
1702 | } |
1703 | ||
851ba692 | 1704 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1705 | { |
631bc487 | 1706 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1707 | u32 error_code; |
631bc487 | 1708 | int r = 1; |
6aa8b732 | 1709 | |
631bc487 GN |
1710 | switch (svm->apf_reason) { |
1711 | default: | |
1712 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1713 | |
631bc487 GN |
1714 | trace_kvm_page_fault(fault_address, error_code); |
1715 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1716 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
1717 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
1718 | svm->vmcb->control.insn_bytes, | |
1719 | svm->vmcb->control.insn_len); | |
631bc487 GN |
1720 | break; |
1721 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1722 | svm->apf_reason = 0; | |
1723 | local_irq_disable(); | |
1724 | kvm_async_pf_task_wait(fault_address); | |
1725 | local_irq_enable(); | |
1726 | break; | |
1727 | case KVM_PV_REASON_PAGE_READY: | |
1728 | svm->apf_reason = 0; | |
1729 | local_irq_disable(); | |
1730 | kvm_async_pf_task_wake(fault_address); | |
1731 | local_irq_enable(); | |
1732 | break; | |
1733 | } | |
1734 | return r; | |
6aa8b732 AK |
1735 | } |
1736 | ||
851ba692 | 1737 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1738 | { |
851ba692 AK |
1739 | struct kvm_run *kvm_run = svm->vcpu.run; |
1740 | ||
d0bfb940 | 1741 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1742 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1743 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1744 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1745 | return 1; | |
1746 | } | |
44c11430 | 1747 | |
6be7d306 JK |
1748 | if (svm->nmi_singlestep) { |
1749 | svm->nmi_singlestep = false; | |
44c11430 GN |
1750 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1751 | svm->vmcb->save.rflags &= | |
1752 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
c8639010 | 1753 | update_db_bp_intercept(&svm->vcpu); |
44c11430 GN |
1754 | } |
1755 | ||
1756 | if (svm->vcpu.guest_debug & | |
e0231715 | 1757 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1758 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1759 | kvm_run->debug.arch.pc = | |
1760 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1761 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1762 | return 0; | |
1763 | } | |
1764 | ||
1765 | return 1; | |
d0bfb940 JK |
1766 | } |
1767 | ||
851ba692 | 1768 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1769 | { |
851ba692 AK |
1770 | struct kvm_run *kvm_run = svm->vcpu.run; |
1771 | ||
d0bfb940 JK |
1772 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1773 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1774 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1775 | return 0; | |
1776 | } | |
1777 | ||
851ba692 | 1778 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1779 | { |
1780 | int er; | |
1781 | ||
51d8b661 | 1782 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1783 | if (er != EMULATE_DONE) |
7ee5d940 | 1784 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1785 | return 1; |
1786 | } | |
1787 | ||
6b52d186 | 1788 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1789 | { |
6b52d186 | 1790 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1791 | |
18c918c5 | 1792 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1793 | |
e756fc62 | 1794 | svm->vcpu.fpu_active = 1; |
d225157b | 1795 | update_cr0_intercept(svm); |
6b52d186 | 1796 | } |
a2fa3e9f | 1797 | |
6b52d186 AK |
1798 | static int nm_interception(struct vcpu_svm *svm) |
1799 | { | |
1800 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1801 | return 1; |
7807fa6c AL |
1802 | } |
1803 | ||
67ec6607 JR |
1804 | static bool is_erratum_383(void) |
1805 | { | |
1806 | int err, i; | |
1807 | u64 value; | |
1808 | ||
1809 | if (!erratum_383_found) | |
1810 | return false; | |
1811 | ||
1812 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1813 | if (err) | |
1814 | return false; | |
1815 | ||
1816 | /* Bit 62 may or may not be set for this mce */ | |
1817 | value &= ~(1ULL << 62); | |
1818 | ||
1819 | if (value != 0xb600000000010015ULL) | |
1820 | return false; | |
1821 | ||
1822 | /* Clear MCi_STATUS registers */ | |
1823 | for (i = 0; i < 6; ++i) | |
1824 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1825 | ||
1826 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1827 | if (!err) { | |
1828 | u32 low, high; | |
1829 | ||
1830 | value &= ~(1ULL << 2); | |
1831 | low = lower_32_bits(value); | |
1832 | high = upper_32_bits(value); | |
1833 | ||
1834 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1835 | } | |
1836 | ||
1837 | /* Flush tlb to evict multi-match entries */ | |
1838 | __flush_tlb_all(); | |
1839 | ||
1840 | return true; | |
1841 | } | |
1842 | ||
fe5913e4 | 1843 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1844 | { |
67ec6607 JR |
1845 | if (is_erratum_383()) { |
1846 | /* | |
1847 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1848 | * guest. | |
1849 | */ | |
1850 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1851 | ||
a8eeb04a | 1852 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1853 | |
1854 | return; | |
1855 | } | |
1856 | ||
53371b50 JR |
1857 | /* |
1858 | * On an #MC intercept the MCE handler is not called automatically in | |
1859 | * the host. So do it by hand here. | |
1860 | */ | |
1861 | asm volatile ( | |
1862 | "int $0x12\n"); | |
1863 | /* not sure if we ever come back to this point */ | |
1864 | ||
fe5913e4 JR |
1865 | return; |
1866 | } | |
1867 | ||
1868 | static int mc_interception(struct vcpu_svm *svm) | |
1869 | { | |
53371b50 JR |
1870 | return 1; |
1871 | } | |
1872 | ||
851ba692 | 1873 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1874 | { |
851ba692 AK |
1875 | struct kvm_run *kvm_run = svm->vcpu.run; |
1876 | ||
46fe4ddd JR |
1877 | /* |
1878 | * VMCB is undefined after a SHUTDOWN intercept | |
1879 | * so reinitialize it. | |
1880 | */ | |
a2fa3e9f | 1881 | clear_page(svm->vmcb); |
e6101a96 | 1882 | init_vmcb(svm); |
46fe4ddd JR |
1883 | |
1884 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1885 | return 0; | |
1886 | } | |
1887 | ||
851ba692 | 1888 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1889 | { |
cf8f70bf | 1890 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1891 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1892 | int size, in, string; |
039576c0 | 1893 | unsigned port; |
6aa8b732 | 1894 | |
e756fc62 | 1895 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1896 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1897 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1898 | if (string || in) |
51d8b661 | 1899 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 1900 | |
039576c0 AK |
1901 | port = io_info >> 16; |
1902 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1903 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1904 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1905 | |
1906 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1907 | } |
1908 | ||
851ba692 | 1909 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1910 | { |
1911 | return 1; | |
1912 | } | |
1913 | ||
851ba692 | 1914 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1915 | { |
1916 | ++svm->vcpu.stat.irq_exits; | |
1917 | return 1; | |
1918 | } | |
1919 | ||
851ba692 | 1920 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1921 | { |
1922 | return 1; | |
1923 | } | |
1924 | ||
851ba692 | 1925 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1926 | { |
5fdbf976 | 1927 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1928 | skip_emulated_instruction(&svm->vcpu); |
1929 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1930 | } |
1931 | ||
851ba692 | 1932 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1933 | { |
5fdbf976 | 1934 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1935 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1936 | kvm_emulate_hypercall(&svm->vcpu); |
1937 | return 1; | |
02e235bc AK |
1938 | } |
1939 | ||
5bd2edc3 JR |
1940 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1941 | { | |
1942 | struct vcpu_svm *svm = to_svm(vcpu); | |
1943 | ||
1944 | return svm->nested.nested_cr3; | |
1945 | } | |
1946 | ||
e4e517b4 AK |
1947 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
1948 | { | |
1949 | struct vcpu_svm *svm = to_svm(vcpu); | |
1950 | u64 cr3 = svm->nested.nested_cr3; | |
1951 | u64 pdpte; | |
1952 | int ret; | |
1953 | ||
1954 | ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte, | |
1955 | offset_in_page(cr3) + index * 8, 8); | |
1956 | if (ret) | |
1957 | return 0; | |
1958 | return pdpte; | |
1959 | } | |
1960 | ||
5bd2edc3 JR |
1961 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
1962 | unsigned long root) | |
1963 | { | |
1964 | struct vcpu_svm *svm = to_svm(vcpu); | |
1965 | ||
1966 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 1967 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 1968 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
1969 | } |
1970 | ||
6389ee94 AK |
1971 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
1972 | struct x86_exception *fault) | |
5bd2edc3 JR |
1973 | { |
1974 | struct vcpu_svm *svm = to_svm(vcpu); | |
1975 | ||
1976 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1977 | svm->vmcb->control.exit_code_hi = 0; | |
6389ee94 AK |
1978 | svm->vmcb->control.exit_info_1 = fault->error_code; |
1979 | svm->vmcb->control.exit_info_2 = fault->address; | |
5bd2edc3 JR |
1980 | |
1981 | nested_svm_vmexit(svm); | |
1982 | } | |
1983 | ||
8a3c1a33 | 1984 | static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
4b16184c | 1985 | { |
8a3c1a33 | 1986 | kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); |
4b16184c JR |
1987 | |
1988 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; | |
1989 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 1990 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c JR |
1991 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
1992 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
1993 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
4b16184c JR |
1994 | } |
1995 | ||
1996 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1997 | { | |
1998 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1999 | } | |
2000 | ||
c0725420 AG |
2001 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
2002 | { | |
f6801dff | 2003 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
2004 | || !is_paging(&svm->vcpu)) { |
2005 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2006 | return 1; | |
2007 | } | |
2008 | ||
2009 | if (svm->vmcb->save.cpl) { | |
2010 | kvm_inject_gp(&svm->vcpu, 0); | |
2011 | return 1; | |
2012 | } | |
2013 | ||
2014 | return 0; | |
2015 | } | |
2016 | ||
cf74a78b AG |
2017 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
2018 | bool has_error_code, u32 error_code) | |
2019 | { | |
b8e88bc8 JR |
2020 | int vmexit; |
2021 | ||
2030753d | 2022 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 2023 | return 0; |
cf74a78b | 2024 | |
0295ad7d JR |
2025 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
2026 | svm->vmcb->control.exit_code_hi = 0; | |
2027 | svm->vmcb->control.exit_info_1 = error_code; | |
2028 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
2029 | ||
b8e88bc8 JR |
2030 | vmexit = nested_svm_intercept(svm); |
2031 | if (vmexit == NESTED_EXIT_DONE) | |
2032 | svm->nested.exit_required = true; | |
2033 | ||
2034 | return vmexit; | |
cf74a78b AG |
2035 | } |
2036 | ||
8fe54654 JR |
2037 | /* This function returns true if it is save to enable the irq window */ |
2038 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 2039 | { |
2030753d | 2040 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 2041 | return true; |
cf74a78b | 2042 | |
26666957 | 2043 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 2044 | return true; |
cf74a78b | 2045 | |
26666957 | 2046 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 2047 | return false; |
cf74a78b | 2048 | |
a0a07cd2 GN |
2049 | /* |
2050 | * if vmexit was already requested (by intercepted exception | |
2051 | * for instance) do not overwrite it with "external interrupt" | |
2052 | * vmexit. | |
2053 | */ | |
2054 | if (svm->nested.exit_required) | |
2055 | return false; | |
2056 | ||
197717d5 JR |
2057 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
2058 | svm->vmcb->control.exit_info_1 = 0; | |
2059 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 2060 | |
cd3ff653 JR |
2061 | if (svm->nested.intercept & 1ULL) { |
2062 | /* | |
2063 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 2064 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
2065 | * #vmexit emulation might sleep. Only signal request for |
2066 | * the #vmexit here. | |
2067 | */ | |
2068 | svm->nested.exit_required = true; | |
236649de | 2069 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2070 | return false; |
cf74a78b AG |
2071 | } |
2072 | ||
8fe54654 | 2073 | return true; |
cf74a78b AG |
2074 | } |
2075 | ||
887f500c JR |
2076 | /* This function returns true if it is save to enable the nmi window */ |
2077 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2078 | { | |
2030753d | 2079 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2080 | return true; |
2081 | ||
2082 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2083 | return true; | |
2084 | ||
2085 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2086 | svm->nested.exit_required = true; | |
2087 | ||
2088 | return false; | |
cf74a78b AG |
2089 | } |
2090 | ||
7597f129 | 2091 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2092 | { |
2093 | struct page *page; | |
2094 | ||
6c3bd3d7 JR |
2095 | might_sleep(); |
2096 | ||
34f80cfa | 2097 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2098 | if (is_error_page(page)) |
2099 | goto error; | |
2100 | ||
7597f129 JR |
2101 | *_page = page; |
2102 | ||
2103 | return kmap(page); | |
34f80cfa JR |
2104 | |
2105 | error: | |
34f80cfa JR |
2106 | kvm_inject_gp(&svm->vcpu, 0); |
2107 | ||
2108 | return NULL; | |
2109 | } | |
2110 | ||
7597f129 | 2111 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2112 | { |
7597f129 | 2113 | kunmap(page); |
34f80cfa JR |
2114 | kvm_release_page_dirty(page); |
2115 | } | |
34f80cfa | 2116 | |
ce2ac085 JR |
2117 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2118 | { | |
2119 | unsigned port; | |
2120 | u8 val, bit; | |
2121 | u64 gpa; | |
34f80cfa | 2122 | |
ce2ac085 JR |
2123 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2124 | return NESTED_EXIT_HOST; | |
34f80cfa | 2125 | |
ce2ac085 JR |
2126 | port = svm->vmcb->control.exit_info_1 >> 16; |
2127 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
2128 | bit = port % 8; | |
2129 | val = 0; | |
2130 | ||
2131 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
2132 | val &= (1 << bit); | |
2133 | ||
2134 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
2135 | } |
2136 | ||
d2477826 | 2137 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2138 | { |
0d6b3537 JR |
2139 | u32 offset, msr, value; |
2140 | int write, mask; | |
4c2161ae | 2141 | |
3d62d9aa | 2142 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2143 | return NESTED_EXIT_HOST; |
3d62d9aa | 2144 | |
0d6b3537 JR |
2145 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2146 | offset = svm_msrpm_offset(msr); | |
2147 | write = svm->vmcb->control.exit_info_1 & 1; | |
2148 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2149 | |
0d6b3537 JR |
2150 | if (offset == MSR_INVALID) |
2151 | return NESTED_EXIT_DONE; | |
4c2161ae | 2152 | |
0d6b3537 JR |
2153 | /* Offset is in 32 bit units but need in 8 bit units */ |
2154 | offset *= 4; | |
4c2161ae | 2155 | |
0d6b3537 JR |
2156 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
2157 | return NESTED_EXIT_DONE; | |
3d62d9aa | 2158 | |
0d6b3537 | 2159 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2160 | } |
2161 | ||
410e4d57 | 2162 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2163 | { |
cf74a78b | 2164 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2165 | |
410e4d57 JR |
2166 | switch (exit_code) { |
2167 | case SVM_EXIT_INTR: | |
2168 | case SVM_EXIT_NMI: | |
ff47a49b | 2169 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2170 | return NESTED_EXIT_HOST; |
410e4d57 | 2171 | case SVM_EXIT_NPF: |
e0231715 | 2172 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2173 | if (npt_enabled) |
2174 | return NESTED_EXIT_HOST; | |
2175 | break; | |
410e4d57 | 2176 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
2177 | /* When we're shadowing, trap PFs, but not async PF */ |
2178 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
2179 | return NESTED_EXIT_HOST; |
2180 | break; | |
66a562f7 JR |
2181 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
2182 | nm_interception(svm); | |
2183 | break; | |
410e4d57 JR |
2184 | default: |
2185 | break; | |
cf74a78b AG |
2186 | } |
2187 | ||
410e4d57 JR |
2188 | return NESTED_EXIT_CONTINUE; |
2189 | } | |
2190 | ||
2191 | /* | |
2192 | * If this function returns true, this #vmexit was already handled | |
2193 | */ | |
b8e88bc8 | 2194 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2195 | { |
2196 | u32 exit_code = svm->vmcb->control.exit_code; | |
2197 | int vmexit = NESTED_EXIT_HOST; | |
2198 | ||
cf74a78b | 2199 | switch (exit_code) { |
9c4e40b9 | 2200 | case SVM_EXIT_MSR: |
3d62d9aa | 2201 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2202 | break; |
ce2ac085 JR |
2203 | case SVM_EXIT_IOIO: |
2204 | vmexit = nested_svm_intercept_ioio(svm); | |
2205 | break; | |
4ee546b4 RJ |
2206 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2207 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2208 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2209 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2210 | break; |
2211 | } | |
3aed041a JR |
2212 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2213 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2214 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2215 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2216 | break; |
2217 | } | |
2218 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2219 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 2220 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 2221 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
2222 | /* async page fault always cause vmexit */ |
2223 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
2224 | svm->apf_reason != 0) | |
2225 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2226 | break; |
2227 | } | |
228070b1 JR |
2228 | case SVM_EXIT_ERR: { |
2229 | vmexit = NESTED_EXIT_DONE; | |
2230 | break; | |
2231 | } | |
cf74a78b AG |
2232 | default: { |
2233 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2234 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2235 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2236 | } |
2237 | } | |
2238 | ||
b8e88bc8 JR |
2239 | return vmexit; |
2240 | } | |
2241 | ||
2242 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2243 | { | |
2244 | int vmexit; | |
2245 | ||
2246 | vmexit = nested_svm_intercept(svm); | |
2247 | ||
2248 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2249 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2250 | |
2251 | return vmexit; | |
cf74a78b AG |
2252 | } |
2253 | ||
0460a979 JR |
2254 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2255 | { | |
2256 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2257 | struct vmcb_control_area *from = &from_vmcb->control; | |
2258 | ||
4ee546b4 | 2259 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2260 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2261 | dst->intercept_exceptions = from->intercept_exceptions; |
2262 | dst->intercept = from->intercept; | |
2263 | dst->iopm_base_pa = from->iopm_base_pa; | |
2264 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2265 | dst->tsc_offset = from->tsc_offset; | |
2266 | dst->asid = from->asid; | |
2267 | dst->tlb_ctl = from->tlb_ctl; | |
2268 | dst->int_ctl = from->int_ctl; | |
2269 | dst->int_vector = from->int_vector; | |
2270 | dst->int_state = from->int_state; | |
2271 | dst->exit_code = from->exit_code; | |
2272 | dst->exit_code_hi = from->exit_code_hi; | |
2273 | dst->exit_info_1 = from->exit_info_1; | |
2274 | dst->exit_info_2 = from->exit_info_2; | |
2275 | dst->exit_int_info = from->exit_int_info; | |
2276 | dst->exit_int_info_err = from->exit_int_info_err; | |
2277 | dst->nested_ctl = from->nested_ctl; | |
2278 | dst->event_inj = from->event_inj; | |
2279 | dst->event_inj_err = from->event_inj_err; | |
2280 | dst->nested_cr3 = from->nested_cr3; | |
2281 | dst->lbr_ctl = from->lbr_ctl; | |
2282 | } | |
2283 | ||
34f80cfa | 2284 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2285 | { |
34f80cfa | 2286 | struct vmcb *nested_vmcb; |
e6aa9abd | 2287 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2288 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2289 | struct page *page; |
cf74a78b | 2290 | |
17897f36 JR |
2291 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2292 | vmcb->control.exit_info_1, | |
2293 | vmcb->control.exit_info_2, | |
2294 | vmcb->control.exit_int_info, | |
e097e5ff SH |
2295 | vmcb->control.exit_int_info_err, |
2296 | KVM_ISA_SVM); | |
17897f36 | 2297 | |
7597f129 | 2298 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2299 | if (!nested_vmcb) |
2300 | return 1; | |
2301 | ||
2030753d JR |
2302 | /* Exit Guest-Mode */ |
2303 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2304 | svm->nested.vmcb = 0; |
2305 | ||
cf74a78b | 2306 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2307 | disable_gif(svm); |
2308 | ||
2309 | nested_vmcb->save.es = vmcb->save.es; | |
2310 | nested_vmcb->save.cs = vmcb->save.cs; | |
2311 | nested_vmcb->save.ss = vmcb->save.ss; | |
2312 | nested_vmcb->save.ds = vmcb->save.ds; | |
2313 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2314 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2315 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2316 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2317 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2318 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2319 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2320 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2321 | nested_vmcb->save.rip = vmcb->save.rip; |
2322 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2323 | nested_vmcb->save.rax = vmcb->save.rax; | |
2324 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2325 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2326 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2327 | ||
2328 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2329 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2330 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2331 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2332 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2333 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2334 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2335 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2336 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
7a190667 | 2337 | nested_vmcb->control.next_rip = vmcb->control.next_rip; |
8d23c466 AG |
2338 | |
2339 | /* | |
2340 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2341 | * to make sure that we do not lose injected events. So check event_inj | |
2342 | * here and copy it to exit_int_info if it is valid. | |
2343 | * Exit_int_info and event_inj can't be both valid because the case | |
2344 | * below only happens on a VMRUN instruction intercept which has | |
2345 | * no valid exit_int_info set. | |
2346 | */ | |
2347 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2348 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2349 | ||
2350 | nc->exit_int_info = vmcb->control.event_inj; | |
2351 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2352 | } | |
2353 | ||
33740e40 JR |
2354 | nested_vmcb->control.tlb_ctl = 0; |
2355 | nested_vmcb->control.event_inj = 0; | |
2356 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2357 | |
2358 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2359 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2360 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2361 | ||
cf74a78b | 2362 | /* Restore the original control entries */ |
0460a979 | 2363 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2364 | |
219b65dc AG |
2365 | kvm_clear_exception_queue(&svm->vcpu); |
2366 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2367 | |
4b16184c JR |
2368 | svm->nested.nested_cr3 = 0; |
2369 | ||
cf74a78b AG |
2370 | /* Restore selected save entries */ |
2371 | svm->vmcb->save.es = hsave->save.es; | |
2372 | svm->vmcb->save.cs = hsave->save.cs; | |
2373 | svm->vmcb->save.ss = hsave->save.ss; | |
2374 | svm->vmcb->save.ds = hsave->save.ds; | |
2375 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2376 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2377 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2378 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2379 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2380 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2381 | if (npt_enabled) { | |
2382 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2383 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2384 | } else { | |
2390218b | 2385 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2386 | } |
2387 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2388 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2389 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2390 | svm->vmcb->save.dr7 = 0; | |
2391 | svm->vmcb->save.cpl = 0; | |
2392 | svm->vmcb->control.exit_int_info = 0; | |
2393 | ||
8d28fec4 RJ |
2394 | mark_all_dirty(svm->vmcb); |
2395 | ||
7597f129 | 2396 | nested_svm_unmap(page); |
cf74a78b | 2397 | |
4b16184c | 2398 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2399 | kvm_mmu_reset_context(&svm->vcpu); |
2400 | kvm_mmu_load(&svm->vcpu); | |
2401 | ||
2402 | return 0; | |
2403 | } | |
3d6368ef | 2404 | |
9738b2c9 | 2405 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2406 | { |
323c3d80 JR |
2407 | /* |
2408 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 2409 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
2410 | * the kvm msr permission bitmap may contain zero bits |
2411 | */ | |
3d6368ef | 2412 | int i; |
9738b2c9 | 2413 | |
323c3d80 JR |
2414 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2415 | return true; | |
9738b2c9 | 2416 | |
323c3d80 JR |
2417 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2418 | u32 value, p; | |
2419 | u64 offset; | |
9738b2c9 | 2420 | |
323c3d80 JR |
2421 | if (msrpm_offsets[i] == 0xffffffff) |
2422 | break; | |
3d6368ef | 2423 | |
0d6b3537 JR |
2424 | p = msrpm_offsets[i]; |
2425 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2426 | |
2427 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2428 | return false; | |
2429 | ||
2430 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2431 | } | |
3d6368ef | 2432 | |
323c3d80 | 2433 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2434 | |
2435 | return true; | |
3d6368ef AG |
2436 | } |
2437 | ||
52c65a30 JR |
2438 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2439 | { | |
2440 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2441 | return false; | |
2442 | ||
dbe77584 JR |
2443 | if (vmcb->control.asid == 0) |
2444 | return false; | |
2445 | ||
4b16184c JR |
2446 | if (vmcb->control.nested_ctl && !npt_enabled) |
2447 | return false; | |
2448 | ||
52c65a30 JR |
2449 | return true; |
2450 | } | |
2451 | ||
9738b2c9 | 2452 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2453 | { |
9738b2c9 | 2454 | struct vmcb *nested_vmcb; |
e6aa9abd | 2455 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2456 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2457 | struct page *page; |
06fc7772 | 2458 | u64 vmcb_gpa; |
3d6368ef | 2459 | |
06fc7772 | 2460 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2461 | |
7597f129 | 2462 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2463 | if (!nested_vmcb) |
2464 | return false; | |
2465 | ||
52c65a30 JR |
2466 | if (!nested_vmcb_checks(nested_vmcb)) { |
2467 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2468 | nested_vmcb->control.exit_code_hi = 0; | |
2469 | nested_vmcb->control.exit_info_1 = 0; | |
2470 | nested_vmcb->control.exit_info_2 = 0; | |
2471 | ||
2472 | nested_svm_unmap(page); | |
2473 | ||
2474 | return false; | |
2475 | } | |
2476 | ||
b75f4eb3 | 2477 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2478 | nested_vmcb->save.rip, |
2479 | nested_vmcb->control.int_ctl, | |
2480 | nested_vmcb->control.event_inj, | |
2481 | nested_vmcb->control.nested_ctl); | |
2482 | ||
4ee546b4 RJ |
2483 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2484 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2485 | nested_vmcb->control.intercept_exceptions, |
2486 | nested_vmcb->control.intercept); | |
2487 | ||
3d6368ef | 2488 | /* Clear internal status */ |
219b65dc AG |
2489 | kvm_clear_exception_queue(&svm->vcpu); |
2490 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2491 | |
e0231715 JR |
2492 | /* |
2493 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2494 | * restore everything when a VMEXIT occurs | |
2495 | */ | |
defbba56 JR |
2496 | hsave->save.es = vmcb->save.es; |
2497 | hsave->save.cs = vmcb->save.cs; | |
2498 | hsave->save.ss = vmcb->save.ss; | |
2499 | hsave->save.ds = vmcb->save.ds; | |
2500 | hsave->save.gdtr = vmcb->save.gdtr; | |
2501 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2502 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2503 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 | 2504 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2505 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); |
b75f4eb3 | 2506 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2507 | hsave->save.rsp = vmcb->save.rsp; |
2508 | hsave->save.rax = vmcb->save.rax; | |
2509 | if (npt_enabled) | |
2510 | hsave->save.cr3 = vmcb->save.cr3; | |
2511 | else | |
9f8fe504 | 2512 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2513 | |
0460a979 | 2514 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef | 2515 | |
f6e78475 | 2516 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2517 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2518 | else | |
2519 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2520 | ||
4b16184c JR |
2521 | if (nested_vmcb->control.nested_ctl) { |
2522 | kvm_mmu_unload(&svm->vcpu); | |
2523 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2524 | nested_svm_init_mmu_context(&svm->vcpu); | |
2525 | } | |
2526 | ||
3d6368ef AG |
2527 | /* Load the nested guest state */ |
2528 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2529 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2530 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2531 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2532 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2533 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2534 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2535 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
2536 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2537 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2538 | if (npt_enabled) { | |
2539 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2540 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2541 | } else |
2390218b | 2542 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2543 | |
2544 | /* Guest paging mode is active - reset mmu */ | |
2545 | kvm_mmu_reset_context(&svm->vcpu); | |
2546 | ||
defbba56 | 2547 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2548 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2549 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2550 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2551 | |
3d6368ef AG |
2552 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2553 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2554 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2555 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2556 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2557 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2558 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2559 | ||
f7138538 | 2560 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2561 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2562 | |
aad42c64 | 2563 | /* cache intercepts */ |
4ee546b4 | 2564 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2565 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2566 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2567 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2568 | ||
f40f6a45 | 2569 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2570 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2571 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2572 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2573 | else | |
2574 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2575 | ||
88ab24ad JR |
2576 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2577 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2578 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2579 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2580 | } |
2581 | ||
0d945bd9 | 2582 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2583 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2584 | |
88ab24ad | 2585 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2586 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2587 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2588 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2589 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2590 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2591 | ||
7597f129 | 2592 | nested_svm_unmap(page); |
9738b2c9 | 2593 | |
2030753d JR |
2594 | /* Enter Guest-Mode */ |
2595 | enter_guest_mode(&svm->vcpu); | |
2596 | ||
384c6368 JR |
2597 | /* |
2598 | * Merge guest and host intercepts - must be called with vcpu in | |
2599 | * guest-mode to take affect here | |
2600 | */ | |
2601 | recalc_intercepts(svm); | |
2602 | ||
06fc7772 | 2603 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2604 | |
2af9194d | 2605 | enable_gif(svm); |
3d6368ef | 2606 | |
8d28fec4 RJ |
2607 | mark_all_dirty(svm->vmcb); |
2608 | ||
9738b2c9 | 2609 | return true; |
3d6368ef AG |
2610 | } |
2611 | ||
9966bf68 | 2612 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2613 | { |
2614 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2615 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2616 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2617 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2618 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2619 | to_vmcb->save.star = from_vmcb->save.star; | |
2620 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2621 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2622 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2623 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2624 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2625 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2626 | } |
2627 | ||
851ba692 | 2628 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2629 | { |
9966bf68 | 2630 | struct vmcb *nested_vmcb; |
7597f129 | 2631 | struct page *page; |
9966bf68 | 2632 | |
5542675b AG |
2633 | if (nested_svm_check_permissions(svm)) |
2634 | return 1; | |
2635 | ||
7597f129 | 2636 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2637 | if (!nested_vmcb) |
2638 | return 1; | |
2639 | ||
e3e9ed3d JR |
2640 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2641 | skip_emulated_instruction(&svm->vcpu); | |
2642 | ||
9966bf68 | 2643 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 2644 | nested_svm_unmap(page); |
5542675b AG |
2645 | |
2646 | return 1; | |
2647 | } | |
2648 | ||
851ba692 | 2649 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2650 | { |
9966bf68 | 2651 | struct vmcb *nested_vmcb; |
7597f129 | 2652 | struct page *page; |
9966bf68 | 2653 | |
5542675b AG |
2654 | if (nested_svm_check_permissions(svm)) |
2655 | return 1; | |
2656 | ||
7597f129 | 2657 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2658 | if (!nested_vmcb) |
2659 | return 1; | |
2660 | ||
e3e9ed3d JR |
2661 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2662 | skip_emulated_instruction(&svm->vcpu); | |
2663 | ||
9966bf68 | 2664 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 2665 | nested_svm_unmap(page); |
5542675b AG |
2666 | |
2667 | return 1; | |
2668 | } | |
2669 | ||
851ba692 | 2670 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2671 | { |
3d6368ef AG |
2672 | if (nested_svm_check_permissions(svm)) |
2673 | return 1; | |
2674 | ||
b75f4eb3 RJ |
2675 | /* Save rip after vmrun instruction */ |
2676 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2677 | |
9738b2c9 | 2678 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2679 | return 1; |
2680 | ||
9738b2c9 | 2681 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2682 | goto failed; |
2683 | ||
2684 | return 1; | |
2685 | ||
2686 | failed: | |
2687 | ||
2688 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2689 | svm->vmcb->control.exit_code_hi = 0; | |
2690 | svm->vmcb->control.exit_info_1 = 0; | |
2691 | svm->vmcb->control.exit_info_2 = 0; | |
2692 | ||
2693 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2694 | |
2695 | return 1; | |
2696 | } | |
2697 | ||
851ba692 | 2698 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2699 | { |
2700 | if (nested_svm_check_permissions(svm)) | |
2701 | return 1; | |
2702 | ||
2703 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2704 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2705 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2706 | |
2af9194d | 2707 | enable_gif(svm); |
1371d904 AG |
2708 | |
2709 | return 1; | |
2710 | } | |
2711 | ||
851ba692 | 2712 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2713 | { |
2714 | if (nested_svm_check_permissions(svm)) | |
2715 | return 1; | |
2716 | ||
2717 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2718 | skip_emulated_instruction(&svm->vcpu); | |
2719 | ||
2af9194d | 2720 | disable_gif(svm); |
1371d904 AG |
2721 | |
2722 | /* After a CLGI no interrupts should come */ | |
2723 | svm_clear_vintr(svm); | |
2724 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2725 | ||
decdbf6a JR |
2726 | mark_dirty(svm->vmcb, VMCB_INTR); |
2727 | ||
1371d904 AG |
2728 | return 1; |
2729 | } | |
2730 | ||
851ba692 | 2731 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2732 | { |
2733 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2734 | |
ec1ff790 JR |
2735 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2736 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2737 | ||
ff092385 AG |
2738 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2739 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2740 | ||
2741 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2742 | skip_emulated_instruction(&svm->vcpu); | |
2743 | return 1; | |
2744 | } | |
2745 | ||
532a46b9 JR |
2746 | static int skinit_interception(struct vcpu_svm *svm) |
2747 | { | |
2748 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2749 | ||
2750 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2751 | return 1; | |
2752 | } | |
2753 | ||
81dd35d4 JR |
2754 | static int xsetbv_interception(struct vcpu_svm *svm) |
2755 | { | |
2756 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
2757 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
2758 | ||
2759 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
2760 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2761 | skip_emulated_instruction(&svm->vcpu); | |
2762 | } | |
2763 | ||
2764 | return 1; | |
2765 | } | |
2766 | ||
851ba692 | 2767 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2768 | { |
37817f29 | 2769 | u16 tss_selector; |
64a7ec06 GN |
2770 | int reason; |
2771 | int int_type = svm->vmcb->control.exit_int_info & | |
2772 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2773 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2774 | uint32_t type = |
2775 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2776 | uint32_t idt_v = | |
2777 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2778 | bool has_error_code = false; |
2779 | u32 error_code = 0; | |
37817f29 IE |
2780 | |
2781 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2782 | |
37817f29 IE |
2783 | if (svm->vmcb->control.exit_info_2 & |
2784 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2785 | reason = TASK_SWITCH_IRET; |
2786 | else if (svm->vmcb->control.exit_info_2 & | |
2787 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2788 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2789 | else if (idt_v) |
64a7ec06 GN |
2790 | reason = TASK_SWITCH_GATE; |
2791 | else | |
2792 | reason = TASK_SWITCH_CALL; | |
2793 | ||
fe8e7f83 GN |
2794 | if (reason == TASK_SWITCH_GATE) { |
2795 | switch (type) { | |
2796 | case SVM_EXITINTINFO_TYPE_NMI: | |
2797 | svm->vcpu.arch.nmi_injected = false; | |
2798 | break; | |
2799 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2800 | if (svm->vmcb->control.exit_info_2 & |
2801 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2802 | has_error_code = true; | |
2803 | error_code = | |
2804 | (u32)svm->vmcb->control.exit_info_2; | |
2805 | } | |
fe8e7f83 GN |
2806 | kvm_clear_exception_queue(&svm->vcpu); |
2807 | break; | |
2808 | case SVM_EXITINTINFO_TYPE_INTR: | |
2809 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2810 | break; | |
2811 | default: | |
2812 | break; | |
2813 | } | |
2814 | } | |
64a7ec06 | 2815 | |
8317c298 GN |
2816 | if (reason != TASK_SWITCH_GATE || |
2817 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2818 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2819 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2820 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2821 | |
7f3d35fd KW |
2822 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
2823 | int_vec = -1; | |
2824 | ||
2825 | if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, | |
acb54517 GN |
2826 | has_error_code, error_code) == EMULATE_FAIL) { |
2827 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2828 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2829 | svm->vcpu.run->internal.ndata = 0; | |
2830 | return 0; | |
2831 | } | |
2832 | return 1; | |
6aa8b732 AK |
2833 | } |
2834 | ||
851ba692 | 2835 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2836 | { |
5fdbf976 | 2837 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2838 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2839 | return 1; |
6aa8b732 AK |
2840 | } |
2841 | ||
851ba692 | 2842 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2843 | { |
2844 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 2845 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 2846 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 2847 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
f303b4ce | 2848 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
95ba8273 GN |
2849 | return 1; |
2850 | } | |
2851 | ||
851ba692 | 2852 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2853 | { |
df4f3108 AP |
2854 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
2855 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
2856 | ||
2857 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
2858 | skip_emulated_instruction(&svm->vcpu); | |
2859 | return 1; | |
a7052897 MT |
2860 | } |
2861 | ||
851ba692 | 2862 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2863 | { |
51d8b661 | 2864 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
2865 | } |
2866 | ||
332b56e4 AK |
2867 | static int rdpmc_interception(struct vcpu_svm *svm) |
2868 | { | |
2869 | int err; | |
2870 | ||
2871 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
2872 | return emulate_on_interception(svm); | |
2873 | ||
2874 | err = kvm_rdpmc(&svm->vcpu); | |
2875 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2876 | ||
2877 | return 1; | |
2878 | } | |
2879 | ||
628afd2a JR |
2880 | bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val) |
2881 | { | |
2882 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
2883 | bool ret = false; | |
2884 | u64 intercept; | |
2885 | ||
2886 | intercept = svm->nested.intercept; | |
2887 | ||
2888 | if (!is_guest_mode(&svm->vcpu) || | |
2889 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
2890 | return false; | |
2891 | ||
2892 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
2893 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
2894 | ||
2895 | if (cr0 ^ val) { | |
2896 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
2897 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
2898 | } | |
2899 | ||
2900 | return ret; | |
2901 | } | |
2902 | ||
7ff76d58 AP |
2903 | #define CR_VALID (1ULL << 63) |
2904 | ||
2905 | static int cr_interception(struct vcpu_svm *svm) | |
2906 | { | |
2907 | int reg, cr; | |
2908 | unsigned long val; | |
2909 | int err; | |
2910 | ||
2911 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2912 | return emulate_on_interception(svm); | |
2913 | ||
2914 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
2915 | return emulate_on_interception(svm); | |
2916 | ||
2917 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2918 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
2919 | ||
2920 | err = 0; | |
2921 | if (cr >= 16) { /* mov to cr */ | |
2922 | cr -= 16; | |
2923 | val = kvm_register_read(&svm->vcpu, reg); | |
2924 | switch (cr) { | |
2925 | case 0: | |
628afd2a JR |
2926 | if (!check_selective_cr0_intercepted(svm, val)) |
2927 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
2928 | else |
2929 | return 1; | |
2930 | ||
7ff76d58 AP |
2931 | break; |
2932 | case 3: | |
2933 | err = kvm_set_cr3(&svm->vcpu, val); | |
2934 | break; | |
2935 | case 4: | |
2936 | err = kvm_set_cr4(&svm->vcpu, val); | |
2937 | break; | |
2938 | case 8: | |
2939 | err = kvm_set_cr8(&svm->vcpu, val); | |
2940 | break; | |
2941 | default: | |
2942 | WARN(1, "unhandled write to CR%d", cr); | |
2943 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2944 | return 1; | |
2945 | } | |
2946 | } else { /* mov from cr */ | |
2947 | switch (cr) { | |
2948 | case 0: | |
2949 | val = kvm_read_cr0(&svm->vcpu); | |
2950 | break; | |
2951 | case 2: | |
2952 | val = svm->vcpu.arch.cr2; | |
2953 | break; | |
2954 | case 3: | |
9f8fe504 | 2955 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
2956 | break; |
2957 | case 4: | |
2958 | val = kvm_read_cr4(&svm->vcpu); | |
2959 | break; | |
2960 | case 8: | |
2961 | val = kvm_get_cr8(&svm->vcpu); | |
2962 | break; | |
2963 | default: | |
2964 | WARN(1, "unhandled read from CR%d", cr); | |
2965 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2966 | return 1; | |
2967 | } | |
2968 | kvm_register_write(&svm->vcpu, reg, val); | |
2969 | } | |
2970 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2971 | ||
2972 | return 1; | |
2973 | } | |
2974 | ||
cae3797a AP |
2975 | static int dr_interception(struct vcpu_svm *svm) |
2976 | { | |
2977 | int reg, dr; | |
2978 | unsigned long val; | |
2979 | int err; | |
2980 | ||
facb0139 PB |
2981 | if (svm->vcpu.guest_debug == 0) { |
2982 | /* | |
2983 | * No more DR vmexits; force a reload of the debug registers | |
2984 | * and reenter on this instruction. The next vmexit will | |
2985 | * retrieve the full state of the debug registers. | |
2986 | */ | |
2987 | clr_dr_intercepts(svm); | |
2988 | svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
2989 | return 1; | |
2990 | } | |
2991 | ||
cae3797a AP |
2992 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) |
2993 | return emulate_on_interception(svm); | |
2994 | ||
2995 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2996 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
2997 | ||
2998 | if (dr >= 16) { /* mov to DRn */ | |
2999 | val = kvm_register_read(&svm->vcpu, reg); | |
3000 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
3001 | } else { | |
3002 | err = kvm_get_dr(&svm->vcpu, dr, &val); | |
3003 | if (!err) | |
3004 | kvm_register_write(&svm->vcpu, reg, val); | |
3005 | } | |
3006 | ||
2c46d2ae JR |
3007 | skip_emulated_instruction(&svm->vcpu); |
3008 | ||
cae3797a AP |
3009 | return 1; |
3010 | } | |
3011 | ||
851ba692 | 3012 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 3013 | { |
851ba692 | 3014 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 3015 | int r; |
851ba692 | 3016 | |
0a5fff19 GN |
3017 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
3018 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 3019 | r = cr_interception(svm); |
596f3142 | 3020 | if (irqchip_in_kernel(svm->vcpu.kvm)) |
7ff76d58 | 3021 | return r; |
0a5fff19 | 3022 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 3023 | return r; |
1d075434 JR |
3024 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
3025 | return 0; | |
3026 | } | |
3027 | ||
886b470c | 3028 | u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
d5c1785d NHE |
3029 | { |
3030 | struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu)); | |
3031 | return vmcb->control.tsc_offset + | |
886b470c | 3032 | svm_scale_tsc(vcpu, host_tsc); |
d5c1785d NHE |
3033 | } |
3034 | ||
6aa8b732 AK |
3035 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
3036 | { | |
a2fa3e9f GH |
3037 | struct vcpu_svm *svm = to_svm(vcpu); |
3038 | ||
6aa8b732 | 3039 | switch (ecx) { |
af24a4e4 | 3040 | case MSR_IA32_TSC: { |
45133eca | 3041 | *data = svm->vmcb->control.tsc_offset + |
fbc0db76 JR |
3042 | svm_scale_tsc(vcpu, native_read_tsc()); |
3043 | ||
6aa8b732 AK |
3044 | break; |
3045 | } | |
8c06585d | 3046 | case MSR_STAR: |
a2fa3e9f | 3047 | *data = svm->vmcb->save.star; |
6aa8b732 | 3048 | break; |
0e859cac | 3049 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3050 | case MSR_LSTAR: |
a2fa3e9f | 3051 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3052 | break; |
3053 | case MSR_CSTAR: | |
a2fa3e9f | 3054 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3055 | break; |
3056 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3057 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3058 | break; |
3059 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3060 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3061 | break; |
3062 | #endif | |
3063 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3064 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3065 | break; |
3066 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3067 | *data = svm->sysenter_eip; |
6aa8b732 AK |
3068 | break; |
3069 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3070 | *data = svm->sysenter_esp; |
6aa8b732 | 3071 | break; |
e0231715 JR |
3072 | /* |
3073 | * Nobody will change the following 5 values in the VMCB so we can | |
3074 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3075 | * implemented. | |
3076 | */ | |
a2938c80 JR |
3077 | case MSR_IA32_DEBUGCTLMSR: |
3078 | *data = svm->vmcb->save.dbgctl; | |
3079 | break; | |
3080 | case MSR_IA32_LASTBRANCHFROMIP: | |
3081 | *data = svm->vmcb->save.br_from; | |
3082 | break; | |
3083 | case MSR_IA32_LASTBRANCHTOIP: | |
3084 | *data = svm->vmcb->save.br_to; | |
3085 | break; | |
3086 | case MSR_IA32_LASTINTFROMIP: | |
3087 | *data = svm->vmcb->save.last_excp_from; | |
3088 | break; | |
3089 | case MSR_IA32_LASTINTTOIP: | |
3090 | *data = svm->vmcb->save.last_excp_to; | |
3091 | break; | |
b286d5d8 | 3092 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3093 | *data = svm->nested.hsave_msr; |
b286d5d8 | 3094 | break; |
eb6f302e | 3095 | case MSR_VM_CR: |
4a810181 | 3096 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 3097 | break; |
c8a73f18 AG |
3098 | case MSR_IA32_UCODE_REV: |
3099 | *data = 0x01000065; | |
3100 | break; | |
6aa8b732 | 3101 | default: |
3bab1f5d | 3102 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
3103 | } |
3104 | return 0; | |
3105 | } | |
3106 | ||
851ba692 | 3107 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3108 | { |
ad312c7c | 3109 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
3110 | u64 data; |
3111 | ||
59200273 AK |
3112 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
3113 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 3114 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 3115 | } else { |
229456fc | 3116 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 3117 | |
5fdbf976 | 3118 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 3119 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 3120 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 3121 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
3122 | } |
3123 | return 1; | |
3124 | } | |
3125 | ||
4a810181 JR |
3126 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3127 | { | |
3128 | struct vcpu_svm *svm = to_svm(vcpu); | |
3129 | int svm_dis, chg_mask; | |
3130 | ||
3131 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3132 | return 1; | |
3133 | ||
3134 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3135 | ||
3136 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3137 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3138 | ||
3139 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3140 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3141 | ||
3142 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3143 | ||
3144 | /* check for svm_disable while efer.svme is set */ | |
3145 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3146 | return 1; | |
3147 | ||
3148 | return 0; | |
3149 | } | |
3150 | ||
8fe8ab46 | 3151 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 3152 | { |
a2fa3e9f GH |
3153 | struct vcpu_svm *svm = to_svm(vcpu); |
3154 | ||
8fe8ab46 WA |
3155 | u32 ecx = msr->index; |
3156 | u64 data = msr->data; | |
6aa8b732 | 3157 | switch (ecx) { |
f4e1b3c8 | 3158 | case MSR_IA32_TSC: |
8fe8ab46 | 3159 | kvm_write_tsc(vcpu, msr); |
6aa8b732 | 3160 | break; |
8c06585d | 3161 | case MSR_STAR: |
a2fa3e9f | 3162 | svm->vmcb->save.star = data; |
6aa8b732 | 3163 | break; |
49b14f24 | 3164 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3165 | case MSR_LSTAR: |
a2fa3e9f | 3166 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3167 | break; |
3168 | case MSR_CSTAR: | |
a2fa3e9f | 3169 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3170 | break; |
3171 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3172 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3173 | break; |
3174 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3175 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3176 | break; |
3177 | #endif | |
3178 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3179 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3180 | break; |
3181 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3182 | svm->sysenter_eip = data; |
a2fa3e9f | 3183 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
3184 | break; |
3185 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3186 | svm->sysenter_esp = data; |
a2fa3e9f | 3187 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 3188 | break; |
a2938c80 | 3189 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 3190 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
3191 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
3192 | __func__, data); | |
24e09cbf JR |
3193 | break; |
3194 | } | |
3195 | if (data & DEBUGCTL_RESERVED_BITS) | |
3196 | return 1; | |
3197 | ||
3198 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 3199 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
3200 | if (data & (1ULL<<0)) |
3201 | svm_enable_lbrv(svm); | |
3202 | else | |
3203 | svm_disable_lbrv(svm); | |
a2938c80 | 3204 | break; |
b286d5d8 | 3205 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3206 | svm->nested.hsave_msr = data; |
62b9abaa | 3207 | break; |
3c5d0a44 | 3208 | case MSR_VM_CR: |
4a810181 | 3209 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3210 | case MSR_VM_IGNNE: |
a737f256 | 3211 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 3212 | break; |
6aa8b732 | 3213 | default: |
8fe8ab46 | 3214 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
3215 | } |
3216 | return 0; | |
3217 | } | |
3218 | ||
851ba692 | 3219 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3220 | { |
8fe8ab46 | 3221 | struct msr_data msr; |
ad312c7c | 3222 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 3223 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 3224 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 3225 | |
8fe8ab46 WA |
3226 | msr.data = data; |
3227 | msr.index = ecx; | |
3228 | msr.host_initiated = false; | |
af9ca2d7 | 3229 | |
5fdbf976 | 3230 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
8fe8ab46 | 3231 | if (svm_set_msr(&svm->vcpu, &msr)) { |
59200273 | 3232 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3233 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
3234 | } else { |
3235 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 3236 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 3237 | } |
6aa8b732 AK |
3238 | return 1; |
3239 | } | |
3240 | ||
851ba692 | 3241 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3242 | { |
e756fc62 | 3243 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3244 | return wrmsr_interception(svm); |
6aa8b732 | 3245 | else |
851ba692 | 3246 | return rdmsr_interception(svm); |
6aa8b732 AK |
3247 | } |
3248 | ||
851ba692 | 3249 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3250 | { |
851ba692 AK |
3251 | struct kvm_run *kvm_run = svm->vcpu.run; |
3252 | ||
3842d135 | 3253 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3254 | svm_clear_vintr(svm); |
85f455f7 | 3255 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3256 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 3257 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3258 | /* |
3259 | * If the user space waits to inject interrupts, exit as soon as | |
3260 | * possible | |
3261 | */ | |
8061823a GN |
3262 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
3263 | kvm_run->request_interrupt_window && | |
3264 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
c1150d8c DL |
3265 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
3266 | return 0; | |
3267 | } | |
3268 | ||
3269 | return 1; | |
3270 | } | |
3271 | ||
565d0998 ML |
3272 | static int pause_interception(struct vcpu_svm *svm) |
3273 | { | |
3274 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3275 | return 1; | |
3276 | } | |
3277 | ||
87c00572 GS |
3278 | static int nop_interception(struct vcpu_svm *svm) |
3279 | { | |
3280 | skip_emulated_instruction(&(svm->vcpu)); | |
3281 | return 1; | |
3282 | } | |
3283 | ||
3284 | static int monitor_interception(struct vcpu_svm *svm) | |
3285 | { | |
3286 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
3287 | return nop_interception(svm); | |
3288 | } | |
3289 | ||
3290 | static int mwait_interception(struct vcpu_svm *svm) | |
3291 | { | |
3292 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
3293 | return nop_interception(svm); | |
3294 | } | |
3295 | ||
09941fbb | 3296 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
3297 | [SVM_EXIT_READ_CR0] = cr_interception, |
3298 | [SVM_EXIT_READ_CR3] = cr_interception, | |
3299 | [SVM_EXIT_READ_CR4] = cr_interception, | |
3300 | [SVM_EXIT_READ_CR8] = cr_interception, | |
d225157b | 3301 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
628afd2a | 3302 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
3303 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
3304 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 3305 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
3306 | [SVM_EXIT_READ_DR0] = dr_interception, |
3307 | [SVM_EXIT_READ_DR1] = dr_interception, | |
3308 | [SVM_EXIT_READ_DR2] = dr_interception, | |
3309 | [SVM_EXIT_READ_DR3] = dr_interception, | |
3310 | [SVM_EXIT_READ_DR4] = dr_interception, | |
3311 | [SVM_EXIT_READ_DR5] = dr_interception, | |
3312 | [SVM_EXIT_READ_DR6] = dr_interception, | |
3313 | [SVM_EXIT_READ_DR7] = dr_interception, | |
3314 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
3315 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
3316 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
3317 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
3318 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
3319 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
3320 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
3321 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
3322 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
3323 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 3324 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
3325 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
3326 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
3327 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
3328 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 3329 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
3330 | [SVM_EXIT_SMI] = nop_on_interception, |
3331 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 3332 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 3333 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 3334 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 3335 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 3336 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 3337 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 3338 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 3339 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 3340 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 3341 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
3342 | [SVM_EXIT_MSR] = msr_interception, |
3343 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 3344 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 3345 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 3346 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
3347 | [SVM_EXIT_VMLOAD] = vmload_interception, |
3348 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
3349 | [SVM_EXIT_STGI] = stgi_interception, |
3350 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 3351 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 3352 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
87c00572 GS |
3353 | [SVM_EXIT_MONITOR] = monitor_interception, |
3354 | [SVM_EXIT_MWAIT] = mwait_interception, | |
81dd35d4 | 3355 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 3356 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
3357 | }; |
3358 | ||
ae8cc059 | 3359 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
3360 | { |
3361 | struct vcpu_svm *svm = to_svm(vcpu); | |
3362 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3363 | struct vmcb_save_area *save = &svm->vmcb->save; | |
3364 | ||
3365 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
3366 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
3367 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
3368 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
3369 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
3370 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
3371 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
3372 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
3373 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
3374 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
3375 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
3376 | pr_err("%-20s%d\n", "asid:", control->asid); | |
3377 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
3378 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
3379 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
3380 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
3381 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
3382 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
3383 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
3384 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
3385 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
3386 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
3387 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
3388 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); | |
3389 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
3390 | pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl); | |
3391 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); | |
3f10c846 | 3392 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
3393 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
3394 | "es:", | |
3395 | save->es.selector, save->es.attrib, | |
3396 | save->es.limit, save->es.base); | |
3397 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3398 | "cs:", | |
3399 | save->cs.selector, save->cs.attrib, | |
3400 | save->cs.limit, save->cs.base); | |
3401 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3402 | "ss:", | |
3403 | save->ss.selector, save->ss.attrib, | |
3404 | save->ss.limit, save->ss.base); | |
3405 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3406 | "ds:", | |
3407 | save->ds.selector, save->ds.attrib, | |
3408 | save->ds.limit, save->ds.base); | |
3409 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3410 | "fs:", | |
3411 | save->fs.selector, save->fs.attrib, | |
3412 | save->fs.limit, save->fs.base); | |
3413 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3414 | "gs:", | |
3415 | save->gs.selector, save->gs.attrib, | |
3416 | save->gs.limit, save->gs.base); | |
3417 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3418 | "gdtr:", | |
3419 | save->gdtr.selector, save->gdtr.attrib, | |
3420 | save->gdtr.limit, save->gdtr.base); | |
3421 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3422 | "ldtr:", | |
3423 | save->ldtr.selector, save->ldtr.attrib, | |
3424 | save->ldtr.limit, save->ldtr.base); | |
3425 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3426 | "idtr:", | |
3427 | save->idtr.selector, save->idtr.attrib, | |
3428 | save->idtr.limit, save->idtr.base); | |
3429 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3430 | "tr:", | |
3431 | save->tr.selector, save->tr.attrib, | |
3432 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
3433 | pr_err("cpl: %d efer: %016llx\n", |
3434 | save->cpl, save->efer); | |
ae8cc059 JP |
3435 | pr_err("%-15s %016llx %-13s %016llx\n", |
3436 | "cr0:", save->cr0, "cr2:", save->cr2); | |
3437 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3438 | "cr3:", save->cr3, "cr4:", save->cr4); | |
3439 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3440 | "dr6:", save->dr6, "dr7:", save->dr7); | |
3441 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3442 | "rip:", save->rip, "rflags:", save->rflags); | |
3443 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3444 | "rsp:", save->rsp, "rax:", save->rax); | |
3445 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3446 | "star:", save->star, "lstar:", save->lstar); | |
3447 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3448 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
3449 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3450 | "kernel_gs_base:", save->kernel_gs_base, | |
3451 | "sysenter_cs:", save->sysenter_cs); | |
3452 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3453 | "sysenter_esp:", save->sysenter_esp, | |
3454 | "sysenter_eip:", save->sysenter_eip); | |
3455 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3456 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
3457 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3458 | "br_from:", save->br_from, "br_to:", save->br_to); | |
3459 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3460 | "excp_from:", save->last_excp_from, | |
3461 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
3462 | } |
3463 | ||
586f9607 AK |
3464 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3465 | { | |
3466 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3467 | ||
3468 | *info1 = control->exit_info_1; | |
3469 | *info2 = control->exit_info_2; | |
3470 | } | |
3471 | ||
851ba692 | 3472 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3473 | { |
04d2cc77 | 3474 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3475 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3476 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3477 | |
4ee546b4 | 3478 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3479 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3480 | if (npt_enabled) | |
3481 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3482 | |
cd3ff653 JR |
3483 | if (unlikely(svm->nested.exit_required)) { |
3484 | nested_svm_vmexit(svm); | |
3485 | svm->nested.exit_required = false; | |
3486 | ||
3487 | return 1; | |
3488 | } | |
3489 | ||
2030753d | 3490 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3491 | int vmexit; |
3492 | ||
d8cabddf JR |
3493 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3494 | svm->vmcb->control.exit_info_1, | |
3495 | svm->vmcb->control.exit_info_2, | |
3496 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
3497 | svm->vmcb->control.exit_int_info_err, |
3498 | KVM_ISA_SVM); | |
d8cabddf | 3499 | |
410e4d57 JR |
3500 | vmexit = nested_svm_exit_special(svm); |
3501 | ||
3502 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3503 | vmexit = nested_svm_exit_handled(svm); | |
3504 | ||
3505 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3506 | return 1; |
cf74a78b AG |
3507 | } |
3508 | ||
a5c3832d JR |
3509 | svm_complete_interrupts(svm); |
3510 | ||
04d2cc77 AK |
3511 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3512 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3513 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3514 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3515 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3516 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3517 | return 0; |
3518 | } | |
3519 | ||
a2fa3e9f | 3520 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3521 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3522 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3523 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 3524 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 3525 | "exit_code 0x%x\n", |
b8688d51 | 3526 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3527 | exit_code); |
3528 | ||
9d8f549d | 3529 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3530 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 3531 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 3532 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
3533 | return 0; |
3534 | } | |
3535 | ||
851ba692 | 3536 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3537 | } |
3538 | ||
3539 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3540 | { | |
3541 | int cpu = raw_smp_processor_id(); | |
3542 | ||
0fe1e009 TH |
3543 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3544 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3545 | load_TR_desc(); |
3546 | } | |
3547 | ||
e756fc62 | 3548 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3549 | { |
3550 | int cpu = raw_smp_processor_id(); | |
3551 | ||
0fe1e009 | 3552 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3553 | |
4b656b12 | 3554 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3555 | if (svm->asid_generation != sd->asid_generation) |
3556 | new_asid(svm, sd); | |
6aa8b732 AK |
3557 | } |
3558 | ||
95ba8273 GN |
3559 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3560 | { | |
3561 | struct vcpu_svm *svm = to_svm(vcpu); | |
3562 | ||
3563 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3564 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3565 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
3566 | ++vcpu->stat.nmi_injections; |
3567 | } | |
6aa8b732 | 3568 | |
85f455f7 | 3569 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3570 | { |
3571 | struct vmcb_control_area *control; | |
3572 | ||
e756fc62 | 3573 | control = &svm->vmcb->control; |
85f455f7 | 3574 | control->int_vector = irq; |
6aa8b732 AK |
3575 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3576 | control->int_ctl |= V_IRQ_MASK | | |
3577 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 3578 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
3579 | } |
3580 | ||
66fd3f7f | 3581 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3582 | { |
3583 | struct vcpu_svm *svm = to_svm(vcpu); | |
3584 | ||
2af9194d | 3585 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3586 | |
9fb2d2b4 GN |
3587 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3588 | ++vcpu->stat.irq_injections; | |
3589 | ||
219b65dc AG |
3590 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3591 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3592 | } |
3593 | ||
95ba8273 | 3594 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3595 | { |
3596 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3597 | |
2030753d | 3598 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3599 | return; |
3600 | ||
596f3142 RK |
3601 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
3602 | ||
95ba8273 | 3603 | if (irr == -1) |
aaacfc9a JR |
3604 | return; |
3605 | ||
95ba8273 | 3606 | if (tpr >= irr) |
4ee546b4 | 3607 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3608 | } |
aaacfc9a | 3609 | |
8d14695f YZ |
3610 | static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
3611 | { | |
3612 | return; | |
3613 | } | |
3614 | ||
c7c9c56c YZ |
3615 | static int svm_vm_has_apicv(struct kvm *kvm) |
3616 | { | |
3617 | return 0; | |
3618 | } | |
3619 | ||
3620 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) | |
3621 | { | |
3622 | return; | |
3623 | } | |
3624 | ||
3625 | static void svm_hwapic_isr_update(struct kvm *kvm, int isr) | |
3626 | { | |
3627 | return; | |
3628 | } | |
3629 | ||
a20ed54d YZ |
3630 | static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
3631 | { | |
3632 | return; | |
3633 | } | |
3634 | ||
95ba8273 GN |
3635 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3636 | { | |
3637 | struct vcpu_svm *svm = to_svm(vcpu); | |
3638 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3639 | int ret; |
3640 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3641 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3642 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3643 | ||
3644 | return ret; | |
aaacfc9a JR |
3645 | } |
3646 | ||
3cfc3092 JK |
3647 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3648 | { | |
3649 | struct vcpu_svm *svm = to_svm(vcpu); | |
3650 | ||
3651 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3652 | } | |
3653 | ||
3654 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3655 | { | |
3656 | struct vcpu_svm *svm = to_svm(vcpu); | |
3657 | ||
3658 | if (masked) { | |
3659 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3660 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3661 | } else { |
3662 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 3663 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3664 | } |
3665 | } | |
3666 | ||
78646121 GN |
3667 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3668 | { | |
3669 | struct vcpu_svm *svm = to_svm(vcpu); | |
3670 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3671 | int ret; |
3672 | ||
3673 | if (!gif_set(svm) || | |
3674 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3675 | return 0; | |
3676 | ||
f6e78475 | 3677 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 3678 | |
2030753d | 3679 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3680 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3681 | ||
3682 | return ret; | |
78646121 GN |
3683 | } |
3684 | ||
c9a7953f | 3685 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3686 | { |
219b65dc | 3687 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3688 | |
e0231715 JR |
3689 | /* |
3690 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3691 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3692 | * get that intercept, this function will be called again though and | |
3693 | * we'll get the vintr intercept. | |
3694 | */ | |
8fe54654 | 3695 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3696 | svm_set_vintr(svm); |
3697 | svm_inject_irq(svm, 0x0); | |
3698 | } | |
85f455f7 ED |
3699 | } |
3700 | ||
c9a7953f | 3701 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3702 | { |
04d2cc77 | 3703 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3704 | |
44c11430 GN |
3705 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3706 | == HF_NMI_MASK) | |
c9a7953f | 3707 | return; /* IRET will cause a vm exit */ |
44c11430 | 3708 | |
e0231715 JR |
3709 | /* |
3710 | * Something prevents NMI from been injected. Single step over possible | |
3711 | * problem (IRET or exception injection or interrupt shadow) | |
3712 | */ | |
6be7d306 | 3713 | svm->nmi_singlestep = true; |
44c11430 | 3714 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c8639010 | 3715 | update_db_bp_intercept(vcpu); |
c1150d8c DL |
3716 | } |
3717 | ||
cbc94022 IE |
3718 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3719 | { | |
3720 | return 0; | |
3721 | } | |
3722 | ||
d9e368d6 AK |
3723 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3724 | { | |
38e5e92f JR |
3725 | struct vcpu_svm *svm = to_svm(vcpu); |
3726 | ||
3727 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
3728 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
3729 | else | |
3730 | svm->asid_generation--; | |
d9e368d6 AK |
3731 | } |
3732 | ||
04d2cc77 AK |
3733 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3734 | { | |
3735 | } | |
3736 | ||
d7bf8221 JR |
3737 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3738 | { | |
3739 | struct vcpu_svm *svm = to_svm(vcpu); | |
3740 | ||
2030753d | 3741 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3742 | return; |
3743 | ||
4ee546b4 | 3744 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3745 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3746 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3747 | } |
3748 | } | |
3749 | ||
649d6864 JR |
3750 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3751 | { | |
3752 | struct vcpu_svm *svm = to_svm(vcpu); | |
3753 | u64 cr8; | |
3754 | ||
2030753d | 3755 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3756 | return; |
3757 | ||
649d6864 JR |
3758 | cr8 = kvm_get_cr8(vcpu); |
3759 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3760 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3761 | } | |
3762 | ||
9222be18 GN |
3763 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3764 | { | |
3765 | u8 vector; | |
3766 | int type; | |
3767 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3768 | unsigned int3_injected = svm->int3_injected; |
3769 | ||
3770 | svm->int3_injected = 0; | |
9222be18 | 3771 | |
bd3d1ec3 AK |
3772 | /* |
3773 | * If we've made progress since setting HF_IRET_MASK, we've | |
3774 | * executed an IRET and can allow NMI injection. | |
3775 | */ | |
3776 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
3777 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 3778 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3779 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3780 | } | |
44c11430 | 3781 | |
9222be18 GN |
3782 | svm->vcpu.arch.nmi_injected = false; |
3783 | kvm_clear_exception_queue(&svm->vcpu); | |
3784 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3785 | ||
3786 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3787 | return; | |
3788 | ||
3842d135 AK |
3789 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3790 | ||
9222be18 GN |
3791 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3792 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3793 | ||
3794 | switch (type) { | |
3795 | case SVM_EXITINTINFO_TYPE_NMI: | |
3796 | svm->vcpu.arch.nmi_injected = true; | |
3797 | break; | |
3798 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3799 | /* |
3800 | * In case of software exceptions, do not reinject the vector, | |
3801 | * but re-execute the instruction instead. Rewind RIP first | |
3802 | * if we emulated INT3 before. | |
3803 | */ | |
3804 | if (kvm_exception_is_soft(vector)) { | |
3805 | if (vector == BP_VECTOR && int3_injected && | |
3806 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3807 | kvm_rip_write(&svm->vcpu, | |
3808 | kvm_rip_read(&svm->vcpu) - | |
3809 | int3_injected); | |
9222be18 | 3810 | break; |
66b7138f | 3811 | } |
9222be18 GN |
3812 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3813 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3814 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3815 | |
3816 | } else | |
ce7ddec4 | 3817 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3818 | break; |
3819 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3820 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3821 | break; |
3822 | default: | |
3823 | break; | |
3824 | } | |
3825 | } | |
3826 | ||
b463a6f7 AK |
3827 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3828 | { | |
3829 | struct vcpu_svm *svm = to_svm(vcpu); | |
3830 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3831 | ||
3832 | control->exit_int_info = control->event_inj; | |
3833 | control->exit_int_info_err = control->event_inj_err; | |
3834 | control->event_inj = 0; | |
3835 | svm_complete_interrupts(svm); | |
3836 | } | |
3837 | ||
851ba692 | 3838 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3839 | { |
a2fa3e9f | 3840 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3841 | |
2041a06a JR |
3842 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3843 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3844 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3845 | ||
cd3ff653 JR |
3846 | /* |
3847 | * A vmexit emulation is required before the vcpu can be executed | |
3848 | * again. | |
3849 | */ | |
3850 | if (unlikely(svm->nested.exit_required)) | |
3851 | return; | |
3852 | ||
e756fc62 | 3853 | pre_svm_run(svm); |
6aa8b732 | 3854 | |
649d6864 JR |
3855 | sync_lapic_to_cr8(vcpu); |
3856 | ||
cda0ffdd | 3857 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3858 | |
04d2cc77 AK |
3859 | clgi(); |
3860 | ||
3861 | local_irq_enable(); | |
36241b8c | 3862 | |
6aa8b732 | 3863 | asm volatile ( |
7454766f AK |
3864 | "push %%" _ASM_BP "; \n\t" |
3865 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
3866 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
3867 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
3868 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
3869 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
3870 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 3871 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3872 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3873 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3874 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3875 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3876 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3877 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3878 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3879 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3880 | #endif |
3881 | ||
6aa8b732 | 3882 | /* Enter guest mode */ |
7454766f AK |
3883 | "push %%" _ASM_AX " \n\t" |
3884 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
4ecac3fd AK |
3885 | __ex(SVM_VMLOAD) "\n\t" |
3886 | __ex(SVM_VMRUN) "\n\t" | |
3887 | __ex(SVM_VMSAVE) "\n\t" | |
7454766f | 3888 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
3889 | |
3890 | /* Save guest registers, load host registers */ | |
7454766f AK |
3891 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
3892 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
3893 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
3894 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
3895 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
3896 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3897 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3898 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3899 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3900 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3901 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3902 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3903 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3904 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3905 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3906 | #endif |
7454766f | 3907 | "pop %%" _ASM_BP |
6aa8b732 | 3908 | : |
fb3f0f51 | 3909 | : [svm]"a"(svm), |
6aa8b732 | 3910 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3911 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3912 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3913 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3914 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3915 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3916 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3917 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3918 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3919 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3920 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3921 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3922 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3923 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3924 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3925 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3926 | #endif |
54a08c04 LV |
3927 | : "cc", "memory" |
3928 | #ifdef CONFIG_X86_64 | |
7454766f | 3929 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 3930 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
3931 | #else |
3932 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
3933 | #endif |
3934 | ); | |
6aa8b732 | 3935 | |
82ca2d10 AK |
3936 | #ifdef CONFIG_X86_64 |
3937 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3938 | #else | |
dacccfdd | 3939 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
3940 | #ifndef CONFIG_X86_32_LAZY_GS |
3941 | loadsegment(gs, svm->host.gs); | |
3942 | #endif | |
9581d442 | 3943 | #endif |
6aa8b732 AK |
3944 | |
3945 | reload_tss(vcpu); | |
3946 | ||
56ba47dd AK |
3947 | local_irq_disable(); |
3948 | ||
13c34e07 AK |
3949 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3950 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3951 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3952 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3953 | ||
1e2b1dd7 JK |
3954 | trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM); |
3955 | ||
3781c01c JR |
3956 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
3957 | kvm_before_handle_nmi(&svm->vcpu); | |
3958 | ||
3959 | stgi(); | |
3960 | ||
3961 | /* Any pending NMI will happen here */ | |
3962 | ||
3963 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
3964 | kvm_after_handle_nmi(&svm->vcpu); | |
3965 | ||
d7bf8221 JR |
3966 | sync_cr8_to_lapic(vcpu); |
3967 | ||
a2fa3e9f | 3968 | svm->next_rip = 0; |
9222be18 | 3969 | |
38e5e92f JR |
3970 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
3971 | ||
631bc487 GN |
3972 | /* if exit due to PF check for async PF */ |
3973 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3974 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3975 | ||
6de4f3ad AK |
3976 | if (npt_enabled) { |
3977 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3978 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3979 | } | |
fe5913e4 JR |
3980 | |
3981 | /* | |
3982 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3983 | * change the physical cpu | |
3984 | */ | |
3985 | if (unlikely(svm->vmcb->control.exit_code == | |
3986 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3987 | svm_handle_mce(svm); | |
8d28fec4 RJ |
3988 | |
3989 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
3990 | } |
3991 | ||
6aa8b732 AK |
3992 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3993 | { | |
a2fa3e9f GH |
3994 | struct vcpu_svm *svm = to_svm(vcpu); |
3995 | ||
3996 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 3997 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 3998 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
3999 | } |
4000 | ||
1c97f0a0 JR |
4001 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
4002 | { | |
4003 | struct vcpu_svm *svm = to_svm(vcpu); | |
4004 | ||
4005 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 4006 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
4007 | |
4008 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 4009 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 4010 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 4011 | |
f40f6a45 | 4012 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
4013 | } |
4014 | ||
6aa8b732 AK |
4015 | static int is_disabled(void) |
4016 | { | |
6031a61c JR |
4017 | u64 vm_cr; |
4018 | ||
4019 | rdmsrl(MSR_VM_CR, vm_cr); | |
4020 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
4021 | return 1; | |
4022 | ||
6aa8b732 AK |
4023 | return 0; |
4024 | } | |
4025 | ||
102d8325 IM |
4026 | static void |
4027 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
4028 | { | |
4029 | /* | |
4030 | * Patch in the VMMCALL instruction: | |
4031 | */ | |
4032 | hypercall[0] = 0x0f; | |
4033 | hypercall[1] = 0x01; | |
4034 | hypercall[2] = 0xd9; | |
102d8325 IM |
4035 | } |
4036 | ||
002c7f7c YS |
4037 | static void svm_check_processor_compat(void *rtn) |
4038 | { | |
4039 | *(int *)rtn = 0; | |
4040 | } | |
4041 | ||
774ead3a AK |
4042 | static bool svm_cpu_has_accelerated_tpr(void) |
4043 | { | |
4044 | return false; | |
4045 | } | |
4046 | ||
4b12f0de | 4047 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
4048 | { |
4049 | return 0; | |
4050 | } | |
4051 | ||
0e851880 SY |
4052 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
4053 | { | |
4054 | } | |
4055 | ||
d4330ef2 JR |
4056 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
4057 | { | |
c2c63a49 | 4058 | switch (func) { |
4c62a2dc JR |
4059 | case 0x80000001: |
4060 | if (nested) | |
4061 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
4062 | break; | |
c2c63a49 JR |
4063 | case 0x8000000A: |
4064 | entry->eax = 1; /* SVM revision 1 */ | |
4065 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
4066 | ASID emulation to nested SVM */ | |
4067 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
4068 | entry->edx = 0; /* Per default do not support any |
4069 | additional features */ | |
4070 | ||
4071 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 4072 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 4073 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 4074 | |
3d4aeaad JR |
4075 | /* Support NPT for the guest if enabled */ |
4076 | if (npt_enabled) | |
4077 | entry->edx |= SVM_FEATURE_NPT; | |
4078 | ||
c2c63a49 JR |
4079 | break; |
4080 | } | |
d4330ef2 JR |
4081 | } |
4082 | ||
17cc3935 | 4083 | static int svm_get_lpage_level(void) |
344f414f | 4084 | { |
17cc3935 | 4085 | return PT_PDPE_LEVEL; |
344f414f JR |
4086 | } |
4087 | ||
4e47c7a6 SY |
4088 | static bool svm_rdtscp_supported(void) |
4089 | { | |
4090 | return false; | |
4091 | } | |
4092 | ||
ad756a16 MJ |
4093 | static bool svm_invpcid_supported(void) |
4094 | { | |
4095 | return false; | |
4096 | } | |
4097 | ||
93c4adc7 PB |
4098 | static bool svm_mpx_supported(void) |
4099 | { | |
4100 | return false; | |
4101 | } | |
4102 | ||
f5f48ee1 SY |
4103 | static bool svm_has_wbinvd_exit(void) |
4104 | { | |
4105 | return true; | |
4106 | } | |
4107 | ||
02daab21 AK |
4108 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
4109 | { | |
4110 | struct vcpu_svm *svm = to_svm(vcpu); | |
4111 | ||
18c918c5 | 4112 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 4113 | update_cr0_intercept(svm); |
02daab21 AK |
4114 | } |
4115 | ||
8061252e | 4116 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4117 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 4118 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4119 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 4120 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 4121 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 4122 | |
09941fbb | 4123 | static const struct __x86_intercept { |
cfec82cb JR |
4124 | u32 exit_code; |
4125 | enum x86_intercept_stage stage; | |
cfec82cb JR |
4126 | } x86_intercept_map[] = { |
4127 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
4128 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4129 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4130 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4131 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
4132 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
4133 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
4134 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
4135 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
4136 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
4137 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
4138 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
4139 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
4140 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
4141 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
4142 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
4143 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
4144 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
4145 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
4146 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
4147 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
4148 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
4149 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
4150 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
4151 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
4152 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
4153 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
4154 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
4155 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
4156 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
4157 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
4158 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
4159 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
4160 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
4161 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
4162 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
4163 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
4164 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
4165 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
4166 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
4167 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
4168 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
4169 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
4170 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
4171 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
4172 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
4173 | }; |
4174 | ||
8061252e | 4175 | #undef PRE_EX |
cfec82cb | 4176 | #undef POST_EX |
d7eb8203 | 4177 | #undef POST_MEM |
cfec82cb | 4178 | |
8a76d7f2 JR |
4179 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
4180 | struct x86_instruction_info *info, | |
4181 | enum x86_intercept_stage stage) | |
4182 | { | |
cfec82cb JR |
4183 | struct vcpu_svm *svm = to_svm(vcpu); |
4184 | int vmexit, ret = X86EMUL_CONTINUE; | |
4185 | struct __x86_intercept icpt_info; | |
4186 | struct vmcb *vmcb = svm->vmcb; | |
4187 | ||
4188 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
4189 | goto out; | |
4190 | ||
4191 | icpt_info = x86_intercept_map[info->intercept]; | |
4192 | ||
40e19b51 | 4193 | if (stage != icpt_info.stage) |
cfec82cb JR |
4194 | goto out; |
4195 | ||
4196 | switch (icpt_info.exit_code) { | |
4197 | case SVM_EXIT_READ_CR0: | |
4198 | if (info->intercept == x86_intercept_cr_read) | |
4199 | icpt_info.exit_code += info->modrm_reg; | |
4200 | break; | |
4201 | case SVM_EXIT_WRITE_CR0: { | |
4202 | unsigned long cr0, val; | |
4203 | u64 intercept; | |
4204 | ||
4205 | if (info->intercept == x86_intercept_cr_write) | |
4206 | icpt_info.exit_code += info->modrm_reg; | |
4207 | ||
4208 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0) | |
4209 | break; | |
4210 | ||
4211 | intercept = svm->nested.intercept; | |
4212 | ||
4213 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
4214 | break; | |
4215 | ||
4216 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
4217 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
4218 | ||
4219 | if (info->intercept == x86_intercept_lmsw) { | |
4220 | cr0 &= 0xfUL; | |
4221 | val &= 0xfUL; | |
4222 | /* lmsw can't clear PE - catch this here */ | |
4223 | if (cr0 & X86_CR0_PE) | |
4224 | val |= X86_CR0_PE; | |
4225 | } | |
4226 | ||
4227 | if (cr0 ^ val) | |
4228 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
4229 | ||
4230 | break; | |
4231 | } | |
3b88e41a JR |
4232 | case SVM_EXIT_READ_DR0: |
4233 | case SVM_EXIT_WRITE_DR0: | |
4234 | icpt_info.exit_code += info->modrm_reg; | |
4235 | break; | |
8061252e JR |
4236 | case SVM_EXIT_MSR: |
4237 | if (info->intercept == x86_intercept_wrmsr) | |
4238 | vmcb->control.exit_info_1 = 1; | |
4239 | else | |
4240 | vmcb->control.exit_info_1 = 0; | |
4241 | break; | |
bf608f88 JR |
4242 | case SVM_EXIT_PAUSE: |
4243 | /* | |
4244 | * We get this for NOP only, but pause | |
4245 | * is rep not, check this here | |
4246 | */ | |
4247 | if (info->rep_prefix != REPE_PREFIX) | |
4248 | goto out; | |
f6511935 JR |
4249 | case SVM_EXIT_IOIO: { |
4250 | u64 exit_info; | |
4251 | u32 bytes; | |
4252 | ||
4253 | exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16; | |
4254 | ||
4255 | if (info->intercept == x86_intercept_in || | |
4256 | info->intercept == x86_intercept_ins) { | |
4257 | exit_info |= SVM_IOIO_TYPE_MASK; | |
4258 | bytes = info->src_bytes; | |
4259 | } else { | |
4260 | bytes = info->dst_bytes; | |
4261 | } | |
4262 | ||
4263 | if (info->intercept == x86_intercept_outs || | |
4264 | info->intercept == x86_intercept_ins) | |
4265 | exit_info |= SVM_IOIO_STR_MASK; | |
4266 | ||
4267 | if (info->rep_prefix) | |
4268 | exit_info |= SVM_IOIO_REP_MASK; | |
4269 | ||
4270 | bytes = min(bytes, 4u); | |
4271 | ||
4272 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
4273 | ||
4274 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
4275 | ||
4276 | vmcb->control.exit_info_1 = exit_info; | |
4277 | vmcb->control.exit_info_2 = info->next_rip; | |
4278 | ||
4279 | break; | |
4280 | } | |
cfec82cb JR |
4281 | default: |
4282 | break; | |
4283 | } | |
4284 | ||
4285 | vmcb->control.next_rip = info->next_rip; | |
4286 | vmcb->control.exit_code = icpt_info.exit_code; | |
4287 | vmexit = nested_svm_exit_handled(svm); | |
4288 | ||
4289 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
4290 | : X86EMUL_CONTINUE; | |
4291 | ||
4292 | out: | |
4293 | return ret; | |
8a76d7f2 JR |
4294 | } |
4295 | ||
a547c6db YZ |
4296 | static void svm_handle_external_intr(struct kvm_vcpu *vcpu) |
4297 | { | |
4298 | local_irq_enable(); | |
4299 | } | |
4300 | ||
cbdd1bea | 4301 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
4302 | .cpu_has_kvm_support = has_svm, |
4303 | .disabled_by_bios = is_disabled, | |
4304 | .hardware_setup = svm_hardware_setup, | |
4305 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 4306 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
4307 | .hardware_enable = svm_hardware_enable, |
4308 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 4309 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
4310 | |
4311 | .vcpu_create = svm_create_vcpu, | |
4312 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 4313 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 4314 | |
04d2cc77 | 4315 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
4316 | .vcpu_load = svm_vcpu_load, |
4317 | .vcpu_put = svm_vcpu_put, | |
4318 | ||
c8639010 | 4319 | .update_db_bp_intercept = update_db_bp_intercept, |
6aa8b732 AK |
4320 | .get_msr = svm_get_msr, |
4321 | .set_msr = svm_set_msr, | |
4322 | .get_segment_base = svm_get_segment_base, | |
4323 | .get_segment = svm_get_segment, | |
4324 | .set_segment = svm_set_segment, | |
2e4d2653 | 4325 | .get_cpl = svm_get_cpl, |
1747fb71 | 4326 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 4327 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 4328 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 4329 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 4330 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
4331 | .set_cr3 = svm_set_cr3, |
4332 | .set_cr4 = svm_set_cr4, | |
4333 | .set_efer = svm_set_efer, | |
4334 | .get_idt = svm_get_idt, | |
4335 | .set_idt = svm_set_idt, | |
4336 | .get_gdt = svm_get_gdt, | |
4337 | .set_gdt = svm_set_gdt, | |
73aaf249 JK |
4338 | .get_dr6 = svm_get_dr6, |
4339 | .set_dr6 = svm_set_dr6, | |
020df079 | 4340 | .set_dr7 = svm_set_dr7, |
facb0139 | 4341 | .sync_dirty_debug_regs = svm_sync_dirty_debug_regs, |
6de4f3ad | 4342 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
4343 | .get_rflags = svm_get_rflags, |
4344 | .set_rflags = svm_set_rflags, | |
6b52d186 | 4345 | .fpu_activate = svm_fpu_activate, |
02daab21 | 4346 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 4347 | |
6aa8b732 | 4348 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 4349 | |
6aa8b732 | 4350 | .run = svm_vcpu_run, |
04d2cc77 | 4351 | .handle_exit = handle_exit, |
6aa8b732 | 4352 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4353 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
4354 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 4355 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 4356 | .set_irq = svm_set_irq, |
95ba8273 | 4357 | .set_nmi = svm_inject_nmi, |
298101da | 4358 | .queue_exception = svm_queue_exception, |
b463a6f7 | 4359 | .cancel_injection = svm_cancel_injection, |
78646121 | 4360 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 4361 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
4362 | .get_nmi_mask = svm_get_nmi_mask, |
4363 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
4364 | .enable_nmi_window = enable_nmi_window, |
4365 | .enable_irq_window = enable_irq_window, | |
4366 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 4367 | .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode, |
c7c9c56c YZ |
4368 | .vm_has_apicv = svm_vm_has_apicv, |
4369 | .load_eoi_exitmap = svm_load_eoi_exitmap, | |
4370 | .hwapic_isr_update = svm_hwapic_isr_update, | |
a20ed54d | 4371 | .sync_pir_to_irr = svm_sync_pir_to_irr, |
cbc94022 IE |
4372 | |
4373 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 4374 | .get_tdp_level = get_npt_level, |
4b12f0de | 4375 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 4376 | |
586f9607 | 4377 | .get_exit_info = svm_get_exit_info, |
586f9607 | 4378 | |
17cc3935 | 4379 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
4380 | |
4381 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
4382 | |
4383 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 4384 | .invpcid_supported = svm_invpcid_supported, |
93c4adc7 | 4385 | .mpx_supported = svm_mpx_supported, |
d4330ef2 JR |
4386 | |
4387 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
4388 | |
4389 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a | 4390 | |
4051b188 | 4391 | .set_tsc_khz = svm_set_tsc_khz, |
ba904635 | 4392 | .read_tsc_offset = svm_read_tsc_offset, |
99e3e30a | 4393 | .write_tsc_offset = svm_write_tsc_offset, |
e48672fa | 4394 | .adjust_tsc_offset = svm_adjust_tsc_offset, |
857e4099 | 4395 | .compute_tsc_offset = svm_compute_tsc_offset, |
d5c1785d | 4396 | .read_l1_tsc = svm_read_l1_tsc, |
1c97f0a0 JR |
4397 | |
4398 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
4399 | |
4400 | .check_intercept = svm_check_intercept, | |
a547c6db | 4401 | .handle_external_intr = svm_handle_external_intr, |
6aa8b732 AK |
4402 | }; |
4403 | ||
4404 | static int __init svm_init(void) | |
4405 | { | |
cb498ea2 | 4406 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 4407 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
4408 | } |
4409 | ||
4410 | static void __exit svm_exit(void) | |
4411 | { | |
cb498ea2 | 4412 | kvm_exit(); |
6aa8b732 AK |
4413 | } |
4414 | ||
4415 | module_init(svm_init) | |
4416 | module_exit(svm_exit) |