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target-i386: kvm_cpu_fill_host(): No need to check xlevel2
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf
EH		 26#include "sysemu/cpus.h"
27#include "topology.h"
c6dc6f63 28
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
53a89e26 44#include "hw/qdev-properties.h"
62fc403f 45#include "hw/cpu/icc_bus.h"
bdeec802 46#ifndef CONFIG_USER_ONLY
0d09e41a 47#include "hw/xen/xen.h"
0d09e41a 48#include "hw/i386/apic_internal.h"
bdeec802
IM		 49#endif
50
5e891bf8
EH		 51
52/* Cache topology CPUID constants: */
53
54/* CPUID Leaf 2 Descriptors */
55
56#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57#define CPUID_2_L1I_32KB_8WAY_64B 0x30
58#define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61/* CPUID Leaf 4 constants: */
62
63/* EAX: */
64#define CPUID_4_TYPE_DCACHE 1
65#define CPUID_4_TYPE_ICACHE 2
66#define CPUID_4_TYPE_UNIFIED 3
67
68#define CPUID_4_LEVEL(l) ((l) << 5)
69
70#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71#define CPUID_4_FULLY_ASSOC (1 << 9)
72
73/* EDX: */
74#define CPUID_4_NO_INVD_SHARING (1 << 0)
75#define CPUID_4_INCLUSIVE (1 << 1)
76#define CPUID_4_COMPLEX_IDX (1 << 2)
77
78#define ASSOC_FULL 0xFF
79
80/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95/* Definitions of the hardcoded cache entries we expose: */
96
97/* L1 data cache: */
98#define L1D_LINE_SIZE 64
99#define L1D_ASSOCIATIVITY 8
100#define L1D_SETS 64
101#define L1D_PARTITIONS 1
102/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105#define L1D_LINES_PER_TAG 1
106#define L1D_SIZE_KB_AMD 64
107#define L1D_ASSOCIATIVITY_AMD 2
108
109/* L1 instruction cache: */
110#define L1I_LINE_SIZE 64
111#define L1I_ASSOCIATIVITY 8
112#define L1I_SETS 64
113#define L1I_PARTITIONS 1
114/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117#define L1I_LINES_PER_TAG 1
118#define L1I_SIZE_KB_AMD 64
119#define L1I_ASSOCIATIVITY_AMD 2
120
121/* Level 2 unified cache: */
122#define L2_LINE_SIZE 64
123#define L2_ASSOCIATIVITY 16
124#define L2_SETS 4096
125#define L2_PARTITIONS 1
126/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130#define L2_LINES_PER_TAG 1
131#define L2_SIZE_KB_AMD 512
132
133/* No L3 cache: */
134#define L3_SIZE_KB 0 /* disabled */
135#define L3_ASSOCIATIVITY 0 /* disabled */
136#define L3_LINES_PER_TAG 0 /* disabled */
137#define L3_LINE_SIZE 0 /* disabled */
138
139/* TLB definitions: */
140
141#define L1_DTLB_2M_ASSOC 1
142#define L1_DTLB_2M_ENTRIES 255
143#define L1_DTLB_4K_ASSOC 1
144#define L1_DTLB_4K_ENTRIES 255
145
146#define L1_ITLB_2M_ASSOC 1
147#define L1_ITLB_2M_ENTRIES 255
148#define L1_ITLB_4K_ASSOC 1
149#define L1_ITLB_4K_ENTRIES 255
150
151#define L2_DTLB_2M_ASSOC 0 /* disabled */
152#define L2_DTLB_2M_ENTRIES 0 /* disabled */
153#define L2_DTLB_4K_ASSOC 4
154#define L2_DTLB_4K_ENTRIES 512
155
156#define L2_ITLB_2M_ASSOC 0 /* disabled */
157#define L2_ITLB_2M_ENTRIES 0 /* disabled */
158#define L2_ITLB_4K_ASSOC 4
159#define L2_ITLB_4K_ENTRIES 512
160
161
162
99b88a17
IM		 163static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165{
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173}
174
c6dc6f63
AP		 175/* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188};
189static const char *ext_feature_name[] = {
f370be3c 190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 191 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 192 "tm2", "ssse3", "cid", NULL,
e117f772 193 "fma", "cx16", "xtpr", "pdcm",
434acb81 194 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 196 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 197 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 198};
3b671a40
EH		 199/* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
c6dc6f63 204static const char *ext2_feature_name[] = {
3b671a40
EH		 205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 212 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 213};
214static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 217 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 222 NULL, NULL, NULL, NULL,
223};
224
89e49c8b
EH		 225static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234};
235
c6dc6f63 236static const char *kvm_feature_name[] = {
c3d39807 237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 245};
246
296acb64
JR		 247static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256};
257
a9321a4d 258static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263};
264
5ef57876
EH		 265typedef struct FeatureWordInfo {
266 const char **feat_names;
04d104b6
EH		 267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
5ef57876
EH		 271} FeatureWordInfo;
272
273static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
89e49c8b
EH		 290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
bffd67b0
EH		 294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
bffd67b0 307 },
5ef57876
EH		 308};
309
8e8aba50
EH		 310typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315} X86RegisterInfo32;
316
317#define REGISTER(reg) \
318 [R_##reg] = { .name = #reg, .qapi_enum = X86_C_P_U_REGISTER32_##reg }
319X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328};
329#undef REGISTER
330
2560f19f
PB		 331typedef struct ExtSaveArea {
332 uint32_t feature, bits;
333 uint32_t offset, size;
334} ExtSaveArea;
335
336static const ExtSaveArea ext_save_areas[] = {
337 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 338 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 339 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
340 .offset = 0x3c0, .size = 0x40 },
341 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
342 .offset = 0x400, .size = 0x10 },
2560f19f 343};
8e8aba50 344
8b4beddc
EH		 345const char *get_register_name_32(unsigned int reg)
346{
31ccdde2 347 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 348 return NULL;
349 }
8e8aba50 350 return x86_reg_info_32[reg].name;
8b4beddc
EH		 351}
352
c6dc6f63
AP		 353/* collects per-function cpuid data
354 */
355typedef struct model_features_t {
356 uint32_t *guest_feat;
357 uint32_t *host_feat;
bffd67b0 358 FeatureWord feat_word;
8b4beddc 359} model_features_t;
c6dc6f63 360
dc59944b
MT		 361static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
362 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 363 (1 << KVM_FEATURE_CLOCKSOURCE2) |
364 (1 << KVM_FEATURE_ASYNC_PF) |
365 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 366 (1 << KVM_FEATURE_PV_EOI) |
dc59944b 367 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
dc59944b 368
29694758 369void disable_kvm_pv_eoi(void)
dc59944b 370{
29694758 371 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
dc59944b
MT		 372}
373
bb44e0d1
JK		 374void host_cpuid(uint32_t function, uint32_t count,
375 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 376{
377#if defined(CONFIG_KVM)
a1fd24af
AL		 378 uint32_t vec[4];
379
380#ifdef __x86_64__
381 asm volatile("cpuid"
382 : "=a"(vec[0]), "=b"(vec[1]),
383 "=c"(vec[2]), "=d"(vec[3])
384 : "0"(function), "c"(count) : "cc");
385#else
386 asm volatile("pusha \n\t"
387 "cpuid \n\t"
388 "mov %%eax, 0(%2) \n\t"
389 "mov %%ebx, 4(%2) \n\t"
390 "mov %%ecx, 8(%2) \n\t"
391 "mov %%edx, 12(%2) \n\t"
392 "popa"
393 : : "a"(function), "c"(count), "S"(vec)
394 : "memory", "cc");
395#endif
396
bdde476a 397 if (eax)
a1fd24af 398 *eax = vec[0];
bdde476a 399 if (ebx)
a1fd24af 400 *ebx = vec[1];
bdde476a 401 if (ecx)
a1fd24af 402 *ecx = vec[2];
bdde476a 403 if (edx)
a1fd24af 404 *edx = vec[3];
bdde476a
AP		 405#endif
406}
c6dc6f63
AP		 407
408#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
409
410/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
411 * a substring. ex if !NULL points to the first char after a substring,
412 * otherwise the string is assumed to sized by a terminating nul.
413 * Return lexical ordering of *s1:*s2.
414 */
415static int sstrcmp(const char *s1, const char *e1, const char *s2,
416 const char *e2)
417{
418 for (;;) {
419 if (!*s1 || !*s2 || *s1 != *s2)
420 return (*s1 - *s2);
421 ++s1, ++s2;
422 if (s1 == e1 && s2 == e2)
423 return (0);
424 else if (s1 == e1)
425 return (*s2);
426 else if (s2 == e2)
427 return (*s1);
428 }
429}
430
431/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
432 * '|' delimited (possibly empty) strings in which case search for a match
433 * within the alternatives proceeds left to right. Return 0 for success,
434 * non-zero otherwise.
435 */
436static int altcmp(const char *s, const char *e, const char *altstr)
437{
438 const char *p, *q;
439
440 for (q = p = altstr; ; ) {
441 while (*p && *p != '|')
442 ++p;
443 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
444 return (0);
445 if (!*p)
446 return (1);
447 else
448 q = ++p;
449 }
450}
451
452/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 453 * *pval and return true, otherwise return false
c6dc6f63 454 */
e41e0fc6
JK		 455static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
456 const char **featureset)
c6dc6f63
AP		 457{
458 uint32_t mask;
459 const char **ppc;
e41e0fc6 460 bool found = false;
c6dc6f63 461
e41e0fc6 462 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 463 if (*ppc && !altcmp(s, e, *ppc)) {
464 *pval |= mask;
e41e0fc6 465 found = true;
c6dc6f63 466 }
e41e0fc6
JK		 467 }
468 return found;
c6dc6f63
AP		 469}
470
5ef57876
EH		 471static void add_flagname_to_bitmaps(const char *flagname,
472 FeatureWordArray words)
c6dc6f63 473{
5ef57876
EH		 474 FeatureWord w;
475 for (w = 0; w < FEATURE_WORDS; w++) {
476 FeatureWordInfo *wi = &feature_word_info[w];
477 if (wi->feat_names &&
478 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
479 break;
480 }
481 }
482 if (w == FEATURE_WORDS) {
483 fprintf(stderr, "CPU feature %s not found\n", flagname);
484 }
c6dc6f63
AP		 485}
486
487typedef struct x86_def_t {
c6dc6f63
AP		 488 const char *name;
489 uint32_t level;
90e4b0c3
EH		 490 uint32_t xlevel;
491 uint32_t xlevel2;
99b88a17
IM		 492 /* vendor is zero-terminated, 12 character ASCII string */
493 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 494 int family;
495 int model;
496 int stepping;
0514ef2f 497 FeatureWordArray features;
c6dc6f63 498 char model_id[48];
787aaf57 499 bool cache_info_passthrough;
c6dc6f63
AP		 500} x86_def_t;
501
502#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
503#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
504 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
505#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
506 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
507 CPUID_PSE36 | CPUID_FXSR)
508#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
509#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
510 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
511 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
512 CPUID_PAE | CPUID_SEP | CPUID_APIC)
513
551a2dec
AP		 514#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
515 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
516 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
517 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
518 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 519 /* partly implemented:
520 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
521 CPUID_PSE36 (needed for Solaris) */
522 /* missing:
523 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
e71827bc
AJ		 524#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
525 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
526 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
d640045a 527 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
8560efed 528 /* missing:
e71827bc
AJ		 529 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
530 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
531 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
d640045a
AJ		 532 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
533 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
83f7dc28 534 CPUID_EXT_RDRAND */
60032ac0 535#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 536 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
537 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 538 /* missing:
539 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 540#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
541 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 542#define TCG_SVM_FEATURES 0
7073fbad 543#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
cd7f97ca 544 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
111994ee 545 /* missing:
7073fbad
RH		 546 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
547 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
cd7f97ca 548 CPUID_7_0_EBX_RDSEED */
551a2dec 549
7fc9b714 550/* built-in CPU model definitions
c6dc6f63
AP		 551 */
552static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 553 {
554 .name = "qemu64",
555 .level = 4,
99b88a17 556 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 557 .family = 6,
f8e6a11a 558 .model = 6,
c6dc6f63 559 .stepping = 3,
0514ef2f 560 .features[FEAT_1_EDX] =
27861ecc 561 PPRO_FEATURES |
c6dc6f63 562 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 563 CPUID_PSE36,
0514ef2f 564 .features[FEAT_1_ECX] =
27861ecc 565 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 566 .features[FEAT_8000_0001_EDX] =
27861ecc 567 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 568 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 569 .features[FEAT_8000_0001_ECX] =
27861ecc 570 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 571 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
572 .xlevel = 0x8000000A,
c6dc6f63
AP		 573 },
574 {
575 .name = "phenom",
576 .level = 5,
99b88a17 577 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 578 .family = 16,
579 .model = 2,
580 .stepping = 3,
0514ef2f 581 .features[FEAT_1_EDX] =
27861ecc 582 PPRO_FEATURES |
c6dc6f63 583 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 584 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 585 .features[FEAT_1_ECX] =
27861ecc 586 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 587 CPUID_EXT_POPCNT,
0514ef2f 588 .features[FEAT_8000_0001_EDX] =
27861ecc 589 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 590 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
591 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 592 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 593 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
594 CPUID_EXT3_CR8LEG,
595 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
596 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 597 .features[FEAT_8000_0001_ECX] =
27861ecc 598 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 599 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 600 .features[FEAT_SVM] =
27861ecc 601 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 602 .xlevel = 0x8000001A,
603 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
604 },
605 {
606 .name = "core2duo",
607 .level = 10,
99b88a17 608 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 609 .family = 6,
610 .model = 15,
611 .stepping = 11,
0514ef2f 612 .features[FEAT_1_EDX] =
27861ecc 613 PPRO_FEATURES |
c6dc6f63 614 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 615 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
616 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 617 .features[FEAT_1_ECX] =
27861ecc 618 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 619 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
620 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 621 .features[FEAT_8000_0001_EDX] =
27861ecc 622 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 623 .features[FEAT_8000_0001_ECX] =
27861ecc 624 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 625 .xlevel = 0x80000008,
626 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
627 },
628 {
629 .name = "kvm64",
630 .level = 5,
99b88a17 631 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 632 .family = 15,
633 .model = 6,
634 .stepping = 1,
635 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 636 .features[FEAT_1_EDX] =
27861ecc 637 PPRO_FEATURES |
c6dc6f63
AP		 638 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
639 CPUID_PSE36,
640 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 641 .features[FEAT_1_ECX] =
27861ecc 642 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 643 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 644 .features[FEAT_8000_0001_EDX] =
27861ecc 645 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 646 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
647 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
648 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
649 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
650 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 651 .features[FEAT_8000_0001_ECX] =
27861ecc 652 0,
c6dc6f63
AP		 653 .xlevel = 0x80000008,
654 .model_id = "Common KVM processor"
655 },
c6dc6f63
AP		 656 {
657 .name = "qemu32",
658 .level = 4,
99b88a17 659 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 660 .family = 6,
f8e6a11a 661 .model = 6,
c6dc6f63 662 .stepping = 3,
0514ef2f 663 .features[FEAT_1_EDX] =
27861ecc 664 PPRO_FEATURES,
0514ef2f 665 .features[FEAT_1_ECX] =
27861ecc 666 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 667 .xlevel = 0x80000004,
c6dc6f63 668 },
eafaf1e5
AP		 669 {
670 .name = "kvm32",
671 .level = 5,
99b88a17 672 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 673 .family = 15,
674 .model = 6,
675 .stepping = 1,
0514ef2f 676 .features[FEAT_1_EDX] =
27861ecc 677 PPRO_FEATURES |
eafaf1e5 678 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 679 .features[FEAT_1_ECX] =
27861ecc 680 CPUID_EXT_SSE3,
0514ef2f 681 .features[FEAT_8000_0001_EDX] =
27861ecc 682 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 683 .features[FEAT_8000_0001_ECX] =
27861ecc 684 0,
eafaf1e5
AP		 685 .xlevel = 0x80000008,
686 .model_id = "Common 32-bit KVM processor"
687 },
c6dc6f63
AP		 688 {
689 .name = "coreduo",
690 .level = 10,
99b88a17 691 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 692 .family = 6,
693 .model = 14,
694 .stepping = 8,
0514ef2f 695 .features[FEAT_1_EDX] =
27861ecc 696 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 697 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
698 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 699 .features[FEAT_1_ECX] =
27861ecc 700 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 701 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 702 .features[FEAT_8000_0001_EDX] =
27861ecc 703 CPUID_EXT2_NX,
c6dc6f63
AP		 704 .xlevel = 0x80000008,
705 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
706 },
707 {
708 .name = "486",
58012d66 709 .level = 1,
99b88a17 710 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 711 .family = 4,
b2a856d9 712 .model = 8,
c6dc6f63 713 .stepping = 0,
0514ef2f 714 .features[FEAT_1_EDX] =
27861ecc 715 I486_FEATURES,
c6dc6f63
AP		 716 .xlevel = 0,
717 },
718 {
719 .name = "pentium",
720 .level = 1,
99b88a17 721 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 722 .family = 5,
723 .model = 4,
724 .stepping = 3,
0514ef2f 725 .features[FEAT_1_EDX] =
27861ecc 726 PENTIUM_FEATURES,
c6dc6f63
AP		 727 .xlevel = 0,
728 },
729 {
730 .name = "pentium2",
731 .level = 2,
99b88a17 732 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 733 .family = 6,
734 .model = 5,
735 .stepping = 2,
0514ef2f 736 .features[FEAT_1_EDX] =
27861ecc 737 PENTIUM2_FEATURES,
c6dc6f63
AP		 738 .xlevel = 0,
739 },
740 {
741 .name = "pentium3",
742 .level = 2,
99b88a17 743 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 744 .family = 6,
745 .model = 7,
746 .stepping = 3,
0514ef2f 747 .features[FEAT_1_EDX] =
27861ecc 748 PENTIUM3_FEATURES,
c6dc6f63
AP		 749 .xlevel = 0,
750 },
751 {
752 .name = "athlon",
753 .level = 2,
99b88a17 754 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 755 .family = 6,
756 .model = 2,
757 .stepping = 3,
0514ef2f 758 .features[FEAT_1_EDX] =
27861ecc 759 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 760 CPUID_MCA,
0514ef2f 761 .features[FEAT_8000_0001_EDX] =
27861ecc 762 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 763 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 764 .xlevel = 0x80000008,
c6dc6f63
AP		 765 },
766 {
767 .name = "n270",
768 /* original is on level 10 */
769 .level = 5,
99b88a17 770 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 771 .family = 6,
772 .model = 28,
773 .stepping = 2,
0514ef2f 774 .features[FEAT_1_EDX] =
27861ecc 775 PPRO_FEATURES |
8560efed
AJ		 776 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
777 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 778 /* Some CPUs got no CPUID_SEP */
0514ef2f 779 .features[FEAT_1_ECX] =
27861ecc 780 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 781 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
782 CPUID_EXT_MOVBE,
0514ef2f 783 .features[FEAT_8000_0001_EDX] =
27861ecc 784 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 785 CPUID_EXT2_NX,
0514ef2f 786 .features[FEAT_8000_0001_ECX] =
27861ecc 787 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 788 .xlevel = 0x8000000A,
789 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
790 },
3eca4642
EH		 791 {
792 .name = "Conroe",
6b11322e 793 .level = 4,
99b88a17 794 .vendor = CPUID_VENDOR_INTEL,
3eca4642 795 .family = 6,
ffce9ebb 796 .model = 15,
3eca4642 797 .stepping = 3,
0514ef2f 798 .features[FEAT_1_EDX] =
27861ecc 799 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 800 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
801 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
802 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
803 CPUID_DE | CPUID_FP87,
0514ef2f 804 .features[FEAT_1_ECX] =
27861ecc 805 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 806 .features[FEAT_8000_0001_EDX] =
27861ecc 807 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 808 .features[FEAT_8000_0001_ECX] =
27861ecc 809 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 810 .xlevel = 0x8000000A,
811 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
812 },
813 {
814 .name = "Penryn",
6b11322e 815 .level = 4,
99b88a17 816 .vendor = CPUID_VENDOR_INTEL,
3eca4642 817 .family = 6,
ffce9ebb 818 .model = 23,
3eca4642 819 .stepping = 3,
0514ef2f 820 .features[FEAT_1_EDX] =
27861ecc 821 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 822 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
823 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
824 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
825 CPUID_DE | CPUID_FP87,
0514ef2f 826 .features[FEAT_1_ECX] =
27861ecc 827 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 828 CPUID_EXT_SSE3,
0514ef2f 829 .features[FEAT_8000_0001_EDX] =
27861ecc 830 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 831 .features[FEAT_8000_0001_ECX] =
27861ecc 832 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 833 .xlevel = 0x8000000A,
834 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
835 },
836 {
837 .name = "Nehalem",
6b11322e 838 .level = 4,
99b88a17 839 .vendor = CPUID_VENDOR_INTEL,
3eca4642 840 .family = 6,
ffce9ebb 841 .model = 26,
3eca4642 842 .stepping = 3,
0514ef2f 843 .features[FEAT_1_EDX] =
27861ecc 844 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 845 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
846 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
847 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
848 CPUID_DE | CPUID_FP87,
0514ef2f 849 .features[FEAT_1_ECX] =
27861ecc 850 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 851 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 852 .features[FEAT_8000_0001_EDX] =
27861ecc 853 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 854 .features[FEAT_8000_0001_ECX] =
27861ecc 855 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 856 .xlevel = 0x8000000A,
857 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
858 },
859 {
860 .name = "Westmere",
861 .level = 11,
99b88a17 862 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 863 .family = 6,
864 .model = 44,
865 .stepping = 1,
0514ef2f 866 .features[FEAT_1_EDX] =
27861ecc 867 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 868 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
869 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
870 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
871 CPUID_DE | CPUID_FP87,
0514ef2f 872 .features[FEAT_1_ECX] =
27861ecc 873 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 874 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 875 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 876 .features[FEAT_8000_0001_EDX] =
27861ecc 877 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 878 .features[FEAT_8000_0001_ECX] =
27861ecc 879 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 880 .xlevel = 0x8000000A,
881 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
882 },
883 {
884 .name = "SandyBridge",
885 .level = 0xd,
99b88a17 886 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 887 .family = 6,
888 .model = 42,
889 .stepping = 1,
0514ef2f 890 .features[FEAT_1_EDX] =
27861ecc 891 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 892 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
893 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
894 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
895 CPUID_DE | CPUID_FP87,
0514ef2f 896 .features[FEAT_1_ECX] =
27861ecc 897 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 898 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
899 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
900 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
901 CPUID_EXT_SSE3,
0514ef2f 902 .features[FEAT_8000_0001_EDX] =
27861ecc 903 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 904 CPUID_EXT2_SYSCALL,
0514ef2f 905 .features[FEAT_8000_0001_ECX] =
27861ecc 906 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 907 .xlevel = 0x8000000A,
908 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
909 },
37507094
EH		 910 {
911 .name = "Haswell",
912 .level = 0xd,
99b88a17 913 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 914 .family = 6,
915 .model = 60,
916 .stepping = 1,
0514ef2f 917 .features[FEAT_1_EDX] =
27861ecc 918 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 919 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 920 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 921 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
922 CPUID_DE | CPUID_FP87,
0514ef2f 923 .features[FEAT_1_ECX] =
27861ecc 924 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH		 925 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
926 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
927 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
928 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
929 CPUID_EXT_PCID,
0514ef2f 930 .features[FEAT_8000_0001_EDX] =
27861ecc 931 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 932 CPUID_EXT2_SYSCALL,
0514ef2f 933 .features[FEAT_8000_0001_ECX] =
27861ecc 934 CPUID_EXT3_LAHF_LM,
0514ef2f 935 .features[FEAT_7_0_EBX] =
27861ecc 936 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 937 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
938 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
939 CPUID_7_0_EBX_RTM,
940 .xlevel = 0x8000000A,
941 .model_id = "Intel Core Processor (Haswell)",
942 },
3eca4642
EH		 943 {
944 .name = "Opteron_G1",
945 .level = 5,
99b88a17 946 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 947 .family = 15,
948 .model = 6,
949 .stepping = 1,
0514ef2f 950 .features[FEAT_1_EDX] =
27861ecc 951 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 952 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
953 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
954 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
955 CPUID_DE | CPUID_FP87,
0514ef2f 956 .features[FEAT_1_ECX] =
27861ecc 957 CPUID_EXT_SSE3,
0514ef2f 958 .features[FEAT_8000_0001_EDX] =
27861ecc 959 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH		 960 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
961 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
962 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
963 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
964 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
965 .xlevel = 0x80000008,
966 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
967 },
968 {
969 .name = "Opteron_G2",
970 .level = 5,
99b88a17 971 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 972 .family = 15,
973 .model = 6,
974 .stepping = 1,
0514ef2f 975 .features[FEAT_1_EDX] =
27861ecc 976 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 977 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
978 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
979 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
980 CPUID_DE | CPUID_FP87,
0514ef2f 981 .features[FEAT_1_ECX] =
27861ecc 982 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 983 .features[FEAT_8000_0001_EDX] =
27861ecc 984 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 985 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
986 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
987 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
988 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
989 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
990 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 991 .features[FEAT_8000_0001_ECX] =
27861ecc 992 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 993 .xlevel = 0x80000008,
994 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
995 },
996 {
997 .name = "Opteron_G3",
998 .level = 5,
99b88a17 999 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1000 .family = 15,
1001 .model = 6,
1002 .stepping = 1,
0514ef2f 1003 .features[FEAT_1_EDX] =
27861ecc 1004 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1005 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1006 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1007 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1008 CPUID_DE | CPUID_FP87,
0514ef2f 1009 .features[FEAT_1_ECX] =
27861ecc 1010 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1011 CPUID_EXT_SSE3,
0514ef2f 1012 .features[FEAT_8000_0001_EDX] =
27861ecc 1013 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1014 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1015 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1016 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1017 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1018 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1019 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1020 .features[FEAT_8000_0001_ECX] =
27861ecc 1021 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH		 1022 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1023 .xlevel = 0x80000008,
1024 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1025 },
1026 {
1027 .name = "Opteron_G4",
1028 .level = 0xd,
99b88a17 1029 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1030 .family = 21,
1031 .model = 1,
1032 .stepping = 2,
0514ef2f 1033 .features[FEAT_1_EDX] =
27861ecc 1034 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1035 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1036 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1037 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1038 CPUID_DE | CPUID_FP87,
0514ef2f 1039 .features[FEAT_1_ECX] =
27861ecc 1040 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 1041 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1042 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1043 CPUID_EXT_SSE3,
0514ef2f 1044 .features[FEAT_8000_0001_EDX] =
27861ecc 1045 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH		 1046 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1047 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1048 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1049 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1050 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1051 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1052 .features[FEAT_8000_0001_ECX] =
27861ecc 1053 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH		 1054 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1055 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1056 CPUID_EXT3_LAHF_LM,
1057 .xlevel = 0x8000001A,
1058 .model_id = "AMD Opteron 62xx class CPU",
1059 },
021941b9
AP		 1060 {
1061 .name = "Opteron_G5",
1062 .level = 0xd,
99b88a17 1063 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1064 .family = 21,
1065 .model = 2,
1066 .stepping = 0,
0514ef2f 1067 .features[FEAT_1_EDX] =
27861ecc 1068 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP		 1069 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1070 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1071 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1072 CPUID_DE | CPUID_FP87,
0514ef2f 1073 .features[FEAT_1_ECX] =
27861ecc 1074 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP		 1075 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1076 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1077 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1078 .features[FEAT_8000_0001_EDX] =
27861ecc 1079 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP		 1080 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1081 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1082 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1083 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1084 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1085 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1086 .features[FEAT_8000_0001_ECX] =
27861ecc 1087 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP		 1088 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1089 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1090 CPUID_EXT3_LAHF_LM,
1091 .xlevel = 0x8000001A,
1092 .model_id = "AMD Opteron 63xx class CPU",
1093 },
c6dc6f63
AP		 1094};
1095
0668af54
EH		 1096/**
1097 * x86_cpu_compat_set_features:
1098 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1099 * @w: Identifies the feature word to be changed.
1100 * @feat_add: Feature bits to be added to feature word
1101 * @feat_remove: Feature bits to be removed from feature word
1102 *
1103 * Change CPU model feature bits for compatibility.
1104 *
1105 * This function may be used by machine-type compatibility functions
1106 * to enable or disable feature bits on specific CPU models.
1107 */
1108void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1109 uint32_t feat_add, uint32_t feat_remove)
1110{
1111 x86_def_t *def;
1112 int i;
1113 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1114 def = &builtin_x86_defs[i];
1115 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1116 def->features[w] |= feat_add;
1117 def->features[w] &= ~feat_remove;
1118 }
1119 }
1120}
1121
e4ab0d6b 1122#ifdef CONFIG_KVM
c6dc6f63
AP		 1123static int cpu_x86_fill_model_id(char *str)
1124{
1125 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1126 int i;
1127
1128 for (i = 0; i < 3; i++) {
1129 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1130 memcpy(str + i * 16 + 0, &eax, 4);
1131 memcpy(str + i * 16 + 4, &ebx, 4);
1132 memcpy(str + i * 16 + 8, &ecx, 4);
1133 memcpy(str + i * 16 + 12, &edx, 4);
1134 }
1135 return 0;
1136}
e4ab0d6b 1137#endif
c6dc6f63 1138
6e746f30
EH		 1139/* Fill a x86_def_t struct with information about the host CPU, and
1140 * the CPU features supported by the host hardware + host kernel
1141 *
1142 * This function may be called only if KVM is enabled.
1143 */
1144static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 1145{
e4ab0d6b 1146#ifdef CONFIG_KVM
12869995 1147 KVMState *s = kvm_state;
c6dc6f63
AP		 1148 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1149
6e746f30
EH		 1150 assert(kvm_enabled());
1151
c6dc6f63 1152 x86_cpu_def->name = "host";
787aaf57 1153 x86_cpu_def->cache_info_passthrough = true;
c6dc6f63 1154 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
99b88a17 1155 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
c6dc6f63
AP		 1156
1157 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1158 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1159 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1160 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 1161
12869995 1162 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
0514ef2f 1163 x86_cpu_def->features[FEAT_1_EDX] =
27861ecc 1164 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
0514ef2f 1165 x86_cpu_def->features[FEAT_1_ECX] =
27861ecc 1166 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 1167
7171a393
EH		 1168 x86_cpu_def->features[FEAT_7_0_EBX] =
1169 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728 1170
12869995 1171 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
0514ef2f 1172 x86_cpu_def->features[FEAT_8000_0001_EDX] =
12869995 1173 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
0514ef2f 1174 x86_cpu_def->features[FEAT_8000_0001_ECX] =
12869995 1175 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 1176
c6dc6f63 1177 cpu_x86_fill_model_id(x86_cpu_def->model_id);
c6dc6f63 1178
b3baa152 1179 /* Call Centaur's CPUID instruction. */
803a9327
EH		 1180 x86_cpu_def->xlevel2 =
1181 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1182 x86_cpu_def->features[FEAT_C000_0001_EDX] =
1183 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
296acb64 1184
fcb93c03 1185 /* Other KVM-specific feature fields: */
0514ef2f 1186 x86_cpu_def->features[FEAT_SVM] =
fcb93c03 1187 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
0514ef2f 1188 x86_cpu_def->features[FEAT_KVM] =
bd004bef 1189 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 1190
e4ab0d6b 1191#endif /* CONFIG_KVM */
c6dc6f63
AP		 1192}
1193
bffd67b0 1194static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 1195{
1196 int i;
1197
1198 for (i = 0; i < 32; ++i)
1199 if (1 << i & mask) {
bffd67b0 1200 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1201 assert(reg);
1202 fprintf(stderr, "warning: host doesn't support requested feature: "
1203 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1204 f->cpuid_eax, reg,
1205 f->feat_names[i] ? "." : "",
1206 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 1207 break;
1208 }
1209 return 0;
1210}
1211
07ca5945
EH		 1212/* Check if all requested cpu flags are making their way to the guest
1213 *
1214 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 1215 *
1216 * This function may be called only if KVM is enabled.
c6dc6f63 1217 */
5ec01c2e 1218static int kvm_check_features_against_host(X86CPU *cpu)
c6dc6f63 1219{
5ec01c2e 1220 CPUX86State *env = &cpu->env;
c6dc6f63
AP		 1221 x86_def_t host_def;
1222 uint32_t mask;
1223 int rv, i;
1224 struct model_features_t ft[] = {
0514ef2f
EH		 1225 {&env->features[FEAT_1_EDX],
1226 &host_def.features[FEAT_1_EDX],
bffd67b0 1227 FEAT_1_EDX },
0514ef2f
EH		 1228 {&env->features[FEAT_1_ECX],
1229 &host_def.features[FEAT_1_ECX],
bffd67b0 1230 FEAT_1_ECX },
0514ef2f
EH		 1231 {&env->features[FEAT_8000_0001_EDX],
1232 &host_def.features[FEAT_8000_0001_EDX],
bffd67b0 1233 FEAT_8000_0001_EDX },
0514ef2f
EH		 1234 {&env->features[FEAT_8000_0001_ECX],
1235 &host_def.features[FEAT_8000_0001_ECX],
bffd67b0 1236 FEAT_8000_0001_ECX },
0514ef2f
EH		 1237 {&env->features[FEAT_C000_0001_EDX],
1238 &host_def.features[FEAT_C000_0001_EDX],
07ca5945 1239 FEAT_C000_0001_EDX },
0514ef2f
EH		 1240 {&env->features[FEAT_7_0_EBX],
1241 &host_def.features[FEAT_7_0_EBX],
07ca5945 1242 FEAT_7_0_EBX },
0514ef2f
EH		 1243 {&env->features[FEAT_SVM],
1244 &host_def.features[FEAT_SVM],
07ca5945 1245 FEAT_SVM },
0514ef2f
EH		 1246 {&env->features[FEAT_KVM],
1247 &host_def.features[FEAT_KVM],
07ca5945 1248 FEAT_KVM },
8b4beddc 1249 };
c6dc6f63 1250
6e746f30
EH		 1251 assert(kvm_enabled());
1252
1253 kvm_cpu_fill_host(&host_def);
bffd67b0
EH		 1254 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1255 FeatureWord w = ft[i].feat_word;
1256 FeatureWordInfo *wi = &feature_word_info[w];
1257 for (mask = 1; mask; mask <<= 1) {
e8beac00 1258 if (*ft[i].guest_feat & mask &&
c6dc6f63 1259 !(*ft[i].host_feat & mask)) {
bffd67b0
EH		 1260 unavailable_host_feature(wi, mask);
1261 rv = 1;
1262 }
1263 }
1264 }
c6dc6f63
AP		 1265 return rv;
1266}
1267
95b8519d
AF		 1268static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1269 const char *name, Error **errp)
1270{
1271 X86CPU *cpu = X86_CPU(obj);
1272 CPUX86State *env = &cpu->env;
1273 int64_t value;
1274
1275 value = (env->cpuid_version >> 8) & 0xf;
1276 if (value == 0xf) {
1277 value += (env->cpuid_version >> 20) & 0xff;
1278 }
1279 visit_type_int(v, &value, name, errp);
1280}
1281
71ad61d3
AF		 1282static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1283 const char *name, Error **errp)
ed5e1ec3 1284{
71ad61d3
AF		 1285 X86CPU *cpu = X86_CPU(obj);
1286 CPUX86State *env = &cpu->env;
1287 const int64_t min = 0;
1288 const int64_t max = 0xff + 0xf;
1289 int64_t value;
1290
1291 visit_type_int(v, &value, name, errp);
1292 if (error_is_set(errp)) {
1293 return;
1294 }
1295 if (value < min || value > max) {
1296 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1297 name ? name : "null", value, min, max);
1298 return;
1299 }
1300
ed5e1ec3 1301 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1302 if (value > 0x0f) {
1303 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1304 } else {
71ad61d3 1305 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1306 }
1307}
1308
67e30c83
AF		 1309static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1310 const char *name, Error **errp)
1311{
1312 X86CPU *cpu = X86_CPU(obj);
1313 CPUX86State *env = &cpu->env;
1314 int64_t value;
1315
1316 value = (env->cpuid_version >> 4) & 0xf;
1317 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1318 visit_type_int(v, &value, name, errp);
1319}
1320
c5291a4f
AF		 1321static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1322 const char *name, Error **errp)
b0704cbd 1323{
c5291a4f
AF		 1324 X86CPU *cpu = X86_CPU(obj);
1325 CPUX86State *env = &cpu->env;
1326 const int64_t min = 0;
1327 const int64_t max = 0xff;
1328 int64_t value;
1329
1330 visit_type_int(v, &value, name, errp);
1331 if (error_is_set(errp)) {
1332 return;
1333 }
1334 if (value < min || value > max) {
1335 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1336 name ? name : "null", value, min, max);
1337 return;
1338 }
1339
b0704cbd 1340 env->cpuid_version &= ~0xf00f0;
c5291a4f 1341 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1342}
1343
35112e41
AF		 1344static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1345 void *opaque, const char *name,
1346 Error **errp)
1347{
1348 X86CPU *cpu = X86_CPU(obj);
1349 CPUX86State *env = &cpu->env;
1350 int64_t value;
1351
1352 value = env->cpuid_version & 0xf;
1353 visit_type_int(v, &value, name, errp);
1354}
1355
036e2222
AF		 1356static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1357 void *opaque, const char *name,
1358 Error **errp)
38c3dc46 1359{
036e2222
AF		 1360 X86CPU *cpu = X86_CPU(obj);
1361 CPUX86State *env = &cpu->env;
1362 const int64_t min = 0;
1363 const int64_t max = 0xf;
1364 int64_t value;
1365
1366 visit_type_int(v, &value, name, errp);
1367 if (error_is_set(errp)) {
1368 return;
1369 }
1370 if (value < min || value > max) {
1371 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1372 name ? name : "null", value, min, max);
1373 return;
1374 }
1375
38c3dc46 1376 env->cpuid_version &= ~0xf;
036e2222 1377 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1378}
1379
8e1898bf
AF		 1380static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1381 const char *name, Error **errp)
1382{
1383 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1384
fa029887 1385 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1386}
1387
1388static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1389 const char *name, Error **errp)
1390{
1391 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1392
fa029887 1393 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1394}
1395
16b93aa8
AF		 1396static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1397 const char *name, Error **errp)
1398{
1399 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1400
fa029887 1401 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1402}
1403
1404static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1405 const char *name, Error **errp)
1406{
1407 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1408
fa029887 1409 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1410}
1411
d480e1af
AF		 1412static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1413{
1414 X86CPU *cpu = X86_CPU(obj);
1415 CPUX86State *env = &cpu->env;
1416 char *value;
d480e1af 1417
9df694ee 1418 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1419 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1420 env->cpuid_vendor3);
d480e1af
AF		 1421 return value;
1422}
1423
1424static void x86_cpuid_set_vendor(Object *obj, const char *value,
1425 Error **errp)
1426{
1427 X86CPU *cpu = X86_CPU(obj);
1428 CPUX86State *env = &cpu->env;
1429 int i;
1430
9df694ee 1431 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1432 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1433 "vendor", value);
1434 return;
1435 }
1436
1437 env->cpuid_vendor1 = 0;
1438 env->cpuid_vendor2 = 0;
1439 env->cpuid_vendor3 = 0;
1440 for (i = 0; i < 4; i++) {
1441 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1442 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1443 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1444 }
d480e1af
AF		 1445}
1446
63e886eb
AF		 1447static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1448{
1449 X86CPU *cpu = X86_CPU(obj);
1450 CPUX86State *env = &cpu->env;
1451 char *value;
1452 int i;
1453
1454 value = g_malloc(48 + 1);
1455 for (i = 0; i < 48; i++) {
1456 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1457 }
1458 value[48] = '\0';
1459 return value;
1460}
1461
938d4c25
AF		 1462static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1463 Error **errp)
dcce6675 1464{
938d4c25
AF		 1465 X86CPU *cpu = X86_CPU(obj);
1466 CPUX86State *env = &cpu->env;
dcce6675
AF		 1467 int c, len, i;
1468
1469 if (model_id == NULL) {
1470 model_id = "";
1471 }
1472 len = strlen(model_id);
d0a6acf4 1473 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1474 for (i = 0; i < 48; i++) {
1475 if (i >= len) {
1476 c = '\0';
1477 } else {
1478 c = (uint8_t)model_id[i];
1479 }
1480 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1481 }
1482}
1483
89e48965
AF		 1484static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1485 const char *name, Error **errp)
1486{
1487 X86CPU *cpu = X86_CPU(obj);
1488 int64_t value;
1489
1490 value = cpu->env.tsc_khz * 1000;
1491 visit_type_int(v, &value, name, errp);
1492}
1493
1494static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1495 const char *name, Error **errp)
1496{
1497 X86CPU *cpu = X86_CPU(obj);
1498 const int64_t min = 0;
2e84849a 1499 const int64_t max = INT64_MAX;
89e48965
AF		 1500 int64_t value;
1501
1502 visit_type_int(v, &value, name, errp);
1503 if (error_is_set(errp)) {
1504 return;
1505 }
1506 if (value < min || value > max) {
1507 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1508 name ? name : "null", value, min, max);
1509 return;
1510 }
1511
1512 cpu->env.tsc_khz = value / 1000;
1513}
1514
31050930
IM		 1515static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1516 const char *name, Error **errp)
1517{
1518 X86CPU *cpu = X86_CPU(obj);
1519 int64_t value = cpu->env.cpuid_apic_id;
1520
1521 visit_type_int(v, &value, name, errp);
1522}
1523
1524static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1525 const char *name, Error **errp)
1526{
1527 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1528 DeviceState *dev = DEVICE(obj);
31050930
IM		 1529 const int64_t min = 0;
1530 const int64_t max = UINT32_MAX;
1531 Error *error = NULL;
1532 int64_t value;
1533
8d6d4980
IM		 1534 if (dev->realized) {
1535 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1536 "it was realized", name, object_get_typename(obj));
1537 return;
1538 }
1539
31050930
IM		 1540 visit_type_int(v, &value, name, &error);
1541 if (error) {
1542 error_propagate(errp, error);
1543 return;
1544 }
1545 if (value < min || value > max) {
1546 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1547 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1548 object_get_typename(obj), name, value, min, max);
1549 return;
1550 }
1551
1552 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1553 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1554 return;
1555 }
1556 cpu->env.cpuid_apic_id = value;
1557}
1558
7e5292b5 1559/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1560static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1561 const char *name, Error **errp)
1562{
7e5292b5 1563 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1564 FeatureWord w;
1565 Error *err = NULL;
1566 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1567 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1568 X86CPUFeatureWordInfoList *list = NULL;
1569
1570 for (w = 0; w < FEATURE_WORDS; w++) {
1571 FeatureWordInfo *wi = &feature_word_info[w];
1572 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1573 qwi->cpuid_input_eax = wi->cpuid_eax;
1574 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1575 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1576 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1577 qwi->features = array[w];
8e8aba50
EH		 1578
1579 /* List will be in reverse order, but order shouldn't matter */
1580 list_entries[w].next = list;
1581 list_entries[w].value = &word_infos[w];
1582 list = &list_entries[w];
1583 }
1584
1585 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1586 error_propagate(errp, err);
1587}
1588
c8f0f88e
IM		 1589static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1590 const char *name, Error **errp)
1591{
1592 X86CPU *cpu = X86_CPU(obj);
1593 int64_t value = cpu->hyperv_spinlock_attempts;
1594
1595 visit_type_int(v, &value, name, errp);
1596}
1597
1598static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1599 const char *name, Error **errp)
1600{
1601 const int64_t min = 0xFFF;
1602 const int64_t max = UINT_MAX;
1603 X86CPU *cpu = X86_CPU(obj);
1604 Error *err = NULL;
1605 int64_t value;
1606
1607 visit_type_int(v, &value, name, &err);
1608 if (err) {
1609 error_propagate(errp, err);
1610 return;
1611 }
1612
1613 if (value < min || value > max) {
1614 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1615 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1616 object_get_typename(obj), name ? name : "null",
1617 value, min, max);
1618 return;
1619 }
1620 cpu->hyperv_spinlock_attempts = value;
1621}
1622
1623static PropertyInfo qdev_prop_spinlocks = {
1624 .name = "int",
1625 .get = x86_get_hv_spinlocks,
1626 .set = x86_set_hv_spinlocks,
1627};
1628
c1399112
EH		 1629static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def,
1630 const char *name)
c6dc6f63 1631{
c6dc6f63 1632 x86_def_t *def;
7fc9b714 1633 int i;
c6dc6f63 1634
4bfe910d
AF		 1635 if (name == NULL) {
1636 return -1;
9f3fb565 1637 }
4bfe910d 1638 if (kvm_enabled() && strcmp(name, "host") == 0) {
6e746f30 1639 kvm_cpu_fill_host(x86_cpu_def);
00b81053 1640 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
4bfe910d 1641 return 0;
c6dc6f63
AP		 1642 }
1643
7fc9b714
AF		 1644 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1645 def = &builtin_x86_defs[i];
4bfe910d
AF		 1646 if (strcmp(name, def->name) == 0) {
1647 memcpy(x86_cpu_def, def, sizeof(*def));
11acfdd5
IM		 1648 /* sysenter isn't supported in compatibility mode on AMD,
1649 * syscall isn't supported in compatibility mode on Intel.
1650 * Normally we advertise the actual CPU vendor, but you can
1651 * override this using the 'vendor' property if you want to use
1652 * KVM's sysenter/syscall emulation in compatibility mode and
1653 * when doing cross vendor migration
1654 */
1655 if (kvm_enabled()) {
1656 uint32_t ebx = 0, ecx = 0, edx = 0;
1657 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1658 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1659 }
4bfe910d
AF		 1660 return 0;
1661 }
1662 }
1663
1664 return -1;
8f961357
EH		 1665}
1666
72ac2e87
IM		 1667/* Convert all '_' in a feature string option name to '-', to make feature
1668 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1669 */
1670static inline void feat2prop(char *s)
1671{
1672 while ((s = strchr(s, '_'))) {
1673 *s = '-';
1674 }
1675}
1676
8f961357
EH		 1677/* Parse "+feature,-feature,feature=foo" CPU feature string
1678 */
a91987c2 1679static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
8f961357 1680{
8f961357
EH		 1681 char *featurestr; /* Single 'key=value" string being parsed */
1682 /* Features to be added */
077c68c3 1683 FeatureWordArray plus_features = { 0 };
8f961357 1684 /* Features to be removed */
5ef57876 1685 FeatureWordArray minus_features = { 0 };
8f961357 1686 uint32_t numvalue;
a91987c2 1687 CPUX86State *env = &cpu->env;
8f961357 1688
8f961357 1689 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1690
1691 while (featurestr) {
1692 char *val;
1693 if (featurestr[0] == '+') {
5ef57876 1694 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1695 } else if (featurestr[0] == '-') {
5ef57876 1696 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1697 } else if ((val = strchr(featurestr, '='))) {
1698 *val = 0; val++;
72ac2e87 1699 feat2prop(featurestr);
d024d209 1700 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1701 char *err;
a91987c2
IM		 1702 char num[32];
1703
c6dc6f63
AP		 1704 numvalue = strtoul(val, &err, 0);
1705 if (!*val || *err) {
312fd5f2 1706 error_setg(errp, "bad numerical value %s", val);
a91987c2 1707 goto out;
c6dc6f63
AP		 1708 }
1709 if (numvalue < 0x80000000) {
8ba8a698
IM		 1710 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1711 ", fixup will be removed in future versions\n");
2f7a21c4 1712 numvalue += 0x80000000;
c6dc6f63 1713 }
a91987c2
IM		 1714 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1715 object_property_parse(OBJECT(cpu), num, featurestr, errp);
72ac2e87 1716 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1717 int64_t tsc_freq;
1718 char *err;
a91987c2 1719 char num[32];
b862d1fe
JR		 1720
1721 tsc_freq = strtosz_suffix_unit(val, &err,
1722 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1723 if (tsc_freq < 0 || *err) {
312fd5f2 1724 error_setg(errp, "bad numerical value %s", val);
a91987c2 1725 goto out;
b862d1fe 1726 }
a91987c2
IM		 1727 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1728 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
72ac2e87 1729 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1730 char *err;
92067bf4 1731 const int min = 0xFFF;
c8f0f88e 1732 char num[32];
28f52cc0
VR		 1733 numvalue = strtoul(val, &err, 0);
1734 if (!*val || *err) {
312fd5f2 1735 error_setg(errp, "bad numerical value %s", val);
a91987c2 1736 goto out;
28f52cc0 1737 }
92067bf4
IM		 1738 if (numvalue < min) {
1739 fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1740 ", fixup will be removed in future versions\n",
1741 min);
1742 numvalue = min;
1743 }
c8f0f88e
IM		 1744 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1745 object_property_parse(OBJECT(cpu), num, featurestr, errp);
c6dc6f63 1746 } else {
d024d209 1747 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1748 }
c6dc6f63 1749 } else {
258f5abe
IM		 1750 feat2prop(featurestr);
1751 object_property_parse(OBJECT(cpu), "on", featurestr, errp);
a91987c2
IM		 1752 }
1753 if (error_is_set(errp)) {
1754 goto out;
c6dc6f63
AP		 1755 }
1756 featurestr = strtok(NULL, ",");
1757 }
0514ef2f
EH		 1758 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1759 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1760 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1761 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1762 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1763 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1764 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1765 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1766 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1767 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1768 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1769 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1770 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1771 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1772 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1773 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63 1774
a91987c2
IM		 1775out:
1776 return;
c6dc6f63
AP		 1777}
1778
1779/* generate a composite string into buf of all cpuid names in featureset
1780 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1781 * if flags, suppress names undefined in featureset.
1782 */
1783static void listflags(char *buf, int bufsize, uint32_t fbits,
1784 const char **featureset, uint32_t flags)
1785{
1786 const char **p = &featureset[31];
1787 char *q, *b, bit;
1788 int nc;
1789
1790 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1791 *buf = '\0';
1792 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1793 if (fbits & 1 << bit && (*p || !flags)) {
1794 if (*p)
1795 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1796 else
1797 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1798 if (bufsize <= nc) {
1799 if (b) {
1800 memcpy(b, "...", sizeof("..."));
1801 }
1802 return;
1803 }
1804 q += nc;
1805 bufsize -= nc;
1806 }
1807}
1808
e916cbf8
PM		 1809/* generate CPU information. */
1810void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1811{
c6dc6f63
AP		 1812 x86_def_t *def;
1813 char buf[256];
7fc9b714 1814 int i;
c6dc6f63 1815
7fc9b714
AF		 1816 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1817 def = &builtin_x86_defs[i];
c04321b3 1818 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1819 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1820 }
21ad7789
JK		 1821#ifdef CONFIG_KVM
1822 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1823 "KVM processor with all supported host features "
1824 "(only available in KVM mode)");
1825#endif
1826
6cdf8854 1827 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1828 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1829 FeatureWordInfo *fw = &feature_word_info[i];
1830
1831 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1832 (*cpu_fprintf)(f, " %s\n", buf);
1833 }
c6dc6f63
AP		 1834}
1835
76b64a7a 1836CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1837{
1838 CpuDefinitionInfoList *cpu_list = NULL;
1839 x86_def_t *def;
7fc9b714 1840 int i;
e3966126 1841
7fc9b714 1842 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1843 CpuDefinitionInfoList *entry;
1844 CpuDefinitionInfo *info;
1845
7fc9b714 1846 def = &builtin_x86_defs[i];
e3966126
AL		 1847 info = g_malloc0(sizeof(*info));
1848 info->name = g_strdup(def->name);
1849
1850 entry = g_malloc0(sizeof(*entry));
1851 entry->value = info;
1852 entry->next = cpu_list;
1853 cpu_list = entry;
1854 }
1855
1856 return cpu_list;
1857}
1858
bc74b7db
EH		 1859#ifdef CONFIG_KVM
1860static void filter_features_for_kvm(X86CPU *cpu)
1861{
1862 CPUX86State *env = &cpu->env;
1863 KVMState *s = kvm_state;
bd87d2a2 1864 FeatureWord w;
bc74b7db 1865
bd87d2a2
EH		 1866 for (w = 0; w < FEATURE_WORDS; w++) {
1867 FeatureWordInfo *wi = &feature_word_info[w];
034acf4a
EH		 1868 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1869 wi->cpuid_ecx,
1870 wi->cpuid_reg);
1871 uint32_t requested_features = env->features[w];
1872 env->features[w] &= host_feat;
1873 cpu->filtered_features[w] = requested_features & ~env->features[w];
bd87d2a2 1874 }
bc74b7db
EH		 1875}
1876#endif
1877
2d64255b 1878static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
c6dc6f63 1879{
61dcd775 1880 CPUX86State *env = &cpu->env;
c6dc6f63
AP		 1881 x86_def_t def1, *def = &def1;
1882
db0ad1ba
JR		 1883 memset(def, 0, sizeof(*def));
1884
c1399112 1885 if (cpu_x86_find_by_name(cpu, def, name) < 0) {
2d64255b
AF		 1886 error_setg(errp, "Unable to find CPU definition: %s", name);
1887 return;
8f961357
EH		 1888 }
1889
aa87d458 1890 if (kvm_enabled()) {
0514ef2f 1891 def->features[FEAT_KVM] |= kvm_default_features;
aa87d458 1892 }
0514ef2f 1893 def->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
077c68c3 1894
2d64255b
AF		 1895 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1896 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1897 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1898 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1899 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
0514ef2f
EH		 1900 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1901 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1902 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1903 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
2d64255b 1904 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
0514ef2f
EH		 1905 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1906 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1907 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1908 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
b3baa152 1909 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1910 cpu->cache_info_passthrough = def->cache_info_passthrough;
3b671a40 1911
2d64255b 1912 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
c6dc6f63
AP		 1913}
1914
62fc403f
IM		 1915X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1916 Error **errp)
5c3c6a68 1917{
2d64255b 1918 X86CPU *cpu = NULL;
2d64255b
AF		 1919 gchar **model_pieces;
1920 char *name, *features;
ba2bc7a4 1921 char *typename;
5c3c6a68
AF		 1922 Error *error = NULL;
1923
2d64255b
AF		 1924 model_pieces = g_strsplit(cpu_model, ",", 2);
1925 if (!model_pieces[0]) {
1926 error_setg(&error, "Invalid/empty CPU model name");
1927 goto out;
1928 }
1929 name = model_pieces[0];
1930 features = model_pieces[1];
1931
5c3c6a68 1932 cpu = X86_CPU(object_new(TYPE_X86_CPU));
62fc403f
IM		 1933#ifndef CONFIG_USER_ONLY
1934 if (icc_bridge == NULL) {
1935 error_setg(&error, "Invalid icc-bridge value");
1936 goto out;
1937 }
1938 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1939 object_unref(OBJECT(cpu));
1940#endif
5c3c6a68 1941
2d64255b
AF		 1942 cpu_x86_register(cpu, name, &error);
1943 if (error) {
1944 goto out;
1945 }
1946
ba2bc7a4
AF		 1947 /* Emulate per-model subclasses for global properties */
1948 typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1949 qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1950 g_free(typename);
1951 if (error) {
1952 goto out;
1953 }
1954
2d64255b
AF		 1955 cpu_x86_parse_featurestr(cpu, features, &error);
1956 if (error) {
1957 goto out;
5c3c6a68
AF		 1958 }
1959
7f833247 1960out:
cd7b87ff
AF		 1961 if (error != NULL) {
1962 error_propagate(errp, error);
1963 object_unref(OBJECT(cpu));
1964 cpu = NULL;
1965 }
7f833247
IM		 1966 g_strfreev(model_pieces);
1967 return cpu;
1968}
1969
1970X86CPU *cpu_x86_init(const char *cpu_model)
1971{
1972 Error *error = NULL;
1973 X86CPU *cpu;
1974
62fc403f 1975 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1976 if (error) {
2d64255b
AF		 1977 goto out;
1978 }
1979
7f833247
IM		 1980 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1981
2d64255b 1982out:
2d64255b 1983 if (error) {
4a44d85e 1984 error_report("%s", error_get_pretty(error));
5c3c6a68 1985 error_free(error);
2d64255b
AF		 1986 if (cpu != NULL) {
1987 object_unref(OBJECT(cpu));
1988 cpu = NULL;
1989 }
5c3c6a68
AF		 1990 }
1991 return cpu;
1992}
1993
c6dc6f63 1994#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1995
0e26b7b8
BS		 1996void cpu_clear_apic_feature(CPUX86State *env)
1997{
0514ef2f 1998 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 1999}
2000
c6dc6f63
AP		 2001#endif /* !CONFIG_USER_ONLY */
2002
c04321b3 2003/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2004 */
2005void x86_cpudef_setup(void)
2006{
93bfef4c
CV		 2007 int i, j;
2008 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2009
2010 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291 2011 x86_def_t *def = &builtin_x86_defs[i];
93bfef4c
CV		 2012
2013 /* Look for specific "cpudef" models that */
09faecf2 2014 /* have the QEMU version in .model_id */
93bfef4c 2015 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2016 if (strcmp(model_with_versions[j], def->name) == 0) {
2017 pstrcpy(def->model_id, sizeof(def->model_id),
2018 "QEMU Virtual CPU version ");
2019 pstrcat(def->model_id, sizeof(def->model_id),
2020 qemu_get_version());
93bfef4c
CV		 2021 break;
2022 }
2023 }
c6dc6f63 2024 }
c6dc6f63
AP		 2025}
2026
c6dc6f63
AP		 2027static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2028 uint32_t *ecx, uint32_t *edx)
2029{
2030 *ebx = env->cpuid_vendor1;
2031 *edx = env->cpuid_vendor2;
2032 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2033}
2034
2035void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2036 uint32_t *eax, uint32_t *ebx,
2037 uint32_t *ecx, uint32_t *edx)
2038{
a60f24b5
AF		 2039 X86CPU *cpu = x86_env_get_cpu(env);
2040 CPUState *cs = CPU(cpu);
2041
c6dc6f63
AP		 2042 /* test if maximum index reached */
2043 if (index & 0x80000000) {
b3baa152
BW		 2044 if (index > env->cpuid_xlevel) {
2045 if (env->cpuid_xlevel2 > 0) {
2046 /* Handle the Centaur's CPUID instruction. */
2047 if (index > env->cpuid_xlevel2) {
2048 index = env->cpuid_xlevel2;
2049 } else if (index < 0xC0000000) {
2050 index = env->cpuid_xlevel;
2051 }
2052 } else {
57f26ae7
EH		 2053 /* Intel documentation states that invalid EAX input will
2054 * return the same information as EAX=cpuid_level
2055 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2056 */
2057 index = env->cpuid_level;
b3baa152
BW		 2058 }
2059 }
c6dc6f63
AP		 2060 } else {
2061 if (index > env->cpuid_level)
2062 index = env->cpuid_level;
2063 }
2064
2065 switch(index) {
2066 case 0:
2067 *eax = env->cpuid_level;
2068 get_cpuid_vendor(env, ebx, ecx, edx);
2069 break;
2070 case 1:
2071 *eax = env->cpuid_version;
2072 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2073 *ecx = env->features[FEAT_1_ECX];
2074 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2075 if (cs->nr_cores * cs->nr_threads > 1) {
2076 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2077 *edx |= 1 << 28; /* HTT bit */
2078 }
2079 break;
2080 case 2:
2081 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2082 if (cpu->cache_info_passthrough) {
2083 host_cpuid(index, 0, eax, ebx, ecx, edx);
2084 break;
2085 }
5e891bf8 2086 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2087 *ebx = 0;
2088 *ecx = 0;
5e891bf8
EH		 2089 *edx = (L1D_DESCRIPTOR << 16) | \
2090 (L1I_DESCRIPTOR << 8) | \
2091 (L2_DESCRIPTOR);
c6dc6f63
AP		 2092 break;
2093 case 4:
2094 /* cache info: needed for Core compatibility */
787aaf57
BC		 2095 if (cpu->cache_info_passthrough) {
2096 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2097 *eax &= ~0xFC000000;
c6dc6f63 2098 } else {
2f7a21c4 2099 *eax = 0;
76c2975a 2100 switch (count) {
c6dc6f63 2101 case 0: /* L1 dcache info */
5e891bf8
EH		 2102 *eax |= CPUID_4_TYPE_DCACHE | \
2103 CPUID_4_LEVEL(1) | \
2104 CPUID_4_SELF_INIT_LEVEL;
2105 *ebx = (L1D_LINE_SIZE - 1) | \
2106 ((L1D_PARTITIONS - 1) << 12) | \
2107 ((L1D_ASSOCIATIVITY - 1) << 22);
2108 *ecx = L1D_SETS - 1;
2109 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2110 break;
2111 case 1: /* L1 icache info */
5e891bf8
EH		 2112 *eax |= CPUID_4_TYPE_ICACHE | \
2113 CPUID_4_LEVEL(1) | \
2114 CPUID_4_SELF_INIT_LEVEL;
2115 *ebx = (L1I_LINE_SIZE - 1) | \
2116 ((L1I_PARTITIONS - 1) << 12) | \
2117 ((L1I_ASSOCIATIVITY - 1) << 22);
2118 *ecx = L1I_SETS - 1;
2119 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2120 break;
2121 case 2: /* L2 cache info */
5e891bf8
EH		 2122 *eax |= CPUID_4_TYPE_UNIFIED | \
2123 CPUID_4_LEVEL(2) | \
2124 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2125 if (cs->nr_threads > 1) {
2126 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2127 }
5e891bf8
EH		 2128 *ebx = (L2_LINE_SIZE - 1) | \
2129 ((L2_PARTITIONS - 1) << 12) | \
2130 ((L2_ASSOCIATIVITY - 1) << 22);
2131 *ecx = L2_SETS - 1;
2132 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2133 break;
2134 default: /* end of info */
2135 *eax = 0;
2136 *ebx = 0;
2137 *ecx = 0;
2138 *edx = 0;
2139 break;
76c2975a
PB		 2140 }
2141 }
2142
2143 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2144 if ((*eax & 31) && cs->nr_cores > 1) {
2145 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2146 }
2147 break;
2148 case 5:
2149 /* mwait info: needed for Core compatibility */
2150 *eax = 0; /* Smallest monitor-line size in bytes */
2151 *ebx = 0; /* Largest monitor-line size in bytes */
2152 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2153 *edx = 0;
2154 break;
2155 case 6:
2156 /* Thermal and Power Leaf */
2157 *eax = 0;
2158 *ebx = 0;
2159 *ecx = 0;
2160 *edx = 0;
2161 break;
f7911686 2162 case 7:
13526728
EH		 2163 /* Structured Extended Feature Flags Enumeration Leaf */
2164 if (count == 0) {
2165 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2166 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2167 *ecx = 0; /* Reserved */
2168 *edx = 0; /* Reserved */
f7911686
YW		 2169 } else {
2170 *eax = 0;
2171 *ebx = 0;
2172 *ecx = 0;
2173 *edx = 0;
2174 }
2175 break;
c6dc6f63
AP		 2176 case 9:
2177 /* Direct Cache Access Information Leaf */
2178 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2179 *ebx = 0;
2180 *ecx = 0;
2181 *edx = 0;
2182 break;
2183 case 0xA:
2184 /* Architectural Performance Monitoring Leaf */
9337e3b6 2185 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2186 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2187
2188 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2189 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2190 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2191 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2192 } else {
2193 *eax = 0;
2194 *ebx = 0;
2195 *ecx = 0;
2196 *edx = 0;
2197 }
c6dc6f63 2198 break;
2560f19f
PB		 2199 case 0xD: {
2200 KVMState *s = cs->kvm_state;
2201 uint64_t kvm_mask;
2202 int i;
2203
51e49430 2204 /* Processor Extended State */
2560f19f
PB		 2205 *eax = 0;
2206 *ebx = 0;
2207 *ecx = 0;
2208 *edx = 0;
2209 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2210 break;
2211 }
2560f19f
PB		 2212 kvm_mask =
2213 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2214 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2215
2560f19f
PB		 2216 if (count == 0) {
2217 *ecx = 0x240;
2218 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2219 const ExtSaveArea *esa = &ext_save_areas[i];
2220 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2221 (kvm_mask & (1 << i)) != 0) {
2222 if (i < 32) {
2223 *eax |= 1 << i;
2224 } else {
2225 *edx |= 1 << (i - 32);
2226 }
2227 *ecx = MAX(*ecx, esa->offset + esa->size);
2228 }
2229 }
2230 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2231 *ebx = *ecx;
2232 } else if (count == 1) {
2233 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2234 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2235 const ExtSaveArea *esa = &ext_save_areas[count];
2236 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2237 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2238 *eax = esa->size;
2239 *ebx = esa->offset;
2560f19f 2240 }
51e49430
SY		 2241 }
2242 break;
2560f19f 2243 }
c6dc6f63
AP		 2244 case 0x80000000:
2245 *eax = env->cpuid_xlevel;
2246 *ebx = env->cpuid_vendor1;
2247 *edx = env->cpuid_vendor2;
2248 *ecx = env->cpuid_vendor3;
2249 break;
2250 case 0x80000001:
2251 *eax = env->cpuid_version;
2252 *ebx = 0;
0514ef2f
EH		 2253 *ecx = env->features[FEAT_8000_0001_ECX];
2254 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2255
2256 /* The Linux kernel checks for the CMPLegacy bit and
2257 * discards multiple thread information if it is set.
2258 * So dont set it here for Intel to make Linux guests happy.
2259 */
ce3960eb 2260 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2261 uint32_t tebx, tecx, tedx;
2262 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2263 if (tebx != CPUID_VENDOR_INTEL_1 ||
2264 tedx != CPUID_VENDOR_INTEL_2 ||
2265 tecx != CPUID_VENDOR_INTEL_3) {
2266 *ecx |= 1 << 1; /* CmpLegacy bit */
2267 }
2268 }
c6dc6f63
AP		 2269 break;
2270 case 0x80000002:
2271 case 0x80000003:
2272 case 0x80000004:
2273 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2274 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2275 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2276 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2277 break;
2278 case 0x80000005:
2279 /* cache info (L1 cache) */
787aaf57
BC		 2280 if (cpu->cache_info_passthrough) {
2281 host_cpuid(index, 0, eax, ebx, ecx, edx);
2282 break;
2283 }
5e891bf8
EH		 2284 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2285 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2286 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2287 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2288 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2289 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2290 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2291 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2292 break;
2293 case 0x80000006:
2294 /* cache info (L2 cache) */
787aaf57
BC		 2295 if (cpu->cache_info_passthrough) {
2296 host_cpuid(index, 0, eax, ebx, ecx, edx);
2297 break;
2298 }
5e891bf8
EH		 2299 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2300 (L2_DTLB_2M_ENTRIES << 16) | \
2301 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2302 (L2_ITLB_2M_ENTRIES);
2303 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2304 (L2_DTLB_4K_ENTRIES << 16) | \
2305 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2306 (L2_ITLB_4K_ENTRIES);
2307 *ecx = (L2_SIZE_KB_AMD << 16) | \
2308 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2309 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2310 *edx = ((L3_SIZE_KB/512) << 18) | \
2311 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2312 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP		 2313 break;
2314 case 0x80000008:
2315 /* virtual & phys address size in low 2 bytes. */
2316/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2317 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2318 /* 64 bit processor */
2319/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2320 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2321 } else {
0514ef2f 2322 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2323 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2324 } else {
c6dc6f63 2325 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2326 }
c6dc6f63
AP		 2327 }
2328 *ebx = 0;
2329 *ecx = 0;
2330 *edx = 0;
ce3960eb
AF		 2331 if (cs->nr_cores * cs->nr_threads > 1) {
2332 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2333 }
2334 break;
2335 case 0x8000000A:
0514ef2f 2336 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2337 *eax = 0x00000001; /* SVM Revision */
2338 *ebx = 0x00000010; /* nr of ASIDs */
2339 *ecx = 0;
0514ef2f 2340 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2341 } else {
2342 *eax = 0;
2343 *ebx = 0;
2344 *ecx = 0;
2345 *edx = 0;
2346 }
c6dc6f63 2347 break;
b3baa152
BW		 2348 case 0xC0000000:
2349 *eax = env->cpuid_xlevel2;
2350 *ebx = 0;
2351 *ecx = 0;
2352 *edx = 0;
2353 break;
2354 case 0xC0000001:
2355 /* Support for VIA CPU's CPUID instruction */
2356 *eax = env->cpuid_version;
2357 *ebx = 0;
2358 *ecx = 0;
0514ef2f 2359 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2360 break;
2361 case 0xC0000002:
2362 case 0xC0000003:
2363 case 0xC0000004:
2364 /* Reserved for the future, and now filled with zero */
2365 *eax = 0;
2366 *ebx = 0;
2367 *ecx = 0;
2368 *edx = 0;
2369 break;
c6dc6f63
AP		 2370 default:
2371 /* reserved values: zero */
2372 *eax = 0;
2373 *ebx = 0;
2374 *ecx = 0;
2375 *edx = 0;
2376 break;
2377 }
2378}
5fd2087a
AF		 2379
2380/* CPUClass::reset() */
2381static void x86_cpu_reset(CPUState *s)
2382{
2383 X86CPU *cpu = X86_CPU(s);
2384 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2385 CPUX86State *env = &cpu->env;
c1958aea
AF		 2386 int i;
2387
5fd2087a
AF		 2388 xcc->parent_reset(s);
2389
c1958aea
AF		 2390
2391 memset(env, 0, offsetof(CPUX86State, breakpoints));
2392
2393 tlb_flush(env, 1);
2394
2395 env->old_exception = -1;
2396
2397 /* init to reset state */
2398
2399#ifdef CONFIG_SOFTMMU
2400 env->hflags |= HF_SOFTMMU_MASK;
2401#endif
2402 env->hflags2 |= HF2_GIF_MASK;
2403
2404 cpu_x86_update_cr0(env, 0x60000010);
2405 env->a20_mask = ~0x0;
2406 env->smbase = 0x30000;
2407
2408 env->idt.limit = 0xffff;
2409 env->gdt.limit = 0xffff;
2410 env->ldt.limit = 0xffff;
2411 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2412 env->tr.limit = 0xffff;
2413 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2414
2415 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2416 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2417 DESC_R_MASK | DESC_A_MASK);
2418 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2419 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2420 DESC_A_MASK);
2421 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2422 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2423 DESC_A_MASK);
2424 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2425 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2426 DESC_A_MASK);
2427 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2428 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2429 DESC_A_MASK);
2430 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2431 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2432 DESC_A_MASK);
2433
2434 env->eip = 0xfff0;
2435 env->regs[R_EDX] = env->cpuid_version;
2436
2437 env->eflags = 0x2;
2438
2439 /* FPU init */
2440 for (i = 0; i < 8; i++) {
2441 env->fptags[i] = 1;
2442 }
2443 env->fpuc = 0x37f;
2444
2445 env->mxcsr = 0x1f80;
c74f41bb 2446 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2447
2448 env->pat = 0x0007040600070406ULL;
2449 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2450
2451 memset(env->dr, 0, sizeof(env->dr));
2452 env->dr[6] = DR6_FIXED_1;
2453 env->dr[7] = DR7_FIXED_1;
2454 cpu_breakpoint_remove_all(env, BP_CPU);
2455 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288 2456
0522604b
FLVC		 2457 env->tsc_adjust = 0;
2458 env->tsc = 0;
2459
dd673288
IM		 2460#if !defined(CONFIG_USER_ONLY)
2461 /* We hard-wire the BSP to the first CPU. */
55e5c285 2462 if (s->cpu_index == 0) {
02e51483 2463 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2464 }
2465
259186a7 2466 s->halted = !cpu_is_bsp(cpu);
dd673288 2467#endif
5fd2087a
AF		 2468}
2469
dd673288
IM		 2470#ifndef CONFIG_USER_ONLY
2471bool cpu_is_bsp(X86CPU *cpu)
2472{
02e51483 2473 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2474}
65dee380
IM		 2475
2476/* TODO: remove me, when reset over QOM tree is implemented */
2477static void x86_cpu_machine_reset_cb(void *opaque)
2478{
2479 X86CPU *cpu = opaque;
2480 cpu_reset(CPU(cpu));
2481}
dd673288
IM		 2482#endif
2483
de024815
AF		 2484static void mce_init(X86CPU *cpu)
2485{
2486 CPUX86State *cenv = &cpu->env;
2487 unsigned int bank;
2488
2489 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2490 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2491 (CPUID_MCE | CPUID_MCA)) {
2492 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2493 cenv->mcg_ctl = ~(uint64_t)0;
2494 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2495 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2496 }
2497 }
2498}
2499
bdeec802 2500#ifndef CONFIG_USER_ONLY
d3c64d6a 2501static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2502{
bdeec802 2503 CPUX86State *env = &cpu->env;
53a89e26 2504 DeviceState *dev = DEVICE(cpu);
449994eb 2505 APICCommonState *apic;
bdeec802
IM		 2506 const char *apic_type = "apic";
2507
2508 if (kvm_irqchip_in_kernel()) {
2509 apic_type = "kvm-apic";
2510 } else if (xen_enabled()) {
2511 apic_type = "xen-apic";
2512 }
2513
02e51483
CF		 2514 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2515 if (cpu->apic_state == NULL) {
bdeec802
IM		 2516 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2517 return;
2518 }
2519
2520 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2521 OBJECT(cpu->apic_state), NULL);
2522 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2523 /* TODO: convert to link<> */
02e51483 2524 apic = APIC_COMMON(cpu->apic_state);
60671e58 2525 apic->cpu = cpu;
d3c64d6a
IM		 2526}
2527
2528static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2529{
02e51483 2530 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2531 return;
2532 }
bdeec802 2533
02e51483 2534 if (qdev_init(cpu->apic_state)) {
bdeec802 2535 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2536 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2537 return;
2538 }
bdeec802 2539}
d3c64d6a
IM		 2540#else
2541static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2542{
2543}
bdeec802
IM		 2544#endif
2545
2b6f294c 2546static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2547{
14a10fc3 2548 CPUState *cs = CPU(dev);
2b6f294c
AF		 2549 X86CPU *cpu = X86_CPU(dev);
2550 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2551 CPUX86State *env = &cpu->env;
2b6f294c 2552 Error *local_err = NULL;
b34d12d1 2553
0514ef2f 2554 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2555 env->cpuid_level = 7;
2556 }
7a059953 2557
9b15cd9e
IM		 2558 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2559 * CPUID[1].EDX.
2560 */
2561 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2562 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2563 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2564 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2565 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2566 & CPUID_EXT2_AMD_ALIASES);
2567 }
2568
4586f157 2569 if (!kvm_enabled()) {
0514ef2f
EH		 2570 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2571 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2572 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
4586f157
IM		 2573#ifdef TARGET_X86_64
2574 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2575#endif
2576 );
0514ef2f
EH		 2577 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2578 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
4586f157 2579 } else {
912ffc47
IM		 2580 if ((cpu->check_cpuid || cpu->enforce_cpuid)
2581 && kvm_check_features_against_host(cpu) && cpu->enforce_cpuid) {
4dc1f449
IM		 2582 error_setg(&local_err,
2583 "Host's CPU doesn't support requested features");
2584 goto out;
5ec01c2e 2585 }
a509d632
EH		 2586#ifdef CONFIG_KVM
2587 filter_features_for_kvm(cpu);
2588#endif
4586f157
IM		 2589 }
2590
65dee380
IM		 2591#ifndef CONFIG_USER_ONLY
2592 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2593
0514ef2f 2594 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2595 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2596 if (local_err != NULL) {
4dc1f449 2597 goto out;
bdeec802
IM		 2598 }
2599 }
65dee380
IM		 2600#endif
2601
7a059953 2602 mce_init(cpu);
14a10fc3 2603 qemu_init_vcpu(cs);
d3c64d6a
IM		 2604
2605 x86_cpu_apic_realize(cpu, &local_err);
2606 if (local_err != NULL) {
2607 goto out;
2608 }
14a10fc3 2609 cpu_reset(cs);
2b6f294c 2610
4dc1f449
IM		 2611 xcc->parent_realize(dev, &local_err);
2612out:
2613 if (local_err != NULL) {
2614 error_propagate(errp, local_err);
2615 return;
2616 }
7a059953
AF		 2617}
2618
8932cfdf
EH		 2619/* Enables contiguous-apic-ID mode, for compatibility */
2620static bool compat_apic_id_mode;
2621
2622void enable_compat_apic_id_mode(void)
2623{
2624 compat_apic_id_mode = true;
2625}
2626
cb41bad3
EH		 2627/* Calculates initial APIC ID for a specific CPU index
2628 *
2629 * Currently we need to be able to calculate the APIC ID from the CPU index
2630 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2631 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2632 * all CPUs up to max_cpus.
2633 */
2634uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2635{
8932cfdf
EH		 2636 uint32_t correct_id;
2637 static bool warned;
2638
2639 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2640 if (compat_apic_id_mode) {
2641 if (cpu_index != correct_id && !warned) {
2642 error_report("APIC IDs set in compatibility mode, "
2643 "CPU topology won't match the configuration");
2644 warned = true;
2645 }
2646 return cpu_index;
2647 } else {
2648 return correct_id;
2649 }
cb41bad3
EH		 2650}
2651
de024815
AF		 2652static void x86_cpu_initfn(Object *obj)
2653{
55e5c285 2654 CPUState *cs = CPU(obj);
de024815
AF		 2655 X86CPU *cpu = X86_CPU(obj);
2656 CPUX86State *env = &cpu->env;
d65e9815 2657 static int inited;
de024815 2658
c05efcb1 2659 cs->env_ptr = env;
de024815 2660 cpu_exec_init(env);
71ad61d3
AF		 2661
2662 object_property_add(obj, "family", "int",
95b8519d 2663 x86_cpuid_version_get_family,
71ad61d3 2664 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2665 object_property_add(obj, "model", "int",
67e30c83 2666 x86_cpuid_version_get_model,
c5291a4f 2667 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2668 object_property_add(obj, "stepping", "int",
35112e41 2669 x86_cpuid_version_get_stepping,
036e2222 2670 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2671 object_property_add(obj, "level", "int",
2672 x86_cpuid_get_level,
2673 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2674 object_property_add(obj, "xlevel", "int",
2675 x86_cpuid_get_xlevel,
2676 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2677 object_property_add_str(obj, "vendor",
2678 x86_cpuid_get_vendor,
2679 x86_cpuid_set_vendor, NULL);
938d4c25 2680 object_property_add_str(obj, "model-id",
63e886eb 2681 x86_cpuid_get_model_id,
938d4c25 2682 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2683 object_property_add(obj, "tsc-frequency", "int",
2684 x86_cpuid_get_tsc_freq,
2685 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2686 object_property_add(obj, "apic-id", "int",
2687 x86_cpuid_get_apic_id,
2688 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2689 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2690 x86_cpu_get_feature_words,
7e5292b5
EH		 2691 NULL, NULL, (void *)env->features, NULL);
2692 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2693 x86_cpu_get_feature_words,
2694 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2695
92067bf4 2696 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2697 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815
IM		 2698
2699 /* init various static tables used in TCG mode */
2700 if (tcg_enabled() && !inited) {
2701 inited = 1;
2702 optimize_flags_init();
2703#ifndef CONFIG_USER_ONLY
2704 cpu_set_debug_excp_handler(breakpoint_handler);
2705#endif
2706 }
de024815
AF		 2707}
2708
997395d3
IM		 2709static int64_t x86_cpu_get_arch_id(CPUState *cs)
2710{
2711 X86CPU *cpu = X86_CPU(cs);
2712 CPUX86State *env = &cpu->env;
2713
2714 return env->cpuid_apic_id;
2715}
2716
444d5590
AF		 2717static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2718{
2719 X86CPU *cpu = X86_CPU(cs);
2720
2721 return cpu->env.cr[0] & CR0_PG_MASK;
2722}
2723
f45748f1
AF		 2724static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2725{
2726 X86CPU *cpu = X86_CPU(cs);
2727
2728 cpu->env.eip = value;
2729}
2730
bdf7ae5b
AF		 2731static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2732{
2733 X86CPU *cpu = X86_CPU(cs);
2734
2735 cpu->env.eip = tb->pc - tb->cs_base;
2736}
2737
9337e3b6
EH		 2738static Property x86_cpu_properties[] = {
2739 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2740 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2741 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2742 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
912ffc47
IM		 2743 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2744 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
9337e3b6
EH		 2745 DEFINE_PROP_END_OF_LIST()
2746};
2747
5fd2087a
AF		 2748static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2749{
2750 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2751 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2752 DeviceClass *dc = DEVICE_CLASS(oc);
2753
2754 xcc->parent_realize = dc->realize;
2755 dc->realize = x86_cpu_realizefn;
62fc403f 2756 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2757 dc->props = x86_cpu_properties;
5fd2087a
AF		 2758
2759 xcc->parent_reset = cc->reset;
2760 cc->reset = x86_cpu_reset;
91b1df8c 2761 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2762
97a8ea5a 2763 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2764 cc->dump_state = x86_cpu_dump_state;
f45748f1 2765 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2766 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2767 cc->gdb_read_register = x86_cpu_gdb_read_register;
2768 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2769 cc->get_arch_id = x86_cpu_get_arch_id;
2770 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
c72bf468 2771#ifndef CONFIG_USER_ONLY
a23bbfda 2772 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2773 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2774 cc->write_elf64_note = x86_cpu_write_elf64_note;
2775 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2776 cc->write_elf32_note = x86_cpu_write_elf32_note;
2777 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2778 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2779#endif
a0e372f0 2780 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2781}
2782
2783static const TypeInfo x86_cpu_type_info = {
2784 .name = TYPE_X86_CPU,
2785 .parent = TYPE_CPU,
2786 .instance_size = sizeof(X86CPU),
de024815 2787 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2788 .abstract = false,
2789 .class_size = sizeof(X86CPUClass),
2790 .class_init = x86_cpu_common_class_init,
2791};
2792
2793static void x86_cpu_register_types(void)
2794{
2795 type_register_static(&x86_cpu_type_info);
2796}
2797
2798type_init(x86_cpu_register_types)
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