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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
44a95dae SS |
17 | |
18 | #define pr_fmt(fmt) "SVM: " fmt | |
19 | ||
edf88417 AK |
20 | #include <linux/kvm_host.h> |
21 | ||
85f455f7 | 22 | #include "irq.h" |
1d737c8a | 23 | #include "mmu.h" |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
fe4c7b19 | 25 | #include "x86.h" |
66f7b72e | 26 | #include "cpuid.h" |
25462f7f | 27 | #include "pmu.h" |
e495606d | 28 | |
6aa8b732 | 29 | #include <linux/module.h> |
ae759544 | 30 | #include <linux/mod_devicetable.h> |
9d8f549d | 31 | #include <linux/kernel.h> |
6aa8b732 AK |
32 | #include <linux/vmalloc.h> |
33 | #include <linux/highmem.h> | |
e8edc6e0 | 34 | #include <linux/sched.h> |
af658dca | 35 | #include <linux/trace_events.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
6aa8b732 | 37 | |
1018faa6 | 38 | #include <asm/perf_event.h> |
67ec6607 | 39 | #include <asm/tlbflush.h> |
e495606d | 40 | #include <asm/desc.h> |
facb0139 | 41 | #include <asm/debugreg.h> |
631bc487 | 42 | #include <asm/kvm_para.h> |
6aa8b732 | 43 | |
63d1142f | 44 | #include <asm/virtext.h> |
229456fc | 45 | #include "trace.h" |
63d1142f | 46 | |
4ecac3fd AK |
47 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
48 | ||
6aa8b732 AK |
49 | MODULE_AUTHOR("Qumranet"); |
50 | MODULE_LICENSE("GPL"); | |
51 | ||
ae759544 JT |
52 | static const struct x86_cpu_id svm_cpu_id[] = { |
53 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
54 | {} | |
55 | }; | |
56 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
57 | ||
6aa8b732 AK |
58 | #define IOPM_ALLOC_ORDER 2 |
59 | #define MSRPM_ALLOC_ORDER 1 | |
60 | ||
6aa8b732 AK |
61 | #define SEG_TYPE_LDT 2 |
62 | #define SEG_TYPE_BUSY_TSS16 3 | |
63 | ||
6bc31bdc AP |
64 | #define SVM_FEATURE_NPT (1 << 0) |
65 | #define SVM_FEATURE_LBRV (1 << 1) | |
66 | #define SVM_FEATURE_SVML (1 << 2) | |
67 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
68 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
69 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
70 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
71 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 72 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 73 | |
340d3bc3 SS |
74 | #define SVM_AVIC_DOORBELL 0xc001011b |
75 | ||
410e4d57 JR |
76 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
77 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
78 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
79 | ||
24e09cbf JR |
80 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
81 | ||
fbc0db76 | 82 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
83 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
84 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 85 | |
44a95dae SS |
86 | #define AVIC_HPA_MASK ~((0xFFFULL << 52) || 0xFFF) |
87 | ||
88 | /* | |
89 | * 0xff is broadcast, so the max index allowed for physical APIC ID | |
90 | * table is 0xfe. APIC IDs above 0xff are reserved. | |
91 | */ | |
92 | #define AVIC_MAX_PHYSICAL_ID_COUNT 255 | |
93 | ||
67ec6607 JR |
94 | static bool erratum_383_found __read_mostly; |
95 | ||
6c8166a7 AK |
96 | static const u32 host_save_user_msrs[] = { |
97 | #ifdef CONFIG_X86_64 | |
98 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
99 | MSR_FS_BASE, | |
100 | #endif | |
101 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
46896c73 | 102 | MSR_TSC_AUX, |
6c8166a7 AK |
103 | }; |
104 | ||
105 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
106 | ||
107 | struct kvm_vcpu; | |
108 | ||
e6aa9abd JR |
109 | struct nested_state { |
110 | struct vmcb *hsave; | |
111 | u64 hsave_msr; | |
4a810181 | 112 | u64 vm_cr_msr; |
e6aa9abd JR |
113 | u64 vmcb; |
114 | ||
115 | /* These are the merged vectors */ | |
116 | u32 *msrpm; | |
117 | ||
118 | /* gpa pointers to the real vectors */ | |
119 | u64 vmcb_msrpm; | |
ce2ac085 | 120 | u64 vmcb_iopm; |
aad42c64 | 121 | |
cd3ff653 JR |
122 | /* A VMEXIT is required but not yet emulated */ |
123 | bool exit_required; | |
124 | ||
aad42c64 | 125 | /* cache for intercepts of the guest */ |
4ee546b4 | 126 | u32 intercept_cr; |
3aed041a | 127 | u32 intercept_dr; |
aad42c64 JR |
128 | u32 intercept_exceptions; |
129 | u64 intercept; | |
130 | ||
5bd2edc3 JR |
131 | /* Nested Paging related state */ |
132 | u64 nested_cr3; | |
e6aa9abd JR |
133 | }; |
134 | ||
323c3d80 JR |
135 | #define MSRPM_OFFSETS 16 |
136 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
137 | ||
2b036c6b BO |
138 | /* |
139 | * Set osvw_len to higher value when updated Revision Guides | |
140 | * are published and we know what the new status bits are | |
141 | */ | |
142 | static uint64_t osvw_len = 4, osvw_status; | |
143 | ||
6c8166a7 AK |
144 | struct vcpu_svm { |
145 | struct kvm_vcpu vcpu; | |
146 | struct vmcb *vmcb; | |
147 | unsigned long vmcb_pa; | |
148 | struct svm_cpu_data *svm_data; | |
149 | uint64_t asid_generation; | |
150 | uint64_t sysenter_esp; | |
151 | uint64_t sysenter_eip; | |
46896c73 | 152 | uint64_t tsc_aux; |
6c8166a7 AK |
153 | |
154 | u64 next_rip; | |
155 | ||
156 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 157 | struct { |
dacccfdd AK |
158 | u16 fs; |
159 | u16 gs; | |
160 | u16 ldt; | |
afe9e66f AK |
161 | u64 gs_base; |
162 | } host; | |
6c8166a7 AK |
163 | |
164 | u32 *msrpm; | |
6c8166a7 | 165 | |
bd3d1ec3 AK |
166 | ulong nmi_iret_rip; |
167 | ||
e6aa9abd | 168 | struct nested_state nested; |
6be7d306 JK |
169 | |
170 | bool nmi_singlestep; | |
66b7138f JK |
171 | |
172 | unsigned int3_injected; | |
173 | unsigned long int3_rip; | |
631bc487 | 174 | u32 apf_reason; |
fbc0db76 | 175 | |
6092d3d3 JR |
176 | /* cached guest cpuid flags for faster access */ |
177 | bool nrips_enabled : 1; | |
44a95dae SS |
178 | |
179 | struct page *avic_backing_page; | |
180 | u64 *avic_physical_id_cache; | |
6c8166a7 AK |
181 | }; |
182 | ||
44a95dae SS |
183 | #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) |
184 | #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) | |
185 | ||
186 | #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) | |
187 | #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) | |
188 | #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) | |
189 | #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) | |
190 | ||
fbc0db76 JR |
191 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
192 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
193 | ||
455716fa JR |
194 | #define MSR_INVALID 0xffffffffU |
195 | ||
09941fbb | 196 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
197 | u32 index; /* Index of the MSR */ |
198 | bool always; /* True if intercept is always on */ | |
199 | } direct_access_msrs[] = { | |
8c06585d | 200 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
201 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
202 | #ifdef CONFIG_X86_64 | |
203 | { .index = MSR_GS_BASE, .always = true }, | |
204 | { .index = MSR_FS_BASE, .always = true }, | |
205 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
206 | { .index = MSR_LSTAR, .always = true }, | |
207 | { .index = MSR_CSTAR, .always = true }, | |
208 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
209 | #endif | |
210 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
211 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
212 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
213 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
214 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
215 | }; |
216 | ||
709ddebf JR |
217 | /* enable NPT for AMD64 and X86 with PAE */ |
218 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
219 | static bool npt_enabled = true; | |
220 | #else | |
e0231715 | 221 | static bool npt_enabled; |
709ddebf | 222 | #endif |
6c7dac72 | 223 | |
e2358851 DB |
224 | /* allow nested paging (virtualized MMU) for all guests */ |
225 | static int npt = true; | |
6c7dac72 | 226 | module_param(npt, int, S_IRUGO); |
e3da3acd | 227 | |
e2358851 DB |
228 | /* allow nested virtualization in KVM/SVM */ |
229 | static int nested = true; | |
236de055 AG |
230 | module_param(nested, int, S_IRUGO); |
231 | ||
44a95dae SS |
232 | /* enable / disable AVIC */ |
233 | static int avic; | |
234 | module_param(avic, int, S_IRUGO); | |
235 | ||
79a8059d | 236 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
44874f84 | 237 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 238 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 239 | |
410e4d57 | 240 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 241 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 242 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
243 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
244 | bool has_error_code, u32 error_code); | |
245 | ||
8d28fec4 | 246 | enum { |
116a0a23 JR |
247 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
248 | pause filter count */ | |
f56838e4 | 249 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 250 | VMCB_ASID, /* ASID */ |
decdbf6a | 251 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 252 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 253 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 254 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 255 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 256 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 257 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 258 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
44a95dae SS |
259 | VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, |
260 | * AVIC PHYSICAL_TABLE pointer, | |
261 | * AVIC LOGICAL_TABLE pointer | |
262 | */ | |
8d28fec4 RJ |
263 | VMCB_DIRTY_MAX, |
264 | }; | |
265 | ||
0574dec0 JR |
266 | /* TPR and CR2 are always written before VMRUN */ |
267 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 | 268 | |
44a95dae SS |
269 | #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL |
270 | ||
8d28fec4 RJ |
271 | static inline void mark_all_dirty(struct vmcb *vmcb) |
272 | { | |
273 | vmcb->control.clean = 0; | |
274 | } | |
275 | ||
276 | static inline void mark_all_clean(struct vmcb *vmcb) | |
277 | { | |
278 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
279 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
280 | } | |
281 | ||
282 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
283 | { | |
284 | vmcb->control.clean &= ~(1 << bit); | |
285 | } | |
286 | ||
a2fa3e9f GH |
287 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
288 | { | |
fb3f0f51 | 289 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
290 | } |
291 | ||
44a95dae SS |
292 | static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) |
293 | { | |
294 | svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; | |
295 | mark_dirty(svm->vmcb, VMCB_AVIC); | |
296 | } | |
297 | ||
340d3bc3 SS |
298 | static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) |
299 | { | |
300 | struct vcpu_svm *svm = to_svm(vcpu); | |
301 | u64 *entry = svm->avic_physical_id_cache; | |
302 | ||
303 | if (!entry) | |
304 | return false; | |
305 | ||
306 | return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
307 | } | |
308 | ||
384c6368 JR |
309 | static void recalc_intercepts(struct vcpu_svm *svm) |
310 | { | |
311 | struct vmcb_control_area *c, *h; | |
312 | struct nested_state *g; | |
313 | ||
116a0a23 JR |
314 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
315 | ||
384c6368 JR |
316 | if (!is_guest_mode(&svm->vcpu)) |
317 | return; | |
318 | ||
319 | c = &svm->vmcb->control; | |
320 | h = &svm->nested.hsave->control; | |
321 | g = &svm->nested; | |
322 | ||
4ee546b4 | 323 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 324 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
325 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
326 | c->intercept = h->intercept | g->intercept; | |
327 | } | |
328 | ||
4ee546b4 RJ |
329 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
330 | { | |
331 | if (is_guest_mode(&svm->vcpu)) | |
332 | return svm->nested.hsave; | |
333 | else | |
334 | return svm->vmcb; | |
335 | } | |
336 | ||
337 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
338 | { | |
339 | struct vmcb *vmcb = get_host_vmcb(svm); | |
340 | ||
341 | vmcb->control.intercept_cr |= (1U << bit); | |
342 | ||
343 | recalc_intercepts(svm); | |
344 | } | |
345 | ||
346 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
347 | { | |
348 | struct vmcb *vmcb = get_host_vmcb(svm); | |
349 | ||
350 | vmcb->control.intercept_cr &= ~(1U << bit); | |
351 | ||
352 | recalc_intercepts(svm); | |
353 | } | |
354 | ||
355 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
356 | { | |
357 | struct vmcb *vmcb = get_host_vmcb(svm); | |
358 | ||
359 | return vmcb->control.intercept_cr & (1U << bit); | |
360 | } | |
361 | ||
5315c716 | 362 | static inline void set_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
363 | { |
364 | struct vmcb *vmcb = get_host_vmcb(svm); | |
365 | ||
5315c716 PB |
366 | vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) |
367 | | (1 << INTERCEPT_DR1_READ) | |
368 | | (1 << INTERCEPT_DR2_READ) | |
369 | | (1 << INTERCEPT_DR3_READ) | |
370 | | (1 << INTERCEPT_DR4_READ) | |
371 | | (1 << INTERCEPT_DR5_READ) | |
372 | | (1 << INTERCEPT_DR6_READ) | |
373 | | (1 << INTERCEPT_DR7_READ) | |
374 | | (1 << INTERCEPT_DR0_WRITE) | |
375 | | (1 << INTERCEPT_DR1_WRITE) | |
376 | | (1 << INTERCEPT_DR2_WRITE) | |
377 | | (1 << INTERCEPT_DR3_WRITE) | |
378 | | (1 << INTERCEPT_DR4_WRITE) | |
379 | | (1 << INTERCEPT_DR5_WRITE) | |
380 | | (1 << INTERCEPT_DR6_WRITE) | |
381 | | (1 << INTERCEPT_DR7_WRITE); | |
3aed041a JR |
382 | |
383 | recalc_intercepts(svm); | |
384 | } | |
385 | ||
5315c716 | 386 | static inline void clr_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
387 | { |
388 | struct vmcb *vmcb = get_host_vmcb(svm); | |
389 | ||
5315c716 | 390 | vmcb->control.intercept_dr = 0; |
3aed041a JR |
391 | |
392 | recalc_intercepts(svm); | |
393 | } | |
394 | ||
18c918c5 JR |
395 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
396 | { | |
397 | struct vmcb *vmcb = get_host_vmcb(svm); | |
398 | ||
399 | vmcb->control.intercept_exceptions |= (1U << bit); | |
400 | ||
401 | recalc_intercepts(svm); | |
402 | } | |
403 | ||
404 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
405 | { | |
406 | struct vmcb *vmcb = get_host_vmcb(svm); | |
407 | ||
408 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
409 | ||
410 | recalc_intercepts(svm); | |
411 | } | |
412 | ||
8a05a1b8 JR |
413 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
414 | { | |
415 | struct vmcb *vmcb = get_host_vmcb(svm); | |
416 | ||
417 | vmcb->control.intercept |= (1ULL << bit); | |
418 | ||
419 | recalc_intercepts(svm); | |
420 | } | |
421 | ||
422 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
423 | { | |
424 | struct vmcb *vmcb = get_host_vmcb(svm); | |
425 | ||
426 | vmcb->control.intercept &= ~(1ULL << bit); | |
427 | ||
428 | recalc_intercepts(svm); | |
429 | } | |
430 | ||
2af9194d JR |
431 | static inline void enable_gif(struct vcpu_svm *svm) |
432 | { | |
433 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
434 | } | |
435 | ||
436 | static inline void disable_gif(struct vcpu_svm *svm) | |
437 | { | |
438 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
439 | } | |
440 | ||
441 | static inline bool gif_set(struct vcpu_svm *svm) | |
442 | { | |
443 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
444 | } | |
445 | ||
4866d5e3 | 446 | static unsigned long iopm_base; |
6aa8b732 AK |
447 | |
448 | struct kvm_ldttss_desc { | |
449 | u16 limit0; | |
450 | u16 base0; | |
e0231715 JR |
451 | unsigned base1:8, type:5, dpl:2, p:1; |
452 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
453 | u32 base3; |
454 | u32 zero1; | |
455 | } __attribute__((packed)); | |
456 | ||
457 | struct svm_cpu_data { | |
458 | int cpu; | |
459 | ||
5008fdf5 AK |
460 | u64 asid_generation; |
461 | u32 max_asid; | |
462 | u32 next_asid; | |
6aa8b732 AK |
463 | struct kvm_ldttss_desc *tss_desc; |
464 | ||
465 | struct page *save_area; | |
466 | }; | |
467 | ||
468 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
469 | ||
470 | struct svm_init_data { | |
471 | int cpu; | |
472 | int r; | |
473 | }; | |
474 | ||
09941fbb | 475 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 476 | |
9d8f549d | 477 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
478 | #define MSRS_RANGE_SIZE 2048 |
479 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
480 | ||
455716fa JR |
481 | static u32 svm_msrpm_offset(u32 msr) |
482 | { | |
483 | u32 offset; | |
484 | int i; | |
485 | ||
486 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
487 | if (msr < msrpm_ranges[i] || | |
488 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
489 | continue; | |
490 | ||
491 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
492 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
493 | ||
494 | /* Now we have the u8 offset - but need the u32 offset */ | |
495 | return offset / 4; | |
496 | } | |
497 | ||
498 | /* MSR not in any range */ | |
499 | return MSR_INVALID; | |
500 | } | |
501 | ||
6aa8b732 AK |
502 | #define MAX_INST_SIZE 15 |
503 | ||
6aa8b732 AK |
504 | static inline void clgi(void) |
505 | { | |
4ecac3fd | 506 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
507 | } |
508 | ||
509 | static inline void stgi(void) | |
510 | { | |
4ecac3fd | 511 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
512 | } |
513 | ||
514 | static inline void invlpga(unsigned long addr, u32 asid) | |
515 | { | |
e0231715 | 516 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
517 | } |
518 | ||
4b16184c JR |
519 | static int get_npt_level(void) |
520 | { | |
521 | #ifdef CONFIG_X86_64 | |
522 | return PT64_ROOT_LEVEL; | |
523 | #else | |
524 | return PT32E_ROOT_LEVEL; | |
525 | #endif | |
526 | } | |
527 | ||
6aa8b732 AK |
528 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
529 | { | |
6dc696d4 | 530 | vcpu->arch.efer = efer; |
709ddebf | 531 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 532 | efer &= ~EFER_LME; |
6aa8b732 | 533 | |
9962d032 | 534 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 535 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
536 | } |
537 | ||
6aa8b732 AK |
538 | static int is_external_interrupt(u32 info) |
539 | { | |
540 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
541 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
542 | } | |
543 | ||
37ccdcbe | 544 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
545 | { |
546 | struct vcpu_svm *svm = to_svm(vcpu); | |
547 | u32 ret = 0; | |
548 | ||
549 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
37ccdcbe PB |
550 | ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
551 | return ret; | |
2809f5d2 GC |
552 | } |
553 | ||
554 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
555 | { | |
556 | struct vcpu_svm *svm = to_svm(vcpu); | |
557 | ||
558 | if (mask == 0) | |
559 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
560 | else | |
561 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
562 | ||
563 | } | |
564 | ||
6aa8b732 AK |
565 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
566 | { | |
a2fa3e9f GH |
567 | struct vcpu_svm *svm = to_svm(vcpu); |
568 | ||
f104765b | 569 | if (svm->vmcb->control.next_rip != 0) { |
d2922422 | 570 | WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS)); |
6bc31bdc | 571 | svm->next_rip = svm->vmcb->control.next_rip; |
f104765b | 572 | } |
6bc31bdc | 573 | |
a2fa3e9f | 574 | if (!svm->next_rip) { |
51d8b661 | 575 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
576 | EMULATE_DONE) |
577 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
578 | return; |
579 | } | |
5fdbf976 MT |
580 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
581 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
582 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 583 | |
5fdbf976 | 584 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 585 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
586 | } |
587 | ||
116a4752 | 588 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
589 | bool has_error_code, u32 error_code, |
590 | bool reinject) | |
116a4752 JK |
591 | { |
592 | struct vcpu_svm *svm = to_svm(vcpu); | |
593 | ||
e0231715 JR |
594 | /* |
595 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
596 | * handle the exception | |
597 | */ | |
ce7ddec4 JR |
598 | if (!reinject && |
599 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
600 | return; |
601 | ||
2a6b20b8 | 602 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
603 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
604 | ||
605 | /* | |
606 | * For guest debugging where we have to reinject #BP if some | |
607 | * INT3 is guest-owned: | |
608 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
609 | * raises a fault that is not intercepted. Still better than | |
610 | * failing in all cases. | |
611 | */ | |
612 | skip_emulated_instruction(&svm->vcpu); | |
613 | rip = kvm_rip_read(&svm->vcpu); | |
614 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
615 | svm->int3_injected = rip - old_rip; | |
616 | } | |
617 | ||
116a4752 JK |
618 | svm->vmcb->control.event_inj = nr |
619 | | SVM_EVTINJ_VALID | |
620 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
621 | | SVM_EVTINJ_TYPE_EXEPT; | |
622 | svm->vmcb->control.event_inj_err = error_code; | |
623 | } | |
624 | ||
67ec6607 JR |
625 | static void svm_init_erratum_383(void) |
626 | { | |
627 | u32 low, high; | |
628 | int err; | |
629 | u64 val; | |
630 | ||
e6ee94d5 | 631 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
632 | return; |
633 | ||
634 | /* Use _safe variants to not break nested virtualization */ | |
635 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
636 | if (err) | |
637 | return; | |
638 | ||
639 | val |= (1ULL << 47); | |
640 | ||
641 | low = lower_32_bits(val); | |
642 | high = upper_32_bits(val); | |
643 | ||
644 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
645 | ||
646 | erratum_383_found = true; | |
647 | } | |
648 | ||
2b036c6b BO |
649 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
650 | { | |
651 | /* | |
652 | * Guests should see errata 400 and 415 as fixed (assuming that | |
653 | * HLT and IO instructions are intercepted). | |
654 | */ | |
655 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
656 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
657 | ||
658 | /* | |
659 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
660 | * all osvw.status bits inside that length, including bit 0 (which is | |
661 | * reserved for erratum 298), are valid. However, if host processor's | |
662 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
663 | * be conservative here and therefore we tell the guest that erratum 298 | |
664 | * is present (because we really don't know). | |
665 | */ | |
666 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
667 | vcpu->arch.osvw.status |= 1; | |
668 | } | |
669 | ||
6aa8b732 AK |
670 | static int has_svm(void) |
671 | { | |
63d1142f | 672 | const char *msg; |
6aa8b732 | 673 | |
63d1142f | 674 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 675 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
676 | return 0; |
677 | } | |
678 | ||
6aa8b732 AK |
679 | return 1; |
680 | } | |
681 | ||
13a34e06 | 682 | static void svm_hardware_disable(void) |
6aa8b732 | 683 | { |
fbc0db76 JR |
684 | /* Make sure we clean up behind us */ |
685 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
686 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
687 | ||
2c8dceeb | 688 | cpu_svm_disable(); |
1018faa6 JR |
689 | |
690 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
691 | } |
692 | ||
13a34e06 | 693 | static int svm_hardware_enable(void) |
6aa8b732 AK |
694 | { |
695 | ||
0fe1e009 | 696 | struct svm_cpu_data *sd; |
6aa8b732 | 697 | uint64_t efer; |
89a27f4d | 698 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
699 | struct desc_struct *gdt; |
700 | int me = raw_smp_processor_id(); | |
701 | ||
10474ae8 AG |
702 | rdmsrl(MSR_EFER, efer); |
703 | if (efer & EFER_SVME) | |
704 | return -EBUSY; | |
705 | ||
6aa8b732 | 706 | if (!has_svm()) { |
1f5b77f5 | 707 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 708 | return -EINVAL; |
6aa8b732 | 709 | } |
0fe1e009 | 710 | sd = per_cpu(svm_data, me); |
0fe1e009 | 711 | if (!sd) { |
1f5b77f5 | 712 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 713 | return -EINVAL; |
6aa8b732 AK |
714 | } |
715 | ||
0fe1e009 TH |
716 | sd->asid_generation = 1; |
717 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
718 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 719 | |
d6ab1ed4 | 720 | native_store_gdt(&gdt_descr); |
89a27f4d | 721 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 722 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 723 | |
9962d032 | 724 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 725 | |
d0316554 | 726 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 727 | |
fbc0db76 JR |
728 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
729 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
89cbc767 | 730 | __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT); |
fbc0db76 JR |
731 | } |
732 | ||
2b036c6b BO |
733 | |
734 | /* | |
735 | * Get OSVW bits. | |
736 | * | |
737 | * Note that it is possible to have a system with mixed processor | |
738 | * revisions and therefore different OSVW bits. If bits are not the same | |
739 | * on different processors then choose the worst case (i.e. if erratum | |
740 | * is present on one processor and not on another then assume that the | |
741 | * erratum is present everywhere). | |
742 | */ | |
743 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
744 | uint64_t len, status = 0; | |
745 | int err; | |
746 | ||
747 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
748 | if (!err) | |
749 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
750 | &err); | |
751 | ||
752 | if (err) | |
753 | osvw_status = osvw_len = 0; | |
754 | else { | |
755 | if (len < osvw_len) | |
756 | osvw_len = len; | |
757 | osvw_status |= status; | |
758 | osvw_status &= (1ULL << osvw_len) - 1; | |
759 | } | |
760 | } else | |
761 | osvw_status = osvw_len = 0; | |
762 | ||
67ec6607 JR |
763 | svm_init_erratum_383(); |
764 | ||
1018faa6 JR |
765 | amd_pmu_enable_virt(); |
766 | ||
10474ae8 | 767 | return 0; |
6aa8b732 AK |
768 | } |
769 | ||
0da1db75 JR |
770 | static void svm_cpu_uninit(int cpu) |
771 | { | |
0fe1e009 | 772 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 773 | |
0fe1e009 | 774 | if (!sd) |
0da1db75 JR |
775 | return; |
776 | ||
777 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
778 | __free_page(sd->save_area); |
779 | kfree(sd); | |
0da1db75 JR |
780 | } |
781 | ||
6aa8b732 AK |
782 | static int svm_cpu_init(int cpu) |
783 | { | |
0fe1e009 | 784 | struct svm_cpu_data *sd; |
6aa8b732 AK |
785 | int r; |
786 | ||
0fe1e009 TH |
787 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
788 | if (!sd) | |
6aa8b732 | 789 | return -ENOMEM; |
0fe1e009 TH |
790 | sd->cpu = cpu; |
791 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 792 | r = -ENOMEM; |
0fe1e009 | 793 | if (!sd->save_area) |
6aa8b732 AK |
794 | goto err_1; |
795 | ||
0fe1e009 | 796 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
797 | |
798 | return 0; | |
799 | ||
800 | err_1: | |
0fe1e009 | 801 | kfree(sd); |
6aa8b732 AK |
802 | return r; |
803 | ||
804 | } | |
805 | ||
ac72a9b7 JR |
806 | static bool valid_msr_intercept(u32 index) |
807 | { | |
808 | int i; | |
809 | ||
810 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
811 | if (direct_access_msrs[i].index == index) | |
812 | return true; | |
813 | ||
814 | return false; | |
815 | } | |
816 | ||
bfc733a7 RR |
817 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
818 | int read, int write) | |
6aa8b732 | 819 | { |
455716fa JR |
820 | u8 bit_read, bit_write; |
821 | unsigned long tmp; | |
822 | u32 offset; | |
6aa8b732 | 823 | |
ac72a9b7 JR |
824 | /* |
825 | * If this warning triggers extend the direct_access_msrs list at the | |
826 | * beginning of the file | |
827 | */ | |
828 | WARN_ON(!valid_msr_intercept(msr)); | |
829 | ||
455716fa JR |
830 | offset = svm_msrpm_offset(msr); |
831 | bit_read = 2 * (msr & 0x0f); | |
832 | bit_write = 2 * (msr & 0x0f) + 1; | |
833 | tmp = msrpm[offset]; | |
834 | ||
835 | BUG_ON(offset == MSR_INVALID); | |
836 | ||
837 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
838 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
839 | ||
840 | msrpm[offset] = tmp; | |
6aa8b732 AK |
841 | } |
842 | ||
f65c229c | 843 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
844 | { |
845 | int i; | |
846 | ||
f65c229c JR |
847 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
848 | ||
ac72a9b7 JR |
849 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
850 | if (!direct_access_msrs[i].always) | |
851 | continue; | |
852 | ||
853 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
854 | } | |
f65c229c JR |
855 | } |
856 | ||
323c3d80 JR |
857 | static void add_msr_offset(u32 offset) |
858 | { | |
859 | int i; | |
860 | ||
861 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
862 | ||
863 | /* Offset already in list? */ | |
864 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 865 | return; |
323c3d80 JR |
866 | |
867 | /* Slot used by another offset? */ | |
868 | if (msrpm_offsets[i] != MSR_INVALID) | |
869 | continue; | |
870 | ||
871 | /* Add offset to list */ | |
872 | msrpm_offsets[i] = offset; | |
873 | ||
874 | return; | |
6aa8b732 | 875 | } |
323c3d80 JR |
876 | |
877 | /* | |
878 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
879 | * increase MSRPM_OFFSETS in this case. | |
880 | */ | |
bfc733a7 | 881 | BUG(); |
6aa8b732 AK |
882 | } |
883 | ||
323c3d80 | 884 | static void init_msrpm_offsets(void) |
f65c229c | 885 | { |
323c3d80 | 886 | int i; |
f65c229c | 887 | |
323c3d80 JR |
888 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
889 | ||
890 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
891 | u32 offset; | |
892 | ||
893 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
894 | BUG_ON(offset == MSR_INVALID); | |
895 | ||
896 | add_msr_offset(offset); | |
897 | } | |
f65c229c JR |
898 | } |
899 | ||
24e09cbf JR |
900 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
901 | { | |
902 | u32 *msrpm = svm->msrpm; | |
903 | ||
904 | svm->vmcb->control.lbr_ctl = 1; | |
905 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
906 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
907 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
908 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
909 | } | |
910 | ||
911 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
912 | { | |
913 | u32 *msrpm = svm->msrpm; | |
914 | ||
915 | svm->vmcb->control.lbr_ctl = 0; | |
916 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
917 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
918 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
919 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
920 | } | |
921 | ||
6aa8b732 AK |
922 | static __init int svm_hardware_setup(void) |
923 | { | |
924 | int cpu; | |
925 | struct page *iopm_pages; | |
f65c229c | 926 | void *iopm_va; |
6aa8b732 AK |
927 | int r; |
928 | ||
6aa8b732 AK |
929 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
930 | ||
931 | if (!iopm_pages) | |
932 | return -ENOMEM; | |
c8681339 AL |
933 | |
934 | iopm_va = page_address(iopm_pages); | |
935 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
936 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
937 | ||
323c3d80 JR |
938 | init_msrpm_offsets(); |
939 | ||
50a37eb4 JR |
940 | if (boot_cpu_has(X86_FEATURE_NX)) |
941 | kvm_enable_efer_bits(EFER_NX); | |
942 | ||
1b2fd70c AG |
943 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
944 | kvm_enable_efer_bits(EFER_FFXSR); | |
945 | ||
92a1f12d | 946 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
92a1f12d | 947 | kvm_has_tsc_control = true; |
bc9b961b HZ |
948 | kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX; |
949 | kvm_tsc_scaling_ratio_frac_bits = 32; | |
92a1f12d JR |
950 | } |
951 | ||
236de055 AG |
952 | if (nested) { |
953 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 954 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
955 | } |
956 | ||
3230bb47 | 957 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
958 | r = svm_cpu_init(cpu); |
959 | if (r) | |
f65c229c | 960 | goto err; |
6aa8b732 | 961 | } |
33bd6a0b | 962 | |
2a6b20b8 | 963 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
964 | npt_enabled = false; |
965 | ||
6c7dac72 JR |
966 | if (npt_enabled && !npt) { |
967 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
968 | npt_enabled = false; | |
969 | } | |
970 | ||
18552672 | 971 | if (npt_enabled) { |
e3da3acd | 972 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 973 | kvm_enable_tdp(); |
5f4cb662 JR |
974 | } else |
975 | kvm_disable_tdp(); | |
e3da3acd | 976 | |
44a95dae SS |
977 | if (avic && (!npt_enabled || !boot_cpu_has(X86_FEATURE_AVIC))) |
978 | avic = false; | |
979 | ||
980 | if (avic) | |
981 | pr_info("AVIC enabled\n"); | |
982 | ||
6aa8b732 AK |
983 | return 0; |
984 | ||
f65c229c | 985 | err: |
6aa8b732 AK |
986 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
987 | iopm_base = 0; | |
988 | return r; | |
989 | } | |
990 | ||
991 | static __exit void svm_hardware_unsetup(void) | |
992 | { | |
0da1db75 JR |
993 | int cpu; |
994 | ||
3230bb47 | 995 | for_each_possible_cpu(cpu) |
0da1db75 JR |
996 | svm_cpu_uninit(cpu); |
997 | ||
6aa8b732 | 998 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 999 | iopm_base = 0; |
6aa8b732 AK |
1000 | } |
1001 | ||
1002 | static void init_seg(struct vmcb_seg *seg) | |
1003 | { | |
1004 | seg->selector = 0; | |
1005 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 1006 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
1007 | seg->limit = 0xffff; |
1008 | seg->base = 0; | |
1009 | } | |
1010 | ||
1011 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
1012 | { | |
1013 | seg->selector = 0; | |
1014 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
1015 | seg->limit = 0xffff; | |
1016 | seg->base = 0; | |
1017 | } | |
1018 | ||
ba904635 WA |
1019 | static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu) |
1020 | { | |
1021 | struct vcpu_svm *svm = to_svm(vcpu); | |
1022 | ||
1023 | return svm->vmcb->control.tsc_offset; | |
1024 | } | |
1025 | ||
f4e1b3c8 ZA |
1026 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1027 | { | |
1028 | struct vcpu_svm *svm = to_svm(vcpu); | |
1029 | u64 g_tsc_offset = 0; | |
1030 | ||
2030753d | 1031 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
1032 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1033 | svm->nested.hsave->control.tsc_offset; | |
1034 | svm->nested.hsave->control.tsc_offset = offset; | |
489223ed YY |
1035 | } else |
1036 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1037 | svm->vmcb->control.tsc_offset, | |
1038 | offset); | |
f4e1b3c8 ZA |
1039 | |
1040 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1041 | |
1042 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
1043 | } |
1044 | ||
58ea6767 | 1045 | static void svm_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment) |
e48672fa ZA |
1046 | { |
1047 | struct vcpu_svm *svm = to_svm(vcpu); | |
1048 | ||
1049 | svm->vmcb->control.tsc_offset += adjustment; | |
2030753d | 1050 | if (is_guest_mode(vcpu)) |
e48672fa | 1051 | svm->nested.hsave->control.tsc_offset += adjustment; |
489223ed YY |
1052 | else |
1053 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1054 | svm->vmcb->control.tsc_offset - adjustment, | |
1055 | svm->vmcb->control.tsc_offset); | |
1056 | ||
116a0a23 | 1057 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
e48672fa ZA |
1058 | } |
1059 | ||
44a95dae SS |
1060 | static void avic_init_vmcb(struct vcpu_svm *svm) |
1061 | { | |
1062 | struct vmcb *vmcb = svm->vmcb; | |
1063 | struct kvm_arch *vm_data = &svm->vcpu.kvm->arch; | |
1064 | phys_addr_t bpa = page_to_phys(svm->avic_backing_page); | |
1065 | phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page); | |
1066 | phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page); | |
1067 | ||
1068 | vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK; | |
1069 | vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK; | |
1070 | vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK; | |
1071 | vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT; | |
1072 | vmcb->control.int_ctl |= AVIC_ENABLE_MASK; | |
1073 | svm->vcpu.arch.apicv_active = true; | |
1074 | } | |
1075 | ||
5690891b | 1076 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1077 | { |
e6101a96 JR |
1078 | struct vmcb_control_area *control = &svm->vmcb->control; |
1079 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1080 | |
bff78274 | 1081 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 1082 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1083 | |
4ee546b4 RJ |
1084 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1085 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1086 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1087 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1088 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1089 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
1090 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1091 | |
5315c716 | 1092 | set_dr_intercepts(svm); |
6aa8b732 | 1093 | |
18c918c5 JR |
1094 | set_exception_intercept(svm, PF_VECTOR); |
1095 | set_exception_intercept(svm, UD_VECTOR); | |
1096 | set_exception_intercept(svm, MC_VECTOR); | |
54a20552 | 1097 | set_exception_intercept(svm, AC_VECTOR); |
cbdb967a | 1098 | set_exception_intercept(svm, DB_VECTOR); |
6aa8b732 | 1099 | |
8a05a1b8 JR |
1100 | set_intercept(svm, INTERCEPT_INTR); |
1101 | set_intercept(svm, INTERCEPT_NMI); | |
1102 | set_intercept(svm, INTERCEPT_SMI); | |
1103 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1104 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1105 | set_intercept(svm, INTERCEPT_CPUID); |
1106 | set_intercept(svm, INTERCEPT_INVD); | |
1107 | set_intercept(svm, INTERCEPT_HLT); | |
1108 | set_intercept(svm, INTERCEPT_INVLPG); | |
1109 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1110 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1111 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1112 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1113 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1114 | set_intercept(svm, INTERCEPT_VMRUN); | |
1115 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1116 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1117 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1118 | set_intercept(svm, INTERCEPT_STGI); | |
1119 | set_intercept(svm, INTERCEPT_CLGI); | |
1120 | set_intercept(svm, INTERCEPT_SKINIT); | |
1121 | set_intercept(svm, INTERCEPT_WBINVD); | |
1122 | set_intercept(svm, INTERCEPT_MONITOR); | |
1123 | set_intercept(svm, INTERCEPT_MWAIT); | |
81dd35d4 | 1124 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 AK |
1125 | |
1126 | control->iopm_base_pa = iopm_base; | |
f65c229c | 1127 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
1128 | control->int_ctl = V_INTR_MASKING_MASK; |
1129 | ||
1130 | init_seg(&save->es); | |
1131 | init_seg(&save->ss); | |
1132 | init_seg(&save->ds); | |
1133 | init_seg(&save->fs); | |
1134 | init_seg(&save->gs); | |
1135 | ||
1136 | save->cs.selector = 0xf000; | |
04b66839 | 1137 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1138 | /* Executable/Readable Code Segment */ |
1139 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1140 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1141 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1142 | |
1143 | save->gdtr.limit = 0xffff; | |
1144 | save->idtr.limit = 0xffff; | |
1145 | ||
1146 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1147 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1148 | ||
5690891b | 1149 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1150 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1151 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1152 | save->rip = 0x0000fff0; |
5fdbf976 | 1153 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1154 | |
e0231715 | 1155 | /* |
18fa000a | 1156 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
d28bc9dd | 1157 | * It also updates the guest-visible cr0 value. |
6aa8b732 | 1158 | */ |
79a8059d | 1159 | svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); |
ebae871a | 1160 | kvm_mmu_reset_context(&svm->vcpu); |
18fa000a | 1161 | |
66aee91a | 1162 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1163 | /* rdx = ?? */ |
709ddebf JR |
1164 | |
1165 | if (npt_enabled) { | |
1166 | /* Setup VMCB for Nested Paging */ | |
1167 | control->nested_ctl = 1; | |
8a05a1b8 | 1168 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1169 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1170 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1171 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
74545705 | 1172 | save->g_pat = svm->vcpu.arch.pat; |
709ddebf JR |
1173 | save->cr3 = 0; |
1174 | save->cr4 = 0; | |
1175 | } | |
f40f6a45 | 1176 | svm->asid_generation = 0; |
1371d904 | 1177 | |
e6aa9abd | 1178 | svm->nested.vmcb = 0; |
2af9194d JR |
1179 | svm->vcpu.arch.hflags = 0; |
1180 | ||
2a6b20b8 | 1181 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1182 | control->pause_filter_count = 3000; |
8a05a1b8 | 1183 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1184 | } |
1185 | ||
44a95dae SS |
1186 | if (avic) |
1187 | avic_init_vmcb(svm); | |
1188 | ||
8d28fec4 RJ |
1189 | mark_all_dirty(svm->vmcb); |
1190 | ||
2af9194d | 1191 | enable_gif(svm); |
44a95dae SS |
1192 | |
1193 | } | |
1194 | ||
1195 | static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index) | |
1196 | { | |
1197 | u64 *avic_physical_id_table; | |
1198 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
1199 | ||
1200 | if (index >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1201 | return NULL; | |
1202 | ||
1203 | avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page); | |
1204 | ||
1205 | return &avic_physical_id_table[index]; | |
1206 | } | |
1207 | ||
1208 | /** | |
1209 | * Note: | |
1210 | * AVIC hardware walks the nested page table to check permissions, | |
1211 | * but does not use the SPA address specified in the leaf page | |
1212 | * table entry since it uses address in the AVIC_BACKING_PAGE pointer | |
1213 | * field of the VMCB. Therefore, we set up the | |
1214 | * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here. | |
1215 | */ | |
1216 | static int avic_init_access_page(struct kvm_vcpu *vcpu) | |
1217 | { | |
1218 | struct kvm *kvm = vcpu->kvm; | |
1219 | int ret; | |
1220 | ||
1221 | if (kvm->arch.apic_access_page_done) | |
1222 | return 0; | |
1223 | ||
1224 | ret = x86_set_memory_region(kvm, | |
1225 | APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
1226 | APIC_DEFAULT_PHYS_BASE, | |
1227 | PAGE_SIZE); | |
1228 | if (ret) | |
1229 | return ret; | |
1230 | ||
1231 | kvm->arch.apic_access_page_done = true; | |
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | static int avic_init_backing_page(struct kvm_vcpu *vcpu) | |
1236 | { | |
1237 | int ret; | |
1238 | u64 *entry, new_entry; | |
1239 | int id = vcpu->vcpu_id; | |
1240 | struct vcpu_svm *svm = to_svm(vcpu); | |
1241 | ||
1242 | ret = avic_init_access_page(vcpu); | |
1243 | if (ret) | |
1244 | return ret; | |
1245 | ||
1246 | if (id >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1247 | return -EINVAL; | |
1248 | ||
1249 | if (!svm->vcpu.arch.apic->regs) | |
1250 | return -EINVAL; | |
1251 | ||
1252 | svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs); | |
1253 | ||
1254 | /* Setting AVIC backing page address in the phy APIC ID table */ | |
1255 | entry = avic_get_physical_id_entry(vcpu, id); | |
1256 | if (!entry) | |
1257 | return -EINVAL; | |
1258 | ||
1259 | new_entry = READ_ONCE(*entry); | |
1260 | new_entry = (page_to_phys(svm->avic_backing_page) & | |
1261 | AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) | | |
1262 | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; | |
1263 | WRITE_ONCE(*entry, new_entry); | |
1264 | ||
1265 | svm->avic_physical_id_cache = entry; | |
1266 | ||
1267 | return 0; | |
1268 | } | |
1269 | ||
1270 | static void avic_vm_destroy(struct kvm *kvm) | |
1271 | { | |
1272 | struct kvm_arch *vm_data = &kvm->arch; | |
1273 | ||
1274 | if (vm_data->avic_logical_id_table_page) | |
1275 | __free_page(vm_data->avic_logical_id_table_page); | |
1276 | if (vm_data->avic_physical_id_table_page) | |
1277 | __free_page(vm_data->avic_physical_id_table_page); | |
1278 | } | |
1279 | ||
1280 | static int avic_vm_init(struct kvm *kvm) | |
1281 | { | |
1282 | int err = -ENOMEM; | |
1283 | struct kvm_arch *vm_data = &kvm->arch; | |
1284 | struct page *p_page; | |
1285 | struct page *l_page; | |
1286 | ||
1287 | if (!avic) | |
1288 | return 0; | |
1289 | ||
1290 | /* Allocating physical APIC ID table (4KB) */ | |
1291 | p_page = alloc_page(GFP_KERNEL); | |
1292 | if (!p_page) | |
1293 | goto free_avic; | |
1294 | ||
1295 | vm_data->avic_physical_id_table_page = p_page; | |
1296 | clear_page(page_address(p_page)); | |
1297 | ||
1298 | /* Allocating logical APIC ID table (4KB) */ | |
1299 | l_page = alloc_page(GFP_KERNEL); | |
1300 | if (!l_page) | |
1301 | goto free_avic; | |
1302 | ||
1303 | vm_data->avic_logical_id_table_page = l_page; | |
1304 | clear_page(page_address(l_page)); | |
1305 | ||
1306 | return 0; | |
1307 | ||
1308 | free_avic: | |
1309 | avic_vm_destroy(kvm); | |
1310 | return err; | |
6aa8b732 AK |
1311 | } |
1312 | ||
d28bc9dd | 1313 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
04d2cc77 AK |
1314 | { |
1315 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
1316 | u32 dummy; |
1317 | u32 eax = 1; | |
04d2cc77 | 1318 | |
d28bc9dd NA |
1319 | if (!init_event) { |
1320 | svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE | | |
1321 | MSR_IA32_APICBASE_ENABLE; | |
1322 | if (kvm_vcpu_is_reset_bsp(&svm->vcpu)) | |
1323 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; | |
1324 | } | |
5690891b | 1325 | init_vmcb(svm); |
70433389 | 1326 | |
66f7b72e JS |
1327 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy); |
1328 | kvm_register_write(vcpu, VCPU_REGS_RDX, eax); | |
44a95dae SS |
1329 | |
1330 | if (kvm_vcpu_apicv_active(vcpu) && !init_event) | |
1331 | avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE); | |
04d2cc77 AK |
1332 | } |
1333 | ||
fb3f0f51 | 1334 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1335 | { |
a2fa3e9f | 1336 | struct vcpu_svm *svm; |
6aa8b732 | 1337 | struct page *page; |
f65c229c | 1338 | struct page *msrpm_pages; |
b286d5d8 | 1339 | struct page *hsave_page; |
3d6368ef | 1340 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1341 | int err; |
6aa8b732 | 1342 | |
c16f862d | 1343 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1344 | if (!svm) { |
1345 | err = -ENOMEM; | |
1346 | goto out; | |
1347 | } | |
1348 | ||
1349 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
1350 | if (err) | |
1351 | goto free_svm; | |
1352 | ||
b7af4043 | 1353 | err = -ENOMEM; |
6aa8b732 | 1354 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1355 | if (!page) |
fb3f0f51 | 1356 | goto uninit; |
6aa8b732 | 1357 | |
f65c229c JR |
1358 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1359 | if (!msrpm_pages) | |
b7af4043 | 1360 | goto free_page1; |
3d6368ef AG |
1361 | |
1362 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1363 | if (!nested_msrpm_pages) | |
b7af4043 | 1364 | goto free_page2; |
f65c229c | 1365 | |
b286d5d8 AG |
1366 | hsave_page = alloc_page(GFP_KERNEL); |
1367 | if (!hsave_page) | |
b7af4043 TY |
1368 | goto free_page3; |
1369 | ||
44a95dae SS |
1370 | if (avic) { |
1371 | err = avic_init_backing_page(&svm->vcpu); | |
1372 | if (err) | |
1373 | goto free_page4; | |
1374 | } | |
1375 | ||
e6aa9abd | 1376 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1377 | |
b7af4043 TY |
1378 | svm->msrpm = page_address(msrpm_pages); |
1379 | svm_vcpu_init_msrpm(svm->msrpm); | |
1380 | ||
e6aa9abd | 1381 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1382 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1383 | |
a2fa3e9f GH |
1384 | svm->vmcb = page_address(page); |
1385 | clear_page(svm->vmcb); | |
1386 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1387 | svm->asid_generation = 0; | |
5690891b | 1388 | init_vmcb(svm); |
6aa8b732 | 1389 | |
2b036c6b BO |
1390 | svm_init_osvw(&svm->vcpu); |
1391 | ||
fb3f0f51 | 1392 | return &svm->vcpu; |
36241b8c | 1393 | |
44a95dae SS |
1394 | free_page4: |
1395 | __free_page(hsave_page); | |
b7af4043 TY |
1396 | free_page3: |
1397 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1398 | free_page2: | |
1399 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1400 | free_page1: | |
1401 | __free_page(page); | |
fb3f0f51 RR |
1402 | uninit: |
1403 | kvm_vcpu_uninit(&svm->vcpu); | |
1404 | free_svm: | |
a4770347 | 1405 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1406 | out: |
1407 | return ERR_PTR(err); | |
6aa8b732 AK |
1408 | } |
1409 | ||
1410 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1411 | { | |
a2fa3e9f GH |
1412 | struct vcpu_svm *svm = to_svm(vcpu); |
1413 | ||
fb3f0f51 | 1414 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1415 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1416 | __free_page(virt_to_page(svm->nested.hsave)); |
1417 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1418 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1419 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1420 | } |
1421 | ||
15ad7146 | 1422 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1423 | { |
a2fa3e9f | 1424 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1425 | int i; |
0cc5064d | 1426 | |
0cc5064d | 1427 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1428 | svm->asid_generation = 0; |
8d28fec4 | 1429 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1430 | } |
94dfbdb3 | 1431 | |
82ca2d10 AK |
1432 | #ifdef CONFIG_X86_64 |
1433 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1434 | #endif | |
dacccfdd AK |
1435 | savesegment(fs, svm->host.fs); |
1436 | savesegment(gs, svm->host.gs); | |
1437 | svm->host.ldt = kvm_read_ldt(); | |
1438 | ||
94dfbdb3 | 1439 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1440 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 | 1441 | |
ad721883 HZ |
1442 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
1443 | u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio; | |
1444 | if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) { | |
1445 | __this_cpu_write(current_tsc_ratio, tsc_ratio); | |
1446 | wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio); | |
1447 | } | |
fbc0db76 | 1448 | } |
46896c73 PB |
1449 | /* This assumes that the kernel never uses MSR_TSC_AUX */ |
1450 | if (static_cpu_has(X86_FEATURE_RDTSCP)) | |
1451 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
6aa8b732 AK |
1452 | } |
1453 | ||
1454 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1455 | { | |
a2fa3e9f | 1456 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1457 | int i; |
1458 | ||
e1beb1d3 | 1459 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1460 | kvm_load_ldt(svm->host.ldt); |
1461 | #ifdef CONFIG_X86_64 | |
1462 | loadsegment(fs, svm->host.fs); | |
dacccfdd | 1463 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); |
893a5ab6 | 1464 | load_gs_index(svm->host.gs); |
dacccfdd | 1465 | #else |
831ca609 | 1466 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1467 | loadsegment(gs, svm->host.gs); |
831ca609 | 1468 | #endif |
dacccfdd | 1469 | #endif |
94dfbdb3 | 1470 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1471 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1472 | } |
1473 | ||
6aa8b732 AK |
1474 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1475 | { | |
a2fa3e9f | 1476 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1477 | } |
1478 | ||
1479 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1480 | { | |
ae9fedc7 PB |
1481 | /* |
1482 | * Any change of EFLAGS.VM is accompained by a reload of SS | |
1483 | * (caused by either a task switch or an inter-privilege IRET), | |
1484 | * so we do not need to update the CPL here. | |
1485 | */ | |
a2fa3e9f | 1486 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1487 | } |
1488 | ||
be94f6b7 HH |
1489 | static u32 svm_get_pkru(struct kvm_vcpu *vcpu) |
1490 | { | |
1491 | return 0; | |
1492 | } | |
1493 | ||
6de4f3ad AK |
1494 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1495 | { | |
1496 | switch (reg) { | |
1497 | case VCPU_EXREG_PDPTR: | |
1498 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1499 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1500 | break; |
1501 | default: | |
1502 | BUG(); | |
1503 | } | |
1504 | } | |
1505 | ||
f0b85051 AG |
1506 | static void svm_set_vintr(struct vcpu_svm *svm) |
1507 | { | |
8a05a1b8 | 1508 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1509 | } |
1510 | ||
1511 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1512 | { | |
8a05a1b8 | 1513 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1514 | } |
1515 | ||
6aa8b732 AK |
1516 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1517 | { | |
a2fa3e9f | 1518 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1519 | |
1520 | switch (seg) { | |
1521 | case VCPU_SREG_CS: return &save->cs; | |
1522 | case VCPU_SREG_DS: return &save->ds; | |
1523 | case VCPU_SREG_ES: return &save->es; | |
1524 | case VCPU_SREG_FS: return &save->fs; | |
1525 | case VCPU_SREG_GS: return &save->gs; | |
1526 | case VCPU_SREG_SS: return &save->ss; | |
1527 | case VCPU_SREG_TR: return &save->tr; | |
1528 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1529 | } | |
1530 | BUG(); | |
8b6d44c7 | 1531 | return NULL; |
6aa8b732 AK |
1532 | } |
1533 | ||
1534 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1535 | { | |
1536 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1537 | ||
1538 | return s->base; | |
1539 | } | |
1540 | ||
1541 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1542 | struct kvm_segment *var, int seg) | |
1543 | { | |
1544 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1545 | ||
1546 | var->base = s->base; | |
1547 | var->limit = s->limit; | |
1548 | var->selector = s->selector; | |
1549 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1550 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1551 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1552 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1553 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1554 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1555 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
80112c89 JM |
1556 | |
1557 | /* | |
1558 | * AMD CPUs circa 2014 track the G bit for all segments except CS. | |
1559 | * However, the SVM spec states that the G bit is not observed by the | |
1560 | * CPU, and some VMware virtual CPUs drop the G bit for all segments. | |
1561 | * So let's synthesize a legal G bit for all segments, this helps | |
1562 | * running KVM nested. It also helps cross-vendor migration, because | |
1563 | * Intel's vmentry has a check on the 'G' bit. | |
1564 | */ | |
1565 | var->g = s->limit > 0xfffff; | |
25022acc | 1566 | |
e0231715 JR |
1567 | /* |
1568 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1569 | * for cross vendor migration purposes by "not present" |
1570 | */ | |
1571 | var->unusable = !var->present || (var->type == 0); | |
1572 | ||
1fbdc7a5 | 1573 | switch (seg) { |
1fbdc7a5 AP |
1574 | case VCPU_SREG_TR: |
1575 | /* | |
1576 | * Work around a bug where the busy flag in the tr selector | |
1577 | * isn't exposed | |
1578 | */ | |
c0d09828 | 1579 | var->type |= 0x2; |
1fbdc7a5 AP |
1580 | break; |
1581 | case VCPU_SREG_DS: | |
1582 | case VCPU_SREG_ES: | |
1583 | case VCPU_SREG_FS: | |
1584 | case VCPU_SREG_GS: | |
1585 | /* | |
1586 | * The accessed bit must always be set in the segment | |
1587 | * descriptor cache, although it can be cleared in the | |
1588 | * descriptor, the cached bit always remains at 1. Since | |
1589 | * Intel has a check on this, set it here to support | |
1590 | * cross-vendor migration. | |
1591 | */ | |
1592 | if (!var->unusable) | |
1593 | var->type |= 0x1; | |
1594 | break; | |
b586eb02 | 1595 | case VCPU_SREG_SS: |
e0231715 JR |
1596 | /* |
1597 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1598 | * descriptor is left as 1, although the whole segment has |
1599 | * been made unusable. Clear it here to pass an Intel VMX | |
1600 | * entry check when cross vendor migrating. | |
1601 | */ | |
1602 | if (var->unusable) | |
1603 | var->db = 0; | |
33b458d2 | 1604 | var->dpl = to_svm(vcpu)->vmcb->save.cpl; |
b586eb02 | 1605 | break; |
1fbdc7a5 | 1606 | } |
6aa8b732 AK |
1607 | } |
1608 | ||
2e4d2653 IE |
1609 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1610 | { | |
1611 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1612 | ||
1613 | return save->cpl; | |
1614 | } | |
1615 | ||
89a27f4d | 1616 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1617 | { |
a2fa3e9f GH |
1618 | struct vcpu_svm *svm = to_svm(vcpu); |
1619 | ||
89a27f4d GN |
1620 | dt->size = svm->vmcb->save.idtr.limit; |
1621 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1622 | } |
1623 | ||
89a27f4d | 1624 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1625 | { |
a2fa3e9f GH |
1626 | struct vcpu_svm *svm = to_svm(vcpu); |
1627 | ||
89a27f4d GN |
1628 | svm->vmcb->save.idtr.limit = dt->size; |
1629 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1630 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1631 | } |
1632 | ||
89a27f4d | 1633 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1634 | { |
a2fa3e9f GH |
1635 | struct vcpu_svm *svm = to_svm(vcpu); |
1636 | ||
89a27f4d GN |
1637 | dt->size = svm->vmcb->save.gdtr.limit; |
1638 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1639 | } |
1640 | ||
89a27f4d | 1641 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1642 | { |
a2fa3e9f GH |
1643 | struct vcpu_svm *svm = to_svm(vcpu); |
1644 | ||
89a27f4d GN |
1645 | svm->vmcb->save.gdtr.limit = dt->size; |
1646 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1647 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1648 | } |
1649 | ||
e8467fda AK |
1650 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1651 | { | |
1652 | } | |
1653 | ||
aff48baa AK |
1654 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1655 | { | |
1656 | } | |
1657 | ||
25c4c276 | 1658 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1659 | { |
1660 | } | |
1661 | ||
d225157b AK |
1662 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1663 | { | |
1664 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1665 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1666 | ||
1667 | if (!svm->vcpu.fpu_active) | |
1668 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1669 | else | |
1670 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1671 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1672 | ||
dcca1a65 | 1673 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b AK |
1674 | |
1675 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1676 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1677 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1678 | } else { |
4ee546b4 RJ |
1679 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1680 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1681 | } |
1682 | } | |
1683 | ||
6aa8b732 AK |
1684 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1685 | { | |
a2fa3e9f GH |
1686 | struct vcpu_svm *svm = to_svm(vcpu); |
1687 | ||
05b3e0c2 | 1688 | #ifdef CONFIG_X86_64 |
f6801dff | 1689 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1690 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1691 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1692 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1693 | } |
1694 | ||
d77c26fc | 1695 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1696 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1697 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1698 | } |
1699 | } | |
1700 | #endif | |
ad312c7c | 1701 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1702 | |
1703 | if (!npt_enabled) | |
1704 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1705 | |
1706 | if (!vcpu->fpu_active) | |
334df50a | 1707 | cr0 |= X86_CR0_TS; |
bcf166a9 PB |
1708 | /* |
1709 | * re-enable caching here because the QEMU bios | |
1710 | * does not do it - this results in some delay at | |
1711 | * reboot | |
1712 | */ | |
1713 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
1714 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1715 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1716 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1717 | update_cr0_intercept(svm); |
6aa8b732 AK |
1718 | } |
1719 | ||
5e1746d6 | 1720 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 1721 | { |
1e02ce4c | 1722 | unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE; |
e5eab0ce JR |
1723 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1724 | ||
5e1746d6 NHE |
1725 | if (cr4 & X86_CR4_VMXE) |
1726 | return 1; | |
1727 | ||
e5eab0ce | 1728 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 1729 | svm_flush_tlb(vcpu); |
6394b649 | 1730 | |
ec077263 JR |
1731 | vcpu->arch.cr4 = cr4; |
1732 | if (!npt_enabled) | |
1733 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1734 | cr4 |= host_cr4_mce; |
ec077263 | 1735 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1736 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 1737 | return 0; |
6aa8b732 AK |
1738 | } |
1739 | ||
1740 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1741 | struct kvm_segment *var, int seg) | |
1742 | { | |
a2fa3e9f | 1743 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1744 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1745 | ||
1746 | s->base = var->base; | |
1747 | s->limit = var->limit; | |
1748 | s->selector = var->selector; | |
1749 | if (var->unusable) | |
1750 | s->attrib = 0; | |
1751 | else { | |
1752 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1753 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1754 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1755 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1756 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1757 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1758 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1759 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1760 | } | |
ae9fedc7 PB |
1761 | |
1762 | /* | |
1763 | * This is always accurate, except if SYSRET returned to a segment | |
1764 | * with SS.DPL != 3. Intel does not have this quirk, and always | |
1765 | * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it | |
1766 | * would entail passing the CPL to userspace and back. | |
1767 | */ | |
1768 | if (seg == VCPU_SREG_SS) | |
1769 | svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
6aa8b732 | 1770 | |
060d0c9a | 1771 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
1772 | } |
1773 | ||
cbdb967a | 1774 | static void update_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1775 | { |
d0bfb940 JK |
1776 | struct vcpu_svm *svm = to_svm(vcpu); |
1777 | ||
18c918c5 | 1778 | clr_exception_intercept(svm, BP_VECTOR); |
44c11430 | 1779 | |
d0bfb940 | 1780 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
d0bfb940 | 1781 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1782 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1783 | } else |
1784 | vcpu->guest_debug = 0; | |
44c11430 GN |
1785 | } |
1786 | ||
0fe1e009 | 1787 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1788 | { |
0fe1e009 TH |
1789 | if (sd->next_asid > sd->max_asid) { |
1790 | ++sd->asid_generation; | |
1791 | sd->next_asid = 1; | |
a2fa3e9f | 1792 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1793 | } |
1794 | ||
0fe1e009 TH |
1795 | svm->asid_generation = sd->asid_generation; |
1796 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
1797 | |
1798 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
1799 | } |
1800 | ||
73aaf249 JK |
1801 | static u64 svm_get_dr6(struct kvm_vcpu *vcpu) |
1802 | { | |
1803 | return to_svm(vcpu)->vmcb->save.dr6; | |
1804 | } | |
1805 | ||
1806 | static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value) | |
1807 | { | |
1808 | struct vcpu_svm *svm = to_svm(vcpu); | |
1809 | ||
1810 | svm->vmcb->save.dr6 = value; | |
1811 | mark_dirty(svm->vmcb, VMCB_DR); | |
1812 | } | |
1813 | ||
facb0139 PB |
1814 | static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
1815 | { | |
1816 | struct vcpu_svm *svm = to_svm(vcpu); | |
1817 | ||
1818 | get_debugreg(vcpu->arch.db[0], 0); | |
1819 | get_debugreg(vcpu->arch.db[1], 1); | |
1820 | get_debugreg(vcpu->arch.db[2], 2); | |
1821 | get_debugreg(vcpu->arch.db[3], 3); | |
1822 | vcpu->arch.dr6 = svm_get_dr6(vcpu); | |
1823 | vcpu->arch.dr7 = svm->vmcb->save.dr7; | |
1824 | ||
1825 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
1826 | set_dr_intercepts(svm); | |
1827 | } | |
1828 | ||
020df079 | 1829 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1830 | { |
42dbaa5a | 1831 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1832 | |
020df079 | 1833 | svm->vmcb->save.dr7 = value; |
72214b96 | 1834 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
1835 | } |
1836 | ||
851ba692 | 1837 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1838 | { |
631bc487 | 1839 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1840 | u32 error_code; |
631bc487 | 1841 | int r = 1; |
6aa8b732 | 1842 | |
631bc487 GN |
1843 | switch (svm->apf_reason) { |
1844 | default: | |
1845 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1846 | |
631bc487 GN |
1847 | trace_kvm_page_fault(fault_address, error_code); |
1848 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1849 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
1850 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
1851 | svm->vmcb->control.insn_bytes, | |
1852 | svm->vmcb->control.insn_len); | |
631bc487 GN |
1853 | break; |
1854 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1855 | svm->apf_reason = 0; | |
1856 | local_irq_disable(); | |
1857 | kvm_async_pf_task_wait(fault_address); | |
1858 | local_irq_enable(); | |
1859 | break; | |
1860 | case KVM_PV_REASON_PAGE_READY: | |
1861 | svm->apf_reason = 0; | |
1862 | local_irq_disable(); | |
1863 | kvm_async_pf_task_wake(fault_address); | |
1864 | local_irq_enable(); | |
1865 | break; | |
1866 | } | |
1867 | return r; | |
6aa8b732 AK |
1868 | } |
1869 | ||
851ba692 | 1870 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1871 | { |
851ba692 AK |
1872 | struct kvm_run *kvm_run = svm->vcpu.run; |
1873 | ||
d0bfb940 | 1874 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1875 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1876 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1877 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1878 | return 1; | |
1879 | } | |
44c11430 | 1880 | |
6be7d306 JK |
1881 | if (svm->nmi_singlestep) { |
1882 | svm->nmi_singlestep = false; | |
44c11430 GN |
1883 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1884 | svm->vmcb->save.rflags &= | |
1885 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
44c11430 GN |
1886 | } |
1887 | ||
1888 | if (svm->vcpu.guest_debug & | |
e0231715 | 1889 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1890 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1891 | kvm_run->debug.arch.pc = | |
1892 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1893 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1894 | return 0; | |
1895 | } | |
1896 | ||
1897 | return 1; | |
d0bfb940 JK |
1898 | } |
1899 | ||
851ba692 | 1900 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1901 | { |
851ba692 AK |
1902 | struct kvm_run *kvm_run = svm->vcpu.run; |
1903 | ||
d0bfb940 JK |
1904 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1905 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1906 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1907 | return 0; | |
1908 | } | |
1909 | ||
851ba692 | 1910 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1911 | { |
1912 | int er; | |
1913 | ||
51d8b661 | 1914 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1915 | if (er != EMULATE_DONE) |
7ee5d940 | 1916 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1917 | return 1; |
1918 | } | |
1919 | ||
54a20552 EN |
1920 | static int ac_interception(struct vcpu_svm *svm) |
1921 | { | |
1922 | kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0); | |
1923 | return 1; | |
1924 | } | |
1925 | ||
6b52d186 | 1926 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1927 | { |
6b52d186 | 1928 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1929 | |
18c918c5 | 1930 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1931 | |
e756fc62 | 1932 | svm->vcpu.fpu_active = 1; |
d225157b | 1933 | update_cr0_intercept(svm); |
6b52d186 | 1934 | } |
a2fa3e9f | 1935 | |
6b52d186 AK |
1936 | static int nm_interception(struct vcpu_svm *svm) |
1937 | { | |
1938 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1939 | return 1; |
7807fa6c AL |
1940 | } |
1941 | ||
67ec6607 JR |
1942 | static bool is_erratum_383(void) |
1943 | { | |
1944 | int err, i; | |
1945 | u64 value; | |
1946 | ||
1947 | if (!erratum_383_found) | |
1948 | return false; | |
1949 | ||
1950 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1951 | if (err) | |
1952 | return false; | |
1953 | ||
1954 | /* Bit 62 may or may not be set for this mce */ | |
1955 | value &= ~(1ULL << 62); | |
1956 | ||
1957 | if (value != 0xb600000000010015ULL) | |
1958 | return false; | |
1959 | ||
1960 | /* Clear MCi_STATUS registers */ | |
1961 | for (i = 0; i < 6; ++i) | |
1962 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1963 | ||
1964 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1965 | if (!err) { | |
1966 | u32 low, high; | |
1967 | ||
1968 | value &= ~(1ULL << 2); | |
1969 | low = lower_32_bits(value); | |
1970 | high = upper_32_bits(value); | |
1971 | ||
1972 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1973 | } | |
1974 | ||
1975 | /* Flush tlb to evict multi-match entries */ | |
1976 | __flush_tlb_all(); | |
1977 | ||
1978 | return true; | |
1979 | } | |
1980 | ||
fe5913e4 | 1981 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1982 | { |
67ec6607 JR |
1983 | if (is_erratum_383()) { |
1984 | /* | |
1985 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1986 | * guest. | |
1987 | */ | |
1988 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1989 | ||
a8eeb04a | 1990 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1991 | |
1992 | return; | |
1993 | } | |
1994 | ||
53371b50 JR |
1995 | /* |
1996 | * On an #MC intercept the MCE handler is not called automatically in | |
1997 | * the host. So do it by hand here. | |
1998 | */ | |
1999 | asm volatile ( | |
2000 | "int $0x12\n"); | |
2001 | /* not sure if we ever come back to this point */ | |
2002 | ||
fe5913e4 JR |
2003 | return; |
2004 | } | |
2005 | ||
2006 | static int mc_interception(struct vcpu_svm *svm) | |
2007 | { | |
53371b50 JR |
2008 | return 1; |
2009 | } | |
2010 | ||
851ba692 | 2011 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 2012 | { |
851ba692 AK |
2013 | struct kvm_run *kvm_run = svm->vcpu.run; |
2014 | ||
46fe4ddd JR |
2015 | /* |
2016 | * VMCB is undefined after a SHUTDOWN intercept | |
2017 | * so reinitialize it. | |
2018 | */ | |
a2fa3e9f | 2019 | clear_page(svm->vmcb); |
5690891b | 2020 | init_vmcb(svm); |
46fe4ddd JR |
2021 | |
2022 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2023 | return 0; | |
2024 | } | |
2025 | ||
851ba692 | 2026 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 2027 | { |
cf8f70bf | 2028 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 2029 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 2030 | int size, in, string; |
039576c0 | 2031 | unsigned port; |
6aa8b732 | 2032 | |
e756fc62 | 2033 | ++svm->vcpu.stat.io_exits; |
e70669ab | 2034 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 2035 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 2036 | if (string || in) |
51d8b661 | 2037 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 2038 | |
039576c0 AK |
2039 | port = io_info >> 16; |
2040 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 2041 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 2042 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
2043 | |
2044 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
2045 | } |
2046 | ||
851ba692 | 2047 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
2048 | { |
2049 | return 1; | |
2050 | } | |
2051 | ||
851ba692 | 2052 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
2053 | { |
2054 | ++svm->vcpu.stat.irq_exits; | |
2055 | return 1; | |
2056 | } | |
2057 | ||
851ba692 | 2058 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
2059 | { |
2060 | return 1; | |
2061 | } | |
2062 | ||
851ba692 | 2063 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 2064 | { |
5fdbf976 | 2065 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 | 2066 | return kvm_emulate_halt(&svm->vcpu); |
6aa8b732 AK |
2067 | } |
2068 | ||
851ba692 | 2069 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 2070 | { |
5fdbf976 | 2071 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
0d9c055e | 2072 | return kvm_emulate_hypercall(&svm->vcpu); |
02e235bc AK |
2073 | } |
2074 | ||
5bd2edc3 JR |
2075 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
2076 | { | |
2077 | struct vcpu_svm *svm = to_svm(vcpu); | |
2078 | ||
2079 | return svm->nested.nested_cr3; | |
2080 | } | |
2081 | ||
e4e517b4 AK |
2082 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
2083 | { | |
2084 | struct vcpu_svm *svm = to_svm(vcpu); | |
2085 | u64 cr3 = svm->nested.nested_cr3; | |
2086 | u64 pdpte; | |
2087 | int ret; | |
2088 | ||
54bf36aa PB |
2089 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte, |
2090 | offset_in_page(cr3) + index * 8, 8); | |
e4e517b4 AK |
2091 | if (ret) |
2092 | return 0; | |
2093 | return pdpte; | |
2094 | } | |
2095 | ||
5bd2edc3 JR |
2096 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
2097 | unsigned long root) | |
2098 | { | |
2099 | struct vcpu_svm *svm = to_svm(vcpu); | |
2100 | ||
2101 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 2102 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 2103 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
2104 | } |
2105 | ||
6389ee94 AK |
2106 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
2107 | struct x86_exception *fault) | |
5bd2edc3 JR |
2108 | { |
2109 | struct vcpu_svm *svm = to_svm(vcpu); | |
2110 | ||
5e352519 PB |
2111 | if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) { |
2112 | /* | |
2113 | * TODO: track the cause of the nested page fault, and | |
2114 | * correctly fill in the high bits of exit_info_1. | |
2115 | */ | |
2116 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
2117 | svm->vmcb->control.exit_code_hi = 0; | |
2118 | svm->vmcb->control.exit_info_1 = (1ULL << 32); | |
2119 | svm->vmcb->control.exit_info_2 = fault->address; | |
2120 | } | |
2121 | ||
2122 | svm->vmcb->control.exit_info_1 &= ~0xffffffffULL; | |
2123 | svm->vmcb->control.exit_info_1 |= fault->error_code; | |
2124 | ||
2125 | /* | |
2126 | * The present bit is always zero for page structure faults on real | |
2127 | * hardware. | |
2128 | */ | |
2129 | if (svm->vmcb->control.exit_info_1 & (2ULL << 32)) | |
2130 | svm->vmcb->control.exit_info_1 &= ~1; | |
5bd2edc3 JR |
2131 | |
2132 | nested_svm_vmexit(svm); | |
2133 | } | |
2134 | ||
8a3c1a33 | 2135 | static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
4b16184c | 2136 | { |
ad896af0 PB |
2137 | WARN_ON(mmu_is_nested(vcpu)); |
2138 | kvm_init_shadow_mmu(vcpu); | |
4b16184c JR |
2139 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; |
2140 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 2141 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c JR |
2142 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
2143 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
c258b62b | 2144 | reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu); |
4b16184c | 2145 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; |
4b16184c JR |
2146 | } |
2147 | ||
2148 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
2149 | { | |
2150 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
2151 | } | |
2152 | ||
c0725420 AG |
2153 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
2154 | { | |
f6801dff | 2155 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
2156 | || !is_paging(&svm->vcpu)) { |
2157 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2158 | return 1; | |
2159 | } | |
2160 | ||
2161 | if (svm->vmcb->save.cpl) { | |
2162 | kvm_inject_gp(&svm->vcpu, 0); | |
2163 | return 1; | |
2164 | } | |
2165 | ||
2166 | return 0; | |
2167 | } | |
2168 | ||
cf74a78b AG |
2169 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
2170 | bool has_error_code, u32 error_code) | |
2171 | { | |
b8e88bc8 JR |
2172 | int vmexit; |
2173 | ||
2030753d | 2174 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 2175 | return 0; |
cf74a78b | 2176 | |
0295ad7d JR |
2177 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
2178 | svm->vmcb->control.exit_code_hi = 0; | |
2179 | svm->vmcb->control.exit_info_1 = error_code; | |
2180 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
2181 | ||
b8e88bc8 JR |
2182 | vmexit = nested_svm_intercept(svm); |
2183 | if (vmexit == NESTED_EXIT_DONE) | |
2184 | svm->nested.exit_required = true; | |
2185 | ||
2186 | return vmexit; | |
cf74a78b AG |
2187 | } |
2188 | ||
8fe54654 JR |
2189 | /* This function returns true if it is save to enable the irq window */ |
2190 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 2191 | { |
2030753d | 2192 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 2193 | return true; |
cf74a78b | 2194 | |
26666957 | 2195 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 2196 | return true; |
cf74a78b | 2197 | |
26666957 | 2198 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 2199 | return false; |
cf74a78b | 2200 | |
a0a07cd2 GN |
2201 | /* |
2202 | * if vmexit was already requested (by intercepted exception | |
2203 | * for instance) do not overwrite it with "external interrupt" | |
2204 | * vmexit. | |
2205 | */ | |
2206 | if (svm->nested.exit_required) | |
2207 | return false; | |
2208 | ||
197717d5 JR |
2209 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
2210 | svm->vmcb->control.exit_info_1 = 0; | |
2211 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 2212 | |
cd3ff653 JR |
2213 | if (svm->nested.intercept & 1ULL) { |
2214 | /* | |
2215 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 2216 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
2217 | * #vmexit emulation might sleep. Only signal request for |
2218 | * the #vmexit here. | |
2219 | */ | |
2220 | svm->nested.exit_required = true; | |
236649de | 2221 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2222 | return false; |
cf74a78b AG |
2223 | } |
2224 | ||
8fe54654 | 2225 | return true; |
cf74a78b AG |
2226 | } |
2227 | ||
887f500c JR |
2228 | /* This function returns true if it is save to enable the nmi window */ |
2229 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2230 | { | |
2030753d | 2231 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2232 | return true; |
2233 | ||
2234 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2235 | return true; | |
2236 | ||
2237 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2238 | svm->nested.exit_required = true; | |
2239 | ||
2240 | return false; | |
cf74a78b AG |
2241 | } |
2242 | ||
7597f129 | 2243 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2244 | { |
2245 | struct page *page; | |
2246 | ||
6c3bd3d7 JR |
2247 | might_sleep(); |
2248 | ||
54bf36aa | 2249 | page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2250 | if (is_error_page(page)) |
2251 | goto error; | |
2252 | ||
7597f129 JR |
2253 | *_page = page; |
2254 | ||
2255 | return kmap(page); | |
34f80cfa JR |
2256 | |
2257 | error: | |
34f80cfa JR |
2258 | kvm_inject_gp(&svm->vcpu, 0); |
2259 | ||
2260 | return NULL; | |
2261 | } | |
2262 | ||
7597f129 | 2263 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2264 | { |
7597f129 | 2265 | kunmap(page); |
34f80cfa JR |
2266 | kvm_release_page_dirty(page); |
2267 | } | |
34f80cfa | 2268 | |
ce2ac085 JR |
2269 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2270 | { | |
9bf41833 JK |
2271 | unsigned port, size, iopm_len; |
2272 | u16 val, mask; | |
2273 | u8 start_bit; | |
ce2ac085 | 2274 | u64 gpa; |
34f80cfa | 2275 | |
ce2ac085 JR |
2276 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2277 | return NESTED_EXIT_HOST; | |
34f80cfa | 2278 | |
ce2ac085 | 2279 | port = svm->vmcb->control.exit_info_1 >> 16; |
9bf41833 JK |
2280 | size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >> |
2281 | SVM_IOIO_SIZE_SHIFT; | |
ce2ac085 | 2282 | gpa = svm->nested.vmcb_iopm + (port / 8); |
9bf41833 JK |
2283 | start_bit = port % 8; |
2284 | iopm_len = (start_bit + size > 8) ? 2 : 1; | |
2285 | mask = (0xf >> (4 - size)) << start_bit; | |
2286 | val = 0; | |
ce2ac085 | 2287 | |
54bf36aa | 2288 | if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len)) |
9bf41833 | 2289 | return NESTED_EXIT_DONE; |
ce2ac085 | 2290 | |
9bf41833 | 2291 | return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
34f80cfa JR |
2292 | } |
2293 | ||
d2477826 | 2294 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2295 | { |
0d6b3537 JR |
2296 | u32 offset, msr, value; |
2297 | int write, mask; | |
4c2161ae | 2298 | |
3d62d9aa | 2299 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2300 | return NESTED_EXIT_HOST; |
3d62d9aa | 2301 | |
0d6b3537 JR |
2302 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2303 | offset = svm_msrpm_offset(msr); | |
2304 | write = svm->vmcb->control.exit_info_1 & 1; | |
2305 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2306 | |
0d6b3537 JR |
2307 | if (offset == MSR_INVALID) |
2308 | return NESTED_EXIT_DONE; | |
4c2161ae | 2309 | |
0d6b3537 JR |
2310 | /* Offset is in 32 bit units but need in 8 bit units */ |
2311 | offset *= 4; | |
4c2161ae | 2312 | |
54bf36aa | 2313 | if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4)) |
0d6b3537 | 2314 | return NESTED_EXIT_DONE; |
3d62d9aa | 2315 | |
0d6b3537 | 2316 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2317 | } |
2318 | ||
410e4d57 | 2319 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2320 | { |
cf74a78b | 2321 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2322 | |
410e4d57 JR |
2323 | switch (exit_code) { |
2324 | case SVM_EXIT_INTR: | |
2325 | case SVM_EXIT_NMI: | |
ff47a49b | 2326 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2327 | return NESTED_EXIT_HOST; |
410e4d57 | 2328 | case SVM_EXIT_NPF: |
e0231715 | 2329 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2330 | if (npt_enabled) |
2331 | return NESTED_EXIT_HOST; | |
2332 | break; | |
410e4d57 | 2333 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
2334 | /* When we're shadowing, trap PFs, but not async PF */ |
2335 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
2336 | return NESTED_EXIT_HOST; |
2337 | break; | |
66a562f7 JR |
2338 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
2339 | nm_interception(svm); | |
2340 | break; | |
410e4d57 JR |
2341 | default: |
2342 | break; | |
cf74a78b AG |
2343 | } |
2344 | ||
410e4d57 JR |
2345 | return NESTED_EXIT_CONTINUE; |
2346 | } | |
2347 | ||
2348 | /* | |
2349 | * If this function returns true, this #vmexit was already handled | |
2350 | */ | |
b8e88bc8 | 2351 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2352 | { |
2353 | u32 exit_code = svm->vmcb->control.exit_code; | |
2354 | int vmexit = NESTED_EXIT_HOST; | |
2355 | ||
cf74a78b | 2356 | switch (exit_code) { |
9c4e40b9 | 2357 | case SVM_EXIT_MSR: |
3d62d9aa | 2358 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2359 | break; |
ce2ac085 JR |
2360 | case SVM_EXIT_IOIO: |
2361 | vmexit = nested_svm_intercept_ioio(svm); | |
2362 | break; | |
4ee546b4 RJ |
2363 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2364 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2365 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2366 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2367 | break; |
2368 | } | |
3aed041a JR |
2369 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2370 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2371 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2372 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2373 | break; |
2374 | } | |
2375 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2376 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 2377 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 2378 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
2379 | /* async page fault always cause vmexit */ |
2380 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
2381 | svm->apf_reason != 0) | |
2382 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2383 | break; |
2384 | } | |
228070b1 JR |
2385 | case SVM_EXIT_ERR: { |
2386 | vmexit = NESTED_EXIT_DONE; | |
2387 | break; | |
2388 | } | |
cf74a78b AG |
2389 | default: { |
2390 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2391 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2392 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2393 | } |
2394 | } | |
2395 | ||
b8e88bc8 JR |
2396 | return vmexit; |
2397 | } | |
2398 | ||
2399 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2400 | { | |
2401 | int vmexit; | |
2402 | ||
2403 | vmexit = nested_svm_intercept(svm); | |
2404 | ||
2405 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2406 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2407 | |
2408 | return vmexit; | |
cf74a78b AG |
2409 | } |
2410 | ||
0460a979 JR |
2411 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2412 | { | |
2413 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2414 | struct vmcb_control_area *from = &from_vmcb->control; | |
2415 | ||
4ee546b4 | 2416 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2417 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2418 | dst->intercept_exceptions = from->intercept_exceptions; |
2419 | dst->intercept = from->intercept; | |
2420 | dst->iopm_base_pa = from->iopm_base_pa; | |
2421 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2422 | dst->tsc_offset = from->tsc_offset; | |
2423 | dst->asid = from->asid; | |
2424 | dst->tlb_ctl = from->tlb_ctl; | |
2425 | dst->int_ctl = from->int_ctl; | |
2426 | dst->int_vector = from->int_vector; | |
2427 | dst->int_state = from->int_state; | |
2428 | dst->exit_code = from->exit_code; | |
2429 | dst->exit_code_hi = from->exit_code_hi; | |
2430 | dst->exit_info_1 = from->exit_info_1; | |
2431 | dst->exit_info_2 = from->exit_info_2; | |
2432 | dst->exit_int_info = from->exit_int_info; | |
2433 | dst->exit_int_info_err = from->exit_int_info_err; | |
2434 | dst->nested_ctl = from->nested_ctl; | |
2435 | dst->event_inj = from->event_inj; | |
2436 | dst->event_inj_err = from->event_inj_err; | |
2437 | dst->nested_cr3 = from->nested_cr3; | |
2438 | dst->lbr_ctl = from->lbr_ctl; | |
2439 | } | |
2440 | ||
34f80cfa | 2441 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2442 | { |
34f80cfa | 2443 | struct vmcb *nested_vmcb; |
e6aa9abd | 2444 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2445 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2446 | struct page *page; |
cf74a78b | 2447 | |
17897f36 JR |
2448 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2449 | vmcb->control.exit_info_1, | |
2450 | vmcb->control.exit_info_2, | |
2451 | vmcb->control.exit_int_info, | |
e097e5ff SH |
2452 | vmcb->control.exit_int_info_err, |
2453 | KVM_ISA_SVM); | |
17897f36 | 2454 | |
7597f129 | 2455 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2456 | if (!nested_vmcb) |
2457 | return 1; | |
2458 | ||
2030753d JR |
2459 | /* Exit Guest-Mode */ |
2460 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2461 | svm->nested.vmcb = 0; |
2462 | ||
cf74a78b | 2463 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2464 | disable_gif(svm); |
2465 | ||
2466 | nested_vmcb->save.es = vmcb->save.es; | |
2467 | nested_vmcb->save.cs = vmcb->save.cs; | |
2468 | nested_vmcb->save.ss = vmcb->save.ss; | |
2469 | nested_vmcb->save.ds = vmcb->save.ds; | |
2470 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2471 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2472 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2473 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2474 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2475 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2476 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2477 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2478 | nested_vmcb->save.rip = vmcb->save.rip; |
2479 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2480 | nested_vmcb->save.rax = vmcb->save.rax; | |
2481 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2482 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2483 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2484 | ||
2485 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2486 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2487 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2488 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2489 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2490 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2491 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2492 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2493 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
6092d3d3 JR |
2494 | |
2495 | if (svm->nrips_enabled) | |
2496 | nested_vmcb->control.next_rip = vmcb->control.next_rip; | |
8d23c466 AG |
2497 | |
2498 | /* | |
2499 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2500 | * to make sure that we do not lose injected events. So check event_inj | |
2501 | * here and copy it to exit_int_info if it is valid. | |
2502 | * Exit_int_info and event_inj can't be both valid because the case | |
2503 | * below only happens on a VMRUN instruction intercept which has | |
2504 | * no valid exit_int_info set. | |
2505 | */ | |
2506 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2507 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2508 | ||
2509 | nc->exit_int_info = vmcb->control.event_inj; | |
2510 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2511 | } | |
2512 | ||
33740e40 JR |
2513 | nested_vmcb->control.tlb_ctl = 0; |
2514 | nested_vmcb->control.event_inj = 0; | |
2515 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2516 | |
2517 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2518 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2519 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2520 | ||
cf74a78b | 2521 | /* Restore the original control entries */ |
0460a979 | 2522 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2523 | |
219b65dc AG |
2524 | kvm_clear_exception_queue(&svm->vcpu); |
2525 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2526 | |
4b16184c JR |
2527 | svm->nested.nested_cr3 = 0; |
2528 | ||
cf74a78b AG |
2529 | /* Restore selected save entries */ |
2530 | svm->vmcb->save.es = hsave->save.es; | |
2531 | svm->vmcb->save.cs = hsave->save.cs; | |
2532 | svm->vmcb->save.ss = hsave->save.ss; | |
2533 | svm->vmcb->save.ds = hsave->save.ds; | |
2534 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2535 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2536 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2537 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2538 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2539 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2540 | if (npt_enabled) { | |
2541 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2542 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2543 | } else { | |
2390218b | 2544 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2545 | } |
2546 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2547 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2548 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2549 | svm->vmcb->save.dr7 = 0; | |
2550 | svm->vmcb->save.cpl = 0; | |
2551 | svm->vmcb->control.exit_int_info = 0; | |
2552 | ||
8d28fec4 RJ |
2553 | mark_all_dirty(svm->vmcb); |
2554 | ||
7597f129 | 2555 | nested_svm_unmap(page); |
cf74a78b | 2556 | |
4b16184c | 2557 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2558 | kvm_mmu_reset_context(&svm->vcpu); |
2559 | kvm_mmu_load(&svm->vcpu); | |
2560 | ||
2561 | return 0; | |
2562 | } | |
3d6368ef | 2563 | |
9738b2c9 | 2564 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2565 | { |
323c3d80 JR |
2566 | /* |
2567 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 2568 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
2569 | * the kvm msr permission bitmap may contain zero bits |
2570 | */ | |
3d6368ef | 2571 | int i; |
9738b2c9 | 2572 | |
323c3d80 JR |
2573 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2574 | return true; | |
9738b2c9 | 2575 | |
323c3d80 JR |
2576 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2577 | u32 value, p; | |
2578 | u64 offset; | |
9738b2c9 | 2579 | |
323c3d80 JR |
2580 | if (msrpm_offsets[i] == 0xffffffff) |
2581 | break; | |
3d6368ef | 2582 | |
0d6b3537 JR |
2583 | p = msrpm_offsets[i]; |
2584 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 | 2585 | |
54bf36aa | 2586 | if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4)) |
323c3d80 JR |
2587 | return false; |
2588 | ||
2589 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2590 | } | |
3d6368ef | 2591 | |
323c3d80 | 2592 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2593 | |
2594 | return true; | |
3d6368ef AG |
2595 | } |
2596 | ||
52c65a30 JR |
2597 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2598 | { | |
2599 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2600 | return false; | |
2601 | ||
dbe77584 JR |
2602 | if (vmcb->control.asid == 0) |
2603 | return false; | |
2604 | ||
4b16184c JR |
2605 | if (vmcb->control.nested_ctl && !npt_enabled) |
2606 | return false; | |
2607 | ||
52c65a30 JR |
2608 | return true; |
2609 | } | |
2610 | ||
9738b2c9 | 2611 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2612 | { |
9738b2c9 | 2613 | struct vmcb *nested_vmcb; |
e6aa9abd | 2614 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2615 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2616 | struct page *page; |
06fc7772 | 2617 | u64 vmcb_gpa; |
3d6368ef | 2618 | |
06fc7772 | 2619 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2620 | |
7597f129 | 2621 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2622 | if (!nested_vmcb) |
2623 | return false; | |
2624 | ||
52c65a30 JR |
2625 | if (!nested_vmcb_checks(nested_vmcb)) { |
2626 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2627 | nested_vmcb->control.exit_code_hi = 0; | |
2628 | nested_vmcb->control.exit_info_1 = 0; | |
2629 | nested_vmcb->control.exit_info_2 = 0; | |
2630 | ||
2631 | nested_svm_unmap(page); | |
2632 | ||
2633 | return false; | |
2634 | } | |
2635 | ||
b75f4eb3 | 2636 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2637 | nested_vmcb->save.rip, |
2638 | nested_vmcb->control.int_ctl, | |
2639 | nested_vmcb->control.event_inj, | |
2640 | nested_vmcb->control.nested_ctl); | |
2641 | ||
4ee546b4 RJ |
2642 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2643 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2644 | nested_vmcb->control.intercept_exceptions, |
2645 | nested_vmcb->control.intercept); | |
2646 | ||
3d6368ef | 2647 | /* Clear internal status */ |
219b65dc AG |
2648 | kvm_clear_exception_queue(&svm->vcpu); |
2649 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2650 | |
e0231715 JR |
2651 | /* |
2652 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2653 | * restore everything when a VMEXIT occurs | |
2654 | */ | |
defbba56 JR |
2655 | hsave->save.es = vmcb->save.es; |
2656 | hsave->save.cs = vmcb->save.cs; | |
2657 | hsave->save.ss = vmcb->save.ss; | |
2658 | hsave->save.ds = vmcb->save.ds; | |
2659 | hsave->save.gdtr = vmcb->save.gdtr; | |
2660 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2661 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2662 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 | 2663 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2664 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); |
b75f4eb3 | 2665 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2666 | hsave->save.rsp = vmcb->save.rsp; |
2667 | hsave->save.rax = vmcb->save.rax; | |
2668 | if (npt_enabled) | |
2669 | hsave->save.cr3 = vmcb->save.cr3; | |
2670 | else | |
9f8fe504 | 2671 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2672 | |
0460a979 | 2673 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef | 2674 | |
f6e78475 | 2675 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2676 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2677 | else | |
2678 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2679 | ||
4b16184c JR |
2680 | if (nested_vmcb->control.nested_ctl) { |
2681 | kvm_mmu_unload(&svm->vcpu); | |
2682 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2683 | nested_svm_init_mmu_context(&svm->vcpu); | |
2684 | } | |
2685 | ||
3d6368ef AG |
2686 | /* Load the nested guest state */ |
2687 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2688 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2689 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2690 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2691 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2692 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2693 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2694 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
2695 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2696 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2697 | if (npt_enabled) { | |
2698 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2699 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2700 | } else |
2390218b | 2701 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2702 | |
2703 | /* Guest paging mode is active - reset mmu */ | |
2704 | kvm_mmu_reset_context(&svm->vcpu); | |
2705 | ||
defbba56 | 2706 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2707 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2708 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2709 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2710 | |
3d6368ef AG |
2711 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2712 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2713 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2714 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2715 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2716 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2717 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2718 | ||
f7138538 | 2719 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2720 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2721 | |
aad42c64 | 2722 | /* cache intercepts */ |
4ee546b4 | 2723 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2724 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2725 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2726 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2727 | ||
f40f6a45 | 2728 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2729 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2730 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2731 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2732 | else | |
2733 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2734 | ||
88ab24ad JR |
2735 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2736 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2737 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2738 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2739 | } |
2740 | ||
0d945bd9 | 2741 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2742 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2743 | |
88ab24ad | 2744 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2745 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2746 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2747 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2748 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2749 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2750 | ||
7597f129 | 2751 | nested_svm_unmap(page); |
9738b2c9 | 2752 | |
2030753d JR |
2753 | /* Enter Guest-Mode */ |
2754 | enter_guest_mode(&svm->vcpu); | |
2755 | ||
384c6368 JR |
2756 | /* |
2757 | * Merge guest and host intercepts - must be called with vcpu in | |
2758 | * guest-mode to take affect here | |
2759 | */ | |
2760 | recalc_intercepts(svm); | |
2761 | ||
06fc7772 | 2762 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2763 | |
2af9194d | 2764 | enable_gif(svm); |
3d6368ef | 2765 | |
8d28fec4 RJ |
2766 | mark_all_dirty(svm->vmcb); |
2767 | ||
9738b2c9 | 2768 | return true; |
3d6368ef AG |
2769 | } |
2770 | ||
9966bf68 | 2771 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2772 | { |
2773 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2774 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2775 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2776 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2777 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2778 | to_vmcb->save.star = from_vmcb->save.star; | |
2779 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2780 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2781 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2782 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2783 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2784 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2785 | } |
2786 | ||
851ba692 | 2787 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2788 | { |
9966bf68 | 2789 | struct vmcb *nested_vmcb; |
7597f129 | 2790 | struct page *page; |
9966bf68 | 2791 | |
5542675b AG |
2792 | if (nested_svm_check_permissions(svm)) |
2793 | return 1; | |
2794 | ||
7597f129 | 2795 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2796 | if (!nested_vmcb) |
2797 | return 1; | |
2798 | ||
e3e9ed3d JR |
2799 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2800 | skip_emulated_instruction(&svm->vcpu); | |
2801 | ||
9966bf68 | 2802 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 2803 | nested_svm_unmap(page); |
5542675b AG |
2804 | |
2805 | return 1; | |
2806 | } | |
2807 | ||
851ba692 | 2808 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2809 | { |
9966bf68 | 2810 | struct vmcb *nested_vmcb; |
7597f129 | 2811 | struct page *page; |
9966bf68 | 2812 | |
5542675b AG |
2813 | if (nested_svm_check_permissions(svm)) |
2814 | return 1; | |
2815 | ||
7597f129 | 2816 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2817 | if (!nested_vmcb) |
2818 | return 1; | |
2819 | ||
e3e9ed3d JR |
2820 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2821 | skip_emulated_instruction(&svm->vcpu); | |
2822 | ||
9966bf68 | 2823 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 2824 | nested_svm_unmap(page); |
5542675b AG |
2825 | |
2826 | return 1; | |
2827 | } | |
2828 | ||
851ba692 | 2829 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2830 | { |
3d6368ef AG |
2831 | if (nested_svm_check_permissions(svm)) |
2832 | return 1; | |
2833 | ||
b75f4eb3 RJ |
2834 | /* Save rip after vmrun instruction */ |
2835 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2836 | |
9738b2c9 | 2837 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2838 | return 1; |
2839 | ||
9738b2c9 | 2840 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2841 | goto failed; |
2842 | ||
2843 | return 1; | |
2844 | ||
2845 | failed: | |
2846 | ||
2847 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2848 | svm->vmcb->control.exit_code_hi = 0; | |
2849 | svm->vmcb->control.exit_info_1 = 0; | |
2850 | svm->vmcb->control.exit_info_2 = 0; | |
2851 | ||
2852 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2853 | |
2854 | return 1; | |
2855 | } | |
2856 | ||
851ba692 | 2857 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2858 | { |
2859 | if (nested_svm_check_permissions(svm)) | |
2860 | return 1; | |
2861 | ||
2862 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2863 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2864 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2865 | |
2af9194d | 2866 | enable_gif(svm); |
1371d904 AG |
2867 | |
2868 | return 1; | |
2869 | } | |
2870 | ||
851ba692 | 2871 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2872 | { |
2873 | if (nested_svm_check_permissions(svm)) | |
2874 | return 1; | |
2875 | ||
2876 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2877 | skip_emulated_instruction(&svm->vcpu); | |
2878 | ||
2af9194d | 2879 | disable_gif(svm); |
1371d904 AG |
2880 | |
2881 | /* After a CLGI no interrupts should come */ | |
340d3bc3 SS |
2882 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) { |
2883 | svm_clear_vintr(svm); | |
2884 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2885 | mark_dirty(svm->vmcb, VMCB_INTR); | |
2886 | } | |
decdbf6a | 2887 | |
1371d904 AG |
2888 | return 1; |
2889 | } | |
2890 | ||
851ba692 | 2891 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2892 | { |
2893 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2894 | |
668f198f DK |
2895 | trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX), |
2896 | kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); | |
ec1ff790 | 2897 | |
ff092385 | 2898 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
668f198f | 2899 | kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
ff092385 AG |
2900 | |
2901 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2902 | skip_emulated_instruction(&svm->vcpu); | |
2903 | return 1; | |
2904 | } | |
2905 | ||
532a46b9 JR |
2906 | static int skinit_interception(struct vcpu_svm *svm) |
2907 | { | |
668f198f | 2908 | trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
532a46b9 JR |
2909 | |
2910 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2911 | return 1; | |
2912 | } | |
2913 | ||
dab429a7 DK |
2914 | static int wbinvd_interception(struct vcpu_svm *svm) |
2915 | { | |
2916 | kvm_emulate_wbinvd(&svm->vcpu); | |
2917 | return 1; | |
2918 | } | |
2919 | ||
81dd35d4 JR |
2920 | static int xsetbv_interception(struct vcpu_svm *svm) |
2921 | { | |
2922 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
2923 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
2924 | ||
2925 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
2926 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2927 | skip_emulated_instruction(&svm->vcpu); | |
2928 | } | |
2929 | ||
2930 | return 1; | |
2931 | } | |
2932 | ||
851ba692 | 2933 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2934 | { |
37817f29 | 2935 | u16 tss_selector; |
64a7ec06 GN |
2936 | int reason; |
2937 | int int_type = svm->vmcb->control.exit_int_info & | |
2938 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2939 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2940 | uint32_t type = |
2941 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2942 | uint32_t idt_v = | |
2943 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2944 | bool has_error_code = false; |
2945 | u32 error_code = 0; | |
37817f29 IE |
2946 | |
2947 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2948 | |
37817f29 IE |
2949 | if (svm->vmcb->control.exit_info_2 & |
2950 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2951 | reason = TASK_SWITCH_IRET; |
2952 | else if (svm->vmcb->control.exit_info_2 & | |
2953 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2954 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2955 | else if (idt_v) |
64a7ec06 GN |
2956 | reason = TASK_SWITCH_GATE; |
2957 | else | |
2958 | reason = TASK_SWITCH_CALL; | |
2959 | ||
fe8e7f83 GN |
2960 | if (reason == TASK_SWITCH_GATE) { |
2961 | switch (type) { | |
2962 | case SVM_EXITINTINFO_TYPE_NMI: | |
2963 | svm->vcpu.arch.nmi_injected = false; | |
2964 | break; | |
2965 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2966 | if (svm->vmcb->control.exit_info_2 & |
2967 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2968 | has_error_code = true; | |
2969 | error_code = | |
2970 | (u32)svm->vmcb->control.exit_info_2; | |
2971 | } | |
fe8e7f83 GN |
2972 | kvm_clear_exception_queue(&svm->vcpu); |
2973 | break; | |
2974 | case SVM_EXITINTINFO_TYPE_INTR: | |
2975 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2976 | break; | |
2977 | default: | |
2978 | break; | |
2979 | } | |
2980 | } | |
64a7ec06 | 2981 | |
8317c298 GN |
2982 | if (reason != TASK_SWITCH_GATE || |
2983 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2984 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2985 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2986 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2987 | |
7f3d35fd KW |
2988 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
2989 | int_vec = -1; | |
2990 | ||
2991 | if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, | |
acb54517 GN |
2992 | has_error_code, error_code) == EMULATE_FAIL) { |
2993 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2994 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2995 | svm->vcpu.run->internal.ndata = 0; | |
2996 | return 0; | |
2997 | } | |
2998 | return 1; | |
6aa8b732 AK |
2999 | } |
3000 | ||
851ba692 | 3001 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 3002 | { |
5fdbf976 | 3003 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 3004 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 3005 | return 1; |
6aa8b732 AK |
3006 | } |
3007 | ||
851ba692 | 3008 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
3009 | { |
3010 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 3011 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 3012 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 3013 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
f303b4ce | 3014 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
95ba8273 GN |
3015 | return 1; |
3016 | } | |
3017 | ||
851ba692 | 3018 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 3019 | { |
df4f3108 AP |
3020 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3021 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
3022 | ||
3023 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
3024 | skip_emulated_instruction(&svm->vcpu); | |
3025 | return 1; | |
a7052897 MT |
3026 | } |
3027 | ||
851ba692 | 3028 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 3029 | { |
51d8b661 | 3030 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
3031 | } |
3032 | ||
332b56e4 AK |
3033 | static int rdpmc_interception(struct vcpu_svm *svm) |
3034 | { | |
3035 | int err; | |
3036 | ||
3037 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
3038 | return emulate_on_interception(svm); | |
3039 | ||
3040 | err = kvm_rdpmc(&svm->vcpu); | |
3041 | kvm_complete_insn_gp(&svm->vcpu, err); | |
3042 | ||
3043 | return 1; | |
3044 | } | |
3045 | ||
52eb5a6d XL |
3046 | static bool check_selective_cr0_intercepted(struct vcpu_svm *svm, |
3047 | unsigned long val) | |
628afd2a JR |
3048 | { |
3049 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
3050 | bool ret = false; | |
3051 | u64 intercept; | |
3052 | ||
3053 | intercept = svm->nested.intercept; | |
3054 | ||
3055 | if (!is_guest_mode(&svm->vcpu) || | |
3056 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
3057 | return false; | |
3058 | ||
3059 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
3060 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
3061 | ||
3062 | if (cr0 ^ val) { | |
3063 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
3064 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
3065 | } | |
3066 | ||
3067 | return ret; | |
3068 | } | |
3069 | ||
7ff76d58 AP |
3070 | #define CR_VALID (1ULL << 63) |
3071 | ||
3072 | static int cr_interception(struct vcpu_svm *svm) | |
3073 | { | |
3074 | int reg, cr; | |
3075 | unsigned long val; | |
3076 | int err; | |
3077 | ||
3078 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
3079 | return emulate_on_interception(svm); | |
3080 | ||
3081 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
3082 | return emulate_on_interception(svm); | |
3083 | ||
3084 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
5e57518d DK |
3085 | if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE) |
3086 | cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0; | |
3087 | else | |
3088 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
7ff76d58 AP |
3089 | |
3090 | err = 0; | |
3091 | if (cr >= 16) { /* mov to cr */ | |
3092 | cr -= 16; | |
3093 | val = kvm_register_read(&svm->vcpu, reg); | |
3094 | switch (cr) { | |
3095 | case 0: | |
628afd2a JR |
3096 | if (!check_selective_cr0_intercepted(svm, val)) |
3097 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
3098 | else |
3099 | return 1; | |
3100 | ||
7ff76d58 AP |
3101 | break; |
3102 | case 3: | |
3103 | err = kvm_set_cr3(&svm->vcpu, val); | |
3104 | break; | |
3105 | case 4: | |
3106 | err = kvm_set_cr4(&svm->vcpu, val); | |
3107 | break; | |
3108 | case 8: | |
3109 | err = kvm_set_cr8(&svm->vcpu, val); | |
3110 | break; | |
3111 | default: | |
3112 | WARN(1, "unhandled write to CR%d", cr); | |
3113 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3114 | return 1; | |
3115 | } | |
3116 | } else { /* mov from cr */ | |
3117 | switch (cr) { | |
3118 | case 0: | |
3119 | val = kvm_read_cr0(&svm->vcpu); | |
3120 | break; | |
3121 | case 2: | |
3122 | val = svm->vcpu.arch.cr2; | |
3123 | break; | |
3124 | case 3: | |
9f8fe504 | 3125 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
3126 | break; |
3127 | case 4: | |
3128 | val = kvm_read_cr4(&svm->vcpu); | |
3129 | break; | |
3130 | case 8: | |
3131 | val = kvm_get_cr8(&svm->vcpu); | |
3132 | break; | |
3133 | default: | |
3134 | WARN(1, "unhandled read from CR%d", cr); | |
3135 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3136 | return 1; | |
3137 | } | |
3138 | kvm_register_write(&svm->vcpu, reg, val); | |
3139 | } | |
3140 | kvm_complete_insn_gp(&svm->vcpu, err); | |
3141 | ||
3142 | return 1; | |
3143 | } | |
3144 | ||
cae3797a AP |
3145 | static int dr_interception(struct vcpu_svm *svm) |
3146 | { | |
3147 | int reg, dr; | |
3148 | unsigned long val; | |
cae3797a | 3149 | |
facb0139 PB |
3150 | if (svm->vcpu.guest_debug == 0) { |
3151 | /* | |
3152 | * No more DR vmexits; force a reload of the debug registers | |
3153 | * and reenter on this instruction. The next vmexit will | |
3154 | * retrieve the full state of the debug registers. | |
3155 | */ | |
3156 | clr_dr_intercepts(svm); | |
3157 | svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
3158 | return 1; | |
3159 | } | |
3160 | ||
cae3797a AP |
3161 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3162 | return emulate_on_interception(svm); | |
3163 | ||
3164 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
3165 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
3166 | ||
3167 | if (dr >= 16) { /* mov to DRn */ | |
16f8a6f9 NA |
3168 | if (!kvm_require_dr(&svm->vcpu, dr - 16)) |
3169 | return 1; | |
cae3797a AP |
3170 | val = kvm_register_read(&svm->vcpu, reg); |
3171 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
3172 | } else { | |
16f8a6f9 NA |
3173 | if (!kvm_require_dr(&svm->vcpu, dr)) |
3174 | return 1; | |
3175 | kvm_get_dr(&svm->vcpu, dr, &val); | |
3176 | kvm_register_write(&svm->vcpu, reg, val); | |
cae3797a AP |
3177 | } |
3178 | ||
2c46d2ae JR |
3179 | skip_emulated_instruction(&svm->vcpu); |
3180 | ||
cae3797a AP |
3181 | return 1; |
3182 | } | |
3183 | ||
851ba692 | 3184 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 3185 | { |
851ba692 | 3186 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 3187 | int r; |
851ba692 | 3188 | |
0a5fff19 GN |
3189 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
3190 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 3191 | r = cr_interception(svm); |
35754c98 | 3192 | if (lapic_in_kernel(&svm->vcpu)) |
7ff76d58 | 3193 | return r; |
0a5fff19 | 3194 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 3195 | return r; |
1d075434 JR |
3196 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
3197 | return 0; | |
3198 | } | |
3199 | ||
48d89b92 | 3200 | static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
d5c1785d NHE |
3201 | { |
3202 | struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu)); | |
4ba76538 | 3203 | return vmcb->control.tsc_offset + host_tsc; |
d5c1785d NHE |
3204 | } |
3205 | ||
609e36d3 | 3206 | static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3207 | { |
a2fa3e9f GH |
3208 | struct vcpu_svm *svm = to_svm(vcpu); |
3209 | ||
609e36d3 | 3210 | switch (msr_info->index) { |
af24a4e4 | 3211 | case MSR_IA32_TSC: { |
609e36d3 | 3212 | msr_info->data = svm->vmcb->control.tsc_offset + |
35181e86 | 3213 | kvm_scale_tsc(vcpu, rdtsc()); |
fbc0db76 | 3214 | |
6aa8b732 AK |
3215 | break; |
3216 | } | |
8c06585d | 3217 | case MSR_STAR: |
609e36d3 | 3218 | msr_info->data = svm->vmcb->save.star; |
6aa8b732 | 3219 | break; |
0e859cac | 3220 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3221 | case MSR_LSTAR: |
609e36d3 | 3222 | msr_info->data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3223 | break; |
3224 | case MSR_CSTAR: | |
609e36d3 | 3225 | msr_info->data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3226 | break; |
3227 | case MSR_KERNEL_GS_BASE: | |
609e36d3 | 3228 | msr_info->data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3229 | break; |
3230 | case MSR_SYSCALL_MASK: | |
609e36d3 | 3231 | msr_info->data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3232 | break; |
3233 | #endif | |
3234 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3235 | msr_info->data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3236 | break; |
3237 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3238 | msr_info->data = svm->sysenter_eip; |
6aa8b732 AK |
3239 | break; |
3240 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3241 | msr_info->data = svm->sysenter_esp; |
6aa8b732 | 3242 | break; |
46896c73 PB |
3243 | case MSR_TSC_AUX: |
3244 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3245 | return 1; | |
3246 | msr_info->data = svm->tsc_aux; | |
3247 | break; | |
e0231715 JR |
3248 | /* |
3249 | * Nobody will change the following 5 values in the VMCB so we can | |
3250 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3251 | * implemented. | |
3252 | */ | |
a2938c80 | 3253 | case MSR_IA32_DEBUGCTLMSR: |
609e36d3 | 3254 | msr_info->data = svm->vmcb->save.dbgctl; |
a2938c80 JR |
3255 | break; |
3256 | case MSR_IA32_LASTBRANCHFROMIP: | |
609e36d3 | 3257 | msr_info->data = svm->vmcb->save.br_from; |
a2938c80 JR |
3258 | break; |
3259 | case MSR_IA32_LASTBRANCHTOIP: | |
609e36d3 | 3260 | msr_info->data = svm->vmcb->save.br_to; |
a2938c80 JR |
3261 | break; |
3262 | case MSR_IA32_LASTINTFROMIP: | |
609e36d3 | 3263 | msr_info->data = svm->vmcb->save.last_excp_from; |
a2938c80 JR |
3264 | break; |
3265 | case MSR_IA32_LASTINTTOIP: | |
609e36d3 | 3266 | msr_info->data = svm->vmcb->save.last_excp_to; |
a2938c80 | 3267 | break; |
b286d5d8 | 3268 | case MSR_VM_HSAVE_PA: |
609e36d3 | 3269 | msr_info->data = svm->nested.hsave_msr; |
b286d5d8 | 3270 | break; |
eb6f302e | 3271 | case MSR_VM_CR: |
609e36d3 | 3272 | msr_info->data = svm->nested.vm_cr_msr; |
eb6f302e | 3273 | break; |
c8a73f18 | 3274 | case MSR_IA32_UCODE_REV: |
609e36d3 | 3275 | msr_info->data = 0x01000065; |
c8a73f18 | 3276 | break; |
ae8b7875 BP |
3277 | case MSR_F15H_IC_CFG: { |
3278 | ||
3279 | int family, model; | |
3280 | ||
3281 | family = guest_cpuid_family(vcpu); | |
3282 | model = guest_cpuid_model(vcpu); | |
3283 | ||
3284 | if (family < 0 || model < 0) | |
3285 | return kvm_get_msr_common(vcpu, msr_info); | |
3286 | ||
3287 | msr_info->data = 0; | |
3288 | ||
3289 | if (family == 0x15 && | |
3290 | (model >= 0x2 && model < 0x20)) | |
3291 | msr_info->data = 0x1E; | |
3292 | } | |
3293 | break; | |
6aa8b732 | 3294 | default: |
609e36d3 | 3295 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3296 | } |
3297 | return 0; | |
3298 | } | |
3299 | ||
851ba692 | 3300 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3301 | { |
668f198f | 3302 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
609e36d3 | 3303 | struct msr_data msr_info; |
6aa8b732 | 3304 | |
609e36d3 PB |
3305 | msr_info.index = ecx; |
3306 | msr_info.host_initiated = false; | |
3307 | if (svm_get_msr(&svm->vcpu, &msr_info)) { | |
59200273 | 3308 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 3309 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 3310 | } else { |
609e36d3 | 3311 | trace_kvm_msr_read(ecx, msr_info.data); |
af9ca2d7 | 3312 | |
609e36d3 PB |
3313 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, |
3314 | msr_info.data & 0xffffffff); | |
3315 | kvm_register_write(&svm->vcpu, VCPU_REGS_RDX, | |
3316 | msr_info.data >> 32); | |
5fdbf976 | 3317 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 3318 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
3319 | } |
3320 | return 1; | |
3321 | } | |
3322 | ||
4a810181 JR |
3323 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3324 | { | |
3325 | struct vcpu_svm *svm = to_svm(vcpu); | |
3326 | int svm_dis, chg_mask; | |
3327 | ||
3328 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3329 | return 1; | |
3330 | ||
3331 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3332 | ||
3333 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3334 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3335 | ||
3336 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3337 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3338 | ||
3339 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3340 | ||
3341 | /* check for svm_disable while efer.svme is set */ | |
3342 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3343 | return 1; | |
3344 | ||
3345 | return 0; | |
3346 | } | |
3347 | ||
8fe8ab46 | 3348 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 3349 | { |
a2fa3e9f GH |
3350 | struct vcpu_svm *svm = to_svm(vcpu); |
3351 | ||
8fe8ab46 WA |
3352 | u32 ecx = msr->index; |
3353 | u64 data = msr->data; | |
6aa8b732 | 3354 | switch (ecx) { |
f4e1b3c8 | 3355 | case MSR_IA32_TSC: |
8fe8ab46 | 3356 | kvm_write_tsc(vcpu, msr); |
6aa8b732 | 3357 | break; |
8c06585d | 3358 | case MSR_STAR: |
a2fa3e9f | 3359 | svm->vmcb->save.star = data; |
6aa8b732 | 3360 | break; |
49b14f24 | 3361 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3362 | case MSR_LSTAR: |
a2fa3e9f | 3363 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3364 | break; |
3365 | case MSR_CSTAR: | |
a2fa3e9f | 3366 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3367 | break; |
3368 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3369 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3370 | break; |
3371 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3372 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3373 | break; |
3374 | #endif | |
3375 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3376 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3377 | break; |
3378 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3379 | svm->sysenter_eip = data; |
a2fa3e9f | 3380 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
3381 | break; |
3382 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3383 | svm->sysenter_esp = data; |
a2fa3e9f | 3384 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 3385 | break; |
46896c73 PB |
3386 | case MSR_TSC_AUX: |
3387 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3388 | return 1; | |
3389 | ||
3390 | /* | |
3391 | * This is rare, so we update the MSR here instead of using | |
3392 | * direct_access_msrs. Doing that would require a rdmsr in | |
3393 | * svm_vcpu_put. | |
3394 | */ | |
3395 | svm->tsc_aux = data; | |
3396 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
3397 | break; | |
a2938c80 | 3398 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 3399 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
3400 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
3401 | __func__, data); | |
24e09cbf JR |
3402 | break; |
3403 | } | |
3404 | if (data & DEBUGCTL_RESERVED_BITS) | |
3405 | return 1; | |
3406 | ||
3407 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 3408 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
3409 | if (data & (1ULL<<0)) |
3410 | svm_enable_lbrv(svm); | |
3411 | else | |
3412 | svm_disable_lbrv(svm); | |
a2938c80 | 3413 | break; |
b286d5d8 | 3414 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3415 | svm->nested.hsave_msr = data; |
62b9abaa | 3416 | break; |
3c5d0a44 | 3417 | case MSR_VM_CR: |
4a810181 | 3418 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3419 | case MSR_VM_IGNNE: |
a737f256 | 3420 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 3421 | break; |
44a95dae SS |
3422 | case MSR_IA32_APICBASE: |
3423 | if (kvm_vcpu_apicv_active(vcpu)) | |
3424 | avic_update_vapic_bar(to_svm(vcpu), data); | |
3425 | /* Follow through */ | |
6aa8b732 | 3426 | default: |
8fe8ab46 | 3427 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
3428 | } |
3429 | return 0; | |
3430 | } | |
3431 | ||
851ba692 | 3432 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3433 | { |
8fe8ab46 | 3434 | struct msr_data msr; |
668f198f DK |
3435 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
3436 | u64 data = kvm_read_edx_eax(&svm->vcpu); | |
af9ca2d7 | 3437 | |
8fe8ab46 WA |
3438 | msr.data = data; |
3439 | msr.index = ecx; | |
3440 | msr.host_initiated = false; | |
af9ca2d7 | 3441 | |
5fdbf976 | 3442 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
854e8bb1 | 3443 | if (kvm_set_msr(&svm->vcpu, &msr)) { |
59200273 | 3444 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3445 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
3446 | } else { |
3447 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 3448 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 3449 | } |
6aa8b732 AK |
3450 | return 1; |
3451 | } | |
3452 | ||
851ba692 | 3453 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3454 | { |
e756fc62 | 3455 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3456 | return wrmsr_interception(svm); |
6aa8b732 | 3457 | else |
851ba692 | 3458 | return rdmsr_interception(svm); |
6aa8b732 AK |
3459 | } |
3460 | ||
851ba692 | 3461 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3462 | { |
3842d135 | 3463 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3464 | svm_clear_vintr(svm); |
85f455f7 | 3465 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3466 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 3467 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3468 | return 1; |
3469 | } | |
3470 | ||
565d0998 ML |
3471 | static int pause_interception(struct vcpu_svm *svm) |
3472 | { | |
3473 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3474 | return 1; | |
3475 | } | |
3476 | ||
87c00572 GS |
3477 | static int nop_interception(struct vcpu_svm *svm) |
3478 | { | |
3479 | skip_emulated_instruction(&(svm->vcpu)); | |
3480 | return 1; | |
3481 | } | |
3482 | ||
3483 | static int monitor_interception(struct vcpu_svm *svm) | |
3484 | { | |
3485 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
3486 | return nop_interception(svm); | |
3487 | } | |
3488 | ||
3489 | static int mwait_interception(struct vcpu_svm *svm) | |
3490 | { | |
3491 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
3492 | return nop_interception(svm); | |
3493 | } | |
3494 | ||
09941fbb | 3495 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
3496 | [SVM_EXIT_READ_CR0] = cr_interception, |
3497 | [SVM_EXIT_READ_CR3] = cr_interception, | |
3498 | [SVM_EXIT_READ_CR4] = cr_interception, | |
3499 | [SVM_EXIT_READ_CR8] = cr_interception, | |
5e57518d | 3500 | [SVM_EXIT_CR0_SEL_WRITE] = cr_interception, |
628afd2a | 3501 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
3502 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
3503 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 3504 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
3505 | [SVM_EXIT_READ_DR0] = dr_interception, |
3506 | [SVM_EXIT_READ_DR1] = dr_interception, | |
3507 | [SVM_EXIT_READ_DR2] = dr_interception, | |
3508 | [SVM_EXIT_READ_DR3] = dr_interception, | |
3509 | [SVM_EXIT_READ_DR4] = dr_interception, | |
3510 | [SVM_EXIT_READ_DR5] = dr_interception, | |
3511 | [SVM_EXIT_READ_DR6] = dr_interception, | |
3512 | [SVM_EXIT_READ_DR7] = dr_interception, | |
3513 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
3514 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
3515 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
3516 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
3517 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
3518 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
3519 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
3520 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
3521 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
3522 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 3523 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
3524 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
3525 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
3526 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
54a20552 | 3527 | [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception, |
e0231715 | 3528 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 3529 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
3530 | [SVM_EXIT_SMI] = nop_on_interception, |
3531 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 3532 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 3533 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 3534 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 3535 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 3536 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 3537 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 3538 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 3539 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 3540 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 3541 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
3542 | [SVM_EXIT_MSR] = msr_interception, |
3543 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 3544 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 3545 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 3546 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
3547 | [SVM_EXIT_VMLOAD] = vmload_interception, |
3548 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
3549 | [SVM_EXIT_STGI] = stgi_interception, |
3550 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 3551 | [SVM_EXIT_SKINIT] = skinit_interception, |
dab429a7 | 3552 | [SVM_EXIT_WBINVD] = wbinvd_interception, |
87c00572 GS |
3553 | [SVM_EXIT_MONITOR] = monitor_interception, |
3554 | [SVM_EXIT_MWAIT] = mwait_interception, | |
81dd35d4 | 3555 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 3556 | [SVM_EXIT_NPF] = pf_interception, |
64d60670 | 3557 | [SVM_EXIT_RSM] = emulate_on_interception, |
6aa8b732 AK |
3558 | }; |
3559 | ||
ae8cc059 | 3560 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
3561 | { |
3562 | struct vcpu_svm *svm = to_svm(vcpu); | |
3563 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3564 | struct vmcb_save_area *save = &svm->vmcb->save; | |
3565 | ||
3566 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
3567 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
3568 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
3569 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
3570 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
3571 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
3572 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
3573 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
3574 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
3575 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
3576 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
3577 | pr_err("%-20s%d\n", "asid:", control->asid); | |
3578 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
3579 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
3580 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
3581 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
3582 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
3583 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
3584 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
3585 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
3586 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
3587 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
3588 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
44a95dae | 3589 | pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar); |
ae8cc059 JP |
3590 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); |
3591 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
3592 | pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl); | |
3593 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); | |
44a95dae SS |
3594 | pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page); |
3595 | pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id); | |
3596 | pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id); | |
3f10c846 | 3597 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
3598 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
3599 | "es:", | |
3600 | save->es.selector, save->es.attrib, | |
3601 | save->es.limit, save->es.base); | |
3602 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3603 | "cs:", | |
3604 | save->cs.selector, save->cs.attrib, | |
3605 | save->cs.limit, save->cs.base); | |
3606 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3607 | "ss:", | |
3608 | save->ss.selector, save->ss.attrib, | |
3609 | save->ss.limit, save->ss.base); | |
3610 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3611 | "ds:", | |
3612 | save->ds.selector, save->ds.attrib, | |
3613 | save->ds.limit, save->ds.base); | |
3614 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3615 | "fs:", | |
3616 | save->fs.selector, save->fs.attrib, | |
3617 | save->fs.limit, save->fs.base); | |
3618 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3619 | "gs:", | |
3620 | save->gs.selector, save->gs.attrib, | |
3621 | save->gs.limit, save->gs.base); | |
3622 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3623 | "gdtr:", | |
3624 | save->gdtr.selector, save->gdtr.attrib, | |
3625 | save->gdtr.limit, save->gdtr.base); | |
3626 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3627 | "ldtr:", | |
3628 | save->ldtr.selector, save->ldtr.attrib, | |
3629 | save->ldtr.limit, save->ldtr.base); | |
3630 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3631 | "idtr:", | |
3632 | save->idtr.selector, save->idtr.attrib, | |
3633 | save->idtr.limit, save->idtr.base); | |
3634 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3635 | "tr:", | |
3636 | save->tr.selector, save->tr.attrib, | |
3637 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
3638 | pr_err("cpl: %d efer: %016llx\n", |
3639 | save->cpl, save->efer); | |
ae8cc059 JP |
3640 | pr_err("%-15s %016llx %-13s %016llx\n", |
3641 | "cr0:", save->cr0, "cr2:", save->cr2); | |
3642 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3643 | "cr3:", save->cr3, "cr4:", save->cr4); | |
3644 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3645 | "dr6:", save->dr6, "dr7:", save->dr7); | |
3646 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3647 | "rip:", save->rip, "rflags:", save->rflags); | |
3648 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3649 | "rsp:", save->rsp, "rax:", save->rax); | |
3650 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3651 | "star:", save->star, "lstar:", save->lstar); | |
3652 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3653 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
3654 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3655 | "kernel_gs_base:", save->kernel_gs_base, | |
3656 | "sysenter_cs:", save->sysenter_cs); | |
3657 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3658 | "sysenter_esp:", save->sysenter_esp, | |
3659 | "sysenter_eip:", save->sysenter_eip); | |
3660 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3661 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
3662 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3663 | "br_from:", save->br_from, "br_to:", save->br_to); | |
3664 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3665 | "excp_from:", save->last_excp_from, | |
3666 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
3667 | } |
3668 | ||
586f9607 AK |
3669 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3670 | { | |
3671 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3672 | ||
3673 | *info1 = control->exit_info_1; | |
3674 | *info2 = control->exit_info_2; | |
3675 | } | |
3676 | ||
851ba692 | 3677 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3678 | { |
04d2cc77 | 3679 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3680 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3681 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3682 | |
8b89fe1f PB |
3683 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
3684 | ||
4ee546b4 | 3685 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3686 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3687 | if (npt_enabled) | |
3688 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3689 | |
cd3ff653 JR |
3690 | if (unlikely(svm->nested.exit_required)) { |
3691 | nested_svm_vmexit(svm); | |
3692 | svm->nested.exit_required = false; | |
3693 | ||
3694 | return 1; | |
3695 | } | |
3696 | ||
2030753d | 3697 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3698 | int vmexit; |
3699 | ||
d8cabddf JR |
3700 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3701 | svm->vmcb->control.exit_info_1, | |
3702 | svm->vmcb->control.exit_info_2, | |
3703 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
3704 | svm->vmcb->control.exit_int_info_err, |
3705 | KVM_ISA_SVM); | |
d8cabddf | 3706 | |
410e4d57 JR |
3707 | vmexit = nested_svm_exit_special(svm); |
3708 | ||
3709 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3710 | vmexit = nested_svm_exit_handled(svm); | |
3711 | ||
3712 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3713 | return 1; |
cf74a78b AG |
3714 | } |
3715 | ||
a5c3832d JR |
3716 | svm_complete_interrupts(svm); |
3717 | ||
04d2cc77 AK |
3718 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3719 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3720 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3721 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3722 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3723 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3724 | return 0; |
3725 | } | |
3726 | ||
a2fa3e9f | 3727 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3728 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3729 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3730 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 3731 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 3732 | "exit_code 0x%x\n", |
b8688d51 | 3733 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3734 | exit_code); |
3735 | ||
9d8f549d | 3736 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3737 | || !svm_exit_handlers[exit_code]) { |
faac2458 | 3738 | WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code); |
2bc19dc3 MT |
3739 | kvm_queue_exception(vcpu, UD_VECTOR); |
3740 | return 1; | |
6aa8b732 AK |
3741 | } |
3742 | ||
851ba692 | 3743 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3744 | } |
3745 | ||
3746 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3747 | { | |
3748 | int cpu = raw_smp_processor_id(); | |
3749 | ||
0fe1e009 TH |
3750 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3751 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3752 | load_TR_desc(); |
3753 | } | |
3754 | ||
e756fc62 | 3755 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3756 | { |
3757 | int cpu = raw_smp_processor_id(); | |
3758 | ||
0fe1e009 | 3759 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3760 | |
4b656b12 | 3761 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3762 | if (svm->asid_generation != sd->asid_generation) |
3763 | new_asid(svm, sd); | |
6aa8b732 AK |
3764 | } |
3765 | ||
95ba8273 GN |
3766 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3767 | { | |
3768 | struct vcpu_svm *svm = to_svm(vcpu); | |
3769 | ||
3770 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3771 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3772 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
3773 | ++vcpu->stat.nmi_injections; |
3774 | } | |
6aa8b732 | 3775 | |
85f455f7 | 3776 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3777 | { |
3778 | struct vmcb_control_area *control; | |
3779 | ||
340d3bc3 | 3780 | /* The following fields are ignored when AVIC is enabled */ |
e756fc62 | 3781 | control = &svm->vmcb->control; |
85f455f7 | 3782 | control->int_vector = irq; |
6aa8b732 AK |
3783 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3784 | control->int_ctl |= V_IRQ_MASK | | |
3785 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 3786 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
3787 | } |
3788 | ||
66fd3f7f | 3789 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3790 | { |
3791 | struct vcpu_svm *svm = to_svm(vcpu); | |
3792 | ||
2af9194d | 3793 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3794 | |
9fb2d2b4 GN |
3795 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3796 | ++vcpu->stat.irq_injections; | |
3797 | ||
219b65dc AG |
3798 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3799 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3800 | } |
3801 | ||
95ba8273 | 3802 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3803 | { |
3804 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3805 | |
2030753d | 3806 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3807 | return; |
3808 | ||
596f3142 RK |
3809 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
3810 | ||
95ba8273 | 3811 | if (irr == -1) |
aaacfc9a JR |
3812 | return; |
3813 | ||
95ba8273 | 3814 | if (tpr >= irr) |
4ee546b4 | 3815 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3816 | } |
aaacfc9a | 3817 | |
8d14695f YZ |
3818 | static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
3819 | { | |
3820 | return; | |
3821 | } | |
3822 | ||
d62caabb AS |
3823 | static bool svm_get_enable_apicv(void) |
3824 | { | |
44a95dae SS |
3825 | return avic; |
3826 | } | |
3827 | ||
3828 | static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
3829 | { | |
3830 | } | |
3831 | ||
3832 | static void svm_hwapic_isr_update(struct kvm *kvm, int isr) | |
3833 | { | |
d62caabb AS |
3834 | } |
3835 | ||
44a95dae | 3836 | /* Note: Currently only used by Hyper-V. */ |
d62caabb | 3837 | static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
c7c9c56c | 3838 | { |
44a95dae SS |
3839 | struct vcpu_svm *svm = to_svm(vcpu); |
3840 | struct vmcb *vmcb = svm->vmcb; | |
3841 | ||
3842 | if (!avic) | |
3843 | return; | |
3844 | ||
3845 | vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK; | |
3846 | mark_dirty(vmcb, VMCB_INTR); | |
c7c9c56c YZ |
3847 | } |
3848 | ||
6308630b | 3849 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c YZ |
3850 | { |
3851 | return; | |
3852 | } | |
3853 | ||
a20ed54d YZ |
3854 | static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
3855 | { | |
3856 | return; | |
3857 | } | |
3858 | ||
340d3bc3 SS |
3859 | static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec) |
3860 | { | |
3861 | kvm_lapic_set_irr(vec, vcpu->arch.apic); | |
3862 | smp_mb__after_atomic(); | |
3863 | ||
3864 | if (avic_vcpu_is_running(vcpu)) | |
3865 | wrmsrl(SVM_AVIC_DOORBELL, | |
3866 | __default_cpu_present_to_apicid(vcpu->cpu)); | |
3867 | else | |
3868 | kvm_vcpu_wake_up(vcpu); | |
3869 | } | |
3870 | ||
95ba8273 GN |
3871 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3872 | { | |
3873 | struct vcpu_svm *svm = to_svm(vcpu); | |
3874 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3875 | int ret; |
3876 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3877 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3878 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3879 | ||
3880 | return ret; | |
aaacfc9a JR |
3881 | } |
3882 | ||
3cfc3092 JK |
3883 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3884 | { | |
3885 | struct vcpu_svm *svm = to_svm(vcpu); | |
3886 | ||
3887 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3888 | } | |
3889 | ||
3890 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3891 | { | |
3892 | struct vcpu_svm *svm = to_svm(vcpu); | |
3893 | ||
3894 | if (masked) { | |
3895 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3896 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3897 | } else { |
3898 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 3899 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3900 | } |
3901 | } | |
3902 | ||
78646121 GN |
3903 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3904 | { | |
3905 | struct vcpu_svm *svm = to_svm(vcpu); | |
3906 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3907 | int ret; |
3908 | ||
3909 | if (!gif_set(svm) || | |
3910 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3911 | return 0; | |
3912 | ||
f6e78475 | 3913 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 3914 | |
2030753d | 3915 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3916 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3917 | ||
3918 | return ret; | |
78646121 GN |
3919 | } |
3920 | ||
c9a7953f | 3921 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3922 | { |
219b65dc | 3923 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3924 | |
340d3bc3 SS |
3925 | if (kvm_vcpu_apicv_active(vcpu)) |
3926 | return; | |
3927 | ||
e0231715 JR |
3928 | /* |
3929 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3930 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3931 | * get that intercept, this function will be called again though and | |
3932 | * we'll get the vintr intercept. | |
3933 | */ | |
8fe54654 | 3934 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3935 | svm_set_vintr(svm); |
3936 | svm_inject_irq(svm, 0x0); | |
3937 | } | |
85f455f7 ED |
3938 | } |
3939 | ||
c9a7953f | 3940 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3941 | { |
04d2cc77 | 3942 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3943 | |
44c11430 GN |
3944 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3945 | == HF_NMI_MASK) | |
c9a7953f | 3946 | return; /* IRET will cause a vm exit */ |
44c11430 | 3947 | |
e0231715 JR |
3948 | /* |
3949 | * Something prevents NMI from been injected. Single step over possible | |
3950 | * problem (IRET or exception injection or interrupt shadow) | |
3951 | */ | |
6be7d306 | 3952 | svm->nmi_singlestep = true; |
44c11430 | 3953 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c1150d8c DL |
3954 | } |
3955 | ||
cbc94022 IE |
3956 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3957 | { | |
3958 | return 0; | |
3959 | } | |
3960 | ||
d9e368d6 AK |
3961 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3962 | { | |
38e5e92f JR |
3963 | struct vcpu_svm *svm = to_svm(vcpu); |
3964 | ||
3965 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
3966 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
3967 | else | |
3968 | svm->asid_generation--; | |
d9e368d6 AK |
3969 | } |
3970 | ||
04d2cc77 AK |
3971 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3972 | { | |
3973 | } | |
3974 | ||
d7bf8221 JR |
3975 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3976 | { | |
3977 | struct vcpu_svm *svm = to_svm(vcpu); | |
3978 | ||
2030753d | 3979 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3980 | return; |
3981 | ||
4ee546b4 | 3982 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3983 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3984 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3985 | } |
3986 | } | |
3987 | ||
649d6864 JR |
3988 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3989 | { | |
3990 | struct vcpu_svm *svm = to_svm(vcpu); | |
3991 | u64 cr8; | |
3992 | ||
2030753d | 3993 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3994 | return; |
3995 | ||
649d6864 JR |
3996 | cr8 = kvm_get_cr8(vcpu); |
3997 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3998 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3999 | } | |
4000 | ||
9222be18 GN |
4001 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
4002 | { | |
4003 | u8 vector; | |
4004 | int type; | |
4005 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
4006 | unsigned int3_injected = svm->int3_injected; |
4007 | ||
4008 | svm->int3_injected = 0; | |
9222be18 | 4009 | |
bd3d1ec3 AK |
4010 | /* |
4011 | * If we've made progress since setting HF_IRET_MASK, we've | |
4012 | * executed an IRET and can allow NMI injection. | |
4013 | */ | |
4014 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
4015 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 4016 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
4017 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
4018 | } | |
44c11430 | 4019 | |
9222be18 GN |
4020 | svm->vcpu.arch.nmi_injected = false; |
4021 | kvm_clear_exception_queue(&svm->vcpu); | |
4022 | kvm_clear_interrupt_queue(&svm->vcpu); | |
4023 | ||
4024 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
4025 | return; | |
4026 | ||
3842d135 AK |
4027 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
4028 | ||
9222be18 GN |
4029 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
4030 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
4031 | ||
4032 | switch (type) { | |
4033 | case SVM_EXITINTINFO_TYPE_NMI: | |
4034 | svm->vcpu.arch.nmi_injected = true; | |
4035 | break; | |
4036 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
4037 | /* |
4038 | * In case of software exceptions, do not reinject the vector, | |
4039 | * but re-execute the instruction instead. Rewind RIP first | |
4040 | * if we emulated INT3 before. | |
4041 | */ | |
4042 | if (kvm_exception_is_soft(vector)) { | |
4043 | if (vector == BP_VECTOR && int3_injected && | |
4044 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
4045 | kvm_rip_write(&svm->vcpu, | |
4046 | kvm_rip_read(&svm->vcpu) - | |
4047 | int3_injected); | |
9222be18 | 4048 | break; |
66b7138f | 4049 | } |
9222be18 GN |
4050 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
4051 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 4052 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
4053 | |
4054 | } else | |
ce7ddec4 | 4055 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
4056 | break; |
4057 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 4058 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
4059 | break; |
4060 | default: | |
4061 | break; | |
4062 | } | |
4063 | } | |
4064 | ||
b463a6f7 AK |
4065 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
4066 | { | |
4067 | struct vcpu_svm *svm = to_svm(vcpu); | |
4068 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4069 | ||
4070 | control->exit_int_info = control->event_inj; | |
4071 | control->exit_int_info_err = control->event_inj_err; | |
4072 | control->event_inj = 0; | |
4073 | svm_complete_interrupts(svm); | |
4074 | } | |
4075 | ||
851ba692 | 4076 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 4077 | { |
a2fa3e9f | 4078 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 4079 | |
2041a06a JR |
4080 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
4081 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
4082 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
4083 | ||
cd3ff653 JR |
4084 | /* |
4085 | * A vmexit emulation is required before the vcpu can be executed | |
4086 | * again. | |
4087 | */ | |
4088 | if (unlikely(svm->nested.exit_required)) | |
4089 | return; | |
4090 | ||
e756fc62 | 4091 | pre_svm_run(svm); |
6aa8b732 | 4092 | |
649d6864 JR |
4093 | sync_lapic_to_cr8(vcpu); |
4094 | ||
cda0ffdd | 4095 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 4096 | |
04d2cc77 AK |
4097 | clgi(); |
4098 | ||
4099 | local_irq_enable(); | |
36241b8c | 4100 | |
6aa8b732 | 4101 | asm volatile ( |
7454766f AK |
4102 | "push %%" _ASM_BP "; \n\t" |
4103 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
4104 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
4105 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
4106 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
4107 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
4108 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 4109 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
4110 | "mov %c[r8](%[svm]), %%r8 \n\t" |
4111 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
4112 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
4113 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
4114 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
4115 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
4116 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
4117 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
4118 | #endif |
4119 | ||
6aa8b732 | 4120 | /* Enter guest mode */ |
7454766f AK |
4121 | "push %%" _ASM_AX " \n\t" |
4122 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
4ecac3fd AK |
4123 | __ex(SVM_VMLOAD) "\n\t" |
4124 | __ex(SVM_VMRUN) "\n\t" | |
4125 | __ex(SVM_VMSAVE) "\n\t" | |
7454766f | 4126 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
4127 | |
4128 | /* Save guest registers, load host registers */ | |
7454766f AK |
4129 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
4130 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
4131 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
4132 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
4133 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
4134 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 4135 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
4136 | "mov %%r8, %c[r8](%[svm]) \n\t" |
4137 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
4138 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
4139 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
4140 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
4141 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
4142 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
4143 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 4144 | #endif |
7454766f | 4145 | "pop %%" _ASM_BP |
6aa8b732 | 4146 | : |
fb3f0f51 | 4147 | : [svm]"a"(svm), |
6aa8b732 | 4148 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
4149 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
4150 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
4151 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
4152 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
4153 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
4154 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 4155 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
4156 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
4157 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
4158 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
4159 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
4160 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
4161 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
4162 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
4163 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 4164 | #endif |
54a08c04 LV |
4165 | : "cc", "memory" |
4166 | #ifdef CONFIG_X86_64 | |
7454766f | 4167 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 4168 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
4169 | #else |
4170 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
4171 | #endif |
4172 | ); | |
6aa8b732 | 4173 | |
82ca2d10 AK |
4174 | #ifdef CONFIG_X86_64 |
4175 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
4176 | #else | |
dacccfdd | 4177 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
4178 | #ifndef CONFIG_X86_32_LAZY_GS |
4179 | loadsegment(gs, svm->host.gs); | |
4180 | #endif | |
9581d442 | 4181 | #endif |
6aa8b732 AK |
4182 | |
4183 | reload_tss(vcpu); | |
4184 | ||
56ba47dd AK |
4185 | local_irq_disable(); |
4186 | ||
13c34e07 AK |
4187 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
4188 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
4189 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
4190 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
4191 | ||
3781c01c JR |
4192 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
4193 | kvm_before_handle_nmi(&svm->vcpu); | |
4194 | ||
4195 | stgi(); | |
4196 | ||
4197 | /* Any pending NMI will happen here */ | |
4198 | ||
4199 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
4200 | kvm_after_handle_nmi(&svm->vcpu); | |
4201 | ||
d7bf8221 JR |
4202 | sync_cr8_to_lapic(vcpu); |
4203 | ||
a2fa3e9f | 4204 | svm->next_rip = 0; |
9222be18 | 4205 | |
38e5e92f JR |
4206 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
4207 | ||
631bc487 GN |
4208 | /* if exit due to PF check for async PF */ |
4209 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
4210 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
4211 | ||
6de4f3ad AK |
4212 | if (npt_enabled) { |
4213 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
4214 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
4215 | } | |
fe5913e4 JR |
4216 | |
4217 | /* | |
4218 | * We need to handle MC intercepts here before the vcpu has a chance to | |
4219 | * change the physical cpu | |
4220 | */ | |
4221 | if (unlikely(svm->vmcb->control.exit_code == | |
4222 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
4223 | svm_handle_mce(svm); | |
8d28fec4 RJ |
4224 | |
4225 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
4226 | } |
4227 | ||
6aa8b732 AK |
4228 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
4229 | { | |
a2fa3e9f GH |
4230 | struct vcpu_svm *svm = to_svm(vcpu); |
4231 | ||
4232 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 4233 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 4234 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
4235 | } |
4236 | ||
1c97f0a0 JR |
4237 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
4238 | { | |
4239 | struct vcpu_svm *svm = to_svm(vcpu); | |
4240 | ||
4241 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 4242 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
4243 | |
4244 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 4245 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 4246 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 4247 | |
f40f6a45 | 4248 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
4249 | } |
4250 | ||
6aa8b732 AK |
4251 | static int is_disabled(void) |
4252 | { | |
6031a61c JR |
4253 | u64 vm_cr; |
4254 | ||
4255 | rdmsrl(MSR_VM_CR, vm_cr); | |
4256 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
4257 | return 1; | |
4258 | ||
6aa8b732 AK |
4259 | return 0; |
4260 | } | |
4261 | ||
102d8325 IM |
4262 | static void |
4263 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
4264 | { | |
4265 | /* | |
4266 | * Patch in the VMMCALL instruction: | |
4267 | */ | |
4268 | hypercall[0] = 0x0f; | |
4269 | hypercall[1] = 0x01; | |
4270 | hypercall[2] = 0xd9; | |
102d8325 IM |
4271 | } |
4272 | ||
002c7f7c YS |
4273 | static void svm_check_processor_compat(void *rtn) |
4274 | { | |
4275 | *(int *)rtn = 0; | |
4276 | } | |
4277 | ||
774ead3a AK |
4278 | static bool svm_cpu_has_accelerated_tpr(void) |
4279 | { | |
4280 | return false; | |
4281 | } | |
4282 | ||
6d396b55 PB |
4283 | static bool svm_has_high_real_mode_segbase(void) |
4284 | { | |
4285 | return true; | |
4286 | } | |
4287 | ||
fc07e76a PB |
4288 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
4289 | { | |
4290 | return 0; | |
4291 | } | |
4292 | ||
0e851880 SY |
4293 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
4294 | { | |
6092d3d3 JR |
4295 | struct vcpu_svm *svm = to_svm(vcpu); |
4296 | ||
4297 | /* Update nrips enabled cache */ | |
4298 | svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu); | |
0e851880 SY |
4299 | } |
4300 | ||
d4330ef2 JR |
4301 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
4302 | { | |
c2c63a49 | 4303 | switch (func) { |
4c62a2dc JR |
4304 | case 0x80000001: |
4305 | if (nested) | |
4306 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
4307 | break; | |
c2c63a49 JR |
4308 | case 0x8000000A: |
4309 | entry->eax = 1; /* SVM revision 1 */ | |
4310 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
4311 | ASID emulation to nested SVM */ | |
4312 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
4313 | entry->edx = 0; /* Per default do not support any |
4314 | additional features */ | |
4315 | ||
4316 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 4317 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 4318 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 4319 | |
3d4aeaad JR |
4320 | /* Support NPT for the guest if enabled */ |
4321 | if (npt_enabled) | |
4322 | entry->edx |= SVM_FEATURE_NPT; | |
4323 | ||
c2c63a49 JR |
4324 | break; |
4325 | } | |
d4330ef2 JR |
4326 | } |
4327 | ||
17cc3935 | 4328 | static int svm_get_lpage_level(void) |
344f414f | 4329 | { |
17cc3935 | 4330 | return PT_PDPE_LEVEL; |
344f414f JR |
4331 | } |
4332 | ||
4e47c7a6 SY |
4333 | static bool svm_rdtscp_supported(void) |
4334 | { | |
46896c73 | 4335 | return boot_cpu_has(X86_FEATURE_RDTSCP); |
4e47c7a6 SY |
4336 | } |
4337 | ||
ad756a16 MJ |
4338 | static bool svm_invpcid_supported(void) |
4339 | { | |
4340 | return false; | |
4341 | } | |
4342 | ||
93c4adc7 PB |
4343 | static bool svm_mpx_supported(void) |
4344 | { | |
4345 | return false; | |
4346 | } | |
4347 | ||
55412b2e WL |
4348 | static bool svm_xsaves_supported(void) |
4349 | { | |
4350 | return false; | |
4351 | } | |
4352 | ||
f5f48ee1 SY |
4353 | static bool svm_has_wbinvd_exit(void) |
4354 | { | |
4355 | return true; | |
4356 | } | |
4357 | ||
02daab21 AK |
4358 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
4359 | { | |
4360 | struct vcpu_svm *svm = to_svm(vcpu); | |
4361 | ||
18c918c5 | 4362 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 4363 | update_cr0_intercept(svm); |
02daab21 AK |
4364 | } |
4365 | ||
8061252e | 4366 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4367 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 4368 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4369 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 4370 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 4371 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 4372 | |
09941fbb | 4373 | static const struct __x86_intercept { |
cfec82cb JR |
4374 | u32 exit_code; |
4375 | enum x86_intercept_stage stage; | |
cfec82cb JR |
4376 | } x86_intercept_map[] = { |
4377 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
4378 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4379 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4380 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4381 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
4382 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
4383 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
4384 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
4385 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
4386 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
4387 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
4388 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
4389 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
4390 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
4391 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
4392 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
4393 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
4394 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
4395 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
4396 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
4397 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
4398 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
4399 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
4400 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
4401 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
4402 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
4403 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
4404 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
4405 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
4406 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
4407 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
4408 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
4409 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
4410 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
4411 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
4412 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
4413 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
4414 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
4415 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
4416 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
4417 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
4418 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
4419 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
4420 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
4421 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
4422 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
4423 | }; |
4424 | ||
8061252e | 4425 | #undef PRE_EX |
cfec82cb | 4426 | #undef POST_EX |
d7eb8203 | 4427 | #undef POST_MEM |
cfec82cb | 4428 | |
8a76d7f2 JR |
4429 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
4430 | struct x86_instruction_info *info, | |
4431 | enum x86_intercept_stage stage) | |
4432 | { | |
cfec82cb JR |
4433 | struct vcpu_svm *svm = to_svm(vcpu); |
4434 | int vmexit, ret = X86EMUL_CONTINUE; | |
4435 | struct __x86_intercept icpt_info; | |
4436 | struct vmcb *vmcb = svm->vmcb; | |
4437 | ||
4438 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
4439 | goto out; | |
4440 | ||
4441 | icpt_info = x86_intercept_map[info->intercept]; | |
4442 | ||
40e19b51 | 4443 | if (stage != icpt_info.stage) |
cfec82cb JR |
4444 | goto out; |
4445 | ||
4446 | switch (icpt_info.exit_code) { | |
4447 | case SVM_EXIT_READ_CR0: | |
4448 | if (info->intercept == x86_intercept_cr_read) | |
4449 | icpt_info.exit_code += info->modrm_reg; | |
4450 | break; | |
4451 | case SVM_EXIT_WRITE_CR0: { | |
4452 | unsigned long cr0, val; | |
4453 | u64 intercept; | |
4454 | ||
4455 | if (info->intercept == x86_intercept_cr_write) | |
4456 | icpt_info.exit_code += info->modrm_reg; | |
4457 | ||
62baf44c JK |
4458 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 || |
4459 | info->intercept == x86_intercept_clts) | |
cfec82cb JR |
4460 | break; |
4461 | ||
4462 | intercept = svm->nested.intercept; | |
4463 | ||
4464 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
4465 | break; | |
4466 | ||
4467 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
4468 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
4469 | ||
4470 | if (info->intercept == x86_intercept_lmsw) { | |
4471 | cr0 &= 0xfUL; | |
4472 | val &= 0xfUL; | |
4473 | /* lmsw can't clear PE - catch this here */ | |
4474 | if (cr0 & X86_CR0_PE) | |
4475 | val |= X86_CR0_PE; | |
4476 | } | |
4477 | ||
4478 | if (cr0 ^ val) | |
4479 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
4480 | ||
4481 | break; | |
4482 | } | |
3b88e41a JR |
4483 | case SVM_EXIT_READ_DR0: |
4484 | case SVM_EXIT_WRITE_DR0: | |
4485 | icpt_info.exit_code += info->modrm_reg; | |
4486 | break; | |
8061252e JR |
4487 | case SVM_EXIT_MSR: |
4488 | if (info->intercept == x86_intercept_wrmsr) | |
4489 | vmcb->control.exit_info_1 = 1; | |
4490 | else | |
4491 | vmcb->control.exit_info_1 = 0; | |
4492 | break; | |
bf608f88 JR |
4493 | case SVM_EXIT_PAUSE: |
4494 | /* | |
4495 | * We get this for NOP only, but pause | |
4496 | * is rep not, check this here | |
4497 | */ | |
4498 | if (info->rep_prefix != REPE_PREFIX) | |
4499 | goto out; | |
f6511935 JR |
4500 | case SVM_EXIT_IOIO: { |
4501 | u64 exit_info; | |
4502 | u32 bytes; | |
4503 | ||
f6511935 JR |
4504 | if (info->intercept == x86_intercept_in || |
4505 | info->intercept == x86_intercept_ins) { | |
6cbc5f5a JK |
4506 | exit_info = ((info->src_val & 0xffff) << 16) | |
4507 | SVM_IOIO_TYPE_MASK; | |
f6511935 | 4508 | bytes = info->dst_bytes; |
6493f157 | 4509 | } else { |
6cbc5f5a | 4510 | exit_info = (info->dst_val & 0xffff) << 16; |
6493f157 | 4511 | bytes = info->src_bytes; |
f6511935 JR |
4512 | } |
4513 | ||
4514 | if (info->intercept == x86_intercept_outs || | |
4515 | info->intercept == x86_intercept_ins) | |
4516 | exit_info |= SVM_IOIO_STR_MASK; | |
4517 | ||
4518 | if (info->rep_prefix) | |
4519 | exit_info |= SVM_IOIO_REP_MASK; | |
4520 | ||
4521 | bytes = min(bytes, 4u); | |
4522 | ||
4523 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
4524 | ||
4525 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
4526 | ||
4527 | vmcb->control.exit_info_1 = exit_info; | |
4528 | vmcb->control.exit_info_2 = info->next_rip; | |
4529 | ||
4530 | break; | |
4531 | } | |
cfec82cb JR |
4532 | default: |
4533 | break; | |
4534 | } | |
4535 | ||
f104765b BD |
4536 | /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ |
4537 | if (static_cpu_has(X86_FEATURE_NRIPS)) | |
4538 | vmcb->control.next_rip = info->next_rip; | |
cfec82cb JR |
4539 | vmcb->control.exit_code = icpt_info.exit_code; |
4540 | vmexit = nested_svm_exit_handled(svm); | |
4541 | ||
4542 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
4543 | : X86EMUL_CONTINUE; | |
4544 | ||
4545 | out: | |
4546 | return ret; | |
8a76d7f2 JR |
4547 | } |
4548 | ||
a547c6db YZ |
4549 | static void svm_handle_external_intr(struct kvm_vcpu *vcpu) |
4550 | { | |
4551 | local_irq_enable(); | |
4552 | } | |
4553 | ||
ae97a3b8 RK |
4554 | static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) |
4555 | { | |
4556 | } | |
4557 | ||
cbdd1bea | 4558 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
4559 | .cpu_has_kvm_support = has_svm, |
4560 | .disabled_by_bios = is_disabled, | |
4561 | .hardware_setup = svm_hardware_setup, | |
4562 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 4563 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
4564 | .hardware_enable = svm_hardware_enable, |
4565 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 4566 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6d396b55 | 4567 | .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase, |
6aa8b732 AK |
4568 | |
4569 | .vcpu_create = svm_create_vcpu, | |
4570 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 4571 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 4572 | |
44a95dae SS |
4573 | .vm_init = avic_vm_init, |
4574 | .vm_destroy = avic_vm_destroy, | |
4575 | ||
04d2cc77 | 4576 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
4577 | .vcpu_load = svm_vcpu_load, |
4578 | .vcpu_put = svm_vcpu_put, | |
4579 | ||
a96036b8 | 4580 | .update_bp_intercept = update_bp_intercept, |
6aa8b732 AK |
4581 | .get_msr = svm_get_msr, |
4582 | .set_msr = svm_set_msr, | |
4583 | .get_segment_base = svm_get_segment_base, | |
4584 | .get_segment = svm_get_segment, | |
4585 | .set_segment = svm_set_segment, | |
2e4d2653 | 4586 | .get_cpl = svm_get_cpl, |
1747fb71 | 4587 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 4588 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 4589 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 4590 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 4591 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
4592 | .set_cr3 = svm_set_cr3, |
4593 | .set_cr4 = svm_set_cr4, | |
4594 | .set_efer = svm_set_efer, | |
4595 | .get_idt = svm_get_idt, | |
4596 | .set_idt = svm_set_idt, | |
4597 | .get_gdt = svm_get_gdt, | |
4598 | .set_gdt = svm_set_gdt, | |
73aaf249 JK |
4599 | .get_dr6 = svm_get_dr6, |
4600 | .set_dr6 = svm_set_dr6, | |
020df079 | 4601 | .set_dr7 = svm_set_dr7, |
facb0139 | 4602 | .sync_dirty_debug_regs = svm_sync_dirty_debug_regs, |
6de4f3ad | 4603 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
4604 | .get_rflags = svm_get_rflags, |
4605 | .set_rflags = svm_set_rflags, | |
be94f6b7 HH |
4606 | |
4607 | .get_pkru = svm_get_pkru, | |
4608 | ||
0fdd74f7 | 4609 | .fpu_activate = svm_fpu_activate, |
02daab21 | 4610 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 4611 | |
6aa8b732 | 4612 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 4613 | |
6aa8b732 | 4614 | .run = svm_vcpu_run, |
04d2cc77 | 4615 | .handle_exit = handle_exit, |
6aa8b732 | 4616 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4617 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
4618 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 4619 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 4620 | .set_irq = svm_set_irq, |
95ba8273 | 4621 | .set_nmi = svm_inject_nmi, |
298101da | 4622 | .queue_exception = svm_queue_exception, |
b463a6f7 | 4623 | .cancel_injection = svm_cancel_injection, |
78646121 | 4624 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 4625 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
4626 | .get_nmi_mask = svm_get_nmi_mask, |
4627 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
4628 | .enable_nmi_window = enable_nmi_window, |
4629 | .enable_irq_window = enable_irq_window, | |
4630 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 4631 | .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode, |
d62caabb AS |
4632 | .get_enable_apicv = svm_get_enable_apicv, |
4633 | .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl, | |
c7c9c56c | 4634 | .load_eoi_exitmap = svm_load_eoi_exitmap, |
a20ed54d | 4635 | .sync_pir_to_irr = svm_sync_pir_to_irr, |
44a95dae SS |
4636 | .hwapic_irr_update = svm_hwapic_irr_update, |
4637 | .hwapic_isr_update = svm_hwapic_isr_update, | |
cbc94022 IE |
4638 | |
4639 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 4640 | .get_tdp_level = get_npt_level, |
4b12f0de | 4641 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 4642 | |
586f9607 | 4643 | .get_exit_info = svm_get_exit_info, |
586f9607 | 4644 | |
17cc3935 | 4645 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
4646 | |
4647 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
4648 | |
4649 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 4650 | .invpcid_supported = svm_invpcid_supported, |
93c4adc7 | 4651 | .mpx_supported = svm_mpx_supported, |
55412b2e | 4652 | .xsaves_supported = svm_xsaves_supported, |
d4330ef2 JR |
4653 | |
4654 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
4655 | |
4656 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a | 4657 | |
ba904635 | 4658 | .read_tsc_offset = svm_read_tsc_offset, |
99e3e30a | 4659 | .write_tsc_offset = svm_write_tsc_offset, |
58ea6767 | 4660 | .adjust_tsc_offset_guest = svm_adjust_tsc_offset_guest, |
d5c1785d | 4661 | .read_l1_tsc = svm_read_l1_tsc, |
1c97f0a0 JR |
4662 | |
4663 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
4664 | |
4665 | .check_intercept = svm_check_intercept, | |
a547c6db | 4666 | .handle_external_intr = svm_handle_external_intr, |
ae97a3b8 RK |
4667 | |
4668 | .sched_in = svm_sched_in, | |
25462f7f WH |
4669 | |
4670 | .pmu_ops = &amd_pmu_ops, | |
340d3bc3 | 4671 | .deliver_posted_interrupt = svm_deliver_avic_intr, |
6aa8b732 AK |
4672 | }; |
4673 | ||
4674 | static int __init svm_init(void) | |
4675 | { | |
cb498ea2 | 4676 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 4677 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
4678 | } |
4679 | ||
4680 | static void __exit svm_exit(void) | |
4681 | { | |
cb498ea2 | 4682 | kvm_exit(); |
6aa8b732 AK |
4683 | } |
4684 | ||
4685 | module_init(svm_init) | |
4686 | module_exit(svm_exit) |