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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
44a95dae SS |
17 | |
18 | #define pr_fmt(fmt) "SVM: " fmt | |
19 | ||
edf88417 AK |
20 | #include <linux/kvm_host.h> |
21 | ||
85f455f7 | 22 | #include "irq.h" |
1d737c8a | 23 | #include "mmu.h" |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
fe4c7b19 | 25 | #include "x86.h" |
66f7b72e | 26 | #include "cpuid.h" |
25462f7f | 27 | #include "pmu.h" |
e495606d | 28 | |
6aa8b732 | 29 | #include <linux/module.h> |
ae759544 | 30 | #include <linux/mod_devicetable.h> |
9d8f549d | 31 | #include <linux/kernel.h> |
6aa8b732 AK |
32 | #include <linux/vmalloc.h> |
33 | #include <linux/highmem.h> | |
e8edc6e0 | 34 | #include <linux/sched.h> |
af658dca | 35 | #include <linux/trace_events.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
5881f737 SS |
37 | #include <linux/amd-iommu.h> |
38 | #include <linux/hashtable.h> | |
6aa8b732 | 39 | |
8221c137 | 40 | #include <asm/apic.h> |
1018faa6 | 41 | #include <asm/perf_event.h> |
67ec6607 | 42 | #include <asm/tlbflush.h> |
e495606d | 43 | #include <asm/desc.h> |
facb0139 | 44 | #include <asm/debugreg.h> |
631bc487 | 45 | #include <asm/kvm_para.h> |
411b44ba | 46 | #include <asm/irq_remapping.h> |
6aa8b732 | 47 | |
63d1142f | 48 | #include <asm/virtext.h> |
229456fc | 49 | #include "trace.h" |
63d1142f | 50 | |
4ecac3fd AK |
51 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
52 | ||
6aa8b732 AK |
53 | MODULE_AUTHOR("Qumranet"); |
54 | MODULE_LICENSE("GPL"); | |
55 | ||
ae759544 JT |
56 | static const struct x86_cpu_id svm_cpu_id[] = { |
57 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
58 | {} | |
59 | }; | |
60 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
61 | ||
6aa8b732 AK |
62 | #define IOPM_ALLOC_ORDER 2 |
63 | #define MSRPM_ALLOC_ORDER 1 | |
64 | ||
6aa8b732 AK |
65 | #define SEG_TYPE_LDT 2 |
66 | #define SEG_TYPE_BUSY_TSS16 3 | |
67 | ||
6bc31bdc AP |
68 | #define SVM_FEATURE_NPT (1 << 0) |
69 | #define SVM_FEATURE_LBRV (1 << 1) | |
70 | #define SVM_FEATURE_SVML (1 << 2) | |
71 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
72 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
73 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
74 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
75 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 76 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 77 | |
340d3bc3 SS |
78 | #define SVM_AVIC_DOORBELL 0xc001011b |
79 | ||
410e4d57 JR |
80 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
81 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
82 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
83 | ||
24e09cbf JR |
84 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
85 | ||
fbc0db76 | 86 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
87 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
88 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 89 | |
5446a979 | 90 | #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) |
44a95dae SS |
91 | |
92 | /* | |
93 | * 0xff is broadcast, so the max index allowed for physical APIC ID | |
94 | * table is 0xfe. APIC IDs above 0xff are reserved. | |
95 | */ | |
96 | #define AVIC_MAX_PHYSICAL_ID_COUNT 255 | |
97 | ||
18f40c53 SS |
98 | #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 |
99 | #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 | |
100 | #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF | |
101 | ||
5ea11f2b SS |
102 | /* AVIC GATAG is encoded using VM and VCPU IDs */ |
103 | #define AVIC_VCPU_ID_BITS 8 | |
104 | #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1) | |
105 | ||
106 | #define AVIC_VM_ID_BITS 24 | |
107 | #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS) | |
108 | #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1) | |
109 | ||
110 | #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \ | |
111 | (y & AVIC_VCPU_ID_MASK)) | |
112 | #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK) | |
113 | #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK) | |
114 | ||
67ec6607 JR |
115 | static bool erratum_383_found __read_mostly; |
116 | ||
6c8166a7 AK |
117 | static const u32 host_save_user_msrs[] = { |
118 | #ifdef CONFIG_X86_64 | |
119 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
120 | MSR_FS_BASE, | |
121 | #endif | |
122 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
46896c73 | 123 | MSR_TSC_AUX, |
6c8166a7 AK |
124 | }; |
125 | ||
126 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
127 | ||
128 | struct kvm_vcpu; | |
129 | ||
e6aa9abd JR |
130 | struct nested_state { |
131 | struct vmcb *hsave; | |
132 | u64 hsave_msr; | |
4a810181 | 133 | u64 vm_cr_msr; |
e6aa9abd JR |
134 | u64 vmcb; |
135 | ||
136 | /* These are the merged vectors */ | |
137 | u32 *msrpm; | |
138 | ||
139 | /* gpa pointers to the real vectors */ | |
140 | u64 vmcb_msrpm; | |
ce2ac085 | 141 | u64 vmcb_iopm; |
aad42c64 | 142 | |
cd3ff653 JR |
143 | /* A VMEXIT is required but not yet emulated */ |
144 | bool exit_required; | |
145 | ||
aad42c64 | 146 | /* cache for intercepts of the guest */ |
4ee546b4 | 147 | u32 intercept_cr; |
3aed041a | 148 | u32 intercept_dr; |
aad42c64 JR |
149 | u32 intercept_exceptions; |
150 | u64 intercept; | |
151 | ||
5bd2edc3 JR |
152 | /* Nested Paging related state */ |
153 | u64 nested_cr3; | |
e6aa9abd JR |
154 | }; |
155 | ||
323c3d80 JR |
156 | #define MSRPM_OFFSETS 16 |
157 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
158 | ||
2b036c6b BO |
159 | /* |
160 | * Set osvw_len to higher value when updated Revision Guides | |
161 | * are published and we know what the new status bits are | |
162 | */ | |
163 | static uint64_t osvw_len = 4, osvw_status; | |
164 | ||
6c8166a7 AK |
165 | struct vcpu_svm { |
166 | struct kvm_vcpu vcpu; | |
167 | struct vmcb *vmcb; | |
168 | unsigned long vmcb_pa; | |
169 | struct svm_cpu_data *svm_data; | |
170 | uint64_t asid_generation; | |
171 | uint64_t sysenter_esp; | |
172 | uint64_t sysenter_eip; | |
46896c73 | 173 | uint64_t tsc_aux; |
6c8166a7 AK |
174 | |
175 | u64 next_rip; | |
176 | ||
177 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 178 | struct { |
dacccfdd AK |
179 | u16 fs; |
180 | u16 gs; | |
181 | u16 ldt; | |
afe9e66f AK |
182 | u64 gs_base; |
183 | } host; | |
6c8166a7 AK |
184 | |
185 | u32 *msrpm; | |
6c8166a7 | 186 | |
bd3d1ec3 AK |
187 | ulong nmi_iret_rip; |
188 | ||
e6aa9abd | 189 | struct nested_state nested; |
6be7d306 JK |
190 | |
191 | bool nmi_singlestep; | |
ab2f4d73 | 192 | u64 nmi_singlestep_guest_rflags; |
66b7138f JK |
193 | |
194 | unsigned int3_injected; | |
195 | unsigned long int3_rip; | |
631bc487 | 196 | u32 apf_reason; |
fbc0db76 | 197 | |
6092d3d3 JR |
198 | /* cached guest cpuid flags for faster access */ |
199 | bool nrips_enabled : 1; | |
44a95dae | 200 | |
18f40c53 | 201 | u32 ldr_reg; |
44a95dae SS |
202 | struct page *avic_backing_page; |
203 | u64 *avic_physical_id_cache; | |
8221c137 | 204 | bool avic_is_running; |
411b44ba SS |
205 | |
206 | /* | |
207 | * Per-vcpu list of struct amd_svm_iommu_ir: | |
208 | * This is used mainly to store interrupt remapping information used | |
209 | * when update the vcpu affinity. This avoids the need to scan for | |
210 | * IRTE and try to match ga_tag in the IOMMU driver. | |
211 | */ | |
212 | struct list_head ir_list; | |
213 | spinlock_t ir_list_lock; | |
214 | }; | |
215 | ||
216 | /* | |
217 | * This is a wrapper of struct amd_iommu_ir_data. | |
218 | */ | |
219 | struct amd_svm_iommu_ir { | |
220 | struct list_head node; /* Used by SVM for per-vcpu ir_list */ | |
221 | void *data; /* Storing pointer to struct amd_ir_data */ | |
6c8166a7 AK |
222 | }; |
223 | ||
44a95dae SS |
224 | #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) |
225 | #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) | |
226 | ||
227 | #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) | |
228 | #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) | |
229 | #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) | |
230 | #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) | |
231 | ||
fbc0db76 JR |
232 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
233 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
234 | ||
455716fa JR |
235 | #define MSR_INVALID 0xffffffffU |
236 | ||
09941fbb | 237 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
238 | u32 index; /* Index of the MSR */ |
239 | bool always; /* True if intercept is always on */ | |
240 | } direct_access_msrs[] = { | |
8c06585d | 241 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
242 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
243 | #ifdef CONFIG_X86_64 | |
244 | { .index = MSR_GS_BASE, .always = true }, | |
245 | { .index = MSR_FS_BASE, .always = true }, | |
246 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
247 | { .index = MSR_LSTAR, .always = true }, | |
248 | { .index = MSR_CSTAR, .always = true }, | |
249 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
250 | #endif | |
251 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
252 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
253 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
254 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
255 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
256 | }; |
257 | ||
709ddebf JR |
258 | /* enable NPT for AMD64 and X86 with PAE */ |
259 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
260 | static bool npt_enabled = true; | |
261 | #else | |
e0231715 | 262 | static bool npt_enabled; |
709ddebf | 263 | #endif |
6c7dac72 | 264 | |
e2358851 DB |
265 | /* allow nested paging (virtualized MMU) for all guests */ |
266 | static int npt = true; | |
6c7dac72 | 267 | module_param(npt, int, S_IRUGO); |
e3da3acd | 268 | |
e2358851 DB |
269 | /* allow nested virtualization in KVM/SVM */ |
270 | static int nested = true; | |
236de055 AG |
271 | module_param(nested, int, S_IRUGO); |
272 | ||
44a95dae SS |
273 | /* enable / disable AVIC */ |
274 | static int avic; | |
5b8abf1f | 275 | #ifdef CONFIG_X86_LOCAL_APIC |
44a95dae | 276 | module_param(avic, int, S_IRUGO); |
5b8abf1f | 277 | #endif |
44a95dae | 278 | |
5ea11f2b SS |
279 | /* AVIC VM ID bit masks and lock */ |
280 | static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR); | |
281 | static DEFINE_SPINLOCK(avic_vm_id_lock); | |
282 | ||
79a8059d | 283 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
44874f84 | 284 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 285 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 286 | |
410e4d57 | 287 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 288 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 289 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
290 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
291 | bool has_error_code, u32 error_code); | |
292 | ||
8d28fec4 | 293 | enum { |
116a0a23 JR |
294 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
295 | pause filter count */ | |
f56838e4 | 296 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 297 | VMCB_ASID, /* ASID */ |
decdbf6a | 298 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 299 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 300 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 301 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 302 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 303 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 304 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 305 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
44a95dae SS |
306 | VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, |
307 | * AVIC PHYSICAL_TABLE pointer, | |
308 | * AVIC LOGICAL_TABLE pointer | |
309 | */ | |
8d28fec4 RJ |
310 | VMCB_DIRTY_MAX, |
311 | }; | |
312 | ||
0574dec0 JR |
313 | /* TPR and CR2 are always written before VMRUN */ |
314 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 | 315 | |
44a95dae SS |
316 | #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL |
317 | ||
8d28fec4 RJ |
318 | static inline void mark_all_dirty(struct vmcb *vmcb) |
319 | { | |
320 | vmcb->control.clean = 0; | |
321 | } | |
322 | ||
323 | static inline void mark_all_clean(struct vmcb *vmcb) | |
324 | { | |
325 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
326 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
327 | } | |
328 | ||
329 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
330 | { | |
331 | vmcb->control.clean &= ~(1 << bit); | |
332 | } | |
333 | ||
a2fa3e9f GH |
334 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
335 | { | |
fb3f0f51 | 336 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
337 | } |
338 | ||
44a95dae SS |
339 | static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) |
340 | { | |
341 | svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; | |
342 | mark_dirty(svm->vmcb, VMCB_AVIC); | |
343 | } | |
344 | ||
340d3bc3 SS |
345 | static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) |
346 | { | |
347 | struct vcpu_svm *svm = to_svm(vcpu); | |
348 | u64 *entry = svm->avic_physical_id_cache; | |
349 | ||
350 | if (!entry) | |
351 | return false; | |
352 | ||
353 | return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
354 | } | |
355 | ||
384c6368 JR |
356 | static void recalc_intercepts(struct vcpu_svm *svm) |
357 | { | |
358 | struct vmcb_control_area *c, *h; | |
359 | struct nested_state *g; | |
360 | ||
116a0a23 JR |
361 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
362 | ||
384c6368 JR |
363 | if (!is_guest_mode(&svm->vcpu)) |
364 | return; | |
365 | ||
366 | c = &svm->vmcb->control; | |
367 | h = &svm->nested.hsave->control; | |
368 | g = &svm->nested; | |
369 | ||
4ee546b4 | 370 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 371 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
372 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
373 | c->intercept = h->intercept | g->intercept; | |
374 | } | |
375 | ||
4ee546b4 RJ |
376 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
377 | { | |
378 | if (is_guest_mode(&svm->vcpu)) | |
379 | return svm->nested.hsave; | |
380 | else | |
381 | return svm->vmcb; | |
382 | } | |
383 | ||
384 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
385 | { | |
386 | struct vmcb *vmcb = get_host_vmcb(svm); | |
387 | ||
388 | vmcb->control.intercept_cr |= (1U << bit); | |
389 | ||
390 | recalc_intercepts(svm); | |
391 | } | |
392 | ||
393 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
394 | { | |
395 | struct vmcb *vmcb = get_host_vmcb(svm); | |
396 | ||
397 | vmcb->control.intercept_cr &= ~(1U << bit); | |
398 | ||
399 | recalc_intercepts(svm); | |
400 | } | |
401 | ||
402 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
403 | { | |
404 | struct vmcb *vmcb = get_host_vmcb(svm); | |
405 | ||
406 | return vmcb->control.intercept_cr & (1U << bit); | |
407 | } | |
408 | ||
5315c716 | 409 | static inline void set_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
410 | { |
411 | struct vmcb *vmcb = get_host_vmcb(svm); | |
412 | ||
5315c716 PB |
413 | vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) |
414 | | (1 << INTERCEPT_DR1_READ) | |
415 | | (1 << INTERCEPT_DR2_READ) | |
416 | | (1 << INTERCEPT_DR3_READ) | |
417 | | (1 << INTERCEPT_DR4_READ) | |
418 | | (1 << INTERCEPT_DR5_READ) | |
419 | | (1 << INTERCEPT_DR6_READ) | |
420 | | (1 << INTERCEPT_DR7_READ) | |
421 | | (1 << INTERCEPT_DR0_WRITE) | |
422 | | (1 << INTERCEPT_DR1_WRITE) | |
423 | | (1 << INTERCEPT_DR2_WRITE) | |
424 | | (1 << INTERCEPT_DR3_WRITE) | |
425 | | (1 << INTERCEPT_DR4_WRITE) | |
426 | | (1 << INTERCEPT_DR5_WRITE) | |
427 | | (1 << INTERCEPT_DR6_WRITE) | |
428 | | (1 << INTERCEPT_DR7_WRITE); | |
3aed041a JR |
429 | |
430 | recalc_intercepts(svm); | |
431 | } | |
432 | ||
5315c716 | 433 | static inline void clr_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
434 | { |
435 | struct vmcb *vmcb = get_host_vmcb(svm); | |
436 | ||
5315c716 | 437 | vmcb->control.intercept_dr = 0; |
3aed041a JR |
438 | |
439 | recalc_intercepts(svm); | |
440 | } | |
441 | ||
18c918c5 JR |
442 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
443 | { | |
444 | struct vmcb *vmcb = get_host_vmcb(svm); | |
445 | ||
446 | vmcb->control.intercept_exceptions |= (1U << bit); | |
447 | ||
448 | recalc_intercepts(svm); | |
449 | } | |
450 | ||
451 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
452 | { | |
453 | struct vmcb *vmcb = get_host_vmcb(svm); | |
454 | ||
455 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
456 | ||
457 | recalc_intercepts(svm); | |
458 | } | |
459 | ||
8a05a1b8 JR |
460 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
461 | { | |
462 | struct vmcb *vmcb = get_host_vmcb(svm); | |
463 | ||
464 | vmcb->control.intercept |= (1ULL << bit); | |
465 | ||
466 | recalc_intercepts(svm); | |
467 | } | |
468 | ||
469 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
470 | { | |
471 | struct vmcb *vmcb = get_host_vmcb(svm); | |
472 | ||
473 | vmcb->control.intercept &= ~(1ULL << bit); | |
474 | ||
475 | recalc_intercepts(svm); | |
476 | } | |
477 | ||
2af9194d JR |
478 | static inline void enable_gif(struct vcpu_svm *svm) |
479 | { | |
480 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
481 | } | |
482 | ||
483 | static inline void disable_gif(struct vcpu_svm *svm) | |
484 | { | |
485 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
486 | } | |
487 | ||
488 | static inline bool gif_set(struct vcpu_svm *svm) | |
489 | { | |
490 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
491 | } | |
492 | ||
4866d5e3 | 493 | static unsigned long iopm_base; |
6aa8b732 AK |
494 | |
495 | struct kvm_ldttss_desc { | |
496 | u16 limit0; | |
497 | u16 base0; | |
e0231715 JR |
498 | unsigned base1:8, type:5, dpl:2, p:1; |
499 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
500 | u32 base3; |
501 | u32 zero1; | |
502 | } __attribute__((packed)); | |
503 | ||
504 | struct svm_cpu_data { | |
505 | int cpu; | |
506 | ||
5008fdf5 AK |
507 | u64 asid_generation; |
508 | u32 max_asid; | |
509 | u32 next_asid; | |
6aa8b732 AK |
510 | struct kvm_ldttss_desc *tss_desc; |
511 | ||
512 | struct page *save_area; | |
513 | }; | |
514 | ||
515 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
516 | ||
517 | struct svm_init_data { | |
518 | int cpu; | |
519 | int r; | |
520 | }; | |
521 | ||
09941fbb | 522 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 523 | |
9d8f549d | 524 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
525 | #define MSRS_RANGE_SIZE 2048 |
526 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
527 | ||
455716fa JR |
528 | static u32 svm_msrpm_offset(u32 msr) |
529 | { | |
530 | u32 offset; | |
531 | int i; | |
532 | ||
533 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
534 | if (msr < msrpm_ranges[i] || | |
535 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
536 | continue; | |
537 | ||
538 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
539 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
540 | ||
541 | /* Now we have the u8 offset - but need the u32 offset */ | |
542 | return offset / 4; | |
543 | } | |
544 | ||
545 | /* MSR not in any range */ | |
546 | return MSR_INVALID; | |
547 | } | |
548 | ||
6aa8b732 AK |
549 | #define MAX_INST_SIZE 15 |
550 | ||
6aa8b732 AK |
551 | static inline void clgi(void) |
552 | { | |
4ecac3fd | 553 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
554 | } |
555 | ||
556 | static inline void stgi(void) | |
557 | { | |
4ecac3fd | 558 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
559 | } |
560 | ||
561 | static inline void invlpga(unsigned long addr, u32 asid) | |
562 | { | |
e0231715 | 563 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
564 | } |
565 | ||
4b16184c JR |
566 | static int get_npt_level(void) |
567 | { | |
568 | #ifdef CONFIG_X86_64 | |
569 | return PT64_ROOT_LEVEL; | |
570 | #else | |
571 | return PT32E_ROOT_LEVEL; | |
572 | #endif | |
573 | } | |
574 | ||
6aa8b732 AK |
575 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
576 | { | |
6dc696d4 | 577 | vcpu->arch.efer = efer; |
709ddebf | 578 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 579 | efer &= ~EFER_LME; |
6aa8b732 | 580 | |
9962d032 | 581 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 582 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
583 | } |
584 | ||
6aa8b732 AK |
585 | static int is_external_interrupt(u32 info) |
586 | { | |
587 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
588 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
589 | } | |
590 | ||
37ccdcbe | 591 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
592 | { |
593 | struct vcpu_svm *svm = to_svm(vcpu); | |
594 | u32 ret = 0; | |
595 | ||
596 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
37ccdcbe PB |
597 | ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
598 | return ret; | |
2809f5d2 GC |
599 | } |
600 | ||
601 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
602 | { | |
603 | struct vcpu_svm *svm = to_svm(vcpu); | |
604 | ||
605 | if (mask == 0) | |
606 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
607 | else | |
608 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
609 | ||
610 | } | |
611 | ||
6aa8b732 AK |
612 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
613 | { | |
a2fa3e9f GH |
614 | struct vcpu_svm *svm = to_svm(vcpu); |
615 | ||
f104765b | 616 | if (svm->vmcb->control.next_rip != 0) { |
d2922422 | 617 | WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS)); |
6bc31bdc | 618 | svm->next_rip = svm->vmcb->control.next_rip; |
f104765b | 619 | } |
6bc31bdc | 620 | |
a2fa3e9f | 621 | if (!svm->next_rip) { |
51d8b661 | 622 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
623 | EMULATE_DONE) |
624 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
625 | return; |
626 | } | |
5fdbf976 MT |
627 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
628 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
629 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 630 | |
5fdbf976 | 631 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 632 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
633 | } |
634 | ||
116a4752 | 635 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
636 | bool has_error_code, u32 error_code, |
637 | bool reinject) | |
116a4752 JK |
638 | { |
639 | struct vcpu_svm *svm = to_svm(vcpu); | |
640 | ||
e0231715 JR |
641 | /* |
642 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
643 | * handle the exception | |
644 | */ | |
ce7ddec4 JR |
645 | if (!reinject && |
646 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
647 | return; |
648 | ||
2a6b20b8 | 649 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
650 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
651 | ||
652 | /* | |
653 | * For guest debugging where we have to reinject #BP if some | |
654 | * INT3 is guest-owned: | |
655 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
656 | * raises a fault that is not intercepted. Still better than | |
657 | * failing in all cases. | |
658 | */ | |
659 | skip_emulated_instruction(&svm->vcpu); | |
660 | rip = kvm_rip_read(&svm->vcpu); | |
661 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
662 | svm->int3_injected = rip - old_rip; | |
663 | } | |
664 | ||
116a4752 JK |
665 | svm->vmcb->control.event_inj = nr |
666 | | SVM_EVTINJ_VALID | |
667 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
668 | | SVM_EVTINJ_TYPE_EXEPT; | |
669 | svm->vmcb->control.event_inj_err = error_code; | |
670 | } | |
671 | ||
67ec6607 JR |
672 | static void svm_init_erratum_383(void) |
673 | { | |
674 | u32 low, high; | |
675 | int err; | |
676 | u64 val; | |
677 | ||
e6ee94d5 | 678 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
679 | return; |
680 | ||
681 | /* Use _safe variants to not break nested virtualization */ | |
682 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
683 | if (err) | |
684 | return; | |
685 | ||
686 | val |= (1ULL << 47); | |
687 | ||
688 | low = lower_32_bits(val); | |
689 | high = upper_32_bits(val); | |
690 | ||
691 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
692 | ||
693 | erratum_383_found = true; | |
694 | } | |
695 | ||
2b036c6b BO |
696 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
697 | { | |
698 | /* | |
699 | * Guests should see errata 400 and 415 as fixed (assuming that | |
700 | * HLT and IO instructions are intercepted). | |
701 | */ | |
702 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
703 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
704 | ||
705 | /* | |
706 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
707 | * all osvw.status bits inside that length, including bit 0 (which is | |
708 | * reserved for erratum 298), are valid. However, if host processor's | |
709 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
710 | * be conservative here and therefore we tell the guest that erratum 298 | |
711 | * is present (because we really don't know). | |
712 | */ | |
713 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
714 | vcpu->arch.osvw.status |= 1; | |
715 | } | |
716 | ||
6aa8b732 AK |
717 | static int has_svm(void) |
718 | { | |
63d1142f | 719 | const char *msg; |
6aa8b732 | 720 | |
63d1142f | 721 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 722 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
723 | return 0; |
724 | } | |
725 | ||
6aa8b732 AK |
726 | return 1; |
727 | } | |
728 | ||
13a34e06 | 729 | static void svm_hardware_disable(void) |
6aa8b732 | 730 | { |
fbc0db76 JR |
731 | /* Make sure we clean up behind us */ |
732 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
733 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
734 | ||
2c8dceeb | 735 | cpu_svm_disable(); |
1018faa6 JR |
736 | |
737 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
738 | } |
739 | ||
13a34e06 | 740 | static int svm_hardware_enable(void) |
6aa8b732 AK |
741 | { |
742 | ||
0fe1e009 | 743 | struct svm_cpu_data *sd; |
6aa8b732 | 744 | uint64_t efer; |
6aa8b732 AK |
745 | struct desc_struct *gdt; |
746 | int me = raw_smp_processor_id(); | |
747 | ||
10474ae8 AG |
748 | rdmsrl(MSR_EFER, efer); |
749 | if (efer & EFER_SVME) | |
750 | return -EBUSY; | |
751 | ||
6aa8b732 | 752 | if (!has_svm()) { |
1f5b77f5 | 753 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 754 | return -EINVAL; |
6aa8b732 | 755 | } |
0fe1e009 | 756 | sd = per_cpu(svm_data, me); |
0fe1e009 | 757 | if (!sd) { |
1f5b77f5 | 758 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 759 | return -EINVAL; |
6aa8b732 AK |
760 | } |
761 | ||
0fe1e009 TH |
762 | sd->asid_generation = 1; |
763 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
764 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 765 | |
45fc8757 | 766 | gdt = get_current_gdt_rw(); |
0fe1e009 | 767 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 768 | |
9962d032 | 769 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 770 | |
d0316554 | 771 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 772 | |
fbc0db76 JR |
773 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
774 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
89cbc767 | 775 | __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT); |
fbc0db76 JR |
776 | } |
777 | ||
2b036c6b BO |
778 | |
779 | /* | |
780 | * Get OSVW bits. | |
781 | * | |
782 | * Note that it is possible to have a system with mixed processor | |
783 | * revisions and therefore different OSVW bits. If bits are not the same | |
784 | * on different processors then choose the worst case (i.e. if erratum | |
785 | * is present on one processor and not on another then assume that the | |
786 | * erratum is present everywhere). | |
787 | */ | |
788 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
789 | uint64_t len, status = 0; | |
790 | int err; | |
791 | ||
792 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
793 | if (!err) | |
794 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
795 | &err); | |
796 | ||
797 | if (err) | |
798 | osvw_status = osvw_len = 0; | |
799 | else { | |
800 | if (len < osvw_len) | |
801 | osvw_len = len; | |
802 | osvw_status |= status; | |
803 | osvw_status &= (1ULL << osvw_len) - 1; | |
804 | } | |
805 | } else | |
806 | osvw_status = osvw_len = 0; | |
807 | ||
67ec6607 JR |
808 | svm_init_erratum_383(); |
809 | ||
1018faa6 JR |
810 | amd_pmu_enable_virt(); |
811 | ||
10474ae8 | 812 | return 0; |
6aa8b732 AK |
813 | } |
814 | ||
0da1db75 JR |
815 | static void svm_cpu_uninit(int cpu) |
816 | { | |
0fe1e009 | 817 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 818 | |
0fe1e009 | 819 | if (!sd) |
0da1db75 JR |
820 | return; |
821 | ||
822 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
823 | __free_page(sd->save_area); |
824 | kfree(sd); | |
0da1db75 JR |
825 | } |
826 | ||
6aa8b732 AK |
827 | static int svm_cpu_init(int cpu) |
828 | { | |
0fe1e009 | 829 | struct svm_cpu_data *sd; |
6aa8b732 AK |
830 | int r; |
831 | ||
0fe1e009 TH |
832 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
833 | if (!sd) | |
6aa8b732 | 834 | return -ENOMEM; |
0fe1e009 TH |
835 | sd->cpu = cpu; |
836 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 837 | r = -ENOMEM; |
0fe1e009 | 838 | if (!sd->save_area) |
6aa8b732 AK |
839 | goto err_1; |
840 | ||
0fe1e009 | 841 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
842 | |
843 | return 0; | |
844 | ||
845 | err_1: | |
0fe1e009 | 846 | kfree(sd); |
6aa8b732 AK |
847 | return r; |
848 | ||
849 | } | |
850 | ||
ac72a9b7 JR |
851 | static bool valid_msr_intercept(u32 index) |
852 | { | |
853 | int i; | |
854 | ||
855 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
856 | if (direct_access_msrs[i].index == index) | |
857 | return true; | |
858 | ||
859 | return false; | |
860 | } | |
861 | ||
bfc733a7 RR |
862 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
863 | int read, int write) | |
6aa8b732 | 864 | { |
455716fa JR |
865 | u8 bit_read, bit_write; |
866 | unsigned long tmp; | |
867 | u32 offset; | |
6aa8b732 | 868 | |
ac72a9b7 JR |
869 | /* |
870 | * If this warning triggers extend the direct_access_msrs list at the | |
871 | * beginning of the file | |
872 | */ | |
873 | WARN_ON(!valid_msr_intercept(msr)); | |
874 | ||
455716fa JR |
875 | offset = svm_msrpm_offset(msr); |
876 | bit_read = 2 * (msr & 0x0f); | |
877 | bit_write = 2 * (msr & 0x0f) + 1; | |
878 | tmp = msrpm[offset]; | |
879 | ||
880 | BUG_ON(offset == MSR_INVALID); | |
881 | ||
882 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
883 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
884 | ||
885 | msrpm[offset] = tmp; | |
6aa8b732 AK |
886 | } |
887 | ||
f65c229c | 888 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
889 | { |
890 | int i; | |
891 | ||
f65c229c JR |
892 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
893 | ||
ac72a9b7 JR |
894 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
895 | if (!direct_access_msrs[i].always) | |
896 | continue; | |
897 | ||
898 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
899 | } | |
f65c229c JR |
900 | } |
901 | ||
323c3d80 JR |
902 | static void add_msr_offset(u32 offset) |
903 | { | |
904 | int i; | |
905 | ||
906 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
907 | ||
908 | /* Offset already in list? */ | |
909 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 910 | return; |
323c3d80 JR |
911 | |
912 | /* Slot used by another offset? */ | |
913 | if (msrpm_offsets[i] != MSR_INVALID) | |
914 | continue; | |
915 | ||
916 | /* Add offset to list */ | |
917 | msrpm_offsets[i] = offset; | |
918 | ||
919 | return; | |
6aa8b732 | 920 | } |
323c3d80 JR |
921 | |
922 | /* | |
923 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
924 | * increase MSRPM_OFFSETS in this case. | |
925 | */ | |
bfc733a7 | 926 | BUG(); |
6aa8b732 AK |
927 | } |
928 | ||
323c3d80 | 929 | static void init_msrpm_offsets(void) |
f65c229c | 930 | { |
323c3d80 | 931 | int i; |
f65c229c | 932 | |
323c3d80 JR |
933 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
934 | ||
935 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
936 | u32 offset; | |
937 | ||
938 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
939 | BUG_ON(offset == MSR_INVALID); | |
940 | ||
941 | add_msr_offset(offset); | |
942 | } | |
f65c229c JR |
943 | } |
944 | ||
24e09cbf JR |
945 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
946 | { | |
947 | u32 *msrpm = svm->msrpm; | |
948 | ||
949 | svm->vmcb->control.lbr_ctl = 1; | |
950 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
951 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
952 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
953 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
954 | } | |
955 | ||
956 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
957 | { | |
958 | u32 *msrpm = svm->msrpm; | |
959 | ||
960 | svm->vmcb->control.lbr_ctl = 0; | |
961 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
962 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
963 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
964 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
965 | } | |
966 | ||
4aebd0e9 LP |
967 | static void disable_nmi_singlestep(struct vcpu_svm *svm) |
968 | { | |
969 | svm->nmi_singlestep = false; | |
ab2f4d73 LP |
970 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) { |
971 | /* Clear our flags if they were not set by the guest */ | |
972 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
973 | svm->vmcb->save.rflags &= ~X86_EFLAGS_TF; | |
974 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
975 | svm->vmcb->save.rflags &= ~X86_EFLAGS_RF; | |
976 | } | |
4aebd0e9 LP |
977 | } |
978 | ||
5881f737 SS |
979 | /* Note: |
980 | * This hash table is used to map VM_ID to a struct kvm_arch, | |
981 | * when handling AMD IOMMU GALOG notification to schedule in | |
982 | * a particular vCPU. | |
983 | */ | |
984 | #define SVM_VM_DATA_HASH_BITS 8 | |
681bcea8 DH |
985 | static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS); |
986 | static DEFINE_SPINLOCK(svm_vm_data_hash_lock); | |
5881f737 SS |
987 | |
988 | /* Note: | |
989 | * This function is called from IOMMU driver to notify | |
990 | * SVM to schedule in a particular vCPU of a particular VM. | |
991 | */ | |
992 | static int avic_ga_log_notifier(u32 ga_tag) | |
993 | { | |
994 | unsigned long flags; | |
995 | struct kvm_arch *ka = NULL; | |
996 | struct kvm_vcpu *vcpu = NULL; | |
997 | u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag); | |
998 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag); | |
999 | ||
1000 | pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id); | |
1001 | ||
1002 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
1003 | hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) { | |
1004 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
1005 | struct kvm_arch *vm_data = &kvm->arch; | |
1006 | ||
1007 | if (vm_data->avic_vm_id != vm_id) | |
1008 | continue; | |
1009 | vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); | |
1010 | break; | |
1011 | } | |
1012 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
1013 | ||
1014 | if (!vcpu) | |
1015 | return 0; | |
1016 | ||
1017 | /* Note: | |
1018 | * At this point, the IOMMU should have already set the pending | |
1019 | * bit in the vAPIC backing page. So, we just need to schedule | |
1020 | * in the vcpu. | |
1021 | */ | |
1022 | if (vcpu->mode == OUTSIDE_GUEST_MODE) | |
1023 | kvm_vcpu_wake_up(vcpu); | |
1024 | ||
1025 | return 0; | |
1026 | } | |
1027 | ||
6aa8b732 AK |
1028 | static __init int svm_hardware_setup(void) |
1029 | { | |
1030 | int cpu; | |
1031 | struct page *iopm_pages; | |
f65c229c | 1032 | void *iopm_va; |
6aa8b732 AK |
1033 | int r; |
1034 | ||
6aa8b732 AK |
1035 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
1036 | ||
1037 | if (!iopm_pages) | |
1038 | return -ENOMEM; | |
c8681339 AL |
1039 | |
1040 | iopm_va = page_address(iopm_pages); | |
1041 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
1042 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
1043 | ||
323c3d80 JR |
1044 | init_msrpm_offsets(); |
1045 | ||
50a37eb4 JR |
1046 | if (boot_cpu_has(X86_FEATURE_NX)) |
1047 | kvm_enable_efer_bits(EFER_NX); | |
1048 | ||
1b2fd70c AG |
1049 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
1050 | kvm_enable_efer_bits(EFER_FFXSR); | |
1051 | ||
92a1f12d | 1052 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
92a1f12d | 1053 | kvm_has_tsc_control = true; |
bc9b961b HZ |
1054 | kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX; |
1055 | kvm_tsc_scaling_ratio_frac_bits = 32; | |
92a1f12d JR |
1056 | } |
1057 | ||
236de055 AG |
1058 | if (nested) { |
1059 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 1060 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
1061 | } |
1062 | ||
3230bb47 | 1063 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
1064 | r = svm_cpu_init(cpu); |
1065 | if (r) | |
f65c229c | 1066 | goto err; |
6aa8b732 | 1067 | } |
33bd6a0b | 1068 | |
2a6b20b8 | 1069 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
1070 | npt_enabled = false; |
1071 | ||
6c7dac72 JR |
1072 | if (npt_enabled && !npt) { |
1073 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
1074 | npt_enabled = false; | |
1075 | } | |
1076 | ||
18552672 | 1077 | if (npt_enabled) { |
e3da3acd | 1078 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 1079 | kvm_enable_tdp(); |
5f4cb662 JR |
1080 | } else |
1081 | kvm_disable_tdp(); | |
e3da3acd | 1082 | |
5b8abf1f SS |
1083 | if (avic) { |
1084 | if (!npt_enabled || | |
1085 | !boot_cpu_has(X86_FEATURE_AVIC) || | |
5881f737 | 1086 | !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) { |
5b8abf1f | 1087 | avic = false; |
5881f737 | 1088 | } else { |
5b8abf1f | 1089 | pr_info("AVIC enabled\n"); |
5881f737 | 1090 | |
5881f737 SS |
1091 | amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); |
1092 | } | |
5b8abf1f | 1093 | } |
44a95dae | 1094 | |
6aa8b732 AK |
1095 | return 0; |
1096 | ||
f65c229c | 1097 | err: |
6aa8b732 AK |
1098 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
1099 | iopm_base = 0; | |
1100 | return r; | |
1101 | } | |
1102 | ||
1103 | static __exit void svm_hardware_unsetup(void) | |
1104 | { | |
0da1db75 JR |
1105 | int cpu; |
1106 | ||
3230bb47 | 1107 | for_each_possible_cpu(cpu) |
0da1db75 JR |
1108 | svm_cpu_uninit(cpu); |
1109 | ||
6aa8b732 | 1110 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 1111 | iopm_base = 0; |
6aa8b732 AK |
1112 | } |
1113 | ||
1114 | static void init_seg(struct vmcb_seg *seg) | |
1115 | { | |
1116 | seg->selector = 0; | |
1117 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 1118 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
1119 | seg->limit = 0xffff; |
1120 | seg->base = 0; | |
1121 | } | |
1122 | ||
1123 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
1124 | { | |
1125 | seg->selector = 0; | |
1126 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
1127 | seg->limit = 0xffff; | |
1128 | seg->base = 0; | |
1129 | } | |
1130 | ||
f4e1b3c8 ZA |
1131 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1132 | { | |
1133 | struct vcpu_svm *svm = to_svm(vcpu); | |
1134 | u64 g_tsc_offset = 0; | |
1135 | ||
2030753d | 1136 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
1137 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1138 | svm->nested.hsave->control.tsc_offset; | |
1139 | svm->nested.hsave->control.tsc_offset = offset; | |
489223ed YY |
1140 | } else |
1141 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1142 | svm->vmcb->control.tsc_offset, | |
1143 | offset); | |
f4e1b3c8 ZA |
1144 | |
1145 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1146 | |
1147 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
1148 | } |
1149 | ||
44a95dae SS |
1150 | static void avic_init_vmcb(struct vcpu_svm *svm) |
1151 | { | |
1152 | struct vmcb *vmcb = svm->vmcb; | |
1153 | struct kvm_arch *vm_data = &svm->vcpu.kvm->arch; | |
1154 | phys_addr_t bpa = page_to_phys(svm->avic_backing_page); | |
1155 | phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page); | |
1156 | phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page); | |
1157 | ||
1158 | vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK; | |
1159 | vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK; | |
1160 | vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK; | |
1161 | vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT; | |
1162 | vmcb->control.int_ctl |= AVIC_ENABLE_MASK; | |
1163 | svm->vcpu.arch.apicv_active = true; | |
1164 | } | |
1165 | ||
5690891b | 1166 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1167 | { |
e6101a96 JR |
1168 | struct vmcb_control_area *control = &svm->vmcb->control; |
1169 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1170 | |
4ee546b4 | 1171 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1172 | |
4ee546b4 RJ |
1173 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1174 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1175 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1176 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1177 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1178 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
3bbf3565 SS |
1179 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
1180 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1181 | |
5315c716 | 1182 | set_dr_intercepts(svm); |
6aa8b732 | 1183 | |
18c918c5 JR |
1184 | set_exception_intercept(svm, PF_VECTOR); |
1185 | set_exception_intercept(svm, UD_VECTOR); | |
1186 | set_exception_intercept(svm, MC_VECTOR); | |
54a20552 | 1187 | set_exception_intercept(svm, AC_VECTOR); |
cbdb967a | 1188 | set_exception_intercept(svm, DB_VECTOR); |
6aa8b732 | 1189 | |
8a05a1b8 JR |
1190 | set_intercept(svm, INTERCEPT_INTR); |
1191 | set_intercept(svm, INTERCEPT_NMI); | |
1192 | set_intercept(svm, INTERCEPT_SMI); | |
1193 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1194 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1195 | set_intercept(svm, INTERCEPT_CPUID); |
1196 | set_intercept(svm, INTERCEPT_INVD); | |
1197 | set_intercept(svm, INTERCEPT_HLT); | |
1198 | set_intercept(svm, INTERCEPT_INVLPG); | |
1199 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1200 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1201 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1202 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1203 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1204 | set_intercept(svm, INTERCEPT_VMRUN); | |
1205 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1206 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1207 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1208 | set_intercept(svm, INTERCEPT_STGI); | |
1209 | set_intercept(svm, INTERCEPT_CLGI); | |
1210 | set_intercept(svm, INTERCEPT_SKINIT); | |
1211 | set_intercept(svm, INTERCEPT_WBINVD); | |
81dd35d4 | 1212 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 | 1213 | |
668fffa3 MT |
1214 | if (!kvm_mwait_in_guest()) { |
1215 | set_intercept(svm, INTERCEPT_MONITOR); | |
1216 | set_intercept(svm, INTERCEPT_MWAIT); | |
1217 | } | |
1218 | ||
6aa8b732 | 1219 | control->iopm_base_pa = iopm_base; |
f65c229c | 1220 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
1221 | control->int_ctl = V_INTR_MASKING_MASK; |
1222 | ||
1223 | init_seg(&save->es); | |
1224 | init_seg(&save->ss); | |
1225 | init_seg(&save->ds); | |
1226 | init_seg(&save->fs); | |
1227 | init_seg(&save->gs); | |
1228 | ||
1229 | save->cs.selector = 0xf000; | |
04b66839 | 1230 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1231 | /* Executable/Readable Code Segment */ |
1232 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1233 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1234 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1235 | |
1236 | save->gdtr.limit = 0xffff; | |
1237 | save->idtr.limit = 0xffff; | |
1238 | ||
1239 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1240 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1241 | ||
5690891b | 1242 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1243 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1244 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1245 | save->rip = 0x0000fff0; |
5fdbf976 | 1246 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1247 | |
e0231715 | 1248 | /* |
18fa000a | 1249 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
d28bc9dd | 1250 | * It also updates the guest-visible cr0 value. |
6aa8b732 | 1251 | */ |
79a8059d | 1252 | svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); |
ebae871a | 1253 | kvm_mmu_reset_context(&svm->vcpu); |
18fa000a | 1254 | |
66aee91a | 1255 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1256 | /* rdx = ?? */ |
709ddebf JR |
1257 | |
1258 | if (npt_enabled) { | |
1259 | /* Setup VMCB for Nested Paging */ | |
1260 | control->nested_ctl = 1; | |
8a05a1b8 | 1261 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1262 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1263 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1264 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
74545705 | 1265 | save->g_pat = svm->vcpu.arch.pat; |
709ddebf JR |
1266 | save->cr3 = 0; |
1267 | save->cr4 = 0; | |
1268 | } | |
f40f6a45 | 1269 | svm->asid_generation = 0; |
1371d904 | 1270 | |
e6aa9abd | 1271 | svm->nested.vmcb = 0; |
2af9194d JR |
1272 | svm->vcpu.arch.hflags = 0; |
1273 | ||
2a6b20b8 | 1274 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1275 | control->pause_filter_count = 3000; |
8a05a1b8 | 1276 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1277 | } |
1278 | ||
44a95dae SS |
1279 | if (avic) |
1280 | avic_init_vmcb(svm); | |
1281 | ||
8d28fec4 RJ |
1282 | mark_all_dirty(svm->vmcb); |
1283 | ||
2af9194d | 1284 | enable_gif(svm); |
44a95dae SS |
1285 | |
1286 | } | |
1287 | ||
d3e7dec0 DC |
1288 | static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, |
1289 | unsigned int index) | |
44a95dae SS |
1290 | { |
1291 | u64 *avic_physical_id_table; | |
1292 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
1293 | ||
1294 | if (index >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1295 | return NULL; | |
1296 | ||
1297 | avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page); | |
1298 | ||
1299 | return &avic_physical_id_table[index]; | |
1300 | } | |
1301 | ||
1302 | /** | |
1303 | * Note: | |
1304 | * AVIC hardware walks the nested page table to check permissions, | |
1305 | * but does not use the SPA address specified in the leaf page | |
1306 | * table entry since it uses address in the AVIC_BACKING_PAGE pointer | |
1307 | * field of the VMCB. Therefore, we set up the | |
1308 | * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here. | |
1309 | */ | |
1310 | static int avic_init_access_page(struct kvm_vcpu *vcpu) | |
1311 | { | |
1312 | struct kvm *kvm = vcpu->kvm; | |
1313 | int ret; | |
1314 | ||
1315 | if (kvm->arch.apic_access_page_done) | |
1316 | return 0; | |
1317 | ||
1318 | ret = x86_set_memory_region(kvm, | |
1319 | APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
1320 | APIC_DEFAULT_PHYS_BASE, | |
1321 | PAGE_SIZE); | |
1322 | if (ret) | |
1323 | return ret; | |
1324 | ||
1325 | kvm->arch.apic_access_page_done = true; | |
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | static int avic_init_backing_page(struct kvm_vcpu *vcpu) | |
1330 | { | |
1331 | int ret; | |
1332 | u64 *entry, new_entry; | |
1333 | int id = vcpu->vcpu_id; | |
1334 | struct vcpu_svm *svm = to_svm(vcpu); | |
1335 | ||
1336 | ret = avic_init_access_page(vcpu); | |
1337 | if (ret) | |
1338 | return ret; | |
1339 | ||
1340 | if (id >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1341 | return -EINVAL; | |
1342 | ||
1343 | if (!svm->vcpu.arch.apic->regs) | |
1344 | return -EINVAL; | |
1345 | ||
1346 | svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs); | |
1347 | ||
1348 | /* Setting AVIC backing page address in the phy APIC ID table */ | |
1349 | entry = avic_get_physical_id_entry(vcpu, id); | |
1350 | if (!entry) | |
1351 | return -EINVAL; | |
1352 | ||
1353 | new_entry = READ_ONCE(*entry); | |
1354 | new_entry = (page_to_phys(svm->avic_backing_page) & | |
1355 | AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) | | |
1356 | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; | |
1357 | WRITE_ONCE(*entry, new_entry); | |
1358 | ||
1359 | svm->avic_physical_id_cache = entry; | |
1360 | ||
1361 | return 0; | |
1362 | } | |
1363 | ||
5ea11f2b SS |
1364 | static inline int avic_get_next_vm_id(void) |
1365 | { | |
1366 | int id; | |
1367 | ||
1368 | spin_lock(&avic_vm_id_lock); | |
1369 | ||
1370 | /* AVIC VM ID is one-based. */ | |
1371 | id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1); | |
1372 | if (id <= AVIC_VM_ID_MASK) | |
1373 | __set_bit(id, avic_vm_id_bitmap); | |
1374 | else | |
1375 | id = -EAGAIN; | |
1376 | ||
1377 | spin_unlock(&avic_vm_id_lock); | |
1378 | return id; | |
1379 | } | |
1380 | ||
1381 | static inline int avic_free_vm_id(int id) | |
1382 | { | |
1383 | if (id <= 0 || id > AVIC_VM_ID_MASK) | |
1384 | return -EINVAL; | |
1385 | ||
1386 | spin_lock(&avic_vm_id_lock); | |
1387 | __clear_bit(id, avic_vm_id_bitmap); | |
1388 | spin_unlock(&avic_vm_id_lock); | |
1389 | return 0; | |
1390 | } | |
1391 | ||
44a95dae SS |
1392 | static void avic_vm_destroy(struct kvm *kvm) |
1393 | { | |
5881f737 | 1394 | unsigned long flags; |
44a95dae SS |
1395 | struct kvm_arch *vm_data = &kvm->arch; |
1396 | ||
3863dff0 DV |
1397 | if (!avic) |
1398 | return; | |
1399 | ||
5ea11f2b SS |
1400 | avic_free_vm_id(vm_data->avic_vm_id); |
1401 | ||
44a95dae SS |
1402 | if (vm_data->avic_logical_id_table_page) |
1403 | __free_page(vm_data->avic_logical_id_table_page); | |
1404 | if (vm_data->avic_physical_id_table_page) | |
1405 | __free_page(vm_data->avic_physical_id_table_page); | |
5881f737 SS |
1406 | |
1407 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
1408 | hash_del(&vm_data->hnode); | |
1409 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
44a95dae SS |
1410 | } |
1411 | ||
1412 | static int avic_vm_init(struct kvm *kvm) | |
1413 | { | |
5881f737 | 1414 | unsigned long flags; |
adad0d02 | 1415 | int vm_id, err = -ENOMEM; |
44a95dae SS |
1416 | struct kvm_arch *vm_data = &kvm->arch; |
1417 | struct page *p_page; | |
1418 | struct page *l_page; | |
1419 | ||
1420 | if (!avic) | |
1421 | return 0; | |
1422 | ||
adad0d02 CIK |
1423 | vm_id = avic_get_next_vm_id(); |
1424 | if (vm_id < 0) | |
1425 | return vm_id; | |
1426 | vm_data->avic_vm_id = (u32)vm_id; | |
5ea11f2b | 1427 | |
44a95dae SS |
1428 | /* Allocating physical APIC ID table (4KB) */ |
1429 | p_page = alloc_page(GFP_KERNEL); | |
1430 | if (!p_page) | |
1431 | goto free_avic; | |
1432 | ||
1433 | vm_data->avic_physical_id_table_page = p_page; | |
1434 | clear_page(page_address(p_page)); | |
1435 | ||
1436 | /* Allocating logical APIC ID table (4KB) */ | |
1437 | l_page = alloc_page(GFP_KERNEL); | |
1438 | if (!l_page) | |
1439 | goto free_avic; | |
1440 | ||
1441 | vm_data->avic_logical_id_table_page = l_page; | |
1442 | clear_page(page_address(l_page)); | |
1443 | ||
5881f737 SS |
1444 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); |
1445 | hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id); | |
1446 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
1447 | ||
44a95dae SS |
1448 | return 0; |
1449 | ||
1450 | free_avic: | |
1451 | avic_vm_destroy(kvm); | |
1452 | return err; | |
6aa8b732 AK |
1453 | } |
1454 | ||
411b44ba SS |
1455 | static inline int |
1456 | avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r) | |
8221c137 | 1457 | { |
411b44ba SS |
1458 | int ret = 0; |
1459 | unsigned long flags; | |
1460 | struct amd_svm_iommu_ir *ir; | |
8221c137 SS |
1461 | struct vcpu_svm *svm = to_svm(vcpu); |
1462 | ||
411b44ba SS |
1463 | if (!kvm_arch_has_assigned_device(vcpu->kvm)) |
1464 | return 0; | |
8221c137 | 1465 | |
411b44ba SS |
1466 | /* |
1467 | * Here, we go through the per-vcpu ir_list to update all existing | |
1468 | * interrupt remapping table entry targeting this vcpu. | |
1469 | */ | |
1470 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
8221c137 | 1471 | |
411b44ba SS |
1472 | if (list_empty(&svm->ir_list)) |
1473 | goto out; | |
8221c137 | 1474 | |
411b44ba SS |
1475 | list_for_each_entry(ir, &svm->ir_list, node) { |
1476 | ret = amd_iommu_update_ga(cpu, r, ir->data); | |
1477 | if (ret) | |
1478 | break; | |
1479 | } | |
1480 | out: | |
1481 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
1482 | return ret; | |
8221c137 SS |
1483 | } |
1484 | ||
1485 | static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
1486 | { | |
1487 | u64 entry; | |
1488 | /* ID = 0xff (broadcast), ID > 0xff (reserved) */ | |
7d669f50 | 1489 | int h_physical_id = kvm_cpu_get_apicid(cpu); |
8221c137 SS |
1490 | struct vcpu_svm *svm = to_svm(vcpu); |
1491 | ||
1492 | if (!kvm_vcpu_apicv_active(vcpu)) | |
1493 | return; | |
1494 | ||
1495 | if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT)) | |
1496 | return; | |
1497 | ||
1498 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
1499 | WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
1500 | ||
1501 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; | |
1502 | entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); | |
1503 | ||
1504 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
1505 | if (svm->avic_is_running) | |
1506 | entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
1507 | ||
1508 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
411b44ba SS |
1509 | avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, |
1510 | svm->avic_is_running); | |
8221c137 SS |
1511 | } |
1512 | ||
1513 | static void avic_vcpu_put(struct kvm_vcpu *vcpu) | |
1514 | { | |
1515 | u64 entry; | |
1516 | struct vcpu_svm *svm = to_svm(vcpu); | |
1517 | ||
1518 | if (!kvm_vcpu_apicv_active(vcpu)) | |
1519 | return; | |
1520 | ||
1521 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
411b44ba SS |
1522 | if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) |
1523 | avic_update_iommu_vcpu_affinity(vcpu, -1, 0); | |
1524 | ||
8221c137 SS |
1525 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; |
1526 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
6aa8b732 AK |
1527 | } |
1528 | ||
411b44ba SS |
1529 | /** |
1530 | * This function is called during VCPU halt/unhalt. | |
1531 | */ | |
1532 | static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run) | |
1533 | { | |
1534 | struct vcpu_svm *svm = to_svm(vcpu); | |
1535 | ||
1536 | svm->avic_is_running = is_run; | |
1537 | if (is_run) | |
1538 | avic_vcpu_load(vcpu, vcpu->cpu); | |
1539 | else | |
1540 | avic_vcpu_put(vcpu); | |
1541 | } | |
1542 | ||
d28bc9dd | 1543 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
04d2cc77 AK |
1544 | { |
1545 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
1546 | u32 dummy; |
1547 | u32 eax = 1; | |
04d2cc77 | 1548 | |
d28bc9dd NA |
1549 | if (!init_event) { |
1550 | svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE | | |
1551 | MSR_IA32_APICBASE_ENABLE; | |
1552 | if (kvm_vcpu_is_reset_bsp(&svm->vcpu)) | |
1553 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; | |
1554 | } | |
5690891b | 1555 | init_vmcb(svm); |
70433389 | 1556 | |
66f7b72e JS |
1557 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy); |
1558 | kvm_register_write(vcpu, VCPU_REGS_RDX, eax); | |
44a95dae SS |
1559 | |
1560 | if (kvm_vcpu_apicv_active(vcpu) && !init_event) | |
1561 | avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE); | |
04d2cc77 AK |
1562 | } |
1563 | ||
fb3f0f51 | 1564 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1565 | { |
a2fa3e9f | 1566 | struct vcpu_svm *svm; |
6aa8b732 | 1567 | struct page *page; |
f65c229c | 1568 | struct page *msrpm_pages; |
b286d5d8 | 1569 | struct page *hsave_page; |
3d6368ef | 1570 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1571 | int err; |
6aa8b732 | 1572 | |
c16f862d | 1573 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1574 | if (!svm) { |
1575 | err = -ENOMEM; | |
1576 | goto out; | |
1577 | } | |
1578 | ||
1579 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
1580 | if (err) | |
1581 | goto free_svm; | |
1582 | ||
b7af4043 | 1583 | err = -ENOMEM; |
6aa8b732 | 1584 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1585 | if (!page) |
fb3f0f51 | 1586 | goto uninit; |
6aa8b732 | 1587 | |
f65c229c JR |
1588 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1589 | if (!msrpm_pages) | |
b7af4043 | 1590 | goto free_page1; |
3d6368ef AG |
1591 | |
1592 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1593 | if (!nested_msrpm_pages) | |
b7af4043 | 1594 | goto free_page2; |
f65c229c | 1595 | |
b286d5d8 AG |
1596 | hsave_page = alloc_page(GFP_KERNEL); |
1597 | if (!hsave_page) | |
b7af4043 TY |
1598 | goto free_page3; |
1599 | ||
44a95dae SS |
1600 | if (avic) { |
1601 | err = avic_init_backing_page(&svm->vcpu); | |
1602 | if (err) | |
1603 | goto free_page4; | |
411b44ba SS |
1604 | |
1605 | INIT_LIST_HEAD(&svm->ir_list); | |
1606 | spin_lock_init(&svm->ir_list_lock); | |
44a95dae SS |
1607 | } |
1608 | ||
8221c137 SS |
1609 | /* We initialize this flag to true to make sure that the is_running |
1610 | * bit would be set the first time the vcpu is loaded. | |
1611 | */ | |
1612 | svm->avic_is_running = true; | |
1613 | ||
e6aa9abd | 1614 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1615 | |
b7af4043 TY |
1616 | svm->msrpm = page_address(msrpm_pages); |
1617 | svm_vcpu_init_msrpm(svm->msrpm); | |
1618 | ||
e6aa9abd | 1619 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1620 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1621 | |
a2fa3e9f GH |
1622 | svm->vmcb = page_address(page); |
1623 | clear_page(svm->vmcb); | |
1624 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1625 | svm->asid_generation = 0; | |
5690891b | 1626 | init_vmcb(svm); |
6aa8b732 | 1627 | |
2b036c6b BO |
1628 | svm_init_osvw(&svm->vcpu); |
1629 | ||
fb3f0f51 | 1630 | return &svm->vcpu; |
36241b8c | 1631 | |
44a95dae SS |
1632 | free_page4: |
1633 | __free_page(hsave_page); | |
b7af4043 TY |
1634 | free_page3: |
1635 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1636 | free_page2: | |
1637 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1638 | free_page1: | |
1639 | __free_page(page); | |
fb3f0f51 RR |
1640 | uninit: |
1641 | kvm_vcpu_uninit(&svm->vcpu); | |
1642 | free_svm: | |
a4770347 | 1643 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1644 | out: |
1645 | return ERR_PTR(err); | |
6aa8b732 AK |
1646 | } |
1647 | ||
1648 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1649 | { | |
a2fa3e9f GH |
1650 | struct vcpu_svm *svm = to_svm(vcpu); |
1651 | ||
fb3f0f51 | 1652 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1653 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1654 | __free_page(virt_to_page(svm->nested.hsave)); |
1655 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1656 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1657 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1658 | } |
1659 | ||
15ad7146 | 1660 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1661 | { |
a2fa3e9f | 1662 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1663 | int i; |
0cc5064d | 1664 | |
0cc5064d | 1665 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1666 | svm->asid_generation = 0; |
8d28fec4 | 1667 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1668 | } |
94dfbdb3 | 1669 | |
82ca2d10 AK |
1670 | #ifdef CONFIG_X86_64 |
1671 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1672 | #endif | |
dacccfdd AK |
1673 | savesegment(fs, svm->host.fs); |
1674 | savesegment(gs, svm->host.gs); | |
1675 | svm->host.ldt = kvm_read_ldt(); | |
1676 | ||
94dfbdb3 | 1677 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1678 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 | 1679 | |
ad721883 HZ |
1680 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
1681 | u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio; | |
1682 | if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) { | |
1683 | __this_cpu_write(current_tsc_ratio, tsc_ratio); | |
1684 | wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio); | |
1685 | } | |
fbc0db76 | 1686 | } |
46896c73 PB |
1687 | /* This assumes that the kernel never uses MSR_TSC_AUX */ |
1688 | if (static_cpu_has(X86_FEATURE_RDTSCP)) | |
1689 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
8221c137 SS |
1690 | |
1691 | avic_vcpu_load(vcpu, cpu); | |
6aa8b732 AK |
1692 | } |
1693 | ||
1694 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1695 | { | |
a2fa3e9f | 1696 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1697 | int i; |
1698 | ||
8221c137 SS |
1699 | avic_vcpu_put(vcpu); |
1700 | ||
e1beb1d3 | 1701 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1702 | kvm_load_ldt(svm->host.ldt); |
1703 | #ifdef CONFIG_X86_64 | |
1704 | loadsegment(fs, svm->host.fs); | |
296f781a | 1705 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase); |
893a5ab6 | 1706 | load_gs_index(svm->host.gs); |
dacccfdd | 1707 | #else |
831ca609 | 1708 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1709 | loadsegment(gs, svm->host.gs); |
831ca609 | 1710 | #endif |
dacccfdd | 1711 | #endif |
94dfbdb3 | 1712 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1713 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1714 | } |
1715 | ||
8221c137 SS |
1716 | static void svm_vcpu_blocking(struct kvm_vcpu *vcpu) |
1717 | { | |
1718 | avic_set_running(vcpu, false); | |
1719 | } | |
1720 | ||
1721 | static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
1722 | { | |
1723 | avic_set_running(vcpu, true); | |
1724 | } | |
1725 | ||
6aa8b732 AK |
1726 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1727 | { | |
9b611747 LP |
1728 | struct vcpu_svm *svm = to_svm(vcpu); |
1729 | unsigned long rflags = svm->vmcb->save.rflags; | |
1730 | ||
1731 | if (svm->nmi_singlestep) { | |
1732 | /* Hide our flags if they were not set by the guest */ | |
1733 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
1734 | rflags &= ~X86_EFLAGS_TF; | |
1735 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
1736 | rflags &= ~X86_EFLAGS_RF; | |
1737 | } | |
1738 | return rflags; | |
6aa8b732 AK |
1739 | } |
1740 | ||
1741 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1742 | { | |
9b611747 LP |
1743 | if (to_svm(vcpu)->nmi_singlestep) |
1744 | rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1745 | ||
ae9fedc7 | 1746 | /* |
bb3541f1 | 1747 | * Any change of EFLAGS.VM is accompanied by a reload of SS |
ae9fedc7 PB |
1748 | * (caused by either a task switch or an inter-privilege IRET), |
1749 | * so we do not need to update the CPL here. | |
1750 | */ | |
a2fa3e9f | 1751 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1752 | } |
1753 | ||
be94f6b7 HH |
1754 | static u32 svm_get_pkru(struct kvm_vcpu *vcpu) |
1755 | { | |
1756 | return 0; | |
1757 | } | |
1758 | ||
6de4f3ad AK |
1759 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1760 | { | |
1761 | switch (reg) { | |
1762 | case VCPU_EXREG_PDPTR: | |
1763 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1764 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1765 | break; |
1766 | default: | |
1767 | BUG(); | |
1768 | } | |
1769 | } | |
1770 | ||
f0b85051 AG |
1771 | static void svm_set_vintr(struct vcpu_svm *svm) |
1772 | { | |
8a05a1b8 | 1773 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1774 | } |
1775 | ||
1776 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1777 | { | |
8a05a1b8 | 1778 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1779 | } |
1780 | ||
6aa8b732 AK |
1781 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1782 | { | |
a2fa3e9f | 1783 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1784 | |
1785 | switch (seg) { | |
1786 | case VCPU_SREG_CS: return &save->cs; | |
1787 | case VCPU_SREG_DS: return &save->ds; | |
1788 | case VCPU_SREG_ES: return &save->es; | |
1789 | case VCPU_SREG_FS: return &save->fs; | |
1790 | case VCPU_SREG_GS: return &save->gs; | |
1791 | case VCPU_SREG_SS: return &save->ss; | |
1792 | case VCPU_SREG_TR: return &save->tr; | |
1793 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1794 | } | |
1795 | BUG(); | |
8b6d44c7 | 1796 | return NULL; |
6aa8b732 AK |
1797 | } |
1798 | ||
1799 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1800 | { | |
1801 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1802 | ||
1803 | return s->base; | |
1804 | } | |
1805 | ||
1806 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1807 | struct kvm_segment *var, int seg) | |
1808 | { | |
1809 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1810 | ||
1811 | var->base = s->base; | |
1812 | var->limit = s->limit; | |
1813 | var->selector = s->selector; | |
1814 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1815 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1816 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1817 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1818 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1819 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1820 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
80112c89 JM |
1821 | |
1822 | /* | |
1823 | * AMD CPUs circa 2014 track the G bit for all segments except CS. | |
1824 | * However, the SVM spec states that the G bit is not observed by the | |
1825 | * CPU, and some VMware virtual CPUs drop the G bit for all segments. | |
1826 | * So let's synthesize a legal G bit for all segments, this helps | |
1827 | * running KVM nested. It also helps cross-vendor migration, because | |
1828 | * Intel's vmentry has a check on the 'G' bit. | |
1829 | */ | |
1830 | var->g = s->limit > 0xfffff; | |
25022acc | 1831 | |
e0231715 JR |
1832 | /* |
1833 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1834 | * for cross vendor migration purposes by "not present" |
1835 | */ | |
8eae9570 | 1836 | var->unusable = !var->present; |
19bca6ab | 1837 | |
1fbdc7a5 | 1838 | switch (seg) { |
1fbdc7a5 AP |
1839 | case VCPU_SREG_TR: |
1840 | /* | |
1841 | * Work around a bug where the busy flag in the tr selector | |
1842 | * isn't exposed | |
1843 | */ | |
c0d09828 | 1844 | var->type |= 0x2; |
1fbdc7a5 AP |
1845 | break; |
1846 | case VCPU_SREG_DS: | |
1847 | case VCPU_SREG_ES: | |
1848 | case VCPU_SREG_FS: | |
1849 | case VCPU_SREG_GS: | |
1850 | /* | |
1851 | * The accessed bit must always be set in the segment | |
1852 | * descriptor cache, although it can be cleared in the | |
1853 | * descriptor, the cached bit always remains at 1. Since | |
1854 | * Intel has a check on this, set it here to support | |
1855 | * cross-vendor migration. | |
1856 | */ | |
1857 | if (!var->unusable) | |
1858 | var->type |= 0x1; | |
1859 | break; | |
b586eb02 | 1860 | case VCPU_SREG_SS: |
e0231715 JR |
1861 | /* |
1862 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1863 | * descriptor is left as 1, although the whole segment has |
1864 | * been made unusable. Clear it here to pass an Intel VMX | |
1865 | * entry check when cross vendor migrating. | |
1866 | */ | |
1867 | if (var->unusable) | |
1868 | var->db = 0; | |
d9c1b543 | 1869 | /* This is symmetric with svm_set_segment() */ |
33b458d2 | 1870 | var->dpl = to_svm(vcpu)->vmcb->save.cpl; |
b586eb02 | 1871 | break; |
1fbdc7a5 | 1872 | } |
6aa8b732 AK |
1873 | } |
1874 | ||
2e4d2653 IE |
1875 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1876 | { | |
1877 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1878 | ||
1879 | return save->cpl; | |
1880 | } | |
1881 | ||
89a27f4d | 1882 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1883 | { |
a2fa3e9f GH |
1884 | struct vcpu_svm *svm = to_svm(vcpu); |
1885 | ||
89a27f4d GN |
1886 | dt->size = svm->vmcb->save.idtr.limit; |
1887 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1888 | } |
1889 | ||
89a27f4d | 1890 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1891 | { |
a2fa3e9f GH |
1892 | struct vcpu_svm *svm = to_svm(vcpu); |
1893 | ||
89a27f4d GN |
1894 | svm->vmcb->save.idtr.limit = dt->size; |
1895 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1896 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1897 | } |
1898 | ||
89a27f4d | 1899 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1900 | { |
a2fa3e9f GH |
1901 | struct vcpu_svm *svm = to_svm(vcpu); |
1902 | ||
89a27f4d GN |
1903 | dt->size = svm->vmcb->save.gdtr.limit; |
1904 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1905 | } |
1906 | ||
89a27f4d | 1907 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1908 | { |
a2fa3e9f GH |
1909 | struct vcpu_svm *svm = to_svm(vcpu); |
1910 | ||
89a27f4d GN |
1911 | svm->vmcb->save.gdtr.limit = dt->size; |
1912 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1913 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1914 | } |
1915 | ||
e8467fda AK |
1916 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1917 | { | |
1918 | } | |
1919 | ||
aff48baa AK |
1920 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1921 | { | |
1922 | } | |
1923 | ||
25c4c276 | 1924 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1925 | { |
1926 | } | |
1927 | ||
d225157b AK |
1928 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1929 | { | |
1930 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1931 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1932 | ||
bd7e5b08 PB |
1933 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) |
1934 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
d225157b | 1935 | |
dcca1a65 | 1936 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1937 | |
bd7e5b08 | 1938 | if (gcr0 == *hcr0) { |
4ee546b4 RJ |
1939 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1940 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1941 | } else { |
4ee546b4 RJ |
1942 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1943 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1944 | } |
1945 | } | |
1946 | ||
6aa8b732 AK |
1947 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1948 | { | |
a2fa3e9f GH |
1949 | struct vcpu_svm *svm = to_svm(vcpu); |
1950 | ||
05b3e0c2 | 1951 | #ifdef CONFIG_X86_64 |
f6801dff | 1952 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1953 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1954 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1955 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1956 | } |
1957 | ||
d77c26fc | 1958 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1959 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1960 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1961 | } |
1962 | } | |
1963 | #endif | |
ad312c7c | 1964 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1965 | |
1966 | if (!npt_enabled) | |
1967 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 | 1968 | |
bcf166a9 PB |
1969 | /* |
1970 | * re-enable caching here because the QEMU bios | |
1971 | * does not do it - this results in some delay at | |
1972 | * reboot | |
1973 | */ | |
1974 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
1975 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1976 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1977 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1978 | update_cr0_intercept(svm); |
6aa8b732 AK |
1979 | } |
1980 | ||
5e1746d6 | 1981 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 1982 | { |
1e02ce4c | 1983 | unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE; |
e5eab0ce JR |
1984 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1985 | ||
5e1746d6 NHE |
1986 | if (cr4 & X86_CR4_VMXE) |
1987 | return 1; | |
1988 | ||
e5eab0ce | 1989 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 1990 | svm_flush_tlb(vcpu); |
6394b649 | 1991 | |
ec077263 JR |
1992 | vcpu->arch.cr4 = cr4; |
1993 | if (!npt_enabled) | |
1994 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1995 | cr4 |= host_cr4_mce; |
ec077263 | 1996 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1997 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 1998 | return 0; |
6aa8b732 AK |
1999 | } |
2000 | ||
2001 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
2002 | struct kvm_segment *var, int seg) | |
2003 | { | |
a2fa3e9f | 2004 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
2005 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
2006 | ||
2007 | s->base = var->base; | |
2008 | s->limit = var->limit; | |
2009 | s->selector = var->selector; | |
d9c1b543 RP |
2010 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); |
2011 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
2012 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
2013 | s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT; | |
2014 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
2015 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
2016 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
2017 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
ae9fedc7 PB |
2018 | |
2019 | /* | |
2020 | * This is always accurate, except if SYSRET returned to a segment | |
2021 | * with SS.DPL != 3. Intel does not have this quirk, and always | |
2022 | * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it | |
2023 | * would entail passing the CPL to userspace and back. | |
2024 | */ | |
2025 | if (seg == VCPU_SREG_SS) | |
d9c1b543 RP |
2026 | /* This is symmetric with svm_get_segment() */ |
2027 | svm->vmcb->save.cpl = (var->dpl & 3); | |
6aa8b732 | 2028 | |
060d0c9a | 2029 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
2030 | } |
2031 | ||
cbdb967a | 2032 | static void update_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 2033 | { |
d0bfb940 JK |
2034 | struct vcpu_svm *svm = to_svm(vcpu); |
2035 | ||
18c918c5 | 2036 | clr_exception_intercept(svm, BP_VECTOR); |
44c11430 | 2037 | |
d0bfb940 | 2038 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
d0bfb940 | 2039 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 2040 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
2041 | } else |
2042 | vcpu->guest_debug = 0; | |
44c11430 GN |
2043 | } |
2044 | ||
0fe1e009 | 2045 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 2046 | { |
0fe1e009 TH |
2047 | if (sd->next_asid > sd->max_asid) { |
2048 | ++sd->asid_generation; | |
2049 | sd->next_asid = 1; | |
a2fa3e9f | 2050 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
2051 | } |
2052 | ||
0fe1e009 TH |
2053 | svm->asid_generation = sd->asid_generation; |
2054 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
2055 | |
2056 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
2057 | } |
2058 | ||
73aaf249 JK |
2059 | static u64 svm_get_dr6(struct kvm_vcpu *vcpu) |
2060 | { | |
2061 | return to_svm(vcpu)->vmcb->save.dr6; | |
2062 | } | |
2063 | ||
2064 | static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value) | |
2065 | { | |
2066 | struct vcpu_svm *svm = to_svm(vcpu); | |
2067 | ||
2068 | svm->vmcb->save.dr6 = value; | |
2069 | mark_dirty(svm->vmcb, VMCB_DR); | |
2070 | } | |
2071 | ||
facb0139 PB |
2072 | static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
2073 | { | |
2074 | struct vcpu_svm *svm = to_svm(vcpu); | |
2075 | ||
2076 | get_debugreg(vcpu->arch.db[0], 0); | |
2077 | get_debugreg(vcpu->arch.db[1], 1); | |
2078 | get_debugreg(vcpu->arch.db[2], 2); | |
2079 | get_debugreg(vcpu->arch.db[3], 3); | |
2080 | vcpu->arch.dr6 = svm_get_dr6(vcpu); | |
2081 | vcpu->arch.dr7 = svm->vmcb->save.dr7; | |
2082 | ||
2083 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
2084 | set_dr_intercepts(svm); | |
2085 | } | |
2086 | ||
020df079 | 2087 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 2088 | { |
42dbaa5a | 2089 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 2090 | |
020df079 | 2091 | svm->vmcb->save.dr7 = value; |
72214b96 | 2092 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
2093 | } |
2094 | ||
851ba692 | 2095 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 2096 | { |
631bc487 | 2097 | u64 fault_address = svm->vmcb->control.exit_info_2; |
14727754 | 2098 | u64 error_code; |
631bc487 | 2099 | int r = 1; |
6aa8b732 | 2100 | |
631bc487 GN |
2101 | switch (svm->apf_reason) { |
2102 | default: | |
2103 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 2104 | |
631bc487 GN |
2105 | trace_kvm_page_fault(fault_address, error_code); |
2106 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
2107 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
2108 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
2109 | svm->vmcb->control.insn_bytes, | |
2110 | svm->vmcb->control.insn_len); | |
631bc487 GN |
2111 | break; |
2112 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
2113 | svm->apf_reason = 0; | |
2114 | local_irq_disable(); | |
2115 | kvm_async_pf_task_wait(fault_address); | |
2116 | local_irq_enable(); | |
2117 | break; | |
2118 | case KVM_PV_REASON_PAGE_READY: | |
2119 | svm->apf_reason = 0; | |
2120 | local_irq_disable(); | |
2121 | kvm_async_pf_task_wake(fault_address); | |
2122 | local_irq_enable(); | |
2123 | break; | |
2124 | } | |
2125 | return r; | |
6aa8b732 AK |
2126 | } |
2127 | ||
851ba692 | 2128 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 2129 | { |
851ba692 AK |
2130 | struct kvm_run *kvm_run = svm->vcpu.run; |
2131 | ||
d0bfb940 | 2132 | if (!(svm->vcpu.guest_debug & |
44c11430 | 2133 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 2134 | !svm->nmi_singlestep) { |
d0bfb940 JK |
2135 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
2136 | return 1; | |
2137 | } | |
44c11430 | 2138 | |
6be7d306 | 2139 | if (svm->nmi_singlestep) { |
4aebd0e9 | 2140 | disable_nmi_singlestep(svm); |
44c11430 GN |
2141 | } |
2142 | ||
2143 | if (svm->vcpu.guest_debug & | |
e0231715 | 2144 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
2145 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2146 | kvm_run->debug.arch.pc = | |
2147 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2148 | kvm_run->debug.arch.exception = DB_VECTOR; | |
2149 | return 0; | |
2150 | } | |
2151 | ||
2152 | return 1; | |
d0bfb940 JK |
2153 | } |
2154 | ||
851ba692 | 2155 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 2156 | { |
851ba692 AK |
2157 | struct kvm_run *kvm_run = svm->vcpu.run; |
2158 | ||
d0bfb940 JK |
2159 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2160 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2161 | kvm_run->debug.arch.exception = BP_VECTOR; | |
2162 | return 0; | |
2163 | } | |
2164 | ||
851ba692 | 2165 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
2166 | { |
2167 | int er; | |
2168 | ||
51d8b661 | 2169 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 2170 | if (er != EMULATE_DONE) |
7ee5d940 | 2171 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
2172 | return 1; |
2173 | } | |
2174 | ||
54a20552 EN |
2175 | static int ac_interception(struct vcpu_svm *svm) |
2176 | { | |
2177 | kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0); | |
2178 | return 1; | |
2179 | } | |
2180 | ||
67ec6607 JR |
2181 | static bool is_erratum_383(void) |
2182 | { | |
2183 | int err, i; | |
2184 | u64 value; | |
2185 | ||
2186 | if (!erratum_383_found) | |
2187 | return false; | |
2188 | ||
2189 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
2190 | if (err) | |
2191 | return false; | |
2192 | ||
2193 | /* Bit 62 may or may not be set for this mce */ | |
2194 | value &= ~(1ULL << 62); | |
2195 | ||
2196 | if (value != 0xb600000000010015ULL) | |
2197 | return false; | |
2198 | ||
2199 | /* Clear MCi_STATUS registers */ | |
2200 | for (i = 0; i < 6; ++i) | |
2201 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
2202 | ||
2203 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
2204 | if (!err) { | |
2205 | u32 low, high; | |
2206 | ||
2207 | value &= ~(1ULL << 2); | |
2208 | low = lower_32_bits(value); | |
2209 | high = upper_32_bits(value); | |
2210 | ||
2211 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
2212 | } | |
2213 | ||
2214 | /* Flush tlb to evict multi-match entries */ | |
2215 | __flush_tlb_all(); | |
2216 | ||
2217 | return true; | |
2218 | } | |
2219 | ||
fe5913e4 | 2220 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 2221 | { |
67ec6607 JR |
2222 | if (is_erratum_383()) { |
2223 | /* | |
2224 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
2225 | * guest. | |
2226 | */ | |
2227 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
2228 | ||
a8eeb04a | 2229 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
2230 | |
2231 | return; | |
2232 | } | |
2233 | ||
53371b50 JR |
2234 | /* |
2235 | * On an #MC intercept the MCE handler is not called automatically in | |
2236 | * the host. So do it by hand here. | |
2237 | */ | |
2238 | asm volatile ( | |
2239 | "int $0x12\n"); | |
2240 | /* not sure if we ever come back to this point */ | |
2241 | ||
fe5913e4 JR |
2242 | return; |
2243 | } | |
2244 | ||
2245 | static int mc_interception(struct vcpu_svm *svm) | |
2246 | { | |
53371b50 JR |
2247 | return 1; |
2248 | } | |
2249 | ||
851ba692 | 2250 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 2251 | { |
851ba692 AK |
2252 | struct kvm_run *kvm_run = svm->vcpu.run; |
2253 | ||
46fe4ddd JR |
2254 | /* |
2255 | * VMCB is undefined after a SHUTDOWN intercept | |
2256 | * so reinitialize it. | |
2257 | */ | |
a2fa3e9f | 2258 | clear_page(svm->vmcb); |
5690891b | 2259 | init_vmcb(svm); |
46fe4ddd JR |
2260 | |
2261 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2262 | return 0; | |
2263 | } | |
2264 | ||
851ba692 | 2265 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 2266 | { |
cf8f70bf | 2267 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 2268 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 2269 | int size, in, string; |
039576c0 | 2270 | unsigned port; |
6aa8b732 | 2271 | |
e756fc62 | 2272 | ++svm->vcpu.stat.io_exits; |
e70669ab | 2273 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 2274 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
8370c3d0 | 2275 | if (string) |
51d8b661 | 2276 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 2277 | |
039576c0 AK |
2278 | port = io_info >> 16; |
2279 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 2280 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 2281 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf | 2282 | |
8370c3d0 TL |
2283 | return in ? kvm_fast_pio_in(vcpu, size, port) |
2284 | : kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
2285 | } |
2286 | ||
851ba692 | 2287 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
2288 | { |
2289 | return 1; | |
2290 | } | |
2291 | ||
851ba692 | 2292 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
2293 | { |
2294 | ++svm->vcpu.stat.irq_exits; | |
2295 | return 1; | |
2296 | } | |
2297 | ||
851ba692 | 2298 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
2299 | { |
2300 | return 1; | |
2301 | } | |
2302 | ||
851ba692 | 2303 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 2304 | { |
5fdbf976 | 2305 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 | 2306 | return kvm_emulate_halt(&svm->vcpu); |
6aa8b732 AK |
2307 | } |
2308 | ||
851ba692 | 2309 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 2310 | { |
5fdbf976 | 2311 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
0d9c055e | 2312 | return kvm_emulate_hypercall(&svm->vcpu); |
02e235bc AK |
2313 | } |
2314 | ||
5bd2edc3 JR |
2315 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
2316 | { | |
2317 | struct vcpu_svm *svm = to_svm(vcpu); | |
2318 | ||
2319 | return svm->nested.nested_cr3; | |
2320 | } | |
2321 | ||
e4e517b4 AK |
2322 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
2323 | { | |
2324 | struct vcpu_svm *svm = to_svm(vcpu); | |
2325 | u64 cr3 = svm->nested.nested_cr3; | |
2326 | u64 pdpte; | |
2327 | int ret; | |
2328 | ||
54bf36aa PB |
2329 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte, |
2330 | offset_in_page(cr3) + index * 8, 8); | |
e4e517b4 AK |
2331 | if (ret) |
2332 | return 0; | |
2333 | return pdpte; | |
2334 | } | |
2335 | ||
5bd2edc3 JR |
2336 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
2337 | unsigned long root) | |
2338 | { | |
2339 | struct vcpu_svm *svm = to_svm(vcpu); | |
2340 | ||
2341 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 2342 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 2343 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
2344 | } |
2345 | ||
6389ee94 AK |
2346 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
2347 | struct x86_exception *fault) | |
5bd2edc3 JR |
2348 | { |
2349 | struct vcpu_svm *svm = to_svm(vcpu); | |
2350 | ||
5e352519 PB |
2351 | if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) { |
2352 | /* | |
2353 | * TODO: track the cause of the nested page fault, and | |
2354 | * correctly fill in the high bits of exit_info_1. | |
2355 | */ | |
2356 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
2357 | svm->vmcb->control.exit_code_hi = 0; | |
2358 | svm->vmcb->control.exit_info_1 = (1ULL << 32); | |
2359 | svm->vmcb->control.exit_info_2 = fault->address; | |
2360 | } | |
2361 | ||
2362 | svm->vmcb->control.exit_info_1 &= ~0xffffffffULL; | |
2363 | svm->vmcb->control.exit_info_1 |= fault->error_code; | |
2364 | ||
2365 | /* | |
2366 | * The present bit is always zero for page structure faults on real | |
2367 | * hardware. | |
2368 | */ | |
2369 | if (svm->vmcb->control.exit_info_1 & (2ULL << 32)) | |
2370 | svm->vmcb->control.exit_info_1 &= ~1; | |
5bd2edc3 JR |
2371 | |
2372 | nested_svm_vmexit(svm); | |
2373 | } | |
2374 | ||
8a3c1a33 | 2375 | static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
4b16184c | 2376 | { |
ad896af0 PB |
2377 | WARN_ON(mmu_is_nested(vcpu)); |
2378 | kvm_init_shadow_mmu(vcpu); | |
4b16184c JR |
2379 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; |
2380 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 2381 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c JR |
2382 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
2383 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
c258b62b | 2384 | reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu); |
4b16184c | 2385 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; |
4b16184c JR |
2386 | } |
2387 | ||
2388 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
2389 | { | |
2390 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
2391 | } | |
2392 | ||
c0725420 AG |
2393 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
2394 | { | |
e9196ceb DC |
2395 | if (!(svm->vcpu.arch.efer & EFER_SVME) || |
2396 | !is_paging(&svm->vcpu)) { | |
c0725420 AG |
2397 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
2398 | return 1; | |
2399 | } | |
2400 | ||
2401 | if (svm->vmcb->save.cpl) { | |
2402 | kvm_inject_gp(&svm->vcpu, 0); | |
2403 | return 1; | |
2404 | } | |
2405 | ||
e9196ceb | 2406 | return 0; |
c0725420 AG |
2407 | } |
2408 | ||
cf74a78b AG |
2409 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
2410 | bool has_error_code, u32 error_code) | |
2411 | { | |
b8e88bc8 JR |
2412 | int vmexit; |
2413 | ||
2030753d | 2414 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 2415 | return 0; |
cf74a78b | 2416 | |
0295ad7d JR |
2417 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
2418 | svm->vmcb->control.exit_code_hi = 0; | |
2419 | svm->vmcb->control.exit_info_1 = error_code; | |
2420 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
2421 | ||
b8e88bc8 JR |
2422 | vmexit = nested_svm_intercept(svm); |
2423 | if (vmexit == NESTED_EXIT_DONE) | |
2424 | svm->nested.exit_required = true; | |
2425 | ||
2426 | return vmexit; | |
cf74a78b AG |
2427 | } |
2428 | ||
8fe54654 JR |
2429 | /* This function returns true if it is save to enable the irq window */ |
2430 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 2431 | { |
2030753d | 2432 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 2433 | return true; |
cf74a78b | 2434 | |
26666957 | 2435 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 2436 | return true; |
cf74a78b | 2437 | |
26666957 | 2438 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 2439 | return false; |
cf74a78b | 2440 | |
a0a07cd2 GN |
2441 | /* |
2442 | * if vmexit was already requested (by intercepted exception | |
2443 | * for instance) do not overwrite it with "external interrupt" | |
2444 | * vmexit. | |
2445 | */ | |
2446 | if (svm->nested.exit_required) | |
2447 | return false; | |
2448 | ||
197717d5 JR |
2449 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
2450 | svm->vmcb->control.exit_info_1 = 0; | |
2451 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 2452 | |
cd3ff653 JR |
2453 | if (svm->nested.intercept & 1ULL) { |
2454 | /* | |
2455 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 2456 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
2457 | * #vmexit emulation might sleep. Only signal request for |
2458 | * the #vmexit here. | |
2459 | */ | |
2460 | svm->nested.exit_required = true; | |
236649de | 2461 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2462 | return false; |
cf74a78b AG |
2463 | } |
2464 | ||
8fe54654 | 2465 | return true; |
cf74a78b AG |
2466 | } |
2467 | ||
887f500c JR |
2468 | /* This function returns true if it is save to enable the nmi window */ |
2469 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2470 | { | |
2030753d | 2471 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2472 | return true; |
2473 | ||
2474 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2475 | return true; | |
2476 | ||
2477 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2478 | svm->nested.exit_required = true; | |
2479 | ||
2480 | return false; | |
cf74a78b AG |
2481 | } |
2482 | ||
7597f129 | 2483 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2484 | { |
2485 | struct page *page; | |
2486 | ||
6c3bd3d7 JR |
2487 | might_sleep(); |
2488 | ||
54bf36aa | 2489 | page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2490 | if (is_error_page(page)) |
2491 | goto error; | |
2492 | ||
7597f129 JR |
2493 | *_page = page; |
2494 | ||
2495 | return kmap(page); | |
34f80cfa JR |
2496 | |
2497 | error: | |
34f80cfa JR |
2498 | kvm_inject_gp(&svm->vcpu, 0); |
2499 | ||
2500 | return NULL; | |
2501 | } | |
2502 | ||
7597f129 | 2503 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2504 | { |
7597f129 | 2505 | kunmap(page); |
34f80cfa JR |
2506 | kvm_release_page_dirty(page); |
2507 | } | |
34f80cfa | 2508 | |
ce2ac085 JR |
2509 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2510 | { | |
9bf41833 JK |
2511 | unsigned port, size, iopm_len; |
2512 | u16 val, mask; | |
2513 | u8 start_bit; | |
ce2ac085 | 2514 | u64 gpa; |
34f80cfa | 2515 | |
ce2ac085 JR |
2516 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2517 | return NESTED_EXIT_HOST; | |
34f80cfa | 2518 | |
ce2ac085 | 2519 | port = svm->vmcb->control.exit_info_1 >> 16; |
9bf41833 JK |
2520 | size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >> |
2521 | SVM_IOIO_SIZE_SHIFT; | |
ce2ac085 | 2522 | gpa = svm->nested.vmcb_iopm + (port / 8); |
9bf41833 JK |
2523 | start_bit = port % 8; |
2524 | iopm_len = (start_bit + size > 8) ? 2 : 1; | |
2525 | mask = (0xf >> (4 - size)) << start_bit; | |
2526 | val = 0; | |
ce2ac085 | 2527 | |
54bf36aa | 2528 | if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len)) |
9bf41833 | 2529 | return NESTED_EXIT_DONE; |
ce2ac085 | 2530 | |
9bf41833 | 2531 | return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
34f80cfa JR |
2532 | } |
2533 | ||
d2477826 | 2534 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2535 | { |
0d6b3537 JR |
2536 | u32 offset, msr, value; |
2537 | int write, mask; | |
4c2161ae | 2538 | |
3d62d9aa | 2539 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2540 | return NESTED_EXIT_HOST; |
3d62d9aa | 2541 | |
0d6b3537 JR |
2542 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2543 | offset = svm_msrpm_offset(msr); | |
2544 | write = svm->vmcb->control.exit_info_1 & 1; | |
2545 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2546 | |
0d6b3537 JR |
2547 | if (offset == MSR_INVALID) |
2548 | return NESTED_EXIT_DONE; | |
4c2161ae | 2549 | |
0d6b3537 JR |
2550 | /* Offset is in 32 bit units but need in 8 bit units */ |
2551 | offset *= 4; | |
4c2161ae | 2552 | |
54bf36aa | 2553 | if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4)) |
0d6b3537 | 2554 | return NESTED_EXIT_DONE; |
3d62d9aa | 2555 | |
0d6b3537 | 2556 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2557 | } |
2558 | ||
ab2f4d73 LP |
2559 | /* DB exceptions for our internal use must not cause vmexit */ |
2560 | static int nested_svm_intercept_db(struct vcpu_svm *svm) | |
2561 | { | |
2562 | unsigned long dr6; | |
2563 | ||
2564 | /* if we're not singlestepping, it's not ours */ | |
2565 | if (!svm->nmi_singlestep) | |
2566 | return NESTED_EXIT_DONE; | |
2567 | ||
2568 | /* if it's not a singlestep exception, it's not ours */ | |
2569 | if (kvm_get_dr(&svm->vcpu, 6, &dr6)) | |
2570 | return NESTED_EXIT_DONE; | |
2571 | if (!(dr6 & DR6_BS)) | |
2572 | return NESTED_EXIT_DONE; | |
2573 | ||
2574 | /* if the guest is singlestepping, it should get the vmexit */ | |
2575 | if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) { | |
2576 | disable_nmi_singlestep(svm); | |
2577 | return NESTED_EXIT_DONE; | |
2578 | } | |
2579 | ||
2580 | /* it's ours, the nested hypervisor must not see this one */ | |
2581 | return NESTED_EXIT_HOST; | |
2582 | } | |
2583 | ||
410e4d57 | 2584 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2585 | { |
cf74a78b | 2586 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2587 | |
410e4d57 JR |
2588 | switch (exit_code) { |
2589 | case SVM_EXIT_INTR: | |
2590 | case SVM_EXIT_NMI: | |
ff47a49b | 2591 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2592 | return NESTED_EXIT_HOST; |
410e4d57 | 2593 | case SVM_EXIT_NPF: |
e0231715 | 2594 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2595 | if (npt_enabled) |
2596 | return NESTED_EXIT_HOST; | |
2597 | break; | |
410e4d57 | 2598 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
2599 | /* When we're shadowing, trap PFs, but not async PF */ |
2600 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
2601 | return NESTED_EXIT_HOST; |
2602 | break; | |
2603 | default: | |
2604 | break; | |
cf74a78b AG |
2605 | } |
2606 | ||
410e4d57 JR |
2607 | return NESTED_EXIT_CONTINUE; |
2608 | } | |
2609 | ||
2610 | /* | |
2611 | * If this function returns true, this #vmexit was already handled | |
2612 | */ | |
b8e88bc8 | 2613 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2614 | { |
2615 | u32 exit_code = svm->vmcb->control.exit_code; | |
2616 | int vmexit = NESTED_EXIT_HOST; | |
2617 | ||
cf74a78b | 2618 | switch (exit_code) { |
9c4e40b9 | 2619 | case SVM_EXIT_MSR: |
3d62d9aa | 2620 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2621 | break; |
ce2ac085 JR |
2622 | case SVM_EXIT_IOIO: |
2623 | vmexit = nested_svm_intercept_ioio(svm); | |
2624 | break; | |
4ee546b4 RJ |
2625 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2626 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2627 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2628 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2629 | break; |
2630 | } | |
3aed041a JR |
2631 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2632 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2633 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2634 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2635 | break; |
2636 | } | |
2637 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2638 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
ab2f4d73 LP |
2639 | if (svm->nested.intercept_exceptions & excp_bits) { |
2640 | if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR) | |
2641 | vmexit = nested_svm_intercept_db(svm); | |
2642 | else | |
2643 | vmexit = NESTED_EXIT_DONE; | |
2644 | } | |
631bc487 GN |
2645 | /* async page fault always cause vmexit */ |
2646 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
2647 | svm->apf_reason != 0) | |
2648 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2649 | break; |
2650 | } | |
228070b1 JR |
2651 | case SVM_EXIT_ERR: { |
2652 | vmexit = NESTED_EXIT_DONE; | |
2653 | break; | |
2654 | } | |
cf74a78b AG |
2655 | default: { |
2656 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2657 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2658 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2659 | } |
2660 | } | |
2661 | ||
b8e88bc8 JR |
2662 | return vmexit; |
2663 | } | |
2664 | ||
2665 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2666 | { | |
2667 | int vmexit; | |
2668 | ||
2669 | vmexit = nested_svm_intercept(svm); | |
2670 | ||
2671 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2672 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2673 | |
2674 | return vmexit; | |
cf74a78b AG |
2675 | } |
2676 | ||
0460a979 JR |
2677 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2678 | { | |
2679 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2680 | struct vmcb_control_area *from = &from_vmcb->control; | |
2681 | ||
4ee546b4 | 2682 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2683 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2684 | dst->intercept_exceptions = from->intercept_exceptions; |
2685 | dst->intercept = from->intercept; | |
2686 | dst->iopm_base_pa = from->iopm_base_pa; | |
2687 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2688 | dst->tsc_offset = from->tsc_offset; | |
2689 | dst->asid = from->asid; | |
2690 | dst->tlb_ctl = from->tlb_ctl; | |
2691 | dst->int_ctl = from->int_ctl; | |
2692 | dst->int_vector = from->int_vector; | |
2693 | dst->int_state = from->int_state; | |
2694 | dst->exit_code = from->exit_code; | |
2695 | dst->exit_code_hi = from->exit_code_hi; | |
2696 | dst->exit_info_1 = from->exit_info_1; | |
2697 | dst->exit_info_2 = from->exit_info_2; | |
2698 | dst->exit_int_info = from->exit_int_info; | |
2699 | dst->exit_int_info_err = from->exit_int_info_err; | |
2700 | dst->nested_ctl = from->nested_ctl; | |
2701 | dst->event_inj = from->event_inj; | |
2702 | dst->event_inj_err = from->event_inj_err; | |
2703 | dst->nested_cr3 = from->nested_cr3; | |
2704 | dst->lbr_ctl = from->lbr_ctl; | |
2705 | } | |
2706 | ||
34f80cfa | 2707 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2708 | { |
34f80cfa | 2709 | struct vmcb *nested_vmcb; |
e6aa9abd | 2710 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2711 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2712 | struct page *page; |
cf74a78b | 2713 | |
17897f36 JR |
2714 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2715 | vmcb->control.exit_info_1, | |
2716 | vmcb->control.exit_info_2, | |
2717 | vmcb->control.exit_int_info, | |
e097e5ff SH |
2718 | vmcb->control.exit_int_info_err, |
2719 | KVM_ISA_SVM); | |
17897f36 | 2720 | |
7597f129 | 2721 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2722 | if (!nested_vmcb) |
2723 | return 1; | |
2724 | ||
2030753d JR |
2725 | /* Exit Guest-Mode */ |
2726 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2727 | svm->nested.vmcb = 0; |
2728 | ||
cf74a78b | 2729 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2730 | disable_gif(svm); |
2731 | ||
2732 | nested_vmcb->save.es = vmcb->save.es; | |
2733 | nested_vmcb->save.cs = vmcb->save.cs; | |
2734 | nested_vmcb->save.ss = vmcb->save.ss; | |
2735 | nested_vmcb->save.ds = vmcb->save.ds; | |
2736 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2737 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2738 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2739 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2740 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2741 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2742 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2743 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2744 | nested_vmcb->save.rip = vmcb->save.rip; |
2745 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2746 | nested_vmcb->save.rax = vmcb->save.rax; | |
2747 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2748 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2749 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2750 | ||
2751 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2752 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2753 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2754 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2755 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2756 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2757 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2758 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2759 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
6092d3d3 JR |
2760 | |
2761 | if (svm->nrips_enabled) | |
2762 | nested_vmcb->control.next_rip = vmcb->control.next_rip; | |
8d23c466 AG |
2763 | |
2764 | /* | |
2765 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2766 | * to make sure that we do not lose injected events. So check event_inj | |
2767 | * here and copy it to exit_int_info if it is valid. | |
2768 | * Exit_int_info and event_inj can't be both valid because the case | |
2769 | * below only happens on a VMRUN instruction intercept which has | |
2770 | * no valid exit_int_info set. | |
2771 | */ | |
2772 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2773 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2774 | ||
2775 | nc->exit_int_info = vmcb->control.event_inj; | |
2776 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2777 | } | |
2778 | ||
33740e40 JR |
2779 | nested_vmcb->control.tlb_ctl = 0; |
2780 | nested_vmcb->control.event_inj = 0; | |
2781 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2782 | |
2783 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2784 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2785 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2786 | ||
cf74a78b | 2787 | /* Restore the original control entries */ |
0460a979 | 2788 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2789 | |
219b65dc AG |
2790 | kvm_clear_exception_queue(&svm->vcpu); |
2791 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2792 | |
4b16184c JR |
2793 | svm->nested.nested_cr3 = 0; |
2794 | ||
cf74a78b AG |
2795 | /* Restore selected save entries */ |
2796 | svm->vmcb->save.es = hsave->save.es; | |
2797 | svm->vmcb->save.cs = hsave->save.cs; | |
2798 | svm->vmcb->save.ss = hsave->save.ss; | |
2799 | svm->vmcb->save.ds = hsave->save.ds; | |
2800 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2801 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2802 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2803 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2804 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2805 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2806 | if (npt_enabled) { | |
2807 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2808 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2809 | } else { | |
2390218b | 2810 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2811 | } |
2812 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2813 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2814 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2815 | svm->vmcb->save.dr7 = 0; | |
2816 | svm->vmcb->save.cpl = 0; | |
2817 | svm->vmcb->control.exit_int_info = 0; | |
2818 | ||
8d28fec4 RJ |
2819 | mark_all_dirty(svm->vmcb); |
2820 | ||
7597f129 | 2821 | nested_svm_unmap(page); |
cf74a78b | 2822 | |
4b16184c | 2823 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2824 | kvm_mmu_reset_context(&svm->vcpu); |
2825 | kvm_mmu_load(&svm->vcpu); | |
2826 | ||
2827 | return 0; | |
2828 | } | |
3d6368ef | 2829 | |
9738b2c9 | 2830 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2831 | { |
323c3d80 JR |
2832 | /* |
2833 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 2834 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
2835 | * the kvm msr permission bitmap may contain zero bits |
2836 | */ | |
3d6368ef | 2837 | int i; |
9738b2c9 | 2838 | |
323c3d80 JR |
2839 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2840 | return true; | |
9738b2c9 | 2841 | |
323c3d80 JR |
2842 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2843 | u32 value, p; | |
2844 | u64 offset; | |
9738b2c9 | 2845 | |
323c3d80 JR |
2846 | if (msrpm_offsets[i] == 0xffffffff) |
2847 | break; | |
3d6368ef | 2848 | |
0d6b3537 JR |
2849 | p = msrpm_offsets[i]; |
2850 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 | 2851 | |
54bf36aa | 2852 | if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4)) |
323c3d80 JR |
2853 | return false; |
2854 | ||
2855 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2856 | } | |
3d6368ef | 2857 | |
323c3d80 | 2858 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2859 | |
2860 | return true; | |
3d6368ef AG |
2861 | } |
2862 | ||
52c65a30 JR |
2863 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2864 | { | |
2865 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2866 | return false; | |
2867 | ||
dbe77584 JR |
2868 | if (vmcb->control.asid == 0) |
2869 | return false; | |
2870 | ||
4b16184c JR |
2871 | if (vmcb->control.nested_ctl && !npt_enabled) |
2872 | return false; | |
2873 | ||
52c65a30 JR |
2874 | return true; |
2875 | } | |
2876 | ||
9738b2c9 | 2877 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2878 | { |
9738b2c9 | 2879 | struct vmcb *nested_vmcb; |
e6aa9abd | 2880 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2881 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2882 | struct page *page; |
06fc7772 | 2883 | u64 vmcb_gpa; |
3d6368ef | 2884 | |
06fc7772 | 2885 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2886 | |
7597f129 | 2887 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2888 | if (!nested_vmcb) |
2889 | return false; | |
2890 | ||
52c65a30 JR |
2891 | if (!nested_vmcb_checks(nested_vmcb)) { |
2892 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2893 | nested_vmcb->control.exit_code_hi = 0; | |
2894 | nested_vmcb->control.exit_info_1 = 0; | |
2895 | nested_vmcb->control.exit_info_2 = 0; | |
2896 | ||
2897 | nested_svm_unmap(page); | |
2898 | ||
2899 | return false; | |
2900 | } | |
2901 | ||
b75f4eb3 | 2902 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2903 | nested_vmcb->save.rip, |
2904 | nested_vmcb->control.int_ctl, | |
2905 | nested_vmcb->control.event_inj, | |
2906 | nested_vmcb->control.nested_ctl); | |
2907 | ||
4ee546b4 RJ |
2908 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2909 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2910 | nested_vmcb->control.intercept_exceptions, |
2911 | nested_vmcb->control.intercept); | |
2912 | ||
3d6368ef | 2913 | /* Clear internal status */ |
219b65dc AG |
2914 | kvm_clear_exception_queue(&svm->vcpu); |
2915 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2916 | |
e0231715 JR |
2917 | /* |
2918 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2919 | * restore everything when a VMEXIT occurs | |
2920 | */ | |
defbba56 JR |
2921 | hsave->save.es = vmcb->save.es; |
2922 | hsave->save.cs = vmcb->save.cs; | |
2923 | hsave->save.ss = vmcb->save.ss; | |
2924 | hsave->save.ds = vmcb->save.ds; | |
2925 | hsave->save.gdtr = vmcb->save.gdtr; | |
2926 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2927 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2928 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 | 2929 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2930 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); |
b75f4eb3 | 2931 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2932 | hsave->save.rsp = vmcb->save.rsp; |
2933 | hsave->save.rax = vmcb->save.rax; | |
2934 | if (npt_enabled) | |
2935 | hsave->save.cr3 = vmcb->save.cr3; | |
2936 | else | |
9f8fe504 | 2937 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2938 | |
0460a979 | 2939 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef | 2940 | |
f6e78475 | 2941 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2942 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2943 | else | |
2944 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2945 | ||
4b16184c JR |
2946 | if (nested_vmcb->control.nested_ctl) { |
2947 | kvm_mmu_unload(&svm->vcpu); | |
2948 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2949 | nested_svm_init_mmu_context(&svm->vcpu); | |
2950 | } | |
2951 | ||
3d6368ef AG |
2952 | /* Load the nested guest state */ |
2953 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2954 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2955 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2956 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2957 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2958 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2959 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2960 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
2961 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2962 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2963 | if (npt_enabled) { | |
2964 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2965 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2966 | } else |
2390218b | 2967 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2968 | |
2969 | /* Guest paging mode is active - reset mmu */ | |
2970 | kvm_mmu_reset_context(&svm->vcpu); | |
2971 | ||
defbba56 | 2972 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2973 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2974 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2975 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2976 | |
3d6368ef AG |
2977 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2978 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2979 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2980 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2981 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2982 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2983 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2984 | ||
f7138538 | 2985 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2986 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2987 | |
aad42c64 | 2988 | /* cache intercepts */ |
4ee546b4 | 2989 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2990 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2991 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2992 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2993 | ||
f40f6a45 | 2994 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2995 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2996 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2997 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2998 | else | |
2999 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
3000 | ||
88ab24ad JR |
3001 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
3002 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
3003 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
3004 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
3005 | } |
3006 | ||
0d945bd9 | 3007 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 3008 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 3009 | |
88ab24ad | 3010 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
3011 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
3012 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
3013 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
3014 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
3015 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
3016 | ||
7597f129 | 3017 | nested_svm_unmap(page); |
9738b2c9 | 3018 | |
2030753d JR |
3019 | /* Enter Guest-Mode */ |
3020 | enter_guest_mode(&svm->vcpu); | |
3021 | ||
384c6368 JR |
3022 | /* |
3023 | * Merge guest and host intercepts - must be called with vcpu in | |
3024 | * guest-mode to take affect here | |
3025 | */ | |
3026 | recalc_intercepts(svm); | |
3027 | ||
06fc7772 | 3028 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 3029 | |
2af9194d | 3030 | enable_gif(svm); |
3d6368ef | 3031 | |
8d28fec4 RJ |
3032 | mark_all_dirty(svm->vmcb); |
3033 | ||
9738b2c9 | 3034 | return true; |
3d6368ef AG |
3035 | } |
3036 | ||
9966bf68 | 3037 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
3038 | { |
3039 | to_vmcb->save.fs = from_vmcb->save.fs; | |
3040 | to_vmcb->save.gs = from_vmcb->save.gs; | |
3041 | to_vmcb->save.tr = from_vmcb->save.tr; | |
3042 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
3043 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
3044 | to_vmcb->save.star = from_vmcb->save.star; | |
3045 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
3046 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
3047 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
3048 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
3049 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
3050 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
3051 | } |
3052 | ||
851ba692 | 3053 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 3054 | { |
9966bf68 | 3055 | struct vmcb *nested_vmcb; |
7597f129 | 3056 | struct page *page; |
9966bf68 | 3057 | |
5542675b AG |
3058 | if (nested_svm_check_permissions(svm)) |
3059 | return 1; | |
3060 | ||
7597f129 | 3061 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
3062 | if (!nested_vmcb) |
3063 | return 1; | |
3064 | ||
e3e9ed3d JR |
3065 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
3066 | skip_emulated_instruction(&svm->vcpu); | |
3067 | ||
9966bf68 | 3068 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 3069 | nested_svm_unmap(page); |
5542675b AG |
3070 | |
3071 | return 1; | |
3072 | } | |
3073 | ||
851ba692 | 3074 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 3075 | { |
9966bf68 | 3076 | struct vmcb *nested_vmcb; |
7597f129 | 3077 | struct page *page; |
9966bf68 | 3078 | |
5542675b AG |
3079 | if (nested_svm_check_permissions(svm)) |
3080 | return 1; | |
3081 | ||
7597f129 | 3082 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
3083 | if (!nested_vmcb) |
3084 | return 1; | |
3085 | ||
e3e9ed3d JR |
3086 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
3087 | skip_emulated_instruction(&svm->vcpu); | |
3088 | ||
9966bf68 | 3089 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 3090 | nested_svm_unmap(page); |
5542675b AG |
3091 | |
3092 | return 1; | |
3093 | } | |
3094 | ||
851ba692 | 3095 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 3096 | { |
3d6368ef AG |
3097 | if (nested_svm_check_permissions(svm)) |
3098 | return 1; | |
3099 | ||
b75f4eb3 RJ |
3100 | /* Save rip after vmrun instruction */ |
3101 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 3102 | |
9738b2c9 | 3103 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
3104 | return 1; |
3105 | ||
9738b2c9 | 3106 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
3107 | goto failed; |
3108 | ||
3109 | return 1; | |
3110 | ||
3111 | failed: | |
3112 | ||
3113 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
3114 | svm->vmcb->control.exit_code_hi = 0; | |
3115 | svm->vmcb->control.exit_info_1 = 0; | |
3116 | svm->vmcb->control.exit_info_2 = 0; | |
3117 | ||
3118 | nested_svm_vmexit(svm); | |
3d6368ef AG |
3119 | |
3120 | return 1; | |
3121 | } | |
3122 | ||
851ba692 | 3123 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
3124 | { |
3125 | if (nested_svm_check_permissions(svm)) | |
3126 | return 1; | |
3127 | ||
3128 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
3129 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 3130 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 3131 | |
2af9194d | 3132 | enable_gif(svm); |
1371d904 AG |
3133 | |
3134 | return 1; | |
3135 | } | |
3136 | ||
851ba692 | 3137 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
3138 | { |
3139 | if (nested_svm_check_permissions(svm)) | |
3140 | return 1; | |
3141 | ||
3142 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
3143 | skip_emulated_instruction(&svm->vcpu); | |
3144 | ||
2af9194d | 3145 | disable_gif(svm); |
1371d904 AG |
3146 | |
3147 | /* After a CLGI no interrupts should come */ | |
340d3bc3 SS |
3148 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) { |
3149 | svm_clear_vintr(svm); | |
3150 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
3151 | mark_dirty(svm->vmcb, VMCB_INTR); | |
3152 | } | |
decdbf6a | 3153 | |
1371d904 AG |
3154 | return 1; |
3155 | } | |
3156 | ||
851ba692 | 3157 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
3158 | { |
3159 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 3160 | |
668f198f DK |
3161 | trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX), |
3162 | kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); | |
ec1ff790 | 3163 | |
ff092385 | 3164 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
668f198f | 3165 | kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
ff092385 AG |
3166 | |
3167 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
3168 | skip_emulated_instruction(&svm->vcpu); | |
3169 | return 1; | |
3170 | } | |
3171 | ||
532a46b9 JR |
3172 | static int skinit_interception(struct vcpu_svm *svm) |
3173 | { | |
668f198f | 3174 | trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
532a46b9 JR |
3175 | |
3176 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3177 | return 1; | |
3178 | } | |
3179 | ||
dab429a7 DK |
3180 | static int wbinvd_interception(struct vcpu_svm *svm) |
3181 | { | |
6affcbed | 3182 | return kvm_emulate_wbinvd(&svm->vcpu); |
dab429a7 DK |
3183 | } |
3184 | ||
81dd35d4 JR |
3185 | static int xsetbv_interception(struct vcpu_svm *svm) |
3186 | { | |
3187 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
3188 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
3189 | ||
3190 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
3191 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
3192 | skip_emulated_instruction(&svm->vcpu); | |
3193 | } | |
3194 | ||
3195 | return 1; | |
3196 | } | |
3197 | ||
851ba692 | 3198 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 3199 | { |
37817f29 | 3200 | u16 tss_selector; |
64a7ec06 GN |
3201 | int reason; |
3202 | int int_type = svm->vmcb->control.exit_int_info & | |
3203 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 3204 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
3205 | uint32_t type = |
3206 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
3207 | uint32_t idt_v = | |
3208 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
3209 | bool has_error_code = false; |
3210 | u32 error_code = 0; | |
37817f29 IE |
3211 | |
3212 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 3213 | |
37817f29 IE |
3214 | if (svm->vmcb->control.exit_info_2 & |
3215 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
3216 | reason = TASK_SWITCH_IRET; |
3217 | else if (svm->vmcb->control.exit_info_2 & | |
3218 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
3219 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 3220 | else if (idt_v) |
64a7ec06 GN |
3221 | reason = TASK_SWITCH_GATE; |
3222 | else | |
3223 | reason = TASK_SWITCH_CALL; | |
3224 | ||
fe8e7f83 GN |
3225 | if (reason == TASK_SWITCH_GATE) { |
3226 | switch (type) { | |
3227 | case SVM_EXITINTINFO_TYPE_NMI: | |
3228 | svm->vcpu.arch.nmi_injected = false; | |
3229 | break; | |
3230 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
3231 | if (svm->vmcb->control.exit_info_2 & |
3232 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
3233 | has_error_code = true; | |
3234 | error_code = | |
3235 | (u32)svm->vmcb->control.exit_info_2; | |
3236 | } | |
fe8e7f83 GN |
3237 | kvm_clear_exception_queue(&svm->vcpu); |
3238 | break; | |
3239 | case SVM_EXITINTINFO_TYPE_INTR: | |
3240 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3241 | break; | |
3242 | default: | |
3243 | break; | |
3244 | } | |
3245 | } | |
64a7ec06 | 3246 | |
8317c298 GN |
3247 | if (reason != TASK_SWITCH_GATE || |
3248 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
3249 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
3250 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
3251 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 3252 | |
7f3d35fd KW |
3253 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
3254 | int_vec = -1; | |
3255 | ||
3256 | if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, | |
acb54517 GN |
3257 | has_error_code, error_code) == EMULATE_FAIL) { |
3258 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
3259 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
3260 | svm->vcpu.run->internal.ndata = 0; | |
3261 | return 0; | |
3262 | } | |
3263 | return 1; | |
6aa8b732 AK |
3264 | } |
3265 | ||
851ba692 | 3266 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 3267 | { |
5fdbf976 | 3268 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
6a908b62 | 3269 | return kvm_emulate_cpuid(&svm->vcpu); |
6aa8b732 AK |
3270 | } |
3271 | ||
851ba692 | 3272 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
3273 | { |
3274 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 3275 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 3276 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 3277 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
f303b4ce | 3278 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
95ba8273 GN |
3279 | return 1; |
3280 | } | |
3281 | ||
851ba692 | 3282 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 3283 | { |
df4f3108 AP |
3284 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3285 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
3286 | ||
3287 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
3288 | skip_emulated_instruction(&svm->vcpu); | |
3289 | return 1; | |
a7052897 MT |
3290 | } |
3291 | ||
851ba692 | 3292 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 3293 | { |
51d8b661 | 3294 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
3295 | } |
3296 | ||
332b56e4 AK |
3297 | static int rdpmc_interception(struct vcpu_svm *svm) |
3298 | { | |
3299 | int err; | |
3300 | ||
3301 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
3302 | return emulate_on_interception(svm); | |
3303 | ||
3304 | err = kvm_rdpmc(&svm->vcpu); | |
6affcbed | 3305 | return kvm_complete_insn_gp(&svm->vcpu, err); |
332b56e4 AK |
3306 | } |
3307 | ||
52eb5a6d XL |
3308 | static bool check_selective_cr0_intercepted(struct vcpu_svm *svm, |
3309 | unsigned long val) | |
628afd2a JR |
3310 | { |
3311 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
3312 | bool ret = false; | |
3313 | u64 intercept; | |
3314 | ||
3315 | intercept = svm->nested.intercept; | |
3316 | ||
3317 | if (!is_guest_mode(&svm->vcpu) || | |
3318 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
3319 | return false; | |
3320 | ||
3321 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
3322 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
3323 | ||
3324 | if (cr0 ^ val) { | |
3325 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
3326 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
3327 | } | |
3328 | ||
3329 | return ret; | |
3330 | } | |
3331 | ||
7ff76d58 AP |
3332 | #define CR_VALID (1ULL << 63) |
3333 | ||
3334 | static int cr_interception(struct vcpu_svm *svm) | |
3335 | { | |
3336 | int reg, cr; | |
3337 | unsigned long val; | |
3338 | int err; | |
3339 | ||
3340 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
3341 | return emulate_on_interception(svm); | |
3342 | ||
3343 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
3344 | return emulate_on_interception(svm); | |
3345 | ||
3346 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
5e57518d DK |
3347 | if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE) |
3348 | cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0; | |
3349 | else | |
3350 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
7ff76d58 AP |
3351 | |
3352 | err = 0; | |
3353 | if (cr >= 16) { /* mov to cr */ | |
3354 | cr -= 16; | |
3355 | val = kvm_register_read(&svm->vcpu, reg); | |
3356 | switch (cr) { | |
3357 | case 0: | |
628afd2a JR |
3358 | if (!check_selective_cr0_intercepted(svm, val)) |
3359 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
3360 | else |
3361 | return 1; | |
3362 | ||
7ff76d58 AP |
3363 | break; |
3364 | case 3: | |
3365 | err = kvm_set_cr3(&svm->vcpu, val); | |
3366 | break; | |
3367 | case 4: | |
3368 | err = kvm_set_cr4(&svm->vcpu, val); | |
3369 | break; | |
3370 | case 8: | |
3371 | err = kvm_set_cr8(&svm->vcpu, val); | |
3372 | break; | |
3373 | default: | |
3374 | WARN(1, "unhandled write to CR%d", cr); | |
3375 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3376 | return 1; | |
3377 | } | |
3378 | } else { /* mov from cr */ | |
3379 | switch (cr) { | |
3380 | case 0: | |
3381 | val = kvm_read_cr0(&svm->vcpu); | |
3382 | break; | |
3383 | case 2: | |
3384 | val = svm->vcpu.arch.cr2; | |
3385 | break; | |
3386 | case 3: | |
9f8fe504 | 3387 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
3388 | break; |
3389 | case 4: | |
3390 | val = kvm_read_cr4(&svm->vcpu); | |
3391 | break; | |
3392 | case 8: | |
3393 | val = kvm_get_cr8(&svm->vcpu); | |
3394 | break; | |
3395 | default: | |
3396 | WARN(1, "unhandled read from CR%d", cr); | |
3397 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3398 | return 1; | |
3399 | } | |
3400 | kvm_register_write(&svm->vcpu, reg, val); | |
3401 | } | |
6affcbed | 3402 | return kvm_complete_insn_gp(&svm->vcpu, err); |
7ff76d58 AP |
3403 | } |
3404 | ||
cae3797a AP |
3405 | static int dr_interception(struct vcpu_svm *svm) |
3406 | { | |
3407 | int reg, dr; | |
3408 | unsigned long val; | |
cae3797a | 3409 | |
facb0139 PB |
3410 | if (svm->vcpu.guest_debug == 0) { |
3411 | /* | |
3412 | * No more DR vmexits; force a reload of the debug registers | |
3413 | * and reenter on this instruction. The next vmexit will | |
3414 | * retrieve the full state of the debug registers. | |
3415 | */ | |
3416 | clr_dr_intercepts(svm); | |
3417 | svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
3418 | return 1; | |
3419 | } | |
3420 | ||
cae3797a AP |
3421 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3422 | return emulate_on_interception(svm); | |
3423 | ||
3424 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
3425 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
3426 | ||
3427 | if (dr >= 16) { /* mov to DRn */ | |
16f8a6f9 NA |
3428 | if (!kvm_require_dr(&svm->vcpu, dr - 16)) |
3429 | return 1; | |
cae3797a AP |
3430 | val = kvm_register_read(&svm->vcpu, reg); |
3431 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
3432 | } else { | |
16f8a6f9 NA |
3433 | if (!kvm_require_dr(&svm->vcpu, dr)) |
3434 | return 1; | |
3435 | kvm_get_dr(&svm->vcpu, dr, &val); | |
3436 | kvm_register_write(&svm->vcpu, reg, val); | |
cae3797a AP |
3437 | } |
3438 | ||
2c46d2ae JR |
3439 | skip_emulated_instruction(&svm->vcpu); |
3440 | ||
cae3797a AP |
3441 | return 1; |
3442 | } | |
3443 | ||
851ba692 | 3444 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 3445 | { |
851ba692 | 3446 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 3447 | int r; |
851ba692 | 3448 | |
0a5fff19 GN |
3449 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
3450 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 3451 | r = cr_interception(svm); |
35754c98 | 3452 | if (lapic_in_kernel(&svm->vcpu)) |
7ff76d58 | 3453 | return r; |
0a5fff19 | 3454 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 3455 | return r; |
1d075434 JR |
3456 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
3457 | return 0; | |
3458 | } | |
3459 | ||
609e36d3 | 3460 | static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3461 | { |
a2fa3e9f GH |
3462 | struct vcpu_svm *svm = to_svm(vcpu); |
3463 | ||
609e36d3 | 3464 | switch (msr_info->index) { |
af24a4e4 | 3465 | case MSR_IA32_TSC: { |
609e36d3 | 3466 | msr_info->data = svm->vmcb->control.tsc_offset + |
35181e86 | 3467 | kvm_scale_tsc(vcpu, rdtsc()); |
fbc0db76 | 3468 | |
6aa8b732 AK |
3469 | break; |
3470 | } | |
8c06585d | 3471 | case MSR_STAR: |
609e36d3 | 3472 | msr_info->data = svm->vmcb->save.star; |
6aa8b732 | 3473 | break; |
0e859cac | 3474 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3475 | case MSR_LSTAR: |
609e36d3 | 3476 | msr_info->data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3477 | break; |
3478 | case MSR_CSTAR: | |
609e36d3 | 3479 | msr_info->data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3480 | break; |
3481 | case MSR_KERNEL_GS_BASE: | |
609e36d3 | 3482 | msr_info->data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3483 | break; |
3484 | case MSR_SYSCALL_MASK: | |
609e36d3 | 3485 | msr_info->data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3486 | break; |
3487 | #endif | |
3488 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3489 | msr_info->data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3490 | break; |
3491 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3492 | msr_info->data = svm->sysenter_eip; |
6aa8b732 AK |
3493 | break; |
3494 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3495 | msr_info->data = svm->sysenter_esp; |
6aa8b732 | 3496 | break; |
46896c73 PB |
3497 | case MSR_TSC_AUX: |
3498 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3499 | return 1; | |
3500 | msr_info->data = svm->tsc_aux; | |
3501 | break; | |
e0231715 JR |
3502 | /* |
3503 | * Nobody will change the following 5 values in the VMCB so we can | |
3504 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3505 | * implemented. | |
3506 | */ | |
a2938c80 | 3507 | case MSR_IA32_DEBUGCTLMSR: |
609e36d3 | 3508 | msr_info->data = svm->vmcb->save.dbgctl; |
a2938c80 JR |
3509 | break; |
3510 | case MSR_IA32_LASTBRANCHFROMIP: | |
609e36d3 | 3511 | msr_info->data = svm->vmcb->save.br_from; |
a2938c80 JR |
3512 | break; |
3513 | case MSR_IA32_LASTBRANCHTOIP: | |
609e36d3 | 3514 | msr_info->data = svm->vmcb->save.br_to; |
a2938c80 JR |
3515 | break; |
3516 | case MSR_IA32_LASTINTFROMIP: | |
609e36d3 | 3517 | msr_info->data = svm->vmcb->save.last_excp_from; |
a2938c80 JR |
3518 | break; |
3519 | case MSR_IA32_LASTINTTOIP: | |
609e36d3 | 3520 | msr_info->data = svm->vmcb->save.last_excp_to; |
a2938c80 | 3521 | break; |
b286d5d8 | 3522 | case MSR_VM_HSAVE_PA: |
609e36d3 | 3523 | msr_info->data = svm->nested.hsave_msr; |
b286d5d8 | 3524 | break; |
eb6f302e | 3525 | case MSR_VM_CR: |
609e36d3 | 3526 | msr_info->data = svm->nested.vm_cr_msr; |
eb6f302e | 3527 | break; |
c8a73f18 | 3528 | case MSR_IA32_UCODE_REV: |
609e36d3 | 3529 | msr_info->data = 0x01000065; |
c8a73f18 | 3530 | break; |
ae8b7875 BP |
3531 | case MSR_F15H_IC_CFG: { |
3532 | ||
3533 | int family, model; | |
3534 | ||
3535 | family = guest_cpuid_family(vcpu); | |
3536 | model = guest_cpuid_model(vcpu); | |
3537 | ||
3538 | if (family < 0 || model < 0) | |
3539 | return kvm_get_msr_common(vcpu, msr_info); | |
3540 | ||
3541 | msr_info->data = 0; | |
3542 | ||
3543 | if (family == 0x15 && | |
3544 | (model >= 0x2 && model < 0x20)) | |
3545 | msr_info->data = 0x1E; | |
3546 | } | |
3547 | break; | |
6aa8b732 | 3548 | default: |
609e36d3 | 3549 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3550 | } |
3551 | return 0; | |
3552 | } | |
3553 | ||
851ba692 | 3554 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3555 | { |
668f198f | 3556 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
609e36d3 | 3557 | struct msr_data msr_info; |
6aa8b732 | 3558 | |
609e36d3 PB |
3559 | msr_info.index = ecx; |
3560 | msr_info.host_initiated = false; | |
3561 | if (svm_get_msr(&svm->vcpu, &msr_info)) { | |
59200273 | 3562 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 3563 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 3564 | } else { |
609e36d3 | 3565 | trace_kvm_msr_read(ecx, msr_info.data); |
af9ca2d7 | 3566 | |
609e36d3 PB |
3567 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, |
3568 | msr_info.data & 0xffffffff); | |
3569 | kvm_register_write(&svm->vcpu, VCPU_REGS_RDX, | |
3570 | msr_info.data >> 32); | |
5fdbf976 | 3571 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 3572 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
3573 | } |
3574 | return 1; | |
3575 | } | |
3576 | ||
4a810181 JR |
3577 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3578 | { | |
3579 | struct vcpu_svm *svm = to_svm(vcpu); | |
3580 | int svm_dis, chg_mask; | |
3581 | ||
3582 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3583 | return 1; | |
3584 | ||
3585 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3586 | ||
3587 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3588 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3589 | ||
3590 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3591 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3592 | ||
3593 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3594 | ||
3595 | /* check for svm_disable while efer.svme is set */ | |
3596 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3597 | return 1; | |
3598 | ||
3599 | return 0; | |
3600 | } | |
3601 | ||
8fe8ab46 | 3602 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 3603 | { |
a2fa3e9f GH |
3604 | struct vcpu_svm *svm = to_svm(vcpu); |
3605 | ||
8fe8ab46 WA |
3606 | u32 ecx = msr->index; |
3607 | u64 data = msr->data; | |
6aa8b732 | 3608 | switch (ecx) { |
f4e1b3c8 | 3609 | case MSR_IA32_TSC: |
8fe8ab46 | 3610 | kvm_write_tsc(vcpu, msr); |
6aa8b732 | 3611 | break; |
8c06585d | 3612 | case MSR_STAR: |
a2fa3e9f | 3613 | svm->vmcb->save.star = data; |
6aa8b732 | 3614 | break; |
49b14f24 | 3615 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3616 | case MSR_LSTAR: |
a2fa3e9f | 3617 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3618 | break; |
3619 | case MSR_CSTAR: | |
a2fa3e9f | 3620 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3621 | break; |
3622 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3623 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3624 | break; |
3625 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3626 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3627 | break; |
3628 | #endif | |
3629 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3630 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3631 | break; |
3632 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3633 | svm->sysenter_eip = data; |
a2fa3e9f | 3634 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
3635 | break; |
3636 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3637 | svm->sysenter_esp = data; |
a2fa3e9f | 3638 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 3639 | break; |
46896c73 PB |
3640 | case MSR_TSC_AUX: |
3641 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3642 | return 1; | |
3643 | ||
3644 | /* | |
3645 | * This is rare, so we update the MSR here instead of using | |
3646 | * direct_access_msrs. Doing that would require a rdmsr in | |
3647 | * svm_vcpu_put. | |
3648 | */ | |
3649 | svm->tsc_aux = data; | |
3650 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
3651 | break; | |
a2938c80 | 3652 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 3653 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
3654 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
3655 | __func__, data); | |
24e09cbf JR |
3656 | break; |
3657 | } | |
3658 | if (data & DEBUGCTL_RESERVED_BITS) | |
3659 | return 1; | |
3660 | ||
3661 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 3662 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
3663 | if (data & (1ULL<<0)) |
3664 | svm_enable_lbrv(svm); | |
3665 | else | |
3666 | svm_disable_lbrv(svm); | |
a2938c80 | 3667 | break; |
b286d5d8 | 3668 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3669 | svm->nested.hsave_msr = data; |
62b9abaa | 3670 | break; |
3c5d0a44 | 3671 | case MSR_VM_CR: |
4a810181 | 3672 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3673 | case MSR_VM_IGNNE: |
a737f256 | 3674 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 3675 | break; |
44a95dae SS |
3676 | case MSR_IA32_APICBASE: |
3677 | if (kvm_vcpu_apicv_active(vcpu)) | |
3678 | avic_update_vapic_bar(to_svm(vcpu), data); | |
3679 | /* Follow through */ | |
6aa8b732 | 3680 | default: |
8fe8ab46 | 3681 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
3682 | } |
3683 | return 0; | |
3684 | } | |
3685 | ||
851ba692 | 3686 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3687 | { |
8fe8ab46 | 3688 | struct msr_data msr; |
668f198f DK |
3689 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
3690 | u64 data = kvm_read_edx_eax(&svm->vcpu); | |
af9ca2d7 | 3691 | |
8fe8ab46 WA |
3692 | msr.data = data; |
3693 | msr.index = ecx; | |
3694 | msr.host_initiated = false; | |
af9ca2d7 | 3695 | |
5fdbf976 | 3696 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
854e8bb1 | 3697 | if (kvm_set_msr(&svm->vcpu, &msr)) { |
59200273 | 3698 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3699 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
3700 | } else { |
3701 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 3702 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 3703 | } |
6aa8b732 AK |
3704 | return 1; |
3705 | } | |
3706 | ||
851ba692 | 3707 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3708 | { |
e756fc62 | 3709 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3710 | return wrmsr_interception(svm); |
6aa8b732 | 3711 | else |
851ba692 | 3712 | return rdmsr_interception(svm); |
6aa8b732 AK |
3713 | } |
3714 | ||
851ba692 | 3715 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3716 | { |
3842d135 | 3717 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3718 | svm_clear_vintr(svm); |
85f455f7 | 3719 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3720 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 3721 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3722 | return 1; |
3723 | } | |
3724 | ||
565d0998 ML |
3725 | static int pause_interception(struct vcpu_svm *svm) |
3726 | { | |
3727 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3728 | return 1; | |
3729 | } | |
3730 | ||
87c00572 GS |
3731 | static int nop_interception(struct vcpu_svm *svm) |
3732 | { | |
3733 | skip_emulated_instruction(&(svm->vcpu)); | |
3734 | return 1; | |
3735 | } | |
3736 | ||
3737 | static int monitor_interception(struct vcpu_svm *svm) | |
3738 | { | |
3739 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
3740 | return nop_interception(svm); | |
3741 | } | |
3742 | ||
3743 | static int mwait_interception(struct vcpu_svm *svm) | |
3744 | { | |
3745 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
3746 | return nop_interception(svm); | |
3747 | } | |
3748 | ||
18f40c53 SS |
3749 | enum avic_ipi_failure_cause { |
3750 | AVIC_IPI_FAILURE_INVALID_INT_TYPE, | |
3751 | AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, | |
3752 | AVIC_IPI_FAILURE_INVALID_TARGET, | |
3753 | AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, | |
3754 | }; | |
3755 | ||
3756 | static int avic_incomplete_ipi_interception(struct vcpu_svm *svm) | |
3757 | { | |
3758 | u32 icrh = svm->vmcb->control.exit_info_1 >> 32; | |
3759 | u32 icrl = svm->vmcb->control.exit_info_1; | |
3760 | u32 id = svm->vmcb->control.exit_info_2 >> 32; | |
5446a979 | 3761 | u32 index = svm->vmcb->control.exit_info_2 & 0xFF; |
18f40c53 SS |
3762 | struct kvm_lapic *apic = svm->vcpu.arch.apic; |
3763 | ||
3764 | trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index); | |
3765 | ||
3766 | switch (id) { | |
3767 | case AVIC_IPI_FAILURE_INVALID_INT_TYPE: | |
3768 | /* | |
3769 | * AVIC hardware handles the generation of | |
3770 | * IPIs when the specified Message Type is Fixed | |
3771 | * (also known as fixed delivery mode) and | |
3772 | * the Trigger Mode is edge-triggered. The hardware | |
3773 | * also supports self and broadcast delivery modes | |
3774 | * specified via the Destination Shorthand(DSH) | |
3775 | * field of the ICRL. Logical and physical APIC ID | |
3776 | * formats are supported. All other IPI types cause | |
3777 | * a #VMEXIT, which needs to emulated. | |
3778 | */ | |
3779 | kvm_lapic_reg_write(apic, APIC_ICR2, icrh); | |
3780 | kvm_lapic_reg_write(apic, APIC_ICR, icrl); | |
3781 | break; | |
3782 | case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: { | |
3783 | int i; | |
3784 | struct kvm_vcpu *vcpu; | |
3785 | struct kvm *kvm = svm->vcpu.kvm; | |
3786 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
3787 | ||
3788 | /* | |
3789 | * At this point, we expect that the AVIC HW has already | |
3790 | * set the appropriate IRR bits on the valid target | |
3791 | * vcpus. So, we just need to kick the appropriate vcpu. | |
3792 | */ | |
3793 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
3794 | bool m = kvm_apic_match_dest(vcpu, apic, | |
3795 | icrl & KVM_APIC_SHORT_MASK, | |
3796 | GET_APIC_DEST_FIELD(icrh), | |
3797 | icrl & KVM_APIC_DEST_MASK); | |
3798 | ||
3799 | if (m && !avic_vcpu_is_running(vcpu)) | |
3800 | kvm_vcpu_wake_up(vcpu); | |
3801 | } | |
3802 | break; | |
3803 | } | |
3804 | case AVIC_IPI_FAILURE_INVALID_TARGET: | |
3805 | break; | |
3806 | case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE: | |
3807 | WARN_ONCE(1, "Invalid backing page\n"); | |
3808 | break; | |
3809 | default: | |
3810 | pr_err("Unknown IPI interception\n"); | |
3811 | } | |
3812 | ||
3813 | return 1; | |
3814 | } | |
3815 | ||
3816 | static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat) | |
3817 | { | |
3818 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
3819 | int index; | |
3820 | u32 *logical_apic_id_table; | |
3821 | int dlid = GET_APIC_LOGICAL_ID(ldr); | |
3822 | ||
3823 | if (!dlid) | |
3824 | return NULL; | |
3825 | ||
3826 | if (flat) { /* flat */ | |
3827 | index = ffs(dlid) - 1; | |
3828 | if (index > 7) | |
3829 | return NULL; | |
3830 | } else { /* cluster */ | |
3831 | int cluster = (dlid & 0xf0) >> 4; | |
3832 | int apic = ffs(dlid & 0x0f) - 1; | |
3833 | ||
3834 | if ((apic < 0) || (apic > 7) || | |
3835 | (cluster >= 0xf)) | |
3836 | return NULL; | |
3837 | index = (cluster << 2) + apic; | |
3838 | } | |
3839 | ||
3840 | logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page); | |
3841 | ||
3842 | return &logical_apic_id_table[index]; | |
3843 | } | |
3844 | ||
3845 | static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr, | |
3846 | bool valid) | |
3847 | { | |
3848 | bool flat; | |
3849 | u32 *entry, new_entry; | |
3850 | ||
3851 | flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT; | |
3852 | entry = avic_get_logical_id_entry(vcpu, ldr, flat); | |
3853 | if (!entry) | |
3854 | return -EINVAL; | |
3855 | ||
3856 | new_entry = READ_ONCE(*entry); | |
3857 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK; | |
3858 | new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK); | |
3859 | if (valid) | |
3860 | new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK; | |
3861 | else | |
3862 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK; | |
3863 | WRITE_ONCE(*entry, new_entry); | |
3864 | ||
3865 | return 0; | |
3866 | } | |
3867 | ||
3868 | static int avic_handle_ldr_update(struct kvm_vcpu *vcpu) | |
3869 | { | |
3870 | int ret; | |
3871 | struct vcpu_svm *svm = to_svm(vcpu); | |
3872 | u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR); | |
3873 | ||
3874 | if (!ldr) | |
3875 | return 1; | |
3876 | ||
3877 | ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true); | |
3878 | if (ret && svm->ldr_reg) { | |
3879 | avic_ldr_write(vcpu, 0, svm->ldr_reg, false); | |
3880 | svm->ldr_reg = 0; | |
3881 | } else { | |
3882 | svm->ldr_reg = ldr; | |
3883 | } | |
3884 | return ret; | |
3885 | } | |
3886 | ||
3887 | static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu) | |
3888 | { | |
3889 | u64 *old, *new; | |
3890 | struct vcpu_svm *svm = to_svm(vcpu); | |
3891 | u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID); | |
3892 | u32 id = (apic_id_reg >> 24) & 0xff; | |
3893 | ||
3894 | if (vcpu->vcpu_id == id) | |
3895 | return 0; | |
3896 | ||
3897 | old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id); | |
3898 | new = avic_get_physical_id_entry(vcpu, id); | |
3899 | if (!new || !old) | |
3900 | return 1; | |
3901 | ||
3902 | /* We need to move physical_id_entry to new offset */ | |
3903 | *new = *old; | |
3904 | *old = 0ULL; | |
3905 | to_svm(vcpu)->avic_physical_id_cache = new; | |
3906 | ||
3907 | /* | |
3908 | * Also update the guest physical APIC ID in the logical | |
3909 | * APIC ID table entry if already setup the LDR. | |
3910 | */ | |
3911 | if (svm->ldr_reg) | |
3912 | avic_handle_ldr_update(vcpu); | |
3913 | ||
3914 | return 0; | |
3915 | } | |
3916 | ||
3917 | static int avic_handle_dfr_update(struct kvm_vcpu *vcpu) | |
3918 | { | |
3919 | struct vcpu_svm *svm = to_svm(vcpu); | |
3920 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
3921 | u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR); | |
3922 | u32 mod = (dfr >> 28) & 0xf; | |
3923 | ||
3924 | /* | |
3925 | * We assume that all local APICs are using the same type. | |
3926 | * If this changes, we need to flush the AVIC logical | |
3927 | * APID id table. | |
3928 | */ | |
3929 | if (vm_data->ldr_mode == mod) | |
3930 | return 0; | |
3931 | ||
3932 | clear_page(page_address(vm_data->avic_logical_id_table_page)); | |
3933 | vm_data->ldr_mode = mod; | |
3934 | ||
3935 | if (svm->ldr_reg) | |
3936 | avic_handle_ldr_update(vcpu); | |
3937 | return 0; | |
3938 | } | |
3939 | ||
3940 | static int avic_unaccel_trap_write(struct vcpu_svm *svm) | |
3941 | { | |
3942 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
3943 | u32 offset = svm->vmcb->control.exit_info_1 & | |
3944 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
3945 | ||
3946 | switch (offset) { | |
3947 | case APIC_ID: | |
3948 | if (avic_handle_apic_id_update(&svm->vcpu)) | |
3949 | return 0; | |
3950 | break; | |
3951 | case APIC_LDR: | |
3952 | if (avic_handle_ldr_update(&svm->vcpu)) | |
3953 | return 0; | |
3954 | break; | |
3955 | case APIC_DFR: | |
3956 | avic_handle_dfr_update(&svm->vcpu); | |
3957 | break; | |
3958 | default: | |
3959 | break; | |
3960 | } | |
3961 | ||
3962 | kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); | |
3963 | ||
3964 | return 1; | |
3965 | } | |
3966 | ||
3967 | static bool is_avic_unaccelerated_access_trap(u32 offset) | |
3968 | { | |
3969 | bool ret = false; | |
3970 | ||
3971 | switch (offset) { | |
3972 | case APIC_ID: | |
3973 | case APIC_EOI: | |
3974 | case APIC_RRR: | |
3975 | case APIC_LDR: | |
3976 | case APIC_DFR: | |
3977 | case APIC_SPIV: | |
3978 | case APIC_ESR: | |
3979 | case APIC_ICR: | |
3980 | case APIC_LVTT: | |
3981 | case APIC_LVTTHMR: | |
3982 | case APIC_LVTPC: | |
3983 | case APIC_LVT0: | |
3984 | case APIC_LVT1: | |
3985 | case APIC_LVTERR: | |
3986 | case APIC_TMICT: | |
3987 | case APIC_TDCR: | |
3988 | ret = true; | |
3989 | break; | |
3990 | default: | |
3991 | break; | |
3992 | } | |
3993 | return ret; | |
3994 | } | |
3995 | ||
3996 | static int avic_unaccelerated_access_interception(struct vcpu_svm *svm) | |
3997 | { | |
3998 | int ret = 0; | |
3999 | u32 offset = svm->vmcb->control.exit_info_1 & | |
4000 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
4001 | u32 vector = svm->vmcb->control.exit_info_2 & | |
4002 | AVIC_UNACCEL_ACCESS_VECTOR_MASK; | |
4003 | bool write = (svm->vmcb->control.exit_info_1 >> 32) & | |
4004 | AVIC_UNACCEL_ACCESS_WRITE_MASK; | |
4005 | bool trap = is_avic_unaccelerated_access_trap(offset); | |
4006 | ||
4007 | trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset, | |
4008 | trap, write, vector); | |
4009 | if (trap) { | |
4010 | /* Handling Trap */ | |
4011 | WARN_ONCE(!write, "svm: Handling trap read.\n"); | |
4012 | ret = avic_unaccel_trap_write(svm); | |
4013 | } else { | |
4014 | /* Handling Fault */ | |
4015 | ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE); | |
4016 | } | |
4017 | ||
4018 | return ret; | |
4019 | } | |
4020 | ||
09941fbb | 4021 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
4022 | [SVM_EXIT_READ_CR0] = cr_interception, |
4023 | [SVM_EXIT_READ_CR3] = cr_interception, | |
4024 | [SVM_EXIT_READ_CR4] = cr_interception, | |
4025 | [SVM_EXIT_READ_CR8] = cr_interception, | |
5e57518d | 4026 | [SVM_EXIT_CR0_SEL_WRITE] = cr_interception, |
628afd2a | 4027 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
4028 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
4029 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 4030 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
4031 | [SVM_EXIT_READ_DR0] = dr_interception, |
4032 | [SVM_EXIT_READ_DR1] = dr_interception, | |
4033 | [SVM_EXIT_READ_DR2] = dr_interception, | |
4034 | [SVM_EXIT_READ_DR3] = dr_interception, | |
4035 | [SVM_EXIT_READ_DR4] = dr_interception, | |
4036 | [SVM_EXIT_READ_DR5] = dr_interception, | |
4037 | [SVM_EXIT_READ_DR6] = dr_interception, | |
4038 | [SVM_EXIT_READ_DR7] = dr_interception, | |
4039 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
4040 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
4041 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
4042 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
4043 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
4044 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
4045 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
4046 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
4047 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
4048 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 4049 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 | 4050 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
e0231715 | 4051 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
54a20552 | 4052 | [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception, |
e0231715 | 4053 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 4054 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
4055 | [SVM_EXIT_SMI] = nop_on_interception, |
4056 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 4057 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 4058 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 4059 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 4060 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 4061 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 4062 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 4063 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 4064 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 4065 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 4066 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
4067 | [SVM_EXIT_MSR] = msr_interception, |
4068 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 4069 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 4070 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 4071 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
4072 | [SVM_EXIT_VMLOAD] = vmload_interception, |
4073 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
4074 | [SVM_EXIT_STGI] = stgi_interception, |
4075 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 4076 | [SVM_EXIT_SKINIT] = skinit_interception, |
dab429a7 | 4077 | [SVM_EXIT_WBINVD] = wbinvd_interception, |
87c00572 GS |
4078 | [SVM_EXIT_MONITOR] = monitor_interception, |
4079 | [SVM_EXIT_MWAIT] = mwait_interception, | |
81dd35d4 | 4080 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 4081 | [SVM_EXIT_NPF] = pf_interception, |
64d60670 | 4082 | [SVM_EXIT_RSM] = emulate_on_interception, |
18f40c53 SS |
4083 | [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception, |
4084 | [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception, | |
6aa8b732 AK |
4085 | }; |
4086 | ||
ae8cc059 | 4087 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
4088 | { |
4089 | struct vcpu_svm *svm = to_svm(vcpu); | |
4090 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4091 | struct vmcb_save_area *save = &svm->vmcb->save; | |
4092 | ||
4093 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
4094 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
4095 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
4096 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
4097 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
4098 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
4099 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
4100 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
4101 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
4102 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
4103 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
4104 | pr_err("%-20s%d\n", "asid:", control->asid); | |
4105 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
4106 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
4107 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
4108 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
4109 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
4110 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
4111 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
4112 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
4113 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
4114 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
4115 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
44a95dae | 4116 | pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar); |
ae8cc059 JP |
4117 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); |
4118 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
4119 | pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl); | |
4120 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); | |
44a95dae SS |
4121 | pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page); |
4122 | pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id); | |
4123 | pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id); | |
3f10c846 | 4124 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
4125 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
4126 | "es:", | |
4127 | save->es.selector, save->es.attrib, | |
4128 | save->es.limit, save->es.base); | |
4129 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4130 | "cs:", | |
4131 | save->cs.selector, save->cs.attrib, | |
4132 | save->cs.limit, save->cs.base); | |
4133 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4134 | "ss:", | |
4135 | save->ss.selector, save->ss.attrib, | |
4136 | save->ss.limit, save->ss.base); | |
4137 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4138 | "ds:", | |
4139 | save->ds.selector, save->ds.attrib, | |
4140 | save->ds.limit, save->ds.base); | |
4141 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4142 | "fs:", | |
4143 | save->fs.selector, save->fs.attrib, | |
4144 | save->fs.limit, save->fs.base); | |
4145 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4146 | "gs:", | |
4147 | save->gs.selector, save->gs.attrib, | |
4148 | save->gs.limit, save->gs.base); | |
4149 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4150 | "gdtr:", | |
4151 | save->gdtr.selector, save->gdtr.attrib, | |
4152 | save->gdtr.limit, save->gdtr.base); | |
4153 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4154 | "ldtr:", | |
4155 | save->ldtr.selector, save->ldtr.attrib, | |
4156 | save->ldtr.limit, save->ldtr.base); | |
4157 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4158 | "idtr:", | |
4159 | save->idtr.selector, save->idtr.attrib, | |
4160 | save->idtr.limit, save->idtr.base); | |
4161 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4162 | "tr:", | |
4163 | save->tr.selector, save->tr.attrib, | |
4164 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
4165 | pr_err("cpl: %d efer: %016llx\n", |
4166 | save->cpl, save->efer); | |
ae8cc059 JP |
4167 | pr_err("%-15s %016llx %-13s %016llx\n", |
4168 | "cr0:", save->cr0, "cr2:", save->cr2); | |
4169 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4170 | "cr3:", save->cr3, "cr4:", save->cr4); | |
4171 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4172 | "dr6:", save->dr6, "dr7:", save->dr7); | |
4173 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4174 | "rip:", save->rip, "rflags:", save->rflags); | |
4175 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4176 | "rsp:", save->rsp, "rax:", save->rax); | |
4177 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4178 | "star:", save->star, "lstar:", save->lstar); | |
4179 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4180 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
4181 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4182 | "kernel_gs_base:", save->kernel_gs_base, | |
4183 | "sysenter_cs:", save->sysenter_cs); | |
4184 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4185 | "sysenter_esp:", save->sysenter_esp, | |
4186 | "sysenter_eip:", save->sysenter_eip); | |
4187 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4188 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
4189 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4190 | "br_from:", save->br_from, "br_to:", save->br_to); | |
4191 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4192 | "excp_from:", save->last_excp_from, | |
4193 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
4194 | } |
4195 | ||
586f9607 AK |
4196 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
4197 | { | |
4198 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
4199 | ||
4200 | *info1 = control->exit_info_1; | |
4201 | *info2 = control->exit_info_2; | |
4202 | } | |
4203 | ||
851ba692 | 4204 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 4205 | { |
04d2cc77 | 4206 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 4207 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 4208 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 4209 | |
8b89fe1f PB |
4210 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
4211 | ||
0f89b207 TL |
4212 | vcpu->arch.gpa_available = (exit_code == SVM_EXIT_NPF); |
4213 | ||
4ee546b4 | 4214 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
4215 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
4216 | if (npt_enabled) | |
4217 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 4218 | |
cd3ff653 JR |
4219 | if (unlikely(svm->nested.exit_required)) { |
4220 | nested_svm_vmexit(svm); | |
4221 | svm->nested.exit_required = false; | |
4222 | ||
4223 | return 1; | |
4224 | } | |
4225 | ||
2030753d | 4226 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
4227 | int vmexit; |
4228 | ||
d8cabddf JR |
4229 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
4230 | svm->vmcb->control.exit_info_1, | |
4231 | svm->vmcb->control.exit_info_2, | |
4232 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
4233 | svm->vmcb->control.exit_int_info_err, |
4234 | KVM_ISA_SVM); | |
d8cabddf | 4235 | |
410e4d57 JR |
4236 | vmexit = nested_svm_exit_special(svm); |
4237 | ||
4238 | if (vmexit == NESTED_EXIT_CONTINUE) | |
4239 | vmexit = nested_svm_exit_handled(svm); | |
4240 | ||
4241 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 4242 | return 1; |
cf74a78b AG |
4243 | } |
4244 | ||
a5c3832d JR |
4245 | svm_complete_interrupts(svm); |
4246 | ||
04d2cc77 AK |
4247 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
4248 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
4249 | kvm_run->fail_entry.hardware_entry_failure_reason | |
4250 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
4251 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
4252 | dump_vmcb(vcpu); | |
04d2cc77 AK |
4253 | return 0; |
4254 | } | |
4255 | ||
a2fa3e9f | 4256 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 4257 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
4258 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
4259 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 4260 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 4261 | "exit_code 0x%x\n", |
b8688d51 | 4262 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
4263 | exit_code); |
4264 | ||
9d8f549d | 4265 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 4266 | || !svm_exit_handlers[exit_code]) { |
faac2458 | 4267 | WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code); |
2bc19dc3 MT |
4268 | kvm_queue_exception(vcpu, UD_VECTOR); |
4269 | return 1; | |
6aa8b732 AK |
4270 | } |
4271 | ||
851ba692 | 4272 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
4273 | } |
4274 | ||
4275 | static void reload_tss(struct kvm_vcpu *vcpu) | |
4276 | { | |
4277 | int cpu = raw_smp_processor_id(); | |
4278 | ||
0fe1e009 TH |
4279 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
4280 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
4281 | load_TR_desc(); |
4282 | } | |
4283 | ||
e756fc62 | 4284 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
4285 | { |
4286 | int cpu = raw_smp_processor_id(); | |
4287 | ||
0fe1e009 | 4288 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 4289 | |
4b656b12 | 4290 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
4291 | if (svm->asid_generation != sd->asid_generation) |
4292 | new_asid(svm, sd); | |
6aa8b732 AK |
4293 | } |
4294 | ||
95ba8273 GN |
4295 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
4296 | { | |
4297 | struct vcpu_svm *svm = to_svm(vcpu); | |
4298 | ||
4299 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
4300 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 4301 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
4302 | ++vcpu->stat.nmi_injections; |
4303 | } | |
6aa8b732 | 4304 | |
85f455f7 | 4305 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
4306 | { |
4307 | struct vmcb_control_area *control; | |
4308 | ||
340d3bc3 | 4309 | /* The following fields are ignored when AVIC is enabled */ |
e756fc62 | 4310 | control = &svm->vmcb->control; |
85f455f7 | 4311 | control->int_vector = irq; |
6aa8b732 AK |
4312 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
4313 | control->int_ctl |= V_IRQ_MASK | | |
4314 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 4315 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
4316 | } |
4317 | ||
66fd3f7f | 4318 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
4319 | { |
4320 | struct vcpu_svm *svm = to_svm(vcpu); | |
4321 | ||
2af9194d | 4322 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 4323 | |
9fb2d2b4 GN |
4324 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
4325 | ++vcpu->stat.irq_injections; | |
4326 | ||
219b65dc AG |
4327 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
4328 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
4329 | } |
4330 | ||
3bbf3565 SS |
4331 | static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu) |
4332 | { | |
4333 | return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK); | |
4334 | } | |
4335 | ||
95ba8273 | 4336 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
4337 | { |
4338 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 4339 | |
3bbf3565 SS |
4340 | if (svm_nested_virtualize_tpr(vcpu) || |
4341 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
4342 | return; |
4343 | ||
596f3142 RK |
4344 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
4345 | ||
95ba8273 | 4346 | if (irr == -1) |
aaacfc9a JR |
4347 | return; |
4348 | ||
95ba8273 | 4349 | if (tpr >= irr) |
4ee546b4 | 4350 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 4351 | } |
aaacfc9a | 4352 | |
8d14695f YZ |
4353 | static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
4354 | { | |
4355 | return; | |
4356 | } | |
4357 | ||
d62caabb AS |
4358 | static bool svm_get_enable_apicv(void) |
4359 | { | |
44a95dae SS |
4360 | return avic; |
4361 | } | |
4362 | ||
4363 | static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
4364 | { | |
d62caabb AS |
4365 | } |
4366 | ||
67c9dddc | 4367 | static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
44a95dae | 4368 | { |
d62caabb AS |
4369 | } |
4370 | ||
44a95dae | 4371 | /* Note: Currently only used by Hyper-V. */ |
d62caabb | 4372 | static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
c7c9c56c | 4373 | { |
44a95dae SS |
4374 | struct vcpu_svm *svm = to_svm(vcpu); |
4375 | struct vmcb *vmcb = svm->vmcb; | |
4376 | ||
4377 | if (!avic) | |
4378 | return; | |
4379 | ||
4380 | vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK; | |
4381 | mark_dirty(vmcb, VMCB_INTR); | |
c7c9c56c YZ |
4382 | } |
4383 | ||
6308630b | 4384 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c YZ |
4385 | { |
4386 | return; | |
4387 | } | |
4388 | ||
340d3bc3 SS |
4389 | static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec) |
4390 | { | |
4391 | kvm_lapic_set_irr(vec, vcpu->arch.apic); | |
4392 | smp_mb__after_atomic(); | |
4393 | ||
4394 | if (avic_vcpu_is_running(vcpu)) | |
4395 | wrmsrl(SVM_AVIC_DOORBELL, | |
7d669f50 | 4396 | kvm_cpu_get_apicid(vcpu->cpu)); |
340d3bc3 SS |
4397 | else |
4398 | kvm_vcpu_wake_up(vcpu); | |
4399 | } | |
4400 | ||
411b44ba SS |
4401 | static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) |
4402 | { | |
4403 | unsigned long flags; | |
4404 | struct amd_svm_iommu_ir *cur; | |
4405 | ||
4406 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
4407 | list_for_each_entry(cur, &svm->ir_list, node) { | |
4408 | if (cur->data != pi->ir_data) | |
4409 | continue; | |
4410 | list_del(&cur->node); | |
4411 | kfree(cur); | |
4412 | break; | |
4413 | } | |
4414 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
4415 | } | |
4416 | ||
4417 | static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) | |
4418 | { | |
4419 | int ret = 0; | |
4420 | unsigned long flags; | |
4421 | struct amd_svm_iommu_ir *ir; | |
4422 | ||
4423 | /** | |
4424 | * In some cases, the existing irte is updaed and re-set, | |
4425 | * so we need to check here if it's already been * added | |
4426 | * to the ir_list. | |
4427 | */ | |
4428 | if (pi->ir_data && (pi->prev_ga_tag != 0)) { | |
4429 | struct kvm *kvm = svm->vcpu.kvm; | |
4430 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag); | |
4431 | struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); | |
4432 | struct vcpu_svm *prev_svm; | |
4433 | ||
4434 | if (!prev_vcpu) { | |
4435 | ret = -EINVAL; | |
4436 | goto out; | |
4437 | } | |
4438 | ||
4439 | prev_svm = to_svm(prev_vcpu); | |
4440 | svm_ir_list_del(prev_svm, pi); | |
4441 | } | |
4442 | ||
4443 | /** | |
4444 | * Allocating new amd_iommu_pi_data, which will get | |
4445 | * add to the per-vcpu ir_list. | |
4446 | */ | |
4447 | ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL); | |
4448 | if (!ir) { | |
4449 | ret = -ENOMEM; | |
4450 | goto out; | |
4451 | } | |
4452 | ir->data = pi->ir_data; | |
4453 | ||
4454 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
4455 | list_add(&ir->node, &svm->ir_list); | |
4456 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
4457 | out: | |
4458 | return ret; | |
4459 | } | |
4460 | ||
4461 | /** | |
4462 | * Note: | |
4463 | * The HW cannot support posting multicast/broadcast | |
4464 | * interrupts to a vCPU. So, we still use legacy interrupt | |
4465 | * remapping for these kind of interrupts. | |
4466 | * | |
4467 | * For lowest-priority interrupts, we only support | |
4468 | * those with single CPU as the destination, e.g. user | |
4469 | * configures the interrupts via /proc/irq or uses | |
4470 | * irqbalance to make the interrupts single-CPU. | |
4471 | */ | |
4472 | static int | |
4473 | get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, | |
4474 | struct vcpu_data *vcpu_info, struct vcpu_svm **svm) | |
4475 | { | |
4476 | struct kvm_lapic_irq irq; | |
4477 | struct kvm_vcpu *vcpu = NULL; | |
4478 | ||
4479 | kvm_set_msi_irq(kvm, e, &irq); | |
4480 | ||
4481 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { | |
4482 | pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n", | |
4483 | __func__, irq.vector); | |
4484 | return -1; | |
4485 | } | |
4486 | ||
4487 | pr_debug("SVM: %s: use GA mode for irq %u\n", __func__, | |
4488 | irq.vector); | |
4489 | *svm = to_svm(vcpu); | |
4490 | vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page); | |
4491 | vcpu_info->vector = irq.vector; | |
4492 | ||
4493 | return 0; | |
4494 | } | |
4495 | ||
4496 | /* | |
4497 | * svm_update_pi_irte - set IRTE for Posted-Interrupts | |
4498 | * | |
4499 | * @kvm: kvm | |
4500 | * @host_irq: host irq of the interrupt | |
4501 | * @guest_irq: gsi of the interrupt | |
4502 | * @set: set or unset PI | |
4503 | * returns 0 on success, < 0 on failure | |
4504 | */ | |
4505 | static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
4506 | uint32_t guest_irq, bool set) | |
4507 | { | |
4508 | struct kvm_kernel_irq_routing_entry *e; | |
4509 | struct kvm_irq_routing_table *irq_rt; | |
4510 | int idx, ret = -EINVAL; | |
4511 | ||
4512 | if (!kvm_arch_has_assigned_device(kvm) || | |
4513 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
4514 | return 0; | |
4515 | ||
4516 | pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n", | |
4517 | __func__, host_irq, guest_irq, set); | |
4518 | ||
4519 | idx = srcu_read_lock(&kvm->irq_srcu); | |
4520 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
4521 | WARN_ON(guest_irq >= irq_rt->nr_rt_entries); | |
4522 | ||
4523 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
4524 | struct vcpu_data vcpu_info; | |
4525 | struct vcpu_svm *svm = NULL; | |
4526 | ||
4527 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
4528 | continue; | |
4529 | ||
4530 | /** | |
4531 | * Here, we setup with legacy mode in the following cases: | |
4532 | * 1. When cannot target interrupt to a specific vcpu. | |
4533 | * 2. Unsetting posted interrupt. | |
4534 | * 3. APIC virtialization is disabled for the vcpu. | |
4535 | */ | |
4536 | if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set && | |
4537 | kvm_vcpu_apicv_active(&svm->vcpu)) { | |
4538 | struct amd_iommu_pi_data pi; | |
4539 | ||
4540 | /* Try to enable guest_mode in IRTE */ | |
4541 | pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK; | |
4542 | pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id, | |
4543 | svm->vcpu.vcpu_id); | |
4544 | pi.is_guest_mode = true; | |
4545 | pi.vcpu_data = &vcpu_info; | |
4546 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
4547 | ||
4548 | /** | |
4549 | * Here, we successfully setting up vcpu affinity in | |
4550 | * IOMMU guest mode. Now, we need to store the posted | |
4551 | * interrupt information in a per-vcpu ir_list so that | |
4552 | * we can reference to them directly when we update vcpu | |
4553 | * scheduling information in IOMMU irte. | |
4554 | */ | |
4555 | if (!ret && pi.is_guest_mode) | |
4556 | svm_ir_list_add(svm, &pi); | |
4557 | } else { | |
4558 | /* Use legacy mode in IRTE */ | |
4559 | struct amd_iommu_pi_data pi; | |
4560 | ||
4561 | /** | |
4562 | * Here, pi is used to: | |
4563 | * - Tell IOMMU to use legacy mode for this interrupt. | |
4564 | * - Retrieve ga_tag of prior interrupt remapping data. | |
4565 | */ | |
4566 | pi.is_guest_mode = false; | |
4567 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
4568 | ||
4569 | /** | |
4570 | * Check if the posted interrupt was previously | |
4571 | * setup with the guest_mode by checking if the ga_tag | |
4572 | * was cached. If so, we need to clean up the per-vcpu | |
4573 | * ir_list. | |
4574 | */ | |
4575 | if (!ret && pi.prev_ga_tag) { | |
4576 | int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag); | |
4577 | struct kvm_vcpu *vcpu; | |
4578 | ||
4579 | vcpu = kvm_get_vcpu_by_id(kvm, id); | |
4580 | if (vcpu) | |
4581 | svm_ir_list_del(to_svm(vcpu), &pi); | |
4582 | } | |
4583 | } | |
4584 | ||
4585 | if (!ret && svm) { | |
4586 | trace_kvm_pi_irte_update(svm->vcpu.vcpu_id, | |
4587 | host_irq, e->gsi, | |
4588 | vcpu_info.vector, | |
4589 | vcpu_info.pi_desc_addr, set); | |
4590 | } | |
4591 | ||
4592 | if (ret < 0) { | |
4593 | pr_err("%s: failed to update PI IRTE\n", __func__); | |
4594 | goto out; | |
4595 | } | |
4596 | } | |
4597 | ||
4598 | ret = 0; | |
4599 | out: | |
4600 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
4601 | return ret; | |
4602 | } | |
4603 | ||
95ba8273 GN |
4604 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
4605 | { | |
4606 | struct vcpu_svm *svm = to_svm(vcpu); | |
4607 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
4608 | int ret; |
4609 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
4610 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
4611 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
4612 | ||
4613 | return ret; | |
aaacfc9a JR |
4614 | } |
4615 | ||
3cfc3092 JK |
4616 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
4617 | { | |
4618 | struct vcpu_svm *svm = to_svm(vcpu); | |
4619 | ||
4620 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
4621 | } | |
4622 | ||
4623 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
4624 | { | |
4625 | struct vcpu_svm *svm = to_svm(vcpu); | |
4626 | ||
4627 | if (masked) { | |
4628 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 4629 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
4630 | } else { |
4631 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 4632 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
4633 | } |
4634 | } | |
4635 | ||
78646121 GN |
4636 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
4637 | { | |
4638 | struct vcpu_svm *svm = to_svm(vcpu); | |
4639 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
4640 | int ret; |
4641 | ||
4642 | if (!gif_set(svm) || | |
4643 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
4644 | return 0; | |
4645 | ||
f6e78475 | 4646 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 4647 | |
2030753d | 4648 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
4649 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
4650 | ||
4651 | return ret; | |
78646121 GN |
4652 | } |
4653 | ||
c9a7953f | 4654 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 4655 | { |
219b65dc | 4656 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 4657 | |
340d3bc3 SS |
4658 | if (kvm_vcpu_apicv_active(vcpu)) |
4659 | return; | |
4660 | ||
e0231715 JR |
4661 | /* |
4662 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
4663 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
4664 | * get that intercept, this function will be called again though and | |
4665 | * we'll get the vintr intercept. | |
4666 | */ | |
8fe54654 | 4667 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
4668 | svm_set_vintr(svm); |
4669 | svm_inject_irq(svm, 0x0); | |
4670 | } | |
85f455f7 ED |
4671 | } |
4672 | ||
c9a7953f | 4673 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 4674 | { |
04d2cc77 | 4675 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 4676 | |
44c11430 GN |
4677 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
4678 | == HF_NMI_MASK) | |
c9a7953f | 4679 | return; /* IRET will cause a vm exit */ |
44c11430 | 4680 | |
e0231715 JR |
4681 | /* |
4682 | * Something prevents NMI from been injected. Single step over possible | |
4683 | * problem (IRET or exception injection or interrupt shadow) | |
4684 | */ | |
ab2f4d73 | 4685 | svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu); |
6be7d306 | 4686 | svm->nmi_singlestep = true; |
44c11430 | 4687 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c1150d8c DL |
4688 | } |
4689 | ||
cbc94022 IE |
4690 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
4691 | { | |
4692 | return 0; | |
4693 | } | |
4694 | ||
d9e368d6 AK |
4695 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
4696 | { | |
38e5e92f JR |
4697 | struct vcpu_svm *svm = to_svm(vcpu); |
4698 | ||
4699 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
4700 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
4701 | else | |
4702 | svm->asid_generation--; | |
d9e368d6 AK |
4703 | } |
4704 | ||
04d2cc77 AK |
4705 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
4706 | { | |
4707 | } | |
4708 | ||
d7bf8221 JR |
4709 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
4710 | { | |
4711 | struct vcpu_svm *svm = to_svm(vcpu); | |
4712 | ||
3bbf3565 | 4713 | if (svm_nested_virtualize_tpr(vcpu)) |
88ab24ad JR |
4714 | return; |
4715 | ||
4ee546b4 | 4716 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 4717 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 4718 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
4719 | } |
4720 | } | |
4721 | ||
649d6864 JR |
4722 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
4723 | { | |
4724 | struct vcpu_svm *svm = to_svm(vcpu); | |
4725 | u64 cr8; | |
4726 | ||
3bbf3565 SS |
4727 | if (svm_nested_virtualize_tpr(vcpu) || |
4728 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
4729 | return; |
4730 | ||
649d6864 JR |
4731 | cr8 = kvm_get_cr8(vcpu); |
4732 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
4733 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
4734 | } | |
4735 | ||
9222be18 GN |
4736 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
4737 | { | |
4738 | u8 vector; | |
4739 | int type; | |
4740 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
4741 | unsigned int3_injected = svm->int3_injected; |
4742 | ||
4743 | svm->int3_injected = 0; | |
9222be18 | 4744 | |
bd3d1ec3 AK |
4745 | /* |
4746 | * If we've made progress since setting HF_IRET_MASK, we've | |
4747 | * executed an IRET and can allow NMI injection. | |
4748 | */ | |
4749 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
4750 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 4751 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
4752 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
4753 | } | |
44c11430 | 4754 | |
9222be18 GN |
4755 | svm->vcpu.arch.nmi_injected = false; |
4756 | kvm_clear_exception_queue(&svm->vcpu); | |
4757 | kvm_clear_interrupt_queue(&svm->vcpu); | |
4758 | ||
4759 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
4760 | return; | |
4761 | ||
3842d135 AK |
4762 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
4763 | ||
9222be18 GN |
4764 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
4765 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
4766 | ||
4767 | switch (type) { | |
4768 | case SVM_EXITINTINFO_TYPE_NMI: | |
4769 | svm->vcpu.arch.nmi_injected = true; | |
4770 | break; | |
4771 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
4772 | /* |
4773 | * In case of software exceptions, do not reinject the vector, | |
4774 | * but re-execute the instruction instead. Rewind RIP first | |
4775 | * if we emulated INT3 before. | |
4776 | */ | |
4777 | if (kvm_exception_is_soft(vector)) { | |
4778 | if (vector == BP_VECTOR && int3_injected && | |
4779 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
4780 | kvm_rip_write(&svm->vcpu, | |
4781 | kvm_rip_read(&svm->vcpu) - | |
4782 | int3_injected); | |
9222be18 | 4783 | break; |
66b7138f | 4784 | } |
9222be18 GN |
4785 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
4786 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 4787 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
4788 | |
4789 | } else | |
ce7ddec4 | 4790 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
4791 | break; |
4792 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 4793 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
4794 | break; |
4795 | default: | |
4796 | break; | |
4797 | } | |
4798 | } | |
4799 | ||
b463a6f7 AK |
4800 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
4801 | { | |
4802 | struct vcpu_svm *svm = to_svm(vcpu); | |
4803 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4804 | ||
4805 | control->exit_int_info = control->event_inj; | |
4806 | control->exit_int_info_err = control->event_inj_err; | |
4807 | control->event_inj = 0; | |
4808 | svm_complete_interrupts(svm); | |
4809 | } | |
4810 | ||
851ba692 | 4811 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 4812 | { |
a2fa3e9f | 4813 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 4814 | |
2041a06a JR |
4815 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
4816 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
4817 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
4818 | ||
cd3ff653 JR |
4819 | /* |
4820 | * A vmexit emulation is required before the vcpu can be executed | |
4821 | * again. | |
4822 | */ | |
4823 | if (unlikely(svm->nested.exit_required)) | |
4824 | return; | |
4825 | ||
e756fc62 | 4826 | pre_svm_run(svm); |
6aa8b732 | 4827 | |
649d6864 JR |
4828 | sync_lapic_to_cr8(vcpu); |
4829 | ||
cda0ffdd | 4830 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 4831 | |
04d2cc77 AK |
4832 | clgi(); |
4833 | ||
4834 | local_irq_enable(); | |
36241b8c | 4835 | |
6aa8b732 | 4836 | asm volatile ( |
7454766f AK |
4837 | "push %%" _ASM_BP "; \n\t" |
4838 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
4839 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
4840 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
4841 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
4842 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
4843 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 4844 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
4845 | "mov %c[r8](%[svm]), %%r8 \n\t" |
4846 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
4847 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
4848 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
4849 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
4850 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
4851 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
4852 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
4853 | #endif |
4854 | ||
6aa8b732 | 4855 | /* Enter guest mode */ |
7454766f AK |
4856 | "push %%" _ASM_AX " \n\t" |
4857 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
4ecac3fd AK |
4858 | __ex(SVM_VMLOAD) "\n\t" |
4859 | __ex(SVM_VMRUN) "\n\t" | |
4860 | __ex(SVM_VMSAVE) "\n\t" | |
7454766f | 4861 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
4862 | |
4863 | /* Save guest registers, load host registers */ | |
7454766f AK |
4864 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
4865 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
4866 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
4867 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
4868 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
4869 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 4870 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
4871 | "mov %%r8, %c[r8](%[svm]) \n\t" |
4872 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
4873 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
4874 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
4875 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
4876 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
4877 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
4878 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 4879 | #endif |
7454766f | 4880 | "pop %%" _ASM_BP |
6aa8b732 | 4881 | : |
fb3f0f51 | 4882 | : [svm]"a"(svm), |
6aa8b732 | 4883 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
4884 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
4885 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
4886 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
4887 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
4888 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
4889 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 4890 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
4891 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
4892 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
4893 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
4894 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
4895 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
4896 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
4897 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
4898 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 4899 | #endif |
54a08c04 LV |
4900 | : "cc", "memory" |
4901 | #ifdef CONFIG_X86_64 | |
7454766f | 4902 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 4903 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
4904 | #else |
4905 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
4906 | #endif |
4907 | ); | |
6aa8b732 | 4908 | |
82ca2d10 AK |
4909 | #ifdef CONFIG_X86_64 |
4910 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
4911 | #else | |
dacccfdd | 4912 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
4913 | #ifndef CONFIG_X86_32_LAZY_GS |
4914 | loadsegment(gs, svm->host.gs); | |
4915 | #endif | |
9581d442 | 4916 | #endif |
6aa8b732 AK |
4917 | |
4918 | reload_tss(vcpu); | |
4919 | ||
56ba47dd AK |
4920 | local_irq_disable(); |
4921 | ||
13c34e07 AK |
4922 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
4923 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
4924 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
4925 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
4926 | ||
3781c01c JR |
4927 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
4928 | kvm_before_handle_nmi(&svm->vcpu); | |
4929 | ||
4930 | stgi(); | |
4931 | ||
4932 | /* Any pending NMI will happen here */ | |
4933 | ||
4934 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
4935 | kvm_after_handle_nmi(&svm->vcpu); | |
4936 | ||
d7bf8221 JR |
4937 | sync_cr8_to_lapic(vcpu); |
4938 | ||
a2fa3e9f | 4939 | svm->next_rip = 0; |
9222be18 | 4940 | |
38e5e92f JR |
4941 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
4942 | ||
631bc487 GN |
4943 | /* if exit due to PF check for async PF */ |
4944 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
4945 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
4946 | ||
6de4f3ad AK |
4947 | if (npt_enabled) { |
4948 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
4949 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
4950 | } | |
fe5913e4 JR |
4951 | |
4952 | /* | |
4953 | * We need to handle MC intercepts here before the vcpu has a chance to | |
4954 | * change the physical cpu | |
4955 | */ | |
4956 | if (unlikely(svm->vmcb->control.exit_code == | |
4957 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
4958 | svm_handle_mce(svm); | |
8d28fec4 RJ |
4959 | |
4960 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
4961 | } |
4962 | ||
6aa8b732 AK |
4963 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
4964 | { | |
a2fa3e9f GH |
4965 | struct vcpu_svm *svm = to_svm(vcpu); |
4966 | ||
4967 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 4968 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 4969 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
4970 | } |
4971 | ||
1c97f0a0 JR |
4972 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
4973 | { | |
4974 | struct vcpu_svm *svm = to_svm(vcpu); | |
4975 | ||
4976 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 4977 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
4978 | |
4979 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 4980 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 4981 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 4982 | |
f40f6a45 | 4983 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
4984 | } |
4985 | ||
6aa8b732 AK |
4986 | static int is_disabled(void) |
4987 | { | |
6031a61c JR |
4988 | u64 vm_cr; |
4989 | ||
4990 | rdmsrl(MSR_VM_CR, vm_cr); | |
4991 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
4992 | return 1; | |
4993 | ||
6aa8b732 AK |
4994 | return 0; |
4995 | } | |
4996 | ||
102d8325 IM |
4997 | static void |
4998 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
4999 | { | |
5000 | /* | |
5001 | * Patch in the VMMCALL instruction: | |
5002 | */ | |
5003 | hypercall[0] = 0x0f; | |
5004 | hypercall[1] = 0x01; | |
5005 | hypercall[2] = 0xd9; | |
102d8325 IM |
5006 | } |
5007 | ||
002c7f7c YS |
5008 | static void svm_check_processor_compat(void *rtn) |
5009 | { | |
5010 | *(int *)rtn = 0; | |
5011 | } | |
5012 | ||
774ead3a AK |
5013 | static bool svm_cpu_has_accelerated_tpr(void) |
5014 | { | |
5015 | return false; | |
5016 | } | |
5017 | ||
6d396b55 PB |
5018 | static bool svm_has_high_real_mode_segbase(void) |
5019 | { | |
5020 | return true; | |
5021 | } | |
5022 | ||
fc07e76a PB |
5023 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
5024 | { | |
5025 | return 0; | |
5026 | } | |
5027 | ||
0e851880 SY |
5028 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
5029 | { | |
6092d3d3 | 5030 | struct vcpu_svm *svm = to_svm(vcpu); |
46781eae | 5031 | struct kvm_cpuid_entry2 *entry; |
6092d3d3 JR |
5032 | |
5033 | /* Update nrips enabled cache */ | |
5034 | svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu); | |
46781eae SS |
5035 | |
5036 | if (!kvm_vcpu_apicv_active(vcpu)) | |
5037 | return; | |
5038 | ||
5039 | entry = kvm_find_cpuid_entry(vcpu, 1, 0); | |
5040 | if (entry) | |
5041 | entry->ecx &= ~bit(X86_FEATURE_X2APIC); | |
0e851880 SY |
5042 | } |
5043 | ||
d4330ef2 JR |
5044 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
5045 | { | |
c2c63a49 | 5046 | switch (func) { |
46781eae SS |
5047 | case 0x1: |
5048 | if (avic) | |
5049 | entry->ecx &= ~bit(X86_FEATURE_X2APIC); | |
5050 | break; | |
4c62a2dc JR |
5051 | case 0x80000001: |
5052 | if (nested) | |
5053 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
5054 | break; | |
c2c63a49 JR |
5055 | case 0x8000000A: |
5056 | entry->eax = 1; /* SVM revision 1 */ | |
5057 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
5058 | ASID emulation to nested SVM */ | |
5059 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
5060 | entry->edx = 0; /* Per default do not support any |
5061 | additional features */ | |
5062 | ||
5063 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 5064 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 5065 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 5066 | |
3d4aeaad JR |
5067 | /* Support NPT for the guest if enabled */ |
5068 | if (npt_enabled) | |
5069 | entry->edx |= SVM_FEATURE_NPT; | |
5070 | ||
c2c63a49 JR |
5071 | break; |
5072 | } | |
d4330ef2 JR |
5073 | } |
5074 | ||
17cc3935 | 5075 | static int svm_get_lpage_level(void) |
344f414f | 5076 | { |
17cc3935 | 5077 | return PT_PDPE_LEVEL; |
344f414f JR |
5078 | } |
5079 | ||
4e47c7a6 SY |
5080 | static bool svm_rdtscp_supported(void) |
5081 | { | |
46896c73 | 5082 | return boot_cpu_has(X86_FEATURE_RDTSCP); |
4e47c7a6 SY |
5083 | } |
5084 | ||
ad756a16 MJ |
5085 | static bool svm_invpcid_supported(void) |
5086 | { | |
5087 | return false; | |
5088 | } | |
5089 | ||
93c4adc7 PB |
5090 | static bool svm_mpx_supported(void) |
5091 | { | |
5092 | return false; | |
5093 | } | |
5094 | ||
55412b2e WL |
5095 | static bool svm_xsaves_supported(void) |
5096 | { | |
5097 | return false; | |
5098 | } | |
5099 | ||
f5f48ee1 SY |
5100 | static bool svm_has_wbinvd_exit(void) |
5101 | { | |
5102 | return true; | |
5103 | } | |
5104 | ||
8061252e | 5105 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 5106 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 5107 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 5108 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 5109 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 5110 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 5111 | |
09941fbb | 5112 | static const struct __x86_intercept { |
cfec82cb JR |
5113 | u32 exit_code; |
5114 | enum x86_intercept_stage stage; | |
cfec82cb JR |
5115 | } x86_intercept_map[] = { |
5116 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
5117 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5118 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5119 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5120 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
5121 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
5122 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
5123 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
5124 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
5125 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
5126 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
5127 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
5128 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
5129 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
5130 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
5131 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
5132 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
5133 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
5134 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
5135 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
5136 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
5137 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
5138 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
5139 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
5140 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
5141 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
5142 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
5143 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
5144 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
5145 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
5146 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
5147 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
5148 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
5149 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
5150 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
5151 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
5152 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
5153 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
5154 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
5155 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
5156 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
5157 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
5158 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
5159 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
5160 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
5161 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
5162 | }; |
5163 | ||
8061252e | 5164 | #undef PRE_EX |
cfec82cb | 5165 | #undef POST_EX |
d7eb8203 | 5166 | #undef POST_MEM |
cfec82cb | 5167 | |
8a76d7f2 JR |
5168 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
5169 | struct x86_instruction_info *info, | |
5170 | enum x86_intercept_stage stage) | |
5171 | { | |
cfec82cb JR |
5172 | struct vcpu_svm *svm = to_svm(vcpu); |
5173 | int vmexit, ret = X86EMUL_CONTINUE; | |
5174 | struct __x86_intercept icpt_info; | |
5175 | struct vmcb *vmcb = svm->vmcb; | |
5176 | ||
5177 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
5178 | goto out; | |
5179 | ||
5180 | icpt_info = x86_intercept_map[info->intercept]; | |
5181 | ||
40e19b51 | 5182 | if (stage != icpt_info.stage) |
cfec82cb JR |
5183 | goto out; |
5184 | ||
5185 | switch (icpt_info.exit_code) { | |
5186 | case SVM_EXIT_READ_CR0: | |
5187 | if (info->intercept == x86_intercept_cr_read) | |
5188 | icpt_info.exit_code += info->modrm_reg; | |
5189 | break; | |
5190 | case SVM_EXIT_WRITE_CR0: { | |
5191 | unsigned long cr0, val; | |
5192 | u64 intercept; | |
5193 | ||
5194 | if (info->intercept == x86_intercept_cr_write) | |
5195 | icpt_info.exit_code += info->modrm_reg; | |
5196 | ||
62baf44c JK |
5197 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 || |
5198 | info->intercept == x86_intercept_clts) | |
cfec82cb JR |
5199 | break; |
5200 | ||
5201 | intercept = svm->nested.intercept; | |
5202 | ||
5203 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
5204 | break; | |
5205 | ||
5206 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
5207 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
5208 | ||
5209 | if (info->intercept == x86_intercept_lmsw) { | |
5210 | cr0 &= 0xfUL; | |
5211 | val &= 0xfUL; | |
5212 | /* lmsw can't clear PE - catch this here */ | |
5213 | if (cr0 & X86_CR0_PE) | |
5214 | val |= X86_CR0_PE; | |
5215 | } | |
5216 | ||
5217 | if (cr0 ^ val) | |
5218 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
5219 | ||
5220 | break; | |
5221 | } | |
3b88e41a JR |
5222 | case SVM_EXIT_READ_DR0: |
5223 | case SVM_EXIT_WRITE_DR0: | |
5224 | icpt_info.exit_code += info->modrm_reg; | |
5225 | break; | |
8061252e JR |
5226 | case SVM_EXIT_MSR: |
5227 | if (info->intercept == x86_intercept_wrmsr) | |
5228 | vmcb->control.exit_info_1 = 1; | |
5229 | else | |
5230 | vmcb->control.exit_info_1 = 0; | |
5231 | break; | |
bf608f88 JR |
5232 | case SVM_EXIT_PAUSE: |
5233 | /* | |
5234 | * We get this for NOP only, but pause | |
5235 | * is rep not, check this here | |
5236 | */ | |
5237 | if (info->rep_prefix != REPE_PREFIX) | |
5238 | goto out; | |
f6511935 JR |
5239 | case SVM_EXIT_IOIO: { |
5240 | u64 exit_info; | |
5241 | u32 bytes; | |
5242 | ||
f6511935 JR |
5243 | if (info->intercept == x86_intercept_in || |
5244 | info->intercept == x86_intercept_ins) { | |
6cbc5f5a JK |
5245 | exit_info = ((info->src_val & 0xffff) << 16) | |
5246 | SVM_IOIO_TYPE_MASK; | |
f6511935 | 5247 | bytes = info->dst_bytes; |
6493f157 | 5248 | } else { |
6cbc5f5a | 5249 | exit_info = (info->dst_val & 0xffff) << 16; |
6493f157 | 5250 | bytes = info->src_bytes; |
f6511935 JR |
5251 | } |
5252 | ||
5253 | if (info->intercept == x86_intercept_outs || | |
5254 | info->intercept == x86_intercept_ins) | |
5255 | exit_info |= SVM_IOIO_STR_MASK; | |
5256 | ||
5257 | if (info->rep_prefix) | |
5258 | exit_info |= SVM_IOIO_REP_MASK; | |
5259 | ||
5260 | bytes = min(bytes, 4u); | |
5261 | ||
5262 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
5263 | ||
5264 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
5265 | ||
5266 | vmcb->control.exit_info_1 = exit_info; | |
5267 | vmcb->control.exit_info_2 = info->next_rip; | |
5268 | ||
5269 | break; | |
5270 | } | |
cfec82cb JR |
5271 | default: |
5272 | break; | |
5273 | } | |
5274 | ||
f104765b BD |
5275 | /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ |
5276 | if (static_cpu_has(X86_FEATURE_NRIPS)) | |
5277 | vmcb->control.next_rip = info->next_rip; | |
cfec82cb JR |
5278 | vmcb->control.exit_code = icpt_info.exit_code; |
5279 | vmexit = nested_svm_exit_handled(svm); | |
5280 | ||
5281 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
5282 | : X86EMUL_CONTINUE; | |
5283 | ||
5284 | out: | |
5285 | return ret; | |
8a76d7f2 JR |
5286 | } |
5287 | ||
a547c6db YZ |
5288 | static void svm_handle_external_intr(struct kvm_vcpu *vcpu) |
5289 | { | |
5290 | local_irq_enable(); | |
f2485b3e PB |
5291 | /* |
5292 | * We must have an instruction with interrupts enabled, so | |
5293 | * the timer interrupt isn't delayed by the interrupt shadow. | |
5294 | */ | |
5295 | asm("nop"); | |
5296 | local_irq_disable(); | |
a547c6db YZ |
5297 | } |
5298 | ||
ae97a3b8 RK |
5299 | static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) |
5300 | { | |
5301 | } | |
5302 | ||
be8ca170 SS |
5303 | static inline void avic_post_state_restore(struct kvm_vcpu *vcpu) |
5304 | { | |
5305 | if (avic_handle_apic_id_update(vcpu) != 0) | |
5306 | return; | |
5307 | if (avic_handle_dfr_update(vcpu) != 0) | |
5308 | return; | |
5309 | avic_handle_ldr_update(vcpu); | |
5310 | } | |
5311 | ||
74f16909 BP |
5312 | static void svm_setup_mce(struct kvm_vcpu *vcpu) |
5313 | { | |
5314 | /* [63:9] are reserved. */ | |
5315 | vcpu->arch.mcg_cap &= 0x1ff; | |
5316 | } | |
5317 | ||
404f6aac | 5318 | static struct kvm_x86_ops svm_x86_ops __ro_after_init = { |
6aa8b732 AK |
5319 | .cpu_has_kvm_support = has_svm, |
5320 | .disabled_by_bios = is_disabled, | |
5321 | .hardware_setup = svm_hardware_setup, | |
5322 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 5323 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
5324 | .hardware_enable = svm_hardware_enable, |
5325 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 5326 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6d396b55 | 5327 | .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase, |
6aa8b732 AK |
5328 | |
5329 | .vcpu_create = svm_create_vcpu, | |
5330 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 5331 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 5332 | |
44a95dae SS |
5333 | .vm_init = avic_vm_init, |
5334 | .vm_destroy = avic_vm_destroy, | |
5335 | ||
04d2cc77 | 5336 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
5337 | .vcpu_load = svm_vcpu_load, |
5338 | .vcpu_put = svm_vcpu_put, | |
8221c137 SS |
5339 | .vcpu_blocking = svm_vcpu_blocking, |
5340 | .vcpu_unblocking = svm_vcpu_unblocking, | |
6aa8b732 | 5341 | |
a96036b8 | 5342 | .update_bp_intercept = update_bp_intercept, |
6aa8b732 AK |
5343 | .get_msr = svm_get_msr, |
5344 | .set_msr = svm_set_msr, | |
5345 | .get_segment_base = svm_get_segment_base, | |
5346 | .get_segment = svm_get_segment, | |
5347 | .set_segment = svm_set_segment, | |
2e4d2653 | 5348 | .get_cpl = svm_get_cpl, |
1747fb71 | 5349 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 5350 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 5351 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 5352 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 5353 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
5354 | .set_cr3 = svm_set_cr3, |
5355 | .set_cr4 = svm_set_cr4, | |
5356 | .set_efer = svm_set_efer, | |
5357 | .get_idt = svm_get_idt, | |
5358 | .set_idt = svm_set_idt, | |
5359 | .get_gdt = svm_get_gdt, | |
5360 | .set_gdt = svm_set_gdt, | |
73aaf249 JK |
5361 | .get_dr6 = svm_get_dr6, |
5362 | .set_dr6 = svm_set_dr6, | |
020df079 | 5363 | .set_dr7 = svm_set_dr7, |
facb0139 | 5364 | .sync_dirty_debug_regs = svm_sync_dirty_debug_regs, |
6de4f3ad | 5365 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
5366 | .get_rflags = svm_get_rflags, |
5367 | .set_rflags = svm_set_rflags, | |
be94f6b7 HH |
5368 | |
5369 | .get_pkru = svm_get_pkru, | |
5370 | ||
6aa8b732 | 5371 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 5372 | |
6aa8b732 | 5373 | .run = svm_vcpu_run, |
04d2cc77 | 5374 | .handle_exit = handle_exit, |
6aa8b732 | 5375 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
5376 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
5377 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 5378 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 5379 | .set_irq = svm_set_irq, |
95ba8273 | 5380 | .set_nmi = svm_inject_nmi, |
298101da | 5381 | .queue_exception = svm_queue_exception, |
b463a6f7 | 5382 | .cancel_injection = svm_cancel_injection, |
78646121 | 5383 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 5384 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
5385 | .get_nmi_mask = svm_get_nmi_mask, |
5386 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
5387 | .enable_nmi_window = enable_nmi_window, |
5388 | .enable_irq_window = enable_irq_window, | |
5389 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 5390 | .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode, |
d62caabb AS |
5391 | .get_enable_apicv = svm_get_enable_apicv, |
5392 | .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl, | |
c7c9c56c | 5393 | .load_eoi_exitmap = svm_load_eoi_exitmap, |
44a95dae SS |
5394 | .hwapic_irr_update = svm_hwapic_irr_update, |
5395 | .hwapic_isr_update = svm_hwapic_isr_update, | |
be8ca170 | 5396 | .apicv_post_state_restore = avic_post_state_restore, |
cbc94022 IE |
5397 | |
5398 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 5399 | .get_tdp_level = get_npt_level, |
4b12f0de | 5400 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 5401 | |
586f9607 | 5402 | .get_exit_info = svm_get_exit_info, |
586f9607 | 5403 | |
17cc3935 | 5404 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
5405 | |
5406 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
5407 | |
5408 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 5409 | .invpcid_supported = svm_invpcid_supported, |
93c4adc7 | 5410 | .mpx_supported = svm_mpx_supported, |
55412b2e | 5411 | .xsaves_supported = svm_xsaves_supported, |
d4330ef2 JR |
5412 | |
5413 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
5414 | |
5415 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a ZA |
5416 | |
5417 | .write_tsc_offset = svm_write_tsc_offset, | |
1c97f0a0 JR |
5418 | |
5419 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
5420 | |
5421 | .check_intercept = svm_check_intercept, | |
a547c6db | 5422 | .handle_external_intr = svm_handle_external_intr, |
ae97a3b8 RK |
5423 | |
5424 | .sched_in = svm_sched_in, | |
25462f7f WH |
5425 | |
5426 | .pmu_ops = &amd_pmu_ops, | |
340d3bc3 | 5427 | .deliver_posted_interrupt = svm_deliver_avic_intr, |
411b44ba | 5428 | .update_pi_irte = svm_update_pi_irte, |
74f16909 | 5429 | .setup_mce = svm_setup_mce, |
6aa8b732 AK |
5430 | }; |
5431 | ||
5432 | static int __init svm_init(void) | |
5433 | { | |
cb498ea2 | 5434 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 5435 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
5436 | } |
5437 | ||
5438 | static void __exit svm_exit(void) | |
5439 | { | |
cb498ea2 | 5440 | kvm_exit(); |
6aa8b732 AK |
5441 | } |
5442 | ||
5443 | module_init(svm_init) | |
5444 | module_exit(svm_exit) |