]> git.proxmox.com Git - mirror_qemu.git/blame - target-i386/cpu.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-i386: Don't declare variables in the middle of blocks
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf
EH		 26#include "sysemu/cpus.h"
27#include "topology.h"
c6dc6f63 28
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
53a89e26 44#include "hw/qdev-properties.h"
62fc403f 45#include "hw/cpu/icc_bus.h"
bdeec802 46#ifndef CONFIG_USER_ONLY
0d09e41a 47#include "hw/xen/xen.h"
0d09e41a 48#include "hw/i386/apic_internal.h"
bdeec802
IM		 49#endif
50
5e891bf8
EH		 51
52/* Cache topology CPUID constants: */
53
54/* CPUID Leaf 2 Descriptors */
55
56#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57#define CPUID_2_L1I_32KB_8WAY_64B 0x30
58#define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61/* CPUID Leaf 4 constants: */
62
63/* EAX: */
64#define CPUID_4_TYPE_DCACHE 1
65#define CPUID_4_TYPE_ICACHE 2
66#define CPUID_4_TYPE_UNIFIED 3
67
68#define CPUID_4_LEVEL(l) ((l) << 5)
69
70#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71#define CPUID_4_FULLY_ASSOC (1 << 9)
72
73/* EDX: */
74#define CPUID_4_NO_INVD_SHARING (1 << 0)
75#define CPUID_4_INCLUSIVE (1 << 1)
76#define CPUID_4_COMPLEX_IDX (1 << 2)
77
78#define ASSOC_FULL 0xFF
79
80/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95/* Definitions of the hardcoded cache entries we expose: */
96
97/* L1 data cache: */
98#define L1D_LINE_SIZE 64
99#define L1D_ASSOCIATIVITY 8
100#define L1D_SETS 64
101#define L1D_PARTITIONS 1
102/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105#define L1D_LINES_PER_TAG 1
106#define L1D_SIZE_KB_AMD 64
107#define L1D_ASSOCIATIVITY_AMD 2
108
109/* L1 instruction cache: */
110#define L1I_LINE_SIZE 64
111#define L1I_ASSOCIATIVITY 8
112#define L1I_SETS 64
113#define L1I_PARTITIONS 1
114/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117#define L1I_LINES_PER_TAG 1
118#define L1I_SIZE_KB_AMD 64
119#define L1I_ASSOCIATIVITY_AMD 2
120
121/* Level 2 unified cache: */
122#define L2_LINE_SIZE 64
123#define L2_ASSOCIATIVITY 16
124#define L2_SETS 4096
125#define L2_PARTITIONS 1
126/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130#define L2_LINES_PER_TAG 1
131#define L2_SIZE_KB_AMD 512
132
133/* No L3 cache: */
134#define L3_SIZE_KB 0 /* disabled */
135#define L3_ASSOCIATIVITY 0 /* disabled */
136#define L3_LINES_PER_TAG 0 /* disabled */
137#define L3_LINE_SIZE 0 /* disabled */
138
139/* TLB definitions: */
140
141#define L1_DTLB_2M_ASSOC 1
142#define L1_DTLB_2M_ENTRIES 255
143#define L1_DTLB_4K_ASSOC 1
144#define L1_DTLB_4K_ENTRIES 255
145
146#define L1_ITLB_2M_ASSOC 1
147#define L1_ITLB_2M_ENTRIES 255
148#define L1_ITLB_4K_ASSOC 1
149#define L1_ITLB_4K_ENTRIES 255
150
151#define L2_DTLB_2M_ASSOC 0 /* disabled */
152#define L2_DTLB_2M_ENTRIES 0 /* disabled */
153#define L2_DTLB_4K_ASSOC 4
154#define L2_DTLB_4K_ENTRIES 512
155
156#define L2_ITLB_2M_ASSOC 0 /* disabled */
157#define L2_ITLB_2M_ENTRIES 0 /* disabled */
158#define L2_ITLB_4K_ASSOC 4
159#define L2_ITLB_4K_ENTRIES 512
160
161
162
99b88a17
IM		 163static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165{
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173}
174
c6dc6f63
AP		 175/* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188};
189static const char *ext_feature_name[] = {
f370be3c 190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 191 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 192 "tm2", "ssse3", "cid", NULL,
e117f772 193 "fma", "cx16", "xtpr", "pdcm",
434acb81 194 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 196 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 197 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 198};
3b671a40
EH		 199/* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
c6dc6f63 204static const char *ext2_feature_name[] = {
3b671a40
EH		 205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 212 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 213};
214static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 217 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 222 NULL, NULL, NULL, NULL,
223};
224
89e49c8b
EH		 225static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234};
235
c6dc6f63 236static const char *kvm_feature_name[] = {
c3d39807 237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 245};
246
296acb64
JR		 247static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256};
257
a9321a4d 258static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263};
264
5ef57876
EH		 265typedef struct FeatureWordInfo {
266 const char **feat_names;
04d104b6
EH		 267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
5ef57876
EH		 271} FeatureWordInfo;
272
273static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
89e49c8b
EH		 290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
bffd67b0
EH		 294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
bffd67b0 307 },
5ef57876
EH		 308};
309
8e8aba50
EH		 310typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315} X86RegisterInfo32;
316
317#define REGISTER(reg) \
5d371f41 318 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
8e8aba50
EH		 319X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328};
329#undef REGISTER
330
2560f19f
PB		 331typedef struct ExtSaveArea {
332 uint32_t feature, bits;
333 uint32_t offset, size;
334} ExtSaveArea;
335
336static const ExtSaveArea ext_save_areas[] = {
337 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 338 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 339 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
340 .offset = 0x3c0, .size = 0x40 },
341 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 342 .offset = 0x400, .size = 0x40 },
2560f19f 343};
8e8aba50 344
8b4beddc
EH		 345const char *get_register_name_32(unsigned int reg)
346{
31ccdde2 347 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 348 return NULL;
349 }
8e8aba50 350 return x86_reg_info_32[reg].name;
8b4beddc
EH		 351}
352
c6dc6f63
AP		 353/* collects per-function cpuid data
354 */
355typedef struct model_features_t {
356 uint32_t *guest_feat;
357 uint32_t *host_feat;
bffd67b0 358 FeatureWord feat_word;
8b4beddc 359} model_features_t;
c6dc6f63 360
dc59944b
MT		 361static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
362 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 363 (1 << KVM_FEATURE_CLOCKSOURCE2) |
364 (1 << KVM_FEATURE_ASYNC_PF) |
365 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 366 (1 << KVM_FEATURE_PV_EOI) |
dc59944b 367 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
dc59944b 368
29694758 369void disable_kvm_pv_eoi(void)
dc59944b 370{
29694758 371 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
dc59944b
MT		 372}
373
bb44e0d1
JK		 374void host_cpuid(uint32_t function, uint32_t count,
375 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 376{
a1fd24af
AL		 377 uint32_t vec[4];
378
379#ifdef __x86_64__
380 asm volatile("cpuid"
381 : "=a"(vec[0]), "=b"(vec[1]),
382 "=c"(vec[2]), "=d"(vec[3])
383 : "0"(function), "c"(count) : "cc");
c1f41226 384#elif defined(__i386__)
a1fd24af
AL		 385 asm volatile("pusha \n\t"
386 "cpuid \n\t"
387 "mov %%eax, 0(%2) \n\t"
388 "mov %%ebx, 4(%2) \n\t"
389 "mov %%ecx, 8(%2) \n\t"
390 "mov %%edx, 12(%2) \n\t"
391 "popa"
392 : : "a"(function), "c"(count), "S"(vec)
393 : "memory", "cc");
c1f41226
EH		 394#else
395 abort();
a1fd24af
AL		 396#endif
397
bdde476a 398 if (eax)
a1fd24af 399 *eax = vec[0];
bdde476a 400 if (ebx)
a1fd24af 401 *ebx = vec[1];
bdde476a 402 if (ecx)
a1fd24af 403 *ecx = vec[2];
bdde476a 404 if (edx)
a1fd24af 405 *edx = vec[3];
bdde476a 406}
c6dc6f63
AP		 407
408#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
409
410/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
411 * a substring. ex if !NULL points to the first char after a substring,
412 * otherwise the string is assumed to sized by a terminating nul.
413 * Return lexical ordering of *s1:*s2.
414 */
415static int sstrcmp(const char *s1, const char *e1, const char *s2,
416 const char *e2)
417{
418 for (;;) {
419 if (!*s1 || !*s2 || *s1 != *s2)
420 return (*s1 - *s2);
421 ++s1, ++s2;
422 if (s1 == e1 && s2 == e2)
423 return (0);
424 else if (s1 == e1)
425 return (*s2);
426 else if (s2 == e2)
427 return (*s1);
428 }
429}
430
431/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
432 * '|' delimited (possibly empty) strings in which case search for a match
433 * within the alternatives proceeds left to right. Return 0 for success,
434 * non-zero otherwise.
435 */
436static int altcmp(const char *s, const char *e, const char *altstr)
437{
438 const char *p, *q;
439
440 for (q = p = altstr; ; ) {
441 while (*p && *p != '|')
442 ++p;
443 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
444 return (0);
445 if (!*p)
446 return (1);
447 else
448 q = ++p;
449 }
450}
451
452/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 453 * *pval and return true, otherwise return false
c6dc6f63 454 */
e41e0fc6
JK		 455static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
456 const char **featureset)
c6dc6f63
AP		 457{
458 uint32_t mask;
459 const char **ppc;
e41e0fc6 460 bool found = false;
c6dc6f63 461
e41e0fc6 462 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 463 if (*ppc && !altcmp(s, e, *ppc)) {
464 *pval |= mask;
e41e0fc6 465 found = true;
c6dc6f63 466 }
e41e0fc6
JK		 467 }
468 return found;
c6dc6f63
AP		 469}
470
5ef57876
EH		 471static void add_flagname_to_bitmaps(const char *flagname,
472 FeatureWordArray words)
c6dc6f63 473{
5ef57876
EH		 474 FeatureWord w;
475 for (w = 0; w < FEATURE_WORDS; w++) {
476 FeatureWordInfo *wi = &feature_word_info[w];
477 if (wi->feat_names &&
478 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
479 break;
480 }
481 }
482 if (w == FEATURE_WORDS) {
483 fprintf(stderr, "CPU feature %s not found\n", flagname);
484 }
c6dc6f63
AP		 485}
486
9576de75 487typedef struct X86CPUDefinition {
c6dc6f63
AP		 488 const char *name;
489 uint32_t level;
90e4b0c3
EH		 490 uint32_t xlevel;
491 uint32_t xlevel2;
99b88a17
IM		 492 /* vendor is zero-terminated, 12 character ASCII string */
493 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 494 int family;
495 int model;
496 int stepping;
0514ef2f 497 FeatureWordArray features;
c6dc6f63 498 char model_id[48];
787aaf57 499 bool cache_info_passthrough;
9576de75 500} X86CPUDefinition;
c6dc6f63
AP		 501
502#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
503#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
504 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
505#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
506 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
507 CPUID_PSE36 | CPUID_FXSR)
508#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
509#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
510 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
511 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
512 CPUID_PAE | CPUID_SEP | CPUID_APIC)
513
551a2dec
AP		 514#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
515 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
516 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
517 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
518 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 519 /* partly implemented:
520 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
521 CPUID_PSE36 (needed for Solaris) */
522 /* missing:
523 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
e71827bc
AJ		 524#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
525 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
526 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
d640045a 527 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
8560efed 528 /* missing:
e71827bc
AJ		 529 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
530 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
531 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
d640045a
AJ		 532 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
533 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
83f7dc28 534 CPUID_EXT_RDRAND */
60032ac0 535#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 536 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
537 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 538 /* missing:
539 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 540#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
541 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 542#define TCG_SVM_FEATURES 0
7073fbad 543#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
cd7f97ca 544 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
111994ee 545 /* missing:
7073fbad
RH		 546 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
547 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
cd7f97ca 548 CPUID_7_0_EBX_RDSEED */
551a2dec 549
7fc9b714 550/* built-in CPU model definitions
c6dc6f63 551 */
9576de75 552static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 553 {
554 .name = "qemu64",
555 .level = 4,
99b88a17 556 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 557 .family = 6,
f8e6a11a 558 .model = 6,
c6dc6f63 559 .stepping = 3,
0514ef2f 560 .features[FEAT_1_EDX] =
27861ecc 561 PPRO_FEATURES |
c6dc6f63 562 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 563 CPUID_PSE36,
0514ef2f 564 .features[FEAT_1_ECX] =
27861ecc 565 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 566 .features[FEAT_8000_0001_EDX] =
27861ecc 567 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 568 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 569 .features[FEAT_8000_0001_ECX] =
27861ecc 570 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 571 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
572 .xlevel = 0x8000000A,
c6dc6f63
AP		 573 },
574 {
575 .name = "phenom",
576 .level = 5,
99b88a17 577 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 578 .family = 16,
579 .model = 2,
580 .stepping = 3,
0514ef2f 581 .features[FEAT_1_EDX] =
27861ecc 582 PPRO_FEATURES |
c6dc6f63 583 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 584 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 585 .features[FEAT_1_ECX] =
27861ecc 586 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 587 CPUID_EXT_POPCNT,
0514ef2f 588 .features[FEAT_8000_0001_EDX] =
27861ecc 589 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 590 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
591 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 592 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 593 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
594 CPUID_EXT3_CR8LEG,
595 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
596 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 597 .features[FEAT_8000_0001_ECX] =
27861ecc 598 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 599 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 600 .features[FEAT_SVM] =
27861ecc 601 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 602 .xlevel = 0x8000001A,
603 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
604 },
605 {
606 .name = "core2duo",
607 .level = 10,
99b88a17 608 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 609 .family = 6,
610 .model = 15,
611 .stepping = 11,
0514ef2f 612 .features[FEAT_1_EDX] =
27861ecc 613 PPRO_FEATURES |
c6dc6f63 614 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 615 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
616 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 617 .features[FEAT_1_ECX] =
27861ecc 618 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 619 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
620 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 621 .features[FEAT_8000_0001_EDX] =
27861ecc 622 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 623 .features[FEAT_8000_0001_ECX] =
27861ecc 624 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 625 .xlevel = 0x80000008,
626 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
627 },
628 {
629 .name = "kvm64",
630 .level = 5,
99b88a17 631 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 632 .family = 15,
633 .model = 6,
634 .stepping = 1,
635 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 636 .features[FEAT_1_EDX] =
27861ecc 637 PPRO_FEATURES |
c6dc6f63
AP		 638 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
639 CPUID_PSE36,
640 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 641 .features[FEAT_1_ECX] =
27861ecc 642 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 643 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 644 .features[FEAT_8000_0001_EDX] =
27861ecc 645 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 646 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
647 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
648 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
649 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
650 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 651 .features[FEAT_8000_0001_ECX] =
27861ecc 652 0,
c6dc6f63
AP		 653 .xlevel = 0x80000008,
654 .model_id = "Common KVM processor"
655 },
c6dc6f63
AP		 656 {
657 .name = "qemu32",
658 .level = 4,
99b88a17 659 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 660 .family = 6,
f8e6a11a 661 .model = 6,
c6dc6f63 662 .stepping = 3,
0514ef2f 663 .features[FEAT_1_EDX] =
27861ecc 664 PPRO_FEATURES,
0514ef2f 665 .features[FEAT_1_ECX] =
27861ecc 666 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 667 .xlevel = 0x80000004,
c6dc6f63 668 },
eafaf1e5
AP		 669 {
670 .name = "kvm32",
671 .level = 5,
99b88a17 672 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 673 .family = 15,
674 .model = 6,
675 .stepping = 1,
0514ef2f 676 .features[FEAT_1_EDX] =
27861ecc 677 PPRO_FEATURES |
eafaf1e5 678 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 679 .features[FEAT_1_ECX] =
27861ecc 680 CPUID_EXT_SSE3,
0514ef2f 681 .features[FEAT_8000_0001_EDX] =
27861ecc 682 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 683 .features[FEAT_8000_0001_ECX] =
27861ecc 684 0,
eafaf1e5
AP		 685 .xlevel = 0x80000008,
686 .model_id = "Common 32-bit KVM processor"
687 },
c6dc6f63
AP		 688 {
689 .name = "coreduo",
690 .level = 10,
99b88a17 691 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 692 .family = 6,
693 .model = 14,
694 .stepping = 8,
0514ef2f 695 .features[FEAT_1_EDX] =
27861ecc 696 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 697 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
698 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 699 .features[FEAT_1_ECX] =
27861ecc 700 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 701 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 702 .features[FEAT_8000_0001_EDX] =
27861ecc 703 CPUID_EXT2_NX,
c6dc6f63
AP		 704 .xlevel = 0x80000008,
705 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
706 },
707 {
708 .name = "486",
58012d66 709 .level = 1,
99b88a17 710 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 711 .family = 4,
b2a856d9 712 .model = 8,
c6dc6f63 713 .stepping = 0,
0514ef2f 714 .features[FEAT_1_EDX] =
27861ecc 715 I486_FEATURES,
c6dc6f63
AP		 716 .xlevel = 0,
717 },
718 {
719 .name = "pentium",
720 .level = 1,
99b88a17 721 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 722 .family = 5,
723 .model = 4,
724 .stepping = 3,
0514ef2f 725 .features[FEAT_1_EDX] =
27861ecc 726 PENTIUM_FEATURES,
c6dc6f63
AP		 727 .xlevel = 0,
728 },
729 {
730 .name = "pentium2",
731 .level = 2,
99b88a17 732 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 733 .family = 6,
734 .model = 5,
735 .stepping = 2,
0514ef2f 736 .features[FEAT_1_EDX] =
27861ecc 737 PENTIUM2_FEATURES,
c6dc6f63
AP		 738 .xlevel = 0,
739 },
740 {
741 .name = "pentium3",
742 .level = 2,
99b88a17 743 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 744 .family = 6,
745 .model = 7,
746 .stepping = 3,
0514ef2f 747 .features[FEAT_1_EDX] =
27861ecc 748 PENTIUM3_FEATURES,
c6dc6f63
AP		 749 .xlevel = 0,
750 },
751 {
752 .name = "athlon",
753 .level = 2,
99b88a17 754 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 755 .family = 6,
756 .model = 2,
757 .stepping = 3,
0514ef2f 758 .features[FEAT_1_EDX] =
27861ecc 759 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 760 CPUID_MCA,
0514ef2f 761 .features[FEAT_8000_0001_EDX] =
27861ecc 762 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 763 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 764 .xlevel = 0x80000008,
c6dc6f63
AP		 765 },
766 {
767 .name = "n270",
768 /* original is on level 10 */
769 .level = 5,
99b88a17 770 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 771 .family = 6,
772 .model = 28,
773 .stepping = 2,
0514ef2f 774 .features[FEAT_1_EDX] =
27861ecc 775 PPRO_FEATURES |
8560efed
AJ		 776 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
777 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 778 /* Some CPUs got no CPUID_SEP */
0514ef2f 779 .features[FEAT_1_ECX] =
27861ecc 780 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 781 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
782 CPUID_EXT_MOVBE,
0514ef2f 783 .features[FEAT_8000_0001_EDX] =
27861ecc 784 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 785 CPUID_EXT2_NX,
0514ef2f 786 .features[FEAT_8000_0001_ECX] =
27861ecc 787 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 788 .xlevel = 0x8000000A,
789 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
790 },
3eca4642
EH		 791 {
792 .name = "Conroe",
6b11322e 793 .level = 4,
99b88a17 794 .vendor = CPUID_VENDOR_INTEL,
3eca4642 795 .family = 6,
ffce9ebb 796 .model = 15,
3eca4642 797 .stepping = 3,
0514ef2f 798 .features[FEAT_1_EDX] =
27861ecc 799 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 800 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
801 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
802 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
803 CPUID_DE | CPUID_FP87,
0514ef2f 804 .features[FEAT_1_ECX] =
27861ecc 805 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 806 .features[FEAT_8000_0001_EDX] =
27861ecc 807 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 808 .features[FEAT_8000_0001_ECX] =
27861ecc 809 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 810 .xlevel = 0x8000000A,
811 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
812 },
813 {
814 .name = "Penryn",
6b11322e 815 .level = 4,
99b88a17 816 .vendor = CPUID_VENDOR_INTEL,
3eca4642 817 .family = 6,
ffce9ebb 818 .model = 23,
3eca4642 819 .stepping = 3,
0514ef2f 820 .features[FEAT_1_EDX] =
27861ecc 821 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 822 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
823 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
824 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
825 CPUID_DE | CPUID_FP87,
0514ef2f 826 .features[FEAT_1_ECX] =
27861ecc 827 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 828 CPUID_EXT_SSE3,
0514ef2f 829 .features[FEAT_8000_0001_EDX] =
27861ecc 830 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 831 .features[FEAT_8000_0001_ECX] =
27861ecc 832 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 833 .xlevel = 0x8000000A,
834 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
835 },
836 {
837 .name = "Nehalem",
6b11322e 838 .level = 4,
99b88a17 839 .vendor = CPUID_VENDOR_INTEL,
3eca4642 840 .family = 6,
ffce9ebb 841 .model = 26,
3eca4642 842 .stepping = 3,
0514ef2f 843 .features[FEAT_1_EDX] =
27861ecc 844 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 845 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
846 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
847 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
848 CPUID_DE | CPUID_FP87,
0514ef2f 849 .features[FEAT_1_ECX] =
27861ecc 850 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 851 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 852 .features[FEAT_8000_0001_EDX] =
27861ecc 853 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 854 .features[FEAT_8000_0001_ECX] =
27861ecc 855 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 856 .xlevel = 0x8000000A,
857 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
858 },
859 {
860 .name = "Westmere",
861 .level = 11,
99b88a17 862 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 863 .family = 6,
864 .model = 44,
865 .stepping = 1,
0514ef2f 866 .features[FEAT_1_EDX] =
27861ecc 867 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 868 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
869 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
870 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
871 CPUID_DE | CPUID_FP87,
0514ef2f 872 .features[FEAT_1_ECX] =
27861ecc 873 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 874 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 875 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 876 .features[FEAT_8000_0001_EDX] =
27861ecc 877 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 878 .features[FEAT_8000_0001_ECX] =
27861ecc 879 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 880 .xlevel = 0x8000000A,
881 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
882 },
883 {
884 .name = "SandyBridge",
885 .level = 0xd,
99b88a17 886 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 887 .family = 6,
888 .model = 42,
889 .stepping = 1,
0514ef2f 890 .features[FEAT_1_EDX] =
27861ecc 891 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 892 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
893 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
894 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
895 CPUID_DE | CPUID_FP87,
0514ef2f 896 .features[FEAT_1_ECX] =
27861ecc 897 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 898 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
899 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
900 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
901 CPUID_EXT_SSE3,
0514ef2f 902 .features[FEAT_8000_0001_EDX] =
27861ecc 903 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 904 CPUID_EXT2_SYSCALL,
0514ef2f 905 .features[FEAT_8000_0001_ECX] =
27861ecc 906 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 907 .xlevel = 0x8000000A,
908 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
909 },
37507094
EH		 910 {
911 .name = "Haswell",
912 .level = 0xd,
99b88a17 913 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 914 .family = 6,
915 .model = 60,
916 .stepping = 1,
0514ef2f 917 .features[FEAT_1_EDX] =
27861ecc 918 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 919 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 920 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 921 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
922 CPUID_DE | CPUID_FP87,
0514ef2f 923 .features[FEAT_1_ECX] =
27861ecc 924 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH		 925 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
926 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
927 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
928 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
929 CPUID_EXT_PCID,
0514ef2f 930 .features[FEAT_8000_0001_EDX] =
27861ecc 931 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 932 CPUID_EXT2_SYSCALL,
0514ef2f 933 .features[FEAT_8000_0001_ECX] =
27861ecc 934 CPUID_EXT3_LAHF_LM,
0514ef2f 935 .features[FEAT_7_0_EBX] =
27861ecc 936 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 937 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
938 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
939 CPUID_7_0_EBX_RTM,
940 .xlevel = 0x8000000A,
941 .model_id = "Intel Core Processor (Haswell)",
942 },
3eca4642
EH		 943 {
944 .name = "Opteron_G1",
945 .level = 5,
99b88a17 946 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 947 .family = 15,
948 .model = 6,
949 .stepping = 1,
0514ef2f 950 .features[FEAT_1_EDX] =
27861ecc 951 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 952 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
953 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
954 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
955 CPUID_DE | CPUID_FP87,
0514ef2f 956 .features[FEAT_1_ECX] =
27861ecc 957 CPUID_EXT_SSE3,
0514ef2f 958 .features[FEAT_8000_0001_EDX] =
27861ecc 959 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH		 960 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
961 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
962 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
963 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
964 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
965 .xlevel = 0x80000008,
966 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
967 },
968 {
969 .name = "Opteron_G2",
970 .level = 5,
99b88a17 971 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 972 .family = 15,
973 .model = 6,
974 .stepping = 1,
0514ef2f 975 .features[FEAT_1_EDX] =
27861ecc 976 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 977 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
978 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
979 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
980 CPUID_DE | CPUID_FP87,
0514ef2f 981 .features[FEAT_1_ECX] =
27861ecc 982 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 983 .features[FEAT_8000_0001_EDX] =
27861ecc 984 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 985 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
986 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
987 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
988 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
989 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
990 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 991 .features[FEAT_8000_0001_ECX] =
27861ecc 992 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 993 .xlevel = 0x80000008,
994 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
995 },
996 {
997 .name = "Opteron_G3",
998 .level = 5,
99b88a17 999 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1000 .family = 15,
1001 .model = 6,
1002 .stepping = 1,
0514ef2f 1003 .features[FEAT_1_EDX] =
27861ecc 1004 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1005 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1006 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1007 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1008 CPUID_DE | CPUID_FP87,
0514ef2f 1009 .features[FEAT_1_ECX] =
27861ecc 1010 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1011 CPUID_EXT_SSE3,
0514ef2f 1012 .features[FEAT_8000_0001_EDX] =
27861ecc 1013 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1014 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1015 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1016 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1017 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1018 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1019 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1020 .features[FEAT_8000_0001_ECX] =
27861ecc 1021 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH		 1022 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1023 .xlevel = 0x80000008,
1024 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1025 },
1026 {
1027 .name = "Opteron_G4",
1028 .level = 0xd,
99b88a17 1029 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1030 .family = 21,
1031 .model = 1,
1032 .stepping = 2,
0514ef2f 1033 .features[FEAT_1_EDX] =
27861ecc 1034 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1035 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1036 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1037 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1038 CPUID_DE | CPUID_FP87,
0514ef2f 1039 .features[FEAT_1_ECX] =
27861ecc 1040 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 1041 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1042 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1043 CPUID_EXT_SSE3,
0514ef2f 1044 .features[FEAT_8000_0001_EDX] =
27861ecc 1045 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH		 1046 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1047 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1048 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1049 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1050 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1051 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1052 .features[FEAT_8000_0001_ECX] =
27861ecc 1053 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH		 1054 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1055 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1056 CPUID_EXT3_LAHF_LM,
1057 .xlevel = 0x8000001A,
1058 .model_id = "AMD Opteron 62xx class CPU",
1059 },
021941b9
AP		 1060 {
1061 .name = "Opteron_G5",
1062 .level = 0xd,
99b88a17 1063 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1064 .family = 21,
1065 .model = 2,
1066 .stepping = 0,
0514ef2f 1067 .features[FEAT_1_EDX] =
27861ecc 1068 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP		 1069 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1070 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1071 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1072 CPUID_DE | CPUID_FP87,
0514ef2f 1073 .features[FEAT_1_ECX] =
27861ecc 1074 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP		 1075 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1076 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1077 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1078 .features[FEAT_8000_0001_EDX] =
27861ecc 1079 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP		 1080 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1081 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1082 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1083 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1084 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1085 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1086 .features[FEAT_8000_0001_ECX] =
27861ecc 1087 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP		 1088 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1089 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1090 CPUID_EXT3_LAHF_LM,
1091 .xlevel = 0x8000001A,
1092 .model_id = "AMD Opteron 63xx class CPU",
1093 },
c6dc6f63
AP		 1094};
1095
0668af54
EH		 1096/**
1097 * x86_cpu_compat_set_features:
1098 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1099 * @w: Identifies the feature word to be changed.
1100 * @feat_add: Feature bits to be added to feature word
1101 * @feat_remove: Feature bits to be removed from feature word
1102 *
1103 * Change CPU model feature bits for compatibility.
1104 *
1105 * This function may be used by machine-type compatibility functions
1106 * to enable or disable feature bits on specific CPU models.
1107 */
1108void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1109 uint32_t feat_add, uint32_t feat_remove)
1110{
9576de75 1111 X86CPUDefinition *def;
0668af54
EH		 1112 int i;
1113 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1114 def = &builtin_x86_defs[i];
1115 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1116 def->features[w] |= feat_add;
1117 def->features[w] &= ~feat_remove;
1118 }
1119 }
1120}
1121
c6dc6f63
AP		 1122static int cpu_x86_fill_model_id(char *str)
1123{
1124 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1125 int i;
1126
1127 for (i = 0; i < 3; i++) {
1128 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1129 memcpy(str + i * 16 + 0, &eax, 4);
1130 memcpy(str + i * 16 + 4, &ebx, 4);
1131 memcpy(str + i * 16 + 8, &ecx, 4);
1132 memcpy(str + i * 16 + 12, &edx, 4);
1133 }
1134 return 0;
1135}
1136
9576de75 1137/* Fill a X86CPUDefinition struct with information about the host CPU, and
6e746f30
EH		 1138 * the CPU features supported by the host hardware + host kernel
1139 *
1140 * This function may be called only if KVM is enabled.
1141 */
9576de75 1142static void kvm_cpu_fill_host(X86CPUDefinition *x86_cpu_def)
c6dc6f63 1143{
12869995 1144 KVMState *s = kvm_state;
c6dc6f63 1145 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
74f54bc4 1146 FeatureWord w;
c6dc6f63 1147
6e746f30
EH		 1148 assert(kvm_enabled());
1149
c6dc6f63 1150 x86_cpu_def->name = "host";
787aaf57 1151 x86_cpu_def->cache_info_passthrough = true;
c6dc6f63 1152 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
99b88a17 1153 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
c6dc6f63
AP		 1154
1155 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1156 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1157 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1158 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 1159
12869995 1160 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
2a573259
EH		 1161 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1162 x86_cpu_def->xlevel2 =
1163 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1164
1165 cpu_x86_fill_model_id(x86_cpu_def->model_id);
1166
2bc65d2b
EH		 1167 for (w = 0; w < FEATURE_WORDS; w++) {
1168 FeatureWordInfo *wi = &feature_word_info[w];
1169 x86_cpu_def->features[w] =
1170 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1171 wi->cpuid_reg);
1172 }
c6dc6f63
AP		 1173}
1174
bffd67b0 1175static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 1176{
1177 int i;
1178
1179 for (i = 0; i < 32; ++i)
1180 if (1 << i & mask) {
bffd67b0 1181 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1182 assert(reg);
1183 fprintf(stderr, "warning: host doesn't support requested feature: "
1184 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1185 f->cpuid_eax, reg,
1186 f->feat_names[i] ? "." : "",
1187 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 1188 break;
1189 }
1190 return 0;
1191}
1192
07ca5945
EH		 1193/* Check if all requested cpu flags are making their way to the guest
1194 *
1195 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 1196 *
1197 * This function may be called only if KVM is enabled.
c6dc6f63 1198 */
f0b9b111 1199static int kvm_check_features_against_host(KVMState *s, X86CPU *cpu)
c6dc6f63 1200{
5ec01c2e 1201 CPUX86State *env = &cpu->env;
f0b9b111
EH		 1202 int rv = 0;
1203 FeatureWord w;
c6dc6f63 1204
6e746f30
EH		 1205 assert(kvm_enabled());
1206
f0b9b111 1207 for (w = 0; w < FEATURE_WORDS; w++) {
bffd67b0 1208 FeatureWordInfo *wi = &feature_word_info[w];
f0b9b111
EH		 1209 uint32_t guest_feat = env->features[w];
1210 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1211 wi->cpuid_ecx,
1212 wi->cpuid_reg);
1213 uint32_t mask;
bffd67b0 1214 for (mask = 1; mask; mask <<= 1) {
f0b9b111 1215 if (guest_feat & mask && !(host_feat & mask)) {
bffd67b0
EH		 1216 unavailable_host_feature(wi, mask);
1217 rv = 1;
1218 }
1219 }
1220 }
c6dc6f63
AP		 1221 return rv;
1222}
1223
95b8519d
AF		 1224static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1225 const char *name, Error **errp)
1226{
1227 X86CPU *cpu = X86_CPU(obj);
1228 CPUX86State *env = &cpu->env;
1229 int64_t value;
1230
1231 value = (env->cpuid_version >> 8) & 0xf;
1232 if (value == 0xf) {
1233 value += (env->cpuid_version >> 20) & 0xff;
1234 }
1235 visit_type_int(v, &value, name, errp);
1236}
1237
71ad61d3
AF		 1238static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1239 const char *name, Error **errp)
ed5e1ec3 1240{
71ad61d3
AF		 1241 X86CPU *cpu = X86_CPU(obj);
1242 CPUX86State *env = &cpu->env;
1243 const int64_t min = 0;
1244 const int64_t max = 0xff + 0xf;
1245 int64_t value;
1246
1247 visit_type_int(v, &value, name, errp);
1248 if (error_is_set(errp)) {
1249 return;
1250 }
1251 if (value < min || value > max) {
1252 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1253 name ? name : "null", value, min, max);
1254 return;
1255 }
1256
ed5e1ec3 1257 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1258 if (value > 0x0f) {
1259 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1260 } else {
71ad61d3 1261 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1262 }
1263}
1264
67e30c83
AF		 1265static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1266 const char *name, Error **errp)
1267{
1268 X86CPU *cpu = X86_CPU(obj);
1269 CPUX86State *env = &cpu->env;
1270 int64_t value;
1271
1272 value = (env->cpuid_version >> 4) & 0xf;
1273 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1274 visit_type_int(v, &value, name, errp);
1275}
1276
c5291a4f
AF		 1277static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1278 const char *name, Error **errp)
b0704cbd 1279{
c5291a4f
AF		 1280 X86CPU *cpu = X86_CPU(obj);
1281 CPUX86State *env = &cpu->env;
1282 const int64_t min = 0;
1283 const int64_t max = 0xff;
1284 int64_t value;
1285
1286 visit_type_int(v, &value, name, errp);
1287 if (error_is_set(errp)) {
1288 return;
1289 }
1290 if (value < min || value > max) {
1291 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1292 name ? name : "null", value, min, max);
1293 return;
1294 }
1295
b0704cbd 1296 env->cpuid_version &= ~0xf00f0;
c5291a4f 1297 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1298}
1299
35112e41
AF		 1300static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1301 void *opaque, const char *name,
1302 Error **errp)
1303{
1304 X86CPU *cpu = X86_CPU(obj);
1305 CPUX86State *env = &cpu->env;
1306 int64_t value;
1307
1308 value = env->cpuid_version & 0xf;
1309 visit_type_int(v, &value, name, errp);
1310}
1311
036e2222
AF		 1312static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1313 void *opaque, const char *name,
1314 Error **errp)
38c3dc46 1315{
036e2222
AF		 1316 X86CPU *cpu = X86_CPU(obj);
1317 CPUX86State *env = &cpu->env;
1318 const int64_t min = 0;
1319 const int64_t max = 0xf;
1320 int64_t value;
1321
1322 visit_type_int(v, &value, name, errp);
1323 if (error_is_set(errp)) {
1324 return;
1325 }
1326 if (value < min || value > max) {
1327 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1328 name ? name : "null", value, min, max);
1329 return;
1330 }
1331
38c3dc46 1332 env->cpuid_version &= ~0xf;
036e2222 1333 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1334}
1335
8e1898bf
AF		 1336static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1337 const char *name, Error **errp)
1338{
1339 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1340
fa029887 1341 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1342}
1343
1344static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1345 const char *name, Error **errp)
1346{
1347 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1348
fa029887 1349 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1350}
1351
16b93aa8
AF		 1352static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1353 const char *name, Error **errp)
1354{
1355 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1356
fa029887 1357 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1358}
1359
1360static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1361 const char *name, Error **errp)
1362{
1363 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1364
fa029887 1365 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1366}
1367
d480e1af
AF		 1368static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1369{
1370 X86CPU *cpu = X86_CPU(obj);
1371 CPUX86State *env = &cpu->env;
1372 char *value;
d480e1af 1373
9df694ee 1374 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1375 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1376 env->cpuid_vendor3);
d480e1af
AF		 1377 return value;
1378}
1379
1380static void x86_cpuid_set_vendor(Object *obj, const char *value,
1381 Error **errp)
1382{
1383 X86CPU *cpu = X86_CPU(obj);
1384 CPUX86State *env = &cpu->env;
1385 int i;
1386
9df694ee 1387 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1388 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1389 "vendor", value);
1390 return;
1391 }
1392
1393 env->cpuid_vendor1 = 0;
1394 env->cpuid_vendor2 = 0;
1395 env->cpuid_vendor3 = 0;
1396 for (i = 0; i < 4; i++) {
1397 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1398 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1399 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1400 }
d480e1af
AF		 1401}
1402
63e886eb
AF		 1403static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1404{
1405 X86CPU *cpu = X86_CPU(obj);
1406 CPUX86State *env = &cpu->env;
1407 char *value;
1408 int i;
1409
1410 value = g_malloc(48 + 1);
1411 for (i = 0; i < 48; i++) {
1412 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1413 }
1414 value[48] = '\0';
1415 return value;
1416}
1417
938d4c25
AF		 1418static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1419 Error **errp)
dcce6675 1420{
938d4c25
AF		 1421 X86CPU *cpu = X86_CPU(obj);
1422 CPUX86State *env = &cpu->env;
dcce6675
AF		 1423 int c, len, i;
1424
1425 if (model_id == NULL) {
1426 model_id = "";
1427 }
1428 len = strlen(model_id);
d0a6acf4 1429 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1430 for (i = 0; i < 48; i++) {
1431 if (i >= len) {
1432 c = '\0';
1433 } else {
1434 c = (uint8_t)model_id[i];
1435 }
1436 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1437 }
1438}
1439
89e48965
AF		 1440static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1441 const char *name, Error **errp)
1442{
1443 X86CPU *cpu = X86_CPU(obj);
1444 int64_t value;
1445
1446 value = cpu->env.tsc_khz * 1000;
1447 visit_type_int(v, &value, name, errp);
1448}
1449
1450static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1451 const char *name, Error **errp)
1452{
1453 X86CPU *cpu = X86_CPU(obj);
1454 const int64_t min = 0;
2e84849a 1455 const int64_t max = INT64_MAX;
89e48965
AF		 1456 int64_t value;
1457
1458 visit_type_int(v, &value, name, errp);
1459 if (error_is_set(errp)) {
1460 return;
1461 }
1462 if (value < min || value > max) {
1463 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1464 name ? name : "null", value, min, max);
1465 return;
1466 }
1467
1468 cpu->env.tsc_khz = value / 1000;
1469}
1470
31050930
IM		 1471static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1472 const char *name, Error **errp)
1473{
1474 X86CPU *cpu = X86_CPU(obj);
1475 int64_t value = cpu->env.cpuid_apic_id;
1476
1477 visit_type_int(v, &value, name, errp);
1478}
1479
1480static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1481 const char *name, Error **errp)
1482{
1483 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1484 DeviceState *dev = DEVICE(obj);
31050930
IM		 1485 const int64_t min = 0;
1486 const int64_t max = UINT32_MAX;
1487 Error *error = NULL;
1488 int64_t value;
1489
8d6d4980
IM		 1490 if (dev->realized) {
1491 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1492 "it was realized", name, object_get_typename(obj));
1493 return;
1494 }
1495
31050930
IM		 1496 visit_type_int(v, &value, name, &error);
1497 if (error) {
1498 error_propagate(errp, error);
1499 return;
1500 }
1501 if (value < min || value > max) {
1502 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1503 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1504 object_get_typename(obj), name, value, min, max);
1505 return;
1506 }
1507
1508 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1509 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1510 return;
1511 }
1512 cpu->env.cpuid_apic_id = value;
1513}
1514
7e5292b5 1515/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1516static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1517 const char *name, Error **errp)
1518{
7e5292b5 1519 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1520 FeatureWord w;
1521 Error *err = NULL;
1522 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1523 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1524 X86CPUFeatureWordInfoList *list = NULL;
1525
1526 for (w = 0; w < FEATURE_WORDS; w++) {
1527 FeatureWordInfo *wi = &feature_word_info[w];
1528 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1529 qwi->cpuid_input_eax = wi->cpuid_eax;
1530 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1531 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1532 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1533 qwi->features = array[w];
8e8aba50
EH		 1534
1535 /* List will be in reverse order, but order shouldn't matter */
1536 list_entries[w].next = list;
1537 list_entries[w].value = &word_infos[w];
1538 list = &list_entries[w];
1539 }
1540
1541 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1542 error_propagate(errp, err);
1543}
1544
c8f0f88e
IM		 1545static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1546 const char *name, Error **errp)
1547{
1548 X86CPU *cpu = X86_CPU(obj);
1549 int64_t value = cpu->hyperv_spinlock_attempts;
1550
1551 visit_type_int(v, &value, name, errp);
1552}
1553
1554static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1555 const char *name, Error **errp)
1556{
1557 const int64_t min = 0xFFF;
1558 const int64_t max = UINT_MAX;
1559 X86CPU *cpu = X86_CPU(obj);
1560 Error *err = NULL;
1561 int64_t value;
1562
1563 visit_type_int(v, &value, name, &err);
1564 if (err) {
1565 error_propagate(errp, err);
1566 return;
1567 }
1568
1569 if (value < min || value > max) {
1570 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1571 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1572 object_get_typename(obj), name ? name : "null",
1573 value, min, max);
1574 return;
1575 }
1576 cpu->hyperv_spinlock_attempts = value;
1577}
1578
1579static PropertyInfo qdev_prop_spinlocks = {
1580 .name = "int",
1581 .get = x86_get_hv_spinlocks,
1582 .set = x86_set_hv_spinlocks,
1583};
1584
9576de75 1585static int cpu_x86_find_by_name(X86CPU *cpu, X86CPUDefinition *x86_cpu_def,
c1399112 1586 const char *name)
c6dc6f63 1587{
9576de75 1588 X86CPUDefinition *def;
7fc9b714 1589 int i;
c6dc6f63 1590
4bfe910d
AF		 1591 if (name == NULL) {
1592 return -1;
9f3fb565 1593 }
4bfe910d 1594 if (kvm_enabled() && strcmp(name, "host") == 0) {
6e746f30 1595 kvm_cpu_fill_host(x86_cpu_def);
00b81053 1596 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
4bfe910d 1597 return 0;
c6dc6f63
AP		 1598 }
1599
7fc9b714
AF		 1600 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1601 def = &builtin_x86_defs[i];
4bfe910d
AF		 1602 if (strcmp(name, def->name) == 0) {
1603 memcpy(x86_cpu_def, def, sizeof(*def));
1604 return 0;
1605 }
1606 }
1607
1608 return -1;
8f961357
EH		 1609}
1610
72ac2e87
IM		 1611/* Convert all '_' in a feature string option name to '-', to make feature
1612 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1613 */
1614static inline void feat2prop(char *s)
1615{
1616 while ((s = strchr(s, '_'))) {
1617 *s = '-';
1618 }
1619}
1620
8f961357
EH		 1621/* Parse "+feature,-feature,feature=foo" CPU feature string
1622 */
a91987c2 1623static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
8f961357 1624{
8f961357
EH		 1625 char *featurestr; /* Single 'key=value" string being parsed */
1626 /* Features to be added */
077c68c3 1627 FeatureWordArray plus_features = { 0 };
8f961357 1628 /* Features to be removed */
5ef57876 1629 FeatureWordArray minus_features = { 0 };
8f961357 1630 uint32_t numvalue;
a91987c2 1631 CPUX86State *env = &cpu->env;
8f961357 1632
8f961357 1633 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1634
1635 while (featurestr) {
1636 char *val;
1637 if (featurestr[0] == '+') {
5ef57876 1638 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1639 } else if (featurestr[0] == '-') {
5ef57876 1640 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1641 } else if ((val = strchr(featurestr, '='))) {
1642 *val = 0; val++;
72ac2e87 1643 feat2prop(featurestr);
d024d209 1644 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1645 char *err;
a91987c2
IM		 1646 char num[32];
1647
c6dc6f63
AP		 1648 numvalue = strtoul(val, &err, 0);
1649 if (!*val || *err) {
312fd5f2 1650 error_setg(errp, "bad numerical value %s", val);
a91987c2 1651 goto out;
c6dc6f63
AP		 1652 }
1653 if (numvalue < 0x80000000) {
8ba8a698
IM		 1654 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1655 ", fixup will be removed in future versions\n");
2f7a21c4 1656 numvalue += 0x80000000;
c6dc6f63 1657 }
a91987c2
IM		 1658 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1659 object_property_parse(OBJECT(cpu), num, featurestr, errp);
72ac2e87 1660 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1661 int64_t tsc_freq;
1662 char *err;
a91987c2 1663 char num[32];
b862d1fe
JR		 1664
1665 tsc_freq = strtosz_suffix_unit(val, &err,
1666 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1667 if (tsc_freq < 0 || *err) {
312fd5f2 1668 error_setg(errp, "bad numerical value %s", val);
a91987c2 1669 goto out;
b862d1fe 1670 }
a91987c2
IM		 1671 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1672 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
72ac2e87 1673 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1674 char *err;
92067bf4 1675 const int min = 0xFFF;
c8f0f88e 1676 char num[32];
28f52cc0
VR		 1677 numvalue = strtoul(val, &err, 0);
1678 if (!*val || *err) {
312fd5f2 1679 error_setg(errp, "bad numerical value %s", val);
a91987c2 1680 goto out;
28f52cc0 1681 }
92067bf4
IM		 1682 if (numvalue < min) {
1683 fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1684 ", fixup will be removed in future versions\n",
1685 min);
1686 numvalue = min;
1687 }
c8f0f88e
IM		 1688 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1689 object_property_parse(OBJECT(cpu), num, featurestr, errp);
c6dc6f63 1690 } else {
d024d209 1691 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1692 }
c6dc6f63 1693 } else {
258f5abe
IM		 1694 feat2prop(featurestr);
1695 object_property_parse(OBJECT(cpu), "on", featurestr, errp);
a91987c2
IM		 1696 }
1697 if (error_is_set(errp)) {
1698 goto out;
c6dc6f63
AP		 1699 }
1700 featurestr = strtok(NULL, ",");
1701 }
0514ef2f
EH		 1702 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1703 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1704 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1705 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1706 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1707 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1708 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1709 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1710 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1711 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1712 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1713 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1714 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1715 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1716 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1717 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63 1718
a91987c2
IM		 1719out:
1720 return;
c6dc6f63
AP		 1721}
1722
1723/* generate a composite string into buf of all cpuid names in featureset
1724 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1725 * if flags, suppress names undefined in featureset.
1726 */
1727static void listflags(char *buf, int bufsize, uint32_t fbits,
1728 const char **featureset, uint32_t flags)
1729{
1730 const char **p = &featureset[31];
1731 char *q, *b, bit;
1732 int nc;
1733
1734 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1735 *buf = '\0';
1736 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1737 if (fbits & 1 << bit && (*p || !flags)) {
1738 if (*p)
1739 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1740 else
1741 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1742 if (bufsize <= nc) {
1743 if (b) {
1744 memcpy(b, "...", sizeof("..."));
1745 }
1746 return;
1747 }
1748 q += nc;
1749 bufsize -= nc;
1750 }
1751}
1752
e916cbf8
PM		 1753/* generate CPU information. */
1754void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1755{
9576de75 1756 X86CPUDefinition *def;
c6dc6f63 1757 char buf[256];
7fc9b714 1758 int i;
c6dc6f63 1759
7fc9b714
AF		 1760 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1761 def = &builtin_x86_defs[i];
c04321b3 1762 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1763 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1764 }
21ad7789
JK		 1765#ifdef CONFIG_KVM
1766 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1767 "KVM processor with all supported host features "
1768 "(only available in KVM mode)");
1769#endif
1770
6cdf8854 1771 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1772 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1773 FeatureWordInfo *fw = &feature_word_info[i];
1774
1775 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1776 (*cpu_fprintf)(f, " %s\n", buf);
1777 }
c6dc6f63
AP		 1778}
1779
76b64a7a 1780CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1781{
1782 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1783 X86CPUDefinition *def;
7fc9b714 1784 int i;
e3966126 1785
7fc9b714 1786 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1787 CpuDefinitionInfoList *entry;
1788 CpuDefinitionInfo *info;
1789
7fc9b714 1790 def = &builtin_x86_defs[i];
e3966126
AL		 1791 info = g_malloc0(sizeof(*info));
1792 info->name = g_strdup(def->name);
1793
1794 entry = g_malloc0(sizeof(*entry));
1795 entry->value = info;
1796 entry->next = cpu_list;
1797 cpu_list = entry;
1798 }
1799
1800 return cpu_list;
1801}
1802
bc74b7db
EH		 1803static void filter_features_for_kvm(X86CPU *cpu)
1804{
1805 CPUX86State *env = &cpu->env;
1806 KVMState *s = kvm_state;
bd87d2a2 1807 FeatureWord w;
bc74b7db 1808
bd87d2a2
EH		 1809 for (w = 0; w < FEATURE_WORDS; w++) {
1810 FeatureWordInfo *wi = &feature_word_info[w];
034acf4a
EH		 1811 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1812 wi->cpuid_ecx,
1813 wi->cpuid_reg);
1814 uint32_t requested_features = env->features[w];
1815 env->features[w] &= host_feat;
1816 cpu->filtered_features[w] = requested_features & ~env->features[w];
bd87d2a2 1817 }
bc74b7db 1818}
bc74b7db 1819
c080e30e
EH		 1820/* Load CPU definition for a given CPU model name
1821 */
1822static void x86_cpu_load_def(X86CPU *cpu, const char *name, Error **errp)
c6dc6f63 1823{
61dcd775 1824 CPUX86State *env = &cpu->env;
9576de75 1825 X86CPUDefinition def1, *def = &def1;
74f54bc4
EH		 1826 const char *vendor;
1827 char host_vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63 1828
db0ad1ba
JR		 1829 memset(def, 0, sizeof(*def));
1830
c1399112 1831 if (cpu_x86_find_by_name(cpu, def, name) < 0) {
2d64255b
AF		 1832 error_setg(errp, "Unable to find CPU definition: %s", name);
1833 return;
8f961357
EH		 1834 }
1835
2d64255b
AF		 1836 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1837 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1838 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1839 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
0514ef2f
EH		 1840 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1841 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1842 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1843 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
2d64255b 1844 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
0514ef2f
EH		 1845 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1846 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1847 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1848 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
b3baa152 1849 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1850 cpu->cache_info_passthrough = def->cache_info_passthrough;
3b671a40 1851
2d64255b 1852 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
82beb536 1853
9576de75 1854 /* Special cases not set in the X86CPUDefinition structs: */
82beb536
EH		 1855 if (kvm_enabled()) {
1856 env->features[FEAT_KVM] |= kvm_default_features;
1857 }
1858 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 1859
1860 /* sysenter isn't supported in compatibility mode on AMD,
1861 * syscall isn't supported in compatibility mode on Intel.
1862 * Normally we advertise the actual CPU vendor, but you can
1863 * override this using the 'vendor' property if you want to use
1864 * KVM's sysenter/syscall emulation in compatibility mode and
1865 * when doing cross vendor migration
1866 */
74f54bc4 1867 vendor = def->vendor;
7c08db30
EH		 1868 if (kvm_enabled()) {
1869 uint32_t ebx = 0, ecx = 0, edx = 0;
1870 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1871 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1872 vendor = host_vendor;
1873 }
1874
1875 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1876
c6dc6f63
AP		 1877}
1878
62fc403f
IM		 1879X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1880 Error **errp)
5c3c6a68 1881{
2d64255b 1882 X86CPU *cpu = NULL;
2d64255b
AF		 1883 gchar **model_pieces;
1884 char *name, *features;
ba2bc7a4 1885 char *typename;
5c3c6a68
AF		 1886 Error *error = NULL;
1887
2d64255b
AF		 1888 model_pieces = g_strsplit(cpu_model, ",", 2);
1889 if (!model_pieces[0]) {
1890 error_setg(&error, "Invalid/empty CPU model name");
1891 goto out;
1892 }
1893 name = model_pieces[0];
1894 features = model_pieces[1];
1895
5c3c6a68 1896 cpu = X86_CPU(object_new(TYPE_X86_CPU));
285f025d
EH		 1897 x86_cpu_load_def(cpu, name, &error);
1898 if (error) {
1899 goto out;
1900 }
1901
62fc403f
IM		 1902#ifndef CONFIG_USER_ONLY
1903 if (icc_bridge == NULL) {
1904 error_setg(&error, "Invalid icc-bridge value");
1905 goto out;
1906 }
1907 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1908 object_unref(OBJECT(cpu));
1909#endif
5c3c6a68 1910
ba2bc7a4
AF		 1911 /* Emulate per-model subclasses for global properties */
1912 typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1913 qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1914 g_free(typename);
1915 if (error) {
1916 goto out;
1917 }
1918
2d64255b
AF		 1919 cpu_x86_parse_featurestr(cpu, features, &error);
1920 if (error) {
1921 goto out;
5c3c6a68
AF		 1922 }
1923
7f833247 1924out:
cd7b87ff
AF		 1925 if (error != NULL) {
1926 error_propagate(errp, error);
1927 object_unref(OBJECT(cpu));
1928 cpu = NULL;
1929 }
7f833247
IM		 1930 g_strfreev(model_pieces);
1931 return cpu;
1932}
1933
1934X86CPU *cpu_x86_init(const char *cpu_model)
1935{
1936 Error *error = NULL;
1937 X86CPU *cpu;
1938
62fc403f 1939 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1940 if (error) {
2d64255b
AF		 1941 goto out;
1942 }
1943
7f833247
IM		 1944 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1945
2d64255b 1946out:
2d64255b 1947 if (error) {
4a44d85e 1948 error_report("%s", error_get_pretty(error));
5c3c6a68 1949 error_free(error);
2d64255b
AF		 1950 if (cpu != NULL) {
1951 object_unref(OBJECT(cpu));
1952 cpu = NULL;
1953 }
5c3c6a68
AF		 1954 }
1955 return cpu;
1956}
1957
c6dc6f63 1958#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1959
0e26b7b8
BS		 1960void cpu_clear_apic_feature(CPUX86State *env)
1961{
0514ef2f 1962 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 1963}
1964
c6dc6f63
AP		 1965#endif /* !CONFIG_USER_ONLY */
1966
c04321b3 1967/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1968 */
1969void x86_cpudef_setup(void)
1970{
93bfef4c
CV		 1971 int i, j;
1972 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1973
1974 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 1975 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 1976
1977 /* Look for specific "cpudef" models that */
09faecf2 1978 /* have the QEMU version in .model_id */
93bfef4c 1979 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1980 if (strcmp(model_with_versions[j], def->name) == 0) {
1981 pstrcpy(def->model_id, sizeof(def->model_id),
1982 "QEMU Virtual CPU version ");
1983 pstrcat(def->model_id, sizeof(def->model_id),
1984 qemu_get_version());
93bfef4c
CV		 1985 break;
1986 }
1987 }
c6dc6f63 1988 }
c6dc6f63
AP		 1989}
1990
c6dc6f63
AP		 1991static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1992 uint32_t *ecx, uint32_t *edx)
1993{
1994 *ebx = env->cpuid_vendor1;
1995 *edx = env->cpuid_vendor2;
1996 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 1997}
1998
1999void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2000 uint32_t *eax, uint32_t *ebx,
2001 uint32_t *ecx, uint32_t *edx)
2002{
a60f24b5
AF		 2003 X86CPU *cpu = x86_env_get_cpu(env);
2004 CPUState *cs = CPU(cpu);
2005
c6dc6f63
AP		 2006 /* test if maximum index reached */
2007 if (index & 0x80000000) {
b3baa152
BW		 2008 if (index > env->cpuid_xlevel) {
2009 if (env->cpuid_xlevel2 > 0) {
2010 /* Handle the Centaur's CPUID instruction. */
2011 if (index > env->cpuid_xlevel2) {
2012 index = env->cpuid_xlevel2;
2013 } else if (index < 0xC0000000) {
2014 index = env->cpuid_xlevel;
2015 }
2016 } else {
57f26ae7
EH		 2017 /* Intel documentation states that invalid EAX input will
2018 * return the same information as EAX=cpuid_level
2019 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2020 */
2021 index = env->cpuid_level;
b3baa152
BW		 2022 }
2023 }
c6dc6f63
AP		 2024 } else {
2025 if (index > env->cpuid_level)
2026 index = env->cpuid_level;
2027 }
2028
2029 switch(index) {
2030 case 0:
2031 *eax = env->cpuid_level;
2032 get_cpuid_vendor(env, ebx, ecx, edx);
2033 break;
2034 case 1:
2035 *eax = env->cpuid_version;
2036 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2037 *ecx = env->features[FEAT_1_ECX];
2038 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2039 if (cs->nr_cores * cs->nr_threads > 1) {
2040 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2041 *edx |= 1 << 28; /* HTT bit */
2042 }
2043 break;
2044 case 2:
2045 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2046 if (cpu->cache_info_passthrough) {
2047 host_cpuid(index, 0, eax, ebx, ecx, edx);
2048 break;
2049 }
5e891bf8 2050 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2051 *ebx = 0;
2052 *ecx = 0;
5e891bf8
EH		 2053 *edx = (L1D_DESCRIPTOR << 16) | \
2054 (L1I_DESCRIPTOR << 8) | \
2055 (L2_DESCRIPTOR);
c6dc6f63
AP		 2056 break;
2057 case 4:
2058 /* cache info: needed for Core compatibility */
787aaf57
BC		 2059 if (cpu->cache_info_passthrough) {
2060 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2061 *eax &= ~0xFC000000;
c6dc6f63 2062 } else {
2f7a21c4 2063 *eax = 0;
76c2975a 2064 switch (count) {
c6dc6f63 2065 case 0: /* L1 dcache info */
5e891bf8
EH		 2066 *eax |= CPUID_4_TYPE_DCACHE | \
2067 CPUID_4_LEVEL(1) | \
2068 CPUID_4_SELF_INIT_LEVEL;
2069 *ebx = (L1D_LINE_SIZE - 1) | \
2070 ((L1D_PARTITIONS - 1) << 12) | \
2071 ((L1D_ASSOCIATIVITY - 1) << 22);
2072 *ecx = L1D_SETS - 1;
2073 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2074 break;
2075 case 1: /* L1 icache info */
5e891bf8
EH		 2076 *eax |= CPUID_4_TYPE_ICACHE | \
2077 CPUID_4_LEVEL(1) | \
2078 CPUID_4_SELF_INIT_LEVEL;
2079 *ebx = (L1I_LINE_SIZE - 1) | \
2080 ((L1I_PARTITIONS - 1) << 12) | \
2081 ((L1I_ASSOCIATIVITY - 1) << 22);
2082 *ecx = L1I_SETS - 1;
2083 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2084 break;
2085 case 2: /* L2 cache info */
5e891bf8
EH		 2086 *eax |= CPUID_4_TYPE_UNIFIED | \
2087 CPUID_4_LEVEL(2) | \
2088 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2089 if (cs->nr_threads > 1) {
2090 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2091 }
5e891bf8
EH		 2092 *ebx = (L2_LINE_SIZE - 1) | \
2093 ((L2_PARTITIONS - 1) << 12) | \
2094 ((L2_ASSOCIATIVITY - 1) << 22);
2095 *ecx = L2_SETS - 1;
2096 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2097 break;
2098 default: /* end of info */
2099 *eax = 0;
2100 *ebx = 0;
2101 *ecx = 0;
2102 *edx = 0;
2103 break;
76c2975a
PB		 2104 }
2105 }
2106
2107 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2108 if ((*eax & 31) && cs->nr_cores > 1) {
2109 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2110 }
2111 break;
2112 case 5:
2113 /* mwait info: needed for Core compatibility */
2114 *eax = 0; /* Smallest monitor-line size in bytes */
2115 *ebx = 0; /* Largest monitor-line size in bytes */
2116 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2117 *edx = 0;
2118 break;
2119 case 6:
2120 /* Thermal and Power Leaf */
2121 *eax = 0;
2122 *ebx = 0;
2123 *ecx = 0;
2124 *edx = 0;
2125 break;
f7911686 2126 case 7:
13526728
EH		 2127 /* Structured Extended Feature Flags Enumeration Leaf */
2128 if (count == 0) {
2129 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2130 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2131 *ecx = 0; /* Reserved */
2132 *edx = 0; /* Reserved */
f7911686
YW		 2133 } else {
2134 *eax = 0;
2135 *ebx = 0;
2136 *ecx = 0;
2137 *edx = 0;
2138 }
2139 break;
c6dc6f63
AP		 2140 case 9:
2141 /* Direct Cache Access Information Leaf */
2142 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2143 *ebx = 0;
2144 *ecx = 0;
2145 *edx = 0;
2146 break;
2147 case 0xA:
2148 /* Architectural Performance Monitoring Leaf */
9337e3b6 2149 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2150 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2151
2152 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2153 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2154 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2155 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2156 } else {
2157 *eax = 0;
2158 *ebx = 0;
2159 *ecx = 0;
2160 *edx = 0;
2161 }
c6dc6f63 2162 break;
2560f19f
PB		 2163 case 0xD: {
2164 KVMState *s = cs->kvm_state;
2165 uint64_t kvm_mask;
2166 int i;
2167
51e49430 2168 /* Processor Extended State */
2560f19f
PB		 2169 *eax = 0;
2170 *ebx = 0;
2171 *ecx = 0;
2172 *edx = 0;
2173 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2174 break;
2175 }
2560f19f
PB		 2176 kvm_mask =
2177 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2178 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2179
2560f19f
PB		 2180 if (count == 0) {
2181 *ecx = 0x240;
2182 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2183 const ExtSaveArea *esa = &ext_save_areas[i];
2184 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2185 (kvm_mask & (1 << i)) != 0) {
2186 if (i < 32) {
2187 *eax |= 1 << i;
2188 } else {
2189 *edx |= 1 << (i - 32);
2190 }
2191 *ecx = MAX(*ecx, esa->offset + esa->size);
2192 }
2193 }
2194 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2195 *ebx = *ecx;
2196 } else if (count == 1) {
2197 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2198 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2199 const ExtSaveArea *esa = &ext_save_areas[count];
2200 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2201 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2202 *eax = esa->size;
2203 *ebx = esa->offset;
2560f19f 2204 }
51e49430
SY		 2205 }
2206 break;
2560f19f 2207 }
c6dc6f63
AP		 2208 case 0x80000000:
2209 *eax = env->cpuid_xlevel;
2210 *ebx = env->cpuid_vendor1;
2211 *edx = env->cpuid_vendor2;
2212 *ecx = env->cpuid_vendor3;
2213 break;
2214 case 0x80000001:
2215 *eax = env->cpuid_version;
2216 *ebx = 0;
0514ef2f
EH		 2217 *ecx = env->features[FEAT_8000_0001_ECX];
2218 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2219
2220 /* The Linux kernel checks for the CMPLegacy bit and
2221 * discards multiple thread information if it is set.
2222 * So dont set it here for Intel to make Linux guests happy.
2223 */
ce3960eb 2224 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2225 uint32_t tebx, tecx, tedx;
2226 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2227 if (tebx != CPUID_VENDOR_INTEL_1 ||
2228 tedx != CPUID_VENDOR_INTEL_2 ||
2229 tecx != CPUID_VENDOR_INTEL_3) {
2230 *ecx |= 1 << 1; /* CmpLegacy bit */
2231 }
2232 }
c6dc6f63
AP		 2233 break;
2234 case 0x80000002:
2235 case 0x80000003:
2236 case 0x80000004:
2237 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2238 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2239 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2240 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2241 break;
2242 case 0x80000005:
2243 /* cache info (L1 cache) */
787aaf57
BC		 2244 if (cpu->cache_info_passthrough) {
2245 host_cpuid(index, 0, eax, ebx, ecx, edx);
2246 break;
2247 }
5e891bf8
EH		 2248 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2249 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2250 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2251 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2252 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2253 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2254 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2255 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2256 break;
2257 case 0x80000006:
2258 /* cache info (L2 cache) */
787aaf57
BC		 2259 if (cpu->cache_info_passthrough) {
2260 host_cpuid(index, 0, eax, ebx, ecx, edx);
2261 break;
2262 }
5e891bf8
EH		 2263 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2264 (L2_DTLB_2M_ENTRIES << 16) | \
2265 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2266 (L2_ITLB_2M_ENTRIES);
2267 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2268 (L2_DTLB_4K_ENTRIES << 16) | \
2269 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2270 (L2_ITLB_4K_ENTRIES);
2271 *ecx = (L2_SIZE_KB_AMD << 16) | \
2272 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2273 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2274 *edx = ((L3_SIZE_KB/512) << 18) | \
2275 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2276 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP		 2277 break;
2278 case 0x80000008:
2279 /* virtual & phys address size in low 2 bytes. */
2280/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2281 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2282 /* 64 bit processor */
2283/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2284 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2285 } else {
0514ef2f 2286 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2287 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2288 } else {
c6dc6f63 2289 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2290 }
c6dc6f63
AP		 2291 }
2292 *ebx = 0;
2293 *ecx = 0;
2294 *edx = 0;
ce3960eb
AF		 2295 if (cs->nr_cores * cs->nr_threads > 1) {
2296 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2297 }
2298 break;
2299 case 0x8000000A:
0514ef2f 2300 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2301 *eax = 0x00000001; /* SVM Revision */
2302 *ebx = 0x00000010; /* nr of ASIDs */
2303 *ecx = 0;
0514ef2f 2304 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2305 } else {
2306 *eax = 0;
2307 *ebx = 0;
2308 *ecx = 0;
2309 *edx = 0;
2310 }
c6dc6f63 2311 break;
b3baa152
BW		 2312 case 0xC0000000:
2313 *eax = env->cpuid_xlevel2;
2314 *ebx = 0;
2315 *ecx = 0;
2316 *edx = 0;
2317 break;
2318 case 0xC0000001:
2319 /* Support for VIA CPU's CPUID instruction */
2320 *eax = env->cpuid_version;
2321 *ebx = 0;
2322 *ecx = 0;
0514ef2f 2323 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2324 break;
2325 case 0xC0000002:
2326 case 0xC0000003:
2327 case 0xC0000004:
2328 /* Reserved for the future, and now filled with zero */
2329 *eax = 0;
2330 *ebx = 0;
2331 *ecx = 0;
2332 *edx = 0;
2333 break;
c6dc6f63
AP		 2334 default:
2335 /* reserved values: zero */
2336 *eax = 0;
2337 *ebx = 0;
2338 *ecx = 0;
2339 *edx = 0;
2340 break;
2341 }
2342}
5fd2087a
AF		 2343
2344/* CPUClass::reset() */
2345static void x86_cpu_reset(CPUState *s)
2346{
2347 X86CPU *cpu = X86_CPU(s);
2348 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2349 CPUX86State *env = &cpu->env;
c1958aea
AF		 2350 int i;
2351
5fd2087a
AF		 2352 xcc->parent_reset(s);
2353
c1958aea
AF		 2354
2355 memset(env, 0, offsetof(CPUX86State, breakpoints));
2356
2357 tlb_flush(env, 1);
2358
2359 env->old_exception = -1;
2360
2361 /* init to reset state */
2362
2363#ifdef CONFIG_SOFTMMU
2364 env->hflags |= HF_SOFTMMU_MASK;
2365#endif
2366 env->hflags2 |= HF2_GIF_MASK;
2367
2368 cpu_x86_update_cr0(env, 0x60000010);
2369 env->a20_mask = ~0x0;
2370 env->smbase = 0x30000;
2371
2372 env->idt.limit = 0xffff;
2373 env->gdt.limit = 0xffff;
2374 env->ldt.limit = 0xffff;
2375 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2376 env->tr.limit = 0xffff;
2377 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2378
2379 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2380 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2381 DESC_R_MASK | DESC_A_MASK);
2382 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2383 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2384 DESC_A_MASK);
2385 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2386 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2387 DESC_A_MASK);
2388 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2389 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2390 DESC_A_MASK);
2391 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2392 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2393 DESC_A_MASK);
2394 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2395 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2396 DESC_A_MASK);
2397
2398 env->eip = 0xfff0;
2399 env->regs[R_EDX] = env->cpuid_version;
2400
2401 env->eflags = 0x2;
2402
2403 /* FPU init */
2404 for (i = 0; i < 8; i++) {
2405 env->fptags[i] = 1;
2406 }
2407 env->fpuc = 0x37f;
2408
2409 env->mxcsr = 0x1f80;
c74f41bb 2410 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2411
2412 env->pat = 0x0007040600070406ULL;
2413 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2414
2415 memset(env->dr, 0, sizeof(env->dr));
2416 env->dr[6] = DR6_FIXED_1;
2417 env->dr[7] = DR7_FIXED_1;
2418 cpu_breakpoint_remove_all(env, BP_CPU);
2419 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288 2420
0522604b
FLVC		 2421 env->tsc_adjust = 0;
2422 env->tsc = 0;
2423
dd673288
IM		 2424#if !defined(CONFIG_USER_ONLY)
2425 /* We hard-wire the BSP to the first CPU. */
55e5c285 2426 if (s->cpu_index == 0) {
02e51483 2427 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2428 }
2429
259186a7 2430 s->halted = !cpu_is_bsp(cpu);
dd673288 2431#endif
5fd2087a
AF		 2432}
2433
dd673288
IM		 2434#ifndef CONFIG_USER_ONLY
2435bool cpu_is_bsp(X86CPU *cpu)
2436{
02e51483 2437 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2438}
65dee380
IM		 2439
2440/* TODO: remove me, when reset over QOM tree is implemented */
2441static void x86_cpu_machine_reset_cb(void *opaque)
2442{
2443 X86CPU *cpu = opaque;
2444 cpu_reset(CPU(cpu));
2445}
dd673288
IM		 2446#endif
2447
de024815
AF		 2448static void mce_init(X86CPU *cpu)
2449{
2450 CPUX86State *cenv = &cpu->env;
2451 unsigned int bank;
2452
2453 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2454 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2455 (CPUID_MCE | CPUID_MCA)) {
2456 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2457 cenv->mcg_ctl = ~(uint64_t)0;
2458 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2459 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2460 }
2461 }
2462}
2463
bdeec802 2464#ifndef CONFIG_USER_ONLY
d3c64d6a 2465static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2466{
bdeec802 2467 CPUX86State *env = &cpu->env;
53a89e26 2468 DeviceState *dev = DEVICE(cpu);
449994eb 2469 APICCommonState *apic;
bdeec802
IM		 2470 const char *apic_type = "apic";
2471
2472 if (kvm_irqchip_in_kernel()) {
2473 apic_type = "kvm-apic";
2474 } else if (xen_enabled()) {
2475 apic_type = "xen-apic";
2476 }
2477
02e51483
CF		 2478 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2479 if (cpu->apic_state == NULL) {
bdeec802
IM		 2480 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2481 return;
2482 }
2483
2484 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2485 OBJECT(cpu->apic_state), NULL);
2486 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2487 /* TODO: convert to link<> */
02e51483 2488 apic = APIC_COMMON(cpu->apic_state);
60671e58 2489 apic->cpu = cpu;
d3c64d6a
IM		 2490}
2491
2492static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2493{
02e51483 2494 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2495 return;
2496 }
bdeec802 2497
02e51483 2498 if (qdev_init(cpu->apic_state)) {
bdeec802 2499 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2500 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2501 return;
2502 }
bdeec802 2503}
d3c64d6a
IM		 2504#else
2505static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2506{
2507}
bdeec802
IM		 2508#endif
2509
2b6f294c 2510static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2511{
14a10fc3 2512 CPUState *cs = CPU(dev);
2b6f294c
AF		 2513 X86CPU *cpu = X86_CPU(dev);
2514 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2515 CPUX86State *env = &cpu->env;
2b6f294c 2516 Error *local_err = NULL;
b34d12d1 2517
0514ef2f 2518 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2519 env->cpuid_level = 7;
2520 }
7a059953 2521
9b15cd9e
IM		 2522 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2523 * CPUID[1].EDX.
2524 */
2525 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2526 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2527 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2528 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2529 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2530 & CPUID_EXT2_AMD_ALIASES);
2531 }
2532
4586f157 2533 if (!kvm_enabled()) {
0514ef2f
EH		 2534 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2535 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2536 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
4586f157
IM		 2537#ifdef TARGET_X86_64
2538 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2539#endif
2540 );
0514ef2f
EH		 2541 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2542 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
4586f157 2543 } else {
f0b9b111 2544 KVMState *s = kvm_state;
912ffc47 2545 if ((cpu->check_cpuid || cpu->enforce_cpuid)
f0b9b111 2546 && kvm_check_features_against_host(s, cpu) && cpu->enforce_cpuid) {
4dc1f449
IM		 2547 error_setg(&local_err,
2548 "Host's CPU doesn't support requested features");
2549 goto out;
5ec01c2e 2550 }
a509d632 2551 filter_features_for_kvm(cpu);
4586f157
IM		 2552 }
2553
65dee380
IM		 2554#ifndef CONFIG_USER_ONLY
2555 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2556
0514ef2f 2557 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2558 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2559 if (local_err != NULL) {
4dc1f449 2560 goto out;
bdeec802
IM		 2561 }
2562 }
65dee380
IM		 2563#endif
2564
7a059953 2565 mce_init(cpu);
14a10fc3 2566 qemu_init_vcpu(cs);
d3c64d6a
IM		 2567
2568 x86_cpu_apic_realize(cpu, &local_err);
2569 if (local_err != NULL) {
2570 goto out;
2571 }
14a10fc3 2572 cpu_reset(cs);
2b6f294c 2573
4dc1f449
IM		 2574 xcc->parent_realize(dev, &local_err);
2575out:
2576 if (local_err != NULL) {
2577 error_propagate(errp, local_err);
2578 return;
2579 }
7a059953
AF		 2580}
2581
8932cfdf
EH		 2582/* Enables contiguous-apic-ID mode, for compatibility */
2583static bool compat_apic_id_mode;
2584
2585void enable_compat_apic_id_mode(void)
2586{
2587 compat_apic_id_mode = true;
2588}
2589
cb41bad3
EH		 2590/* Calculates initial APIC ID for a specific CPU index
2591 *
2592 * Currently we need to be able to calculate the APIC ID from the CPU index
2593 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2594 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2595 * all CPUs up to max_cpus.
2596 */
2597uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2598{
8932cfdf
EH		 2599 uint32_t correct_id;
2600 static bool warned;
2601
2602 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2603 if (compat_apic_id_mode) {
2604 if (cpu_index != correct_id && !warned) {
2605 error_report("APIC IDs set in compatibility mode, "
2606 "CPU topology won't match the configuration");
2607 warned = true;
2608 }
2609 return cpu_index;
2610 } else {
2611 return correct_id;
2612 }
cb41bad3
EH		 2613}
2614
de024815
AF		 2615static void x86_cpu_initfn(Object *obj)
2616{
55e5c285 2617 CPUState *cs = CPU(obj);
de024815
AF		 2618 X86CPU *cpu = X86_CPU(obj);
2619 CPUX86State *env = &cpu->env;
d65e9815 2620 static int inited;
de024815 2621
c05efcb1 2622 cs->env_ptr = env;
de024815 2623 cpu_exec_init(env);
71ad61d3
AF		 2624
2625 object_property_add(obj, "family", "int",
95b8519d 2626 x86_cpuid_version_get_family,
71ad61d3 2627 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2628 object_property_add(obj, "model", "int",
67e30c83 2629 x86_cpuid_version_get_model,
c5291a4f 2630 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2631 object_property_add(obj, "stepping", "int",
35112e41 2632 x86_cpuid_version_get_stepping,
036e2222 2633 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2634 object_property_add(obj, "level", "int",
2635 x86_cpuid_get_level,
2636 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2637 object_property_add(obj, "xlevel", "int",
2638 x86_cpuid_get_xlevel,
2639 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2640 object_property_add_str(obj, "vendor",
2641 x86_cpuid_get_vendor,
2642 x86_cpuid_set_vendor, NULL);
938d4c25 2643 object_property_add_str(obj, "model-id",
63e886eb 2644 x86_cpuid_get_model_id,
938d4c25 2645 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2646 object_property_add(obj, "tsc-frequency", "int",
2647 x86_cpuid_get_tsc_freq,
2648 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2649 object_property_add(obj, "apic-id", "int",
2650 x86_cpuid_get_apic_id,
2651 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2652 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2653 x86_cpu_get_feature_words,
7e5292b5
EH		 2654 NULL, NULL, (void *)env->features, NULL);
2655 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2656 x86_cpu_get_feature_words,
2657 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2658
92067bf4 2659 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2660 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815
IM		 2661
2662 /* init various static tables used in TCG mode */
2663 if (tcg_enabled() && !inited) {
2664 inited = 1;
2665 optimize_flags_init();
2666#ifndef CONFIG_USER_ONLY
2667 cpu_set_debug_excp_handler(breakpoint_handler);
2668#endif
2669 }
de024815
AF		 2670}
2671
997395d3
IM		 2672static int64_t x86_cpu_get_arch_id(CPUState *cs)
2673{
2674 X86CPU *cpu = X86_CPU(cs);
2675 CPUX86State *env = &cpu->env;
2676
2677 return env->cpuid_apic_id;
2678}
2679
444d5590
AF		 2680static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2681{
2682 X86CPU *cpu = X86_CPU(cs);
2683
2684 return cpu->env.cr[0] & CR0_PG_MASK;
2685}
2686
f45748f1
AF		 2687static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2688{
2689 X86CPU *cpu = X86_CPU(cs);
2690
2691 cpu->env.eip = value;
2692}
2693
bdf7ae5b
AF		 2694static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2695{
2696 X86CPU *cpu = X86_CPU(cs);
2697
2698 cpu->env.eip = tb->pc - tb->cs_base;
2699}
2700
8c2e1b00
AF		 2701static bool x86_cpu_has_work(CPUState *cs)
2702{
2703 X86CPU *cpu = X86_CPU(cs);
2704 CPUX86State *env = &cpu->env;
2705
2706 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2707 CPU_INTERRUPT_POLL)) &&
2708 (env->eflags & IF_MASK)) ||
2709 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2710 CPU_INTERRUPT_INIT |
2711 CPU_INTERRUPT_SIPI |
2712 CPU_INTERRUPT_MCE));
2713}
2714
9337e3b6
EH		 2715static Property x86_cpu_properties[] = {
2716 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2717 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2718 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2719 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2720 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2721 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2722 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
9337e3b6
EH		 2723 DEFINE_PROP_END_OF_LIST()
2724};
2725
5fd2087a
AF		 2726static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2727{
2728 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2729 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2730 DeviceClass *dc = DEVICE_CLASS(oc);
2731
2732 xcc->parent_realize = dc->realize;
2733 dc->realize = x86_cpu_realizefn;
62fc403f 2734 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2735 dc->props = x86_cpu_properties;
5fd2087a
AF		 2736
2737 xcc->parent_reset = cc->reset;
2738 cc->reset = x86_cpu_reset;
91b1df8c 2739 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2740
8c2e1b00 2741 cc->has_work = x86_cpu_has_work;
97a8ea5a 2742 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2743 cc->dump_state = x86_cpu_dump_state;
f45748f1 2744 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2745 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2746 cc->gdb_read_register = x86_cpu_gdb_read_register;
2747 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2748 cc->get_arch_id = x86_cpu_get_arch_id;
2749 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
c72bf468 2750#ifndef CONFIG_USER_ONLY
a23bbfda 2751 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2752 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2753 cc->write_elf64_note = x86_cpu_write_elf64_note;
2754 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2755 cc->write_elf32_note = x86_cpu_write_elf32_note;
2756 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2757 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2758#endif
a0e372f0 2759 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2760}
2761
2762static const TypeInfo x86_cpu_type_info = {
2763 .name = TYPE_X86_CPU,
2764 .parent = TYPE_CPU,
2765 .instance_size = sizeof(X86CPU),
de024815 2766 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2767 .abstract = false,
2768 .class_size = sizeof(X86CPUClass),
2769 .class_init = x86_cpu_common_class_init,
2770};
2771
2772static void x86_cpu_register_types(void)
2773{
2774 type_register_static(&x86_cpu_type_info);
2775}
2776
2777type_init(x86_cpu_register_types)
QEMU mirror