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target-i386: Enable x2apic by default on KVM
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf
EH		 26#include "sysemu/cpus.h"
27#include "topology.h"
c6dc6f63 28
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
53a89e26 44#include "hw/qdev-properties.h"
62fc403f 45#include "hw/cpu/icc_bus.h"
bdeec802 46#ifndef CONFIG_USER_ONLY
0d09e41a 47#include "hw/xen/xen.h"
0d09e41a 48#include "hw/i386/apic_internal.h"
bdeec802
IM		 49#endif
50
5e891bf8
EH		 51
52/* Cache topology CPUID constants: */
53
54/* CPUID Leaf 2 Descriptors */
55
56#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57#define CPUID_2_L1I_32KB_8WAY_64B 0x30
58#define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61/* CPUID Leaf 4 constants: */
62
63/* EAX: */
64#define CPUID_4_TYPE_DCACHE 1
65#define CPUID_4_TYPE_ICACHE 2
66#define CPUID_4_TYPE_UNIFIED 3
67
68#define CPUID_4_LEVEL(l) ((l) << 5)
69
70#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71#define CPUID_4_FULLY_ASSOC (1 << 9)
72
73/* EDX: */
74#define CPUID_4_NO_INVD_SHARING (1 << 0)
75#define CPUID_4_INCLUSIVE (1 << 1)
76#define CPUID_4_COMPLEX_IDX (1 << 2)
77
78#define ASSOC_FULL 0xFF
79
80/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95/* Definitions of the hardcoded cache entries we expose: */
96
97/* L1 data cache: */
98#define L1D_LINE_SIZE 64
99#define L1D_ASSOCIATIVITY 8
100#define L1D_SETS 64
101#define L1D_PARTITIONS 1
102/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105#define L1D_LINES_PER_TAG 1
106#define L1D_SIZE_KB_AMD 64
107#define L1D_ASSOCIATIVITY_AMD 2
108
109/* L1 instruction cache: */
110#define L1I_LINE_SIZE 64
111#define L1I_ASSOCIATIVITY 8
112#define L1I_SETS 64
113#define L1I_PARTITIONS 1
114/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117#define L1I_LINES_PER_TAG 1
118#define L1I_SIZE_KB_AMD 64
119#define L1I_ASSOCIATIVITY_AMD 2
120
121/* Level 2 unified cache: */
122#define L2_LINE_SIZE 64
123#define L2_ASSOCIATIVITY 16
124#define L2_SETS 4096
125#define L2_PARTITIONS 1
126/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130#define L2_LINES_PER_TAG 1
131#define L2_SIZE_KB_AMD 512
132
133/* No L3 cache: */
134#define L3_SIZE_KB 0 /* disabled */
135#define L3_ASSOCIATIVITY 0 /* disabled */
136#define L3_LINES_PER_TAG 0 /* disabled */
137#define L3_LINE_SIZE 0 /* disabled */
138
139/* TLB definitions: */
140
141#define L1_DTLB_2M_ASSOC 1
142#define L1_DTLB_2M_ENTRIES 255
143#define L1_DTLB_4K_ASSOC 1
144#define L1_DTLB_4K_ENTRIES 255
145
146#define L1_ITLB_2M_ASSOC 1
147#define L1_ITLB_2M_ENTRIES 255
148#define L1_ITLB_4K_ASSOC 1
149#define L1_ITLB_4K_ENTRIES 255
150
151#define L2_DTLB_2M_ASSOC 0 /* disabled */
152#define L2_DTLB_2M_ENTRIES 0 /* disabled */
153#define L2_DTLB_4K_ASSOC 4
154#define L2_DTLB_4K_ENTRIES 512
155
156#define L2_ITLB_2M_ASSOC 0 /* disabled */
157#define L2_ITLB_2M_ENTRIES 0 /* disabled */
158#define L2_ITLB_4K_ASSOC 4
159#define L2_ITLB_4K_ENTRIES 512
160
161
162
99b88a17
IM		 163static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165{
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173}
174
c6dc6f63
AP		 175/* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188};
189static const char *ext_feature_name[] = {
f370be3c 190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 191 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 192 "tm2", "ssse3", "cid", NULL,
e117f772 193 "fma", "cx16", "xtpr", "pdcm",
434acb81 194 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 196 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 197 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 198};
3b671a40
EH		 199/* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
c6dc6f63 204static const char *ext2_feature_name[] = {
3b671a40
EH		 205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 212 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 213};
214static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 217 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 222 NULL, NULL, NULL, NULL,
223};
224
89e49c8b
EH		 225static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234};
235
c6dc6f63 236static const char *kvm_feature_name[] = {
c3d39807 237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 245};
246
296acb64
JR		 247static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256};
257
a9321a4d 258static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263};
264
5ef57876
EH		 265typedef struct FeatureWordInfo {
266 const char **feat_names;
04d104b6
EH		 267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
5ef57876
EH		 271} FeatureWordInfo;
272
273static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
89e49c8b
EH		 290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
bffd67b0
EH		 294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
bffd67b0 307 },
5ef57876
EH		 308};
309
8e8aba50
EH		 310typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315} X86RegisterInfo32;
316
317#define REGISTER(reg) \
5d371f41 318 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
8e8aba50
EH		 319X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328};
329#undef REGISTER
330
2560f19f
PB		 331typedef struct ExtSaveArea {
332 uint32_t feature, bits;
333 uint32_t offset, size;
334} ExtSaveArea;
335
336static const ExtSaveArea ext_save_areas[] = {
337 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 338 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 339 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
340 .offset = 0x3c0, .size = 0x40 },
341 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 342 .offset = 0x400, .size = 0x40 },
2560f19f 343};
8e8aba50 344
8b4beddc
EH		 345const char *get_register_name_32(unsigned int reg)
346{
31ccdde2 347 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 348 return NULL;
349 }
8e8aba50 350 return x86_reg_info_32[reg].name;
8b4beddc
EH		 351}
352
c6dc6f63
AP		 353/* collects per-function cpuid data
354 */
355typedef struct model_features_t {
356 uint32_t *guest_feat;
357 uint32_t *host_feat;
bffd67b0 358 FeatureWord feat_word;
8b4beddc 359} model_features_t;
c6dc6f63 360
5fcca9ff
EH		 361/* KVM-specific features that are automatically added to all CPU models
362 * when KVM is enabled.
363 */
364static uint32_t kvm_default_features[FEATURE_WORDS] = {
365 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 366 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 367 (1 << KVM_FEATURE_CLOCKSOURCE2) |
368 (1 << KVM_FEATURE_ASYNC_PF) |
369 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 370 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 371 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 372 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 373};
dc59944b 374
8fb4f821 375void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
dc59944b 376{
8fb4f821 377 kvm_default_features[w] &= ~features;
dc59944b
MT		 378}
379
bb44e0d1
JK		 380void host_cpuid(uint32_t function, uint32_t count,
381 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 382{
a1fd24af
AL		 383 uint32_t vec[4];
384
385#ifdef __x86_64__
386 asm volatile("cpuid"
387 : "=a"(vec[0]), "=b"(vec[1]),
388 "=c"(vec[2]), "=d"(vec[3])
389 : "0"(function), "c"(count) : "cc");
c1f41226 390#elif defined(__i386__)
a1fd24af
AL		 391 asm volatile("pusha \n\t"
392 "cpuid \n\t"
393 "mov %%eax, 0(%2) \n\t"
394 "mov %%ebx, 4(%2) \n\t"
395 "mov %%ecx, 8(%2) \n\t"
396 "mov %%edx, 12(%2) \n\t"
397 "popa"
398 : : "a"(function), "c"(count), "S"(vec)
399 : "memory", "cc");
c1f41226
EH		 400#else
401 abort();
a1fd24af
AL		 402#endif
403
bdde476a 404 if (eax)
a1fd24af 405 *eax = vec[0];
bdde476a 406 if (ebx)
a1fd24af 407 *ebx = vec[1];
bdde476a 408 if (ecx)
a1fd24af 409 *ecx = vec[2];
bdde476a 410 if (edx)
a1fd24af 411 *edx = vec[3];
bdde476a 412}
c6dc6f63
AP		 413
414#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
415
416/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
417 * a substring. ex if !NULL points to the first char after a substring,
418 * otherwise the string is assumed to sized by a terminating nul.
419 * Return lexical ordering of *s1:*s2.
420 */
421static int sstrcmp(const char *s1, const char *e1, const char *s2,
422 const char *e2)
423{
424 for (;;) {
425 if (!*s1 || !*s2 || *s1 != *s2)
426 return (*s1 - *s2);
427 ++s1, ++s2;
428 if (s1 == e1 && s2 == e2)
429 return (0);
430 else if (s1 == e1)
431 return (*s2);
432 else if (s2 == e2)
433 return (*s1);
434 }
435}
436
437/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
438 * '|' delimited (possibly empty) strings in which case search for a match
439 * within the alternatives proceeds left to right. Return 0 for success,
440 * non-zero otherwise.
441 */
442static int altcmp(const char *s, const char *e, const char *altstr)
443{
444 const char *p, *q;
445
446 for (q = p = altstr; ; ) {
447 while (*p && *p != '|')
448 ++p;
449 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
450 return (0);
451 if (!*p)
452 return (1);
453 else
454 q = ++p;
455 }
456}
457
458/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 459 * *pval and return true, otherwise return false
c6dc6f63 460 */
e41e0fc6
JK		 461static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
462 const char **featureset)
c6dc6f63
AP		 463{
464 uint32_t mask;
465 const char **ppc;
e41e0fc6 466 bool found = false;
c6dc6f63 467
e41e0fc6 468 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 469 if (*ppc && !altcmp(s, e, *ppc)) {
470 *pval |= mask;
e41e0fc6 471 found = true;
c6dc6f63 472 }
e41e0fc6
JK		 473 }
474 return found;
c6dc6f63
AP		 475}
476
5ef57876
EH		 477static void add_flagname_to_bitmaps(const char *flagname,
478 FeatureWordArray words)
c6dc6f63 479{
5ef57876
EH		 480 FeatureWord w;
481 for (w = 0; w < FEATURE_WORDS; w++) {
482 FeatureWordInfo *wi = &feature_word_info[w];
483 if (wi->feat_names &&
484 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
485 break;
486 }
487 }
488 if (w == FEATURE_WORDS) {
489 fprintf(stderr, "CPU feature %s not found\n", flagname);
490 }
c6dc6f63
AP		 491}
492
9576de75 493typedef struct X86CPUDefinition {
c6dc6f63
AP		 494 const char *name;
495 uint32_t level;
90e4b0c3
EH		 496 uint32_t xlevel;
497 uint32_t xlevel2;
99b88a17
IM		 498 /* vendor is zero-terminated, 12 character ASCII string */
499 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 500 int family;
501 int model;
502 int stepping;
0514ef2f 503 FeatureWordArray features;
c6dc6f63 504 char model_id[48];
787aaf57 505 bool cache_info_passthrough;
9576de75 506} X86CPUDefinition;
c6dc6f63
AP		 507
508#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
509#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
510 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
511#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
512 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
513 CPUID_PSE36 | CPUID_FXSR)
514#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
515#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
516 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
517 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
518 CPUID_PAE | CPUID_SEP | CPUID_APIC)
519
551a2dec
AP		 520#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
521 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
522 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
523 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
524 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 525 /* partly implemented:
526 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
527 CPUID_PSE36 (needed for Solaris) */
528 /* missing:
529 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
e71827bc
AJ		 530#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
531 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
532 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
d640045a 533 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
8560efed 534 /* missing:
e71827bc
AJ		 535 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
536 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
537 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
d640045a
AJ		 538 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
539 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
83f7dc28 540 CPUID_EXT_RDRAND */
60032ac0 541#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 542 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
543 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 544 /* missing:
545 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 546#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
547 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 548#define TCG_SVM_FEATURES 0
7073fbad 549#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
cd7f97ca 550 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
111994ee 551 /* missing:
7073fbad
RH		 552 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
553 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
cd7f97ca 554 CPUID_7_0_EBX_RDSEED */
551a2dec 555
7fc9b714 556/* built-in CPU model definitions
c6dc6f63 557 */
9576de75 558static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 559 {
560 .name = "qemu64",
561 .level = 4,
99b88a17 562 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 563 .family = 6,
f8e6a11a 564 .model = 6,
c6dc6f63 565 .stepping = 3,
0514ef2f 566 .features[FEAT_1_EDX] =
27861ecc 567 PPRO_FEATURES |
c6dc6f63 568 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 569 CPUID_PSE36,
0514ef2f 570 .features[FEAT_1_ECX] =
27861ecc 571 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 572 .features[FEAT_8000_0001_EDX] =
27861ecc 573 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 574 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 575 .features[FEAT_8000_0001_ECX] =
27861ecc 576 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 577 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
578 .xlevel = 0x8000000A,
c6dc6f63
AP		 579 },
580 {
581 .name = "phenom",
582 .level = 5,
99b88a17 583 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 584 .family = 16,
585 .model = 2,
586 .stepping = 3,
0514ef2f 587 .features[FEAT_1_EDX] =
27861ecc 588 PPRO_FEATURES |
c6dc6f63 589 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 590 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 591 .features[FEAT_1_ECX] =
27861ecc 592 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 593 CPUID_EXT_POPCNT,
0514ef2f 594 .features[FEAT_8000_0001_EDX] =
27861ecc 595 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 596 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
597 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 598 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 599 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
600 CPUID_EXT3_CR8LEG,
601 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
602 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 603 .features[FEAT_8000_0001_ECX] =
27861ecc 604 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 605 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 606 .features[FEAT_SVM] =
27861ecc 607 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 608 .xlevel = 0x8000001A,
609 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
610 },
611 {
612 .name = "core2duo",
613 .level = 10,
99b88a17 614 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 615 .family = 6,
616 .model = 15,
617 .stepping = 11,
0514ef2f 618 .features[FEAT_1_EDX] =
27861ecc 619 PPRO_FEATURES |
c6dc6f63 620 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 621 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
622 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 623 .features[FEAT_1_ECX] =
27861ecc 624 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 625 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
626 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 627 .features[FEAT_8000_0001_EDX] =
27861ecc 628 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 629 .features[FEAT_8000_0001_ECX] =
27861ecc 630 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 631 .xlevel = 0x80000008,
632 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
633 },
634 {
635 .name = "kvm64",
636 .level = 5,
99b88a17 637 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 638 .family = 15,
639 .model = 6,
640 .stepping = 1,
641 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 642 .features[FEAT_1_EDX] =
27861ecc 643 PPRO_FEATURES |
c6dc6f63
AP		 644 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
645 CPUID_PSE36,
646 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 647 .features[FEAT_1_ECX] =
27861ecc 648 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 649 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 650 .features[FEAT_8000_0001_EDX] =
27861ecc 651 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 652 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
653 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
654 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
655 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
656 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 657 .features[FEAT_8000_0001_ECX] =
27861ecc 658 0,
c6dc6f63
AP		 659 .xlevel = 0x80000008,
660 .model_id = "Common KVM processor"
661 },
c6dc6f63
AP		 662 {
663 .name = "qemu32",
664 .level = 4,
99b88a17 665 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 666 .family = 6,
f8e6a11a 667 .model = 6,
c6dc6f63 668 .stepping = 3,
0514ef2f 669 .features[FEAT_1_EDX] =
27861ecc 670 PPRO_FEATURES,
0514ef2f 671 .features[FEAT_1_ECX] =
27861ecc 672 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 673 .xlevel = 0x80000004,
c6dc6f63 674 },
eafaf1e5
AP		 675 {
676 .name = "kvm32",
677 .level = 5,
99b88a17 678 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 679 .family = 15,
680 .model = 6,
681 .stepping = 1,
0514ef2f 682 .features[FEAT_1_EDX] =
27861ecc 683 PPRO_FEATURES |
eafaf1e5 684 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 685 .features[FEAT_1_ECX] =
27861ecc 686 CPUID_EXT_SSE3,
0514ef2f 687 .features[FEAT_8000_0001_EDX] =
27861ecc 688 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 689 .features[FEAT_8000_0001_ECX] =
27861ecc 690 0,
eafaf1e5
AP		 691 .xlevel = 0x80000008,
692 .model_id = "Common 32-bit KVM processor"
693 },
c6dc6f63
AP		 694 {
695 .name = "coreduo",
696 .level = 10,
99b88a17 697 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 698 .family = 6,
699 .model = 14,
700 .stepping = 8,
0514ef2f 701 .features[FEAT_1_EDX] =
27861ecc 702 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 703 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
704 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 705 .features[FEAT_1_ECX] =
27861ecc 706 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 707 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 708 .features[FEAT_8000_0001_EDX] =
27861ecc 709 CPUID_EXT2_NX,
c6dc6f63
AP		 710 .xlevel = 0x80000008,
711 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
712 },
713 {
714 .name = "486",
58012d66 715 .level = 1,
99b88a17 716 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 717 .family = 4,
b2a856d9 718 .model = 8,
c6dc6f63 719 .stepping = 0,
0514ef2f 720 .features[FEAT_1_EDX] =
27861ecc 721 I486_FEATURES,
c6dc6f63
AP		 722 .xlevel = 0,
723 },
724 {
725 .name = "pentium",
726 .level = 1,
99b88a17 727 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 728 .family = 5,
729 .model = 4,
730 .stepping = 3,
0514ef2f 731 .features[FEAT_1_EDX] =
27861ecc 732 PENTIUM_FEATURES,
c6dc6f63
AP		 733 .xlevel = 0,
734 },
735 {
736 .name = "pentium2",
737 .level = 2,
99b88a17 738 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 739 .family = 6,
740 .model = 5,
741 .stepping = 2,
0514ef2f 742 .features[FEAT_1_EDX] =
27861ecc 743 PENTIUM2_FEATURES,
c6dc6f63
AP		 744 .xlevel = 0,
745 },
746 {
747 .name = "pentium3",
748 .level = 2,
99b88a17 749 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 750 .family = 6,
751 .model = 7,
752 .stepping = 3,
0514ef2f 753 .features[FEAT_1_EDX] =
27861ecc 754 PENTIUM3_FEATURES,
c6dc6f63
AP		 755 .xlevel = 0,
756 },
757 {
758 .name = "athlon",
759 .level = 2,
99b88a17 760 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 761 .family = 6,
762 .model = 2,
763 .stepping = 3,
0514ef2f 764 .features[FEAT_1_EDX] =
27861ecc 765 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 766 CPUID_MCA,
0514ef2f 767 .features[FEAT_8000_0001_EDX] =
27861ecc 768 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 769 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 770 .xlevel = 0x80000008,
c6dc6f63
AP		 771 },
772 {
773 .name = "n270",
774 /* original is on level 10 */
775 .level = 5,
99b88a17 776 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 777 .family = 6,
778 .model = 28,
779 .stepping = 2,
0514ef2f 780 .features[FEAT_1_EDX] =
27861ecc 781 PPRO_FEATURES |
8560efed
AJ		 782 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
783 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 784 /* Some CPUs got no CPUID_SEP */
0514ef2f 785 .features[FEAT_1_ECX] =
27861ecc 786 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 787 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
788 CPUID_EXT_MOVBE,
0514ef2f 789 .features[FEAT_8000_0001_EDX] =
27861ecc 790 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 791 CPUID_EXT2_NX,
0514ef2f 792 .features[FEAT_8000_0001_ECX] =
27861ecc 793 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 794 .xlevel = 0x8000000A,
795 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
796 },
3eca4642
EH		 797 {
798 .name = "Conroe",
6b11322e 799 .level = 4,
99b88a17 800 .vendor = CPUID_VENDOR_INTEL,
3eca4642 801 .family = 6,
ffce9ebb 802 .model = 15,
3eca4642 803 .stepping = 3,
0514ef2f 804 .features[FEAT_1_EDX] =
27861ecc 805 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 806 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
807 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
808 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
809 CPUID_DE | CPUID_FP87,
0514ef2f 810 .features[FEAT_1_ECX] =
27861ecc 811 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 812 .features[FEAT_8000_0001_EDX] =
27861ecc 813 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 814 .features[FEAT_8000_0001_ECX] =
27861ecc 815 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 816 .xlevel = 0x8000000A,
817 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
818 },
819 {
820 .name = "Penryn",
6b11322e 821 .level = 4,
99b88a17 822 .vendor = CPUID_VENDOR_INTEL,
3eca4642 823 .family = 6,
ffce9ebb 824 .model = 23,
3eca4642 825 .stepping = 3,
0514ef2f 826 .features[FEAT_1_EDX] =
27861ecc 827 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 828 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
829 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
830 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
831 CPUID_DE | CPUID_FP87,
0514ef2f 832 .features[FEAT_1_ECX] =
27861ecc 833 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 834 CPUID_EXT_SSE3,
0514ef2f 835 .features[FEAT_8000_0001_EDX] =
27861ecc 836 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 837 .features[FEAT_8000_0001_ECX] =
27861ecc 838 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 839 .xlevel = 0x8000000A,
840 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
841 },
842 {
843 .name = "Nehalem",
6b11322e 844 .level = 4,
99b88a17 845 .vendor = CPUID_VENDOR_INTEL,
3eca4642 846 .family = 6,
ffce9ebb 847 .model = 26,
3eca4642 848 .stepping = 3,
0514ef2f 849 .features[FEAT_1_EDX] =
27861ecc 850 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 851 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
852 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
853 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
854 CPUID_DE | CPUID_FP87,
0514ef2f 855 .features[FEAT_1_ECX] =
27861ecc 856 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 857 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 858 .features[FEAT_8000_0001_EDX] =
27861ecc 859 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 860 .features[FEAT_8000_0001_ECX] =
27861ecc 861 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 862 .xlevel = 0x8000000A,
863 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
864 },
865 {
866 .name = "Westmere",
867 .level = 11,
99b88a17 868 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 869 .family = 6,
870 .model = 44,
871 .stepping = 1,
0514ef2f 872 .features[FEAT_1_EDX] =
27861ecc 873 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 874 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
875 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
876 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
877 CPUID_DE | CPUID_FP87,
0514ef2f 878 .features[FEAT_1_ECX] =
27861ecc 879 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 880 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 881 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 882 .features[FEAT_8000_0001_EDX] =
27861ecc 883 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 884 .features[FEAT_8000_0001_ECX] =
27861ecc 885 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 886 .xlevel = 0x8000000A,
887 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
888 },
889 {
890 .name = "SandyBridge",
891 .level = 0xd,
99b88a17 892 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 893 .family = 6,
894 .model = 42,
895 .stepping = 1,
0514ef2f 896 .features[FEAT_1_EDX] =
27861ecc 897 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 898 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
899 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
900 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
901 CPUID_DE | CPUID_FP87,
0514ef2f 902 .features[FEAT_1_ECX] =
27861ecc 903 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 904 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
905 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
906 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
907 CPUID_EXT_SSE3,
0514ef2f 908 .features[FEAT_8000_0001_EDX] =
27861ecc 909 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 910 CPUID_EXT2_SYSCALL,
0514ef2f 911 .features[FEAT_8000_0001_ECX] =
27861ecc 912 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 913 .xlevel = 0x8000000A,
914 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
915 },
37507094
EH		 916 {
917 .name = "Haswell",
918 .level = 0xd,
99b88a17 919 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 920 .family = 6,
921 .model = 60,
922 .stepping = 1,
0514ef2f 923 .features[FEAT_1_EDX] =
27861ecc 924 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 925 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 926 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 927 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
928 CPUID_DE | CPUID_FP87,
0514ef2f 929 .features[FEAT_1_ECX] =
27861ecc 930 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH		 931 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
932 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
933 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
934 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
935 CPUID_EXT_PCID,
0514ef2f 936 .features[FEAT_8000_0001_EDX] =
27861ecc 937 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 938 CPUID_EXT2_SYSCALL,
0514ef2f 939 .features[FEAT_8000_0001_ECX] =
27861ecc 940 CPUID_EXT3_LAHF_LM,
0514ef2f 941 .features[FEAT_7_0_EBX] =
27861ecc 942 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 943 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
944 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
945 CPUID_7_0_EBX_RTM,
946 .xlevel = 0x8000000A,
947 .model_id = "Intel Core Processor (Haswell)",
948 },
3eca4642
EH		 949 {
950 .name = "Opteron_G1",
951 .level = 5,
99b88a17 952 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 953 .family = 15,
954 .model = 6,
955 .stepping = 1,
0514ef2f 956 .features[FEAT_1_EDX] =
27861ecc 957 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 958 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
959 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
960 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
961 CPUID_DE | CPUID_FP87,
0514ef2f 962 .features[FEAT_1_ECX] =
27861ecc 963 CPUID_EXT_SSE3,
0514ef2f 964 .features[FEAT_8000_0001_EDX] =
27861ecc 965 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH		 966 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
967 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
968 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
969 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
970 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
971 .xlevel = 0x80000008,
972 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
973 },
974 {
975 .name = "Opteron_G2",
976 .level = 5,
99b88a17 977 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 978 .family = 15,
979 .model = 6,
980 .stepping = 1,
0514ef2f 981 .features[FEAT_1_EDX] =
27861ecc 982 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 983 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
984 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
985 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
986 CPUID_DE | CPUID_FP87,
0514ef2f 987 .features[FEAT_1_ECX] =
27861ecc 988 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 989 .features[FEAT_8000_0001_EDX] =
27861ecc 990 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 991 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
992 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
993 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
994 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
995 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
996 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 997 .features[FEAT_8000_0001_ECX] =
27861ecc 998 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 999 .xlevel = 0x80000008,
1000 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1001 },
1002 {
1003 .name = "Opteron_G3",
1004 .level = 5,
99b88a17 1005 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1006 .family = 15,
1007 .model = 6,
1008 .stepping = 1,
0514ef2f 1009 .features[FEAT_1_EDX] =
27861ecc 1010 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1011 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1012 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1013 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1014 CPUID_DE | CPUID_FP87,
0514ef2f 1015 .features[FEAT_1_ECX] =
27861ecc 1016 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1017 CPUID_EXT_SSE3,
0514ef2f 1018 .features[FEAT_8000_0001_EDX] =
27861ecc 1019 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1020 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1021 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1022 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1023 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1024 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1025 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1026 .features[FEAT_8000_0001_ECX] =
27861ecc 1027 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH		 1028 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1029 .xlevel = 0x80000008,
1030 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1031 },
1032 {
1033 .name = "Opteron_G4",
1034 .level = 0xd,
99b88a17 1035 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1036 .family = 21,
1037 .model = 1,
1038 .stepping = 2,
0514ef2f 1039 .features[FEAT_1_EDX] =
27861ecc 1040 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1041 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1042 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1043 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1044 CPUID_DE | CPUID_FP87,
0514ef2f 1045 .features[FEAT_1_ECX] =
27861ecc 1046 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 1047 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1048 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1049 CPUID_EXT_SSE3,
0514ef2f 1050 .features[FEAT_8000_0001_EDX] =
27861ecc 1051 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH		 1052 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1053 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1054 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1055 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1056 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1057 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1058 .features[FEAT_8000_0001_ECX] =
27861ecc 1059 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH		 1060 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1061 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1062 CPUID_EXT3_LAHF_LM,
1063 .xlevel = 0x8000001A,
1064 .model_id = "AMD Opteron 62xx class CPU",
1065 },
021941b9
AP		 1066 {
1067 .name = "Opteron_G5",
1068 .level = 0xd,
99b88a17 1069 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1070 .family = 21,
1071 .model = 2,
1072 .stepping = 0,
0514ef2f 1073 .features[FEAT_1_EDX] =
27861ecc 1074 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP		 1075 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1076 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1077 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1078 CPUID_DE | CPUID_FP87,
0514ef2f 1079 .features[FEAT_1_ECX] =
27861ecc 1080 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP		 1081 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1082 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1083 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1084 .features[FEAT_8000_0001_EDX] =
27861ecc 1085 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP		 1086 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1087 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1088 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1089 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1090 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1091 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1092 .features[FEAT_8000_0001_ECX] =
27861ecc 1093 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP		 1094 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1095 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1096 CPUID_EXT3_LAHF_LM,
1097 .xlevel = 0x8000001A,
1098 .model_id = "AMD Opteron 63xx class CPU",
1099 },
c6dc6f63
AP		 1100};
1101
0668af54
EH		 1102/**
1103 * x86_cpu_compat_set_features:
1104 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1105 * @w: Identifies the feature word to be changed.
1106 * @feat_add: Feature bits to be added to feature word
1107 * @feat_remove: Feature bits to be removed from feature word
1108 *
1109 * Change CPU model feature bits for compatibility.
1110 *
1111 * This function may be used by machine-type compatibility functions
1112 * to enable or disable feature bits on specific CPU models.
1113 */
1114void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1115 uint32_t feat_add, uint32_t feat_remove)
1116{
9576de75 1117 X86CPUDefinition *def;
0668af54
EH		 1118 int i;
1119 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1120 def = &builtin_x86_defs[i];
1121 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1122 def->features[w] |= feat_add;
1123 def->features[w] &= ~feat_remove;
1124 }
1125 }
1126}
1127
c6dc6f63
AP		 1128static int cpu_x86_fill_model_id(char *str)
1129{
1130 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1131 int i;
1132
1133 for (i = 0; i < 3; i++) {
1134 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1135 memcpy(str + i * 16 + 0, &eax, 4);
1136 memcpy(str + i * 16 + 4, &ebx, 4);
1137 memcpy(str + i * 16 + 8, &ecx, 4);
1138 memcpy(str + i * 16 + 12, &edx, 4);
1139 }
1140 return 0;
1141}
1142
9576de75 1143/* Fill a X86CPUDefinition struct with information about the host CPU, and
6e746f30
EH		 1144 * the CPU features supported by the host hardware + host kernel
1145 *
1146 * This function may be called only if KVM is enabled.
1147 */
9576de75 1148static void kvm_cpu_fill_host(X86CPUDefinition *x86_cpu_def)
c6dc6f63 1149{
12869995 1150 KVMState *s = kvm_state;
c6dc6f63 1151 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
74f54bc4 1152 FeatureWord w;
c6dc6f63 1153
6e746f30
EH		 1154 assert(kvm_enabled());
1155
c6dc6f63 1156 x86_cpu_def->name = "host";
787aaf57 1157 x86_cpu_def->cache_info_passthrough = true;
c6dc6f63 1158 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
99b88a17 1159 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
c6dc6f63
AP		 1160
1161 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1162 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1163 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1164 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 1165
12869995 1166 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
2a573259
EH		 1167 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1168 x86_cpu_def->xlevel2 =
1169 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1170
1171 cpu_x86_fill_model_id(x86_cpu_def->model_id);
1172
2bc65d2b
EH		 1173 for (w = 0; w < FEATURE_WORDS; w++) {
1174 FeatureWordInfo *wi = &feature_word_info[w];
1175 x86_cpu_def->features[w] =
1176 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1177 wi->cpuid_reg);
1178 }
c6dc6f63
AP		 1179}
1180
bffd67b0 1181static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 1182{
1183 int i;
1184
1185 for (i = 0; i < 32; ++i)
1186 if (1 << i & mask) {
bffd67b0 1187 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1188 assert(reg);
1189 fprintf(stderr, "warning: host doesn't support requested feature: "
1190 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1191 f->cpuid_eax, reg,
1192 f->feat_names[i] ? "." : "",
1193 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 1194 break;
1195 }
1196 return 0;
1197}
1198
07ca5945
EH		 1199/* Check if all requested cpu flags are making their way to the guest
1200 *
1201 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 1202 *
1203 * This function may be called only if KVM is enabled.
c6dc6f63 1204 */
f0b9b111 1205static int kvm_check_features_against_host(KVMState *s, X86CPU *cpu)
c6dc6f63 1206{
5ec01c2e 1207 CPUX86State *env = &cpu->env;
f0b9b111
EH		 1208 int rv = 0;
1209 FeatureWord w;
c6dc6f63 1210
6e746f30
EH		 1211 assert(kvm_enabled());
1212
f0b9b111 1213 for (w = 0; w < FEATURE_WORDS; w++) {
bffd67b0 1214 FeatureWordInfo *wi = &feature_word_info[w];
f0b9b111
EH		 1215 uint32_t guest_feat = env->features[w];
1216 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1217 wi->cpuid_ecx,
1218 wi->cpuid_reg);
1219 uint32_t mask;
bffd67b0 1220 for (mask = 1; mask; mask <<= 1) {
f0b9b111 1221 if (guest_feat & mask && !(host_feat & mask)) {
bffd67b0
EH		 1222 unavailable_host_feature(wi, mask);
1223 rv = 1;
1224 }
1225 }
1226 }
c6dc6f63
AP		 1227 return rv;
1228}
1229
95b8519d
AF		 1230static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1231 const char *name, Error **errp)
1232{
1233 X86CPU *cpu = X86_CPU(obj);
1234 CPUX86State *env = &cpu->env;
1235 int64_t value;
1236
1237 value = (env->cpuid_version >> 8) & 0xf;
1238 if (value == 0xf) {
1239 value += (env->cpuid_version >> 20) & 0xff;
1240 }
1241 visit_type_int(v, &value, name, errp);
1242}
1243
71ad61d3
AF		 1244static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1245 const char *name, Error **errp)
ed5e1ec3 1246{
71ad61d3
AF		 1247 X86CPU *cpu = X86_CPU(obj);
1248 CPUX86State *env = &cpu->env;
1249 const int64_t min = 0;
1250 const int64_t max = 0xff + 0xf;
1251 int64_t value;
1252
1253 visit_type_int(v, &value, name, errp);
1254 if (error_is_set(errp)) {
1255 return;
1256 }
1257 if (value < min || value > max) {
1258 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1259 name ? name : "null", value, min, max);
1260 return;
1261 }
1262
ed5e1ec3 1263 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1264 if (value > 0x0f) {
1265 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1266 } else {
71ad61d3 1267 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1268 }
1269}
1270
67e30c83
AF		 1271static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1272 const char *name, Error **errp)
1273{
1274 X86CPU *cpu = X86_CPU(obj);
1275 CPUX86State *env = &cpu->env;
1276 int64_t value;
1277
1278 value = (env->cpuid_version >> 4) & 0xf;
1279 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1280 visit_type_int(v, &value, name, errp);
1281}
1282
c5291a4f
AF		 1283static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1284 const char *name, Error **errp)
b0704cbd 1285{
c5291a4f
AF		 1286 X86CPU *cpu = X86_CPU(obj);
1287 CPUX86State *env = &cpu->env;
1288 const int64_t min = 0;
1289 const int64_t max = 0xff;
1290 int64_t value;
1291
1292 visit_type_int(v, &value, name, errp);
1293 if (error_is_set(errp)) {
1294 return;
1295 }
1296 if (value < min || value > max) {
1297 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1298 name ? name : "null", value, min, max);
1299 return;
1300 }
1301
b0704cbd 1302 env->cpuid_version &= ~0xf00f0;
c5291a4f 1303 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1304}
1305
35112e41
AF		 1306static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1307 void *opaque, const char *name,
1308 Error **errp)
1309{
1310 X86CPU *cpu = X86_CPU(obj);
1311 CPUX86State *env = &cpu->env;
1312 int64_t value;
1313
1314 value = env->cpuid_version & 0xf;
1315 visit_type_int(v, &value, name, errp);
1316}
1317
036e2222
AF		 1318static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1319 void *opaque, const char *name,
1320 Error **errp)
38c3dc46 1321{
036e2222
AF		 1322 X86CPU *cpu = X86_CPU(obj);
1323 CPUX86State *env = &cpu->env;
1324 const int64_t min = 0;
1325 const int64_t max = 0xf;
1326 int64_t value;
1327
1328 visit_type_int(v, &value, name, errp);
1329 if (error_is_set(errp)) {
1330 return;
1331 }
1332 if (value < min || value > max) {
1333 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1334 name ? name : "null", value, min, max);
1335 return;
1336 }
1337
38c3dc46 1338 env->cpuid_version &= ~0xf;
036e2222 1339 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1340}
1341
8e1898bf
AF		 1342static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1343 const char *name, Error **errp)
1344{
1345 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1346
fa029887 1347 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1348}
1349
1350static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1351 const char *name, Error **errp)
1352{
1353 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1354
fa029887 1355 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1356}
1357
16b93aa8
AF		 1358static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1359 const char *name, Error **errp)
1360{
1361 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1362
fa029887 1363 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1364}
1365
1366static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1367 const char *name, Error **errp)
1368{
1369 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1370
fa029887 1371 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1372}
1373
d480e1af
AF		 1374static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1375{
1376 X86CPU *cpu = X86_CPU(obj);
1377 CPUX86State *env = &cpu->env;
1378 char *value;
d480e1af 1379
9df694ee 1380 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1381 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1382 env->cpuid_vendor3);
d480e1af
AF		 1383 return value;
1384}
1385
1386static void x86_cpuid_set_vendor(Object *obj, const char *value,
1387 Error **errp)
1388{
1389 X86CPU *cpu = X86_CPU(obj);
1390 CPUX86State *env = &cpu->env;
1391 int i;
1392
9df694ee 1393 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1394 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1395 "vendor", value);
1396 return;
1397 }
1398
1399 env->cpuid_vendor1 = 0;
1400 env->cpuid_vendor2 = 0;
1401 env->cpuid_vendor3 = 0;
1402 for (i = 0; i < 4; i++) {
1403 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1404 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1405 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1406 }
d480e1af
AF		 1407}
1408
63e886eb
AF		 1409static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1410{
1411 X86CPU *cpu = X86_CPU(obj);
1412 CPUX86State *env = &cpu->env;
1413 char *value;
1414 int i;
1415
1416 value = g_malloc(48 + 1);
1417 for (i = 0; i < 48; i++) {
1418 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1419 }
1420 value[48] = '\0';
1421 return value;
1422}
1423
938d4c25
AF		 1424static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1425 Error **errp)
dcce6675 1426{
938d4c25
AF		 1427 X86CPU *cpu = X86_CPU(obj);
1428 CPUX86State *env = &cpu->env;
dcce6675
AF		 1429 int c, len, i;
1430
1431 if (model_id == NULL) {
1432 model_id = "";
1433 }
1434 len = strlen(model_id);
d0a6acf4 1435 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1436 for (i = 0; i < 48; i++) {
1437 if (i >= len) {
1438 c = '\0';
1439 } else {
1440 c = (uint8_t)model_id[i];
1441 }
1442 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1443 }
1444}
1445
89e48965
AF		 1446static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1447 const char *name, Error **errp)
1448{
1449 X86CPU *cpu = X86_CPU(obj);
1450 int64_t value;
1451
1452 value = cpu->env.tsc_khz * 1000;
1453 visit_type_int(v, &value, name, errp);
1454}
1455
1456static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1457 const char *name, Error **errp)
1458{
1459 X86CPU *cpu = X86_CPU(obj);
1460 const int64_t min = 0;
2e84849a 1461 const int64_t max = INT64_MAX;
89e48965
AF		 1462 int64_t value;
1463
1464 visit_type_int(v, &value, name, errp);
1465 if (error_is_set(errp)) {
1466 return;
1467 }
1468 if (value < min || value > max) {
1469 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1470 name ? name : "null", value, min, max);
1471 return;
1472 }
1473
1474 cpu->env.tsc_khz = value / 1000;
1475}
1476
31050930
IM		 1477static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1478 const char *name, Error **errp)
1479{
1480 X86CPU *cpu = X86_CPU(obj);
1481 int64_t value = cpu->env.cpuid_apic_id;
1482
1483 visit_type_int(v, &value, name, errp);
1484}
1485
1486static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1487 const char *name, Error **errp)
1488{
1489 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1490 DeviceState *dev = DEVICE(obj);
31050930
IM		 1491 const int64_t min = 0;
1492 const int64_t max = UINT32_MAX;
1493 Error *error = NULL;
1494 int64_t value;
1495
8d6d4980
IM		 1496 if (dev->realized) {
1497 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1498 "it was realized", name, object_get_typename(obj));
1499 return;
1500 }
1501
31050930
IM		 1502 visit_type_int(v, &value, name, &error);
1503 if (error) {
1504 error_propagate(errp, error);
1505 return;
1506 }
1507 if (value < min || value > max) {
1508 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1509 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1510 object_get_typename(obj), name, value, min, max);
1511 return;
1512 }
1513
1514 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1515 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1516 return;
1517 }
1518 cpu->env.cpuid_apic_id = value;
1519}
1520
7e5292b5 1521/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1522static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1523 const char *name, Error **errp)
1524{
7e5292b5 1525 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1526 FeatureWord w;
1527 Error *err = NULL;
1528 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1529 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1530 X86CPUFeatureWordInfoList *list = NULL;
1531
1532 for (w = 0; w < FEATURE_WORDS; w++) {
1533 FeatureWordInfo *wi = &feature_word_info[w];
1534 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1535 qwi->cpuid_input_eax = wi->cpuid_eax;
1536 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1537 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1538 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1539 qwi->features = array[w];
8e8aba50
EH		 1540
1541 /* List will be in reverse order, but order shouldn't matter */
1542 list_entries[w].next = list;
1543 list_entries[w].value = &word_infos[w];
1544 list = &list_entries[w];
1545 }
1546
1547 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1548 error_propagate(errp, err);
1549}
1550
c8f0f88e
IM		 1551static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1552 const char *name, Error **errp)
1553{
1554 X86CPU *cpu = X86_CPU(obj);
1555 int64_t value = cpu->hyperv_spinlock_attempts;
1556
1557 visit_type_int(v, &value, name, errp);
1558}
1559
1560static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1561 const char *name, Error **errp)
1562{
1563 const int64_t min = 0xFFF;
1564 const int64_t max = UINT_MAX;
1565 X86CPU *cpu = X86_CPU(obj);
1566 Error *err = NULL;
1567 int64_t value;
1568
1569 visit_type_int(v, &value, name, &err);
1570 if (err) {
1571 error_propagate(errp, err);
1572 return;
1573 }
1574
1575 if (value < min || value > max) {
1576 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1577 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1578 object_get_typename(obj), name ? name : "null",
1579 value, min, max);
1580 return;
1581 }
1582 cpu->hyperv_spinlock_attempts = value;
1583}
1584
1585static PropertyInfo qdev_prop_spinlocks = {
1586 .name = "int",
1587 .get = x86_get_hv_spinlocks,
1588 .set = x86_set_hv_spinlocks,
1589};
1590
9576de75 1591static int cpu_x86_find_by_name(X86CPU *cpu, X86CPUDefinition *x86_cpu_def,
c1399112 1592 const char *name)
c6dc6f63 1593{
9576de75 1594 X86CPUDefinition *def;
7fc9b714 1595 int i;
c6dc6f63 1596
4bfe910d
AF		 1597 if (name == NULL) {
1598 return -1;
9f3fb565 1599 }
4bfe910d 1600 if (kvm_enabled() && strcmp(name, "host") == 0) {
6e746f30 1601 kvm_cpu_fill_host(x86_cpu_def);
00b81053 1602 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
4bfe910d 1603 return 0;
c6dc6f63
AP		 1604 }
1605
7fc9b714
AF		 1606 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1607 def = &builtin_x86_defs[i];
4bfe910d
AF		 1608 if (strcmp(name, def->name) == 0) {
1609 memcpy(x86_cpu_def, def, sizeof(*def));
1610 return 0;
1611 }
1612 }
1613
1614 return -1;
8f961357
EH		 1615}
1616
72ac2e87
IM		 1617/* Convert all '_' in a feature string option name to '-', to make feature
1618 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1619 */
1620static inline void feat2prop(char *s)
1621{
1622 while ((s = strchr(s, '_'))) {
1623 *s = '-';
1624 }
1625}
1626
8f961357
EH		 1627/* Parse "+feature,-feature,feature=foo" CPU feature string
1628 */
a91987c2 1629static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
8f961357 1630{
8f961357
EH		 1631 char *featurestr; /* Single 'key=value" string being parsed */
1632 /* Features to be added */
077c68c3 1633 FeatureWordArray plus_features = { 0 };
8f961357 1634 /* Features to be removed */
5ef57876 1635 FeatureWordArray minus_features = { 0 };
8f961357 1636 uint32_t numvalue;
a91987c2 1637 CPUX86State *env = &cpu->env;
8f961357 1638
8f961357 1639 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1640
1641 while (featurestr) {
1642 char *val;
1643 if (featurestr[0] == '+') {
5ef57876 1644 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1645 } else if (featurestr[0] == '-') {
5ef57876 1646 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1647 } else if ((val = strchr(featurestr, '='))) {
1648 *val = 0; val++;
72ac2e87 1649 feat2prop(featurestr);
d024d209 1650 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1651 char *err;
a91987c2
IM		 1652 char num[32];
1653
c6dc6f63
AP		 1654 numvalue = strtoul(val, &err, 0);
1655 if (!*val || *err) {
312fd5f2 1656 error_setg(errp, "bad numerical value %s", val);
a91987c2 1657 goto out;
c6dc6f63
AP		 1658 }
1659 if (numvalue < 0x80000000) {
8ba8a698
IM		 1660 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1661 ", fixup will be removed in future versions\n");
2f7a21c4 1662 numvalue += 0x80000000;
c6dc6f63 1663 }
a91987c2
IM		 1664 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1665 object_property_parse(OBJECT(cpu), num, featurestr, errp);
72ac2e87 1666 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1667 int64_t tsc_freq;
1668 char *err;
a91987c2 1669 char num[32];
b862d1fe
JR		 1670
1671 tsc_freq = strtosz_suffix_unit(val, &err,
1672 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1673 if (tsc_freq < 0 || *err) {
312fd5f2 1674 error_setg(errp, "bad numerical value %s", val);
a91987c2 1675 goto out;
b862d1fe 1676 }
a91987c2
IM		 1677 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1678 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
72ac2e87 1679 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1680 char *err;
92067bf4 1681 const int min = 0xFFF;
c8f0f88e 1682 char num[32];
28f52cc0
VR		 1683 numvalue = strtoul(val, &err, 0);
1684 if (!*val || *err) {
312fd5f2 1685 error_setg(errp, "bad numerical value %s", val);
a91987c2 1686 goto out;
28f52cc0 1687 }
92067bf4
IM		 1688 if (numvalue < min) {
1689 fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1690 ", fixup will be removed in future versions\n",
1691 min);
1692 numvalue = min;
1693 }
c8f0f88e
IM		 1694 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1695 object_property_parse(OBJECT(cpu), num, featurestr, errp);
c6dc6f63 1696 } else {
d024d209 1697 object_property_parse(OBJECT(cpu), val, featurestr, errp);
c6dc6f63 1698 }
c6dc6f63 1699 } else {
258f5abe
IM		 1700 feat2prop(featurestr);
1701 object_property_parse(OBJECT(cpu), "on", featurestr, errp);
a91987c2
IM		 1702 }
1703 if (error_is_set(errp)) {
1704 goto out;
c6dc6f63
AP		 1705 }
1706 featurestr = strtok(NULL, ",");
1707 }
0514ef2f
EH		 1708 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1709 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1710 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1711 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1712 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1713 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1714 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1715 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1716 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1717 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1718 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1719 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1720 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1721 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1722 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1723 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63 1724
a91987c2
IM		 1725out:
1726 return;
c6dc6f63
AP		 1727}
1728
1729/* generate a composite string into buf of all cpuid names in featureset
1730 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1731 * if flags, suppress names undefined in featureset.
1732 */
1733static void listflags(char *buf, int bufsize, uint32_t fbits,
1734 const char **featureset, uint32_t flags)
1735{
1736 const char **p = &featureset[31];
1737 char *q, *b, bit;
1738 int nc;
1739
1740 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1741 *buf = '\0';
1742 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1743 if (fbits & 1 << bit && (*p || !flags)) {
1744 if (*p)
1745 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1746 else
1747 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1748 if (bufsize <= nc) {
1749 if (b) {
1750 memcpy(b, "...", sizeof("..."));
1751 }
1752 return;
1753 }
1754 q += nc;
1755 bufsize -= nc;
1756 }
1757}
1758
e916cbf8
PM		 1759/* generate CPU information. */
1760void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1761{
9576de75 1762 X86CPUDefinition *def;
c6dc6f63 1763 char buf[256];
7fc9b714 1764 int i;
c6dc6f63 1765
7fc9b714
AF		 1766 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1767 def = &builtin_x86_defs[i];
c04321b3 1768 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1769 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1770 }
21ad7789
JK		 1771#ifdef CONFIG_KVM
1772 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1773 "KVM processor with all supported host features "
1774 "(only available in KVM mode)");
1775#endif
1776
6cdf8854 1777 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1778 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1779 FeatureWordInfo *fw = &feature_word_info[i];
1780
1781 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1782 (*cpu_fprintf)(f, " %s\n", buf);
1783 }
c6dc6f63
AP		 1784}
1785
76b64a7a 1786CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1787{
1788 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1789 X86CPUDefinition *def;
7fc9b714 1790 int i;
e3966126 1791
7fc9b714 1792 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1793 CpuDefinitionInfoList *entry;
1794 CpuDefinitionInfo *info;
1795
7fc9b714 1796 def = &builtin_x86_defs[i];
e3966126
AL		 1797 info = g_malloc0(sizeof(*info));
1798 info->name = g_strdup(def->name);
1799
1800 entry = g_malloc0(sizeof(*entry));
1801 entry->value = info;
1802 entry->next = cpu_list;
1803 cpu_list = entry;
1804 }
1805
1806 return cpu_list;
1807}
1808
bc74b7db
EH		 1809static void filter_features_for_kvm(X86CPU *cpu)
1810{
1811 CPUX86State *env = &cpu->env;
1812 KVMState *s = kvm_state;
bd87d2a2 1813 FeatureWord w;
bc74b7db 1814
bd87d2a2
EH		 1815 for (w = 0; w < FEATURE_WORDS; w++) {
1816 FeatureWordInfo *wi = &feature_word_info[w];
034acf4a
EH		 1817 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1818 wi->cpuid_ecx,
1819 wi->cpuid_reg);
1820 uint32_t requested_features = env->features[w];
1821 env->features[w] &= host_feat;
1822 cpu->filtered_features[w] = requested_features & ~env->features[w];
bd87d2a2 1823 }
bc74b7db 1824}
bc74b7db 1825
c080e30e
EH		 1826/* Load CPU definition for a given CPU model name
1827 */
1828static void x86_cpu_load_def(X86CPU *cpu, const char *name, Error **errp)
c6dc6f63 1829{
61dcd775 1830 CPUX86State *env = &cpu->env;
9576de75 1831 X86CPUDefinition def1, *def = &def1;
74f54bc4
EH		 1832 const char *vendor;
1833 char host_vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63 1834
db0ad1ba
JR		 1835 memset(def, 0, sizeof(*def));
1836
c1399112 1837 if (cpu_x86_find_by_name(cpu, def, name) < 0) {
2d64255b
AF		 1838 error_setg(errp, "Unable to find CPU definition: %s", name);
1839 return;
8f961357
EH		 1840 }
1841
2d64255b
AF		 1842 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1843 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1844 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1845 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
0514ef2f
EH		 1846 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1847 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1848 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1849 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
2d64255b 1850 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
0514ef2f
EH		 1851 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1852 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1853 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1854 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
b3baa152 1855 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1856 cpu->cache_info_passthrough = def->cache_info_passthrough;
3b671a40 1857
2d64255b 1858 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
82beb536 1859
9576de75 1860 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 1861 if (kvm_enabled()) {
5fcca9ff
EH		 1862 FeatureWord w;
1863 for (w = 0; w < FEATURE_WORDS; w++) {
1864 env->features[w] |= kvm_default_features[w];
1865 }
82beb536 1866 }
5fcca9ff 1867
82beb536 1868 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 1869
1870 /* sysenter isn't supported in compatibility mode on AMD,
1871 * syscall isn't supported in compatibility mode on Intel.
1872 * Normally we advertise the actual CPU vendor, but you can
1873 * override this using the 'vendor' property if you want to use
1874 * KVM's sysenter/syscall emulation in compatibility mode and
1875 * when doing cross vendor migration
1876 */
74f54bc4 1877 vendor = def->vendor;
7c08db30
EH		 1878 if (kvm_enabled()) {
1879 uint32_t ebx = 0, ecx = 0, edx = 0;
1880 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1881 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1882 vendor = host_vendor;
1883 }
1884
1885 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1886
c6dc6f63
AP		 1887}
1888
62fc403f
IM		 1889X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1890 Error **errp)
5c3c6a68 1891{
2d64255b 1892 X86CPU *cpu = NULL;
2d64255b
AF		 1893 gchar **model_pieces;
1894 char *name, *features;
ba2bc7a4 1895 char *typename;
5c3c6a68
AF		 1896 Error *error = NULL;
1897
2d64255b
AF		 1898 model_pieces = g_strsplit(cpu_model, ",", 2);
1899 if (!model_pieces[0]) {
1900 error_setg(&error, "Invalid/empty CPU model name");
1901 goto out;
1902 }
1903 name = model_pieces[0];
1904 features = model_pieces[1];
1905
5c3c6a68 1906 cpu = X86_CPU(object_new(TYPE_X86_CPU));
285f025d
EH		 1907 x86_cpu_load_def(cpu, name, &error);
1908 if (error) {
1909 goto out;
1910 }
1911
62fc403f
IM		 1912#ifndef CONFIG_USER_ONLY
1913 if (icc_bridge == NULL) {
1914 error_setg(&error, "Invalid icc-bridge value");
1915 goto out;
1916 }
1917 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1918 object_unref(OBJECT(cpu));
1919#endif
5c3c6a68 1920
ba2bc7a4
AF		 1921 /* Emulate per-model subclasses for global properties */
1922 typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1923 qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1924 g_free(typename);
1925 if (error) {
1926 goto out;
1927 }
1928
2d64255b
AF		 1929 cpu_x86_parse_featurestr(cpu, features, &error);
1930 if (error) {
1931 goto out;
5c3c6a68
AF		 1932 }
1933
7f833247 1934out:
cd7b87ff
AF		 1935 if (error != NULL) {
1936 error_propagate(errp, error);
1937 object_unref(OBJECT(cpu));
1938 cpu = NULL;
1939 }
7f833247
IM		 1940 g_strfreev(model_pieces);
1941 return cpu;
1942}
1943
1944X86CPU *cpu_x86_init(const char *cpu_model)
1945{
1946 Error *error = NULL;
1947 X86CPU *cpu;
1948
62fc403f 1949 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1950 if (error) {
2d64255b
AF		 1951 goto out;
1952 }
1953
7f833247
IM		 1954 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1955
2d64255b 1956out:
2d64255b 1957 if (error) {
4a44d85e 1958 error_report("%s", error_get_pretty(error));
5c3c6a68 1959 error_free(error);
2d64255b
AF		 1960 if (cpu != NULL) {
1961 object_unref(OBJECT(cpu));
1962 cpu = NULL;
1963 }
5c3c6a68
AF		 1964 }
1965 return cpu;
1966}
1967
c6dc6f63 1968#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1969
0e26b7b8
BS		 1970void cpu_clear_apic_feature(CPUX86State *env)
1971{
0514ef2f 1972 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 1973}
1974
c6dc6f63
AP		 1975#endif /* !CONFIG_USER_ONLY */
1976
c04321b3 1977/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1978 */
1979void x86_cpudef_setup(void)
1980{
93bfef4c
CV		 1981 int i, j;
1982 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1983
1984 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 1985 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 1986
1987 /* Look for specific "cpudef" models that */
09faecf2 1988 /* have the QEMU version in .model_id */
93bfef4c 1989 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1990 if (strcmp(model_with_versions[j], def->name) == 0) {
1991 pstrcpy(def->model_id, sizeof(def->model_id),
1992 "QEMU Virtual CPU version ");
1993 pstrcat(def->model_id, sizeof(def->model_id),
1994 qemu_get_version());
93bfef4c
CV		 1995 break;
1996 }
1997 }
c6dc6f63 1998 }
c6dc6f63
AP		 1999}
2000
c6dc6f63
AP		 2001static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2002 uint32_t *ecx, uint32_t *edx)
2003{
2004 *ebx = env->cpuid_vendor1;
2005 *edx = env->cpuid_vendor2;
2006 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2007}
2008
2009void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2010 uint32_t *eax, uint32_t *ebx,
2011 uint32_t *ecx, uint32_t *edx)
2012{
a60f24b5
AF		 2013 X86CPU *cpu = x86_env_get_cpu(env);
2014 CPUState *cs = CPU(cpu);
2015
c6dc6f63
AP		 2016 /* test if maximum index reached */
2017 if (index & 0x80000000) {
b3baa152
BW		 2018 if (index > env->cpuid_xlevel) {
2019 if (env->cpuid_xlevel2 > 0) {
2020 /* Handle the Centaur's CPUID instruction. */
2021 if (index > env->cpuid_xlevel2) {
2022 index = env->cpuid_xlevel2;
2023 } else if (index < 0xC0000000) {
2024 index = env->cpuid_xlevel;
2025 }
2026 } else {
57f26ae7
EH		 2027 /* Intel documentation states that invalid EAX input will
2028 * return the same information as EAX=cpuid_level
2029 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2030 */
2031 index = env->cpuid_level;
b3baa152
BW		 2032 }
2033 }
c6dc6f63
AP		 2034 } else {
2035 if (index > env->cpuid_level)
2036 index = env->cpuid_level;
2037 }
2038
2039 switch(index) {
2040 case 0:
2041 *eax = env->cpuid_level;
2042 get_cpuid_vendor(env, ebx, ecx, edx);
2043 break;
2044 case 1:
2045 *eax = env->cpuid_version;
2046 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2047 *ecx = env->features[FEAT_1_ECX];
2048 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2049 if (cs->nr_cores * cs->nr_threads > 1) {
2050 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2051 *edx |= 1 << 28; /* HTT bit */
2052 }
2053 break;
2054 case 2:
2055 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2056 if (cpu->cache_info_passthrough) {
2057 host_cpuid(index, 0, eax, ebx, ecx, edx);
2058 break;
2059 }
5e891bf8 2060 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2061 *ebx = 0;
2062 *ecx = 0;
5e891bf8
EH		 2063 *edx = (L1D_DESCRIPTOR << 16) | \
2064 (L1I_DESCRIPTOR << 8) | \
2065 (L2_DESCRIPTOR);
c6dc6f63
AP		 2066 break;
2067 case 4:
2068 /* cache info: needed for Core compatibility */
787aaf57
BC		 2069 if (cpu->cache_info_passthrough) {
2070 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2071 *eax &= ~0xFC000000;
c6dc6f63 2072 } else {
2f7a21c4 2073 *eax = 0;
76c2975a 2074 switch (count) {
c6dc6f63 2075 case 0: /* L1 dcache info */
5e891bf8
EH		 2076 *eax |= CPUID_4_TYPE_DCACHE | \
2077 CPUID_4_LEVEL(1) | \
2078 CPUID_4_SELF_INIT_LEVEL;
2079 *ebx = (L1D_LINE_SIZE - 1) | \
2080 ((L1D_PARTITIONS - 1) << 12) | \
2081 ((L1D_ASSOCIATIVITY - 1) << 22);
2082 *ecx = L1D_SETS - 1;
2083 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2084 break;
2085 case 1: /* L1 icache info */
5e891bf8
EH		 2086 *eax |= CPUID_4_TYPE_ICACHE | \
2087 CPUID_4_LEVEL(1) | \
2088 CPUID_4_SELF_INIT_LEVEL;
2089 *ebx = (L1I_LINE_SIZE - 1) | \
2090 ((L1I_PARTITIONS - 1) << 12) | \
2091 ((L1I_ASSOCIATIVITY - 1) << 22);
2092 *ecx = L1I_SETS - 1;
2093 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2094 break;
2095 case 2: /* L2 cache info */
5e891bf8
EH		 2096 *eax |= CPUID_4_TYPE_UNIFIED | \
2097 CPUID_4_LEVEL(2) | \
2098 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2099 if (cs->nr_threads > 1) {
2100 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2101 }
5e891bf8
EH		 2102 *ebx = (L2_LINE_SIZE - 1) | \
2103 ((L2_PARTITIONS - 1) << 12) | \
2104 ((L2_ASSOCIATIVITY - 1) << 22);
2105 *ecx = L2_SETS - 1;
2106 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2107 break;
2108 default: /* end of info */
2109 *eax = 0;
2110 *ebx = 0;
2111 *ecx = 0;
2112 *edx = 0;
2113 break;
76c2975a
PB		 2114 }
2115 }
2116
2117 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2118 if ((*eax & 31) && cs->nr_cores > 1) {
2119 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2120 }
2121 break;
2122 case 5:
2123 /* mwait info: needed for Core compatibility */
2124 *eax = 0; /* Smallest monitor-line size in bytes */
2125 *ebx = 0; /* Largest monitor-line size in bytes */
2126 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2127 *edx = 0;
2128 break;
2129 case 6:
2130 /* Thermal and Power Leaf */
2131 *eax = 0;
2132 *ebx = 0;
2133 *ecx = 0;
2134 *edx = 0;
2135 break;
f7911686 2136 case 7:
13526728
EH		 2137 /* Structured Extended Feature Flags Enumeration Leaf */
2138 if (count == 0) {
2139 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2140 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2141 *ecx = 0; /* Reserved */
2142 *edx = 0; /* Reserved */
f7911686
YW		 2143 } else {
2144 *eax = 0;
2145 *ebx = 0;
2146 *ecx = 0;
2147 *edx = 0;
2148 }
2149 break;
c6dc6f63
AP		 2150 case 9:
2151 /* Direct Cache Access Information Leaf */
2152 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2153 *ebx = 0;
2154 *ecx = 0;
2155 *edx = 0;
2156 break;
2157 case 0xA:
2158 /* Architectural Performance Monitoring Leaf */
9337e3b6 2159 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2160 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2161
2162 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2163 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2164 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2165 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2166 } else {
2167 *eax = 0;
2168 *ebx = 0;
2169 *ecx = 0;
2170 *edx = 0;
2171 }
c6dc6f63 2172 break;
2560f19f
PB		 2173 case 0xD: {
2174 KVMState *s = cs->kvm_state;
2175 uint64_t kvm_mask;
2176 int i;
2177
51e49430 2178 /* Processor Extended State */
2560f19f
PB		 2179 *eax = 0;
2180 *ebx = 0;
2181 *ecx = 0;
2182 *edx = 0;
2183 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2184 break;
2185 }
2560f19f
PB		 2186 kvm_mask =
2187 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2188 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2189
2560f19f
PB		 2190 if (count == 0) {
2191 *ecx = 0x240;
2192 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2193 const ExtSaveArea *esa = &ext_save_areas[i];
2194 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2195 (kvm_mask & (1 << i)) != 0) {
2196 if (i < 32) {
2197 *eax |= 1 << i;
2198 } else {
2199 *edx |= 1 << (i - 32);
2200 }
2201 *ecx = MAX(*ecx, esa->offset + esa->size);
2202 }
2203 }
2204 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2205 *ebx = *ecx;
2206 } else if (count == 1) {
2207 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2208 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2209 const ExtSaveArea *esa = &ext_save_areas[count];
2210 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2211 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2212 *eax = esa->size;
2213 *ebx = esa->offset;
2560f19f 2214 }
51e49430
SY		 2215 }
2216 break;
2560f19f 2217 }
c6dc6f63
AP		 2218 case 0x80000000:
2219 *eax = env->cpuid_xlevel;
2220 *ebx = env->cpuid_vendor1;
2221 *edx = env->cpuid_vendor2;
2222 *ecx = env->cpuid_vendor3;
2223 break;
2224 case 0x80000001:
2225 *eax = env->cpuid_version;
2226 *ebx = 0;
0514ef2f
EH		 2227 *ecx = env->features[FEAT_8000_0001_ECX];
2228 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2229
2230 /* The Linux kernel checks for the CMPLegacy bit and
2231 * discards multiple thread information if it is set.
2232 * So dont set it here for Intel to make Linux guests happy.
2233 */
ce3960eb 2234 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2235 uint32_t tebx, tecx, tedx;
2236 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2237 if (tebx != CPUID_VENDOR_INTEL_1 ||
2238 tedx != CPUID_VENDOR_INTEL_2 ||
2239 tecx != CPUID_VENDOR_INTEL_3) {
2240 *ecx |= 1 << 1; /* CmpLegacy bit */
2241 }
2242 }
c6dc6f63
AP		 2243 break;
2244 case 0x80000002:
2245 case 0x80000003:
2246 case 0x80000004:
2247 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2248 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2249 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2250 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2251 break;
2252 case 0x80000005:
2253 /* cache info (L1 cache) */
787aaf57
BC		 2254 if (cpu->cache_info_passthrough) {
2255 host_cpuid(index, 0, eax, ebx, ecx, edx);
2256 break;
2257 }
5e891bf8
EH		 2258 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2259 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2260 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2261 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2262 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2263 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2264 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2265 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2266 break;
2267 case 0x80000006:
2268 /* cache info (L2 cache) */
787aaf57
BC		 2269 if (cpu->cache_info_passthrough) {
2270 host_cpuid(index, 0, eax, ebx, ecx, edx);
2271 break;
2272 }
5e891bf8
EH		 2273 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2274 (L2_DTLB_2M_ENTRIES << 16) | \
2275 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2276 (L2_ITLB_2M_ENTRIES);
2277 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2278 (L2_DTLB_4K_ENTRIES << 16) | \
2279 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2280 (L2_ITLB_4K_ENTRIES);
2281 *ecx = (L2_SIZE_KB_AMD << 16) | \
2282 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2283 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2284 *edx = ((L3_SIZE_KB/512) << 18) | \
2285 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2286 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP		 2287 break;
2288 case 0x80000008:
2289 /* virtual & phys address size in low 2 bytes. */
2290/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2291 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2292 /* 64 bit processor */
2293/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2294 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2295 } else {
0514ef2f 2296 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2297 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2298 } else {
c6dc6f63 2299 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2300 }
c6dc6f63
AP		 2301 }
2302 *ebx = 0;
2303 *ecx = 0;
2304 *edx = 0;
ce3960eb
AF		 2305 if (cs->nr_cores * cs->nr_threads > 1) {
2306 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2307 }
2308 break;
2309 case 0x8000000A:
0514ef2f 2310 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2311 *eax = 0x00000001; /* SVM Revision */
2312 *ebx = 0x00000010; /* nr of ASIDs */
2313 *ecx = 0;
0514ef2f 2314 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2315 } else {
2316 *eax = 0;
2317 *ebx = 0;
2318 *ecx = 0;
2319 *edx = 0;
2320 }
c6dc6f63 2321 break;
b3baa152
BW		 2322 case 0xC0000000:
2323 *eax = env->cpuid_xlevel2;
2324 *ebx = 0;
2325 *ecx = 0;
2326 *edx = 0;
2327 break;
2328 case 0xC0000001:
2329 /* Support for VIA CPU's CPUID instruction */
2330 *eax = env->cpuid_version;
2331 *ebx = 0;
2332 *ecx = 0;
0514ef2f 2333 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2334 break;
2335 case 0xC0000002:
2336 case 0xC0000003:
2337 case 0xC0000004:
2338 /* Reserved for the future, and now filled with zero */
2339 *eax = 0;
2340 *ebx = 0;
2341 *ecx = 0;
2342 *edx = 0;
2343 break;
c6dc6f63
AP		 2344 default:
2345 /* reserved values: zero */
2346 *eax = 0;
2347 *ebx = 0;
2348 *ecx = 0;
2349 *edx = 0;
2350 break;
2351 }
2352}
5fd2087a
AF		 2353
2354/* CPUClass::reset() */
2355static void x86_cpu_reset(CPUState *s)
2356{
2357 X86CPU *cpu = X86_CPU(s);
2358 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2359 CPUX86State *env = &cpu->env;
c1958aea
AF		 2360 int i;
2361
5fd2087a
AF		 2362 xcc->parent_reset(s);
2363
c1958aea
AF		 2364
2365 memset(env, 0, offsetof(CPUX86State, breakpoints));
2366
2367 tlb_flush(env, 1);
2368
2369 env->old_exception = -1;
2370
2371 /* init to reset state */
2372
2373#ifdef CONFIG_SOFTMMU
2374 env->hflags |= HF_SOFTMMU_MASK;
2375#endif
2376 env->hflags2 |= HF2_GIF_MASK;
2377
2378 cpu_x86_update_cr0(env, 0x60000010);
2379 env->a20_mask = ~0x0;
2380 env->smbase = 0x30000;
2381
2382 env->idt.limit = 0xffff;
2383 env->gdt.limit = 0xffff;
2384 env->ldt.limit = 0xffff;
2385 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2386 env->tr.limit = 0xffff;
2387 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2388
2389 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2390 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2391 DESC_R_MASK | DESC_A_MASK);
2392 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2393 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2394 DESC_A_MASK);
2395 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2396 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2397 DESC_A_MASK);
2398 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2399 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2400 DESC_A_MASK);
2401 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2402 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2403 DESC_A_MASK);
2404 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2405 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2406 DESC_A_MASK);
2407
2408 env->eip = 0xfff0;
2409 env->regs[R_EDX] = env->cpuid_version;
2410
2411 env->eflags = 0x2;
2412
2413 /* FPU init */
2414 for (i = 0; i < 8; i++) {
2415 env->fptags[i] = 1;
2416 }
2417 env->fpuc = 0x37f;
2418
2419 env->mxcsr = 0x1f80;
c74f41bb 2420 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2421
2422 env->pat = 0x0007040600070406ULL;
2423 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2424
2425 memset(env->dr, 0, sizeof(env->dr));
2426 env->dr[6] = DR6_FIXED_1;
2427 env->dr[7] = DR7_FIXED_1;
2428 cpu_breakpoint_remove_all(env, BP_CPU);
2429 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288 2430
0522604b
FLVC		 2431 env->tsc_adjust = 0;
2432 env->tsc = 0;
2433
dd673288
IM		 2434#if !defined(CONFIG_USER_ONLY)
2435 /* We hard-wire the BSP to the first CPU. */
55e5c285 2436 if (s->cpu_index == 0) {
02e51483 2437 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2438 }
2439
259186a7 2440 s->halted = !cpu_is_bsp(cpu);
dd673288 2441#endif
5fd2087a
AF		 2442}
2443
dd673288
IM		 2444#ifndef CONFIG_USER_ONLY
2445bool cpu_is_bsp(X86CPU *cpu)
2446{
02e51483 2447 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2448}
65dee380
IM		 2449
2450/* TODO: remove me, when reset over QOM tree is implemented */
2451static void x86_cpu_machine_reset_cb(void *opaque)
2452{
2453 X86CPU *cpu = opaque;
2454 cpu_reset(CPU(cpu));
2455}
dd673288
IM		 2456#endif
2457
de024815
AF		 2458static void mce_init(X86CPU *cpu)
2459{
2460 CPUX86State *cenv = &cpu->env;
2461 unsigned int bank;
2462
2463 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2464 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2465 (CPUID_MCE | CPUID_MCA)) {
2466 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2467 cenv->mcg_ctl = ~(uint64_t)0;
2468 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2469 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2470 }
2471 }
2472}
2473
bdeec802 2474#ifndef CONFIG_USER_ONLY
d3c64d6a 2475static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2476{
bdeec802 2477 CPUX86State *env = &cpu->env;
53a89e26 2478 DeviceState *dev = DEVICE(cpu);
449994eb 2479 APICCommonState *apic;
bdeec802
IM		 2480 const char *apic_type = "apic";
2481
2482 if (kvm_irqchip_in_kernel()) {
2483 apic_type = "kvm-apic";
2484 } else if (xen_enabled()) {
2485 apic_type = "xen-apic";
2486 }
2487
02e51483
CF		 2488 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2489 if (cpu->apic_state == NULL) {
bdeec802
IM		 2490 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2491 return;
2492 }
2493
2494 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2495 OBJECT(cpu->apic_state), NULL);
2496 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2497 /* TODO: convert to link<> */
02e51483 2498 apic = APIC_COMMON(cpu->apic_state);
60671e58 2499 apic->cpu = cpu;
d3c64d6a
IM		 2500}
2501
2502static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2503{
02e51483 2504 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2505 return;
2506 }
bdeec802 2507
02e51483 2508 if (qdev_init(cpu->apic_state)) {
bdeec802 2509 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2510 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2511 return;
2512 }
bdeec802 2513}
d3c64d6a
IM		 2514#else
2515static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2516{
2517}
bdeec802
IM		 2518#endif
2519
2b6f294c 2520static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2521{
14a10fc3 2522 CPUState *cs = CPU(dev);
2b6f294c
AF		 2523 X86CPU *cpu = X86_CPU(dev);
2524 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2525 CPUX86State *env = &cpu->env;
2b6f294c 2526 Error *local_err = NULL;
b34d12d1 2527
0514ef2f 2528 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2529 env->cpuid_level = 7;
2530 }
7a059953 2531
9b15cd9e
IM		 2532 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2533 * CPUID[1].EDX.
2534 */
2535 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2536 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2537 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2538 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2539 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2540 & CPUID_EXT2_AMD_ALIASES);
2541 }
2542
4586f157 2543 if (!kvm_enabled()) {
0514ef2f
EH		 2544 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2545 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2546 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
4586f157
IM		 2547#ifdef TARGET_X86_64
2548 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2549#endif
2550 );
0514ef2f
EH		 2551 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2552 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
4586f157 2553 } else {
f0b9b111 2554 KVMState *s = kvm_state;
912ffc47 2555 if ((cpu->check_cpuid || cpu->enforce_cpuid)
f0b9b111 2556 && kvm_check_features_against_host(s, cpu) && cpu->enforce_cpuid) {
4dc1f449
IM		 2557 error_setg(&local_err,
2558 "Host's CPU doesn't support requested features");
2559 goto out;
5ec01c2e 2560 }
a509d632 2561 filter_features_for_kvm(cpu);
4586f157
IM		 2562 }
2563
65dee380
IM		 2564#ifndef CONFIG_USER_ONLY
2565 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2566
0514ef2f 2567 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2568 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2569 if (local_err != NULL) {
4dc1f449 2570 goto out;
bdeec802
IM		 2571 }
2572 }
65dee380
IM		 2573#endif
2574
7a059953 2575 mce_init(cpu);
14a10fc3 2576 qemu_init_vcpu(cs);
d3c64d6a
IM		 2577
2578 x86_cpu_apic_realize(cpu, &local_err);
2579 if (local_err != NULL) {
2580 goto out;
2581 }
14a10fc3 2582 cpu_reset(cs);
2b6f294c 2583
4dc1f449
IM		 2584 xcc->parent_realize(dev, &local_err);
2585out:
2586 if (local_err != NULL) {
2587 error_propagate(errp, local_err);
2588 return;
2589 }
7a059953
AF		 2590}
2591
8932cfdf
EH		 2592/* Enables contiguous-apic-ID mode, for compatibility */
2593static bool compat_apic_id_mode;
2594
2595void enable_compat_apic_id_mode(void)
2596{
2597 compat_apic_id_mode = true;
2598}
2599
cb41bad3
EH		 2600/* Calculates initial APIC ID for a specific CPU index
2601 *
2602 * Currently we need to be able to calculate the APIC ID from the CPU index
2603 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2604 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2605 * all CPUs up to max_cpus.
2606 */
2607uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2608{
8932cfdf
EH		 2609 uint32_t correct_id;
2610 static bool warned;
2611
2612 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2613 if (compat_apic_id_mode) {
2614 if (cpu_index != correct_id && !warned) {
2615 error_report("APIC IDs set in compatibility mode, "
2616 "CPU topology won't match the configuration");
2617 warned = true;
2618 }
2619 return cpu_index;
2620 } else {
2621 return correct_id;
2622 }
cb41bad3
EH		 2623}
2624
de024815
AF		 2625static void x86_cpu_initfn(Object *obj)
2626{
55e5c285 2627 CPUState *cs = CPU(obj);
de024815
AF		 2628 X86CPU *cpu = X86_CPU(obj);
2629 CPUX86State *env = &cpu->env;
d65e9815 2630 static int inited;
de024815 2631
c05efcb1 2632 cs->env_ptr = env;
de024815 2633 cpu_exec_init(env);
71ad61d3
AF		 2634
2635 object_property_add(obj, "family", "int",
95b8519d 2636 x86_cpuid_version_get_family,
71ad61d3 2637 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2638 object_property_add(obj, "model", "int",
67e30c83 2639 x86_cpuid_version_get_model,
c5291a4f 2640 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2641 object_property_add(obj, "stepping", "int",
35112e41 2642 x86_cpuid_version_get_stepping,
036e2222 2643 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2644 object_property_add(obj, "level", "int",
2645 x86_cpuid_get_level,
2646 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2647 object_property_add(obj, "xlevel", "int",
2648 x86_cpuid_get_xlevel,
2649 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2650 object_property_add_str(obj, "vendor",
2651 x86_cpuid_get_vendor,
2652 x86_cpuid_set_vendor, NULL);
938d4c25 2653 object_property_add_str(obj, "model-id",
63e886eb 2654 x86_cpuid_get_model_id,
938d4c25 2655 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2656 object_property_add(obj, "tsc-frequency", "int",
2657 x86_cpuid_get_tsc_freq,
2658 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2659 object_property_add(obj, "apic-id", "int",
2660 x86_cpuid_get_apic_id,
2661 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2662 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2663 x86_cpu_get_feature_words,
7e5292b5
EH		 2664 NULL, NULL, (void *)env->features, NULL);
2665 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2666 x86_cpu_get_feature_words,
2667 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2668
92067bf4 2669 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2670 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815
IM		 2671
2672 /* init various static tables used in TCG mode */
2673 if (tcg_enabled() && !inited) {
2674 inited = 1;
2675 optimize_flags_init();
2676#ifndef CONFIG_USER_ONLY
2677 cpu_set_debug_excp_handler(breakpoint_handler);
2678#endif
2679 }
de024815
AF		 2680}
2681
997395d3
IM		 2682static int64_t x86_cpu_get_arch_id(CPUState *cs)
2683{
2684 X86CPU *cpu = X86_CPU(cs);
2685 CPUX86State *env = &cpu->env;
2686
2687 return env->cpuid_apic_id;
2688}
2689
444d5590
AF		 2690static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2691{
2692 X86CPU *cpu = X86_CPU(cs);
2693
2694 return cpu->env.cr[0] & CR0_PG_MASK;
2695}
2696
f45748f1
AF		 2697static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2698{
2699 X86CPU *cpu = X86_CPU(cs);
2700
2701 cpu->env.eip = value;
2702}
2703
bdf7ae5b
AF		 2704static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2705{
2706 X86CPU *cpu = X86_CPU(cs);
2707
2708 cpu->env.eip = tb->pc - tb->cs_base;
2709}
2710
8c2e1b00
AF		 2711static bool x86_cpu_has_work(CPUState *cs)
2712{
2713 X86CPU *cpu = X86_CPU(cs);
2714 CPUX86State *env = &cpu->env;
2715
2716 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2717 CPU_INTERRUPT_POLL)) &&
2718 (env->eflags & IF_MASK)) ||
2719 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2720 CPU_INTERRUPT_INIT |
2721 CPU_INTERRUPT_SIPI |
2722 CPU_INTERRUPT_MCE));
2723}
2724
9337e3b6
EH		 2725static Property x86_cpu_properties[] = {
2726 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2727 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2728 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2729 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2730 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2731 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2732 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
9337e3b6
EH		 2733 DEFINE_PROP_END_OF_LIST()
2734};
2735
5fd2087a
AF		 2736static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2737{
2738 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2739 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2740 DeviceClass *dc = DEVICE_CLASS(oc);
2741
2742 xcc->parent_realize = dc->realize;
2743 dc->realize = x86_cpu_realizefn;
62fc403f 2744 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2745 dc->props = x86_cpu_properties;
5fd2087a
AF		 2746
2747 xcc->parent_reset = cc->reset;
2748 cc->reset = x86_cpu_reset;
91b1df8c 2749 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2750
8c2e1b00 2751 cc->has_work = x86_cpu_has_work;
97a8ea5a 2752 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2753 cc->dump_state = x86_cpu_dump_state;
f45748f1 2754 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2755 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2756 cc->gdb_read_register = x86_cpu_gdb_read_register;
2757 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2758 cc->get_arch_id = x86_cpu_get_arch_id;
2759 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
c72bf468 2760#ifndef CONFIG_USER_ONLY
a23bbfda 2761 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2762 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2763 cc->write_elf64_note = x86_cpu_write_elf64_note;
2764 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2765 cc->write_elf32_note = x86_cpu_write_elf32_note;
2766 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2767 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2768#endif
a0e372f0 2769 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2770}
2771
2772static const TypeInfo x86_cpu_type_info = {
2773 .name = TYPE_X86_CPU,
2774 .parent = TYPE_CPU,
2775 .instance_size = sizeof(X86CPU),
de024815 2776 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2777 .abstract = false,
2778 .class_size = sizeof(X86CPUClass),
2779 .class_init = x86_cpu_common_class_init,
2780};
2781
2782static void x86_cpu_register_types(void)
2783{
2784 type_register_static(&x86_cpu_type_info);
2785}
2786
2787type_init(x86_cpu_register_types)
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