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target-i386: the x86 CPL is stored in CS.selector - auto update hflags accordingly.
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf
EH		 26#include "sysemu/cpus.h"
27#include "topology.h"
c6dc6f63 28
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
53a89e26 44#include "hw/qdev-properties.h"
62fc403f 45#include "hw/cpu/icc_bus.h"
bdeec802 46#ifndef CONFIG_USER_ONLY
0d09e41a 47#include "hw/xen/xen.h"
0d09e41a 48#include "hw/i386/apic_internal.h"
bdeec802
IM		 49#endif
50
5e891bf8
EH		 51
52/* Cache topology CPUID constants: */
53
54/* CPUID Leaf 2 Descriptors */
55
56#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57#define CPUID_2_L1I_32KB_8WAY_64B 0x30
58#define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61/* CPUID Leaf 4 constants: */
62
63/* EAX: */
64#define CPUID_4_TYPE_DCACHE 1
65#define CPUID_4_TYPE_ICACHE 2
66#define CPUID_4_TYPE_UNIFIED 3
67
68#define CPUID_4_LEVEL(l) ((l) << 5)
69
70#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71#define CPUID_4_FULLY_ASSOC (1 << 9)
72
73/* EDX: */
74#define CPUID_4_NO_INVD_SHARING (1 << 0)
75#define CPUID_4_INCLUSIVE (1 << 1)
76#define CPUID_4_COMPLEX_IDX (1 << 2)
77
78#define ASSOC_FULL 0xFF
79
80/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95/* Definitions of the hardcoded cache entries we expose: */
96
97/* L1 data cache: */
98#define L1D_LINE_SIZE 64
99#define L1D_ASSOCIATIVITY 8
100#define L1D_SETS 64
101#define L1D_PARTITIONS 1
102/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105#define L1D_LINES_PER_TAG 1
106#define L1D_SIZE_KB_AMD 64
107#define L1D_ASSOCIATIVITY_AMD 2
108
109/* L1 instruction cache: */
110#define L1I_LINE_SIZE 64
111#define L1I_ASSOCIATIVITY 8
112#define L1I_SETS 64
113#define L1I_PARTITIONS 1
114/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117#define L1I_LINES_PER_TAG 1
118#define L1I_SIZE_KB_AMD 64
119#define L1I_ASSOCIATIVITY_AMD 2
120
121/* Level 2 unified cache: */
122#define L2_LINE_SIZE 64
123#define L2_ASSOCIATIVITY 16
124#define L2_SETS 4096
125#define L2_PARTITIONS 1
126/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130#define L2_LINES_PER_TAG 1
131#define L2_SIZE_KB_AMD 512
132
133/* No L3 cache: */
134#define L3_SIZE_KB 0 /* disabled */
135#define L3_ASSOCIATIVITY 0 /* disabled */
136#define L3_LINES_PER_TAG 0 /* disabled */
137#define L3_LINE_SIZE 0 /* disabled */
138
139/* TLB definitions: */
140
141#define L1_DTLB_2M_ASSOC 1
142#define L1_DTLB_2M_ENTRIES 255
143#define L1_DTLB_4K_ASSOC 1
144#define L1_DTLB_4K_ENTRIES 255
145
146#define L1_ITLB_2M_ASSOC 1
147#define L1_ITLB_2M_ENTRIES 255
148#define L1_ITLB_4K_ASSOC 1
149#define L1_ITLB_4K_ENTRIES 255
150
151#define L2_DTLB_2M_ASSOC 0 /* disabled */
152#define L2_DTLB_2M_ENTRIES 0 /* disabled */
153#define L2_DTLB_4K_ASSOC 4
154#define L2_DTLB_4K_ENTRIES 512
155
156#define L2_ITLB_2M_ASSOC 0 /* disabled */
157#define L2_ITLB_2M_ENTRIES 0 /* disabled */
158#define L2_ITLB_4K_ASSOC 4
159#define L2_ITLB_4K_ENTRIES 512
160
161
162
99b88a17
IM		 163static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165{
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173}
174
c6dc6f63
AP		 175/* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188};
189static const char *ext_feature_name[] = {
f370be3c 190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 191 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 192 "tm2", "ssse3", "cid", NULL,
e117f772 193 "fma", "cx16", "xtpr", "pdcm",
434acb81 194 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 196 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 197 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 198};
3b671a40
EH		 199/* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
c6dc6f63 204static const char *ext2_feature_name[] = {
3b671a40
EH		 205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 212 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 213};
214static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 217 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 222 NULL, NULL, NULL, NULL,
223};
224
89e49c8b
EH		 225static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234};
235
c6dc6f63 236static const char *kvm_feature_name[] = {
c3d39807 237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 245};
246
296acb64
JR		 247static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256};
257
a9321a4d 258static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263};
264
5ef57876
EH		 265typedef struct FeatureWordInfo {
266 const char **feat_names;
04d104b6
EH		 267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
5ef57876
EH		 271} FeatureWordInfo;
272
273static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
89e49c8b
EH		 290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
bffd67b0
EH		 294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
bffd67b0 307 },
5ef57876
EH		 308};
309
8e8aba50
EH		 310typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315} X86RegisterInfo32;
316
317#define REGISTER(reg) \
5d371f41 318 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 319static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328};
329#undef REGISTER
330
2560f19f
PB		 331typedef struct ExtSaveArea {
332 uint32_t feature, bits;
333 uint32_t offset, size;
334} ExtSaveArea;
335
336static const ExtSaveArea ext_save_areas[] = {
337 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 338 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 339 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
340 .offset = 0x3c0, .size = 0x40 },
341 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 342 .offset = 0x400, .size = 0x40 },
2560f19f 343};
8e8aba50 344
8b4beddc
EH		 345const char *get_register_name_32(unsigned int reg)
346{
31ccdde2 347 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 348 return NULL;
349 }
8e8aba50 350 return x86_reg_info_32[reg].name;
8b4beddc
EH		 351}
352
c6dc6f63
AP		 353/* collects per-function cpuid data
354 */
355typedef struct model_features_t {
356 uint32_t *guest_feat;
357 uint32_t *host_feat;
bffd67b0 358 FeatureWord feat_word;
8b4beddc 359} model_features_t;
c6dc6f63 360
5fcca9ff
EH		 361/* KVM-specific features that are automatically added to all CPU models
362 * when KVM is enabled.
363 */
364static uint32_t kvm_default_features[FEATURE_WORDS] = {
365 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 366 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 367 (1 << KVM_FEATURE_CLOCKSOURCE2) |
368 (1 << KVM_FEATURE_ASYNC_PF) |
369 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 370 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 371 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 372 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 373};
dc59944b 374
8fb4f821 375void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
dc59944b 376{
8fb4f821 377 kvm_default_features[w] &= ~features;
dc59944b
MT		 378}
379
bb44e0d1
JK		 380void host_cpuid(uint32_t function, uint32_t count,
381 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 382{
a1fd24af
AL		 383 uint32_t vec[4];
384
385#ifdef __x86_64__
386 asm volatile("cpuid"
387 : "=a"(vec[0]), "=b"(vec[1]),
388 "=c"(vec[2]), "=d"(vec[3])
389 : "0"(function), "c"(count) : "cc");
c1f41226 390#elif defined(__i386__)
a1fd24af
AL		 391 asm volatile("pusha \n\t"
392 "cpuid \n\t"
393 "mov %%eax, 0(%2) \n\t"
394 "mov %%ebx, 4(%2) \n\t"
395 "mov %%ecx, 8(%2) \n\t"
396 "mov %%edx, 12(%2) \n\t"
397 "popa"
398 : : "a"(function), "c"(count), "S"(vec)
399 : "memory", "cc");
c1f41226
EH		 400#else
401 abort();
a1fd24af
AL		 402#endif
403
bdde476a 404 if (eax)
a1fd24af 405 *eax = vec[0];
bdde476a 406 if (ebx)
a1fd24af 407 *ebx = vec[1];
bdde476a 408 if (ecx)
a1fd24af 409 *ecx = vec[2];
bdde476a 410 if (edx)
a1fd24af 411 *edx = vec[3];
bdde476a 412}
c6dc6f63
AP		 413
414#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
415
416/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
417 * a substring. ex if !NULL points to the first char after a substring,
418 * otherwise the string is assumed to sized by a terminating nul.
419 * Return lexical ordering of *s1:*s2.
420 */
421static int sstrcmp(const char *s1, const char *e1, const char *s2,
422 const char *e2)
423{
424 for (;;) {
425 if (!*s1 || !*s2 || *s1 != *s2)
426 return (*s1 - *s2);
427 ++s1, ++s2;
428 if (s1 == e1 && s2 == e2)
429 return (0);
430 else if (s1 == e1)
431 return (*s2);
432 else if (s2 == e2)
433 return (*s1);
434 }
435}
436
437/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
438 * '|' delimited (possibly empty) strings in which case search for a match
439 * within the alternatives proceeds left to right. Return 0 for success,
440 * non-zero otherwise.
441 */
442static int altcmp(const char *s, const char *e, const char *altstr)
443{
444 const char *p, *q;
445
446 for (q = p = altstr; ; ) {
447 while (*p && *p != '|')
448 ++p;
449 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
450 return (0);
451 if (!*p)
452 return (1);
453 else
454 q = ++p;
455 }
456}
457
458/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 459 * *pval and return true, otherwise return false
c6dc6f63 460 */
e41e0fc6
JK		 461static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
462 const char **featureset)
c6dc6f63
AP		 463{
464 uint32_t mask;
465 const char **ppc;
e41e0fc6 466 bool found = false;
c6dc6f63 467
e41e0fc6 468 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 469 if (*ppc && !altcmp(s, e, *ppc)) {
470 *pval |= mask;
e41e0fc6 471 found = true;
c6dc6f63 472 }
e41e0fc6
JK		 473 }
474 return found;
c6dc6f63
AP		 475}
476
5ef57876
EH		 477static void add_flagname_to_bitmaps(const char *flagname,
478 FeatureWordArray words)
c6dc6f63 479{
5ef57876
EH		 480 FeatureWord w;
481 for (w = 0; w < FEATURE_WORDS; w++) {
482 FeatureWordInfo *wi = &feature_word_info[w];
483 if (wi->feat_names &&
484 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
485 break;
486 }
487 }
488 if (w == FEATURE_WORDS) {
489 fprintf(stderr, "CPU feature %s not found\n", flagname);
490 }
c6dc6f63
AP		 491}
492
d940ee9b
EH		 493/* CPU class name definitions: */
494
495#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
496#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
497
498/* Return type name for a given CPU model name
499 * Caller is responsible for freeing the returned string.
500 */
501static char *x86_cpu_type_name(const char *model_name)
502{
503 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
504}
505
500050d1
AF		 506static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
507{
d940ee9b
EH		 508 ObjectClass *oc;
509 char *typename;
510
500050d1
AF		 511 if (cpu_model == NULL) {
512 return NULL;
513 }
514
d940ee9b
EH		 515 typename = x86_cpu_type_name(cpu_model);
516 oc = object_class_by_name(typename);
517 g_free(typename);
518 return oc;
500050d1
AF		 519}
520
d940ee9b 521struct X86CPUDefinition {
c6dc6f63
AP		 522 const char *name;
523 uint32_t level;
90e4b0c3
EH		 524 uint32_t xlevel;
525 uint32_t xlevel2;
99b88a17
IM		 526 /* vendor is zero-terminated, 12 character ASCII string */
527 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 528 int family;
529 int model;
530 int stepping;
0514ef2f 531 FeatureWordArray features;
c6dc6f63 532 char model_id[48];
787aaf57 533 bool cache_info_passthrough;
d940ee9b 534};
c6dc6f63
AP		 535
536#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
537#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
538 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
539#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
540 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
541 CPUID_PSE36 | CPUID_FXSR)
542#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
543#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
544 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
545 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
546 CPUID_PAE | CPUID_SEP | CPUID_APIC)
547
551a2dec
AP		 548#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
549 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
550 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
551 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
552 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 553 /* partly implemented:
554 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
555 CPUID_PSE36 (needed for Solaris) */
556 /* missing:
557 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
e71827bc
AJ		 558#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
559 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
560 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
d640045a 561 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
8560efed 562 /* missing:
e71827bc
AJ		 563 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
564 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
565 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
d640045a
AJ		 566 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
567 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
83f7dc28 568 CPUID_EXT_RDRAND */
60032ac0 569#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 570 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
571 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 572 /* missing:
573 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 574#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
575 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 576#define TCG_SVM_FEATURES 0
7073fbad 577#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
cd7f97ca 578 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
111994ee 579 /* missing:
7073fbad
RH		 580 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
581 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
cd7f97ca 582 CPUID_7_0_EBX_RDSEED */
551a2dec 583
9576de75 584static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 585 {
586 .name = "qemu64",
587 .level = 4,
99b88a17 588 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 589 .family = 6,
f8e6a11a 590 .model = 6,
c6dc6f63 591 .stepping = 3,
0514ef2f 592 .features[FEAT_1_EDX] =
27861ecc 593 PPRO_FEATURES |
c6dc6f63 594 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 595 CPUID_PSE36,
0514ef2f 596 .features[FEAT_1_ECX] =
27861ecc 597 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 598 .features[FEAT_8000_0001_EDX] =
27861ecc 599 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 600 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 601 .features[FEAT_8000_0001_ECX] =
27861ecc 602 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 603 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
604 .xlevel = 0x8000000A,
c6dc6f63
AP		 605 },
606 {
607 .name = "phenom",
608 .level = 5,
99b88a17 609 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 610 .family = 16,
611 .model = 2,
612 .stepping = 3,
0514ef2f 613 .features[FEAT_1_EDX] =
27861ecc 614 PPRO_FEATURES |
c6dc6f63 615 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 616 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 617 .features[FEAT_1_ECX] =
27861ecc 618 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 619 CPUID_EXT_POPCNT,
0514ef2f 620 .features[FEAT_8000_0001_EDX] =
27861ecc 621 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 622 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
623 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 624 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 625 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
626 CPUID_EXT3_CR8LEG,
627 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
628 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 629 .features[FEAT_8000_0001_ECX] =
27861ecc 630 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 631 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 632 .features[FEAT_SVM] =
27861ecc 633 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 634 .xlevel = 0x8000001A,
635 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
636 },
637 {
638 .name = "core2duo",
639 .level = 10,
99b88a17 640 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 641 .family = 6,
642 .model = 15,
643 .stepping = 11,
0514ef2f 644 .features[FEAT_1_EDX] =
27861ecc 645 PPRO_FEATURES |
c6dc6f63 646 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 647 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
648 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 649 .features[FEAT_1_ECX] =
27861ecc 650 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 651 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
652 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 653 .features[FEAT_8000_0001_EDX] =
27861ecc 654 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 655 .features[FEAT_8000_0001_ECX] =
27861ecc 656 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 657 .xlevel = 0x80000008,
658 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
659 },
660 {
661 .name = "kvm64",
662 .level = 5,
99b88a17 663 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 664 .family = 15,
665 .model = 6,
666 .stepping = 1,
667 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 668 .features[FEAT_1_EDX] =
27861ecc 669 PPRO_FEATURES |
c6dc6f63
AP		 670 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
671 CPUID_PSE36,
672 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 673 .features[FEAT_1_ECX] =
27861ecc 674 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 675 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 676 .features[FEAT_8000_0001_EDX] =
27861ecc 677 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 678 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
679 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
680 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
681 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
682 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 683 .features[FEAT_8000_0001_ECX] =
27861ecc 684 0,
c6dc6f63
AP		 685 .xlevel = 0x80000008,
686 .model_id = "Common KVM processor"
687 },
c6dc6f63
AP		 688 {
689 .name = "qemu32",
690 .level = 4,
99b88a17 691 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 692 .family = 6,
f8e6a11a 693 .model = 6,
c6dc6f63 694 .stepping = 3,
0514ef2f 695 .features[FEAT_1_EDX] =
27861ecc 696 PPRO_FEATURES,
0514ef2f 697 .features[FEAT_1_ECX] =
27861ecc 698 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 699 .xlevel = 0x80000004,
c6dc6f63 700 },
eafaf1e5
AP		 701 {
702 .name = "kvm32",
703 .level = 5,
99b88a17 704 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 705 .family = 15,
706 .model = 6,
707 .stepping = 1,
0514ef2f 708 .features[FEAT_1_EDX] =
27861ecc 709 PPRO_FEATURES |
eafaf1e5 710 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 711 .features[FEAT_1_ECX] =
27861ecc 712 CPUID_EXT_SSE3,
0514ef2f 713 .features[FEAT_8000_0001_EDX] =
27861ecc 714 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 715 .features[FEAT_8000_0001_ECX] =
27861ecc 716 0,
eafaf1e5
AP		 717 .xlevel = 0x80000008,
718 .model_id = "Common 32-bit KVM processor"
719 },
c6dc6f63
AP		 720 {
721 .name = "coreduo",
722 .level = 10,
99b88a17 723 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 724 .family = 6,
725 .model = 14,
726 .stepping = 8,
0514ef2f 727 .features[FEAT_1_EDX] =
27861ecc 728 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 729 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
730 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 731 .features[FEAT_1_ECX] =
27861ecc 732 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 733 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 734 .features[FEAT_8000_0001_EDX] =
27861ecc 735 CPUID_EXT2_NX,
c6dc6f63
AP		 736 .xlevel = 0x80000008,
737 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
738 },
739 {
740 .name = "486",
58012d66 741 .level = 1,
99b88a17 742 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 743 .family = 4,
b2a856d9 744 .model = 8,
c6dc6f63 745 .stepping = 0,
0514ef2f 746 .features[FEAT_1_EDX] =
27861ecc 747 I486_FEATURES,
c6dc6f63
AP		 748 .xlevel = 0,
749 },
750 {
751 .name = "pentium",
752 .level = 1,
99b88a17 753 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 754 .family = 5,
755 .model = 4,
756 .stepping = 3,
0514ef2f 757 .features[FEAT_1_EDX] =
27861ecc 758 PENTIUM_FEATURES,
c6dc6f63
AP		 759 .xlevel = 0,
760 },
761 {
762 .name = "pentium2",
763 .level = 2,
99b88a17 764 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 765 .family = 6,
766 .model = 5,
767 .stepping = 2,
0514ef2f 768 .features[FEAT_1_EDX] =
27861ecc 769 PENTIUM2_FEATURES,
c6dc6f63
AP		 770 .xlevel = 0,
771 },
772 {
773 .name = "pentium3",
774 .level = 2,
99b88a17 775 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 776 .family = 6,
777 .model = 7,
778 .stepping = 3,
0514ef2f 779 .features[FEAT_1_EDX] =
27861ecc 780 PENTIUM3_FEATURES,
c6dc6f63
AP		 781 .xlevel = 0,
782 },
783 {
784 .name = "athlon",
785 .level = 2,
99b88a17 786 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 787 .family = 6,
788 .model = 2,
789 .stepping = 3,
0514ef2f 790 .features[FEAT_1_EDX] =
27861ecc 791 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 792 CPUID_MCA,
0514ef2f 793 .features[FEAT_8000_0001_EDX] =
27861ecc 794 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 795 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 796 .xlevel = 0x80000008,
c6dc6f63
AP		 797 },
798 {
799 .name = "n270",
800 /* original is on level 10 */
801 .level = 5,
99b88a17 802 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 803 .family = 6,
804 .model = 28,
805 .stepping = 2,
0514ef2f 806 .features[FEAT_1_EDX] =
27861ecc 807 PPRO_FEATURES |
8560efed
AJ		 808 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
809 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 810 /* Some CPUs got no CPUID_SEP */
0514ef2f 811 .features[FEAT_1_ECX] =
27861ecc 812 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 813 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
814 CPUID_EXT_MOVBE,
0514ef2f 815 .features[FEAT_8000_0001_EDX] =
27861ecc 816 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 817 CPUID_EXT2_NX,
0514ef2f 818 .features[FEAT_8000_0001_ECX] =
27861ecc 819 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 820 .xlevel = 0x8000000A,
821 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
822 },
3eca4642
EH		 823 {
824 .name = "Conroe",
6b11322e 825 .level = 4,
99b88a17 826 .vendor = CPUID_VENDOR_INTEL,
3eca4642 827 .family = 6,
ffce9ebb 828 .model = 15,
3eca4642 829 .stepping = 3,
0514ef2f 830 .features[FEAT_1_EDX] =
27861ecc 831 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 832 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
833 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
834 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
835 CPUID_DE | CPUID_FP87,
0514ef2f 836 .features[FEAT_1_ECX] =
27861ecc 837 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 838 .features[FEAT_8000_0001_EDX] =
27861ecc 839 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 840 .features[FEAT_8000_0001_ECX] =
27861ecc 841 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 842 .xlevel = 0x8000000A,
843 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
844 },
845 {
846 .name = "Penryn",
6b11322e 847 .level = 4,
99b88a17 848 .vendor = CPUID_VENDOR_INTEL,
3eca4642 849 .family = 6,
ffce9ebb 850 .model = 23,
3eca4642 851 .stepping = 3,
0514ef2f 852 .features[FEAT_1_EDX] =
27861ecc 853 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 854 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
855 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
856 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
857 CPUID_DE | CPUID_FP87,
0514ef2f 858 .features[FEAT_1_ECX] =
27861ecc 859 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 860 CPUID_EXT_SSE3,
0514ef2f 861 .features[FEAT_8000_0001_EDX] =
27861ecc 862 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 863 .features[FEAT_8000_0001_ECX] =
27861ecc 864 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 865 .xlevel = 0x8000000A,
866 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
867 },
868 {
869 .name = "Nehalem",
6b11322e 870 .level = 4,
99b88a17 871 .vendor = CPUID_VENDOR_INTEL,
3eca4642 872 .family = 6,
ffce9ebb 873 .model = 26,
3eca4642 874 .stepping = 3,
0514ef2f 875 .features[FEAT_1_EDX] =
27861ecc 876 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 877 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
878 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
879 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
880 CPUID_DE | CPUID_FP87,
0514ef2f 881 .features[FEAT_1_ECX] =
27861ecc 882 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 883 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 884 .features[FEAT_8000_0001_EDX] =
27861ecc 885 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 886 .features[FEAT_8000_0001_ECX] =
27861ecc 887 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 888 .xlevel = 0x8000000A,
889 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
890 },
891 {
892 .name = "Westmere",
893 .level = 11,
99b88a17 894 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 895 .family = 6,
896 .model = 44,
897 .stepping = 1,
0514ef2f 898 .features[FEAT_1_EDX] =
27861ecc 899 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 900 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
901 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
902 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
903 CPUID_DE | CPUID_FP87,
0514ef2f 904 .features[FEAT_1_ECX] =
27861ecc 905 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 906 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 907 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 908 .features[FEAT_8000_0001_EDX] =
27861ecc 909 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 910 .features[FEAT_8000_0001_ECX] =
27861ecc 911 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 912 .xlevel = 0x8000000A,
913 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
914 },
915 {
916 .name = "SandyBridge",
917 .level = 0xd,
99b88a17 918 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 919 .family = 6,
920 .model = 42,
921 .stepping = 1,
0514ef2f 922 .features[FEAT_1_EDX] =
27861ecc 923 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 924 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
925 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
926 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
927 CPUID_DE | CPUID_FP87,
0514ef2f 928 .features[FEAT_1_ECX] =
27861ecc 929 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 930 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
931 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
932 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
933 CPUID_EXT_SSE3,
0514ef2f 934 .features[FEAT_8000_0001_EDX] =
27861ecc 935 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 936 CPUID_EXT2_SYSCALL,
0514ef2f 937 .features[FEAT_8000_0001_ECX] =
27861ecc 938 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 939 .xlevel = 0x8000000A,
940 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
941 },
37507094
EH		 942 {
943 .name = "Haswell",
944 .level = 0xd,
99b88a17 945 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 946 .family = 6,
947 .model = 60,
948 .stepping = 1,
0514ef2f 949 .features[FEAT_1_EDX] =
27861ecc 950 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 951 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 952 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 953 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
954 CPUID_DE | CPUID_FP87,
0514ef2f 955 .features[FEAT_1_ECX] =
27861ecc 956 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH		 957 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
958 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
959 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
960 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
961 CPUID_EXT_PCID,
0514ef2f 962 .features[FEAT_8000_0001_EDX] =
27861ecc 963 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 964 CPUID_EXT2_SYSCALL,
0514ef2f 965 .features[FEAT_8000_0001_ECX] =
27861ecc 966 CPUID_EXT3_LAHF_LM,
0514ef2f 967 .features[FEAT_7_0_EBX] =
27861ecc 968 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 969 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
970 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
971 CPUID_7_0_EBX_RTM,
972 .xlevel = 0x8000000A,
973 .model_id = "Intel Core Processor (Haswell)",
974 },
3eca4642
EH		 975 {
976 .name = "Opteron_G1",
977 .level = 5,
99b88a17 978 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 979 .family = 15,
980 .model = 6,
981 .stepping = 1,
0514ef2f 982 .features[FEAT_1_EDX] =
27861ecc 983 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 984 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
985 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
986 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
987 CPUID_DE | CPUID_FP87,
0514ef2f 988 .features[FEAT_1_ECX] =
27861ecc 989 CPUID_EXT_SSE3,
0514ef2f 990 .features[FEAT_8000_0001_EDX] =
27861ecc 991 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH		 992 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
993 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
994 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
995 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
996 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
997 .xlevel = 0x80000008,
998 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
999 },
1000 {
1001 .name = "Opteron_G2",
1002 .level = 5,
99b88a17 1003 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1004 .family = 15,
1005 .model = 6,
1006 .stepping = 1,
0514ef2f 1007 .features[FEAT_1_EDX] =
27861ecc 1008 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1009 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1010 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1011 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1012 CPUID_DE | CPUID_FP87,
0514ef2f 1013 .features[FEAT_1_ECX] =
27861ecc 1014 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1015 .features[FEAT_8000_0001_EDX] =
27861ecc 1016 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1017 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1018 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1019 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1020 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1021 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1022 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1023 .features[FEAT_8000_0001_ECX] =
27861ecc 1024 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1025 .xlevel = 0x80000008,
1026 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1027 },
1028 {
1029 .name = "Opteron_G3",
1030 .level = 5,
99b88a17 1031 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1032 .family = 15,
1033 .model = 6,
1034 .stepping = 1,
0514ef2f 1035 .features[FEAT_1_EDX] =
27861ecc 1036 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1037 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1038 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1039 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1040 CPUID_DE | CPUID_FP87,
0514ef2f 1041 .features[FEAT_1_ECX] =
27861ecc 1042 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1043 CPUID_EXT_SSE3,
0514ef2f 1044 .features[FEAT_8000_0001_EDX] =
27861ecc 1045 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1046 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1047 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1048 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1049 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1050 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1051 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1052 .features[FEAT_8000_0001_ECX] =
27861ecc 1053 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH		 1054 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1055 .xlevel = 0x80000008,
1056 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1057 },
1058 {
1059 .name = "Opteron_G4",
1060 .level = 0xd,
99b88a17 1061 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1062 .family = 21,
1063 .model = 1,
1064 .stepping = 2,
0514ef2f 1065 .features[FEAT_1_EDX] =
27861ecc 1066 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1067 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1068 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1069 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1070 CPUID_DE | CPUID_FP87,
0514ef2f 1071 .features[FEAT_1_ECX] =
27861ecc 1072 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 1073 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1074 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1075 CPUID_EXT_SSE3,
0514ef2f 1076 .features[FEAT_8000_0001_EDX] =
27861ecc 1077 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH		 1078 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1079 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1080 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1081 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1082 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1083 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1084 .features[FEAT_8000_0001_ECX] =
27861ecc 1085 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH		 1086 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1087 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1088 CPUID_EXT3_LAHF_LM,
1089 .xlevel = 0x8000001A,
1090 .model_id = "AMD Opteron 62xx class CPU",
1091 },
021941b9
AP		 1092 {
1093 .name = "Opteron_G5",
1094 .level = 0xd,
99b88a17 1095 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1096 .family = 21,
1097 .model = 2,
1098 .stepping = 0,
0514ef2f 1099 .features[FEAT_1_EDX] =
27861ecc 1100 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP		 1101 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1102 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1103 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1104 CPUID_DE | CPUID_FP87,
0514ef2f 1105 .features[FEAT_1_ECX] =
27861ecc 1106 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP		 1107 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1108 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1109 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1110 .features[FEAT_8000_0001_EDX] =
27861ecc 1111 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP		 1112 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1113 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1114 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1115 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1116 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1117 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1118 .features[FEAT_8000_0001_ECX] =
27861ecc 1119 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP		 1120 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1121 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1122 CPUID_EXT3_LAHF_LM,
1123 .xlevel = 0x8000001A,
1124 .model_id = "AMD Opteron 63xx class CPU",
1125 },
c6dc6f63
AP		 1126};
1127
0668af54
EH		 1128/**
1129 * x86_cpu_compat_set_features:
1130 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1131 * @w: Identifies the feature word to be changed.
1132 * @feat_add: Feature bits to be added to feature word
1133 * @feat_remove: Feature bits to be removed from feature word
1134 *
1135 * Change CPU model feature bits for compatibility.
1136 *
1137 * This function may be used by machine-type compatibility functions
1138 * to enable or disable feature bits on specific CPU models.
1139 */
1140void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1141 uint32_t feat_add, uint32_t feat_remove)
1142{
9576de75 1143 X86CPUDefinition *def;
0668af54
EH		 1144 int i;
1145 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1146 def = &builtin_x86_defs[i];
1147 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1148 def->features[w] |= feat_add;
1149 def->features[w] &= ~feat_remove;
1150 }
1151 }
1152}
1153
d940ee9b
EH		 1154#ifdef CONFIG_KVM
1155
c6dc6f63
AP		 1156static int cpu_x86_fill_model_id(char *str)
1157{
1158 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1159 int i;
1160
1161 for (i = 0; i < 3; i++) {
1162 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1163 memcpy(str + i * 16 + 0, &eax, 4);
1164 memcpy(str + i * 16 + 4, &ebx, 4);
1165 memcpy(str + i * 16 + 8, &ecx, 4);
1166 memcpy(str + i * 16 + 12, &edx, 4);
1167 }
1168 return 0;
1169}
1170
d940ee9b
EH		 1171static X86CPUDefinition host_cpudef;
1172
1173/* class_init for the "host" CPU model
6e746f30 1174 *
d940ee9b 1175 * This function may be called before KVM is initialized.
6e746f30 1176 */
d940ee9b 1177static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1178{
d940ee9b 1179 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1180 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1181
d940ee9b 1182 xcc->kvm_required = true;
6e746f30 1183
c6dc6f63 1184 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1185 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1186
1187 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1188 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1189 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1190 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1191
d940ee9b 1192 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1193
d940ee9b
EH		 1194 xcc->cpu_def = &host_cpudef;
1195 host_cpudef.cache_info_passthrough = true;
1196
1197 /* level, xlevel, xlevel2, and the feature words are initialized on
1198 * instance_init, because they require KVM to be initialized.
1199 */
1200}
1201
1202static void host_x86_cpu_initfn(Object *obj)
1203{
1204 X86CPU *cpu = X86_CPU(obj);
1205 CPUX86State *env = &cpu->env;
1206 KVMState *s = kvm_state;
1207 FeatureWord w;
1208
1209 assert(kvm_enabled());
1210
1211 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1212 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1213 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1214
2bc65d2b
EH		 1215 for (w = 0; w < FEATURE_WORDS; w++) {
1216 FeatureWordInfo *wi = &feature_word_info[w];
d940ee9b 1217 env->features[w] =
2bc65d2b
EH		 1218 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1219 wi->cpuid_reg);
1220 }
d940ee9b 1221 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1222}
1223
d940ee9b
EH		 1224static const TypeInfo host_x86_cpu_type_info = {
1225 .name = X86_CPU_TYPE_NAME("host"),
1226 .parent = TYPE_X86_CPU,
1227 .instance_init = host_x86_cpu_initfn,
1228 .class_init = host_x86_cpu_class_init,
1229};
1230
1231#endif
1232
bffd67b0 1233static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 1234{
1235 int i;
1236
1237 for (i = 0; i < 32; ++i)
1238 if (1 << i & mask) {
bffd67b0 1239 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1240 assert(reg);
1241 fprintf(stderr, "warning: host doesn't support requested feature: "
1242 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1243 f->cpuid_eax, reg,
1244 f->feat_names[i] ? "." : "",
1245 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 1246 break;
1247 }
1248 return 0;
1249}
1250
07ca5945
EH		 1251/* Check if all requested cpu flags are making their way to the guest
1252 *
1253 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 1254 *
1255 * This function may be called only if KVM is enabled.
c6dc6f63 1256 */
f0b9b111 1257static int kvm_check_features_against_host(KVMState *s, X86CPU *cpu)
c6dc6f63 1258{
5ec01c2e 1259 CPUX86State *env = &cpu->env;
f0b9b111
EH		 1260 int rv = 0;
1261 FeatureWord w;
c6dc6f63 1262
6e746f30
EH		 1263 assert(kvm_enabled());
1264
f0b9b111 1265 for (w = 0; w < FEATURE_WORDS; w++) {
bffd67b0 1266 FeatureWordInfo *wi = &feature_word_info[w];
f0b9b111
EH		 1267 uint32_t guest_feat = env->features[w];
1268 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1269 wi->cpuid_ecx,
1270 wi->cpuid_reg);
1271 uint32_t mask;
bffd67b0 1272 for (mask = 1; mask; mask <<= 1) {
f0b9b111 1273 if (guest_feat & mask && !(host_feat & mask)) {
bffd67b0
EH		 1274 unavailable_host_feature(wi, mask);
1275 rv = 1;
1276 }
1277 }
1278 }
c6dc6f63
AP		 1279 return rv;
1280}
1281
95b8519d
AF		 1282static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1283 const char *name, Error **errp)
1284{
1285 X86CPU *cpu = X86_CPU(obj);
1286 CPUX86State *env = &cpu->env;
1287 int64_t value;
1288
1289 value = (env->cpuid_version >> 8) & 0xf;
1290 if (value == 0xf) {
1291 value += (env->cpuid_version >> 20) & 0xff;
1292 }
1293 visit_type_int(v, &value, name, errp);
1294}
1295
71ad61d3
AF		 1296static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1297 const char *name, Error **errp)
ed5e1ec3 1298{
71ad61d3
AF		 1299 X86CPU *cpu = X86_CPU(obj);
1300 CPUX86State *env = &cpu->env;
1301 const int64_t min = 0;
1302 const int64_t max = 0xff + 0xf;
65cd9064 1303 Error *local_err = NULL;
71ad61d3
AF		 1304 int64_t value;
1305
65cd9064
MA		 1306 visit_type_int(v, &value, name, &local_err);
1307 if (local_err) {
1308 error_propagate(errp, local_err);
71ad61d3
AF		 1309 return;
1310 }
1311 if (value < min || value > max) {
1312 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1313 name ? name : "null", value, min, max);
1314 return;
1315 }
1316
ed5e1ec3 1317 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1318 if (value > 0x0f) {
1319 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1320 } else {
71ad61d3 1321 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1322 }
1323}
1324
67e30c83
AF		 1325static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1326 const char *name, Error **errp)
1327{
1328 X86CPU *cpu = X86_CPU(obj);
1329 CPUX86State *env = &cpu->env;
1330 int64_t value;
1331
1332 value = (env->cpuid_version >> 4) & 0xf;
1333 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1334 visit_type_int(v, &value, name, errp);
1335}
1336
c5291a4f
AF		 1337static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1338 const char *name, Error **errp)
b0704cbd 1339{
c5291a4f
AF		 1340 X86CPU *cpu = X86_CPU(obj);
1341 CPUX86State *env = &cpu->env;
1342 const int64_t min = 0;
1343 const int64_t max = 0xff;
65cd9064 1344 Error *local_err = NULL;
c5291a4f
AF		 1345 int64_t value;
1346
65cd9064
MA		 1347 visit_type_int(v, &value, name, &local_err);
1348 if (local_err) {
1349 error_propagate(errp, local_err);
c5291a4f
AF		 1350 return;
1351 }
1352 if (value < min || value > max) {
1353 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1354 name ? name : "null", value, min, max);
1355 return;
1356 }
1357
b0704cbd 1358 env->cpuid_version &= ~0xf00f0;
c5291a4f 1359 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1360}
1361
35112e41
AF		 1362static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1363 void *opaque, const char *name,
1364 Error **errp)
1365{
1366 X86CPU *cpu = X86_CPU(obj);
1367 CPUX86State *env = &cpu->env;
1368 int64_t value;
1369
1370 value = env->cpuid_version & 0xf;
1371 visit_type_int(v, &value, name, errp);
1372}
1373
036e2222
AF		 1374static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1375 void *opaque, const char *name,
1376 Error **errp)
38c3dc46 1377{
036e2222
AF		 1378 X86CPU *cpu = X86_CPU(obj);
1379 CPUX86State *env = &cpu->env;
1380 const int64_t min = 0;
1381 const int64_t max = 0xf;
65cd9064 1382 Error *local_err = NULL;
036e2222
AF		 1383 int64_t value;
1384
65cd9064
MA		 1385 visit_type_int(v, &value, name, &local_err);
1386 if (local_err) {
1387 error_propagate(errp, local_err);
036e2222
AF		 1388 return;
1389 }
1390 if (value < min || value > max) {
1391 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1392 name ? name : "null", value, min, max);
1393 return;
1394 }
1395
38c3dc46 1396 env->cpuid_version &= ~0xf;
036e2222 1397 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1398}
1399
8e1898bf
AF		 1400static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1401 const char *name, Error **errp)
1402{
1403 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1404
fa029887 1405 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1406}
1407
1408static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1409 const char *name, Error **errp)
1410{
1411 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1412
fa029887 1413 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1414}
1415
16b93aa8
AF		 1416static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1417 const char *name, Error **errp)
1418{
1419 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1420
fa029887 1421 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1422}
1423
1424static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1425 const char *name, Error **errp)
1426{
1427 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1428
fa029887 1429 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1430}
1431
d480e1af
AF		 1432static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1433{
1434 X86CPU *cpu = X86_CPU(obj);
1435 CPUX86State *env = &cpu->env;
1436 char *value;
d480e1af 1437
9df694ee 1438 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1439 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1440 env->cpuid_vendor3);
d480e1af
AF		 1441 return value;
1442}
1443
1444static void x86_cpuid_set_vendor(Object *obj, const char *value,
1445 Error **errp)
1446{
1447 X86CPU *cpu = X86_CPU(obj);
1448 CPUX86State *env = &cpu->env;
1449 int i;
1450
9df694ee 1451 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1452 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1453 "vendor", value);
1454 return;
1455 }
1456
1457 env->cpuid_vendor1 = 0;
1458 env->cpuid_vendor2 = 0;
1459 env->cpuid_vendor3 = 0;
1460 for (i = 0; i < 4; i++) {
1461 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1462 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1463 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1464 }
d480e1af
AF		 1465}
1466
63e886eb
AF		 1467static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1468{
1469 X86CPU *cpu = X86_CPU(obj);
1470 CPUX86State *env = &cpu->env;
1471 char *value;
1472 int i;
1473
1474 value = g_malloc(48 + 1);
1475 for (i = 0; i < 48; i++) {
1476 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1477 }
1478 value[48] = '\0';
1479 return value;
1480}
1481
938d4c25
AF		 1482static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1483 Error **errp)
dcce6675 1484{
938d4c25
AF		 1485 X86CPU *cpu = X86_CPU(obj);
1486 CPUX86State *env = &cpu->env;
dcce6675
AF		 1487 int c, len, i;
1488
1489 if (model_id == NULL) {
1490 model_id = "";
1491 }
1492 len = strlen(model_id);
d0a6acf4 1493 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1494 for (i = 0; i < 48; i++) {
1495 if (i >= len) {
1496 c = '\0';
1497 } else {
1498 c = (uint8_t)model_id[i];
1499 }
1500 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1501 }
1502}
1503
89e48965
AF		 1504static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1505 const char *name, Error **errp)
1506{
1507 X86CPU *cpu = X86_CPU(obj);
1508 int64_t value;
1509
1510 value = cpu->env.tsc_khz * 1000;
1511 visit_type_int(v, &value, name, errp);
1512}
1513
1514static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1515 const char *name, Error **errp)
1516{
1517 X86CPU *cpu = X86_CPU(obj);
1518 const int64_t min = 0;
2e84849a 1519 const int64_t max = INT64_MAX;
65cd9064 1520 Error *local_err = NULL;
89e48965
AF		 1521 int64_t value;
1522
65cd9064
MA		 1523 visit_type_int(v, &value, name, &local_err);
1524 if (local_err) {
1525 error_propagate(errp, local_err);
89e48965
AF		 1526 return;
1527 }
1528 if (value < min || value > max) {
1529 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1530 name ? name : "null", value, min, max);
1531 return;
1532 }
1533
1534 cpu->env.tsc_khz = value / 1000;
1535}
1536
31050930
IM		 1537static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1538 const char *name, Error **errp)
1539{
1540 X86CPU *cpu = X86_CPU(obj);
1541 int64_t value = cpu->env.cpuid_apic_id;
1542
1543 visit_type_int(v, &value, name, errp);
1544}
1545
1546static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1547 const char *name, Error **errp)
1548{
1549 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1550 DeviceState *dev = DEVICE(obj);
31050930
IM		 1551 const int64_t min = 0;
1552 const int64_t max = UINT32_MAX;
1553 Error *error = NULL;
1554 int64_t value;
1555
8d6d4980
IM		 1556 if (dev->realized) {
1557 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1558 "it was realized", name, object_get_typename(obj));
1559 return;
1560 }
1561
31050930
IM		 1562 visit_type_int(v, &value, name, &error);
1563 if (error) {
1564 error_propagate(errp, error);
1565 return;
1566 }
1567 if (value < min || value > max) {
1568 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1569 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1570 object_get_typename(obj), name, value, min, max);
1571 return;
1572 }
1573
1574 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1575 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1576 return;
1577 }
1578 cpu->env.cpuid_apic_id = value;
1579}
1580
7e5292b5 1581/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1582static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1583 const char *name, Error **errp)
1584{
7e5292b5 1585 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1586 FeatureWord w;
1587 Error *err = NULL;
1588 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1589 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1590 X86CPUFeatureWordInfoList *list = NULL;
1591
1592 for (w = 0; w < FEATURE_WORDS; w++) {
1593 FeatureWordInfo *wi = &feature_word_info[w];
1594 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1595 qwi->cpuid_input_eax = wi->cpuid_eax;
1596 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1597 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1598 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1599 qwi->features = array[w];
8e8aba50
EH		 1600
1601 /* List will be in reverse order, but order shouldn't matter */
1602 list_entries[w].next = list;
1603 list_entries[w].value = &word_infos[w];
1604 list = &list_entries[w];
1605 }
1606
1607 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1608 error_propagate(errp, err);
1609}
1610
c8f0f88e
IM		 1611static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1612 const char *name, Error **errp)
1613{
1614 X86CPU *cpu = X86_CPU(obj);
1615 int64_t value = cpu->hyperv_spinlock_attempts;
1616
1617 visit_type_int(v, &value, name, errp);
1618}
1619
1620static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1621 const char *name, Error **errp)
1622{
1623 const int64_t min = 0xFFF;
1624 const int64_t max = UINT_MAX;
1625 X86CPU *cpu = X86_CPU(obj);
1626 Error *err = NULL;
1627 int64_t value;
1628
1629 visit_type_int(v, &value, name, &err);
1630 if (err) {
1631 error_propagate(errp, err);
1632 return;
1633 }
1634
1635 if (value < min || value > max) {
1636 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1637 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1638 object_get_typename(obj), name ? name : "null",
1639 value, min, max);
1640 return;
1641 }
1642 cpu->hyperv_spinlock_attempts = value;
1643}
1644
1645static PropertyInfo qdev_prop_spinlocks = {
1646 .name = "int",
1647 .get = x86_get_hv_spinlocks,
1648 .set = x86_set_hv_spinlocks,
1649};
1650
72ac2e87
IM		 1651/* Convert all '_' in a feature string option name to '-', to make feature
1652 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1653 */
1654static inline void feat2prop(char *s)
1655{
1656 while ((s = strchr(s, '_'))) {
1657 *s = '-';
1658 }
1659}
1660
8f961357
EH		 1661/* Parse "+feature,-feature,feature=foo" CPU feature string
1662 */
94a444b2
AF		 1663static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1664 Error **errp)
8f961357 1665{
94a444b2 1666 X86CPU *cpu = X86_CPU(cs);
8f961357
EH		 1667 char *featurestr; /* Single 'key=value" string being parsed */
1668 /* Features to be added */
077c68c3 1669 FeatureWordArray plus_features = { 0 };
8f961357 1670 /* Features to be removed */
5ef57876 1671 FeatureWordArray minus_features = { 0 };
8f961357 1672 uint32_t numvalue;
a91987c2 1673 CPUX86State *env = &cpu->env;
94a444b2 1674 Error *local_err = NULL;
8f961357 1675
8f961357 1676 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1677
1678 while (featurestr) {
1679 char *val;
1680 if (featurestr[0] == '+') {
5ef57876 1681 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1682 } else if (featurestr[0] == '-') {
5ef57876 1683 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1684 } else if ((val = strchr(featurestr, '='))) {
1685 *val = 0; val++;
72ac2e87 1686 feat2prop(featurestr);
d024d209 1687 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1688 char *err;
a91987c2
IM		 1689 char num[32];
1690
c6dc6f63
AP		 1691 numvalue = strtoul(val, &err, 0);
1692 if (!*val || *err) {
94a444b2 1693 error_setg(&local_err, "bad numerical value %s", val);
a91987c2 1694 goto out;
c6dc6f63
AP		 1695 }
1696 if (numvalue < 0x80000000) {
94a444b2
AF		 1697 error_report("xlevel value shall always be >= 0x80000000"
1698 ", fixup will be removed in future versions");
2f7a21c4 1699 numvalue += 0x80000000;
c6dc6f63 1700 }
a91987c2 1701 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1702 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1703 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1704 int64_t tsc_freq;
1705 char *err;
a91987c2 1706 char num[32];
b862d1fe
JR		 1707
1708 tsc_freq = strtosz_suffix_unit(val, &err,
1709 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1710 if (tsc_freq < 0 || *err) {
94a444b2 1711 error_setg(&local_err, "bad numerical value %s", val);
a91987c2 1712 goto out;
b862d1fe 1713 }
a91987c2 1714 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1715 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1716 &local_err);
72ac2e87 1717 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1718 char *err;
92067bf4 1719 const int min = 0xFFF;
c8f0f88e 1720 char num[32];
28f52cc0
VR		 1721 numvalue = strtoul(val, &err, 0);
1722 if (!*val || *err) {
94a444b2 1723 error_setg(&local_err, "bad numerical value %s", val);
a91987c2 1724 goto out;
28f52cc0 1725 }
92067bf4 1726 if (numvalue < min) {
94a444b2
AF		 1727 error_report("hv-spinlocks value shall always be >= 0x%x"
1728 ", fixup will be removed in future versions",
92067bf4
IM		 1729 min);
1730 numvalue = min;
1731 }
c8f0f88e 1732 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1733 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1734 } else {
94a444b2 1735 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1736 }
c6dc6f63 1737 } else {
258f5abe 1738 feat2prop(featurestr);
94a444b2 1739 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1740 }
94a444b2
AF		 1741 if (local_err) {
1742 error_propagate(errp, local_err);
a91987c2 1743 goto out;
c6dc6f63
AP		 1744 }
1745 featurestr = strtok(NULL, ",");
1746 }
0514ef2f
EH		 1747 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1748 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1749 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1750 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1751 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1752 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1753 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1754 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1755 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1756 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1757 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1758 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1759 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1760 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1761 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1762 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63 1763
a91987c2
IM		 1764out:
1765 return;
c6dc6f63
AP		 1766}
1767
1768/* generate a composite string into buf of all cpuid names in featureset
1769 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1770 * if flags, suppress names undefined in featureset.
1771 */
1772static void listflags(char *buf, int bufsize, uint32_t fbits,
1773 const char **featureset, uint32_t flags)
1774{
1775 const char **p = &featureset[31];
1776 char *q, *b, bit;
1777 int nc;
1778
1779 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1780 *buf = '\0';
1781 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1782 if (fbits & 1 << bit && (*p || !flags)) {
1783 if (*p)
1784 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1785 else
1786 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1787 if (bufsize <= nc) {
1788 if (b) {
1789 memcpy(b, "...", sizeof("..."));
1790 }
1791 return;
1792 }
1793 q += nc;
1794 bufsize -= nc;
1795 }
1796}
1797
e916cbf8
PM		 1798/* generate CPU information. */
1799void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1800{
9576de75 1801 X86CPUDefinition *def;
c6dc6f63 1802 char buf[256];
7fc9b714 1803 int i;
c6dc6f63 1804
7fc9b714
AF		 1805 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1806 def = &builtin_x86_defs[i];
c04321b3 1807 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1808 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1809 }
21ad7789
JK		 1810#ifdef CONFIG_KVM
1811 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1812 "KVM processor with all supported host features "
1813 "(only available in KVM mode)");
1814#endif
1815
6cdf8854 1816 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1817 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1818 FeatureWordInfo *fw = &feature_word_info[i];
1819
1820 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1821 (*cpu_fprintf)(f, " %s\n", buf);
1822 }
c6dc6f63
AP		 1823}
1824
76b64a7a 1825CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1826{
1827 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1828 X86CPUDefinition *def;
7fc9b714 1829 int i;
e3966126 1830
7fc9b714 1831 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1832 CpuDefinitionInfoList *entry;
1833 CpuDefinitionInfo *info;
1834
7fc9b714 1835 def = &builtin_x86_defs[i];
e3966126
AL		 1836 info = g_malloc0(sizeof(*info));
1837 info->name = g_strdup(def->name);
1838
1839 entry = g_malloc0(sizeof(*entry));
1840 entry->value = info;
1841 entry->next = cpu_list;
1842 cpu_list = entry;
1843 }
1844
1845 return cpu_list;
1846}
1847
bc74b7db
EH		 1848static void filter_features_for_kvm(X86CPU *cpu)
1849{
1850 CPUX86State *env = &cpu->env;
1851 KVMState *s = kvm_state;
bd87d2a2 1852 FeatureWord w;
bc74b7db 1853
bd87d2a2
EH		 1854 for (w = 0; w < FEATURE_WORDS; w++) {
1855 FeatureWordInfo *wi = &feature_word_info[w];
034acf4a
EH		 1856 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1857 wi->cpuid_ecx,
1858 wi->cpuid_reg);
1859 uint32_t requested_features = env->features[w];
1860 env->features[w] &= host_feat;
1861 cpu->filtered_features[w] = requested_features & ~env->features[w];
bd87d2a2 1862 }
bc74b7db 1863}
bc74b7db 1864
d940ee9b 1865/* Load data from X86CPUDefinition
c080e30e 1866 */
d940ee9b 1867static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 1868{
61dcd775 1869 CPUX86State *env = &cpu->env;
74f54bc4
EH		 1870 const char *vendor;
1871 char host_vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63 1872
2d64255b
AF		 1873 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1874 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1875 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1876 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
0514ef2f
EH		 1877 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1878 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1879 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1880 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
2d64255b 1881 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
0514ef2f
EH		 1882 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1883 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1884 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1885 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
b3baa152 1886 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1887 cpu->cache_info_passthrough = def->cache_info_passthrough;
3b671a40 1888
2d64255b 1889 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
82beb536 1890
9576de75 1891 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 1892 if (kvm_enabled()) {
5fcca9ff
EH		 1893 FeatureWord w;
1894 for (w = 0; w < FEATURE_WORDS; w++) {
1895 env->features[w] |= kvm_default_features[w];
1896 }
82beb536 1897 }
5fcca9ff 1898
82beb536 1899 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 1900
1901 /* sysenter isn't supported in compatibility mode on AMD,
1902 * syscall isn't supported in compatibility mode on Intel.
1903 * Normally we advertise the actual CPU vendor, but you can
1904 * override this using the 'vendor' property if you want to use
1905 * KVM's sysenter/syscall emulation in compatibility mode and
1906 * when doing cross vendor migration
1907 */
74f54bc4 1908 vendor = def->vendor;
7c08db30
EH		 1909 if (kvm_enabled()) {
1910 uint32_t ebx = 0, ecx = 0, edx = 0;
1911 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1912 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1913 vendor = host_vendor;
1914 }
1915
1916 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1917
c6dc6f63
AP		 1918}
1919
62fc403f
IM		 1920X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1921 Error **errp)
5c3c6a68 1922{
2d64255b 1923 X86CPU *cpu = NULL;
d940ee9b 1924 X86CPUClass *xcc;
500050d1 1925 ObjectClass *oc;
2d64255b
AF		 1926 gchar **model_pieces;
1927 char *name, *features;
5c3c6a68
AF		 1928 Error *error = NULL;
1929
2d64255b
AF		 1930 model_pieces = g_strsplit(cpu_model, ",", 2);
1931 if (!model_pieces[0]) {
1932 error_setg(&error, "Invalid/empty CPU model name");
1933 goto out;
1934 }
1935 name = model_pieces[0];
1936 features = model_pieces[1];
1937
500050d1
AF		 1938 oc = x86_cpu_class_by_name(name);
1939 if (oc == NULL) {
1940 error_setg(&error, "Unable to find CPU definition: %s", name);
1941 goto out;
1942 }
d940ee9b
EH		 1943 xcc = X86_CPU_CLASS(oc);
1944
1945 if (xcc->kvm_required && !kvm_enabled()) {
1946 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 1947 goto out;
1948 }
1949
d940ee9b
EH		 1950 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1951
62fc403f
IM		 1952#ifndef CONFIG_USER_ONLY
1953 if (icc_bridge == NULL) {
1954 error_setg(&error, "Invalid icc-bridge value");
1955 goto out;
1956 }
1957 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1958 object_unref(OBJECT(cpu));
1959#endif
5c3c6a68 1960
94a444b2 1961 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 1962 if (error) {
1963 goto out;
5c3c6a68
AF		 1964 }
1965
7f833247 1966out:
cd7b87ff
AF		 1967 if (error != NULL) {
1968 error_propagate(errp, error);
500050d1
AF		 1969 if (cpu) {
1970 object_unref(OBJECT(cpu));
1971 cpu = NULL;
1972 }
cd7b87ff 1973 }
7f833247
IM		 1974 g_strfreev(model_pieces);
1975 return cpu;
1976}
1977
1978X86CPU *cpu_x86_init(const char *cpu_model)
1979{
1980 Error *error = NULL;
1981 X86CPU *cpu;
1982
62fc403f 1983 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1984 if (error) {
2d64255b
AF		 1985 goto out;
1986 }
1987
7f833247
IM		 1988 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1989
2d64255b 1990out:
2d64255b 1991 if (error) {
4a44d85e 1992 error_report("%s", error_get_pretty(error));
5c3c6a68 1993 error_free(error);
2d64255b
AF		 1994 if (cpu != NULL) {
1995 object_unref(OBJECT(cpu));
1996 cpu = NULL;
1997 }
5c3c6a68
AF		 1998 }
1999 return cpu;
2000}
2001
d940ee9b
EH		 2002static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2003{
2004 X86CPUDefinition *cpudef = data;
2005 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2006
2007 xcc->cpu_def = cpudef;
2008}
2009
2010static void x86_register_cpudef_type(X86CPUDefinition *def)
2011{
2012 char *typename = x86_cpu_type_name(def->name);
2013 TypeInfo ti = {
2014 .name = typename,
2015 .parent = TYPE_X86_CPU,
2016 .class_init = x86_cpu_cpudef_class_init,
2017 .class_data = def,
2018 };
2019
2020 type_register(&ti);
2021 g_free(typename);
2022}
2023
c6dc6f63 2024#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2025
0e26b7b8
BS		 2026void cpu_clear_apic_feature(CPUX86State *env)
2027{
0514ef2f 2028 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2029}
2030
c6dc6f63
AP		 2031#endif /* !CONFIG_USER_ONLY */
2032
c04321b3 2033/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2034 */
2035void x86_cpudef_setup(void)
2036{
93bfef4c
CV		 2037 int i, j;
2038 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2039
2040 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2041 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2042
2043 /* Look for specific "cpudef" models that */
09faecf2 2044 /* have the QEMU version in .model_id */
93bfef4c 2045 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2046 if (strcmp(model_with_versions[j], def->name) == 0) {
2047 pstrcpy(def->model_id, sizeof(def->model_id),
2048 "QEMU Virtual CPU version ");
2049 pstrcat(def->model_id, sizeof(def->model_id),
2050 qemu_get_version());
93bfef4c
CV		 2051 break;
2052 }
2053 }
c6dc6f63 2054 }
c6dc6f63
AP		 2055}
2056
c6dc6f63
AP		 2057static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2058 uint32_t *ecx, uint32_t *edx)
2059{
2060 *ebx = env->cpuid_vendor1;
2061 *edx = env->cpuid_vendor2;
2062 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2063}
2064
2065void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2066 uint32_t *eax, uint32_t *ebx,
2067 uint32_t *ecx, uint32_t *edx)
2068{
a60f24b5
AF		 2069 X86CPU *cpu = x86_env_get_cpu(env);
2070 CPUState *cs = CPU(cpu);
2071
c6dc6f63
AP		 2072 /* test if maximum index reached */
2073 if (index & 0x80000000) {
b3baa152
BW		 2074 if (index > env->cpuid_xlevel) {
2075 if (env->cpuid_xlevel2 > 0) {
2076 /* Handle the Centaur's CPUID instruction. */
2077 if (index > env->cpuid_xlevel2) {
2078 index = env->cpuid_xlevel2;
2079 } else if (index < 0xC0000000) {
2080 index = env->cpuid_xlevel;
2081 }
2082 } else {
57f26ae7
EH		 2083 /* Intel documentation states that invalid EAX input will
2084 * return the same information as EAX=cpuid_level
2085 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2086 */
2087 index = env->cpuid_level;
b3baa152
BW		 2088 }
2089 }
c6dc6f63
AP		 2090 } else {
2091 if (index > env->cpuid_level)
2092 index = env->cpuid_level;
2093 }
2094
2095 switch(index) {
2096 case 0:
2097 *eax = env->cpuid_level;
2098 get_cpuid_vendor(env, ebx, ecx, edx);
2099 break;
2100 case 1:
2101 *eax = env->cpuid_version;
2102 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2103 *ecx = env->features[FEAT_1_ECX];
2104 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2105 if (cs->nr_cores * cs->nr_threads > 1) {
2106 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2107 *edx |= 1 << 28; /* HTT bit */
2108 }
2109 break;
2110 case 2:
2111 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2112 if (cpu->cache_info_passthrough) {
2113 host_cpuid(index, 0, eax, ebx, ecx, edx);
2114 break;
2115 }
5e891bf8 2116 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2117 *ebx = 0;
2118 *ecx = 0;
5e891bf8
EH		 2119 *edx = (L1D_DESCRIPTOR << 16) | \
2120 (L1I_DESCRIPTOR << 8) | \
2121 (L2_DESCRIPTOR);
c6dc6f63
AP		 2122 break;
2123 case 4:
2124 /* cache info: needed for Core compatibility */
787aaf57
BC		 2125 if (cpu->cache_info_passthrough) {
2126 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2127 *eax &= ~0xFC000000;
c6dc6f63 2128 } else {
2f7a21c4 2129 *eax = 0;
76c2975a 2130 switch (count) {
c6dc6f63 2131 case 0: /* L1 dcache info */
5e891bf8
EH		 2132 *eax |= CPUID_4_TYPE_DCACHE | \
2133 CPUID_4_LEVEL(1) | \
2134 CPUID_4_SELF_INIT_LEVEL;
2135 *ebx = (L1D_LINE_SIZE - 1) | \
2136 ((L1D_PARTITIONS - 1) << 12) | \
2137 ((L1D_ASSOCIATIVITY - 1) << 22);
2138 *ecx = L1D_SETS - 1;
2139 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2140 break;
2141 case 1: /* L1 icache info */
5e891bf8
EH		 2142 *eax |= CPUID_4_TYPE_ICACHE | \
2143 CPUID_4_LEVEL(1) | \
2144 CPUID_4_SELF_INIT_LEVEL;
2145 *ebx = (L1I_LINE_SIZE - 1) | \
2146 ((L1I_PARTITIONS - 1) << 12) | \
2147 ((L1I_ASSOCIATIVITY - 1) << 22);
2148 *ecx = L1I_SETS - 1;
2149 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2150 break;
2151 case 2: /* L2 cache info */
5e891bf8
EH		 2152 *eax |= CPUID_4_TYPE_UNIFIED | \
2153 CPUID_4_LEVEL(2) | \
2154 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2155 if (cs->nr_threads > 1) {
2156 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2157 }
5e891bf8
EH		 2158 *ebx = (L2_LINE_SIZE - 1) | \
2159 ((L2_PARTITIONS - 1) << 12) | \
2160 ((L2_ASSOCIATIVITY - 1) << 22);
2161 *ecx = L2_SETS - 1;
2162 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2163 break;
2164 default: /* end of info */
2165 *eax = 0;
2166 *ebx = 0;
2167 *ecx = 0;
2168 *edx = 0;
2169 break;
76c2975a
PB		 2170 }
2171 }
2172
2173 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2174 if ((*eax & 31) && cs->nr_cores > 1) {
2175 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2176 }
2177 break;
2178 case 5:
2179 /* mwait info: needed for Core compatibility */
2180 *eax = 0; /* Smallest monitor-line size in bytes */
2181 *ebx = 0; /* Largest monitor-line size in bytes */
2182 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2183 *edx = 0;
2184 break;
2185 case 6:
2186 /* Thermal and Power Leaf */
2187 *eax = 0;
2188 *ebx = 0;
2189 *ecx = 0;
2190 *edx = 0;
2191 break;
f7911686 2192 case 7:
13526728
EH		 2193 /* Structured Extended Feature Flags Enumeration Leaf */
2194 if (count == 0) {
2195 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2196 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2197 *ecx = 0; /* Reserved */
2198 *edx = 0; /* Reserved */
f7911686
YW		 2199 } else {
2200 *eax = 0;
2201 *ebx = 0;
2202 *ecx = 0;
2203 *edx = 0;
2204 }
2205 break;
c6dc6f63
AP		 2206 case 9:
2207 /* Direct Cache Access Information Leaf */
2208 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2209 *ebx = 0;
2210 *ecx = 0;
2211 *edx = 0;
2212 break;
2213 case 0xA:
2214 /* Architectural Performance Monitoring Leaf */
9337e3b6 2215 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2216 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2217
2218 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2219 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2220 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2221 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2222 } else {
2223 *eax = 0;
2224 *ebx = 0;
2225 *ecx = 0;
2226 *edx = 0;
2227 }
c6dc6f63 2228 break;
2560f19f
PB		 2229 case 0xD: {
2230 KVMState *s = cs->kvm_state;
2231 uint64_t kvm_mask;
2232 int i;
2233
51e49430 2234 /* Processor Extended State */
2560f19f
PB		 2235 *eax = 0;
2236 *ebx = 0;
2237 *ecx = 0;
2238 *edx = 0;
2239 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2240 break;
2241 }
2560f19f
PB		 2242 kvm_mask =
2243 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2244 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2245
2560f19f
PB		 2246 if (count == 0) {
2247 *ecx = 0x240;
2248 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2249 const ExtSaveArea *esa = &ext_save_areas[i];
2250 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2251 (kvm_mask & (1 << i)) != 0) {
2252 if (i < 32) {
2253 *eax |= 1 << i;
2254 } else {
2255 *edx |= 1 << (i - 32);
2256 }
2257 *ecx = MAX(*ecx, esa->offset + esa->size);
2258 }
2259 }
2260 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2261 *ebx = *ecx;
2262 } else if (count == 1) {
2263 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2264 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2265 const ExtSaveArea *esa = &ext_save_areas[count];
2266 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2267 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2268 *eax = esa->size;
2269 *ebx = esa->offset;
2560f19f 2270 }
51e49430
SY		 2271 }
2272 break;
2560f19f 2273 }
c6dc6f63
AP		 2274 case 0x80000000:
2275 *eax = env->cpuid_xlevel;
2276 *ebx = env->cpuid_vendor1;
2277 *edx = env->cpuid_vendor2;
2278 *ecx = env->cpuid_vendor3;
2279 break;
2280 case 0x80000001:
2281 *eax = env->cpuid_version;
2282 *ebx = 0;
0514ef2f
EH		 2283 *ecx = env->features[FEAT_8000_0001_ECX];
2284 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2285
2286 /* The Linux kernel checks for the CMPLegacy bit and
2287 * discards multiple thread information if it is set.
2288 * So dont set it here for Intel to make Linux guests happy.
2289 */
ce3960eb 2290 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2291 uint32_t tebx, tecx, tedx;
2292 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2293 if (tebx != CPUID_VENDOR_INTEL_1 ||
2294 tedx != CPUID_VENDOR_INTEL_2 ||
2295 tecx != CPUID_VENDOR_INTEL_3) {
2296 *ecx |= 1 << 1; /* CmpLegacy bit */
2297 }
2298 }
c6dc6f63
AP		 2299 break;
2300 case 0x80000002:
2301 case 0x80000003:
2302 case 0x80000004:
2303 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2304 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2305 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2306 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2307 break;
2308 case 0x80000005:
2309 /* cache info (L1 cache) */
787aaf57
BC		 2310 if (cpu->cache_info_passthrough) {
2311 host_cpuid(index, 0, eax, ebx, ecx, edx);
2312 break;
2313 }
5e891bf8
EH		 2314 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2315 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2316 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2317 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2318 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2319 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2320 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2321 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2322 break;
2323 case 0x80000006:
2324 /* cache info (L2 cache) */
787aaf57
BC		 2325 if (cpu->cache_info_passthrough) {
2326 host_cpuid(index, 0, eax, ebx, ecx, edx);
2327 break;
2328 }
5e891bf8
EH		 2329 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2330 (L2_DTLB_2M_ENTRIES << 16) | \
2331 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2332 (L2_ITLB_2M_ENTRIES);
2333 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2334 (L2_DTLB_4K_ENTRIES << 16) | \
2335 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2336 (L2_ITLB_4K_ENTRIES);
2337 *ecx = (L2_SIZE_KB_AMD << 16) | \
2338 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2339 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2340 *edx = ((L3_SIZE_KB/512) << 18) | \
2341 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2342 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP		 2343 break;
2344 case 0x80000008:
2345 /* virtual & phys address size in low 2 bytes. */
2346/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2347 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2348 /* 64 bit processor */
2349/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2350 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2351 } else {
0514ef2f 2352 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2353 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2354 } else {
c6dc6f63 2355 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2356 }
c6dc6f63
AP		 2357 }
2358 *ebx = 0;
2359 *ecx = 0;
2360 *edx = 0;
ce3960eb
AF		 2361 if (cs->nr_cores * cs->nr_threads > 1) {
2362 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2363 }
2364 break;
2365 case 0x8000000A:
0514ef2f 2366 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2367 *eax = 0x00000001; /* SVM Revision */
2368 *ebx = 0x00000010; /* nr of ASIDs */
2369 *ecx = 0;
0514ef2f 2370 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2371 } else {
2372 *eax = 0;
2373 *ebx = 0;
2374 *ecx = 0;
2375 *edx = 0;
2376 }
c6dc6f63 2377 break;
b3baa152
BW		 2378 case 0xC0000000:
2379 *eax = env->cpuid_xlevel2;
2380 *ebx = 0;
2381 *ecx = 0;
2382 *edx = 0;
2383 break;
2384 case 0xC0000001:
2385 /* Support for VIA CPU's CPUID instruction */
2386 *eax = env->cpuid_version;
2387 *ebx = 0;
2388 *ecx = 0;
0514ef2f 2389 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2390 break;
2391 case 0xC0000002:
2392 case 0xC0000003:
2393 case 0xC0000004:
2394 /* Reserved for the future, and now filled with zero */
2395 *eax = 0;
2396 *ebx = 0;
2397 *ecx = 0;
2398 *edx = 0;
2399 break;
c6dc6f63
AP		 2400 default:
2401 /* reserved values: zero */
2402 *eax = 0;
2403 *ebx = 0;
2404 *ecx = 0;
2405 *edx = 0;
2406 break;
2407 }
2408}
5fd2087a
AF		 2409
2410/* CPUClass::reset() */
2411static void x86_cpu_reset(CPUState *s)
2412{
2413 X86CPU *cpu = X86_CPU(s);
2414 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2415 CPUX86State *env = &cpu->env;
c1958aea
AF		 2416 int i;
2417
5fd2087a
AF		 2418 xcc->parent_reset(s);
2419
c1958aea 2420
f0c3c505 2421 memset(env, 0, offsetof(CPUX86State, pat));
c1958aea 2422
00c8cb0a 2423 tlb_flush(s, 1);
c1958aea
AF		 2424
2425 env->old_exception = -1;
2426
2427 /* init to reset state */
2428
2429#ifdef CONFIG_SOFTMMU
2430 env->hflags |= HF_SOFTMMU_MASK;
2431#endif
2432 env->hflags2 |= HF2_GIF_MASK;
2433
2434 cpu_x86_update_cr0(env, 0x60000010);
2435 env->a20_mask = ~0x0;
2436 env->smbase = 0x30000;
2437
2438 env->idt.limit = 0xffff;
2439 env->gdt.limit = 0xffff;
2440 env->ldt.limit = 0xffff;
2441 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2442 env->tr.limit = 0xffff;
2443 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2444
2445 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2446 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2447 DESC_R_MASK | DESC_A_MASK);
2448 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2449 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2450 DESC_A_MASK);
2451 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2452 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2453 DESC_A_MASK);
2454 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2455 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2456 DESC_A_MASK);
2457 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2458 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2459 DESC_A_MASK);
2460 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2461 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2462 DESC_A_MASK);
2463
2464 env->eip = 0xfff0;
2465 env->regs[R_EDX] = env->cpuid_version;
2466
2467 env->eflags = 0x2;
2468
2469 /* FPU init */
2470 for (i = 0; i < 8; i++) {
2471 env->fptags[i] = 1;
2472 }
2473 env->fpuc = 0x37f;
2474
2475 env->mxcsr = 0x1f80;
c74f41bb 2476 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2477
2478 env->pat = 0x0007040600070406ULL;
2479 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2480
2481 memset(env->dr, 0, sizeof(env->dr));
2482 env->dr[6] = DR6_FIXED_1;
2483 env->dr[7] = DR7_FIXED_1;
b3310ab3 2484 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2485 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2486
0522604b
FLVC		 2487 env->tsc_adjust = 0;
2488 env->tsc = 0;
2489
dd673288
IM		 2490#if !defined(CONFIG_USER_ONLY)
2491 /* We hard-wire the BSP to the first CPU. */
55e5c285 2492 if (s->cpu_index == 0) {
02e51483 2493 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2494 }
2495
259186a7 2496 s->halted = !cpu_is_bsp(cpu);
dd673288 2497#endif
5fd2087a
AF		 2498}
2499
dd673288
IM		 2500#ifndef CONFIG_USER_ONLY
2501bool cpu_is_bsp(X86CPU *cpu)
2502{
02e51483 2503 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2504}
65dee380
IM		 2505
2506/* TODO: remove me, when reset over QOM tree is implemented */
2507static void x86_cpu_machine_reset_cb(void *opaque)
2508{
2509 X86CPU *cpu = opaque;
2510 cpu_reset(CPU(cpu));
2511}
dd673288
IM		 2512#endif
2513
de024815
AF		 2514static void mce_init(X86CPU *cpu)
2515{
2516 CPUX86State *cenv = &cpu->env;
2517 unsigned int bank;
2518
2519 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2520 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2521 (CPUID_MCE | CPUID_MCA)) {
2522 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2523 cenv->mcg_ctl = ~(uint64_t)0;
2524 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2525 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2526 }
2527 }
2528}
2529
bdeec802 2530#ifndef CONFIG_USER_ONLY
d3c64d6a 2531static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2532{
bdeec802 2533 CPUX86State *env = &cpu->env;
53a89e26 2534 DeviceState *dev = DEVICE(cpu);
449994eb 2535 APICCommonState *apic;
bdeec802
IM		 2536 const char *apic_type = "apic";
2537
2538 if (kvm_irqchip_in_kernel()) {
2539 apic_type = "kvm-apic";
2540 } else if (xen_enabled()) {
2541 apic_type = "xen-apic";
2542 }
2543
02e51483
CF		 2544 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2545 if (cpu->apic_state == NULL) {
bdeec802
IM		 2546 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2547 return;
2548 }
2549
2550 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2551 OBJECT(cpu->apic_state), NULL);
2552 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2553 /* TODO: convert to link<> */
02e51483 2554 apic = APIC_COMMON(cpu->apic_state);
60671e58 2555 apic->cpu = cpu;
d3c64d6a
IM		 2556}
2557
2558static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2559{
02e51483 2560 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2561 return;
2562 }
bdeec802 2563
02e51483 2564 if (qdev_init(cpu->apic_state)) {
bdeec802 2565 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2566 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2567 return;
2568 }
bdeec802 2569}
d3c64d6a
IM		 2570#else
2571static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2572{
2573}
bdeec802
IM		 2574#endif
2575
2b6f294c 2576static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2577{
14a10fc3 2578 CPUState *cs = CPU(dev);
2b6f294c
AF		 2579 X86CPU *cpu = X86_CPU(dev);
2580 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2581 CPUX86State *env = &cpu->env;
2b6f294c 2582 Error *local_err = NULL;
b34d12d1 2583
0514ef2f 2584 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2585 env->cpuid_level = 7;
2586 }
7a059953 2587
9b15cd9e
IM		 2588 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2589 * CPUID[1].EDX.
2590 */
2591 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2592 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2593 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2594 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2595 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2596 & CPUID_EXT2_AMD_ALIASES);
2597 }
2598
4586f157 2599 if (!kvm_enabled()) {
0514ef2f
EH		 2600 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2601 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2602 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
4586f157
IM		 2603#ifdef TARGET_X86_64
2604 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2605#endif
2606 );
0514ef2f
EH		 2607 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2608 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
4586f157 2609 } else {
f0b9b111 2610 KVMState *s = kvm_state;
912ffc47 2611 if ((cpu->check_cpuid || cpu->enforce_cpuid)
f0b9b111 2612 && kvm_check_features_against_host(s, cpu) && cpu->enforce_cpuid) {
4dc1f449
IM		 2613 error_setg(&local_err,
2614 "Host's CPU doesn't support requested features");
2615 goto out;
5ec01c2e 2616 }
a509d632 2617 filter_features_for_kvm(cpu);
4586f157
IM		 2618 }
2619
65dee380
IM		 2620#ifndef CONFIG_USER_ONLY
2621 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2622
0514ef2f 2623 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2624 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2625 if (local_err != NULL) {
4dc1f449 2626 goto out;
bdeec802
IM		 2627 }
2628 }
65dee380
IM		 2629#endif
2630
7a059953 2631 mce_init(cpu);
14a10fc3 2632 qemu_init_vcpu(cs);
d3c64d6a
IM		 2633
2634 x86_cpu_apic_realize(cpu, &local_err);
2635 if (local_err != NULL) {
2636 goto out;
2637 }
14a10fc3 2638 cpu_reset(cs);
2b6f294c 2639
4dc1f449
IM		 2640 xcc->parent_realize(dev, &local_err);
2641out:
2642 if (local_err != NULL) {
2643 error_propagate(errp, local_err);
2644 return;
2645 }
7a059953
AF		 2646}
2647
8932cfdf
EH		 2648/* Enables contiguous-apic-ID mode, for compatibility */
2649static bool compat_apic_id_mode;
2650
2651void enable_compat_apic_id_mode(void)
2652{
2653 compat_apic_id_mode = true;
2654}
2655
cb41bad3
EH		 2656/* Calculates initial APIC ID for a specific CPU index
2657 *
2658 * Currently we need to be able to calculate the APIC ID from the CPU index
2659 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2660 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2661 * all CPUs up to max_cpus.
2662 */
2663uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2664{
8932cfdf
EH		 2665 uint32_t correct_id;
2666 static bool warned;
2667
2668 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2669 if (compat_apic_id_mode) {
2670 if (cpu_index != correct_id && !warned) {
2671 error_report("APIC IDs set in compatibility mode, "
2672 "CPU topology won't match the configuration");
2673 warned = true;
2674 }
2675 return cpu_index;
2676 } else {
2677 return correct_id;
2678 }
cb41bad3
EH		 2679}
2680
de024815
AF		 2681static void x86_cpu_initfn(Object *obj)
2682{
55e5c285 2683 CPUState *cs = CPU(obj);
de024815 2684 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2685 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2686 CPUX86State *env = &cpu->env;
d65e9815 2687 static int inited;
de024815 2688
c05efcb1 2689 cs->env_ptr = env;
de024815 2690 cpu_exec_init(env);
71ad61d3
AF		 2691
2692 object_property_add(obj, "family", "int",
95b8519d 2693 x86_cpuid_version_get_family,
71ad61d3 2694 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2695 object_property_add(obj, "model", "int",
67e30c83 2696 x86_cpuid_version_get_model,
c5291a4f 2697 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2698 object_property_add(obj, "stepping", "int",
35112e41 2699 x86_cpuid_version_get_stepping,
036e2222 2700 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2701 object_property_add(obj, "level", "int",
2702 x86_cpuid_get_level,
2703 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2704 object_property_add(obj, "xlevel", "int",
2705 x86_cpuid_get_xlevel,
2706 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2707 object_property_add_str(obj, "vendor",
2708 x86_cpuid_get_vendor,
2709 x86_cpuid_set_vendor, NULL);
938d4c25 2710 object_property_add_str(obj, "model-id",
63e886eb 2711 x86_cpuid_get_model_id,
938d4c25 2712 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2713 object_property_add(obj, "tsc-frequency", "int",
2714 x86_cpuid_get_tsc_freq,
2715 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2716 object_property_add(obj, "apic-id", "int",
2717 x86_cpuid_get_apic_id,
2718 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2719 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2720 x86_cpu_get_feature_words,
7e5292b5
EH		 2721 NULL, NULL, (void *)env->features, NULL);
2722 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2723 x86_cpu_get_feature_words,
2724 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2725
92067bf4 2726 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2727 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815 2728
d940ee9b
EH		 2729 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2730
d65e9815
IM		 2731 /* init various static tables used in TCG mode */
2732 if (tcg_enabled() && !inited) {
2733 inited = 1;
2734 optimize_flags_init();
2735#ifndef CONFIG_USER_ONLY
2736 cpu_set_debug_excp_handler(breakpoint_handler);
2737#endif
2738 }
de024815
AF		 2739}
2740
997395d3
IM		 2741static int64_t x86_cpu_get_arch_id(CPUState *cs)
2742{
2743 X86CPU *cpu = X86_CPU(cs);
2744 CPUX86State *env = &cpu->env;
2745
2746 return env->cpuid_apic_id;
2747}
2748
444d5590
AF		 2749static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2750{
2751 X86CPU *cpu = X86_CPU(cs);
2752
2753 return cpu->env.cr[0] & CR0_PG_MASK;
2754}
2755
f45748f1
AF		 2756static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2757{
2758 X86CPU *cpu = X86_CPU(cs);
2759
2760 cpu->env.eip = value;
2761}
2762
bdf7ae5b
AF		 2763static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2764{
2765 X86CPU *cpu = X86_CPU(cs);
2766
2767 cpu->env.eip = tb->pc - tb->cs_base;
2768}
2769
8c2e1b00
AF		 2770static bool x86_cpu_has_work(CPUState *cs)
2771{
2772 X86CPU *cpu = X86_CPU(cs);
2773 CPUX86State *env = &cpu->env;
2774
2775 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2776 CPU_INTERRUPT_POLL)) &&
2777 (env->eflags & IF_MASK)) ||
2778 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2779 CPU_INTERRUPT_INIT |
2780 CPU_INTERRUPT_SIPI |
2781 CPU_INTERRUPT_MCE));
2782}
2783
9337e3b6
EH		 2784static Property x86_cpu_properties[] = {
2785 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2786 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2787 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2788 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2789 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2790 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2791 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
9337e3b6
EH		 2792 DEFINE_PROP_END_OF_LIST()
2793};
2794
5fd2087a
AF		 2795static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2796{
2797 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2798 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2799 DeviceClass *dc = DEVICE_CLASS(oc);
2800
2801 xcc->parent_realize = dc->realize;
2802 dc->realize = x86_cpu_realizefn;
62fc403f 2803 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2804 dc->props = x86_cpu_properties;
5fd2087a
AF		 2805
2806 xcc->parent_reset = cc->reset;
2807 cc->reset = x86_cpu_reset;
91b1df8c 2808 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2809
500050d1 2810 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 2811 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 2812 cc->has_work = x86_cpu_has_work;
97a8ea5a 2813 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2814 cc->dump_state = x86_cpu_dump_state;
f45748f1 2815 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2816 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2817 cc->gdb_read_register = x86_cpu_gdb_read_register;
2818 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2819 cc->get_arch_id = x86_cpu_get_arch_id;
2820 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 2821#ifdef CONFIG_USER_ONLY
2822 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2823#else
a23bbfda 2824 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2825 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2826 cc->write_elf64_note = x86_cpu_write_elf64_note;
2827 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2828 cc->write_elf32_note = x86_cpu_write_elf32_note;
2829 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2830 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2831#endif
a0e372f0 2832 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2833}
2834
2835static const TypeInfo x86_cpu_type_info = {
2836 .name = TYPE_X86_CPU,
2837 .parent = TYPE_CPU,
2838 .instance_size = sizeof(X86CPU),
de024815 2839 .instance_init = x86_cpu_initfn,
d940ee9b 2840 .abstract = true,
5fd2087a
AF		 2841 .class_size = sizeof(X86CPUClass),
2842 .class_init = x86_cpu_common_class_init,
2843};
2844
2845static void x86_cpu_register_types(void)
2846{
d940ee9b
EH		 2847 int i;
2848
5fd2087a 2849 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 2850 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2851 x86_register_cpudef_type(&builtin_x86_defs[i]);
2852 }
2853#ifdef CONFIG_KVM
2854 type_register_static(&host_x86_cpu_type_info);
2855#endif
5fd2087a
AF		 2856}
2857
2858type_init(x86_cpu_register_types)
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