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Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-2014-06-24' into staging
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
8932cfdf 28#include "topology.h"
c6dc6f63 29
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 260 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 262 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 263 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
264};
265
5ef57876
EH		 266typedef struct FeatureWordInfo {
267 const char **feat_names;
04d104b6
EH		 268 uint32_t cpuid_eax; /* Input EAX for CPUID */
269 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
270 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
271 int cpuid_reg; /* output register (R_* constant) */
5ef57876
EH		 272} FeatureWordInfo;
273
274static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 275 [FEAT_1_EDX] = {
276 .feat_names = feature_name,
277 .cpuid_eax = 1, .cpuid_reg = R_EDX,
278 },
279 [FEAT_1_ECX] = {
280 .feat_names = ext_feature_name,
281 .cpuid_eax = 1, .cpuid_reg = R_ECX,
282 },
283 [FEAT_8000_0001_EDX] = {
284 .feat_names = ext2_feature_name,
285 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
286 },
287 [FEAT_8000_0001_ECX] = {
288 .feat_names = ext3_feature_name,
289 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
290 },
89e49c8b
EH		 291 [FEAT_C000_0001_EDX] = {
292 .feat_names = ext4_feature_name,
293 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
294 },
bffd67b0
EH		 295 [FEAT_KVM] = {
296 .feat_names = kvm_feature_name,
297 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
298 },
299 [FEAT_SVM] = {
300 .feat_names = svm_feature_name,
301 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
302 },
303 [FEAT_7_0_EBX] = {
304 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 305 .cpuid_eax = 7,
306 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
307 .cpuid_reg = R_EBX,
bffd67b0 308 },
5ef57876
EH		 309};
310
8e8aba50
EH		 311typedef struct X86RegisterInfo32 {
312 /* Name of register */
313 const char *name;
314 /* QAPI enum value register */
315 X86CPURegister32 qapi_enum;
316} X86RegisterInfo32;
317
318#define REGISTER(reg) \
5d371f41 319 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 320static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 321 REGISTER(EAX),
322 REGISTER(ECX),
323 REGISTER(EDX),
324 REGISTER(EBX),
325 REGISTER(ESP),
326 REGISTER(EBP),
327 REGISTER(ESI),
328 REGISTER(EDI),
329};
330#undef REGISTER
331
2560f19f
PB		 332typedef struct ExtSaveArea {
333 uint32_t feature, bits;
334 uint32_t offset, size;
335} ExtSaveArea;
336
337static const ExtSaveArea ext_save_areas[] = {
338 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 339 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 340 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
341 .offset = 0x3c0, .size = 0x40 },
342 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 343 .offset = 0x400, .size = 0x40 },
2560f19f 344};
8e8aba50 345
8b4beddc
EH		 346const char *get_register_name_32(unsigned int reg)
347{
31ccdde2 348 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 349 return NULL;
350 }
8e8aba50 351 return x86_reg_info_32[reg].name;
8b4beddc
EH		 352}
353
c6dc6f63
AP		 354/* collects per-function cpuid data
355 */
356typedef struct model_features_t {
357 uint32_t *guest_feat;
358 uint32_t *host_feat;
bffd67b0 359 FeatureWord feat_word;
8b4beddc 360} model_features_t;
c6dc6f63 361
5fcca9ff
EH		 362/* KVM-specific features that are automatically added to all CPU models
363 * when KVM is enabled.
364 */
365static uint32_t kvm_default_features[FEATURE_WORDS] = {
366 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 367 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 368 (1 << KVM_FEATURE_CLOCKSOURCE2) |
369 (1 << KVM_FEATURE_ASYNC_PF) |
370 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 371 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 372 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 373 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 374};
dc59944b 375
8fb4f821 376void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
dc59944b 377{
8fb4f821 378 kvm_default_features[w] &= ~features;
dc59944b
MT		 379}
380
bb44e0d1
JK		 381void host_cpuid(uint32_t function, uint32_t count,
382 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 383{
a1fd24af
AL		 384 uint32_t vec[4];
385
386#ifdef __x86_64__
387 asm volatile("cpuid"
388 : "=a"(vec[0]), "=b"(vec[1]),
389 "=c"(vec[2]), "=d"(vec[3])
390 : "0"(function), "c"(count) : "cc");
c1f41226 391#elif defined(__i386__)
a1fd24af
AL		 392 asm volatile("pusha \n\t"
393 "cpuid \n\t"
394 "mov %%eax, 0(%2) \n\t"
395 "mov %%ebx, 4(%2) \n\t"
396 "mov %%ecx, 8(%2) \n\t"
397 "mov %%edx, 12(%2) \n\t"
398 "popa"
399 : : "a"(function), "c"(count), "S"(vec)
400 : "memory", "cc");
c1f41226
EH		 401#else
402 abort();
a1fd24af
AL		 403#endif
404
bdde476a 405 if (eax)
a1fd24af 406 *eax = vec[0];
bdde476a 407 if (ebx)
a1fd24af 408 *ebx = vec[1];
bdde476a 409 if (ecx)
a1fd24af 410 *ecx = vec[2];
bdde476a 411 if (edx)
a1fd24af 412 *edx = vec[3];
bdde476a 413}
c6dc6f63
AP		 414
415#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
416
417/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
418 * a substring. ex if !NULL points to the first char after a substring,
419 * otherwise the string is assumed to sized by a terminating nul.
420 * Return lexical ordering of *s1:*s2.
421 */
422static int sstrcmp(const char *s1, const char *e1, const char *s2,
423 const char *e2)
424{
425 for (;;) {
426 if (!*s1 || !*s2 || *s1 != *s2)
427 return (*s1 - *s2);
428 ++s1, ++s2;
429 if (s1 == e1 && s2 == e2)
430 return (0);
431 else if (s1 == e1)
432 return (*s2);
433 else if (s2 == e2)
434 return (*s1);
435 }
436}
437
438/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
439 * '|' delimited (possibly empty) strings in which case search for a match
440 * within the alternatives proceeds left to right. Return 0 for success,
441 * non-zero otherwise.
442 */
443static int altcmp(const char *s, const char *e, const char *altstr)
444{
445 const char *p, *q;
446
447 for (q = p = altstr; ; ) {
448 while (*p && *p != '|')
449 ++p;
450 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
451 return (0);
452 if (!*p)
453 return (1);
454 else
455 q = ++p;
456 }
457}
458
459/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 460 * *pval and return true, otherwise return false
c6dc6f63 461 */
e41e0fc6
JK		 462static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
463 const char **featureset)
c6dc6f63
AP		 464{
465 uint32_t mask;
466 const char **ppc;
e41e0fc6 467 bool found = false;
c6dc6f63 468
e41e0fc6 469 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 470 if (*ppc && !altcmp(s, e, *ppc)) {
471 *pval |= mask;
e41e0fc6 472 found = true;
c6dc6f63 473 }
e41e0fc6
JK		 474 }
475 return found;
c6dc6f63
AP		 476}
477
5ef57876
EH		 478static void add_flagname_to_bitmaps(const char *flagname,
479 FeatureWordArray words)
c6dc6f63 480{
5ef57876
EH		 481 FeatureWord w;
482 for (w = 0; w < FEATURE_WORDS; w++) {
483 FeatureWordInfo *wi = &feature_word_info[w];
484 if (wi->feat_names &&
485 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
486 break;
487 }
488 }
489 if (w == FEATURE_WORDS) {
490 fprintf(stderr, "CPU feature %s not found\n", flagname);
491 }
c6dc6f63
AP		 492}
493
d940ee9b
EH		 494/* CPU class name definitions: */
495
496#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
497#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
498
499/* Return type name for a given CPU model name
500 * Caller is responsible for freeing the returned string.
501 */
502static char *x86_cpu_type_name(const char *model_name)
503{
504 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
505}
506
500050d1
AF		 507static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
508{
d940ee9b
EH		 509 ObjectClass *oc;
510 char *typename;
511
500050d1
AF		 512 if (cpu_model == NULL) {
513 return NULL;
514 }
515
d940ee9b
EH		 516 typename = x86_cpu_type_name(cpu_model);
517 oc = object_class_by_name(typename);
518 g_free(typename);
519 return oc;
500050d1
AF		 520}
521
d940ee9b 522struct X86CPUDefinition {
c6dc6f63
AP		 523 const char *name;
524 uint32_t level;
90e4b0c3
EH		 525 uint32_t xlevel;
526 uint32_t xlevel2;
99b88a17
IM		 527 /* vendor is zero-terminated, 12 character ASCII string */
528 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 529 int family;
530 int model;
531 int stepping;
0514ef2f 532 FeatureWordArray features;
c6dc6f63 533 char model_id[48];
787aaf57 534 bool cache_info_passthrough;
d940ee9b 535};
c6dc6f63
AP		 536
537#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
538#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
539 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
540#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
541 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
542 CPUID_PSE36 | CPUID_FXSR)
543#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
544#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
545 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
546 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
547 CPUID_PAE | CPUID_SEP | CPUID_APIC)
548
551a2dec
AP		 549#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
550 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
551 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
552 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
553 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed 554 /* partly implemented:
de431a65 555 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
8560efed
AJ		 556 /* missing:
557 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
e71827bc
AJ		 558#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
559 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
560 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
d640045a 561 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
8560efed 562 /* missing:
e71827bc
AJ		 563 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
564 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
565 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
d640045a
AJ		 566 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
567 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
83f7dc28 568 CPUID_EXT_RDRAND */
60032ac0 569#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec 570 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
77549a78 571 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB)
551a2dec
AP		 572#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
573 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 574#define TCG_SVM_FEATURES 0
7073fbad 575#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
cd7f97ca 576 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
111994ee 577 /* missing:
7073fbad
RH		 578 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
579 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
cd7f97ca 580 CPUID_7_0_EBX_RDSEED */
551a2dec 581
9576de75 582static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 583 {
584 .name = "qemu64",
585 .level = 4,
99b88a17 586 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 587 .family = 6,
f8e6a11a 588 .model = 6,
c6dc6f63 589 .stepping = 3,
0514ef2f 590 .features[FEAT_1_EDX] =
27861ecc 591 PPRO_FEATURES |
c6dc6f63 592 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 593 CPUID_PSE36,
0514ef2f 594 .features[FEAT_1_ECX] =
27861ecc 595 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 596 .features[FEAT_8000_0001_EDX] =
27861ecc 597 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 598 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 599 .features[FEAT_8000_0001_ECX] =
27861ecc 600 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 601 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
602 .xlevel = 0x8000000A,
c6dc6f63
AP		 603 },
604 {
605 .name = "phenom",
606 .level = 5,
99b88a17 607 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 608 .family = 16,
609 .model = 2,
610 .stepping = 3,
0514ef2f 611 .features[FEAT_1_EDX] =
27861ecc 612 PPRO_FEATURES |
c6dc6f63 613 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 614 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 615 .features[FEAT_1_ECX] =
27861ecc 616 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 617 CPUID_EXT_POPCNT,
0514ef2f 618 .features[FEAT_8000_0001_EDX] =
27861ecc 619 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 620 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
621 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 622 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 623 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
624 CPUID_EXT3_CR8LEG,
625 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
626 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 627 .features[FEAT_8000_0001_ECX] =
27861ecc 628 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 629 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 630 .features[FEAT_SVM] =
27861ecc 631 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 632 .xlevel = 0x8000001A,
633 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
634 },
635 {
636 .name = "core2duo",
637 .level = 10,
99b88a17 638 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 639 .family = 6,
640 .model = 15,
641 .stepping = 11,
0514ef2f 642 .features[FEAT_1_EDX] =
27861ecc 643 PPRO_FEATURES |
c6dc6f63 644 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 645 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
646 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 647 .features[FEAT_1_ECX] =
27861ecc 648 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 649 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
650 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 651 .features[FEAT_8000_0001_EDX] =
27861ecc 652 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 653 .features[FEAT_8000_0001_ECX] =
27861ecc 654 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 655 .xlevel = 0x80000008,
656 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
657 },
658 {
659 .name = "kvm64",
660 .level = 5,
99b88a17 661 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 662 .family = 15,
663 .model = 6,
664 .stepping = 1,
665 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 666 .features[FEAT_1_EDX] =
27861ecc 667 PPRO_FEATURES |
c6dc6f63
AP		 668 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
669 CPUID_PSE36,
670 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 671 .features[FEAT_1_ECX] =
27861ecc 672 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 673 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 674 .features[FEAT_8000_0001_EDX] =
27861ecc 675 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 676 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
677 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
678 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
679 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
680 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 681 .features[FEAT_8000_0001_ECX] =
27861ecc 682 0,
c6dc6f63
AP		 683 .xlevel = 0x80000008,
684 .model_id = "Common KVM processor"
685 },
c6dc6f63
AP		 686 {
687 .name = "qemu32",
688 .level = 4,
99b88a17 689 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 690 .family = 6,
f8e6a11a 691 .model = 6,
c6dc6f63 692 .stepping = 3,
0514ef2f 693 .features[FEAT_1_EDX] =
27861ecc 694 PPRO_FEATURES,
0514ef2f 695 .features[FEAT_1_ECX] =
27861ecc 696 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 697 .xlevel = 0x80000004,
c6dc6f63 698 },
eafaf1e5
AP		 699 {
700 .name = "kvm32",
701 .level = 5,
99b88a17 702 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 703 .family = 15,
704 .model = 6,
705 .stepping = 1,
0514ef2f 706 .features[FEAT_1_EDX] =
27861ecc 707 PPRO_FEATURES |
eafaf1e5 708 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 709 .features[FEAT_1_ECX] =
27861ecc 710 CPUID_EXT_SSE3,
0514ef2f 711 .features[FEAT_8000_0001_EDX] =
27861ecc 712 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 713 .features[FEAT_8000_0001_ECX] =
27861ecc 714 0,
eafaf1e5
AP		 715 .xlevel = 0x80000008,
716 .model_id = "Common 32-bit KVM processor"
717 },
c6dc6f63
AP		 718 {
719 .name = "coreduo",
720 .level = 10,
99b88a17 721 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 722 .family = 6,
723 .model = 14,
724 .stepping = 8,
0514ef2f 725 .features[FEAT_1_EDX] =
27861ecc 726 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 727 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
728 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 729 .features[FEAT_1_ECX] =
27861ecc 730 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 731 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 732 .features[FEAT_8000_0001_EDX] =
27861ecc 733 CPUID_EXT2_NX,
c6dc6f63
AP		 734 .xlevel = 0x80000008,
735 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
736 },
737 {
738 .name = "486",
58012d66 739 .level = 1,
99b88a17 740 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 741 .family = 4,
b2a856d9 742 .model = 8,
c6dc6f63 743 .stepping = 0,
0514ef2f 744 .features[FEAT_1_EDX] =
27861ecc 745 I486_FEATURES,
c6dc6f63
AP		 746 .xlevel = 0,
747 },
748 {
749 .name = "pentium",
750 .level = 1,
99b88a17 751 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 752 .family = 5,
753 .model = 4,
754 .stepping = 3,
0514ef2f 755 .features[FEAT_1_EDX] =
27861ecc 756 PENTIUM_FEATURES,
c6dc6f63
AP		 757 .xlevel = 0,
758 },
759 {
760 .name = "pentium2",
761 .level = 2,
99b88a17 762 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 763 .family = 6,
764 .model = 5,
765 .stepping = 2,
0514ef2f 766 .features[FEAT_1_EDX] =
27861ecc 767 PENTIUM2_FEATURES,
c6dc6f63
AP		 768 .xlevel = 0,
769 },
770 {
771 .name = "pentium3",
772 .level = 2,
99b88a17 773 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 774 .family = 6,
775 .model = 7,
776 .stepping = 3,
0514ef2f 777 .features[FEAT_1_EDX] =
27861ecc 778 PENTIUM3_FEATURES,
c6dc6f63
AP		 779 .xlevel = 0,
780 },
781 {
782 .name = "athlon",
783 .level = 2,
99b88a17 784 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 785 .family = 6,
786 .model = 2,
787 .stepping = 3,
0514ef2f 788 .features[FEAT_1_EDX] =
27861ecc 789 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 790 CPUID_MCA,
0514ef2f 791 .features[FEAT_8000_0001_EDX] =
27861ecc 792 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 793 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 794 .xlevel = 0x80000008,
c6dc6f63
AP		 795 },
796 {
797 .name = "n270",
798 /* original is on level 10 */
799 .level = 5,
99b88a17 800 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 801 .family = 6,
802 .model = 28,
803 .stepping = 2,
0514ef2f 804 .features[FEAT_1_EDX] =
27861ecc 805 PPRO_FEATURES |
8560efed
AJ		 806 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
807 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 808 /* Some CPUs got no CPUID_SEP */
0514ef2f 809 .features[FEAT_1_ECX] =
27861ecc 810 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 811 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
812 CPUID_EXT_MOVBE,
0514ef2f 813 .features[FEAT_8000_0001_EDX] =
27861ecc 814 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 815 CPUID_EXT2_NX,
0514ef2f 816 .features[FEAT_8000_0001_ECX] =
27861ecc 817 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 818 .xlevel = 0x8000000A,
819 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
820 },
3eca4642
EH		 821 {
822 .name = "Conroe",
6b11322e 823 .level = 4,
99b88a17 824 .vendor = CPUID_VENDOR_INTEL,
3eca4642 825 .family = 6,
ffce9ebb 826 .model = 15,
3eca4642 827 .stepping = 3,
0514ef2f 828 .features[FEAT_1_EDX] =
27861ecc 829 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 830 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
831 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
832 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
833 CPUID_DE | CPUID_FP87,
0514ef2f 834 .features[FEAT_1_ECX] =
27861ecc 835 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 836 .features[FEAT_8000_0001_EDX] =
27861ecc 837 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 838 .features[FEAT_8000_0001_ECX] =
27861ecc 839 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 840 .xlevel = 0x8000000A,
841 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
842 },
843 {
844 .name = "Penryn",
6b11322e 845 .level = 4,
99b88a17 846 .vendor = CPUID_VENDOR_INTEL,
3eca4642 847 .family = 6,
ffce9ebb 848 .model = 23,
3eca4642 849 .stepping = 3,
0514ef2f 850 .features[FEAT_1_EDX] =
27861ecc 851 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 852 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
853 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
854 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
855 CPUID_DE | CPUID_FP87,
0514ef2f 856 .features[FEAT_1_ECX] =
27861ecc 857 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 858 CPUID_EXT_SSE3,
0514ef2f 859 .features[FEAT_8000_0001_EDX] =
27861ecc 860 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 861 .features[FEAT_8000_0001_ECX] =
27861ecc 862 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 863 .xlevel = 0x8000000A,
864 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
865 },
866 {
867 .name = "Nehalem",
6b11322e 868 .level = 4,
99b88a17 869 .vendor = CPUID_VENDOR_INTEL,
3eca4642 870 .family = 6,
ffce9ebb 871 .model = 26,
3eca4642 872 .stepping = 3,
0514ef2f 873 .features[FEAT_1_EDX] =
27861ecc 874 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 875 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
876 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
877 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
878 CPUID_DE | CPUID_FP87,
0514ef2f 879 .features[FEAT_1_ECX] =
27861ecc 880 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 881 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 882 .features[FEAT_8000_0001_EDX] =
27861ecc 883 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 884 .features[FEAT_8000_0001_ECX] =
27861ecc 885 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 886 .xlevel = 0x8000000A,
887 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
888 },
889 {
890 .name = "Westmere",
891 .level = 11,
99b88a17 892 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 893 .family = 6,
894 .model = 44,
895 .stepping = 1,
0514ef2f 896 .features[FEAT_1_EDX] =
27861ecc 897 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 898 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
899 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
900 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
901 CPUID_DE | CPUID_FP87,
0514ef2f 902 .features[FEAT_1_ECX] =
27861ecc 903 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 904 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 905 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 906 .features[FEAT_8000_0001_EDX] =
27861ecc 907 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 908 .features[FEAT_8000_0001_ECX] =
27861ecc 909 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 910 .xlevel = 0x8000000A,
911 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
912 },
913 {
914 .name = "SandyBridge",
915 .level = 0xd,
99b88a17 916 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 917 .family = 6,
918 .model = 42,
919 .stepping = 1,
0514ef2f 920 .features[FEAT_1_EDX] =
27861ecc 921 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 922 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
923 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
924 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
925 CPUID_DE | CPUID_FP87,
0514ef2f 926 .features[FEAT_1_ECX] =
27861ecc 927 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 928 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
929 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
930 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
931 CPUID_EXT_SSE3,
0514ef2f 932 .features[FEAT_8000_0001_EDX] =
27861ecc 933 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 934 CPUID_EXT2_SYSCALL,
0514ef2f 935 .features[FEAT_8000_0001_ECX] =
27861ecc 936 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 937 .xlevel = 0x8000000A,
938 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
939 },
37507094
EH		 940 {
941 .name = "Haswell",
942 .level = 0xd,
99b88a17 943 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 944 .family = 6,
945 .model = 60,
946 .stepping = 1,
0514ef2f 947 .features[FEAT_1_EDX] =
27861ecc 948 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 949 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 950 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 951 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
952 CPUID_DE | CPUID_FP87,
0514ef2f 953 .features[FEAT_1_ECX] =
27861ecc 954 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH		 955 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
956 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
957 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
958 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
959 CPUID_EXT_PCID,
0514ef2f 960 .features[FEAT_8000_0001_EDX] =
27861ecc 961 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 962 CPUID_EXT2_SYSCALL,
0514ef2f 963 .features[FEAT_8000_0001_ECX] =
27861ecc 964 CPUID_EXT3_LAHF_LM,
0514ef2f 965 .features[FEAT_7_0_EBX] =
27861ecc 966 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 967 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
968 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
969 CPUID_7_0_EBX_RTM,
970 .xlevel = 0x8000000A,
971 .model_id = "Intel Core Processor (Haswell)",
972 },
3eca4642
EH		 973 {
974 .name = "Opteron_G1",
975 .level = 5,
99b88a17 976 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 977 .family = 15,
978 .model = 6,
979 .stepping = 1,
0514ef2f 980 .features[FEAT_1_EDX] =
27861ecc 981 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 982 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
983 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
984 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
985 CPUID_DE | CPUID_FP87,
0514ef2f 986 .features[FEAT_1_ECX] =
27861ecc 987 CPUID_EXT_SSE3,
0514ef2f 988 .features[FEAT_8000_0001_EDX] =
27861ecc 989 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH		 990 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
991 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
992 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
993 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
994 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
995 .xlevel = 0x80000008,
996 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
997 },
998 {
999 .name = "Opteron_G2",
1000 .level = 5,
99b88a17 1001 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1002 .family = 15,
1003 .model = 6,
1004 .stepping = 1,
0514ef2f 1005 .features[FEAT_1_EDX] =
27861ecc 1006 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1007 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1008 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1009 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1010 CPUID_DE | CPUID_FP87,
0514ef2f 1011 .features[FEAT_1_ECX] =
27861ecc 1012 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1013 .features[FEAT_8000_0001_EDX] =
27861ecc 1014 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1015 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1016 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1017 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1018 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1019 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1020 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1021 .features[FEAT_8000_0001_ECX] =
27861ecc 1022 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1023 .xlevel = 0x80000008,
1024 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1025 },
1026 {
1027 .name = "Opteron_G3",
1028 .level = 5,
99b88a17 1029 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1030 .family = 15,
1031 .model = 6,
1032 .stepping = 1,
0514ef2f 1033 .features[FEAT_1_EDX] =
27861ecc 1034 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1035 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1036 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1037 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1038 CPUID_DE | CPUID_FP87,
0514ef2f 1039 .features[FEAT_1_ECX] =
27861ecc 1040 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1041 CPUID_EXT_SSE3,
0514ef2f 1042 .features[FEAT_8000_0001_EDX] =
27861ecc 1043 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1044 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1045 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1046 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1047 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1048 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1049 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1050 .features[FEAT_8000_0001_ECX] =
27861ecc 1051 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH		 1052 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1053 .xlevel = 0x80000008,
1054 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1055 },
1056 {
1057 .name = "Opteron_G4",
1058 .level = 0xd,
99b88a17 1059 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1060 .family = 21,
1061 .model = 1,
1062 .stepping = 2,
0514ef2f 1063 .features[FEAT_1_EDX] =
27861ecc 1064 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1065 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1066 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1067 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1068 CPUID_DE | CPUID_FP87,
0514ef2f 1069 .features[FEAT_1_ECX] =
27861ecc 1070 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 1071 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1072 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1073 CPUID_EXT_SSE3,
0514ef2f 1074 .features[FEAT_8000_0001_EDX] =
27861ecc 1075 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH		 1076 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1077 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1078 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1079 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1080 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1081 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1082 .features[FEAT_8000_0001_ECX] =
27861ecc 1083 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH		 1084 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1085 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1086 CPUID_EXT3_LAHF_LM,
1087 .xlevel = 0x8000001A,
1088 .model_id = "AMD Opteron 62xx class CPU",
1089 },
021941b9
AP		 1090 {
1091 .name = "Opteron_G5",
1092 .level = 0xd,
99b88a17 1093 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1094 .family = 21,
1095 .model = 2,
1096 .stepping = 0,
0514ef2f 1097 .features[FEAT_1_EDX] =
27861ecc 1098 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP		 1099 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1100 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1101 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1102 CPUID_DE | CPUID_FP87,
0514ef2f 1103 .features[FEAT_1_ECX] =
27861ecc 1104 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP		 1105 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1106 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1107 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1108 .features[FEAT_8000_0001_EDX] =
27861ecc 1109 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP		 1110 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1111 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1112 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1113 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1114 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1115 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1116 .features[FEAT_8000_0001_ECX] =
27861ecc 1117 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP		 1118 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1119 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1120 CPUID_EXT3_LAHF_LM,
1121 .xlevel = 0x8000001A,
1122 .model_id = "AMD Opteron 63xx class CPU",
1123 },
c6dc6f63
AP		 1124};
1125
0668af54
EH		 1126/**
1127 * x86_cpu_compat_set_features:
1128 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1129 * @w: Identifies the feature word to be changed.
1130 * @feat_add: Feature bits to be added to feature word
1131 * @feat_remove: Feature bits to be removed from feature word
1132 *
1133 * Change CPU model feature bits for compatibility.
1134 *
1135 * This function may be used by machine-type compatibility functions
1136 * to enable or disable feature bits on specific CPU models.
1137 */
1138void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1139 uint32_t feat_add, uint32_t feat_remove)
1140{
9576de75 1141 X86CPUDefinition *def;
0668af54
EH		 1142 int i;
1143 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1144 def = &builtin_x86_defs[i];
1145 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1146 def->features[w] |= feat_add;
1147 def->features[w] &= ~feat_remove;
1148 }
1149 }
1150}
1151
d940ee9b
EH		 1152#ifdef CONFIG_KVM
1153
c6dc6f63
AP		 1154static int cpu_x86_fill_model_id(char *str)
1155{
1156 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1157 int i;
1158
1159 for (i = 0; i < 3; i++) {
1160 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1161 memcpy(str + i * 16 + 0, &eax, 4);
1162 memcpy(str + i * 16 + 4, &ebx, 4);
1163 memcpy(str + i * 16 + 8, &ecx, 4);
1164 memcpy(str + i * 16 + 12, &edx, 4);
1165 }
1166 return 0;
1167}
1168
d940ee9b
EH		 1169static X86CPUDefinition host_cpudef;
1170
1171/* class_init for the "host" CPU model
6e746f30 1172 *
d940ee9b 1173 * This function may be called before KVM is initialized.
6e746f30 1174 */
d940ee9b 1175static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1176{
d940ee9b 1177 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1178 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1179
d940ee9b 1180 xcc->kvm_required = true;
6e746f30 1181
c6dc6f63 1182 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1183 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1184
1185 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1186 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1187 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1188 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1189
d940ee9b 1190 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1191
d940ee9b
EH		 1192 xcc->cpu_def = &host_cpudef;
1193 host_cpudef.cache_info_passthrough = true;
1194
1195 /* level, xlevel, xlevel2, and the feature words are initialized on
1196 * instance_init, because they require KVM to be initialized.
1197 */
1198}
1199
1200static void host_x86_cpu_initfn(Object *obj)
1201{
1202 X86CPU *cpu = X86_CPU(obj);
1203 CPUX86State *env = &cpu->env;
1204 KVMState *s = kvm_state;
1205 FeatureWord w;
1206
1207 assert(kvm_enabled());
1208
1209 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1210 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1211 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1212
2bc65d2b
EH		 1213 for (w = 0; w < FEATURE_WORDS; w++) {
1214 FeatureWordInfo *wi = &feature_word_info[w];
d940ee9b 1215 env->features[w] =
2bc65d2b
EH		 1216 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1217 wi->cpuid_reg);
1218 }
d940ee9b 1219 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1220}
1221
d940ee9b
EH		 1222static const TypeInfo host_x86_cpu_type_info = {
1223 .name = X86_CPU_TYPE_NAME("host"),
1224 .parent = TYPE_X86_CPU,
1225 .instance_init = host_x86_cpu_initfn,
1226 .class_init = host_x86_cpu_class_init,
1227};
1228
1229#endif
1230
bffd67b0 1231static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 1232{
1233 int i;
1234
1235 for (i = 0; i < 32; ++i)
1236 if (1 << i & mask) {
bffd67b0 1237 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1238 assert(reg);
1239 fprintf(stderr, "warning: host doesn't support requested feature: "
1240 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1241 f->cpuid_eax, reg,
1242 f->feat_names[i] ? "." : "",
1243 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 1244 break;
1245 }
1246 return 0;
1247}
1248
07ca5945
EH		 1249/* Check if all requested cpu flags are making their way to the guest
1250 *
1251 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 1252 *
1253 * This function may be called only if KVM is enabled.
c6dc6f63 1254 */
f0b9b111 1255static int kvm_check_features_against_host(KVMState *s, X86CPU *cpu)
c6dc6f63 1256{
5ec01c2e 1257 CPUX86State *env = &cpu->env;
f0b9b111
EH		 1258 int rv = 0;
1259 FeatureWord w;
c6dc6f63 1260
6e746f30
EH		 1261 assert(kvm_enabled());
1262
f0b9b111 1263 for (w = 0; w < FEATURE_WORDS; w++) {
bffd67b0 1264 FeatureWordInfo *wi = &feature_word_info[w];
f0b9b111
EH		 1265 uint32_t guest_feat = env->features[w];
1266 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1267 wi->cpuid_ecx,
1268 wi->cpuid_reg);
1269 uint32_t mask;
bffd67b0 1270 for (mask = 1; mask; mask <<= 1) {
f0b9b111 1271 if (guest_feat & mask && !(host_feat & mask)) {
bffd67b0
EH		 1272 unavailable_host_feature(wi, mask);
1273 rv = 1;
1274 }
1275 }
1276 }
c6dc6f63
AP		 1277 return rv;
1278}
1279
95b8519d
AF		 1280static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1281 const char *name, Error **errp)
1282{
1283 X86CPU *cpu = X86_CPU(obj);
1284 CPUX86State *env = &cpu->env;
1285 int64_t value;
1286
1287 value = (env->cpuid_version >> 8) & 0xf;
1288 if (value == 0xf) {
1289 value += (env->cpuid_version >> 20) & 0xff;
1290 }
1291 visit_type_int(v, &value, name, errp);
1292}
1293
71ad61d3
AF		 1294static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1295 const char *name, Error **errp)
ed5e1ec3 1296{
71ad61d3
AF		 1297 X86CPU *cpu = X86_CPU(obj);
1298 CPUX86State *env = &cpu->env;
1299 const int64_t min = 0;
1300 const int64_t max = 0xff + 0xf;
65cd9064 1301 Error *local_err = NULL;
71ad61d3
AF		 1302 int64_t value;
1303
65cd9064
MA		 1304 visit_type_int(v, &value, name, &local_err);
1305 if (local_err) {
1306 error_propagate(errp, local_err);
71ad61d3
AF		 1307 return;
1308 }
1309 if (value < min || value > max) {
1310 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1311 name ? name : "null", value, min, max);
1312 return;
1313 }
1314
ed5e1ec3 1315 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1316 if (value > 0x0f) {
1317 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1318 } else {
71ad61d3 1319 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1320 }
1321}
1322
67e30c83
AF		 1323static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1324 const char *name, Error **errp)
1325{
1326 X86CPU *cpu = X86_CPU(obj);
1327 CPUX86State *env = &cpu->env;
1328 int64_t value;
1329
1330 value = (env->cpuid_version >> 4) & 0xf;
1331 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1332 visit_type_int(v, &value, name, errp);
1333}
1334
c5291a4f
AF		 1335static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1336 const char *name, Error **errp)
b0704cbd 1337{
c5291a4f
AF		 1338 X86CPU *cpu = X86_CPU(obj);
1339 CPUX86State *env = &cpu->env;
1340 const int64_t min = 0;
1341 const int64_t max = 0xff;
65cd9064 1342 Error *local_err = NULL;
c5291a4f
AF		 1343 int64_t value;
1344
65cd9064
MA		 1345 visit_type_int(v, &value, name, &local_err);
1346 if (local_err) {
1347 error_propagate(errp, local_err);
c5291a4f
AF		 1348 return;
1349 }
1350 if (value < min || value > max) {
1351 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1352 name ? name : "null", value, min, max);
1353 return;
1354 }
1355
b0704cbd 1356 env->cpuid_version &= ~0xf00f0;
c5291a4f 1357 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1358}
1359
35112e41
AF		 1360static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1361 void *opaque, const char *name,
1362 Error **errp)
1363{
1364 X86CPU *cpu = X86_CPU(obj);
1365 CPUX86State *env = &cpu->env;
1366 int64_t value;
1367
1368 value = env->cpuid_version & 0xf;
1369 visit_type_int(v, &value, name, errp);
1370}
1371
036e2222
AF		 1372static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1373 void *opaque, const char *name,
1374 Error **errp)
38c3dc46 1375{
036e2222
AF		 1376 X86CPU *cpu = X86_CPU(obj);
1377 CPUX86State *env = &cpu->env;
1378 const int64_t min = 0;
1379 const int64_t max = 0xf;
65cd9064 1380 Error *local_err = NULL;
036e2222
AF		 1381 int64_t value;
1382
65cd9064
MA		 1383 visit_type_int(v, &value, name, &local_err);
1384 if (local_err) {
1385 error_propagate(errp, local_err);
036e2222
AF		 1386 return;
1387 }
1388 if (value < min || value > max) {
1389 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1390 name ? name : "null", value, min, max);
1391 return;
1392 }
1393
38c3dc46 1394 env->cpuid_version &= ~0xf;
036e2222 1395 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1396}
1397
8e1898bf
AF		 1398static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1399 const char *name, Error **errp)
1400{
1401 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1402
fa029887 1403 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1404}
1405
1406static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1407 const char *name, Error **errp)
1408{
1409 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1410
fa029887 1411 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1412}
1413
16b93aa8
AF		 1414static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1415 const char *name, Error **errp)
1416{
1417 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1418
fa029887 1419 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1420}
1421
1422static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1423 const char *name, Error **errp)
1424{
1425 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1426
fa029887 1427 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1428}
1429
d480e1af
AF		 1430static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1431{
1432 X86CPU *cpu = X86_CPU(obj);
1433 CPUX86State *env = &cpu->env;
1434 char *value;
d480e1af 1435
9df694ee 1436 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1437 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1438 env->cpuid_vendor3);
d480e1af
AF		 1439 return value;
1440}
1441
1442static void x86_cpuid_set_vendor(Object *obj, const char *value,
1443 Error **errp)
1444{
1445 X86CPU *cpu = X86_CPU(obj);
1446 CPUX86State *env = &cpu->env;
1447 int i;
1448
9df694ee 1449 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1450 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1451 "vendor", value);
1452 return;
1453 }
1454
1455 env->cpuid_vendor1 = 0;
1456 env->cpuid_vendor2 = 0;
1457 env->cpuid_vendor3 = 0;
1458 for (i = 0; i < 4; i++) {
1459 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1460 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1461 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1462 }
d480e1af
AF		 1463}
1464
63e886eb
AF		 1465static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1466{
1467 X86CPU *cpu = X86_CPU(obj);
1468 CPUX86State *env = &cpu->env;
1469 char *value;
1470 int i;
1471
1472 value = g_malloc(48 + 1);
1473 for (i = 0; i < 48; i++) {
1474 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1475 }
1476 value[48] = '\0';
1477 return value;
1478}
1479
938d4c25
AF		 1480static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1481 Error **errp)
dcce6675 1482{
938d4c25
AF		 1483 X86CPU *cpu = X86_CPU(obj);
1484 CPUX86State *env = &cpu->env;
dcce6675
AF		 1485 int c, len, i;
1486
1487 if (model_id == NULL) {
1488 model_id = "";
1489 }
1490 len = strlen(model_id);
d0a6acf4 1491 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1492 for (i = 0; i < 48; i++) {
1493 if (i >= len) {
1494 c = '\0';
1495 } else {
1496 c = (uint8_t)model_id[i];
1497 }
1498 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1499 }
1500}
1501
89e48965
AF		 1502static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1503 const char *name, Error **errp)
1504{
1505 X86CPU *cpu = X86_CPU(obj);
1506 int64_t value;
1507
1508 value = cpu->env.tsc_khz * 1000;
1509 visit_type_int(v, &value, name, errp);
1510}
1511
1512static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1513 const char *name, Error **errp)
1514{
1515 X86CPU *cpu = X86_CPU(obj);
1516 const int64_t min = 0;
2e84849a 1517 const int64_t max = INT64_MAX;
65cd9064 1518 Error *local_err = NULL;
89e48965
AF		 1519 int64_t value;
1520
65cd9064
MA		 1521 visit_type_int(v, &value, name, &local_err);
1522 if (local_err) {
1523 error_propagate(errp, local_err);
89e48965
AF		 1524 return;
1525 }
1526 if (value < min || value > max) {
1527 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1528 name ? name : "null", value, min, max);
1529 return;
1530 }
1531
1532 cpu->env.tsc_khz = value / 1000;
1533}
1534
31050930
IM		 1535static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1536 const char *name, Error **errp)
1537{
1538 X86CPU *cpu = X86_CPU(obj);
1539 int64_t value = cpu->env.cpuid_apic_id;
1540
1541 visit_type_int(v, &value, name, errp);
1542}
1543
1544static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1545 const char *name, Error **errp)
1546{
1547 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1548 DeviceState *dev = DEVICE(obj);
31050930
IM		 1549 const int64_t min = 0;
1550 const int64_t max = UINT32_MAX;
1551 Error *error = NULL;
1552 int64_t value;
1553
8d6d4980
IM		 1554 if (dev->realized) {
1555 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1556 "it was realized", name, object_get_typename(obj));
1557 return;
1558 }
1559
31050930
IM		 1560 visit_type_int(v, &value, name, &error);
1561 if (error) {
1562 error_propagate(errp, error);
1563 return;
1564 }
1565 if (value < min || value > max) {
1566 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1567 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1568 object_get_typename(obj), name, value, min, max);
1569 return;
1570 }
1571
1572 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1573 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1574 return;
1575 }
1576 cpu->env.cpuid_apic_id = value;
1577}
1578
7e5292b5 1579/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1580static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1581 const char *name, Error **errp)
1582{
7e5292b5 1583 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1584 FeatureWord w;
1585 Error *err = NULL;
1586 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1587 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1588 X86CPUFeatureWordInfoList *list = NULL;
1589
1590 for (w = 0; w < FEATURE_WORDS; w++) {
1591 FeatureWordInfo *wi = &feature_word_info[w];
1592 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1593 qwi->cpuid_input_eax = wi->cpuid_eax;
1594 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1595 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1596 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1597 qwi->features = array[w];
8e8aba50
EH		 1598
1599 /* List will be in reverse order, but order shouldn't matter */
1600 list_entries[w].next = list;
1601 list_entries[w].value = &word_infos[w];
1602 list = &list_entries[w];
1603 }
1604
1605 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1606 error_propagate(errp, err);
1607}
1608
c8f0f88e
IM		 1609static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1610 const char *name, Error **errp)
1611{
1612 X86CPU *cpu = X86_CPU(obj);
1613 int64_t value = cpu->hyperv_spinlock_attempts;
1614
1615 visit_type_int(v, &value, name, errp);
1616}
1617
1618static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1619 const char *name, Error **errp)
1620{
1621 const int64_t min = 0xFFF;
1622 const int64_t max = UINT_MAX;
1623 X86CPU *cpu = X86_CPU(obj);
1624 Error *err = NULL;
1625 int64_t value;
1626
1627 visit_type_int(v, &value, name, &err);
1628 if (err) {
1629 error_propagate(errp, err);
1630 return;
1631 }
1632
1633 if (value < min || value > max) {
1634 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1635 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1636 object_get_typename(obj), name ? name : "null",
1637 value, min, max);
1638 return;
1639 }
1640 cpu->hyperv_spinlock_attempts = value;
1641}
1642
1643static PropertyInfo qdev_prop_spinlocks = {
1644 .name = "int",
1645 .get = x86_get_hv_spinlocks,
1646 .set = x86_set_hv_spinlocks,
1647};
1648
72ac2e87
IM		 1649/* Convert all '_' in a feature string option name to '-', to make feature
1650 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1651 */
1652static inline void feat2prop(char *s)
1653{
1654 while ((s = strchr(s, '_'))) {
1655 *s = '-';
1656 }
1657}
1658
8f961357
EH		 1659/* Parse "+feature,-feature,feature=foo" CPU feature string
1660 */
94a444b2
AF		 1661static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1662 Error **errp)
8f961357 1663{
94a444b2 1664 X86CPU *cpu = X86_CPU(cs);
8f961357
EH		 1665 char *featurestr; /* Single 'key=value" string being parsed */
1666 /* Features to be added */
077c68c3 1667 FeatureWordArray plus_features = { 0 };
8f961357 1668 /* Features to be removed */
5ef57876 1669 FeatureWordArray minus_features = { 0 };
8f961357 1670 uint32_t numvalue;
a91987c2 1671 CPUX86State *env = &cpu->env;
94a444b2 1672 Error *local_err = NULL;
8f961357 1673
8f961357 1674 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1675
1676 while (featurestr) {
1677 char *val;
1678 if (featurestr[0] == '+') {
5ef57876 1679 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1680 } else if (featurestr[0] == '-') {
5ef57876 1681 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1682 } else if ((val = strchr(featurestr, '='))) {
1683 *val = 0; val++;
72ac2e87 1684 feat2prop(featurestr);
d024d209 1685 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1686 char *err;
a91987c2
IM		 1687 char num[32];
1688
c6dc6f63
AP		 1689 numvalue = strtoul(val, &err, 0);
1690 if (!*val || *err) {
6b1dd54b
PB		 1691 error_setg(errp, "bad numerical value %s", val);
1692 return;
c6dc6f63
AP		 1693 }
1694 if (numvalue < 0x80000000) {
94a444b2
AF		 1695 error_report("xlevel value shall always be >= 0x80000000"
1696 ", fixup will be removed in future versions");
2f7a21c4 1697 numvalue += 0x80000000;
c6dc6f63 1698 }
a91987c2 1699 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1700 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1701 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1702 int64_t tsc_freq;
1703 char *err;
a91987c2 1704 char num[32];
b862d1fe
JR		 1705
1706 tsc_freq = strtosz_suffix_unit(val, &err,
1707 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1708 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1709 error_setg(errp, "bad numerical value %s", val);
1710 return;
b862d1fe 1711 }
a91987c2 1712 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1713 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1714 &local_err);
72ac2e87 1715 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1716 char *err;
92067bf4 1717 const int min = 0xFFF;
c8f0f88e 1718 char num[32];
28f52cc0
VR		 1719 numvalue = strtoul(val, &err, 0);
1720 if (!*val || *err) {
6b1dd54b
PB		 1721 error_setg(errp, "bad numerical value %s", val);
1722 return;
28f52cc0 1723 }
92067bf4 1724 if (numvalue < min) {
94a444b2
AF		 1725 error_report("hv-spinlocks value shall always be >= 0x%x"
1726 ", fixup will be removed in future versions",
92067bf4
IM		 1727 min);
1728 numvalue = min;
1729 }
c8f0f88e 1730 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1731 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1732 } else {
94a444b2 1733 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1734 }
c6dc6f63 1735 } else {
258f5abe 1736 feat2prop(featurestr);
94a444b2 1737 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1738 }
94a444b2
AF		 1739 if (local_err) {
1740 error_propagate(errp, local_err);
6b1dd54b 1741 return;
c6dc6f63
AP		 1742 }
1743 featurestr = strtok(NULL, ",");
1744 }
0514ef2f
EH		 1745 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1746 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1747 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1748 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1749 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1750 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1751 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1752 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1753 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1754 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1755 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1756 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1757 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1758 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1759 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1760 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63
AP		 1761}
1762
1763/* generate a composite string into buf of all cpuid names in featureset
1764 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1765 * if flags, suppress names undefined in featureset.
1766 */
1767static void listflags(char *buf, int bufsize, uint32_t fbits,
1768 const char **featureset, uint32_t flags)
1769{
1770 const char **p = &featureset[31];
1771 char *q, *b, bit;
1772 int nc;
1773
1774 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1775 *buf = '\0';
1776 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1777 if (fbits & 1 << bit && (*p || !flags)) {
1778 if (*p)
1779 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1780 else
1781 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1782 if (bufsize <= nc) {
1783 if (b) {
1784 memcpy(b, "...", sizeof("..."));
1785 }
1786 return;
1787 }
1788 q += nc;
1789 bufsize -= nc;
1790 }
1791}
1792
e916cbf8
PM		 1793/* generate CPU information. */
1794void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1795{
9576de75 1796 X86CPUDefinition *def;
c6dc6f63 1797 char buf[256];
7fc9b714 1798 int i;
c6dc6f63 1799
7fc9b714
AF		 1800 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1801 def = &builtin_x86_defs[i];
c04321b3 1802 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1803 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1804 }
21ad7789
JK		 1805#ifdef CONFIG_KVM
1806 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1807 "KVM processor with all supported host features "
1808 "(only available in KVM mode)");
1809#endif
1810
6cdf8854 1811 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1812 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1813 FeatureWordInfo *fw = &feature_word_info[i];
1814
1815 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1816 (*cpu_fprintf)(f, " %s\n", buf);
1817 }
c6dc6f63
AP		 1818}
1819
76b64a7a 1820CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1821{
1822 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1823 X86CPUDefinition *def;
7fc9b714 1824 int i;
e3966126 1825
7fc9b714 1826 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1827 CpuDefinitionInfoList *entry;
1828 CpuDefinitionInfo *info;
1829
7fc9b714 1830 def = &builtin_x86_defs[i];
e3966126
AL		 1831 info = g_malloc0(sizeof(*info));
1832 info->name = g_strdup(def->name);
1833
1834 entry = g_malloc0(sizeof(*entry));
1835 entry->value = info;
1836 entry->next = cpu_list;
1837 cpu_list = entry;
1838 }
1839
1840 return cpu_list;
1841}
1842
bc74b7db
EH		 1843static void filter_features_for_kvm(X86CPU *cpu)
1844{
1845 CPUX86State *env = &cpu->env;
1846 KVMState *s = kvm_state;
bd87d2a2 1847 FeatureWord w;
bc74b7db 1848
bd87d2a2
EH		 1849 for (w = 0; w < FEATURE_WORDS; w++) {
1850 FeatureWordInfo *wi = &feature_word_info[w];
034acf4a
EH		 1851 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1852 wi->cpuid_ecx,
1853 wi->cpuid_reg);
1854 uint32_t requested_features = env->features[w];
1855 env->features[w] &= host_feat;
1856 cpu->filtered_features[w] = requested_features & ~env->features[w];
bd87d2a2 1857 }
bc74b7db 1858}
bc74b7db 1859
d940ee9b 1860/* Load data from X86CPUDefinition
c080e30e 1861 */
d940ee9b 1862static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 1863{
61dcd775 1864 CPUX86State *env = &cpu->env;
74f54bc4
EH		 1865 const char *vendor;
1866 char host_vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63 1867
2d64255b
AF		 1868 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1869 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1870 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1871 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
0514ef2f
EH		 1872 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1873 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1874 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1875 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
2d64255b 1876 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
0514ef2f
EH		 1877 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1878 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1879 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1880 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
b3baa152 1881 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1882 cpu->cache_info_passthrough = def->cache_info_passthrough;
3b671a40 1883
2d64255b 1884 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
82beb536 1885
9576de75 1886 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 1887 if (kvm_enabled()) {
5fcca9ff
EH		 1888 FeatureWord w;
1889 for (w = 0; w < FEATURE_WORDS; w++) {
1890 env->features[w] |= kvm_default_features[w];
1891 }
82beb536 1892 }
5fcca9ff 1893
82beb536 1894 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 1895
1896 /* sysenter isn't supported in compatibility mode on AMD,
1897 * syscall isn't supported in compatibility mode on Intel.
1898 * Normally we advertise the actual CPU vendor, but you can
1899 * override this using the 'vendor' property if you want to use
1900 * KVM's sysenter/syscall emulation in compatibility mode and
1901 * when doing cross vendor migration
1902 */
74f54bc4 1903 vendor = def->vendor;
7c08db30
EH		 1904 if (kvm_enabled()) {
1905 uint32_t ebx = 0, ecx = 0, edx = 0;
1906 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1907 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1908 vendor = host_vendor;
1909 }
1910
1911 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1912
c6dc6f63
AP		 1913}
1914
62fc403f
IM		 1915X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1916 Error **errp)
5c3c6a68 1917{
2d64255b 1918 X86CPU *cpu = NULL;
d940ee9b 1919 X86CPUClass *xcc;
500050d1 1920 ObjectClass *oc;
2d64255b
AF		 1921 gchar **model_pieces;
1922 char *name, *features;
5c3c6a68
AF		 1923 Error *error = NULL;
1924
2d64255b
AF		 1925 model_pieces = g_strsplit(cpu_model, ",", 2);
1926 if (!model_pieces[0]) {
1927 error_setg(&error, "Invalid/empty CPU model name");
1928 goto out;
1929 }
1930 name = model_pieces[0];
1931 features = model_pieces[1];
1932
500050d1
AF		 1933 oc = x86_cpu_class_by_name(name);
1934 if (oc == NULL) {
1935 error_setg(&error, "Unable to find CPU definition: %s", name);
1936 goto out;
1937 }
d940ee9b
EH		 1938 xcc = X86_CPU_CLASS(oc);
1939
1940 if (xcc->kvm_required && !kvm_enabled()) {
1941 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 1942 goto out;
1943 }
1944
d940ee9b
EH		 1945 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1946
62fc403f
IM		 1947#ifndef CONFIG_USER_ONLY
1948 if (icc_bridge == NULL) {
1949 error_setg(&error, "Invalid icc-bridge value");
1950 goto out;
1951 }
1952 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1953 object_unref(OBJECT(cpu));
1954#endif
5c3c6a68 1955
94a444b2 1956 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 1957 if (error) {
1958 goto out;
5c3c6a68
AF		 1959 }
1960
7f833247 1961out:
cd7b87ff
AF		 1962 if (error != NULL) {
1963 error_propagate(errp, error);
500050d1
AF		 1964 if (cpu) {
1965 object_unref(OBJECT(cpu));
1966 cpu = NULL;
1967 }
cd7b87ff 1968 }
7f833247
IM		 1969 g_strfreev(model_pieces);
1970 return cpu;
1971}
1972
1973X86CPU *cpu_x86_init(const char *cpu_model)
1974{
1975 Error *error = NULL;
1976 X86CPU *cpu;
1977
62fc403f 1978 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1979 if (error) {
2d64255b
AF		 1980 goto out;
1981 }
1982
7f833247
IM		 1983 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1984
2d64255b 1985out:
2d64255b 1986 if (error) {
4a44d85e 1987 error_report("%s", error_get_pretty(error));
5c3c6a68 1988 error_free(error);
2d64255b
AF		 1989 if (cpu != NULL) {
1990 object_unref(OBJECT(cpu));
1991 cpu = NULL;
1992 }
5c3c6a68
AF		 1993 }
1994 return cpu;
1995}
1996
d940ee9b
EH		 1997static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
1998{
1999 X86CPUDefinition *cpudef = data;
2000 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2001
2002 xcc->cpu_def = cpudef;
2003}
2004
2005static void x86_register_cpudef_type(X86CPUDefinition *def)
2006{
2007 char *typename = x86_cpu_type_name(def->name);
2008 TypeInfo ti = {
2009 .name = typename,
2010 .parent = TYPE_X86_CPU,
2011 .class_init = x86_cpu_cpudef_class_init,
2012 .class_data = def,
2013 };
2014
2015 type_register(&ti);
2016 g_free(typename);
2017}
2018
c6dc6f63 2019#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2020
0e26b7b8
BS		 2021void cpu_clear_apic_feature(CPUX86State *env)
2022{
0514ef2f 2023 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2024}
2025
c6dc6f63
AP		 2026#endif /* !CONFIG_USER_ONLY */
2027
c04321b3 2028/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2029 */
2030void x86_cpudef_setup(void)
2031{
93bfef4c
CV		 2032 int i, j;
2033 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2034
2035 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2036 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2037
2038 /* Look for specific "cpudef" models that */
09faecf2 2039 /* have the QEMU version in .model_id */
93bfef4c 2040 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2041 if (strcmp(model_with_versions[j], def->name) == 0) {
2042 pstrcpy(def->model_id, sizeof(def->model_id),
2043 "QEMU Virtual CPU version ");
2044 pstrcat(def->model_id, sizeof(def->model_id),
2045 qemu_get_version());
93bfef4c
CV		 2046 break;
2047 }
2048 }
c6dc6f63 2049 }
c6dc6f63
AP		 2050}
2051
c6dc6f63
AP		 2052static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2053 uint32_t *ecx, uint32_t *edx)
2054{
2055 *ebx = env->cpuid_vendor1;
2056 *edx = env->cpuid_vendor2;
2057 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2058}
2059
2060void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2061 uint32_t *eax, uint32_t *ebx,
2062 uint32_t *ecx, uint32_t *edx)
2063{
a60f24b5
AF		 2064 X86CPU *cpu = x86_env_get_cpu(env);
2065 CPUState *cs = CPU(cpu);
2066
c6dc6f63
AP		 2067 /* test if maximum index reached */
2068 if (index & 0x80000000) {
b3baa152
BW		 2069 if (index > env->cpuid_xlevel) {
2070 if (env->cpuid_xlevel2 > 0) {
2071 /* Handle the Centaur's CPUID instruction. */
2072 if (index > env->cpuid_xlevel2) {
2073 index = env->cpuid_xlevel2;
2074 } else if (index < 0xC0000000) {
2075 index = env->cpuid_xlevel;
2076 }
2077 } else {
57f26ae7
EH		 2078 /* Intel documentation states that invalid EAX input will
2079 * return the same information as EAX=cpuid_level
2080 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2081 */
2082 index = env->cpuid_level;
b3baa152
BW		 2083 }
2084 }
c6dc6f63
AP		 2085 } else {
2086 if (index > env->cpuid_level)
2087 index = env->cpuid_level;
2088 }
2089
2090 switch(index) {
2091 case 0:
2092 *eax = env->cpuid_level;
2093 get_cpuid_vendor(env, ebx, ecx, edx);
2094 break;
2095 case 1:
2096 *eax = env->cpuid_version;
2097 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2098 *ecx = env->features[FEAT_1_ECX];
2099 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2100 if (cs->nr_cores * cs->nr_threads > 1) {
2101 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2102 *edx |= 1 << 28; /* HTT bit */
2103 }
2104 break;
2105 case 2:
2106 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2107 if (cpu->cache_info_passthrough) {
2108 host_cpuid(index, 0, eax, ebx, ecx, edx);
2109 break;
2110 }
5e891bf8 2111 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2112 *ebx = 0;
2113 *ecx = 0;
5e891bf8
EH		 2114 *edx = (L1D_DESCRIPTOR << 16) | \
2115 (L1I_DESCRIPTOR << 8) | \
2116 (L2_DESCRIPTOR);
c6dc6f63
AP		 2117 break;
2118 case 4:
2119 /* cache info: needed for Core compatibility */
787aaf57
BC		 2120 if (cpu->cache_info_passthrough) {
2121 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2122 *eax &= ~0xFC000000;
c6dc6f63 2123 } else {
2f7a21c4 2124 *eax = 0;
76c2975a 2125 switch (count) {
c6dc6f63 2126 case 0: /* L1 dcache info */
5e891bf8
EH		 2127 *eax |= CPUID_4_TYPE_DCACHE | \
2128 CPUID_4_LEVEL(1) | \
2129 CPUID_4_SELF_INIT_LEVEL;
2130 *ebx = (L1D_LINE_SIZE - 1) | \
2131 ((L1D_PARTITIONS - 1) << 12) | \
2132 ((L1D_ASSOCIATIVITY - 1) << 22);
2133 *ecx = L1D_SETS - 1;
2134 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2135 break;
2136 case 1: /* L1 icache info */
5e891bf8
EH		 2137 *eax |= CPUID_4_TYPE_ICACHE | \
2138 CPUID_4_LEVEL(1) | \
2139 CPUID_4_SELF_INIT_LEVEL;
2140 *ebx = (L1I_LINE_SIZE - 1) | \
2141 ((L1I_PARTITIONS - 1) << 12) | \
2142 ((L1I_ASSOCIATIVITY - 1) << 22);
2143 *ecx = L1I_SETS - 1;
2144 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2145 break;
2146 case 2: /* L2 cache info */
5e891bf8
EH		 2147 *eax |= CPUID_4_TYPE_UNIFIED | \
2148 CPUID_4_LEVEL(2) | \
2149 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2150 if (cs->nr_threads > 1) {
2151 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2152 }
5e891bf8
EH		 2153 *ebx = (L2_LINE_SIZE - 1) | \
2154 ((L2_PARTITIONS - 1) << 12) | \
2155 ((L2_ASSOCIATIVITY - 1) << 22);
2156 *ecx = L2_SETS - 1;
2157 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2158 break;
2159 default: /* end of info */
2160 *eax = 0;
2161 *ebx = 0;
2162 *ecx = 0;
2163 *edx = 0;
2164 break;
76c2975a
PB		 2165 }
2166 }
2167
2168 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2169 if ((*eax & 31) && cs->nr_cores > 1) {
2170 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2171 }
2172 break;
2173 case 5:
2174 /* mwait info: needed for Core compatibility */
2175 *eax = 0; /* Smallest monitor-line size in bytes */
2176 *ebx = 0; /* Largest monitor-line size in bytes */
2177 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2178 *edx = 0;
2179 break;
2180 case 6:
2181 /* Thermal and Power Leaf */
2182 *eax = 0;
2183 *ebx = 0;
2184 *ecx = 0;
2185 *edx = 0;
2186 break;
f7911686 2187 case 7:
13526728
EH		 2188 /* Structured Extended Feature Flags Enumeration Leaf */
2189 if (count == 0) {
2190 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2191 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2192 *ecx = 0; /* Reserved */
2193 *edx = 0; /* Reserved */
f7911686
YW		 2194 } else {
2195 *eax = 0;
2196 *ebx = 0;
2197 *ecx = 0;
2198 *edx = 0;
2199 }
2200 break;
c6dc6f63
AP		 2201 case 9:
2202 /* Direct Cache Access Information Leaf */
2203 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2204 *ebx = 0;
2205 *ecx = 0;
2206 *edx = 0;
2207 break;
2208 case 0xA:
2209 /* Architectural Performance Monitoring Leaf */
9337e3b6 2210 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2211 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2212
2213 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2214 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2215 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2216 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2217 } else {
2218 *eax = 0;
2219 *ebx = 0;
2220 *ecx = 0;
2221 *edx = 0;
2222 }
c6dc6f63 2223 break;
2560f19f
PB		 2224 case 0xD: {
2225 KVMState *s = cs->kvm_state;
2226 uint64_t kvm_mask;
2227 int i;
2228
51e49430 2229 /* Processor Extended State */
2560f19f
PB		 2230 *eax = 0;
2231 *ebx = 0;
2232 *ecx = 0;
2233 *edx = 0;
2234 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2235 break;
2236 }
2560f19f
PB		 2237 kvm_mask =
2238 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2239 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2240
2560f19f
PB		 2241 if (count == 0) {
2242 *ecx = 0x240;
2243 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2244 const ExtSaveArea *esa = &ext_save_areas[i];
2245 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2246 (kvm_mask & (1 << i)) != 0) {
2247 if (i < 32) {
2248 *eax |= 1 << i;
2249 } else {
2250 *edx |= 1 << (i - 32);
2251 }
2252 *ecx = MAX(*ecx, esa->offset + esa->size);
2253 }
2254 }
2255 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2256 *ebx = *ecx;
2257 } else if (count == 1) {
2258 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2259 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2260 const ExtSaveArea *esa = &ext_save_areas[count];
2261 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2262 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2263 *eax = esa->size;
2264 *ebx = esa->offset;
2560f19f 2265 }
51e49430
SY		 2266 }
2267 break;
2560f19f 2268 }
c6dc6f63
AP		 2269 case 0x80000000:
2270 *eax = env->cpuid_xlevel;
2271 *ebx = env->cpuid_vendor1;
2272 *edx = env->cpuid_vendor2;
2273 *ecx = env->cpuid_vendor3;
2274 break;
2275 case 0x80000001:
2276 *eax = env->cpuid_version;
2277 *ebx = 0;
0514ef2f
EH		 2278 *ecx = env->features[FEAT_8000_0001_ECX];
2279 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2280
2281 /* The Linux kernel checks for the CMPLegacy bit and
2282 * discards multiple thread information if it is set.
2283 * So dont set it here for Intel to make Linux guests happy.
2284 */
ce3960eb 2285 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2286 uint32_t tebx, tecx, tedx;
2287 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2288 if (tebx != CPUID_VENDOR_INTEL_1 ||
2289 tedx != CPUID_VENDOR_INTEL_2 ||
2290 tecx != CPUID_VENDOR_INTEL_3) {
2291 *ecx |= 1 << 1; /* CmpLegacy bit */
2292 }
2293 }
c6dc6f63
AP		 2294 break;
2295 case 0x80000002:
2296 case 0x80000003:
2297 case 0x80000004:
2298 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2299 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2300 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2301 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2302 break;
2303 case 0x80000005:
2304 /* cache info (L1 cache) */
787aaf57
BC		 2305 if (cpu->cache_info_passthrough) {
2306 host_cpuid(index, 0, eax, ebx, ecx, edx);
2307 break;
2308 }
5e891bf8
EH		 2309 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2310 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2311 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2312 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2313 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2314 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2315 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2316 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2317 break;
2318 case 0x80000006:
2319 /* cache info (L2 cache) */
787aaf57
BC		 2320 if (cpu->cache_info_passthrough) {
2321 host_cpuid(index, 0, eax, ebx, ecx, edx);
2322 break;
2323 }
5e891bf8
EH		 2324 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2325 (L2_DTLB_2M_ENTRIES << 16) | \
2326 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2327 (L2_ITLB_2M_ENTRIES);
2328 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2329 (L2_DTLB_4K_ENTRIES << 16) | \
2330 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2331 (L2_ITLB_4K_ENTRIES);
2332 *ecx = (L2_SIZE_KB_AMD << 16) | \
2333 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2334 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2335 *edx = ((L3_SIZE_KB/512) << 18) | \
2336 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2337 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP		 2338 break;
2339 case 0x80000008:
2340 /* virtual & phys address size in low 2 bytes. */
2341/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2342 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2343 /* 64 bit processor */
2344/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2345 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2346 } else {
0514ef2f 2347 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2348 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2349 } else {
c6dc6f63 2350 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2351 }
c6dc6f63
AP		 2352 }
2353 *ebx = 0;
2354 *ecx = 0;
2355 *edx = 0;
ce3960eb
AF		 2356 if (cs->nr_cores * cs->nr_threads > 1) {
2357 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2358 }
2359 break;
2360 case 0x8000000A:
0514ef2f 2361 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2362 *eax = 0x00000001; /* SVM Revision */
2363 *ebx = 0x00000010; /* nr of ASIDs */
2364 *ecx = 0;
0514ef2f 2365 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2366 } else {
2367 *eax = 0;
2368 *ebx = 0;
2369 *ecx = 0;
2370 *edx = 0;
2371 }
c6dc6f63 2372 break;
b3baa152
BW		 2373 case 0xC0000000:
2374 *eax = env->cpuid_xlevel2;
2375 *ebx = 0;
2376 *ecx = 0;
2377 *edx = 0;
2378 break;
2379 case 0xC0000001:
2380 /* Support for VIA CPU's CPUID instruction */
2381 *eax = env->cpuid_version;
2382 *ebx = 0;
2383 *ecx = 0;
0514ef2f 2384 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2385 break;
2386 case 0xC0000002:
2387 case 0xC0000003:
2388 case 0xC0000004:
2389 /* Reserved for the future, and now filled with zero */
2390 *eax = 0;
2391 *ebx = 0;
2392 *ecx = 0;
2393 *edx = 0;
2394 break;
c6dc6f63
AP		 2395 default:
2396 /* reserved values: zero */
2397 *eax = 0;
2398 *ebx = 0;
2399 *ecx = 0;
2400 *edx = 0;
2401 break;
2402 }
2403}
5fd2087a
AF		 2404
2405/* CPUClass::reset() */
2406static void x86_cpu_reset(CPUState *s)
2407{
2408 X86CPU *cpu = X86_CPU(s);
2409 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2410 CPUX86State *env = &cpu->env;
c1958aea
AF		 2411 int i;
2412
5fd2087a
AF		 2413 xcc->parent_reset(s);
2414
43175fa9 2415 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2416
00c8cb0a 2417 tlb_flush(s, 1);
c1958aea
AF		 2418
2419 env->old_exception = -1;
2420
2421 /* init to reset state */
2422
2423#ifdef CONFIG_SOFTMMU
2424 env->hflags |= HF_SOFTMMU_MASK;
2425#endif
2426 env->hflags2 |= HF2_GIF_MASK;
2427
2428 cpu_x86_update_cr0(env, 0x60000010);
2429 env->a20_mask = ~0x0;
2430 env->smbase = 0x30000;
2431
2432 env->idt.limit = 0xffff;
2433 env->gdt.limit = 0xffff;
2434 env->ldt.limit = 0xffff;
2435 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2436 env->tr.limit = 0xffff;
2437 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2438
2439 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2440 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2441 DESC_R_MASK | DESC_A_MASK);
2442 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2443 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2444 DESC_A_MASK);
2445 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2446 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2447 DESC_A_MASK);
2448 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2449 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2450 DESC_A_MASK);
2451 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2452 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2453 DESC_A_MASK);
2454 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2455 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2456 DESC_A_MASK);
2457
2458 env->eip = 0xfff0;
2459 env->regs[R_EDX] = env->cpuid_version;
2460
2461 env->eflags = 0x2;
2462
2463 /* FPU init */
2464 for (i = 0; i < 8; i++) {
2465 env->fptags[i] = 1;
2466 }
2467 env->fpuc = 0x37f;
2468
2469 env->mxcsr = 0x1f80;
c74f41bb 2470 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2471
2472 env->pat = 0x0007040600070406ULL;
2473 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2474
2475 memset(env->dr, 0, sizeof(env->dr));
2476 env->dr[6] = DR6_FIXED_1;
2477 env->dr[7] = DR7_FIXED_1;
b3310ab3 2478 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2479 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2480
05e7e819 2481 env->xcr0 = 1;
0522604b 2482
dd673288
IM		 2483#if !defined(CONFIG_USER_ONLY)
2484 /* We hard-wire the BSP to the first CPU. */
55e5c285 2485 if (s->cpu_index == 0) {
02e51483 2486 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2487 }
2488
259186a7 2489 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2490
2491 if (kvm_enabled()) {
2492 kvm_arch_reset_vcpu(cpu);
2493 }
dd673288 2494#endif
5fd2087a
AF		 2495}
2496
dd673288
IM		 2497#ifndef CONFIG_USER_ONLY
2498bool cpu_is_bsp(X86CPU *cpu)
2499{
02e51483 2500 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2501}
65dee380
IM		 2502
2503/* TODO: remove me, when reset over QOM tree is implemented */
2504static void x86_cpu_machine_reset_cb(void *opaque)
2505{
2506 X86CPU *cpu = opaque;
2507 cpu_reset(CPU(cpu));
2508}
dd673288
IM		 2509#endif
2510
de024815
AF		 2511static void mce_init(X86CPU *cpu)
2512{
2513 CPUX86State *cenv = &cpu->env;
2514 unsigned int bank;
2515
2516 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2517 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2518 (CPUID_MCE | CPUID_MCA)) {
2519 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2520 cenv->mcg_ctl = ~(uint64_t)0;
2521 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2522 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2523 }
2524 }
2525}
2526
bdeec802 2527#ifndef CONFIG_USER_ONLY
d3c64d6a 2528static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2529{
bdeec802 2530 CPUX86State *env = &cpu->env;
53a89e26 2531 DeviceState *dev = DEVICE(cpu);
449994eb 2532 APICCommonState *apic;
bdeec802
IM		 2533 const char *apic_type = "apic";
2534
2535 if (kvm_irqchip_in_kernel()) {
2536 apic_type = "kvm-apic";
2537 } else if (xen_enabled()) {
2538 apic_type = "xen-apic";
2539 }
2540
02e51483
CF		 2541 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2542 if (cpu->apic_state == NULL) {
bdeec802
IM		 2543 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2544 return;
2545 }
2546
2547 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2548 OBJECT(cpu->apic_state), NULL);
2549 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2550 /* TODO: convert to link<> */
02e51483 2551 apic = APIC_COMMON(cpu->apic_state);
60671e58 2552 apic->cpu = cpu;
d3c64d6a
IM		 2553}
2554
2555static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2556{
02e51483 2557 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2558 return;
2559 }
bdeec802 2560
02e51483 2561 if (qdev_init(cpu->apic_state)) {
bdeec802 2562 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2563 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2564 return;
2565 }
bdeec802 2566}
d3c64d6a
IM		 2567#else
2568static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2569{
2570}
bdeec802
IM		 2571#endif
2572
2b6f294c 2573static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2574{
14a10fc3 2575 CPUState *cs = CPU(dev);
2b6f294c
AF		 2576 X86CPU *cpu = X86_CPU(dev);
2577 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2578 CPUX86State *env = &cpu->env;
2b6f294c 2579 Error *local_err = NULL;
b34d12d1 2580
0514ef2f 2581 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2582 env->cpuid_level = 7;
2583 }
7a059953 2584
9b15cd9e
IM		 2585 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2586 * CPUID[1].EDX.
2587 */
2588 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2589 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2590 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2591 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2592 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2593 & CPUID_EXT2_AMD_ALIASES);
2594 }
2595
4586f157 2596 if (!kvm_enabled()) {
0514ef2f
EH		 2597 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2598 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2599 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
4586f157
IM		 2600#ifdef TARGET_X86_64
2601 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2602#endif
2603 );
0514ef2f
EH		 2604 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2605 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
4586f157 2606 } else {
f0b9b111 2607 KVMState *s = kvm_state;
912ffc47 2608 if ((cpu->check_cpuid || cpu->enforce_cpuid)
f0b9b111 2609 && kvm_check_features_against_host(s, cpu) && cpu->enforce_cpuid) {
4dc1f449
IM		 2610 error_setg(&local_err,
2611 "Host's CPU doesn't support requested features");
2612 goto out;
5ec01c2e 2613 }
a509d632 2614 filter_features_for_kvm(cpu);
4586f157
IM		 2615 }
2616
65dee380
IM		 2617#ifndef CONFIG_USER_ONLY
2618 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2619
0514ef2f 2620 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2621 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2622 if (local_err != NULL) {
4dc1f449 2623 goto out;
bdeec802
IM		 2624 }
2625 }
65dee380
IM		 2626#endif
2627
7a059953 2628 mce_init(cpu);
14a10fc3 2629 qemu_init_vcpu(cs);
d3c64d6a
IM		 2630
2631 x86_cpu_apic_realize(cpu, &local_err);
2632 if (local_err != NULL) {
2633 goto out;
2634 }
14a10fc3 2635 cpu_reset(cs);
2b6f294c 2636
4dc1f449
IM		 2637 xcc->parent_realize(dev, &local_err);
2638out:
2639 if (local_err != NULL) {
2640 error_propagate(errp, local_err);
2641 return;
2642 }
7a059953
AF		 2643}
2644
8932cfdf
EH		 2645/* Enables contiguous-apic-ID mode, for compatibility */
2646static bool compat_apic_id_mode;
2647
2648void enable_compat_apic_id_mode(void)
2649{
2650 compat_apic_id_mode = true;
2651}
2652
cb41bad3
EH		 2653/* Calculates initial APIC ID for a specific CPU index
2654 *
2655 * Currently we need to be able to calculate the APIC ID from the CPU index
2656 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2657 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2658 * all CPUs up to max_cpus.
2659 */
2660uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2661{
8932cfdf
EH		 2662 uint32_t correct_id;
2663 static bool warned;
2664
2665 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2666 if (compat_apic_id_mode) {
2667 if (cpu_index != correct_id && !warned) {
2668 error_report("APIC IDs set in compatibility mode, "
2669 "CPU topology won't match the configuration");
2670 warned = true;
2671 }
2672 return cpu_index;
2673 } else {
2674 return correct_id;
2675 }
cb41bad3
EH		 2676}
2677
de024815
AF		 2678static void x86_cpu_initfn(Object *obj)
2679{
55e5c285 2680 CPUState *cs = CPU(obj);
de024815 2681 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2682 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2683 CPUX86State *env = &cpu->env;
d65e9815 2684 static int inited;
de024815 2685
c05efcb1 2686 cs->env_ptr = env;
de024815 2687 cpu_exec_init(env);
71ad61d3
AF		 2688
2689 object_property_add(obj, "family", "int",
95b8519d 2690 x86_cpuid_version_get_family,
71ad61d3 2691 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2692 object_property_add(obj, "model", "int",
67e30c83 2693 x86_cpuid_version_get_model,
c5291a4f 2694 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2695 object_property_add(obj, "stepping", "int",
35112e41 2696 x86_cpuid_version_get_stepping,
036e2222 2697 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2698 object_property_add(obj, "level", "int",
2699 x86_cpuid_get_level,
2700 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2701 object_property_add(obj, "xlevel", "int",
2702 x86_cpuid_get_xlevel,
2703 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2704 object_property_add_str(obj, "vendor",
2705 x86_cpuid_get_vendor,
2706 x86_cpuid_set_vendor, NULL);
938d4c25 2707 object_property_add_str(obj, "model-id",
63e886eb 2708 x86_cpuid_get_model_id,
938d4c25 2709 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2710 object_property_add(obj, "tsc-frequency", "int",
2711 x86_cpuid_get_tsc_freq,
2712 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2713 object_property_add(obj, "apic-id", "int",
2714 x86_cpuid_get_apic_id,
2715 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2716 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2717 x86_cpu_get_feature_words,
7e5292b5
EH		 2718 NULL, NULL, (void *)env->features, NULL);
2719 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2720 x86_cpu_get_feature_words,
2721 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2722
92067bf4 2723 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2724 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815 2725
d940ee9b
EH		 2726 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2727
d65e9815
IM		 2728 /* init various static tables used in TCG mode */
2729 if (tcg_enabled() && !inited) {
2730 inited = 1;
2731 optimize_flags_init();
2732#ifndef CONFIG_USER_ONLY
2733 cpu_set_debug_excp_handler(breakpoint_handler);
2734#endif
2735 }
de024815
AF		 2736}
2737
997395d3
IM		 2738static int64_t x86_cpu_get_arch_id(CPUState *cs)
2739{
2740 X86CPU *cpu = X86_CPU(cs);
2741 CPUX86State *env = &cpu->env;
2742
2743 return env->cpuid_apic_id;
2744}
2745
444d5590
AF		 2746static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2747{
2748 X86CPU *cpu = X86_CPU(cs);
2749
2750 return cpu->env.cr[0] & CR0_PG_MASK;
2751}
2752
f45748f1
AF		 2753static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2754{
2755 X86CPU *cpu = X86_CPU(cs);
2756
2757 cpu->env.eip = value;
2758}
2759
bdf7ae5b
AF		 2760static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2761{
2762 X86CPU *cpu = X86_CPU(cs);
2763
2764 cpu->env.eip = tb->pc - tb->cs_base;
2765}
2766
8c2e1b00
AF		 2767static bool x86_cpu_has_work(CPUState *cs)
2768{
2769 X86CPU *cpu = X86_CPU(cs);
2770 CPUX86State *env = &cpu->env;
2771
2772 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2773 CPU_INTERRUPT_POLL)) &&
2774 (env->eflags & IF_MASK)) ||
2775 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2776 CPU_INTERRUPT_INIT |
2777 CPU_INTERRUPT_SIPI |
2778 CPU_INTERRUPT_MCE));
2779}
2780
9337e3b6
EH		 2781static Property x86_cpu_properties[] = {
2782 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2783 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2784 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2785 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2786 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2787 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2788 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 2789 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
9337e3b6
EH		 2790 DEFINE_PROP_END_OF_LIST()
2791};
2792
5fd2087a
AF		 2793static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2794{
2795 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2796 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2797 DeviceClass *dc = DEVICE_CLASS(oc);
2798
2799 xcc->parent_realize = dc->realize;
2800 dc->realize = x86_cpu_realizefn;
62fc403f 2801 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2802 dc->props = x86_cpu_properties;
5fd2087a
AF		 2803
2804 xcc->parent_reset = cc->reset;
2805 cc->reset = x86_cpu_reset;
91b1df8c 2806 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2807
500050d1 2808 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 2809 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 2810 cc->has_work = x86_cpu_has_work;
97a8ea5a 2811 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2812 cc->dump_state = x86_cpu_dump_state;
f45748f1 2813 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2814 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2815 cc->gdb_read_register = x86_cpu_gdb_read_register;
2816 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2817 cc->get_arch_id = x86_cpu_get_arch_id;
2818 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 2819#ifdef CONFIG_USER_ONLY
2820 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2821#else
a23bbfda 2822 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2823 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2824 cc->write_elf64_note = x86_cpu_write_elf64_note;
2825 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2826 cc->write_elf32_note = x86_cpu_write_elf32_note;
2827 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2828 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2829#endif
a0e372f0 2830 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2831}
2832
2833static const TypeInfo x86_cpu_type_info = {
2834 .name = TYPE_X86_CPU,
2835 .parent = TYPE_CPU,
2836 .instance_size = sizeof(X86CPU),
de024815 2837 .instance_init = x86_cpu_initfn,
d940ee9b 2838 .abstract = true,
5fd2087a
AF		 2839 .class_size = sizeof(X86CPUClass),
2840 .class_init = x86_cpu_common_class_init,
2841};
2842
2843static void x86_cpu_register_types(void)
2844{
d940ee9b
EH		 2845 int i;
2846
5fd2087a 2847 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 2848 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2849 x86_register_cpudef_type(&builtin_x86_defs[i]);
2850 }
2851#ifdef CONFIG_KVM
2852 type_register_static(&host_x86_cpu_type_info);
2853#endif
5fd2087a
AF		 2854}
2855
2856type_init(x86_cpu_register_types)
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